rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

prompt stringlengths 162 4.26M	response stringlengths 109 5.16M
Generate the Verilog code corresponding to this FIRRTL code module BoomIOMSHR : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, mem_access : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip mem_ack : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}, clock reg grant_word : UInt<64>, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T wire size : UInt<2> connect size, req.uop.mem_size node a_data = cat(req.data, req.data) node _get_legal_T = leq(UInt<1>(0h0), req.uop.mem_size) node _get_legal_T_1 = leq(req.uop.mem_size, UInt<4>(0hc)) node _get_legal_T_2 = and(_get_legal_T, _get_legal_T_1) node _get_legal_T_3 = or(UInt<1>(0h0), _get_legal_T_2) node _get_legal_T_4 = xor(req.addr, UInt<14>(0h3000)) node _get_legal_T_5 = cvt(_get_legal_T_4) node _get_legal_T_6 = and(_get_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _get_legal_T_7 = asSInt(_get_legal_T_6) node _get_legal_T_8 = eq(_get_legal_T_7, asSInt(UInt<1>(0h0))) node _get_legal_T_9 = and(_get_legal_T_3, _get_legal_T_8) node _get_legal_T_10 = leq(UInt<1>(0h0), req.uop.mem_size) node _get_legal_T_11 = leq(req.uop.mem_size, UInt<3>(0h6)) node _get_legal_T_12 = and(_get_legal_T_10, _get_legal_T_11) node _get_legal_T_13 = or(UInt<1>(0h0), _get_legal_T_12) node _get_legal_T_14 = xor(req.addr, UInt<1>(0h0)) node _get_legal_T_15 = cvt(_get_legal_T_14) node _get_legal_T_16 = and(_get_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _get_legal_T_17 = asSInt(_get_legal_T_16) node _get_legal_T_18 = eq(_get_legal_T_17, asSInt(UInt<1>(0h0))) node _get_legal_T_19 = xor(req.addr, UInt<17>(0h10000)) node _get_legal_T_20 = cvt(_get_legal_T_19) node _get_legal_T_21 = and(_get_legal_T_20, asSInt(UInt<33>(0h98013000))) node _get_legal_T_22 = asSInt(_get_legal_T_21) node _get_legal_T_23 = eq(_get_legal_T_22, asSInt(UInt<1>(0h0))) node _get_legal_T_24 = xor(req.addr, UInt<17>(0h10000)) node _get_legal_T_25 = cvt(_get_legal_T_24) node _get_legal_T_26 = and(_get_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _get_legal_T_27 = asSInt(_get_legal_T_26) node _get_legal_T_28 = eq(_get_legal_T_27, asSInt(UInt<1>(0h0))) node _get_legal_T_29 = xor(req.addr, UInt<26>(0h2000000)) node _get_legal_T_30 = cvt(_get_legal_T_29) node _get_legal_T_31 = and(_get_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _get_legal_T_32 = asSInt(_get_legal_T_31) node _get_legal_T_33 = eq(_get_legal_T_32, asSInt(UInt<1>(0h0))) node _get_legal_T_34 = xor(req.addr, UInt<28>(0h8000000)) node _get_legal_T_35 = cvt(_get_legal_T_34) node _get_legal_T_36 = and(_get_legal_T_35, asSInt(UInt<33>(0h98000000))) node _get_legal_T_37 = asSInt(_get_legal_T_36) node _get_legal_T_38 = eq(_get_legal_T_37, asSInt(UInt<1>(0h0))) node _get_legal_T_39 = xor(req.addr, UInt<28>(0h8000000)) node _get_legal_T_40 = cvt(_get_legal_T_39) node _get_legal_T_41 = and(_get_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _get_legal_T_42 = asSInt(_get_legal_T_41) node _get_legal_T_43 = eq(_get_legal_T_42, asSInt(UInt<1>(0h0))) node _get_legal_T_44 = xor(req.addr, UInt<29>(0h10000000)) node _get_legal_T_45 = cvt(_get_legal_T_44) node _get_legal_T_46 = and(_get_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _get_legal_T_47 = asSInt(_get_legal_T_46) node _get_legal_T_48 = eq(_get_legal_T_47, asSInt(UInt<1>(0h0))) node _get_legal_T_49 = xor(req.addr, UInt<32>(0h80000000)) node _get_legal_T_50 = cvt(_get_legal_T_49) node _get_legal_T_51 = and(_get_legal_T_50, asSInt(UInt<33>(0h90000000))) node _get_legal_T_52 = asSInt(_get_legal_T_51) node _get_legal_T_53 = eq(_get_legal_T_52, asSInt(UInt<1>(0h0))) node _get_legal_T_54 = or(_get_legal_T_18, _get_legal_T_23) node _get_legal_T_55 = or(_get_legal_T_54, _get_legal_T_28) node _get_legal_T_56 = or(_get_legal_T_55, _get_legal_T_33) node _get_legal_T_57 = or(_get_legal_T_56, _get_legal_T_38) node _get_legal_T_58 = or(_get_legal_T_57, _get_legal_T_43) node _get_legal_T_59 = or(_get_legal_T_58, _get_legal_T_48) node _get_legal_T_60 = or(_get_legal_T_59, _get_legal_T_53) node _get_legal_T_61 = and(_get_legal_T_13, _get_legal_T_60) node _get_legal_T_62 = or(UInt<1>(0h0), _get_legal_T_9) node get_legal = or(_get_legal_T_62, _get_legal_T_61) wire get : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect get.opcode, UInt<3>(0h4) connect get.param, UInt<1>(0h0) connect get.size, req.uop.mem_size connect get.source, UInt<3>(0h5) connect get.address, req.addr node _get_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<4>(0h0)) node get_a_mask_sizeOH_shiftAmount = bits(_get_a_mask_sizeOH_T, 1, 0) node _get_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_a_mask_sizeOH_shiftAmount) node _get_a_mask_sizeOH_T_2 = bits(_get_a_mask_sizeOH_T_1, 3, 0) node get_a_mask_sizeOH = or(_get_a_mask_sizeOH_T_2, UInt<1>(0h1)) node get_a_mask_sub_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<3>(0h4)) node get_a_mask_sub_sub_sub_size = bits(get_a_mask_sizeOH, 3, 3) node get_a_mask_sub_sub_sub_bit = bits(req.addr, 3, 3) node get_a_mask_sub_sub_sub_nbit = eq(get_a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node get_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_sub_nbit) node _get_a_mask_sub_sub_sub_acc_T = and(get_a_mask_sub_sub_sub_size, get_a_mask_sub_sub_sub_0_2) node get_a_mask_sub_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_sub_0_1, _get_a_mask_sub_sub_sub_acc_T) node get_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_sub_bit) node _get_a_mask_sub_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_sub_size, get_a_mask_sub_sub_sub_1_2) node get_a_mask_sub_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_sub_0_1, _get_a_mask_sub_sub_sub_acc_T_1) node get_a_mask_sub_sub_size = bits(get_a_mask_sizeOH, 2, 2) node get_a_mask_sub_sub_bit = bits(req.addr, 2, 2) node get_a_mask_sub_sub_nbit = eq(get_a_mask_sub_sub_bit, UInt<1>(0h0)) node get_a_mask_sub_sub_0_2 = and(get_a_mask_sub_sub_sub_0_2, get_a_mask_sub_sub_nbit) node _get_a_mask_sub_sub_acc_T = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_0_2) node get_a_mask_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T) node get_a_mask_sub_sub_1_2 = and(get_a_mask_sub_sub_sub_0_2, get_a_mask_sub_sub_bit) node _get_a_mask_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_1_2) node get_a_mask_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T_1) node get_a_mask_sub_sub_2_2 = and(get_a_mask_sub_sub_sub_1_2, get_a_mask_sub_sub_nbit) node _get_a_mask_sub_sub_acc_T_2 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_2_2) node get_a_mask_sub_sub_2_1 = or(get_a_mask_sub_sub_sub_1_1, _get_a_mask_sub_sub_acc_T_2) node get_a_mask_sub_sub_3_2 = and(get_a_mask_sub_sub_sub_1_2, get_a_mask_sub_sub_bit) node _get_a_mask_sub_sub_acc_T_3 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_3_2) node get_a_mask_sub_sub_3_1 = or(get_a_mask_sub_sub_sub_1_1, _get_a_mask_sub_sub_acc_T_3) node get_a_mask_sub_size = bits(get_a_mask_sizeOH, 1, 1) node get_a_mask_sub_bit = bits(req.addr, 1, 1) node get_a_mask_sub_nbit = eq(get_a_mask_sub_bit, UInt<1>(0h0)) node get_a_mask_sub_0_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T = and(get_a_mask_sub_size, get_a_mask_sub_0_2) node get_a_mask_sub_0_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T) node get_a_mask_sub_1_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_bit) node _get_a_mask_sub_acc_T_1 = and(get_a_mask_sub_size, get_a_mask_sub_1_2) node get_a_mask_sub_1_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T_1) node get_a_mask_sub_2_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T_2 = and(get_a_mask_sub_size, get_a_mask_sub_2_2) node get_a_mask_sub_2_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_2) node get_a_mask_sub_3_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_bit) node _get_a_mask_sub_acc_T_3 = and(get_a_mask_sub_size, get_a_mask_sub_3_2) node get_a_mask_sub_3_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_3) node get_a_mask_sub_4_2 = and(get_a_mask_sub_sub_2_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T_4 = and(get_a_mask_sub_size, get_a_mask_sub_4_2) node get_a_mask_sub_4_1 = or(get_a_mask_sub_sub_2_1, _get_a_mask_sub_acc_T_4) node get_a_mask_sub_5_2 = and(get_a_mask_sub_sub_2_2, get_a_mask_sub_bit) node _get_a_mask_sub_acc_T_5 = and(get_a_mask_sub_size, get_a_mask_sub_5_2) node get_a_mask_sub_5_1 = or(get_a_mask_sub_sub_2_1, _get_a_mask_sub_acc_T_5) node get_a_mask_sub_6_2 = and(get_a_mask_sub_sub_3_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T_6 = and(get_a_mask_sub_size, get_a_mask_sub_6_2) node get_a_mask_sub_6_1 = or(get_a_mask_sub_sub_3_1, _get_a_mask_sub_acc_T_6) node get_a_mask_sub_7_2 = and(get_a_mask_sub_sub_3_2, get_a_mask_sub_bit) node _get_a_mask_sub_acc_T_7 = and(get_a_mask_sub_size, get_a_mask_sub_7_2) node get_a_mask_sub_7_1 = or(get_a_mask_sub_sub_3_1, _get_a_mask_sub_acc_T_7) node get_a_mask_size = bits(get_a_mask_sizeOH, 0, 0) node get_a_mask_bit = bits(req.addr, 0, 0) node get_a_mask_nbit = eq(get_a_mask_bit, UInt<1>(0h0)) node get_a_mask_eq = and(get_a_mask_sub_0_2, get_a_mask_nbit) node _get_a_mask_acc_T = and(get_a_mask_size, get_a_mask_eq) node get_a_mask_acc = or(get_a_mask_sub_0_1, _get_a_mask_acc_T) node get_a_mask_eq_1 = and(get_a_mask_sub_0_2, get_a_mask_bit) node _get_a_mask_acc_T_1 = and(get_a_mask_size, get_a_mask_eq_1) node get_a_mask_acc_1 = or(get_a_mask_sub_0_1, _get_a_mask_acc_T_1) node get_a_mask_eq_2 = and(get_a_mask_sub_1_2, get_a_mask_nbit) node _get_a_mask_acc_T_2 = and(get_a_mask_size, get_a_mask_eq_2) node get_a_mask_acc_2 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_2) node get_a_mask_eq_3 = and(get_a_mask_sub_1_2, get_a_mask_bit) node _get_a_mask_acc_T_3 = and(get_a_mask_size, get_a_mask_eq_3) node get_a_mask_acc_3 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_3) node get_a_mask_eq_4 = and(get_a_mask_sub_2_2, get_a_mask_nbit) node _get_a_mask_acc_T_4 = and(get_a_mask_size, get_a_mask_eq_4) node get_a_mask_acc_4 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_4) node get_a_mask_eq_5 = and(get_a_mask_sub_2_2, get_a_mask_bit) node _get_a_mask_acc_T_5 = and(get_a_mask_size, get_a_mask_eq_5) node get_a_mask_acc_5 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_5) node get_a_mask_eq_6 = and(get_a_mask_sub_3_2, get_a_mask_nbit) node _get_a_mask_acc_T_6 = and(get_a_mask_size, get_a_mask_eq_6) node get_a_mask_acc_6 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_6) node get_a_mask_eq_7 = and(get_a_mask_sub_3_2, get_a_mask_bit) node _get_a_mask_acc_T_7 = and(get_a_mask_size, get_a_mask_eq_7) node get_a_mask_acc_7 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_7) node get_a_mask_eq_8 = and(get_a_mask_sub_4_2, get_a_mask_nbit) node _get_a_mask_acc_T_8 = and(get_a_mask_size, get_a_mask_eq_8) node get_a_mask_acc_8 = or(get_a_mask_sub_4_1, _get_a_mask_acc_T_8) node get_a_mask_eq_9 = and(get_a_mask_sub_4_2, get_a_mask_bit) node _get_a_mask_acc_T_9 = and(get_a_mask_size, get_a_mask_eq_9) node get_a_mask_acc_9 = or(get_a_mask_sub_4_1, _get_a_mask_acc_T_9) node get_a_mask_eq_10 = and(get_a_mask_sub_5_2, get_a_mask_nbit) node _get_a_mask_acc_T_10 = and(get_a_mask_size, get_a_mask_eq_10) node get_a_mask_acc_10 = or(get_a_mask_sub_5_1, _get_a_mask_acc_T_10) node get_a_mask_eq_11 = and(get_a_mask_sub_5_2, get_a_mask_bit) node _get_a_mask_acc_T_11 = and(get_a_mask_size, get_a_mask_eq_11) node get_a_mask_acc_11 = or(get_a_mask_sub_5_1, _get_a_mask_acc_T_11) node get_a_mask_eq_12 = and(get_a_mask_sub_6_2, get_a_mask_nbit) node _get_a_mask_acc_T_12 = and(get_a_mask_size, get_a_mask_eq_12) node get_a_mask_acc_12 = or(get_a_mask_sub_6_1, _get_a_mask_acc_T_12) node get_a_mask_eq_13 = and(get_a_mask_sub_6_2, get_a_mask_bit) node _get_a_mask_acc_T_13 = and(get_a_mask_size, get_a_mask_eq_13) node get_a_mask_acc_13 = or(get_a_mask_sub_6_1, _get_a_mask_acc_T_13) node get_a_mask_eq_14 = and(get_a_mask_sub_7_2, get_a_mask_nbit) node _get_a_mask_acc_T_14 = and(get_a_mask_size, get_a_mask_eq_14) node get_a_mask_acc_14 = or(get_a_mask_sub_7_1, _get_a_mask_acc_T_14) node get_a_mask_eq_15 = and(get_a_mask_sub_7_2, get_a_mask_bit) node _get_a_mask_acc_T_15 = and(get_a_mask_size, get_a_mask_eq_15) node get_a_mask_acc_15 = or(get_a_mask_sub_7_1, _get_a_mask_acc_T_15) node get_a_mask_lo_lo_lo = cat(get_a_mask_acc_1, get_a_mask_acc) node get_a_mask_lo_lo_hi = cat(get_a_mask_acc_3, get_a_mask_acc_2) node get_a_mask_lo_lo = cat(get_a_mask_lo_lo_hi, get_a_mask_lo_lo_lo) node get_a_mask_lo_hi_lo = cat(get_a_mask_acc_5, get_a_mask_acc_4) node get_a_mask_lo_hi_hi = cat(get_a_mask_acc_7, get_a_mask_acc_6) node get_a_mask_lo_hi = cat(get_a_mask_lo_hi_hi, get_a_mask_lo_hi_lo) node get_a_mask_lo = cat(get_a_mask_lo_hi, get_a_mask_lo_lo) node get_a_mask_hi_lo_lo = cat(get_a_mask_acc_9, get_a_mask_acc_8) node get_a_mask_hi_lo_hi = cat(get_a_mask_acc_11, get_a_mask_acc_10) node get_a_mask_hi_lo = cat(get_a_mask_hi_lo_hi, get_a_mask_hi_lo_lo) node get_a_mask_hi_hi_lo = cat(get_a_mask_acc_13, get_a_mask_acc_12) node get_a_mask_hi_hi_hi = cat(get_a_mask_acc_15, get_a_mask_acc_14) node get_a_mask_hi_hi = cat(get_a_mask_hi_hi_hi, get_a_mask_hi_hi_lo) node get_a_mask_hi = cat(get_a_mask_hi_hi, get_a_mask_hi_lo) node _get_a_mask_T = cat(get_a_mask_hi, get_a_mask_lo) connect get.mask, _get_a_mask_T invalidate get.data connect get.corrupt, UInt<1>(0h0) node _put_legal_T = leq(UInt<1>(0h0), req.uop.mem_size) node _put_legal_T_1 = leq(req.uop.mem_size, UInt<4>(0hc)) node _put_legal_T_2 = and(_put_legal_T, _put_legal_T_1) node _put_legal_T_3 = or(UInt<1>(0h0), _put_legal_T_2) node _put_legal_T_4 = xor(req.addr, UInt<14>(0h3000)) node _put_legal_T_5 = cvt(_put_legal_T_4) node _put_legal_T_6 = and(_put_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _put_legal_T_7 = asSInt(_put_legal_T_6) node _put_legal_T_8 = eq(_put_legal_T_7, asSInt(UInt<1>(0h0))) node _put_legal_T_9 = and(_put_legal_T_3, _put_legal_T_8) node _put_legal_T_10 = leq(UInt<1>(0h0), req.uop.mem_size) node _put_legal_T_11 = leq(req.uop.mem_size, UInt<3>(0h6)) node _put_legal_T_12 = and(_put_legal_T_10, _put_legal_T_11) node _put_legal_T_13 = or(UInt<1>(0h0), _put_legal_T_12) node _put_legal_T_14 = xor(req.addr, UInt<1>(0h0)) node _put_legal_T_15 = cvt(_put_legal_T_14) node _put_legal_T_16 = and(_put_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _put_legal_T_17 = asSInt(_put_legal_T_16) node _put_legal_T_18 = eq(_put_legal_T_17, asSInt(UInt<1>(0h0))) node _put_legal_T_19 = xor(req.addr, UInt<21>(0h100000)) node _put_legal_T_20 = cvt(_put_legal_T_19) node _put_legal_T_21 = and(_put_legal_T_20, asSInt(UInt<33>(0h9a103000))) node _put_legal_T_22 = asSInt(_put_legal_T_21) node _put_legal_T_23 = eq(_put_legal_T_22, asSInt(UInt<1>(0h0))) node _put_legal_T_24 = xor(req.addr, UInt<26>(0h2000000)) node _put_legal_T_25 = cvt(_put_legal_T_24) node _put_legal_T_26 = and(_put_legal_T_25, asSInt(UInt<33>(0h9a110000))) node _put_legal_T_27 = asSInt(_put_legal_T_26) node _put_legal_T_28 = eq(_put_legal_T_27, asSInt(UInt<1>(0h0))) node _put_legal_T_29 = xor(req.addr, UInt<26>(0h2010000)) node _put_legal_T_30 = cvt(_put_legal_T_29) node _put_legal_T_31 = and(_put_legal_T_30, asSInt(UInt<33>(0h9a113000))) node _put_legal_T_32 = asSInt(_put_legal_T_31) node _put_legal_T_33 = eq(_put_legal_T_32, asSInt(UInt<1>(0h0))) node _put_legal_T_34 = xor(req.addr, UInt<28>(0h8000000)) node _put_legal_T_35 = cvt(_put_legal_T_34) node _put_legal_T_36 = and(_put_legal_T_35, asSInt(UInt<33>(0h98000000))) node _put_legal_T_37 = asSInt(_put_legal_T_36) node _put_legal_T_38 = eq(_put_legal_T_37, asSInt(UInt<1>(0h0))) node _put_legal_T_39 = xor(req.addr, UInt<28>(0h8000000)) node _put_legal_T_40 = cvt(_put_legal_T_39) node _put_legal_T_41 = and(_put_legal_T_40, asSInt(UInt<33>(0h9a110000))) node _put_legal_T_42 = asSInt(_put_legal_T_41) node _put_legal_T_43 = eq(_put_legal_T_42, asSInt(UInt<1>(0h0))) node _put_legal_T_44 = xor(req.addr, UInt<29>(0h10000000)) node _put_legal_T_45 = cvt(_put_legal_T_44) node _put_legal_T_46 = and(_put_legal_T_45, asSInt(UInt<33>(0h9a113000))) node _put_legal_T_47 = asSInt(_put_legal_T_46) node _put_legal_T_48 = eq(_put_legal_T_47, asSInt(UInt<1>(0h0))) node _put_legal_T_49 = xor(req.addr, UInt<32>(0h80000000)) node _put_legal_T_50 = cvt(_put_legal_T_49) node _put_legal_T_51 = and(_put_legal_T_50, asSInt(UInt<33>(0h90000000))) node _put_legal_T_52 = asSInt(_put_legal_T_51) node _put_legal_T_53 = eq(_put_legal_T_52, asSInt(UInt<1>(0h0))) node _put_legal_T_54 = or(_put_legal_T_18, _put_legal_T_23) node _put_legal_T_55 = or(_put_legal_T_54, _put_legal_T_28) node _put_legal_T_56 = or(_put_legal_T_55, _put_legal_T_33) node _put_legal_T_57 = or(_put_legal_T_56, _put_legal_T_38) node _put_legal_T_58 = or(_put_legal_T_57, _put_legal_T_43) node _put_legal_T_59 = or(_put_legal_T_58, _put_legal_T_48) node _put_legal_T_60 = or(_put_legal_T_59, _put_legal_T_53) node _put_legal_T_61 = and(_put_legal_T_13, _put_legal_T_60) node _put_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) node _put_legal_T_63 = xor(req.addr, UInt<17>(0h10000)) node _put_legal_T_64 = cvt(_put_legal_T_63) node _put_legal_T_65 = and(_put_legal_T_64, asSInt(UInt<33>(0h9a110000))) node _put_legal_T_66 = asSInt(_put_legal_T_65) node _put_legal_T_67 = eq(_put_legal_T_66, asSInt(UInt<1>(0h0))) node _put_legal_T_68 = and(_put_legal_T_62, _put_legal_T_67) node _put_legal_T_69 = or(UInt<1>(0h0), _put_legal_T_9) node _put_legal_T_70 = or(_put_legal_T_69, _put_legal_T_61) node put_legal = or(_put_legal_T_70, _put_legal_T_68) wire put : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect put.opcode, UInt<1>(0h0) connect put.param, UInt<1>(0h0) connect put.size, req.uop.mem_size connect put.source, UInt<3>(0h5) connect put.address, req.addr node _put_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<4>(0h0)) node put_a_mask_sizeOH_shiftAmount = bits(_put_a_mask_sizeOH_T, 1, 0) node _put_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), put_a_mask_sizeOH_shiftAmount) node _put_a_mask_sizeOH_T_2 = bits(_put_a_mask_sizeOH_T_1, 3, 0) node put_a_mask_sizeOH = or(_put_a_mask_sizeOH_T_2, UInt<1>(0h1)) node put_a_mask_sub_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<3>(0h4)) node put_a_mask_sub_sub_sub_size = bits(put_a_mask_sizeOH, 3, 3) node put_a_mask_sub_sub_sub_bit = bits(req.addr, 3, 3) node put_a_mask_sub_sub_sub_nbit = eq(put_a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node put_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_sub_nbit) node _put_a_mask_sub_sub_sub_acc_T = and(put_a_mask_sub_sub_sub_size, put_a_mask_sub_sub_sub_0_2) node put_a_mask_sub_sub_sub_0_1 = or(put_a_mask_sub_sub_sub_sub_0_1, _put_a_mask_sub_sub_sub_acc_T) node put_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_sub_bit) node _put_a_mask_sub_sub_sub_acc_T_1 = and(put_a_mask_sub_sub_sub_size, put_a_mask_sub_sub_sub_1_2) node put_a_mask_sub_sub_sub_1_1 = or(put_a_mask_sub_sub_sub_sub_0_1, _put_a_mask_sub_sub_sub_acc_T_1) node put_a_mask_sub_sub_size = bits(put_a_mask_sizeOH, 2, 2) node put_a_mask_sub_sub_bit = bits(req.addr, 2, 2) node put_a_mask_sub_sub_nbit = eq(put_a_mask_sub_sub_bit, UInt<1>(0h0)) node put_a_mask_sub_sub_0_2 = and(put_a_mask_sub_sub_sub_0_2, put_a_mask_sub_sub_nbit) node _put_a_mask_sub_sub_acc_T = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_0_2) node put_a_mask_sub_sub_0_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T) node put_a_mask_sub_sub_1_2 = and(put_a_mask_sub_sub_sub_0_2, put_a_mask_sub_sub_bit) node _put_a_mask_sub_sub_acc_T_1 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_1_2) node put_a_mask_sub_sub_1_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T_1) node put_a_mask_sub_sub_2_2 = and(put_a_mask_sub_sub_sub_1_2, put_a_mask_sub_sub_nbit) node _put_a_mask_sub_sub_acc_T_2 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_2_2) node put_a_mask_sub_sub_2_1 = or(put_a_mask_sub_sub_sub_1_1, _put_a_mask_sub_sub_acc_T_2) node put_a_mask_sub_sub_3_2 = and(put_a_mask_sub_sub_sub_1_2, put_a_mask_sub_sub_bit) node _put_a_mask_sub_sub_acc_T_3 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_3_2) node put_a_mask_sub_sub_3_1 = or(put_a_mask_sub_sub_sub_1_1, _put_a_mask_sub_sub_acc_T_3) node put_a_mask_sub_size = bits(put_a_mask_sizeOH, 1, 1) node put_a_mask_sub_bit = bits(req.addr, 1, 1) node put_a_mask_sub_nbit = eq(put_a_mask_sub_bit, UInt<1>(0h0)) node put_a_mask_sub_0_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_nbit) node _put_a_mask_sub_acc_T = and(put_a_mask_sub_size, put_a_mask_sub_0_2) node put_a_mask_sub_0_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T) node put_a_mask_sub_1_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_bit) node _put_a_mask_sub_acc_T_1 = and(put_a_mask_sub_size, put_a_mask_sub_1_2) node put_a_mask_sub_1_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T_1) node put_a_mask_sub_2_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_nbit) node _put_a_mask_sub_acc_T_2 = and(put_a_mask_sub_size, put_a_mask_sub_2_2) node put_a_mask_sub_2_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_2) node put_a_mask_sub_3_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_bit) node _put_a_mask_sub_acc_T_3 = and(put_a_mask_sub_size, put_a_mask_sub_3_2) node put_a_mask_sub_3_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_3) node put_a_mask_sub_4_2 = and(put_a_mask_sub_sub_2_2, put_a_mask_sub_nbit) node _put_a_mask_sub_acc_T_4 = and(put_a_mask_sub_size, put_a_mask_sub_4_2) node put_a_mask_sub_4_1 = or(put_a_mask_sub_sub_2_1, _put_a_mask_sub_acc_T_4) node put_a_mask_sub_5_2 = and(put_a_mask_sub_sub_2_2, put_a_mask_sub_bit) node _put_a_mask_sub_acc_T_5 = and(put_a_mask_sub_size, put_a_mask_sub_5_2) node put_a_mask_sub_5_1 = or(put_a_mask_sub_sub_2_1, _put_a_mask_sub_acc_T_5) node put_a_mask_sub_6_2 = and(put_a_mask_sub_sub_3_2, put_a_mask_sub_nbit) node _put_a_mask_sub_acc_T_6 = and(put_a_mask_sub_size, put_a_mask_sub_6_2) node put_a_mask_sub_6_1 = or(put_a_mask_sub_sub_3_1, _put_a_mask_sub_acc_T_6) node put_a_mask_sub_7_2 = and(put_a_mask_sub_sub_3_2, put_a_mask_sub_bit) node _put_a_mask_sub_acc_T_7 = and(put_a_mask_sub_size, put_a_mask_sub_7_2) node put_a_mask_sub_7_1 = or(put_a_mask_sub_sub_3_1, _put_a_mask_sub_acc_T_7) node put_a_mask_size = bits(put_a_mask_sizeOH, 0, 0) node put_a_mask_bit = bits(req.addr, 0, 0) node put_a_mask_nbit = eq(put_a_mask_bit, UInt<1>(0h0)) node put_a_mask_eq = and(put_a_mask_sub_0_2, put_a_mask_nbit) node _put_a_mask_acc_T = and(put_a_mask_size, put_a_mask_eq) node put_a_mask_acc = or(put_a_mask_sub_0_1, _put_a_mask_acc_T) node put_a_mask_eq_1 = and(put_a_mask_sub_0_2, put_a_mask_bit) node _put_a_mask_acc_T_1 = and(put_a_mask_size, put_a_mask_eq_1) node put_a_mask_acc_1 = or(put_a_mask_sub_0_1, _put_a_mask_acc_T_1) node put_a_mask_eq_2 = and(put_a_mask_sub_1_2, put_a_mask_nbit) node _put_a_mask_acc_T_2 = and(put_a_mask_size, put_a_mask_eq_2) node put_a_mask_acc_2 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_2) node put_a_mask_eq_3 = and(put_a_mask_sub_1_2, put_a_mask_bit) node _put_a_mask_acc_T_3 = and(put_a_mask_size, put_a_mask_eq_3) node put_a_mask_acc_3 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_3) node put_a_mask_eq_4 = and(put_a_mask_sub_2_2, put_a_mask_nbit) node _put_a_mask_acc_T_4 = and(put_a_mask_size, put_a_mask_eq_4) node put_a_mask_acc_4 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_4) node put_a_mask_eq_5 = and(put_a_mask_sub_2_2, put_a_mask_bit) node _put_a_mask_acc_T_5 = and(put_a_mask_size, put_a_mask_eq_5) node put_a_mask_acc_5 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_5) node put_a_mask_eq_6 = and(put_a_mask_sub_3_2, put_a_mask_nbit) node _put_a_mask_acc_T_6 = and(put_a_mask_size, put_a_mask_eq_6) node put_a_mask_acc_6 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_6) node put_a_mask_eq_7 = and(put_a_mask_sub_3_2, put_a_mask_bit) node _put_a_mask_acc_T_7 = and(put_a_mask_size, put_a_mask_eq_7) node put_a_mask_acc_7 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_7) node put_a_mask_eq_8 = and(put_a_mask_sub_4_2, put_a_mask_nbit) node _put_a_mask_acc_T_8 = and(put_a_mask_size, put_a_mask_eq_8) node put_a_mask_acc_8 = or(put_a_mask_sub_4_1, _put_a_mask_acc_T_8) node put_a_mask_eq_9 = and(put_a_mask_sub_4_2, put_a_mask_bit) node _put_a_mask_acc_T_9 = and(put_a_mask_size, put_a_mask_eq_9) node put_a_mask_acc_9 = or(put_a_mask_sub_4_1, _put_a_mask_acc_T_9) node put_a_mask_eq_10 = and(put_a_mask_sub_5_2, put_a_mask_nbit) node _put_a_mask_acc_T_10 = and(put_a_mask_size, put_a_mask_eq_10) node put_a_mask_acc_10 = or(put_a_mask_sub_5_1, _put_a_mask_acc_T_10) node put_a_mask_eq_11 = and(put_a_mask_sub_5_2, put_a_mask_bit) node _put_a_mask_acc_T_11 = and(put_a_mask_size, put_a_mask_eq_11) node put_a_mask_acc_11 = or(put_a_mask_sub_5_1, _put_a_mask_acc_T_11) node put_a_mask_eq_12 = and(put_a_mask_sub_6_2, put_a_mask_nbit) node _put_a_mask_acc_T_12 = and(put_a_mask_size, put_a_mask_eq_12) node put_a_mask_acc_12 = or(put_a_mask_sub_6_1, _put_a_mask_acc_T_12) node put_a_mask_eq_13 = and(put_a_mask_sub_6_2, put_a_mask_bit) node _put_a_mask_acc_T_13 = and(put_a_mask_size, put_a_mask_eq_13) node put_a_mask_acc_13 = or(put_a_mask_sub_6_1, _put_a_mask_acc_T_13) node put_a_mask_eq_14 = and(put_a_mask_sub_7_2, put_a_mask_nbit) node _put_a_mask_acc_T_14 = and(put_a_mask_size, put_a_mask_eq_14) node put_a_mask_acc_14 = or(put_a_mask_sub_7_1, _put_a_mask_acc_T_14) node put_a_mask_eq_15 = and(put_a_mask_sub_7_2, put_a_mask_bit) node _put_a_mask_acc_T_15 = and(put_a_mask_size, put_a_mask_eq_15) node put_a_mask_acc_15 = or(put_a_mask_sub_7_1, _put_a_mask_acc_T_15) node put_a_mask_lo_lo_lo = cat(put_a_mask_acc_1, put_a_mask_acc) node put_a_mask_lo_lo_hi = cat(put_a_mask_acc_3, put_a_mask_acc_2) node put_a_mask_lo_lo = cat(put_a_mask_lo_lo_hi, put_a_mask_lo_lo_lo) node put_a_mask_lo_hi_lo = cat(put_a_mask_acc_5, put_a_mask_acc_4) node put_a_mask_lo_hi_hi = cat(put_a_mask_acc_7, put_a_mask_acc_6) node put_a_mask_lo_hi = cat(put_a_mask_lo_hi_hi, put_a_mask_lo_hi_lo) node put_a_mask_lo = cat(put_a_mask_lo_hi, put_a_mask_lo_lo) node put_a_mask_hi_lo_lo = cat(put_a_mask_acc_9, put_a_mask_acc_8) node put_a_mask_hi_lo_hi = cat(put_a_mask_acc_11, put_a_mask_acc_10) node put_a_mask_hi_lo = cat(put_a_mask_hi_lo_hi, put_a_mask_hi_lo_lo) node put_a_mask_hi_hi_lo = cat(put_a_mask_acc_13, put_a_mask_acc_12) node put_a_mask_hi_hi_hi = cat(put_a_mask_acc_15, put_a_mask_acc_14) node put_a_mask_hi_hi = cat(put_a_mask_hi_hi_hi, put_a_mask_hi_hi_lo) node put_a_mask_hi = cat(put_a_mask_hi_hi, put_a_mask_hi_lo) node _put_a_mask_T = cat(put_a_mask_hi, put_a_mask_lo) connect put.mask, _put_a_mask_T connect put.data, a_data connect put.corrupt, UInt<1>(0h0) wire _atomics_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect _atomics_WIRE.corrupt, UInt<1>(0h0) connect _atomics_WIRE.data, UInt<128>(0h0) connect _atomics_WIRE.mask, UInt<16>(0h0) connect _atomics_WIRE.address, UInt<32>(0h0) connect _atomics_WIRE.source, UInt<3>(0h0) connect _atomics_WIRE.size, UInt<4>(0h0) connect _atomics_WIRE.param, UInt<3>(0h0) connect _atomics_WIRE.opcode, UInt<3>(0h0) node _atomics_legal_T = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_1 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_2 = and(_atomics_legal_T, _atomics_legal_T_1) node _atomics_legal_T_3 = or(UInt<1>(0h0), _atomics_legal_T_2) node _atomics_legal_T_4 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_5 = cvt(_atomics_legal_T_4) node _atomics_legal_T_6 = and(_atomics_legal_T_5, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_7 = asSInt(_atomics_legal_T_6) node _atomics_legal_T_8 = eq(_atomics_legal_T_7, asSInt(UInt<1>(0h0))) node _atomics_legal_T_9 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_10 = cvt(_atomics_legal_T_9) node _atomics_legal_T_11 = and(_atomics_legal_T_10, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_12 = asSInt(_atomics_legal_T_11) node _atomics_legal_T_13 = eq(_atomics_legal_T_12, asSInt(UInt<1>(0h0))) node _atomics_legal_T_14 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_15 = cvt(_atomics_legal_T_14) node _atomics_legal_T_16 = and(_atomics_legal_T_15, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_17 = asSInt(_atomics_legal_T_16) node _atomics_legal_T_18 = eq(_atomics_legal_T_17, asSInt(UInt<1>(0h0))) node _atomics_legal_T_19 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_20 = cvt(_atomics_legal_T_19) node _atomics_legal_T_21 = and(_atomics_legal_T_20, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_22 = asSInt(_atomics_legal_T_21) node _atomics_legal_T_23 = eq(_atomics_legal_T_22, asSInt(UInt<1>(0h0))) node _atomics_legal_T_24 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_25 = cvt(_atomics_legal_T_24) node _atomics_legal_T_26 = and(_atomics_legal_T_25, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_27 = asSInt(_atomics_legal_T_26) node _atomics_legal_T_28 = eq(_atomics_legal_T_27, asSInt(UInt<1>(0h0))) node _atomics_legal_T_29 = or(_atomics_legal_T_8, _atomics_legal_T_13) node _atomics_legal_T_30 = or(_atomics_legal_T_29, _atomics_legal_T_18) node _atomics_legal_T_31 = or(_atomics_legal_T_30, _atomics_legal_T_23) node _atomics_legal_T_32 = or(_atomics_legal_T_31, _atomics_legal_T_28) node _atomics_legal_T_33 = and(_atomics_legal_T_3, _atomics_legal_T_32) node _atomics_legal_T_34 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_35 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_36 = cvt(_atomics_legal_T_35) node _atomics_legal_T_37 = and(_atomics_legal_T_36, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_38 = asSInt(_atomics_legal_T_37) node _atomics_legal_T_39 = eq(_atomics_legal_T_38, asSInt(UInt<1>(0h0))) node _atomics_legal_T_40 = and(_atomics_legal_T_34, _atomics_legal_T_39) node _atomics_legal_T_41 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_42 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_43 = and(_atomics_legal_T_41, _atomics_legal_T_42) node _atomics_legal_T_44 = or(UInt<1>(0h0), _atomics_legal_T_43) node _atomics_legal_T_45 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_46 = cvt(_atomics_legal_T_45) node _atomics_legal_T_47 = and(_atomics_legal_T_46, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_48 = asSInt(_atomics_legal_T_47) node _atomics_legal_T_49 = eq(_atomics_legal_T_48, asSInt(UInt<1>(0h0))) node _atomics_legal_T_50 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_51 = cvt(_atomics_legal_T_50) node _atomics_legal_T_52 = and(_atomics_legal_T_51, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_53 = asSInt(_atomics_legal_T_52) node _atomics_legal_T_54 = eq(_atomics_legal_T_53, asSInt(UInt<1>(0h0))) node _atomics_legal_T_55 = or(_atomics_legal_T_49, _atomics_legal_T_54) node _atomics_legal_T_56 = and(_atomics_legal_T_44, _atomics_legal_T_55) node _atomics_legal_T_57 = or(UInt<1>(0h0), _atomics_legal_T_33) node _atomics_legal_T_58 = or(_atomics_legal_T_57, _atomics_legal_T_40) node atomics_legal = or(_atomics_legal_T_58, _atomics_legal_T_56) wire atomics_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a.opcode, UInt<2>(0h3) connect atomics_a.param, UInt<3>(0h3) connect atomics_a.size, req.uop.mem_size connect atomics_a.source, UInt<3>(0h5) connect atomics_a.address, req.addr node _atomics_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount = bits(_atomics_a_mask_sizeOH_T, 1, 0) node _atomics_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount) node _atomics_a_mask_sizeOH_T_2 = bits(_atomics_a_mask_sizeOH_T_1, 3, 0) node atomics_a_mask_sizeOH = or(_atomics_a_mask_sizeOH_T_2, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size = bits(atomics_a_mask_sizeOH, 3, 3) node atomics_a_mask_sub_sub_sub_bit = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit = eq(atomics_a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit) node _atomics_a_mask_sub_sub_sub_acc_T = and(atomics_a_mask_sub_sub_sub_size, atomics_a_mask_sub_sub_sub_0_2) node atomics_a_mask_sub_sub_sub_0_1 = or(atomics_a_mask_sub_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_sub_acc_T) node atomics_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit) node _atomics_a_mask_sub_sub_sub_acc_T_1 = and(atomics_a_mask_sub_sub_sub_size, atomics_a_mask_sub_sub_sub_1_2) node atomics_a_mask_sub_sub_sub_1_1 = or(atomics_a_mask_sub_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_sub_acc_T_1) node atomics_a_mask_sub_sub_size = bits(atomics_a_mask_sizeOH, 2, 2) node atomics_a_mask_sub_sub_bit = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit = eq(atomics_a_mask_sub_sub_bit, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2 = and(atomics_a_mask_sub_sub_sub_0_2, atomics_a_mask_sub_sub_nbit) node _atomics_a_mask_sub_sub_acc_T = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_0_2) node atomics_a_mask_sub_sub_0_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T) node atomics_a_mask_sub_sub_1_2 = and(atomics_a_mask_sub_sub_sub_0_2, atomics_a_mask_sub_sub_bit) node _atomics_a_mask_sub_sub_acc_T_1 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_1_2) node atomics_a_mask_sub_sub_1_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T_1) node atomics_a_mask_sub_sub_2_2 = and(atomics_a_mask_sub_sub_sub_1_2, atomics_a_mask_sub_sub_nbit) node _atomics_a_mask_sub_sub_acc_T_2 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_2_2) node atomics_a_mask_sub_sub_2_1 = or(atomics_a_mask_sub_sub_sub_1_1, _atomics_a_mask_sub_sub_acc_T_2) node atomics_a_mask_sub_sub_3_2 = and(atomics_a_mask_sub_sub_sub_1_2, atomics_a_mask_sub_sub_bit) node _atomics_a_mask_sub_sub_acc_T_3 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_3_2) node atomics_a_mask_sub_sub_3_1 = or(atomics_a_mask_sub_sub_sub_1_1, _atomics_a_mask_sub_sub_acc_T_3) node atomics_a_mask_sub_size = bits(atomics_a_mask_sizeOH, 1, 1) node atomics_a_mask_sub_bit = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit = eq(atomics_a_mask_sub_bit, UInt<1>(0h0)) node atomics_a_mask_sub_0_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_nbit) node _atomics_a_mask_sub_acc_T = and(atomics_a_mask_sub_size, atomics_a_mask_sub_0_2) node atomics_a_mask_sub_0_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T) node atomics_a_mask_sub_1_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_bit) node _atomics_a_mask_sub_acc_T_1 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_1_2) node atomics_a_mask_sub_1_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T_1) node atomics_a_mask_sub_2_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_nbit) node _atomics_a_mask_sub_acc_T_2 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_2_2) node atomics_a_mask_sub_2_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_2) node atomics_a_mask_sub_3_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_bit) node _atomics_a_mask_sub_acc_T_3 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_3_2) node atomics_a_mask_sub_3_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_3) node atomics_a_mask_sub_4_2 = and(atomics_a_mask_sub_sub_2_2, atomics_a_mask_sub_nbit) node _atomics_a_mask_sub_acc_T_4 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_4_2) node atomics_a_mask_sub_4_1 = or(atomics_a_mask_sub_sub_2_1, _atomics_a_mask_sub_acc_T_4) node atomics_a_mask_sub_5_2 = and(atomics_a_mask_sub_sub_2_2, atomics_a_mask_sub_bit) node _atomics_a_mask_sub_acc_T_5 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_5_2) node atomics_a_mask_sub_5_1 = or(atomics_a_mask_sub_sub_2_1, _atomics_a_mask_sub_acc_T_5) node atomics_a_mask_sub_6_2 = and(atomics_a_mask_sub_sub_3_2, atomics_a_mask_sub_nbit) node _atomics_a_mask_sub_acc_T_6 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_6_2) node atomics_a_mask_sub_6_1 = or(atomics_a_mask_sub_sub_3_1, _atomics_a_mask_sub_acc_T_6) node atomics_a_mask_sub_7_2 = and(atomics_a_mask_sub_sub_3_2, atomics_a_mask_sub_bit) node _atomics_a_mask_sub_acc_T_7 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_7_2) node atomics_a_mask_sub_7_1 = or(atomics_a_mask_sub_sub_3_1, _atomics_a_mask_sub_acc_T_7) node atomics_a_mask_size = bits(atomics_a_mask_sizeOH, 0, 0) node atomics_a_mask_bit = bits(req.addr, 0, 0) node atomics_a_mask_nbit = eq(atomics_a_mask_bit, UInt<1>(0h0)) node atomics_a_mask_eq = and(atomics_a_mask_sub_0_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T = and(atomics_a_mask_size, atomics_a_mask_eq) node atomics_a_mask_acc = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T) node atomics_a_mask_eq_1 = and(atomics_a_mask_sub_0_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_1 = and(atomics_a_mask_size, atomics_a_mask_eq_1) node atomics_a_mask_acc_1 = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T_1) node atomics_a_mask_eq_2 = and(atomics_a_mask_sub_1_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_2 = and(atomics_a_mask_size, atomics_a_mask_eq_2) node atomics_a_mask_acc_2 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_2) node atomics_a_mask_eq_3 = and(atomics_a_mask_sub_1_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_3 = and(atomics_a_mask_size, atomics_a_mask_eq_3) node atomics_a_mask_acc_3 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_3) node atomics_a_mask_eq_4 = and(atomics_a_mask_sub_2_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_4 = and(atomics_a_mask_size, atomics_a_mask_eq_4) node atomics_a_mask_acc_4 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_4) node atomics_a_mask_eq_5 = and(atomics_a_mask_sub_2_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_5 = and(atomics_a_mask_size, atomics_a_mask_eq_5) node atomics_a_mask_acc_5 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_5) node atomics_a_mask_eq_6 = and(atomics_a_mask_sub_3_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_6 = and(atomics_a_mask_size, atomics_a_mask_eq_6) node atomics_a_mask_acc_6 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_6) node atomics_a_mask_eq_7 = and(atomics_a_mask_sub_3_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_7 = and(atomics_a_mask_size, atomics_a_mask_eq_7) node atomics_a_mask_acc_7 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_7) node atomics_a_mask_eq_8 = and(atomics_a_mask_sub_4_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_8 = and(atomics_a_mask_size, atomics_a_mask_eq_8) node atomics_a_mask_acc_8 = or(atomics_a_mask_sub_4_1, _atomics_a_mask_acc_T_8) node atomics_a_mask_eq_9 = and(atomics_a_mask_sub_4_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_9 = and(atomics_a_mask_size, atomics_a_mask_eq_9) node atomics_a_mask_acc_9 = or(atomics_a_mask_sub_4_1, _atomics_a_mask_acc_T_9) node atomics_a_mask_eq_10 = and(atomics_a_mask_sub_5_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_10 = and(atomics_a_mask_size, atomics_a_mask_eq_10) node atomics_a_mask_acc_10 = or(atomics_a_mask_sub_5_1, _atomics_a_mask_acc_T_10) node atomics_a_mask_eq_11 = and(atomics_a_mask_sub_5_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_11 = and(atomics_a_mask_size, atomics_a_mask_eq_11) node atomics_a_mask_acc_11 = or(atomics_a_mask_sub_5_1, _atomics_a_mask_acc_T_11) node atomics_a_mask_eq_12 = and(atomics_a_mask_sub_6_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_12 = and(atomics_a_mask_size, atomics_a_mask_eq_12) node atomics_a_mask_acc_12 = or(atomics_a_mask_sub_6_1, _atomics_a_mask_acc_T_12) node atomics_a_mask_eq_13 = and(atomics_a_mask_sub_6_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_13 = and(atomics_a_mask_size, atomics_a_mask_eq_13) node atomics_a_mask_acc_13 = or(atomics_a_mask_sub_6_1, _atomics_a_mask_acc_T_13) node atomics_a_mask_eq_14 = and(atomics_a_mask_sub_7_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_14 = and(atomics_a_mask_size, atomics_a_mask_eq_14) node atomics_a_mask_acc_14 = or(atomics_a_mask_sub_7_1, _atomics_a_mask_acc_T_14) node atomics_a_mask_eq_15 = and(atomics_a_mask_sub_7_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_15 = and(atomics_a_mask_size, atomics_a_mask_eq_15) node atomics_a_mask_acc_15 = or(atomics_a_mask_sub_7_1, _atomics_a_mask_acc_T_15) node atomics_a_mask_lo_lo_lo = cat(atomics_a_mask_acc_1, atomics_a_mask_acc) node atomics_a_mask_lo_lo_hi = cat(atomics_a_mask_acc_3, atomics_a_mask_acc_2) node atomics_a_mask_lo_lo = cat(atomics_a_mask_lo_lo_hi, atomics_a_mask_lo_lo_lo) node atomics_a_mask_lo_hi_lo = cat(atomics_a_mask_acc_5, atomics_a_mask_acc_4) node atomics_a_mask_lo_hi_hi = cat(atomics_a_mask_acc_7, atomics_a_mask_acc_6) node atomics_a_mask_lo_hi = cat(atomics_a_mask_lo_hi_hi, atomics_a_mask_lo_hi_lo) node atomics_a_mask_lo = cat(atomics_a_mask_lo_hi, atomics_a_mask_lo_lo) node atomics_a_mask_hi_lo_lo = cat(atomics_a_mask_acc_9, atomics_a_mask_acc_8) node atomics_a_mask_hi_lo_hi = cat(atomics_a_mask_acc_11, atomics_a_mask_acc_10) node atomics_a_mask_hi_lo = cat(atomics_a_mask_hi_lo_hi, atomics_a_mask_hi_lo_lo) node atomics_a_mask_hi_hi_lo = cat(atomics_a_mask_acc_13, atomics_a_mask_acc_12) node atomics_a_mask_hi_hi_hi = cat(atomics_a_mask_acc_15, atomics_a_mask_acc_14) node atomics_a_mask_hi_hi = cat(atomics_a_mask_hi_hi_hi, atomics_a_mask_hi_hi_lo) node atomics_a_mask_hi = cat(atomics_a_mask_hi_hi, atomics_a_mask_hi_lo) node _atomics_a_mask_T = cat(atomics_a_mask_hi, atomics_a_mask_lo) connect atomics_a.mask, _atomics_a_mask_T connect atomics_a.data, a_data connect atomics_a.corrupt, UInt<1>(0h0) node _atomics_legal_T_59 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_60 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_61 = and(_atomics_legal_T_59, _atomics_legal_T_60) node _atomics_legal_T_62 = or(UInt<1>(0h0), _atomics_legal_T_61) node _atomics_legal_T_63 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_64 = cvt(_atomics_legal_T_63) node _atomics_legal_T_65 = and(_atomics_legal_T_64, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_66 = asSInt(_atomics_legal_T_65) node _atomics_legal_T_67 = eq(_atomics_legal_T_66, asSInt(UInt<1>(0h0))) node _atomics_legal_T_68 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_69 = cvt(_atomics_legal_T_68) node _atomics_legal_T_70 = and(_atomics_legal_T_69, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_71 = asSInt(_atomics_legal_T_70) node _atomics_legal_T_72 = eq(_atomics_legal_T_71, asSInt(UInt<1>(0h0))) node _atomics_legal_T_73 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_74 = cvt(_atomics_legal_T_73) node _atomics_legal_T_75 = and(_atomics_legal_T_74, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_76 = asSInt(_atomics_legal_T_75) node _atomics_legal_T_77 = eq(_atomics_legal_T_76, asSInt(UInt<1>(0h0))) node _atomics_legal_T_78 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_79 = cvt(_atomics_legal_T_78) node _atomics_legal_T_80 = and(_atomics_legal_T_79, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_81 = asSInt(_atomics_legal_T_80) node _atomics_legal_T_82 = eq(_atomics_legal_T_81, asSInt(UInt<1>(0h0))) node _atomics_legal_T_83 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_84 = cvt(_atomics_legal_T_83) node _atomics_legal_T_85 = and(_atomics_legal_T_84, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_86 = asSInt(_atomics_legal_T_85) node _atomics_legal_T_87 = eq(_atomics_legal_T_86, asSInt(UInt<1>(0h0))) node _atomics_legal_T_88 = or(_atomics_legal_T_67, _atomics_legal_T_72) node _atomics_legal_T_89 = or(_atomics_legal_T_88, _atomics_legal_T_77) node _atomics_legal_T_90 = or(_atomics_legal_T_89, _atomics_legal_T_82) node _atomics_legal_T_91 = or(_atomics_legal_T_90, _atomics_legal_T_87) node _atomics_legal_T_92 = and(_atomics_legal_T_62, _atomics_legal_T_91) node _atomics_legal_T_93 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_94 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_95 = cvt(_atomics_legal_T_94) node _atomics_legal_T_96 = and(_atomics_legal_T_95, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_97 = asSInt(_atomics_legal_T_96) node _atomics_legal_T_98 = eq(_atomics_legal_T_97, asSInt(UInt<1>(0h0))) node _atomics_legal_T_99 = and(_atomics_legal_T_93, _atomics_legal_T_98) node _atomics_legal_T_100 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_101 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_102 = and(_atomics_legal_T_100, _atomics_legal_T_101) node _atomics_legal_T_103 = or(UInt<1>(0h0), _atomics_legal_T_102) node _atomics_legal_T_104 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_105 = cvt(_atomics_legal_T_104) node _atomics_legal_T_106 = and(_atomics_legal_T_105, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_107 = asSInt(_atomics_legal_T_106) node _atomics_legal_T_108 = eq(_atomics_legal_T_107, asSInt(UInt<1>(0h0))) node _atomics_legal_T_109 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_110 = cvt(_atomics_legal_T_109) node _atomics_legal_T_111 = and(_atomics_legal_T_110, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_112 = asSInt(_atomics_legal_T_111) node _atomics_legal_T_113 = eq(_atomics_legal_T_112, asSInt(UInt<1>(0h0))) node _atomics_legal_T_114 = or(_atomics_legal_T_108, _atomics_legal_T_113) node _atomics_legal_T_115 = and(_atomics_legal_T_103, _atomics_legal_T_114) node _atomics_legal_T_116 = or(UInt<1>(0h0), _atomics_legal_T_92) node _atomics_legal_T_117 = or(_atomics_legal_T_116, _atomics_legal_T_99) node atomics_legal_1 = or(_atomics_legal_T_117, _atomics_legal_T_115) wire atomics_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_1.opcode, UInt<2>(0h3) connect atomics_a_1.param, UInt<3>(0h0) connect atomics_a_1.size, req.uop.mem_size connect atomics_a_1.source, UInt<3>(0h5) connect atomics_a_1.address, req.addr node _atomics_a_mask_sizeOH_T_3 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_1 = bits(_atomics_a_mask_sizeOH_T_3, 1, 0) node _atomics_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_1) node _atomics_a_mask_sizeOH_T_5 = bits(_atomics_a_mask_sizeOH_T_4, 3, 0) node atomics_a_mask_sizeOH_1 = or(_atomics_a_mask_sizeOH_T_5, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_1 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 3, 3) node atomics_a_mask_sub_sub_sub_bit_1 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_1 = eq(atomics_a_mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_1) node _atomics_a_mask_sub_sub_sub_acc_T_2 = and(atomics_a_mask_sub_sub_sub_size_1, atomics_a_mask_sub_sub_sub_0_2_1) node atomics_a_mask_sub_sub_sub_0_1_1 = or(atomics_a_mask_sub_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_sub_acc_T_2) node atomics_a_mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_1) node _atomics_a_mask_sub_sub_sub_acc_T_3 = and(atomics_a_mask_sub_sub_sub_size_1, atomics_a_mask_sub_sub_sub_1_2_1) node atomics_a_mask_sub_sub_sub_1_1_1 = or(atomics_a_mask_sub_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_sub_acc_T_3) node atomics_a_mask_sub_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 2, 2) node atomics_a_mask_sub_sub_bit_1 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_1 = eq(atomics_a_mask_sub_sub_bit_1, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_1 = and(atomics_a_mask_sub_sub_sub_0_2_1, atomics_a_mask_sub_sub_nbit_1) node _atomics_a_mask_sub_sub_acc_T_4 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_0_2_1) node atomics_a_mask_sub_sub_0_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_4) node atomics_a_mask_sub_sub_1_2_1 = and(atomics_a_mask_sub_sub_sub_0_2_1, atomics_a_mask_sub_sub_bit_1) node _atomics_a_mask_sub_sub_acc_T_5 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_1_2_1) node atomics_a_mask_sub_sub_1_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_5) node atomics_a_mask_sub_sub_2_2_1 = and(atomics_a_mask_sub_sub_sub_1_2_1, atomics_a_mask_sub_sub_nbit_1) node _atomics_a_mask_sub_sub_acc_T_6 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_2_2_1) node atomics_a_mask_sub_sub_2_1_1 = or(atomics_a_mask_sub_sub_sub_1_1_1, _atomics_a_mask_sub_sub_acc_T_6) node atomics_a_mask_sub_sub_3_2_1 = and(atomics_a_mask_sub_sub_sub_1_2_1, atomics_a_mask_sub_sub_bit_1) node _atomics_a_mask_sub_sub_acc_T_7 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_3_2_1) node atomics_a_mask_sub_sub_3_1_1 = or(atomics_a_mask_sub_sub_sub_1_1_1, _atomics_a_mask_sub_sub_acc_T_7) node atomics_a_mask_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 1, 1) node atomics_a_mask_sub_bit_1 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_1 = eq(atomics_a_mask_sub_bit_1, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_nbit_1) node _atomics_a_mask_sub_acc_T_8 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_0_2_1) node atomics_a_mask_sub_0_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_8) node atomics_a_mask_sub_1_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_bit_1) node _atomics_a_mask_sub_acc_T_9 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_1_2_1) node atomics_a_mask_sub_1_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_9) node atomics_a_mask_sub_2_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_nbit_1) node _atomics_a_mask_sub_acc_T_10 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_2_2_1) node atomics_a_mask_sub_2_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_10) node atomics_a_mask_sub_3_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_bit_1) node _atomics_a_mask_sub_acc_T_11 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_3_2_1) node atomics_a_mask_sub_3_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_11) node atomics_a_mask_sub_4_2_1 = and(atomics_a_mask_sub_sub_2_2_1, atomics_a_mask_sub_nbit_1) node _atomics_a_mask_sub_acc_T_12 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_4_2_1) node atomics_a_mask_sub_4_1_1 = or(atomics_a_mask_sub_sub_2_1_1, _atomics_a_mask_sub_acc_T_12) node atomics_a_mask_sub_5_2_1 = and(atomics_a_mask_sub_sub_2_2_1, atomics_a_mask_sub_bit_1) node _atomics_a_mask_sub_acc_T_13 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_5_2_1) node atomics_a_mask_sub_5_1_1 = or(atomics_a_mask_sub_sub_2_1_1, _atomics_a_mask_sub_acc_T_13) node atomics_a_mask_sub_6_2_1 = and(atomics_a_mask_sub_sub_3_2_1, atomics_a_mask_sub_nbit_1) node _atomics_a_mask_sub_acc_T_14 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_6_2_1) node atomics_a_mask_sub_6_1_1 = or(atomics_a_mask_sub_sub_3_1_1, _atomics_a_mask_sub_acc_T_14) node atomics_a_mask_sub_7_2_1 = and(atomics_a_mask_sub_sub_3_2_1, atomics_a_mask_sub_bit_1) node _atomics_a_mask_sub_acc_T_15 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_7_2_1) node atomics_a_mask_sub_7_1_1 = or(atomics_a_mask_sub_sub_3_1_1, _atomics_a_mask_sub_acc_T_15) node atomics_a_mask_size_1 = bits(atomics_a_mask_sizeOH_1, 0, 0) node atomics_a_mask_bit_1 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_1 = eq(atomics_a_mask_bit_1, UInt<1>(0h0)) node atomics_a_mask_eq_16 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_16 = and(atomics_a_mask_size_1, atomics_a_mask_eq_16) node atomics_a_mask_acc_16 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_16) node atomics_a_mask_eq_17 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_17 = and(atomics_a_mask_size_1, atomics_a_mask_eq_17) node atomics_a_mask_acc_17 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_17) node atomics_a_mask_eq_18 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_18 = and(atomics_a_mask_size_1, atomics_a_mask_eq_18) node atomics_a_mask_acc_18 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_18) node atomics_a_mask_eq_19 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_19 = and(atomics_a_mask_size_1, atomics_a_mask_eq_19) node atomics_a_mask_acc_19 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_19) node atomics_a_mask_eq_20 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_20 = and(atomics_a_mask_size_1, atomics_a_mask_eq_20) node atomics_a_mask_acc_20 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_20) node atomics_a_mask_eq_21 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_21 = and(atomics_a_mask_size_1, atomics_a_mask_eq_21) node atomics_a_mask_acc_21 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_21) node atomics_a_mask_eq_22 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_22 = and(atomics_a_mask_size_1, atomics_a_mask_eq_22) node atomics_a_mask_acc_22 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_22) node atomics_a_mask_eq_23 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_23 = and(atomics_a_mask_size_1, atomics_a_mask_eq_23) node atomics_a_mask_acc_23 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_23) node atomics_a_mask_eq_24 = and(atomics_a_mask_sub_4_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_24 = and(atomics_a_mask_size_1, atomics_a_mask_eq_24) node atomics_a_mask_acc_24 = or(atomics_a_mask_sub_4_1_1, _atomics_a_mask_acc_T_24) node atomics_a_mask_eq_25 = and(atomics_a_mask_sub_4_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_25 = and(atomics_a_mask_size_1, atomics_a_mask_eq_25) node atomics_a_mask_acc_25 = or(atomics_a_mask_sub_4_1_1, _atomics_a_mask_acc_T_25) node atomics_a_mask_eq_26 = and(atomics_a_mask_sub_5_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_26 = and(atomics_a_mask_size_1, atomics_a_mask_eq_26) node atomics_a_mask_acc_26 = or(atomics_a_mask_sub_5_1_1, _atomics_a_mask_acc_T_26) node atomics_a_mask_eq_27 = and(atomics_a_mask_sub_5_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_27 = and(atomics_a_mask_size_1, atomics_a_mask_eq_27) node atomics_a_mask_acc_27 = or(atomics_a_mask_sub_5_1_1, _atomics_a_mask_acc_T_27) node atomics_a_mask_eq_28 = and(atomics_a_mask_sub_6_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_28 = and(atomics_a_mask_size_1, atomics_a_mask_eq_28) node atomics_a_mask_acc_28 = or(atomics_a_mask_sub_6_1_1, _atomics_a_mask_acc_T_28) node atomics_a_mask_eq_29 = and(atomics_a_mask_sub_6_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_29 = and(atomics_a_mask_size_1, atomics_a_mask_eq_29) node atomics_a_mask_acc_29 = or(atomics_a_mask_sub_6_1_1, _atomics_a_mask_acc_T_29) node atomics_a_mask_eq_30 = and(atomics_a_mask_sub_7_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_30 = and(atomics_a_mask_size_1, atomics_a_mask_eq_30) node atomics_a_mask_acc_30 = or(atomics_a_mask_sub_7_1_1, _atomics_a_mask_acc_T_30) node atomics_a_mask_eq_31 = and(atomics_a_mask_sub_7_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_31 = and(atomics_a_mask_size_1, atomics_a_mask_eq_31) node atomics_a_mask_acc_31 = or(atomics_a_mask_sub_7_1_1, _atomics_a_mask_acc_T_31) node atomics_a_mask_lo_lo_lo_1 = cat(atomics_a_mask_acc_17, atomics_a_mask_acc_16) node atomics_a_mask_lo_lo_hi_1 = cat(atomics_a_mask_acc_19, atomics_a_mask_acc_18) node atomics_a_mask_lo_lo_1 = cat(atomics_a_mask_lo_lo_hi_1, atomics_a_mask_lo_lo_lo_1) node atomics_a_mask_lo_hi_lo_1 = cat(atomics_a_mask_acc_21, atomics_a_mask_acc_20) node atomics_a_mask_lo_hi_hi_1 = cat(atomics_a_mask_acc_23, atomics_a_mask_acc_22) node atomics_a_mask_lo_hi_1 = cat(atomics_a_mask_lo_hi_hi_1, atomics_a_mask_lo_hi_lo_1) node atomics_a_mask_lo_1 = cat(atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1) node atomics_a_mask_hi_lo_lo_1 = cat(atomics_a_mask_acc_25, atomics_a_mask_acc_24) node atomics_a_mask_hi_lo_hi_1 = cat(atomics_a_mask_acc_27, atomics_a_mask_acc_26) node atomics_a_mask_hi_lo_1 = cat(atomics_a_mask_hi_lo_hi_1, atomics_a_mask_hi_lo_lo_1) node atomics_a_mask_hi_hi_lo_1 = cat(atomics_a_mask_acc_29, atomics_a_mask_acc_28) node atomics_a_mask_hi_hi_hi_1 = cat(atomics_a_mask_acc_31, atomics_a_mask_acc_30) node atomics_a_mask_hi_hi_1 = cat(atomics_a_mask_hi_hi_hi_1, atomics_a_mask_hi_hi_lo_1) node atomics_a_mask_hi_1 = cat(atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1) node _atomics_a_mask_T_1 = cat(atomics_a_mask_hi_1, atomics_a_mask_lo_1) connect atomics_a_1.mask, _atomics_a_mask_T_1 connect atomics_a_1.data, a_data connect atomics_a_1.corrupt, UInt<1>(0h0) node _atomics_legal_T_118 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_119 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_120 = and(_atomics_legal_T_118, _atomics_legal_T_119) node _atomics_legal_T_121 = or(UInt<1>(0h0), _atomics_legal_T_120) node _atomics_legal_T_122 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_123 = cvt(_atomics_legal_T_122) node _atomics_legal_T_124 = and(_atomics_legal_T_123, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_125 = asSInt(_atomics_legal_T_124) node _atomics_legal_T_126 = eq(_atomics_legal_T_125, asSInt(UInt<1>(0h0))) node _atomics_legal_T_127 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_128 = cvt(_atomics_legal_T_127) node _atomics_legal_T_129 = and(_atomics_legal_T_128, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_130 = asSInt(_atomics_legal_T_129) node _atomics_legal_T_131 = eq(_atomics_legal_T_130, asSInt(UInt<1>(0h0))) node _atomics_legal_T_132 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_133 = cvt(_atomics_legal_T_132) node _atomics_legal_T_134 = and(_atomics_legal_T_133, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_135 = asSInt(_atomics_legal_T_134) node _atomics_legal_T_136 = eq(_atomics_legal_T_135, asSInt(UInt<1>(0h0))) node _atomics_legal_T_137 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_138 = cvt(_atomics_legal_T_137) node _atomics_legal_T_139 = and(_atomics_legal_T_138, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_140 = asSInt(_atomics_legal_T_139) node _atomics_legal_T_141 = eq(_atomics_legal_T_140, asSInt(UInt<1>(0h0))) node _atomics_legal_T_142 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_143 = cvt(_atomics_legal_T_142) node _atomics_legal_T_144 = and(_atomics_legal_T_143, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_145 = asSInt(_atomics_legal_T_144) node _atomics_legal_T_146 = eq(_atomics_legal_T_145, asSInt(UInt<1>(0h0))) node _atomics_legal_T_147 = or(_atomics_legal_T_126, _atomics_legal_T_131) node _atomics_legal_T_148 = or(_atomics_legal_T_147, _atomics_legal_T_136) node _atomics_legal_T_149 = or(_atomics_legal_T_148, _atomics_legal_T_141) node _atomics_legal_T_150 = or(_atomics_legal_T_149, _atomics_legal_T_146) node _atomics_legal_T_151 = and(_atomics_legal_T_121, _atomics_legal_T_150) node _atomics_legal_T_152 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_153 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_154 = cvt(_atomics_legal_T_153) node _atomics_legal_T_155 = and(_atomics_legal_T_154, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_156 = asSInt(_atomics_legal_T_155) node _atomics_legal_T_157 = eq(_atomics_legal_T_156, asSInt(UInt<1>(0h0))) node _atomics_legal_T_158 = and(_atomics_legal_T_152, _atomics_legal_T_157) node _atomics_legal_T_159 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_160 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_161 = and(_atomics_legal_T_159, _atomics_legal_T_160) node _atomics_legal_T_162 = or(UInt<1>(0h0), _atomics_legal_T_161) node _atomics_legal_T_163 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_164 = cvt(_atomics_legal_T_163) node _atomics_legal_T_165 = and(_atomics_legal_T_164, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_166 = asSInt(_atomics_legal_T_165) node _atomics_legal_T_167 = eq(_atomics_legal_T_166, asSInt(UInt<1>(0h0))) node _atomics_legal_T_168 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_169 = cvt(_atomics_legal_T_168) node _atomics_legal_T_170 = and(_atomics_legal_T_169, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_171 = asSInt(_atomics_legal_T_170) node _atomics_legal_T_172 = eq(_atomics_legal_T_171, asSInt(UInt<1>(0h0))) node _atomics_legal_T_173 = or(_atomics_legal_T_167, _atomics_legal_T_172) node _atomics_legal_T_174 = and(_atomics_legal_T_162, _atomics_legal_T_173) node _atomics_legal_T_175 = or(UInt<1>(0h0), _atomics_legal_T_151) node _atomics_legal_T_176 = or(_atomics_legal_T_175, _atomics_legal_T_158) node atomics_legal_2 = or(_atomics_legal_T_176, _atomics_legal_T_174) wire atomics_a_2 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_2.opcode, UInt<2>(0h3) connect atomics_a_2.param, UInt<3>(0h1) connect atomics_a_2.size, req.uop.mem_size connect atomics_a_2.source, UInt<3>(0h5) connect atomics_a_2.address, req.addr node _atomics_a_mask_sizeOH_T_6 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_2 = bits(_atomics_a_mask_sizeOH_T_6, 1, 0) node _atomics_a_mask_sizeOH_T_7 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_2) node _atomics_a_mask_sizeOH_T_8 = bits(_atomics_a_mask_sizeOH_T_7, 3, 0) node atomics_a_mask_sizeOH_2 = or(_atomics_a_mask_sizeOH_T_8, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_2 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 3, 3) node atomics_a_mask_sub_sub_sub_bit_2 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_2 = eq(atomics_a_mask_sub_sub_sub_bit_2, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_2) node _atomics_a_mask_sub_sub_sub_acc_T_4 = and(atomics_a_mask_sub_sub_sub_size_2, atomics_a_mask_sub_sub_sub_0_2_2) node atomics_a_mask_sub_sub_sub_0_1_2 = or(atomics_a_mask_sub_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_sub_acc_T_4) node atomics_a_mask_sub_sub_sub_1_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_2) node _atomics_a_mask_sub_sub_sub_acc_T_5 = and(atomics_a_mask_sub_sub_sub_size_2, atomics_a_mask_sub_sub_sub_1_2_2) node atomics_a_mask_sub_sub_sub_1_1_2 = or(atomics_a_mask_sub_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_sub_acc_T_5) node atomics_a_mask_sub_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 2, 2) node atomics_a_mask_sub_sub_bit_2 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_2 = eq(atomics_a_mask_sub_sub_bit_2, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_2 = and(atomics_a_mask_sub_sub_sub_0_2_2, atomics_a_mask_sub_sub_nbit_2) node _atomics_a_mask_sub_sub_acc_T_8 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_0_2_2) node atomics_a_mask_sub_sub_0_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_8) node atomics_a_mask_sub_sub_1_2_2 = and(atomics_a_mask_sub_sub_sub_0_2_2, atomics_a_mask_sub_sub_bit_2) node _atomics_a_mask_sub_sub_acc_T_9 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_1_2_2) node atomics_a_mask_sub_sub_1_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_9) node atomics_a_mask_sub_sub_2_2_2 = and(atomics_a_mask_sub_sub_sub_1_2_2, atomics_a_mask_sub_sub_nbit_2) node _atomics_a_mask_sub_sub_acc_T_10 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_2_2_2) node atomics_a_mask_sub_sub_2_1_2 = or(atomics_a_mask_sub_sub_sub_1_1_2, _atomics_a_mask_sub_sub_acc_T_10) node atomics_a_mask_sub_sub_3_2_2 = and(atomics_a_mask_sub_sub_sub_1_2_2, atomics_a_mask_sub_sub_bit_2) node _atomics_a_mask_sub_sub_acc_T_11 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_3_2_2) node atomics_a_mask_sub_sub_3_1_2 = or(atomics_a_mask_sub_sub_sub_1_1_2, _atomics_a_mask_sub_sub_acc_T_11) node atomics_a_mask_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 1, 1) node atomics_a_mask_sub_bit_2 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_2 = eq(atomics_a_mask_sub_bit_2, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_nbit_2) node _atomics_a_mask_sub_acc_T_16 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_0_2_2) node atomics_a_mask_sub_0_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_16) node atomics_a_mask_sub_1_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_bit_2) node _atomics_a_mask_sub_acc_T_17 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_1_2_2) node atomics_a_mask_sub_1_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_17) node atomics_a_mask_sub_2_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_nbit_2) node _atomics_a_mask_sub_acc_T_18 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_2_2_2) node atomics_a_mask_sub_2_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_18) node atomics_a_mask_sub_3_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_bit_2) node _atomics_a_mask_sub_acc_T_19 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_3_2_2) node atomics_a_mask_sub_3_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_19) node atomics_a_mask_sub_4_2_2 = and(atomics_a_mask_sub_sub_2_2_2, atomics_a_mask_sub_nbit_2) node _atomics_a_mask_sub_acc_T_20 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_4_2_2) node atomics_a_mask_sub_4_1_2 = or(atomics_a_mask_sub_sub_2_1_2, _atomics_a_mask_sub_acc_T_20) node atomics_a_mask_sub_5_2_2 = and(atomics_a_mask_sub_sub_2_2_2, atomics_a_mask_sub_bit_2) node _atomics_a_mask_sub_acc_T_21 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_5_2_2) node atomics_a_mask_sub_5_1_2 = or(atomics_a_mask_sub_sub_2_1_2, _atomics_a_mask_sub_acc_T_21) node atomics_a_mask_sub_6_2_2 = and(atomics_a_mask_sub_sub_3_2_2, atomics_a_mask_sub_nbit_2) node _atomics_a_mask_sub_acc_T_22 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_6_2_2) node atomics_a_mask_sub_6_1_2 = or(atomics_a_mask_sub_sub_3_1_2, _atomics_a_mask_sub_acc_T_22) node atomics_a_mask_sub_7_2_2 = and(atomics_a_mask_sub_sub_3_2_2, atomics_a_mask_sub_bit_2) node _atomics_a_mask_sub_acc_T_23 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_7_2_2) node atomics_a_mask_sub_7_1_2 = or(atomics_a_mask_sub_sub_3_1_2, _atomics_a_mask_sub_acc_T_23) node atomics_a_mask_size_2 = bits(atomics_a_mask_sizeOH_2, 0, 0) node atomics_a_mask_bit_2 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_2 = eq(atomics_a_mask_bit_2, UInt<1>(0h0)) node atomics_a_mask_eq_32 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_32 = and(atomics_a_mask_size_2, atomics_a_mask_eq_32) node atomics_a_mask_acc_32 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_32) node atomics_a_mask_eq_33 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_33 = and(atomics_a_mask_size_2, atomics_a_mask_eq_33) node atomics_a_mask_acc_33 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_33) node atomics_a_mask_eq_34 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_34 = and(atomics_a_mask_size_2, atomics_a_mask_eq_34) node atomics_a_mask_acc_34 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_34) node atomics_a_mask_eq_35 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_35 = and(atomics_a_mask_size_2, atomics_a_mask_eq_35) node atomics_a_mask_acc_35 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_35) node atomics_a_mask_eq_36 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_36 = and(atomics_a_mask_size_2, atomics_a_mask_eq_36) node atomics_a_mask_acc_36 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_36) node atomics_a_mask_eq_37 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_37 = and(atomics_a_mask_size_2, atomics_a_mask_eq_37) node atomics_a_mask_acc_37 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_37) node atomics_a_mask_eq_38 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_38 = and(atomics_a_mask_size_2, atomics_a_mask_eq_38) node atomics_a_mask_acc_38 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_38) node atomics_a_mask_eq_39 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_39 = and(atomics_a_mask_size_2, atomics_a_mask_eq_39) node atomics_a_mask_acc_39 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_39) node atomics_a_mask_eq_40 = and(atomics_a_mask_sub_4_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_40 = and(atomics_a_mask_size_2, atomics_a_mask_eq_40) node atomics_a_mask_acc_40 = or(atomics_a_mask_sub_4_1_2, _atomics_a_mask_acc_T_40) node atomics_a_mask_eq_41 = and(atomics_a_mask_sub_4_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_41 = and(atomics_a_mask_size_2, atomics_a_mask_eq_41) node atomics_a_mask_acc_41 = or(atomics_a_mask_sub_4_1_2, _atomics_a_mask_acc_T_41) node atomics_a_mask_eq_42 = and(atomics_a_mask_sub_5_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_42 = and(atomics_a_mask_size_2, atomics_a_mask_eq_42) node atomics_a_mask_acc_42 = or(atomics_a_mask_sub_5_1_2, _atomics_a_mask_acc_T_42) node atomics_a_mask_eq_43 = and(atomics_a_mask_sub_5_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_43 = and(atomics_a_mask_size_2, atomics_a_mask_eq_43) node atomics_a_mask_acc_43 = or(atomics_a_mask_sub_5_1_2, _atomics_a_mask_acc_T_43) node atomics_a_mask_eq_44 = and(atomics_a_mask_sub_6_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_44 = and(atomics_a_mask_size_2, atomics_a_mask_eq_44) node atomics_a_mask_acc_44 = or(atomics_a_mask_sub_6_1_2, _atomics_a_mask_acc_T_44) node atomics_a_mask_eq_45 = and(atomics_a_mask_sub_6_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_45 = and(atomics_a_mask_size_2, atomics_a_mask_eq_45) node atomics_a_mask_acc_45 = or(atomics_a_mask_sub_6_1_2, _atomics_a_mask_acc_T_45) node atomics_a_mask_eq_46 = and(atomics_a_mask_sub_7_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_46 = and(atomics_a_mask_size_2, atomics_a_mask_eq_46) node atomics_a_mask_acc_46 = or(atomics_a_mask_sub_7_1_2, _atomics_a_mask_acc_T_46) node atomics_a_mask_eq_47 = and(atomics_a_mask_sub_7_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_47 = and(atomics_a_mask_size_2, atomics_a_mask_eq_47) node atomics_a_mask_acc_47 = or(atomics_a_mask_sub_7_1_2, _atomics_a_mask_acc_T_47) node atomics_a_mask_lo_lo_lo_2 = cat(atomics_a_mask_acc_33, atomics_a_mask_acc_32) node atomics_a_mask_lo_lo_hi_2 = cat(atomics_a_mask_acc_35, atomics_a_mask_acc_34) node atomics_a_mask_lo_lo_2 = cat(atomics_a_mask_lo_lo_hi_2, atomics_a_mask_lo_lo_lo_2) node atomics_a_mask_lo_hi_lo_2 = cat(atomics_a_mask_acc_37, atomics_a_mask_acc_36) node atomics_a_mask_lo_hi_hi_2 = cat(atomics_a_mask_acc_39, atomics_a_mask_acc_38) node atomics_a_mask_lo_hi_2 = cat(atomics_a_mask_lo_hi_hi_2, atomics_a_mask_lo_hi_lo_2) node atomics_a_mask_lo_2 = cat(atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2) node atomics_a_mask_hi_lo_lo_2 = cat(atomics_a_mask_acc_41, atomics_a_mask_acc_40) node atomics_a_mask_hi_lo_hi_2 = cat(atomics_a_mask_acc_43, atomics_a_mask_acc_42) node atomics_a_mask_hi_lo_2 = cat(atomics_a_mask_hi_lo_hi_2, atomics_a_mask_hi_lo_lo_2) node atomics_a_mask_hi_hi_lo_2 = cat(atomics_a_mask_acc_45, atomics_a_mask_acc_44) node atomics_a_mask_hi_hi_hi_2 = cat(atomics_a_mask_acc_47, atomics_a_mask_acc_46) node atomics_a_mask_hi_hi_2 = cat(atomics_a_mask_hi_hi_hi_2, atomics_a_mask_hi_hi_lo_2) node atomics_a_mask_hi_2 = cat(atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2) node _atomics_a_mask_T_2 = cat(atomics_a_mask_hi_2, atomics_a_mask_lo_2) connect atomics_a_2.mask, _atomics_a_mask_T_2 connect atomics_a_2.data, a_data connect atomics_a_2.corrupt, UInt<1>(0h0) node _atomics_legal_T_177 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_178 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_179 = and(_atomics_legal_T_177, _atomics_legal_T_178) node _atomics_legal_T_180 = or(UInt<1>(0h0), _atomics_legal_T_179) node _atomics_legal_T_181 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_182 = cvt(_atomics_legal_T_181) node _atomics_legal_T_183 = and(_atomics_legal_T_182, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_184 = asSInt(_atomics_legal_T_183) node _atomics_legal_T_185 = eq(_atomics_legal_T_184, asSInt(UInt<1>(0h0))) node _atomics_legal_T_186 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_187 = cvt(_atomics_legal_T_186) node _atomics_legal_T_188 = and(_atomics_legal_T_187, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_189 = asSInt(_atomics_legal_T_188) node _atomics_legal_T_190 = eq(_atomics_legal_T_189, asSInt(UInt<1>(0h0))) node _atomics_legal_T_191 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_192 = cvt(_atomics_legal_T_191) node _atomics_legal_T_193 = and(_atomics_legal_T_192, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_194 = asSInt(_atomics_legal_T_193) node _atomics_legal_T_195 = eq(_atomics_legal_T_194, asSInt(UInt<1>(0h0))) node _atomics_legal_T_196 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_197 = cvt(_atomics_legal_T_196) node _atomics_legal_T_198 = and(_atomics_legal_T_197, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_199 = asSInt(_atomics_legal_T_198) node _atomics_legal_T_200 = eq(_atomics_legal_T_199, asSInt(UInt<1>(0h0))) node _atomics_legal_T_201 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_202 = cvt(_atomics_legal_T_201) node _atomics_legal_T_203 = and(_atomics_legal_T_202, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_204 = asSInt(_atomics_legal_T_203) node _atomics_legal_T_205 = eq(_atomics_legal_T_204, asSInt(UInt<1>(0h0))) node _atomics_legal_T_206 = or(_atomics_legal_T_185, _atomics_legal_T_190) node _atomics_legal_T_207 = or(_atomics_legal_T_206, _atomics_legal_T_195) node _atomics_legal_T_208 = or(_atomics_legal_T_207, _atomics_legal_T_200) node _atomics_legal_T_209 = or(_atomics_legal_T_208, _atomics_legal_T_205) node _atomics_legal_T_210 = and(_atomics_legal_T_180, _atomics_legal_T_209) node _atomics_legal_T_211 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_212 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_213 = cvt(_atomics_legal_T_212) node _atomics_legal_T_214 = and(_atomics_legal_T_213, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_215 = asSInt(_atomics_legal_T_214) node _atomics_legal_T_216 = eq(_atomics_legal_T_215, asSInt(UInt<1>(0h0))) node _atomics_legal_T_217 = and(_atomics_legal_T_211, _atomics_legal_T_216) node _atomics_legal_T_218 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_219 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_220 = and(_atomics_legal_T_218, _atomics_legal_T_219) node _atomics_legal_T_221 = or(UInt<1>(0h0), _atomics_legal_T_220) node _atomics_legal_T_222 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_223 = cvt(_atomics_legal_T_222) node _atomics_legal_T_224 = and(_atomics_legal_T_223, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_225 = asSInt(_atomics_legal_T_224) node _atomics_legal_T_226 = eq(_atomics_legal_T_225, asSInt(UInt<1>(0h0))) node _atomics_legal_T_227 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_228 = cvt(_atomics_legal_T_227) node _atomics_legal_T_229 = and(_atomics_legal_T_228, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_230 = asSInt(_atomics_legal_T_229) node _atomics_legal_T_231 = eq(_atomics_legal_T_230, asSInt(UInt<1>(0h0))) node _atomics_legal_T_232 = or(_atomics_legal_T_226, _atomics_legal_T_231) node _atomics_legal_T_233 = and(_atomics_legal_T_221, _atomics_legal_T_232) node _atomics_legal_T_234 = or(UInt<1>(0h0), _atomics_legal_T_210) node _atomics_legal_T_235 = or(_atomics_legal_T_234, _atomics_legal_T_217) node atomics_legal_3 = or(_atomics_legal_T_235, _atomics_legal_T_233) wire atomics_a_3 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_3.opcode, UInt<2>(0h3) connect atomics_a_3.param, UInt<3>(0h2) connect atomics_a_3.size, req.uop.mem_size connect atomics_a_3.source, UInt<3>(0h5) connect atomics_a_3.address, req.addr node _atomics_a_mask_sizeOH_T_9 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_3 = bits(_atomics_a_mask_sizeOH_T_9, 1, 0) node _atomics_a_mask_sizeOH_T_10 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_3) node _atomics_a_mask_sizeOH_T_11 = bits(_atomics_a_mask_sizeOH_T_10, 3, 0) node atomics_a_mask_sizeOH_3 = or(_atomics_a_mask_sizeOH_T_11, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_3 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 3, 3) node atomics_a_mask_sub_sub_sub_bit_3 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_3 = eq(atomics_a_mask_sub_sub_sub_bit_3, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_3) node _atomics_a_mask_sub_sub_sub_acc_T_6 = and(atomics_a_mask_sub_sub_sub_size_3, atomics_a_mask_sub_sub_sub_0_2_3) node atomics_a_mask_sub_sub_sub_0_1_3 = or(atomics_a_mask_sub_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_sub_acc_T_6) node atomics_a_mask_sub_sub_sub_1_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_3) node _atomics_a_mask_sub_sub_sub_acc_T_7 = and(atomics_a_mask_sub_sub_sub_size_3, atomics_a_mask_sub_sub_sub_1_2_3) node atomics_a_mask_sub_sub_sub_1_1_3 = or(atomics_a_mask_sub_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_sub_acc_T_7) node atomics_a_mask_sub_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 2, 2) node atomics_a_mask_sub_sub_bit_3 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_3 = eq(atomics_a_mask_sub_sub_bit_3, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_3 = and(atomics_a_mask_sub_sub_sub_0_2_3, atomics_a_mask_sub_sub_nbit_3) node _atomics_a_mask_sub_sub_acc_T_12 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_0_2_3) node atomics_a_mask_sub_sub_0_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_12) node atomics_a_mask_sub_sub_1_2_3 = and(atomics_a_mask_sub_sub_sub_0_2_3, atomics_a_mask_sub_sub_bit_3) node _atomics_a_mask_sub_sub_acc_T_13 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_1_2_3) node atomics_a_mask_sub_sub_1_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_13) node atomics_a_mask_sub_sub_2_2_3 = and(atomics_a_mask_sub_sub_sub_1_2_3, atomics_a_mask_sub_sub_nbit_3) node _atomics_a_mask_sub_sub_acc_T_14 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_2_2_3) node atomics_a_mask_sub_sub_2_1_3 = or(atomics_a_mask_sub_sub_sub_1_1_3, _atomics_a_mask_sub_sub_acc_T_14) node atomics_a_mask_sub_sub_3_2_3 = and(atomics_a_mask_sub_sub_sub_1_2_3, atomics_a_mask_sub_sub_bit_3) node _atomics_a_mask_sub_sub_acc_T_15 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_3_2_3) node atomics_a_mask_sub_sub_3_1_3 = or(atomics_a_mask_sub_sub_sub_1_1_3, _atomics_a_mask_sub_sub_acc_T_15) node atomics_a_mask_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 1, 1) node atomics_a_mask_sub_bit_3 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_3 = eq(atomics_a_mask_sub_bit_3, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_nbit_3) node _atomics_a_mask_sub_acc_T_24 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_0_2_3) node atomics_a_mask_sub_0_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_24) node atomics_a_mask_sub_1_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_bit_3) node _atomics_a_mask_sub_acc_T_25 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_1_2_3) node atomics_a_mask_sub_1_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_25) node atomics_a_mask_sub_2_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_nbit_3) node _atomics_a_mask_sub_acc_T_26 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_2_2_3) node atomics_a_mask_sub_2_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_26) node atomics_a_mask_sub_3_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_bit_3) node _atomics_a_mask_sub_acc_T_27 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_3_2_3) node atomics_a_mask_sub_3_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_27) node atomics_a_mask_sub_4_2_3 = and(atomics_a_mask_sub_sub_2_2_3, atomics_a_mask_sub_nbit_3) node _atomics_a_mask_sub_acc_T_28 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_4_2_3) node atomics_a_mask_sub_4_1_3 = or(atomics_a_mask_sub_sub_2_1_3, _atomics_a_mask_sub_acc_T_28) node atomics_a_mask_sub_5_2_3 = and(atomics_a_mask_sub_sub_2_2_3, atomics_a_mask_sub_bit_3) node _atomics_a_mask_sub_acc_T_29 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_5_2_3) node atomics_a_mask_sub_5_1_3 = or(atomics_a_mask_sub_sub_2_1_3, _atomics_a_mask_sub_acc_T_29) node atomics_a_mask_sub_6_2_3 = and(atomics_a_mask_sub_sub_3_2_3, atomics_a_mask_sub_nbit_3) node _atomics_a_mask_sub_acc_T_30 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_6_2_3) node atomics_a_mask_sub_6_1_3 = or(atomics_a_mask_sub_sub_3_1_3, _atomics_a_mask_sub_acc_T_30) node atomics_a_mask_sub_7_2_3 = and(atomics_a_mask_sub_sub_3_2_3, atomics_a_mask_sub_bit_3) node _atomics_a_mask_sub_acc_T_31 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_7_2_3) node atomics_a_mask_sub_7_1_3 = or(atomics_a_mask_sub_sub_3_1_3, _atomics_a_mask_sub_acc_T_31) node atomics_a_mask_size_3 = bits(atomics_a_mask_sizeOH_3, 0, 0) node atomics_a_mask_bit_3 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_3 = eq(atomics_a_mask_bit_3, UInt<1>(0h0)) node atomics_a_mask_eq_48 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_48 = and(atomics_a_mask_size_3, atomics_a_mask_eq_48) node atomics_a_mask_acc_48 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_48) node atomics_a_mask_eq_49 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_49 = and(atomics_a_mask_size_3, atomics_a_mask_eq_49) node atomics_a_mask_acc_49 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_49) node atomics_a_mask_eq_50 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_50 = and(atomics_a_mask_size_3, atomics_a_mask_eq_50) node atomics_a_mask_acc_50 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_50) node atomics_a_mask_eq_51 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_51 = and(atomics_a_mask_size_3, atomics_a_mask_eq_51) node atomics_a_mask_acc_51 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_51) node atomics_a_mask_eq_52 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_52 = and(atomics_a_mask_size_3, atomics_a_mask_eq_52) node atomics_a_mask_acc_52 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_52) node atomics_a_mask_eq_53 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_53 = and(atomics_a_mask_size_3, atomics_a_mask_eq_53) node atomics_a_mask_acc_53 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_53) node atomics_a_mask_eq_54 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_54 = and(atomics_a_mask_size_3, atomics_a_mask_eq_54) node atomics_a_mask_acc_54 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_54) node atomics_a_mask_eq_55 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_55 = and(atomics_a_mask_size_3, atomics_a_mask_eq_55) node atomics_a_mask_acc_55 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_55) node atomics_a_mask_eq_56 = and(atomics_a_mask_sub_4_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_56 = and(atomics_a_mask_size_3, atomics_a_mask_eq_56) node atomics_a_mask_acc_56 = or(atomics_a_mask_sub_4_1_3, _atomics_a_mask_acc_T_56) node atomics_a_mask_eq_57 = and(atomics_a_mask_sub_4_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_57 = and(atomics_a_mask_size_3, atomics_a_mask_eq_57) node atomics_a_mask_acc_57 = or(atomics_a_mask_sub_4_1_3, _atomics_a_mask_acc_T_57) node atomics_a_mask_eq_58 = and(atomics_a_mask_sub_5_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_58 = and(atomics_a_mask_size_3, atomics_a_mask_eq_58) node atomics_a_mask_acc_58 = or(atomics_a_mask_sub_5_1_3, _atomics_a_mask_acc_T_58) node atomics_a_mask_eq_59 = and(atomics_a_mask_sub_5_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_59 = and(atomics_a_mask_size_3, atomics_a_mask_eq_59) node atomics_a_mask_acc_59 = or(atomics_a_mask_sub_5_1_3, _atomics_a_mask_acc_T_59) node atomics_a_mask_eq_60 = and(atomics_a_mask_sub_6_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_60 = and(atomics_a_mask_size_3, atomics_a_mask_eq_60) node atomics_a_mask_acc_60 = or(atomics_a_mask_sub_6_1_3, _atomics_a_mask_acc_T_60) node atomics_a_mask_eq_61 = and(atomics_a_mask_sub_6_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_61 = and(atomics_a_mask_size_3, atomics_a_mask_eq_61) node atomics_a_mask_acc_61 = or(atomics_a_mask_sub_6_1_3, _atomics_a_mask_acc_T_61) node atomics_a_mask_eq_62 = and(atomics_a_mask_sub_7_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_62 = and(atomics_a_mask_size_3, atomics_a_mask_eq_62) node atomics_a_mask_acc_62 = or(atomics_a_mask_sub_7_1_3, _atomics_a_mask_acc_T_62) node atomics_a_mask_eq_63 = and(atomics_a_mask_sub_7_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_63 = and(atomics_a_mask_size_3, atomics_a_mask_eq_63) node atomics_a_mask_acc_63 = or(atomics_a_mask_sub_7_1_3, _atomics_a_mask_acc_T_63) node atomics_a_mask_lo_lo_lo_3 = cat(atomics_a_mask_acc_49, atomics_a_mask_acc_48) node atomics_a_mask_lo_lo_hi_3 = cat(atomics_a_mask_acc_51, atomics_a_mask_acc_50) node atomics_a_mask_lo_lo_3 = cat(atomics_a_mask_lo_lo_hi_3, atomics_a_mask_lo_lo_lo_3) node atomics_a_mask_lo_hi_lo_3 = cat(atomics_a_mask_acc_53, atomics_a_mask_acc_52) node atomics_a_mask_lo_hi_hi_3 = cat(atomics_a_mask_acc_55, atomics_a_mask_acc_54) node atomics_a_mask_lo_hi_3 = cat(atomics_a_mask_lo_hi_hi_3, atomics_a_mask_lo_hi_lo_3) node atomics_a_mask_lo_3 = cat(atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3) node atomics_a_mask_hi_lo_lo_3 = cat(atomics_a_mask_acc_57, atomics_a_mask_acc_56) node atomics_a_mask_hi_lo_hi_3 = cat(atomics_a_mask_acc_59, atomics_a_mask_acc_58) node atomics_a_mask_hi_lo_3 = cat(atomics_a_mask_hi_lo_hi_3, atomics_a_mask_hi_lo_lo_3) node atomics_a_mask_hi_hi_lo_3 = cat(atomics_a_mask_acc_61, atomics_a_mask_acc_60) node atomics_a_mask_hi_hi_hi_3 = cat(atomics_a_mask_acc_63, atomics_a_mask_acc_62) node atomics_a_mask_hi_hi_3 = cat(atomics_a_mask_hi_hi_hi_3, atomics_a_mask_hi_hi_lo_3) node atomics_a_mask_hi_3 = cat(atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3) node _atomics_a_mask_T_3 = cat(atomics_a_mask_hi_3, atomics_a_mask_lo_3) connect atomics_a_3.mask, _atomics_a_mask_T_3 connect atomics_a_3.data, a_data connect atomics_a_3.corrupt, UInt<1>(0h0) node _atomics_legal_T_236 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_237 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_238 = and(_atomics_legal_T_236, _atomics_legal_T_237) node _atomics_legal_T_239 = or(UInt<1>(0h0), _atomics_legal_T_238) node _atomics_legal_T_240 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_241 = cvt(_atomics_legal_T_240) node _atomics_legal_T_242 = and(_atomics_legal_T_241, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_243 = asSInt(_atomics_legal_T_242) node _atomics_legal_T_244 = eq(_atomics_legal_T_243, asSInt(UInt<1>(0h0))) node _atomics_legal_T_245 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_246 = cvt(_atomics_legal_T_245) node _atomics_legal_T_247 = and(_atomics_legal_T_246, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_248 = asSInt(_atomics_legal_T_247) node _atomics_legal_T_249 = eq(_atomics_legal_T_248, asSInt(UInt<1>(0h0))) node _atomics_legal_T_250 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_251 = cvt(_atomics_legal_T_250) node _atomics_legal_T_252 = and(_atomics_legal_T_251, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_253 = asSInt(_atomics_legal_T_252) node _atomics_legal_T_254 = eq(_atomics_legal_T_253, asSInt(UInt<1>(0h0))) node _atomics_legal_T_255 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_256 = cvt(_atomics_legal_T_255) node _atomics_legal_T_257 = and(_atomics_legal_T_256, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_258 = asSInt(_atomics_legal_T_257) node _atomics_legal_T_259 = eq(_atomics_legal_T_258, asSInt(UInt<1>(0h0))) node _atomics_legal_T_260 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_261 = cvt(_atomics_legal_T_260) node _atomics_legal_T_262 = and(_atomics_legal_T_261, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_263 = asSInt(_atomics_legal_T_262) node _atomics_legal_T_264 = eq(_atomics_legal_T_263, asSInt(UInt<1>(0h0))) node _atomics_legal_T_265 = or(_atomics_legal_T_244, _atomics_legal_T_249) node _atomics_legal_T_266 = or(_atomics_legal_T_265, _atomics_legal_T_254) node _atomics_legal_T_267 = or(_atomics_legal_T_266, _atomics_legal_T_259) node _atomics_legal_T_268 = or(_atomics_legal_T_267, _atomics_legal_T_264) node _atomics_legal_T_269 = and(_atomics_legal_T_239, _atomics_legal_T_268) node _atomics_legal_T_270 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_271 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_272 = cvt(_atomics_legal_T_271) node _atomics_legal_T_273 = and(_atomics_legal_T_272, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_274 = asSInt(_atomics_legal_T_273) node _atomics_legal_T_275 = eq(_atomics_legal_T_274, asSInt(UInt<1>(0h0))) node _atomics_legal_T_276 = and(_atomics_legal_T_270, _atomics_legal_T_275) node _atomics_legal_T_277 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_278 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_279 = and(_atomics_legal_T_277, _atomics_legal_T_278) node _atomics_legal_T_280 = or(UInt<1>(0h0), _atomics_legal_T_279) node _atomics_legal_T_281 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_282 = cvt(_atomics_legal_T_281) node _atomics_legal_T_283 = and(_atomics_legal_T_282, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_284 = asSInt(_atomics_legal_T_283) node _atomics_legal_T_285 = eq(_atomics_legal_T_284, asSInt(UInt<1>(0h0))) node _atomics_legal_T_286 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_287 = cvt(_atomics_legal_T_286) node _atomics_legal_T_288 = and(_atomics_legal_T_287, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_289 = asSInt(_atomics_legal_T_288) node _atomics_legal_T_290 = eq(_atomics_legal_T_289, asSInt(UInt<1>(0h0))) node _atomics_legal_T_291 = or(_atomics_legal_T_285, _atomics_legal_T_290) node _atomics_legal_T_292 = and(_atomics_legal_T_280, _atomics_legal_T_291) node _atomics_legal_T_293 = or(UInt<1>(0h0), _atomics_legal_T_269) node _atomics_legal_T_294 = or(_atomics_legal_T_293, _atomics_legal_T_276) node atomics_legal_4 = or(_atomics_legal_T_294, _atomics_legal_T_292) wire atomics_a_4 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_4.opcode, UInt<2>(0h2) connect atomics_a_4.param, UInt<3>(0h4) connect atomics_a_4.size, req.uop.mem_size connect atomics_a_4.source, UInt<3>(0h5) connect atomics_a_4.address, req.addr node _atomics_a_mask_sizeOH_T_12 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_4 = bits(_atomics_a_mask_sizeOH_T_12, 1, 0) node _atomics_a_mask_sizeOH_T_13 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_4) node _atomics_a_mask_sizeOH_T_14 = bits(_atomics_a_mask_sizeOH_T_13, 3, 0) node atomics_a_mask_sizeOH_4 = or(_atomics_a_mask_sizeOH_T_14, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_4 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 3, 3) node atomics_a_mask_sub_sub_sub_bit_4 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_4 = eq(atomics_a_mask_sub_sub_sub_bit_4, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_4) node _atomics_a_mask_sub_sub_sub_acc_T_8 = and(atomics_a_mask_sub_sub_sub_size_4, atomics_a_mask_sub_sub_sub_0_2_4) node atomics_a_mask_sub_sub_sub_0_1_4 = or(atomics_a_mask_sub_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_sub_acc_T_8) node atomics_a_mask_sub_sub_sub_1_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_4) node _atomics_a_mask_sub_sub_sub_acc_T_9 = and(atomics_a_mask_sub_sub_sub_size_4, atomics_a_mask_sub_sub_sub_1_2_4) node atomics_a_mask_sub_sub_sub_1_1_4 = or(atomics_a_mask_sub_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_sub_acc_T_9) node atomics_a_mask_sub_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 2, 2) node atomics_a_mask_sub_sub_bit_4 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_4 = eq(atomics_a_mask_sub_sub_bit_4, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_4 = and(atomics_a_mask_sub_sub_sub_0_2_4, atomics_a_mask_sub_sub_nbit_4) node _atomics_a_mask_sub_sub_acc_T_16 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_0_2_4) node atomics_a_mask_sub_sub_0_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_16) node atomics_a_mask_sub_sub_1_2_4 = and(atomics_a_mask_sub_sub_sub_0_2_4, atomics_a_mask_sub_sub_bit_4) node _atomics_a_mask_sub_sub_acc_T_17 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_1_2_4) node atomics_a_mask_sub_sub_1_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_17) node atomics_a_mask_sub_sub_2_2_4 = and(atomics_a_mask_sub_sub_sub_1_2_4, atomics_a_mask_sub_sub_nbit_4) node _atomics_a_mask_sub_sub_acc_T_18 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_2_2_4) node atomics_a_mask_sub_sub_2_1_4 = or(atomics_a_mask_sub_sub_sub_1_1_4, _atomics_a_mask_sub_sub_acc_T_18) node atomics_a_mask_sub_sub_3_2_4 = and(atomics_a_mask_sub_sub_sub_1_2_4, atomics_a_mask_sub_sub_bit_4) node _atomics_a_mask_sub_sub_acc_T_19 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_3_2_4) node atomics_a_mask_sub_sub_3_1_4 = or(atomics_a_mask_sub_sub_sub_1_1_4, _atomics_a_mask_sub_sub_acc_T_19) node atomics_a_mask_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 1, 1) node atomics_a_mask_sub_bit_4 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_4 = eq(atomics_a_mask_sub_bit_4, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_nbit_4) node _atomics_a_mask_sub_acc_T_32 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_0_2_4) node atomics_a_mask_sub_0_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_32) node atomics_a_mask_sub_1_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_bit_4) node _atomics_a_mask_sub_acc_T_33 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_1_2_4) node atomics_a_mask_sub_1_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_33) node atomics_a_mask_sub_2_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_nbit_4) node _atomics_a_mask_sub_acc_T_34 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_2_2_4) node atomics_a_mask_sub_2_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_34) node atomics_a_mask_sub_3_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_bit_4) node _atomics_a_mask_sub_acc_T_35 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_3_2_4) node atomics_a_mask_sub_3_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_35) node atomics_a_mask_sub_4_2_4 = and(atomics_a_mask_sub_sub_2_2_4, atomics_a_mask_sub_nbit_4) node _atomics_a_mask_sub_acc_T_36 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_4_2_4) node atomics_a_mask_sub_4_1_4 = or(atomics_a_mask_sub_sub_2_1_4, _atomics_a_mask_sub_acc_T_36) node atomics_a_mask_sub_5_2_4 = and(atomics_a_mask_sub_sub_2_2_4, atomics_a_mask_sub_bit_4) node _atomics_a_mask_sub_acc_T_37 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_5_2_4) node atomics_a_mask_sub_5_1_4 = or(atomics_a_mask_sub_sub_2_1_4, _atomics_a_mask_sub_acc_T_37) node atomics_a_mask_sub_6_2_4 = and(atomics_a_mask_sub_sub_3_2_4, atomics_a_mask_sub_nbit_4) node _atomics_a_mask_sub_acc_T_38 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_6_2_4) node atomics_a_mask_sub_6_1_4 = or(atomics_a_mask_sub_sub_3_1_4, _atomics_a_mask_sub_acc_T_38) node atomics_a_mask_sub_7_2_4 = and(atomics_a_mask_sub_sub_3_2_4, atomics_a_mask_sub_bit_4) node _atomics_a_mask_sub_acc_T_39 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_7_2_4) node atomics_a_mask_sub_7_1_4 = or(atomics_a_mask_sub_sub_3_1_4, _atomics_a_mask_sub_acc_T_39) node atomics_a_mask_size_4 = bits(atomics_a_mask_sizeOH_4, 0, 0) node atomics_a_mask_bit_4 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_4 = eq(atomics_a_mask_bit_4, UInt<1>(0h0)) node atomics_a_mask_eq_64 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_64 = and(atomics_a_mask_size_4, atomics_a_mask_eq_64) node atomics_a_mask_acc_64 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_64) node atomics_a_mask_eq_65 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_65 = and(atomics_a_mask_size_4, atomics_a_mask_eq_65) node atomics_a_mask_acc_65 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_65) node atomics_a_mask_eq_66 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_66 = and(atomics_a_mask_size_4, atomics_a_mask_eq_66) node atomics_a_mask_acc_66 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_66) node atomics_a_mask_eq_67 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_67 = and(atomics_a_mask_size_4, atomics_a_mask_eq_67) node atomics_a_mask_acc_67 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_67) node atomics_a_mask_eq_68 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_68 = and(atomics_a_mask_size_4, atomics_a_mask_eq_68) node atomics_a_mask_acc_68 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_68) node atomics_a_mask_eq_69 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_69 = and(atomics_a_mask_size_4, atomics_a_mask_eq_69) node atomics_a_mask_acc_69 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_69) node atomics_a_mask_eq_70 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_70 = and(atomics_a_mask_size_4, atomics_a_mask_eq_70) node atomics_a_mask_acc_70 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_70) node atomics_a_mask_eq_71 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_71 = and(atomics_a_mask_size_4, atomics_a_mask_eq_71) node atomics_a_mask_acc_71 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_71) node atomics_a_mask_eq_72 = and(atomics_a_mask_sub_4_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_72 = and(atomics_a_mask_size_4, atomics_a_mask_eq_72) node atomics_a_mask_acc_72 = or(atomics_a_mask_sub_4_1_4, _atomics_a_mask_acc_T_72) node atomics_a_mask_eq_73 = and(atomics_a_mask_sub_4_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_73 = and(atomics_a_mask_size_4, atomics_a_mask_eq_73) node atomics_a_mask_acc_73 = or(atomics_a_mask_sub_4_1_4, _atomics_a_mask_acc_T_73) node atomics_a_mask_eq_74 = and(atomics_a_mask_sub_5_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_74 = and(atomics_a_mask_size_4, atomics_a_mask_eq_74) node atomics_a_mask_acc_74 = or(atomics_a_mask_sub_5_1_4, _atomics_a_mask_acc_T_74) node atomics_a_mask_eq_75 = and(atomics_a_mask_sub_5_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_75 = and(atomics_a_mask_size_4, atomics_a_mask_eq_75) node atomics_a_mask_acc_75 = or(atomics_a_mask_sub_5_1_4, _atomics_a_mask_acc_T_75) node atomics_a_mask_eq_76 = and(atomics_a_mask_sub_6_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_76 = and(atomics_a_mask_size_4, atomics_a_mask_eq_76) node atomics_a_mask_acc_76 = or(atomics_a_mask_sub_6_1_4, _atomics_a_mask_acc_T_76) node atomics_a_mask_eq_77 = and(atomics_a_mask_sub_6_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_77 = and(atomics_a_mask_size_4, atomics_a_mask_eq_77) node atomics_a_mask_acc_77 = or(atomics_a_mask_sub_6_1_4, _atomics_a_mask_acc_T_77) node atomics_a_mask_eq_78 = and(atomics_a_mask_sub_7_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_78 = and(atomics_a_mask_size_4, atomics_a_mask_eq_78) node atomics_a_mask_acc_78 = or(atomics_a_mask_sub_7_1_4, _atomics_a_mask_acc_T_78) node atomics_a_mask_eq_79 = and(atomics_a_mask_sub_7_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_79 = and(atomics_a_mask_size_4, atomics_a_mask_eq_79) node atomics_a_mask_acc_79 = or(atomics_a_mask_sub_7_1_4, _atomics_a_mask_acc_T_79) node atomics_a_mask_lo_lo_lo_4 = cat(atomics_a_mask_acc_65, atomics_a_mask_acc_64) node atomics_a_mask_lo_lo_hi_4 = cat(atomics_a_mask_acc_67, atomics_a_mask_acc_66) node atomics_a_mask_lo_lo_4 = cat(atomics_a_mask_lo_lo_hi_4, atomics_a_mask_lo_lo_lo_4) node atomics_a_mask_lo_hi_lo_4 = cat(atomics_a_mask_acc_69, atomics_a_mask_acc_68) node atomics_a_mask_lo_hi_hi_4 = cat(atomics_a_mask_acc_71, atomics_a_mask_acc_70) node atomics_a_mask_lo_hi_4 = cat(atomics_a_mask_lo_hi_hi_4, atomics_a_mask_lo_hi_lo_4) node atomics_a_mask_lo_4 = cat(atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4) node atomics_a_mask_hi_lo_lo_4 = cat(atomics_a_mask_acc_73, atomics_a_mask_acc_72) node atomics_a_mask_hi_lo_hi_4 = cat(atomics_a_mask_acc_75, atomics_a_mask_acc_74) node atomics_a_mask_hi_lo_4 = cat(atomics_a_mask_hi_lo_hi_4, atomics_a_mask_hi_lo_lo_4) node atomics_a_mask_hi_hi_lo_4 = cat(atomics_a_mask_acc_77, atomics_a_mask_acc_76) node atomics_a_mask_hi_hi_hi_4 = cat(atomics_a_mask_acc_79, atomics_a_mask_acc_78) node atomics_a_mask_hi_hi_4 = cat(atomics_a_mask_hi_hi_hi_4, atomics_a_mask_hi_hi_lo_4) node atomics_a_mask_hi_4 = cat(atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4) node _atomics_a_mask_T_4 = cat(atomics_a_mask_hi_4, atomics_a_mask_lo_4) connect atomics_a_4.mask, _atomics_a_mask_T_4 connect atomics_a_4.data, a_data connect atomics_a_4.corrupt, UInt<1>(0h0) node _atomics_legal_T_295 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_296 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_297 = and(_atomics_legal_T_295, _atomics_legal_T_296) node _atomics_legal_T_298 = or(UInt<1>(0h0), _atomics_legal_T_297) node _atomics_legal_T_299 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_300 = cvt(_atomics_legal_T_299) node _atomics_legal_T_301 = and(_atomics_legal_T_300, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_302 = asSInt(_atomics_legal_T_301) node _atomics_legal_T_303 = eq(_atomics_legal_T_302, asSInt(UInt<1>(0h0))) node _atomics_legal_T_304 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_305 = cvt(_atomics_legal_T_304) node _atomics_legal_T_306 = and(_atomics_legal_T_305, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_307 = asSInt(_atomics_legal_T_306) node _atomics_legal_T_308 = eq(_atomics_legal_T_307, asSInt(UInt<1>(0h0))) node _atomics_legal_T_309 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_310 = cvt(_atomics_legal_T_309) node _atomics_legal_T_311 = and(_atomics_legal_T_310, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_312 = asSInt(_atomics_legal_T_311) node _atomics_legal_T_313 = eq(_atomics_legal_T_312, asSInt(UInt<1>(0h0))) node _atomics_legal_T_314 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_315 = cvt(_atomics_legal_T_314) node _atomics_legal_T_316 = and(_atomics_legal_T_315, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_317 = asSInt(_atomics_legal_T_316) node _atomics_legal_T_318 = eq(_atomics_legal_T_317, asSInt(UInt<1>(0h0))) node _atomics_legal_T_319 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_320 = cvt(_atomics_legal_T_319) node _atomics_legal_T_321 = and(_atomics_legal_T_320, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_322 = asSInt(_atomics_legal_T_321) node _atomics_legal_T_323 = eq(_atomics_legal_T_322, asSInt(UInt<1>(0h0))) node _atomics_legal_T_324 = or(_atomics_legal_T_303, _atomics_legal_T_308) node _atomics_legal_T_325 = or(_atomics_legal_T_324, _atomics_legal_T_313) node _atomics_legal_T_326 = or(_atomics_legal_T_325, _atomics_legal_T_318) node _atomics_legal_T_327 = or(_atomics_legal_T_326, _atomics_legal_T_323) node _atomics_legal_T_328 = and(_atomics_legal_T_298, _atomics_legal_T_327) node _atomics_legal_T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_330 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_331 = cvt(_atomics_legal_T_330) node _atomics_legal_T_332 = and(_atomics_legal_T_331, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_333 = asSInt(_atomics_legal_T_332) node _atomics_legal_T_334 = eq(_atomics_legal_T_333, asSInt(UInt<1>(0h0))) node _atomics_legal_T_335 = and(_atomics_legal_T_329, _atomics_legal_T_334) node _atomics_legal_T_336 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_337 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_338 = and(_atomics_legal_T_336, _atomics_legal_T_337) node _atomics_legal_T_339 = or(UInt<1>(0h0), _atomics_legal_T_338) node _atomics_legal_T_340 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_341 = cvt(_atomics_legal_T_340) node _atomics_legal_T_342 = and(_atomics_legal_T_341, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_343 = asSInt(_atomics_legal_T_342) node _atomics_legal_T_344 = eq(_atomics_legal_T_343, asSInt(UInt<1>(0h0))) node _atomics_legal_T_345 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_346 = cvt(_atomics_legal_T_345) node _atomics_legal_T_347 = and(_atomics_legal_T_346, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_348 = asSInt(_atomics_legal_T_347) node _atomics_legal_T_349 = eq(_atomics_legal_T_348, asSInt(UInt<1>(0h0))) node _atomics_legal_T_350 = or(_atomics_legal_T_344, _atomics_legal_T_349) node _atomics_legal_T_351 = and(_atomics_legal_T_339, _atomics_legal_T_350) node _atomics_legal_T_352 = or(UInt<1>(0h0), _atomics_legal_T_328) node _atomics_legal_T_353 = or(_atomics_legal_T_352, _atomics_legal_T_335) node atomics_legal_5 = or(_atomics_legal_T_353, _atomics_legal_T_351) wire atomics_a_5 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_5.opcode, UInt<2>(0h2) connect atomics_a_5.param, UInt<3>(0h0) connect atomics_a_5.size, req.uop.mem_size connect atomics_a_5.source, UInt<3>(0h5) connect atomics_a_5.address, req.addr node _atomics_a_mask_sizeOH_T_15 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_5 = bits(_atomics_a_mask_sizeOH_T_15, 1, 0) node _atomics_a_mask_sizeOH_T_16 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_5) node _atomics_a_mask_sizeOH_T_17 = bits(_atomics_a_mask_sizeOH_T_16, 3, 0) node atomics_a_mask_sizeOH_5 = or(_atomics_a_mask_sizeOH_T_17, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_5 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 3, 3) node atomics_a_mask_sub_sub_sub_bit_5 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_5 = eq(atomics_a_mask_sub_sub_sub_bit_5, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_5) node _atomics_a_mask_sub_sub_sub_acc_T_10 = and(atomics_a_mask_sub_sub_sub_size_5, atomics_a_mask_sub_sub_sub_0_2_5) node atomics_a_mask_sub_sub_sub_0_1_5 = or(atomics_a_mask_sub_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_sub_acc_T_10) node atomics_a_mask_sub_sub_sub_1_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_5) node _atomics_a_mask_sub_sub_sub_acc_T_11 = and(atomics_a_mask_sub_sub_sub_size_5, atomics_a_mask_sub_sub_sub_1_2_5) node atomics_a_mask_sub_sub_sub_1_1_5 = or(atomics_a_mask_sub_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_sub_acc_T_11) node atomics_a_mask_sub_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 2, 2) node atomics_a_mask_sub_sub_bit_5 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_5 = eq(atomics_a_mask_sub_sub_bit_5, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_5 = and(atomics_a_mask_sub_sub_sub_0_2_5, atomics_a_mask_sub_sub_nbit_5) node _atomics_a_mask_sub_sub_acc_T_20 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_0_2_5) node atomics_a_mask_sub_sub_0_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_20) node atomics_a_mask_sub_sub_1_2_5 = and(atomics_a_mask_sub_sub_sub_0_2_5, atomics_a_mask_sub_sub_bit_5) node _atomics_a_mask_sub_sub_acc_T_21 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_1_2_5) node atomics_a_mask_sub_sub_1_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_21) node atomics_a_mask_sub_sub_2_2_5 = and(atomics_a_mask_sub_sub_sub_1_2_5, atomics_a_mask_sub_sub_nbit_5) node _atomics_a_mask_sub_sub_acc_T_22 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_2_2_5) node atomics_a_mask_sub_sub_2_1_5 = or(atomics_a_mask_sub_sub_sub_1_1_5, _atomics_a_mask_sub_sub_acc_T_22) node atomics_a_mask_sub_sub_3_2_5 = and(atomics_a_mask_sub_sub_sub_1_2_5, atomics_a_mask_sub_sub_bit_5) node _atomics_a_mask_sub_sub_acc_T_23 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_3_2_5) node atomics_a_mask_sub_sub_3_1_5 = or(atomics_a_mask_sub_sub_sub_1_1_5, _atomics_a_mask_sub_sub_acc_T_23) node atomics_a_mask_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 1, 1) node atomics_a_mask_sub_bit_5 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_5 = eq(atomics_a_mask_sub_bit_5, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_nbit_5) node _atomics_a_mask_sub_acc_T_40 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_0_2_5) node atomics_a_mask_sub_0_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_40) node atomics_a_mask_sub_1_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_bit_5) node _atomics_a_mask_sub_acc_T_41 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_1_2_5) node atomics_a_mask_sub_1_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_41) node atomics_a_mask_sub_2_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_nbit_5) node _atomics_a_mask_sub_acc_T_42 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_2_2_5) node atomics_a_mask_sub_2_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_42) node atomics_a_mask_sub_3_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_bit_5) node _atomics_a_mask_sub_acc_T_43 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_3_2_5) node atomics_a_mask_sub_3_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_43) node atomics_a_mask_sub_4_2_5 = and(atomics_a_mask_sub_sub_2_2_5, atomics_a_mask_sub_nbit_5) node _atomics_a_mask_sub_acc_T_44 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_4_2_5) node atomics_a_mask_sub_4_1_5 = or(atomics_a_mask_sub_sub_2_1_5, _atomics_a_mask_sub_acc_T_44) node atomics_a_mask_sub_5_2_5 = and(atomics_a_mask_sub_sub_2_2_5, atomics_a_mask_sub_bit_5) node _atomics_a_mask_sub_acc_T_45 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_5_2_5) node atomics_a_mask_sub_5_1_5 = or(atomics_a_mask_sub_sub_2_1_5, _atomics_a_mask_sub_acc_T_45) node atomics_a_mask_sub_6_2_5 = and(atomics_a_mask_sub_sub_3_2_5, atomics_a_mask_sub_nbit_5) node _atomics_a_mask_sub_acc_T_46 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_6_2_5) node atomics_a_mask_sub_6_1_5 = or(atomics_a_mask_sub_sub_3_1_5, _atomics_a_mask_sub_acc_T_46) node atomics_a_mask_sub_7_2_5 = and(atomics_a_mask_sub_sub_3_2_5, atomics_a_mask_sub_bit_5) node _atomics_a_mask_sub_acc_T_47 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_7_2_5) node atomics_a_mask_sub_7_1_5 = or(atomics_a_mask_sub_sub_3_1_5, _atomics_a_mask_sub_acc_T_47) node atomics_a_mask_size_5 = bits(atomics_a_mask_sizeOH_5, 0, 0) node atomics_a_mask_bit_5 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_5 = eq(atomics_a_mask_bit_5, UInt<1>(0h0)) node atomics_a_mask_eq_80 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_80 = and(atomics_a_mask_size_5, atomics_a_mask_eq_80) node atomics_a_mask_acc_80 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_80) node atomics_a_mask_eq_81 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_81 = and(atomics_a_mask_size_5, atomics_a_mask_eq_81) node atomics_a_mask_acc_81 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_81) node atomics_a_mask_eq_82 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_82 = and(atomics_a_mask_size_5, atomics_a_mask_eq_82) node atomics_a_mask_acc_82 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_82) node atomics_a_mask_eq_83 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_83 = and(atomics_a_mask_size_5, atomics_a_mask_eq_83) node atomics_a_mask_acc_83 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_83) node atomics_a_mask_eq_84 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_84 = and(atomics_a_mask_size_5, atomics_a_mask_eq_84) node atomics_a_mask_acc_84 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_84) node atomics_a_mask_eq_85 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_85 = and(atomics_a_mask_size_5, atomics_a_mask_eq_85) node atomics_a_mask_acc_85 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_85) node atomics_a_mask_eq_86 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_86 = and(atomics_a_mask_size_5, atomics_a_mask_eq_86) node atomics_a_mask_acc_86 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_86) node atomics_a_mask_eq_87 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_87 = and(atomics_a_mask_size_5, atomics_a_mask_eq_87) node atomics_a_mask_acc_87 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_87) node atomics_a_mask_eq_88 = and(atomics_a_mask_sub_4_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_88 = and(atomics_a_mask_size_5, atomics_a_mask_eq_88) node atomics_a_mask_acc_88 = or(atomics_a_mask_sub_4_1_5, _atomics_a_mask_acc_T_88) node atomics_a_mask_eq_89 = and(atomics_a_mask_sub_4_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_89 = and(atomics_a_mask_size_5, atomics_a_mask_eq_89) node atomics_a_mask_acc_89 = or(atomics_a_mask_sub_4_1_5, _atomics_a_mask_acc_T_89) node atomics_a_mask_eq_90 = and(atomics_a_mask_sub_5_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_90 = and(atomics_a_mask_size_5, atomics_a_mask_eq_90) node atomics_a_mask_acc_90 = or(atomics_a_mask_sub_5_1_5, _atomics_a_mask_acc_T_90) node atomics_a_mask_eq_91 = and(atomics_a_mask_sub_5_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_91 = and(atomics_a_mask_size_5, atomics_a_mask_eq_91) node atomics_a_mask_acc_91 = or(atomics_a_mask_sub_5_1_5, _atomics_a_mask_acc_T_91) node atomics_a_mask_eq_92 = and(atomics_a_mask_sub_6_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_92 = and(atomics_a_mask_size_5, atomics_a_mask_eq_92) node atomics_a_mask_acc_92 = or(atomics_a_mask_sub_6_1_5, _atomics_a_mask_acc_T_92) node atomics_a_mask_eq_93 = and(atomics_a_mask_sub_6_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_93 = and(atomics_a_mask_size_5, atomics_a_mask_eq_93) node atomics_a_mask_acc_93 = or(atomics_a_mask_sub_6_1_5, _atomics_a_mask_acc_T_93) node atomics_a_mask_eq_94 = and(atomics_a_mask_sub_7_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_94 = and(atomics_a_mask_size_5, atomics_a_mask_eq_94) node atomics_a_mask_acc_94 = or(atomics_a_mask_sub_7_1_5, _atomics_a_mask_acc_T_94) node atomics_a_mask_eq_95 = and(atomics_a_mask_sub_7_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_95 = and(atomics_a_mask_size_5, atomics_a_mask_eq_95) node atomics_a_mask_acc_95 = or(atomics_a_mask_sub_7_1_5, _atomics_a_mask_acc_T_95) node atomics_a_mask_lo_lo_lo_5 = cat(atomics_a_mask_acc_81, atomics_a_mask_acc_80) node atomics_a_mask_lo_lo_hi_5 = cat(atomics_a_mask_acc_83, atomics_a_mask_acc_82) node atomics_a_mask_lo_lo_5 = cat(atomics_a_mask_lo_lo_hi_5, atomics_a_mask_lo_lo_lo_5) node atomics_a_mask_lo_hi_lo_5 = cat(atomics_a_mask_acc_85, atomics_a_mask_acc_84) node atomics_a_mask_lo_hi_hi_5 = cat(atomics_a_mask_acc_87, atomics_a_mask_acc_86) node atomics_a_mask_lo_hi_5 = cat(atomics_a_mask_lo_hi_hi_5, atomics_a_mask_lo_hi_lo_5) node atomics_a_mask_lo_5 = cat(atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5) node atomics_a_mask_hi_lo_lo_5 = cat(atomics_a_mask_acc_89, atomics_a_mask_acc_88) node atomics_a_mask_hi_lo_hi_5 = cat(atomics_a_mask_acc_91, atomics_a_mask_acc_90) node atomics_a_mask_hi_lo_5 = cat(atomics_a_mask_hi_lo_hi_5, atomics_a_mask_hi_lo_lo_5) node atomics_a_mask_hi_hi_lo_5 = cat(atomics_a_mask_acc_93, atomics_a_mask_acc_92) node atomics_a_mask_hi_hi_hi_5 = cat(atomics_a_mask_acc_95, atomics_a_mask_acc_94) node atomics_a_mask_hi_hi_5 = cat(atomics_a_mask_hi_hi_hi_5, atomics_a_mask_hi_hi_lo_5) node atomics_a_mask_hi_5 = cat(atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5) node _atomics_a_mask_T_5 = cat(atomics_a_mask_hi_5, atomics_a_mask_lo_5) connect atomics_a_5.mask, _atomics_a_mask_T_5 connect atomics_a_5.data, a_data connect atomics_a_5.corrupt, UInt<1>(0h0) node _atomics_legal_T_354 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_355 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_356 = and(_atomics_legal_T_354, _atomics_legal_T_355) node _atomics_legal_T_357 = or(UInt<1>(0h0), _atomics_legal_T_356) node _atomics_legal_T_358 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_359 = cvt(_atomics_legal_T_358) node _atomics_legal_T_360 = and(_atomics_legal_T_359, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_361 = asSInt(_atomics_legal_T_360) node _atomics_legal_T_362 = eq(_atomics_legal_T_361, asSInt(UInt<1>(0h0))) node _atomics_legal_T_363 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_364 = cvt(_atomics_legal_T_363) node _atomics_legal_T_365 = and(_atomics_legal_T_364, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_366 = asSInt(_atomics_legal_T_365) node _atomics_legal_T_367 = eq(_atomics_legal_T_366, asSInt(UInt<1>(0h0))) node _atomics_legal_T_368 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_369 = cvt(_atomics_legal_T_368) node _atomics_legal_T_370 = and(_atomics_legal_T_369, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_371 = asSInt(_atomics_legal_T_370) node _atomics_legal_T_372 = eq(_atomics_legal_T_371, asSInt(UInt<1>(0h0))) node _atomics_legal_T_373 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_374 = cvt(_atomics_legal_T_373) node _atomics_legal_T_375 = and(_atomics_legal_T_374, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_376 = asSInt(_atomics_legal_T_375) node _atomics_legal_T_377 = eq(_atomics_legal_T_376, asSInt(UInt<1>(0h0))) node _atomics_legal_T_378 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_379 = cvt(_atomics_legal_T_378) node _atomics_legal_T_380 = and(_atomics_legal_T_379, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_381 = asSInt(_atomics_legal_T_380) node _atomics_legal_T_382 = eq(_atomics_legal_T_381, asSInt(UInt<1>(0h0))) node _atomics_legal_T_383 = or(_atomics_legal_T_362, _atomics_legal_T_367) node _atomics_legal_T_384 = or(_atomics_legal_T_383, _atomics_legal_T_372) node _atomics_legal_T_385 = or(_atomics_legal_T_384, _atomics_legal_T_377) node _atomics_legal_T_386 = or(_atomics_legal_T_385, _atomics_legal_T_382) node _atomics_legal_T_387 = and(_atomics_legal_T_357, _atomics_legal_T_386) node _atomics_legal_T_388 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_389 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_390 = cvt(_atomics_legal_T_389) node _atomics_legal_T_391 = and(_atomics_legal_T_390, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_392 = asSInt(_atomics_legal_T_391) node _atomics_legal_T_393 = eq(_atomics_legal_T_392, asSInt(UInt<1>(0h0))) node _atomics_legal_T_394 = and(_atomics_legal_T_388, _atomics_legal_T_393) node _atomics_legal_T_395 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_396 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_397 = and(_atomics_legal_T_395, _atomics_legal_T_396) node _atomics_legal_T_398 = or(UInt<1>(0h0), _atomics_legal_T_397) node _atomics_legal_T_399 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_400 = cvt(_atomics_legal_T_399) node _atomics_legal_T_401 = and(_atomics_legal_T_400, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_402 = asSInt(_atomics_legal_T_401) node _atomics_legal_T_403 = eq(_atomics_legal_T_402, asSInt(UInt<1>(0h0))) node _atomics_legal_T_404 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_405 = cvt(_atomics_legal_T_404) node _atomics_legal_T_406 = and(_atomics_legal_T_405, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_407 = asSInt(_atomics_legal_T_406) node _atomics_legal_T_408 = eq(_atomics_legal_T_407, asSInt(UInt<1>(0h0))) node _atomics_legal_T_409 = or(_atomics_legal_T_403, _atomics_legal_T_408) node _atomics_legal_T_410 = and(_atomics_legal_T_398, _atomics_legal_T_409) node _atomics_legal_T_411 = or(UInt<1>(0h0), _atomics_legal_T_387) node _atomics_legal_T_412 = or(_atomics_legal_T_411, _atomics_legal_T_394) node atomics_legal_6 = or(_atomics_legal_T_412, _atomics_legal_T_410) wire atomics_a_6 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_6.opcode, UInt<2>(0h2) connect atomics_a_6.param, UInt<3>(0h1) connect atomics_a_6.size, req.uop.mem_size connect atomics_a_6.source, UInt<3>(0h5) connect atomics_a_6.address, req.addr node _atomics_a_mask_sizeOH_T_18 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_6 = bits(_atomics_a_mask_sizeOH_T_18, 1, 0) node _atomics_a_mask_sizeOH_T_19 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_6) node _atomics_a_mask_sizeOH_T_20 = bits(_atomics_a_mask_sizeOH_T_19, 3, 0) node atomics_a_mask_sizeOH_6 = or(_atomics_a_mask_sizeOH_T_20, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_6 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 3, 3) node atomics_a_mask_sub_sub_sub_bit_6 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_6 = eq(atomics_a_mask_sub_sub_sub_bit_6, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_6) node _atomics_a_mask_sub_sub_sub_acc_T_12 = and(atomics_a_mask_sub_sub_sub_size_6, atomics_a_mask_sub_sub_sub_0_2_6) node atomics_a_mask_sub_sub_sub_0_1_6 = or(atomics_a_mask_sub_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_sub_acc_T_12) node atomics_a_mask_sub_sub_sub_1_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_6) node _atomics_a_mask_sub_sub_sub_acc_T_13 = and(atomics_a_mask_sub_sub_sub_size_6, atomics_a_mask_sub_sub_sub_1_2_6) node atomics_a_mask_sub_sub_sub_1_1_6 = or(atomics_a_mask_sub_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_sub_acc_T_13) node atomics_a_mask_sub_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 2, 2) node atomics_a_mask_sub_sub_bit_6 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_6 = eq(atomics_a_mask_sub_sub_bit_6, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_6 = and(atomics_a_mask_sub_sub_sub_0_2_6, atomics_a_mask_sub_sub_nbit_6) node _atomics_a_mask_sub_sub_acc_T_24 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_0_2_6) node atomics_a_mask_sub_sub_0_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_24) node atomics_a_mask_sub_sub_1_2_6 = and(atomics_a_mask_sub_sub_sub_0_2_6, atomics_a_mask_sub_sub_bit_6) node _atomics_a_mask_sub_sub_acc_T_25 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_1_2_6) node atomics_a_mask_sub_sub_1_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_25) node atomics_a_mask_sub_sub_2_2_6 = and(atomics_a_mask_sub_sub_sub_1_2_6, atomics_a_mask_sub_sub_nbit_6) node _atomics_a_mask_sub_sub_acc_T_26 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_2_2_6) node atomics_a_mask_sub_sub_2_1_6 = or(atomics_a_mask_sub_sub_sub_1_1_6, _atomics_a_mask_sub_sub_acc_T_26) node atomics_a_mask_sub_sub_3_2_6 = and(atomics_a_mask_sub_sub_sub_1_2_6, atomics_a_mask_sub_sub_bit_6) node _atomics_a_mask_sub_sub_acc_T_27 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_3_2_6) node atomics_a_mask_sub_sub_3_1_6 = or(atomics_a_mask_sub_sub_sub_1_1_6, _atomics_a_mask_sub_sub_acc_T_27) node atomics_a_mask_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 1, 1) node atomics_a_mask_sub_bit_6 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_6 = eq(atomics_a_mask_sub_bit_6, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_nbit_6) node _atomics_a_mask_sub_acc_T_48 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_0_2_6) node atomics_a_mask_sub_0_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_48) node atomics_a_mask_sub_1_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_bit_6) node _atomics_a_mask_sub_acc_T_49 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_1_2_6) node atomics_a_mask_sub_1_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_49) node atomics_a_mask_sub_2_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_nbit_6) node _atomics_a_mask_sub_acc_T_50 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_2_2_6) node atomics_a_mask_sub_2_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_50) node atomics_a_mask_sub_3_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_bit_6) node _atomics_a_mask_sub_acc_T_51 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_3_2_6) node atomics_a_mask_sub_3_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_51) node atomics_a_mask_sub_4_2_6 = and(atomics_a_mask_sub_sub_2_2_6, atomics_a_mask_sub_nbit_6) node _atomics_a_mask_sub_acc_T_52 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_4_2_6) node atomics_a_mask_sub_4_1_6 = or(atomics_a_mask_sub_sub_2_1_6, _atomics_a_mask_sub_acc_T_52) node atomics_a_mask_sub_5_2_6 = and(atomics_a_mask_sub_sub_2_2_6, atomics_a_mask_sub_bit_6) node _atomics_a_mask_sub_acc_T_53 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_5_2_6) node atomics_a_mask_sub_5_1_6 = or(atomics_a_mask_sub_sub_2_1_6, _atomics_a_mask_sub_acc_T_53) node atomics_a_mask_sub_6_2_6 = and(atomics_a_mask_sub_sub_3_2_6, atomics_a_mask_sub_nbit_6) node _atomics_a_mask_sub_acc_T_54 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_6_2_6) node atomics_a_mask_sub_6_1_6 = or(atomics_a_mask_sub_sub_3_1_6, _atomics_a_mask_sub_acc_T_54) node atomics_a_mask_sub_7_2_6 = and(atomics_a_mask_sub_sub_3_2_6, atomics_a_mask_sub_bit_6) node _atomics_a_mask_sub_acc_T_55 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_7_2_6) node atomics_a_mask_sub_7_1_6 = or(atomics_a_mask_sub_sub_3_1_6, _atomics_a_mask_sub_acc_T_55) node atomics_a_mask_size_6 = bits(atomics_a_mask_sizeOH_6, 0, 0) node atomics_a_mask_bit_6 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_6 = eq(atomics_a_mask_bit_6, UInt<1>(0h0)) node atomics_a_mask_eq_96 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_96 = and(atomics_a_mask_size_6, atomics_a_mask_eq_96) node atomics_a_mask_acc_96 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_96) node atomics_a_mask_eq_97 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_97 = and(atomics_a_mask_size_6, atomics_a_mask_eq_97) node atomics_a_mask_acc_97 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_97) node atomics_a_mask_eq_98 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_98 = and(atomics_a_mask_size_6, atomics_a_mask_eq_98) node atomics_a_mask_acc_98 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_98) node atomics_a_mask_eq_99 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_99 = and(atomics_a_mask_size_6, atomics_a_mask_eq_99) node atomics_a_mask_acc_99 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_99) node atomics_a_mask_eq_100 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_100 = and(atomics_a_mask_size_6, atomics_a_mask_eq_100) node atomics_a_mask_acc_100 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_100) node atomics_a_mask_eq_101 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_101 = and(atomics_a_mask_size_6, atomics_a_mask_eq_101) node atomics_a_mask_acc_101 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_101) node atomics_a_mask_eq_102 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_102 = and(atomics_a_mask_size_6, atomics_a_mask_eq_102) node atomics_a_mask_acc_102 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_102) node atomics_a_mask_eq_103 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_103 = and(atomics_a_mask_size_6, atomics_a_mask_eq_103) node atomics_a_mask_acc_103 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_103) node atomics_a_mask_eq_104 = and(atomics_a_mask_sub_4_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_104 = and(atomics_a_mask_size_6, atomics_a_mask_eq_104) node atomics_a_mask_acc_104 = or(atomics_a_mask_sub_4_1_6, _atomics_a_mask_acc_T_104) node atomics_a_mask_eq_105 = and(atomics_a_mask_sub_4_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_105 = and(atomics_a_mask_size_6, atomics_a_mask_eq_105) node atomics_a_mask_acc_105 = or(atomics_a_mask_sub_4_1_6, _atomics_a_mask_acc_T_105) node atomics_a_mask_eq_106 = and(atomics_a_mask_sub_5_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_106 = and(atomics_a_mask_size_6, atomics_a_mask_eq_106) node atomics_a_mask_acc_106 = or(atomics_a_mask_sub_5_1_6, _atomics_a_mask_acc_T_106) node atomics_a_mask_eq_107 = and(atomics_a_mask_sub_5_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_107 = and(atomics_a_mask_size_6, atomics_a_mask_eq_107) node atomics_a_mask_acc_107 = or(atomics_a_mask_sub_5_1_6, _atomics_a_mask_acc_T_107) node atomics_a_mask_eq_108 = and(atomics_a_mask_sub_6_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_108 = and(atomics_a_mask_size_6, atomics_a_mask_eq_108) node atomics_a_mask_acc_108 = or(atomics_a_mask_sub_6_1_6, _atomics_a_mask_acc_T_108) node atomics_a_mask_eq_109 = and(atomics_a_mask_sub_6_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_109 = and(atomics_a_mask_size_6, atomics_a_mask_eq_109) node atomics_a_mask_acc_109 = or(atomics_a_mask_sub_6_1_6, _atomics_a_mask_acc_T_109) node atomics_a_mask_eq_110 = and(atomics_a_mask_sub_7_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_110 = and(atomics_a_mask_size_6, atomics_a_mask_eq_110) node atomics_a_mask_acc_110 = or(atomics_a_mask_sub_7_1_6, _atomics_a_mask_acc_T_110) node atomics_a_mask_eq_111 = and(atomics_a_mask_sub_7_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_111 = and(atomics_a_mask_size_6, atomics_a_mask_eq_111) node atomics_a_mask_acc_111 = or(atomics_a_mask_sub_7_1_6, _atomics_a_mask_acc_T_111) node atomics_a_mask_lo_lo_lo_6 = cat(atomics_a_mask_acc_97, atomics_a_mask_acc_96) node atomics_a_mask_lo_lo_hi_6 = cat(atomics_a_mask_acc_99, atomics_a_mask_acc_98) node atomics_a_mask_lo_lo_6 = cat(atomics_a_mask_lo_lo_hi_6, atomics_a_mask_lo_lo_lo_6) node atomics_a_mask_lo_hi_lo_6 = cat(atomics_a_mask_acc_101, atomics_a_mask_acc_100) node atomics_a_mask_lo_hi_hi_6 = cat(atomics_a_mask_acc_103, atomics_a_mask_acc_102) node atomics_a_mask_lo_hi_6 = cat(atomics_a_mask_lo_hi_hi_6, atomics_a_mask_lo_hi_lo_6) node atomics_a_mask_lo_6 = cat(atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6) node atomics_a_mask_hi_lo_lo_6 = cat(atomics_a_mask_acc_105, atomics_a_mask_acc_104) node atomics_a_mask_hi_lo_hi_6 = cat(atomics_a_mask_acc_107, atomics_a_mask_acc_106) node atomics_a_mask_hi_lo_6 = cat(atomics_a_mask_hi_lo_hi_6, atomics_a_mask_hi_lo_lo_6) node atomics_a_mask_hi_hi_lo_6 = cat(atomics_a_mask_acc_109, atomics_a_mask_acc_108) node atomics_a_mask_hi_hi_hi_6 = cat(atomics_a_mask_acc_111, atomics_a_mask_acc_110) node atomics_a_mask_hi_hi_6 = cat(atomics_a_mask_hi_hi_hi_6, atomics_a_mask_hi_hi_lo_6) node atomics_a_mask_hi_6 = cat(atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6) node _atomics_a_mask_T_6 = cat(atomics_a_mask_hi_6, atomics_a_mask_lo_6) connect atomics_a_6.mask, _atomics_a_mask_T_6 connect atomics_a_6.data, a_data connect atomics_a_6.corrupt, UInt<1>(0h0) node _atomics_legal_T_413 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_414 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_415 = and(_atomics_legal_T_413, _atomics_legal_T_414) node _atomics_legal_T_416 = or(UInt<1>(0h0), _atomics_legal_T_415) node _atomics_legal_T_417 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_418 = cvt(_atomics_legal_T_417) node _atomics_legal_T_419 = and(_atomics_legal_T_418, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_420 = asSInt(_atomics_legal_T_419) node _atomics_legal_T_421 = eq(_atomics_legal_T_420, asSInt(UInt<1>(0h0))) node _atomics_legal_T_422 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_423 = cvt(_atomics_legal_T_422) node _atomics_legal_T_424 = and(_atomics_legal_T_423, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_425 = asSInt(_atomics_legal_T_424) node _atomics_legal_T_426 = eq(_atomics_legal_T_425, asSInt(UInt<1>(0h0))) node _atomics_legal_T_427 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_428 = cvt(_atomics_legal_T_427) node _atomics_legal_T_429 = and(_atomics_legal_T_428, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_430 = asSInt(_atomics_legal_T_429) node _atomics_legal_T_431 = eq(_atomics_legal_T_430, asSInt(UInt<1>(0h0))) node _atomics_legal_T_432 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_433 = cvt(_atomics_legal_T_432) node _atomics_legal_T_434 = and(_atomics_legal_T_433, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_435 = asSInt(_atomics_legal_T_434) node _atomics_legal_T_436 = eq(_atomics_legal_T_435, asSInt(UInt<1>(0h0))) node _atomics_legal_T_437 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_438 = cvt(_atomics_legal_T_437) node _atomics_legal_T_439 = and(_atomics_legal_T_438, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_440 = asSInt(_atomics_legal_T_439) node _atomics_legal_T_441 = eq(_atomics_legal_T_440, asSInt(UInt<1>(0h0))) node _atomics_legal_T_442 = or(_atomics_legal_T_421, _atomics_legal_T_426) node _atomics_legal_T_443 = or(_atomics_legal_T_442, _atomics_legal_T_431) node _atomics_legal_T_444 = or(_atomics_legal_T_443, _atomics_legal_T_436) node _atomics_legal_T_445 = or(_atomics_legal_T_444, _atomics_legal_T_441) node _atomics_legal_T_446 = and(_atomics_legal_T_416, _atomics_legal_T_445) node _atomics_legal_T_447 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_448 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_449 = cvt(_atomics_legal_T_448) node _atomics_legal_T_450 = and(_atomics_legal_T_449, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_451 = asSInt(_atomics_legal_T_450) node _atomics_legal_T_452 = eq(_atomics_legal_T_451, asSInt(UInt<1>(0h0))) node _atomics_legal_T_453 = and(_atomics_legal_T_447, _atomics_legal_T_452) node _atomics_legal_T_454 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_455 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_456 = and(_atomics_legal_T_454, _atomics_legal_T_455) node _atomics_legal_T_457 = or(UInt<1>(0h0), _atomics_legal_T_456) node _atomics_legal_T_458 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_459 = cvt(_atomics_legal_T_458) node _atomics_legal_T_460 = and(_atomics_legal_T_459, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_461 = asSInt(_atomics_legal_T_460) node _atomics_legal_T_462 = eq(_atomics_legal_T_461, asSInt(UInt<1>(0h0))) node _atomics_legal_T_463 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_464 = cvt(_atomics_legal_T_463) node _atomics_legal_T_465 = and(_atomics_legal_T_464, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_466 = asSInt(_atomics_legal_T_465) node _atomics_legal_T_467 = eq(_atomics_legal_T_466, asSInt(UInt<1>(0h0))) node _atomics_legal_T_468 = or(_atomics_legal_T_462, _atomics_legal_T_467) node _atomics_legal_T_469 = and(_atomics_legal_T_457, _atomics_legal_T_468) node _atomics_legal_T_470 = or(UInt<1>(0h0), _atomics_legal_T_446) node _atomics_legal_T_471 = or(_atomics_legal_T_470, _atomics_legal_T_453) node atomics_legal_7 = or(_atomics_legal_T_471, _atomics_legal_T_469) wire atomics_a_7 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_7.opcode, UInt<2>(0h2) connect atomics_a_7.param, UInt<3>(0h2) connect atomics_a_7.size, req.uop.mem_size connect atomics_a_7.source, UInt<3>(0h5) connect atomics_a_7.address, req.addr node _atomics_a_mask_sizeOH_T_21 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_7 = bits(_atomics_a_mask_sizeOH_T_21, 1, 0) node _atomics_a_mask_sizeOH_T_22 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_7) node _atomics_a_mask_sizeOH_T_23 = bits(_atomics_a_mask_sizeOH_T_22, 3, 0) node atomics_a_mask_sizeOH_7 = or(_atomics_a_mask_sizeOH_T_23, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_7 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 3, 3) node atomics_a_mask_sub_sub_sub_bit_7 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_7 = eq(atomics_a_mask_sub_sub_sub_bit_7, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_7) node _atomics_a_mask_sub_sub_sub_acc_T_14 = and(atomics_a_mask_sub_sub_sub_size_7, atomics_a_mask_sub_sub_sub_0_2_7) node atomics_a_mask_sub_sub_sub_0_1_7 = or(atomics_a_mask_sub_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_sub_acc_T_14) node atomics_a_mask_sub_sub_sub_1_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_7) node _atomics_a_mask_sub_sub_sub_acc_T_15 = and(atomics_a_mask_sub_sub_sub_size_7, atomics_a_mask_sub_sub_sub_1_2_7) node atomics_a_mask_sub_sub_sub_1_1_7 = or(atomics_a_mask_sub_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_sub_acc_T_15) node atomics_a_mask_sub_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 2, 2) node atomics_a_mask_sub_sub_bit_7 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_7 = eq(atomics_a_mask_sub_sub_bit_7, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_7 = and(atomics_a_mask_sub_sub_sub_0_2_7, atomics_a_mask_sub_sub_nbit_7) node _atomics_a_mask_sub_sub_acc_T_28 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_0_2_7) node atomics_a_mask_sub_sub_0_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_28) node atomics_a_mask_sub_sub_1_2_7 = and(atomics_a_mask_sub_sub_sub_0_2_7, atomics_a_mask_sub_sub_bit_7) node _atomics_a_mask_sub_sub_acc_T_29 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_1_2_7) node atomics_a_mask_sub_sub_1_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_29) node atomics_a_mask_sub_sub_2_2_7 = and(atomics_a_mask_sub_sub_sub_1_2_7, atomics_a_mask_sub_sub_nbit_7) node _atomics_a_mask_sub_sub_acc_T_30 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_2_2_7) node atomics_a_mask_sub_sub_2_1_7 = or(atomics_a_mask_sub_sub_sub_1_1_7, _atomics_a_mask_sub_sub_acc_T_30) node atomics_a_mask_sub_sub_3_2_7 = and(atomics_a_mask_sub_sub_sub_1_2_7, atomics_a_mask_sub_sub_bit_7) node _atomics_a_mask_sub_sub_acc_T_31 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_3_2_7) node atomics_a_mask_sub_sub_3_1_7 = or(atomics_a_mask_sub_sub_sub_1_1_7, _atomics_a_mask_sub_sub_acc_T_31) node atomics_a_mask_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 1, 1) node atomics_a_mask_sub_bit_7 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_7 = eq(atomics_a_mask_sub_bit_7, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_nbit_7) node _atomics_a_mask_sub_acc_T_56 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_0_2_7) node atomics_a_mask_sub_0_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_56) node atomics_a_mask_sub_1_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_bit_7) node _atomics_a_mask_sub_acc_T_57 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_1_2_7) node atomics_a_mask_sub_1_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_57) node atomics_a_mask_sub_2_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_nbit_7) node _atomics_a_mask_sub_acc_T_58 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_2_2_7) node atomics_a_mask_sub_2_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_58) node atomics_a_mask_sub_3_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_bit_7) node _atomics_a_mask_sub_acc_T_59 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_3_2_7) node atomics_a_mask_sub_3_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_59) node atomics_a_mask_sub_4_2_7 = and(atomics_a_mask_sub_sub_2_2_7, atomics_a_mask_sub_nbit_7) node _atomics_a_mask_sub_acc_T_60 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_4_2_7) node atomics_a_mask_sub_4_1_7 = or(atomics_a_mask_sub_sub_2_1_7, _atomics_a_mask_sub_acc_T_60) node atomics_a_mask_sub_5_2_7 = and(atomics_a_mask_sub_sub_2_2_7, atomics_a_mask_sub_bit_7) node _atomics_a_mask_sub_acc_T_61 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_5_2_7) node atomics_a_mask_sub_5_1_7 = or(atomics_a_mask_sub_sub_2_1_7, _atomics_a_mask_sub_acc_T_61) node atomics_a_mask_sub_6_2_7 = and(atomics_a_mask_sub_sub_3_2_7, atomics_a_mask_sub_nbit_7) node _atomics_a_mask_sub_acc_T_62 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_6_2_7) node atomics_a_mask_sub_6_1_7 = or(atomics_a_mask_sub_sub_3_1_7, _atomics_a_mask_sub_acc_T_62) node atomics_a_mask_sub_7_2_7 = and(atomics_a_mask_sub_sub_3_2_7, atomics_a_mask_sub_bit_7) node _atomics_a_mask_sub_acc_T_63 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_7_2_7) node atomics_a_mask_sub_7_1_7 = or(atomics_a_mask_sub_sub_3_1_7, _atomics_a_mask_sub_acc_T_63) node atomics_a_mask_size_7 = bits(atomics_a_mask_sizeOH_7, 0, 0) node atomics_a_mask_bit_7 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_7 = eq(atomics_a_mask_bit_7, UInt<1>(0h0)) node atomics_a_mask_eq_112 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_112 = and(atomics_a_mask_size_7, atomics_a_mask_eq_112) node atomics_a_mask_acc_112 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_112) node atomics_a_mask_eq_113 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_113 = and(atomics_a_mask_size_7, atomics_a_mask_eq_113) node atomics_a_mask_acc_113 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_113) node atomics_a_mask_eq_114 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_114 = and(atomics_a_mask_size_7, atomics_a_mask_eq_114) node atomics_a_mask_acc_114 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_114) node atomics_a_mask_eq_115 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_115 = and(atomics_a_mask_size_7, atomics_a_mask_eq_115) node atomics_a_mask_acc_115 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_115) node atomics_a_mask_eq_116 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_116 = and(atomics_a_mask_size_7, atomics_a_mask_eq_116) node atomics_a_mask_acc_116 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_116) node atomics_a_mask_eq_117 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_117 = and(atomics_a_mask_size_7, atomics_a_mask_eq_117) node atomics_a_mask_acc_117 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_117) node atomics_a_mask_eq_118 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_118 = and(atomics_a_mask_size_7, atomics_a_mask_eq_118) node atomics_a_mask_acc_118 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_118) node atomics_a_mask_eq_119 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_119 = and(atomics_a_mask_size_7, atomics_a_mask_eq_119) node atomics_a_mask_acc_119 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_119) node atomics_a_mask_eq_120 = and(atomics_a_mask_sub_4_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_120 = and(atomics_a_mask_size_7, atomics_a_mask_eq_120) node atomics_a_mask_acc_120 = or(atomics_a_mask_sub_4_1_7, _atomics_a_mask_acc_T_120) node atomics_a_mask_eq_121 = and(atomics_a_mask_sub_4_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_121 = and(atomics_a_mask_size_7, atomics_a_mask_eq_121) node atomics_a_mask_acc_121 = or(atomics_a_mask_sub_4_1_7, _atomics_a_mask_acc_T_121) node atomics_a_mask_eq_122 = and(atomics_a_mask_sub_5_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_122 = and(atomics_a_mask_size_7, atomics_a_mask_eq_122) node atomics_a_mask_acc_122 = or(atomics_a_mask_sub_5_1_7, _atomics_a_mask_acc_T_122) node atomics_a_mask_eq_123 = and(atomics_a_mask_sub_5_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_123 = and(atomics_a_mask_size_7, atomics_a_mask_eq_123) node atomics_a_mask_acc_123 = or(atomics_a_mask_sub_5_1_7, _atomics_a_mask_acc_T_123) node atomics_a_mask_eq_124 = and(atomics_a_mask_sub_6_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_124 = and(atomics_a_mask_size_7, atomics_a_mask_eq_124) node atomics_a_mask_acc_124 = or(atomics_a_mask_sub_6_1_7, _atomics_a_mask_acc_T_124) node atomics_a_mask_eq_125 = and(atomics_a_mask_sub_6_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_125 = and(atomics_a_mask_size_7, atomics_a_mask_eq_125) node atomics_a_mask_acc_125 = or(atomics_a_mask_sub_6_1_7, _atomics_a_mask_acc_T_125) node atomics_a_mask_eq_126 = and(atomics_a_mask_sub_7_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_126 = and(atomics_a_mask_size_7, atomics_a_mask_eq_126) node atomics_a_mask_acc_126 = or(atomics_a_mask_sub_7_1_7, _atomics_a_mask_acc_T_126) node atomics_a_mask_eq_127 = and(atomics_a_mask_sub_7_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_127 = and(atomics_a_mask_size_7, atomics_a_mask_eq_127) node atomics_a_mask_acc_127 = or(atomics_a_mask_sub_7_1_7, _atomics_a_mask_acc_T_127) node atomics_a_mask_lo_lo_lo_7 = cat(atomics_a_mask_acc_113, atomics_a_mask_acc_112) node atomics_a_mask_lo_lo_hi_7 = cat(atomics_a_mask_acc_115, atomics_a_mask_acc_114) node atomics_a_mask_lo_lo_7 = cat(atomics_a_mask_lo_lo_hi_7, atomics_a_mask_lo_lo_lo_7) node atomics_a_mask_lo_hi_lo_7 = cat(atomics_a_mask_acc_117, atomics_a_mask_acc_116) node atomics_a_mask_lo_hi_hi_7 = cat(atomics_a_mask_acc_119, atomics_a_mask_acc_118) node atomics_a_mask_lo_hi_7 = cat(atomics_a_mask_lo_hi_hi_7, atomics_a_mask_lo_hi_lo_7) node atomics_a_mask_lo_7 = cat(atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7) node atomics_a_mask_hi_lo_lo_7 = cat(atomics_a_mask_acc_121, atomics_a_mask_acc_120) node atomics_a_mask_hi_lo_hi_7 = cat(atomics_a_mask_acc_123, atomics_a_mask_acc_122) node atomics_a_mask_hi_lo_7 = cat(atomics_a_mask_hi_lo_hi_7, atomics_a_mask_hi_lo_lo_7) node atomics_a_mask_hi_hi_lo_7 = cat(atomics_a_mask_acc_125, atomics_a_mask_acc_124) node atomics_a_mask_hi_hi_hi_7 = cat(atomics_a_mask_acc_127, atomics_a_mask_acc_126) node atomics_a_mask_hi_hi_7 = cat(atomics_a_mask_hi_hi_hi_7, atomics_a_mask_hi_hi_lo_7) node atomics_a_mask_hi_7 = cat(atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7) node _atomics_a_mask_T_7 = cat(atomics_a_mask_hi_7, atomics_a_mask_lo_7) connect atomics_a_7.mask, _atomics_a_mask_T_7 connect atomics_a_7.data, a_data connect atomics_a_7.corrupt, UInt<1>(0h0) node _atomics_legal_T_472 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_473 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_474 = and(_atomics_legal_T_472, _atomics_legal_T_473) node _atomics_legal_T_475 = or(UInt<1>(0h0), _atomics_legal_T_474) node _atomics_legal_T_476 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_477 = cvt(_atomics_legal_T_476) node _atomics_legal_T_478 = and(_atomics_legal_T_477, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_479 = asSInt(_atomics_legal_T_478) node _atomics_legal_T_480 = eq(_atomics_legal_T_479, asSInt(UInt<1>(0h0))) node _atomics_legal_T_481 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_482 = cvt(_atomics_legal_T_481) node _atomics_legal_T_483 = and(_atomics_legal_T_482, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_484 = asSInt(_atomics_legal_T_483) node _atomics_legal_T_485 = eq(_atomics_legal_T_484, asSInt(UInt<1>(0h0))) node _atomics_legal_T_486 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_487 = cvt(_atomics_legal_T_486) node _atomics_legal_T_488 = and(_atomics_legal_T_487, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_489 = asSInt(_atomics_legal_T_488) node _atomics_legal_T_490 = eq(_atomics_legal_T_489, asSInt(UInt<1>(0h0))) node _atomics_legal_T_491 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_492 = cvt(_atomics_legal_T_491) node _atomics_legal_T_493 = and(_atomics_legal_T_492, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_494 = asSInt(_atomics_legal_T_493) node _atomics_legal_T_495 = eq(_atomics_legal_T_494, asSInt(UInt<1>(0h0))) node _atomics_legal_T_496 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_497 = cvt(_atomics_legal_T_496) node _atomics_legal_T_498 = and(_atomics_legal_T_497, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_499 = asSInt(_atomics_legal_T_498) node _atomics_legal_T_500 = eq(_atomics_legal_T_499, asSInt(UInt<1>(0h0))) node _atomics_legal_T_501 = or(_atomics_legal_T_480, _atomics_legal_T_485) node _atomics_legal_T_502 = or(_atomics_legal_T_501, _atomics_legal_T_490) node _atomics_legal_T_503 = or(_atomics_legal_T_502, _atomics_legal_T_495) node _atomics_legal_T_504 = or(_atomics_legal_T_503, _atomics_legal_T_500) node _atomics_legal_T_505 = and(_atomics_legal_T_475, _atomics_legal_T_504) node _atomics_legal_T_506 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_507 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_508 = cvt(_atomics_legal_T_507) node _atomics_legal_T_509 = and(_atomics_legal_T_508, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_510 = asSInt(_atomics_legal_T_509) node _atomics_legal_T_511 = eq(_atomics_legal_T_510, asSInt(UInt<1>(0h0))) node _atomics_legal_T_512 = and(_atomics_legal_T_506, _atomics_legal_T_511) node _atomics_legal_T_513 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_514 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_515 = and(_atomics_legal_T_513, _atomics_legal_T_514) node _atomics_legal_T_516 = or(UInt<1>(0h0), _atomics_legal_T_515) node _atomics_legal_T_517 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_518 = cvt(_atomics_legal_T_517) node _atomics_legal_T_519 = and(_atomics_legal_T_518, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_520 = asSInt(_atomics_legal_T_519) node _atomics_legal_T_521 = eq(_atomics_legal_T_520, asSInt(UInt<1>(0h0))) node _atomics_legal_T_522 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_523 = cvt(_atomics_legal_T_522) node _atomics_legal_T_524 = and(_atomics_legal_T_523, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_525 = asSInt(_atomics_legal_T_524) node _atomics_legal_T_526 = eq(_atomics_legal_T_525, asSInt(UInt<1>(0h0))) node _atomics_legal_T_527 = or(_atomics_legal_T_521, _atomics_legal_T_526) node _atomics_legal_T_528 = and(_atomics_legal_T_516, _atomics_legal_T_527) node _atomics_legal_T_529 = or(UInt<1>(0h0), _atomics_legal_T_505) node _atomics_legal_T_530 = or(_atomics_legal_T_529, _atomics_legal_T_512) node atomics_legal_8 = or(_atomics_legal_T_530, _atomics_legal_T_528) wire atomics_a_8 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_8.opcode, UInt<2>(0h2) connect atomics_a_8.param, UInt<3>(0h3) connect atomics_a_8.size, req.uop.mem_size connect atomics_a_8.source, UInt<3>(0h5) connect atomics_a_8.address, req.addr node _atomics_a_mask_sizeOH_T_24 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_8 = bits(_atomics_a_mask_sizeOH_T_24, 1, 0) node _atomics_a_mask_sizeOH_T_25 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_8) node _atomics_a_mask_sizeOH_T_26 = bits(_atomics_a_mask_sizeOH_T_25, 3, 0) node atomics_a_mask_sizeOH_8 = or(_atomics_a_mask_sizeOH_T_26, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_8 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 3, 3) node atomics_a_mask_sub_sub_sub_bit_8 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_8 = eq(atomics_a_mask_sub_sub_sub_bit_8, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_8) node _atomics_a_mask_sub_sub_sub_acc_T_16 = and(atomics_a_mask_sub_sub_sub_size_8, atomics_a_mask_sub_sub_sub_0_2_8) node atomics_a_mask_sub_sub_sub_0_1_8 = or(atomics_a_mask_sub_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_sub_acc_T_16) node atomics_a_mask_sub_sub_sub_1_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_8) node _atomics_a_mask_sub_sub_sub_acc_T_17 = and(atomics_a_mask_sub_sub_sub_size_8, atomics_a_mask_sub_sub_sub_1_2_8) node atomics_a_mask_sub_sub_sub_1_1_8 = or(atomics_a_mask_sub_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_sub_acc_T_17) node atomics_a_mask_sub_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 2, 2) node atomics_a_mask_sub_sub_bit_8 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_8 = eq(atomics_a_mask_sub_sub_bit_8, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_8 = and(atomics_a_mask_sub_sub_sub_0_2_8, atomics_a_mask_sub_sub_nbit_8) node _atomics_a_mask_sub_sub_acc_T_32 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_0_2_8) node atomics_a_mask_sub_sub_0_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_32) node atomics_a_mask_sub_sub_1_2_8 = and(atomics_a_mask_sub_sub_sub_0_2_8, atomics_a_mask_sub_sub_bit_8) node _atomics_a_mask_sub_sub_acc_T_33 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_1_2_8) node atomics_a_mask_sub_sub_1_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_33) node atomics_a_mask_sub_sub_2_2_8 = and(atomics_a_mask_sub_sub_sub_1_2_8, atomics_a_mask_sub_sub_nbit_8) node _atomics_a_mask_sub_sub_acc_T_34 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_2_2_8) node atomics_a_mask_sub_sub_2_1_8 = or(atomics_a_mask_sub_sub_sub_1_1_8, _atomics_a_mask_sub_sub_acc_T_34) node atomics_a_mask_sub_sub_3_2_8 = and(atomics_a_mask_sub_sub_sub_1_2_8, atomics_a_mask_sub_sub_bit_8) node _atomics_a_mask_sub_sub_acc_T_35 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_3_2_8) node atomics_a_mask_sub_sub_3_1_8 = or(atomics_a_mask_sub_sub_sub_1_1_8, _atomics_a_mask_sub_sub_acc_T_35) node atomics_a_mask_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 1, 1) node atomics_a_mask_sub_bit_8 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_8 = eq(atomics_a_mask_sub_bit_8, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_nbit_8) node _atomics_a_mask_sub_acc_T_64 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_0_2_8) node atomics_a_mask_sub_0_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_64) node atomics_a_mask_sub_1_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_bit_8) node _atomics_a_mask_sub_acc_T_65 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_1_2_8) node atomics_a_mask_sub_1_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_65) node atomics_a_mask_sub_2_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_nbit_8) node _atomics_a_mask_sub_acc_T_66 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_2_2_8) node atomics_a_mask_sub_2_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_66) node atomics_a_mask_sub_3_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_bit_8) node _atomics_a_mask_sub_acc_T_67 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_3_2_8) node atomics_a_mask_sub_3_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_67) node atomics_a_mask_sub_4_2_8 = and(atomics_a_mask_sub_sub_2_2_8, atomics_a_mask_sub_nbit_8) node _atomics_a_mask_sub_acc_T_68 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_4_2_8) node atomics_a_mask_sub_4_1_8 = or(atomics_a_mask_sub_sub_2_1_8, _atomics_a_mask_sub_acc_T_68) node atomics_a_mask_sub_5_2_8 = and(atomics_a_mask_sub_sub_2_2_8, atomics_a_mask_sub_bit_8) node _atomics_a_mask_sub_acc_T_69 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_5_2_8) node atomics_a_mask_sub_5_1_8 = or(atomics_a_mask_sub_sub_2_1_8, _atomics_a_mask_sub_acc_T_69) node atomics_a_mask_sub_6_2_8 = and(atomics_a_mask_sub_sub_3_2_8, atomics_a_mask_sub_nbit_8) node _atomics_a_mask_sub_acc_T_70 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_6_2_8) node atomics_a_mask_sub_6_1_8 = or(atomics_a_mask_sub_sub_3_1_8, _atomics_a_mask_sub_acc_T_70) node atomics_a_mask_sub_7_2_8 = and(atomics_a_mask_sub_sub_3_2_8, atomics_a_mask_sub_bit_8) node _atomics_a_mask_sub_acc_T_71 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_7_2_8) node atomics_a_mask_sub_7_1_8 = or(atomics_a_mask_sub_sub_3_1_8, _atomics_a_mask_sub_acc_T_71) node atomics_a_mask_size_8 = bits(atomics_a_mask_sizeOH_8, 0, 0) node atomics_a_mask_bit_8 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_8 = eq(atomics_a_mask_bit_8, UInt<1>(0h0)) node atomics_a_mask_eq_128 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_128 = and(atomics_a_mask_size_8, atomics_a_mask_eq_128) node atomics_a_mask_acc_128 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_128) node atomics_a_mask_eq_129 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_129 = and(atomics_a_mask_size_8, atomics_a_mask_eq_129) node atomics_a_mask_acc_129 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_129) node atomics_a_mask_eq_130 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_130 = and(atomics_a_mask_size_8, atomics_a_mask_eq_130) node atomics_a_mask_acc_130 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_130) node atomics_a_mask_eq_131 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_131 = and(atomics_a_mask_size_8, atomics_a_mask_eq_131) node atomics_a_mask_acc_131 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_131) node atomics_a_mask_eq_132 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_132 = and(atomics_a_mask_size_8, atomics_a_mask_eq_132) node atomics_a_mask_acc_132 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_132) node atomics_a_mask_eq_133 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_133 = and(atomics_a_mask_size_8, atomics_a_mask_eq_133) node atomics_a_mask_acc_133 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_133) node atomics_a_mask_eq_134 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_134 = and(atomics_a_mask_size_8, atomics_a_mask_eq_134) node atomics_a_mask_acc_134 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_134) node atomics_a_mask_eq_135 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_135 = and(atomics_a_mask_size_8, atomics_a_mask_eq_135) node atomics_a_mask_acc_135 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_135) node atomics_a_mask_eq_136 = and(atomics_a_mask_sub_4_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_136 = and(atomics_a_mask_size_8, atomics_a_mask_eq_136) node atomics_a_mask_acc_136 = or(atomics_a_mask_sub_4_1_8, _atomics_a_mask_acc_T_136) node atomics_a_mask_eq_137 = and(atomics_a_mask_sub_4_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_137 = and(atomics_a_mask_size_8, atomics_a_mask_eq_137) node atomics_a_mask_acc_137 = or(atomics_a_mask_sub_4_1_8, _atomics_a_mask_acc_T_137) node atomics_a_mask_eq_138 = and(atomics_a_mask_sub_5_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_138 = and(atomics_a_mask_size_8, atomics_a_mask_eq_138) node atomics_a_mask_acc_138 = or(atomics_a_mask_sub_5_1_8, _atomics_a_mask_acc_T_138) node atomics_a_mask_eq_139 = and(atomics_a_mask_sub_5_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_139 = and(atomics_a_mask_size_8, atomics_a_mask_eq_139) node atomics_a_mask_acc_139 = or(atomics_a_mask_sub_5_1_8, _atomics_a_mask_acc_T_139) node atomics_a_mask_eq_140 = and(atomics_a_mask_sub_6_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_140 = and(atomics_a_mask_size_8, atomics_a_mask_eq_140) node atomics_a_mask_acc_140 = or(atomics_a_mask_sub_6_1_8, _atomics_a_mask_acc_T_140) node atomics_a_mask_eq_141 = and(atomics_a_mask_sub_6_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_141 = and(atomics_a_mask_size_8, atomics_a_mask_eq_141) node atomics_a_mask_acc_141 = or(atomics_a_mask_sub_6_1_8, _atomics_a_mask_acc_T_141) node atomics_a_mask_eq_142 = and(atomics_a_mask_sub_7_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_142 = and(atomics_a_mask_size_8, atomics_a_mask_eq_142) node atomics_a_mask_acc_142 = or(atomics_a_mask_sub_7_1_8, _atomics_a_mask_acc_T_142) node atomics_a_mask_eq_143 = and(atomics_a_mask_sub_7_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_143 = and(atomics_a_mask_size_8, atomics_a_mask_eq_143) node atomics_a_mask_acc_143 = or(atomics_a_mask_sub_7_1_8, _atomics_a_mask_acc_T_143) node atomics_a_mask_lo_lo_lo_8 = cat(atomics_a_mask_acc_129, atomics_a_mask_acc_128) node atomics_a_mask_lo_lo_hi_8 = cat(atomics_a_mask_acc_131, atomics_a_mask_acc_130) node atomics_a_mask_lo_lo_8 = cat(atomics_a_mask_lo_lo_hi_8, atomics_a_mask_lo_lo_lo_8) node atomics_a_mask_lo_hi_lo_8 = cat(atomics_a_mask_acc_133, atomics_a_mask_acc_132) node atomics_a_mask_lo_hi_hi_8 = cat(atomics_a_mask_acc_135, atomics_a_mask_acc_134) node atomics_a_mask_lo_hi_8 = cat(atomics_a_mask_lo_hi_hi_8, atomics_a_mask_lo_hi_lo_8) node atomics_a_mask_lo_8 = cat(atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8) node atomics_a_mask_hi_lo_lo_8 = cat(atomics_a_mask_acc_137, atomics_a_mask_acc_136) node atomics_a_mask_hi_lo_hi_8 = cat(atomics_a_mask_acc_139, atomics_a_mask_acc_138) node atomics_a_mask_hi_lo_8 = cat(atomics_a_mask_hi_lo_hi_8, atomics_a_mask_hi_lo_lo_8) node atomics_a_mask_hi_hi_lo_8 = cat(atomics_a_mask_acc_141, atomics_a_mask_acc_140) node atomics_a_mask_hi_hi_hi_8 = cat(atomics_a_mask_acc_143, atomics_a_mask_acc_142) node atomics_a_mask_hi_hi_8 = cat(atomics_a_mask_hi_hi_hi_8, atomics_a_mask_hi_hi_lo_8) node atomics_a_mask_hi_8 = cat(atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8) node _atomics_a_mask_T_8 = cat(atomics_a_mask_hi_8, atomics_a_mask_lo_8) connect atomics_a_8.mask, _atomics_a_mask_T_8 connect atomics_a_8.data, a_data connect atomics_a_8.corrupt, UInt<1>(0h0) node _atomics_T = eq(UInt<3>(0h4), req.uop.mem_cmd) node _atomics_T_1 = mux(_atomics_T, atomics_a, _atomics_WIRE) node _atomics_T_2 = eq(UInt<4>(0h9), req.uop.mem_cmd) node _atomics_T_3 = mux(_atomics_T_2, atomics_a_1, _atomics_T_1) node _atomics_T_4 = eq(UInt<4>(0ha), req.uop.mem_cmd) node _atomics_T_5 = mux(_atomics_T_4, atomics_a_2, _atomics_T_3) node _atomics_T_6 = eq(UInt<4>(0hb), req.uop.mem_cmd) node _atomics_T_7 = mux(_atomics_T_6, atomics_a_3, _atomics_T_5) node _atomics_T_8 = eq(UInt<4>(0h8), req.uop.mem_cmd) node _atomics_T_9 = mux(_atomics_T_8, atomics_a_4, _atomics_T_7) node _atomics_T_10 = eq(UInt<4>(0hc), req.uop.mem_cmd) node _atomics_T_11 = mux(_atomics_T_10, atomics_a_5, _atomics_T_9) node _atomics_T_12 = eq(UInt<4>(0hd), req.uop.mem_cmd) node _atomics_T_13 = mux(_atomics_T_12, atomics_a_6, _atomics_T_11) node _atomics_T_14 = eq(UInt<4>(0he), req.uop.mem_cmd) node _atomics_T_15 = mux(_atomics_T_14, atomics_a_7, _atomics_T_13) node _atomics_T_16 = eq(UInt<4>(0hf), req.uop.mem_cmd) node atomics = mux(_atomics_T_16, atomics_a_8, _atomics_T_15) node _T = eq(state, UInt<2>(0h0)) node _T_1 = neq(req.uop.mem_cmd, UInt<3>(0h7)) node _T_2 = or(_T, _T_1) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:454 assert(state === s_idle \|\| req.uop.mem_cmd =/= M_XSC)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_mem_access_valid_T = eq(state, UInt<2>(0h1)) connect io.mem_access.valid, _io_mem_access_valid_T node _io_mem_access_bits_T = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _io_mem_access_bits_T_1 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _io_mem_access_bits_T_2 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _io_mem_access_bits_T_3 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _io_mem_access_bits_T_4 = or(_io_mem_access_bits_T, _io_mem_access_bits_T_1) node _io_mem_access_bits_T_5 = or(_io_mem_access_bits_T_4, _io_mem_access_bits_T_2) node _io_mem_access_bits_T_6 = or(_io_mem_access_bits_T_5, _io_mem_access_bits_T_3) node _io_mem_access_bits_T_7 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _io_mem_access_bits_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _io_mem_access_bits_T_9 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _io_mem_access_bits_T_10 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _io_mem_access_bits_T_11 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _io_mem_access_bits_T_12 = or(_io_mem_access_bits_T_7, _io_mem_access_bits_T_8) node _io_mem_access_bits_T_13 = or(_io_mem_access_bits_T_12, _io_mem_access_bits_T_9) node _io_mem_access_bits_T_14 = or(_io_mem_access_bits_T_13, _io_mem_access_bits_T_10) node _io_mem_access_bits_T_15 = or(_io_mem_access_bits_T_14, _io_mem_access_bits_T_11) node _io_mem_access_bits_T_16 = or(_io_mem_access_bits_T_6, _io_mem_access_bits_T_15) node _io_mem_access_bits_T_17 = eq(req.uop.mem_cmd, UInt<1>(0h0)) node _io_mem_access_bits_T_18 = eq(req.uop.mem_cmd, UInt<5>(0h10)) node _io_mem_access_bits_T_19 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _io_mem_access_bits_T_20 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _io_mem_access_bits_T_21 = or(_io_mem_access_bits_T_17, _io_mem_access_bits_T_18) node _io_mem_access_bits_T_22 = or(_io_mem_access_bits_T_21, _io_mem_access_bits_T_19) node _io_mem_access_bits_T_23 = or(_io_mem_access_bits_T_22, _io_mem_access_bits_T_20) node _io_mem_access_bits_T_24 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _io_mem_access_bits_T_25 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _io_mem_access_bits_T_26 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _io_mem_access_bits_T_27 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _io_mem_access_bits_T_28 = or(_io_mem_access_bits_T_24, _io_mem_access_bits_T_25) node _io_mem_access_bits_T_29 = or(_io_mem_access_bits_T_28, _io_mem_access_bits_T_26) node _io_mem_access_bits_T_30 = or(_io_mem_access_bits_T_29, _io_mem_access_bits_T_27) node _io_mem_access_bits_T_31 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _io_mem_access_bits_T_32 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _io_mem_access_bits_T_33 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _io_mem_access_bits_T_34 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _io_mem_access_bits_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _io_mem_access_bits_T_36 = or(_io_mem_access_bits_T_31, _io_mem_access_bits_T_32) node _io_mem_access_bits_T_37 = or(_io_mem_access_bits_T_36, _io_mem_access_bits_T_33) node _io_mem_access_bits_T_38 = or(_io_mem_access_bits_T_37, _io_mem_access_bits_T_34) node _io_mem_access_bits_T_39 = or(_io_mem_access_bits_T_38, _io_mem_access_bits_T_35) node _io_mem_access_bits_T_40 = or(_io_mem_access_bits_T_30, _io_mem_access_bits_T_39) node _io_mem_access_bits_T_41 = or(_io_mem_access_bits_T_23, _io_mem_access_bits_T_40) node _io_mem_access_bits_T_42 = mux(_io_mem_access_bits_T_41, get, put) node _io_mem_access_bits_T_43 = mux(_io_mem_access_bits_T_16, atomics, _io_mem_access_bits_T_42) connect io.mem_access.bits, _io_mem_access_bits_T_43 node _send_resp_T = eq(req.uop.mem_cmd, UInt<1>(0h0)) node _send_resp_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h10)) node _send_resp_T_2 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _send_resp_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _send_resp_T_4 = or(_send_resp_T, _send_resp_T_1) node _send_resp_T_5 = or(_send_resp_T_4, _send_resp_T_2) node _send_resp_T_6 = or(_send_resp_T_5, _send_resp_T_3) node _send_resp_T_7 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _send_resp_T_8 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _send_resp_T_9 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _send_resp_T_10 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _send_resp_T_11 = or(_send_resp_T_7, _send_resp_T_8) node _send_resp_T_12 = or(_send_resp_T_11, _send_resp_T_9) node _send_resp_T_13 = or(_send_resp_T_12, _send_resp_T_10) node _send_resp_T_14 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _send_resp_T_15 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _send_resp_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _send_resp_T_17 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _send_resp_T_18 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _send_resp_T_19 = or(_send_resp_T_14, _send_resp_T_15) node _send_resp_T_20 = or(_send_resp_T_19, _send_resp_T_16) node _send_resp_T_21 = or(_send_resp_T_20, _send_resp_T_17) node _send_resp_T_22 = or(_send_resp_T_21, _send_resp_T_18) node _send_resp_T_23 = or(_send_resp_T_13, _send_resp_T_22) node send_resp = or(_send_resp_T_6, _send_resp_T_23) node _io_resp_valid_T = eq(state, UInt<2>(0h3)) node _io_resp_valid_T_1 = and(_io_resp_valid_T, send_resp) connect io.resp.valid, _io_resp_valid_T_1 connect io.resp.bits.is_hella, req.is_hella connect io.resp.bits.uop, req.uop node _io_resp_bits_data_shifted_T = bits(req.addr, 2, 2) node _io_resp_bits_data_shifted_T_1 = bits(grant_word, 63, 32) node _io_resp_bits_data_shifted_T_2 = bits(grant_word, 31, 0) node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2) node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted) node _io_resp_bits_data_T = eq(size, UInt<2>(0h2)) node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero) node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31) node _io_resp_bits_data_T_3 = and(req.uop.mem_signed, _io_resp_bits_data_T_2) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_resp_bits_data_T_5 = bits(grant_word, 63, 32) node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5) node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed) node _io_resp_bits_data_shifted_T_3 = bits(req.addr, 1, 1) node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16) node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0) node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5) node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1) node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1) node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15) node _io_resp_bits_data_T_11 = and(req.uop.mem_signed, _io_resp_bits_data_T_10) node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16) node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13) node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1) node _io_resp_bits_data_shifted_T_6 = bits(req.addr, 0, 0) node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8) node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0) node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8) node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2) node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2) node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7) node _io_resp_bits_data_T_19 = and(req.uop.mem_signed, _io_resp_bits_data_T_18) node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8) node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21) node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2) connect io.resp.bits.data, _io_resp_bits_data_T_23 node _T_6 = and(io.req.ready, io.req.valid) when _T_6 : connect req, io.req.bits connect state, UInt<2>(0h1) node _T_7 = and(io.mem_access.ready, io.mem_access.valid) when _T_7 : connect state, UInt<2>(0h2) node _T_8 = eq(state, UInt<2>(0h2)) node _T_9 = and(_T_8, io.mem_ack.valid) when _T_9 : connect state, UInt<2>(0h3) node _T_10 = eq(req.uop.mem_cmd, UInt<1>(0h0)) node _T_11 = eq(req.uop.mem_cmd, UInt<5>(0h10)) node _T_12 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _T_13 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _T_14 = or(_T_10, _T_11) node _T_15 = or(_T_14, _T_12) node _T_16 = or(_T_15, _T_13) node _T_17 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _T_18 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _T_19 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _T_20 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _T_21 = or(_T_17, _T_18) node _T_22 = or(_T_21, _T_19) node _T_23 = or(_T_22, _T_20) node _T_24 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _T_25 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _T_26 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _T_27 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _T_28 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _T_29 = or(_T_24, _T_25) node _T_30 = or(_T_29, _T_26) node _T_31 = or(_T_30, _T_27) node _T_32 = or(_T_31, _T_28) node _T_33 = or(_T_23, _T_32) node _T_34 = or(_T_16, _T_33) when _T_34 : node _grant_word_shift_T = bits(req.addr, 3, 3) node grant_word_shift = cat(_grant_word_shift_T, UInt<6>(0h0)) node _grant_word_T = dshr(io.mem_ack.bits.data, grant_word_shift) node _grant_word_T_1 = bits(_grant_word_T, 63, 0) connect grant_word, _grant_word_T_1 node _T_35 = eq(state, UInt<2>(0h3)) when _T_35 : node _T_36 = eq(send_resp, UInt<1>(0h0)) node _T_37 = and(io.resp.ready, io.resp.valid) node _T_38 = or(_T_36, _T_37) when _T_38 : connect state, UInt<2>(0h0)	module BoomIOMSHR( // @[mshrs.scala:402:7] input clock, // @[mshrs.scala:402:7] input reset, // @[mshrs.scala:402:7] output io_req_ready, // @[mshrs.scala:405:14] input io_req_valid, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_uopc, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_inst, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_debug_inst, // @[mshrs.scala:405:14] input io_req_bits_uop_is_rvc, // @[mshrs.scala:405:14] input [39:0] io_req_bits_uop_debug_pc, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_iq_type, // @[mshrs.scala:405:14] input [9:0] io_req_bits_uop_fu_code, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_iw_state, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_is_br, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jalr, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jal, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sfb, // @[mshrs.scala:405:14] input [15:0] io_req_bits_uop_br_mask, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_br_tag, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ftq_idx, // @[mshrs.scala:405:14] input io_req_bits_uop_edge_inst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_pc_lob, // @[mshrs.scala:405:14] input io_req_bits_uop_taken, // @[mshrs.scala:405:14] input [19:0] io_req_bits_uop_imm_packed, // @[mshrs.scala:405:14] input [11:0] io_req_bits_uop_csr_addr, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_rob_idx, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ldq_idx, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_stq_idx, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_rxq_idx, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_pdst, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs1, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs2, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs3, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ppred, // @[mshrs.scala:405:14] input io_req_bits_uop_prs1_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs2_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs3_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_ppred_busy, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_stale_pdst, // @[mshrs.scala:405:14] input io_req_bits_uop_exception, // @[mshrs.scala:405:14] input [63:0] io_req_bits_uop_exc_cause, // @[mshrs.scala:405:14] input io_req_bits_uop_bypassable, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_mem_cmd, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_mem_size, // @[mshrs.scala:405:14] input io_req_bits_uop_mem_signed, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fence, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fencei, // @[mshrs.scala:405:14] input io_req_bits_uop_is_amo, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_ldq, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_stq, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] input io_req_bits_uop_is_unique, // @[mshrs.scala:405:14] input io_req_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_ldst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs2, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs3, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_val, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_dst_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] input io_req_bits_uop_frs3_en, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_val, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_single, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] input [39:0] io_req_bits_addr, // @[mshrs.scala:405:14] input [63:0] io_req_bits_data, // @[mshrs.scala:405:14] input io_req_bits_is_hella, // @[mshrs.scala:405:14] input io_resp_ready, // @[mshrs.scala:405:14] output io_resp_valid, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:405:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:405:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:405:14] output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:405:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:405:14] output io_resp_bits_uop_taken, // @[mshrs.scala:405:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:405:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:405:14] output io_resp_bits_uop_exception, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:405:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:405:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:405:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:405:14] output io_resp_bits_is_hella, // @[mshrs.scala:405:14] input io_mem_access_ready, // @[mshrs.scala:405:14] output io_mem_access_valid, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_opcode, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_param, // @[mshrs.scala:405:14] output [3:0] io_mem_access_bits_size, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_source, // @[mshrs.scala:405:14] output [31:0] io_mem_access_bits_address, // @[mshrs.scala:405:14] output [15:0] io_mem_access_bits_mask, // @[mshrs.scala:405:14] output [127:0] io_mem_access_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_valid, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_opcode, // @[mshrs.scala:405:14] input [1:0] io_mem_ack_bits_param, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_size, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_source, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_sink, // @[mshrs.scala:405:14] input io_mem_ack_bits_denied, // @[mshrs.scala:405:14] input [127:0] io_mem_ack_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_bits_corrupt // @[mshrs.scala:405:14] ); wire io_req_valid_0 = io_req_valid; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[mshrs.scala:402:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[mshrs.scala:402:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[mshrs.scala:402:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[mshrs.scala:402:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[mshrs.scala:402:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[mshrs.scala:402:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[mshrs.scala:402:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[mshrs.scala:402:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[mshrs.scala:402:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[mshrs.scala:402:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[mshrs.scala:402:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[mshrs.scala:402:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[mshrs.scala:402:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[mshrs.scala:402:7] wire io_req_bits_is_hella_0 = io_req_bits_is_hella; // @[mshrs.scala:402:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:402:7] wire io_mem_access_ready_0 = io_mem_access_ready; // @[mshrs.scala:402:7] wire io_mem_ack_valid_0 = io_mem_ack_valid; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_opcode_0 = io_mem_ack_bits_opcode; // @[mshrs.scala:402:7] wire [1:0] io_mem_ack_bits_param_0 = io_mem_ack_bits_param; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_size_0 = io_mem_ack_bits_size; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_source_0 = io_mem_ack_bits_source; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_sink_0 = io_mem_ack_bits_sink; // @[mshrs.scala:402:7] wire io_mem_ack_bits_denied_0 = io_mem_ack_bits_denied; // @[mshrs.scala:402:7] wire [127:0] io_mem_ack_bits_data_0 = io_mem_ack_bits_data; // @[mshrs.scala:402:7] wire io_mem_ack_bits_corrupt_0 = io_mem_ack_bits_corrupt; // @[mshrs.scala:402:7] wire io_mem_access_bits_corrupt = 1'h0; // @[mshrs.scala:402:7] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire get_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire put_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_WIRE_corrupt = 1'h0; // @[mshrs.scala:439:46] wire _atomics_legal_T_34 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_40 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_93 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_99 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_152 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_158 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_2 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_211 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_217 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_3 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_270 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_276 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_4 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_329 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_335 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_5 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_388 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_394 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_6 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_447 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_453 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_7 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_506 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_512 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_8 = 1'h0; // @[Misc.scala:206:21] wire _atomics_T_1_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_3_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_5_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_7_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_9_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_11_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_13_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_15_corrupt = 1'h0; // @[mshrs.scala:439:75] wire atomics_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_42_corrupt = 1'h0; // @[mshrs.scala:457:66] wire _io_mem_access_bits_T_43_corrupt = 1'h0; // @[mshrs.scala:457:29] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire [2:0] get_source = 3'h5; // @[Edges.scala:460:17] wire [2:0] put_source = 3'h5; // @[Edges.scala:480:17] wire [2:0] atomics_a_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_source = 3'h5; // @[mshrs.scala:457:66] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[mshrs.scala:439:46] wire [2:0] _atomics_WIRE_param = 3'h0; // @[mshrs.scala:439:46] wire [2:0] _atomics_WIRE_source = 3'h0; // @[mshrs.scala:439:46] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_param = 3'h0; // @[mshrs.scala:457:66] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_41 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_42 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_43 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_44 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_59 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_100 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_101 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_102 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_103 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_118 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_119 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_120 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_121 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_159 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_160 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_161 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_177 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_178 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_179 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_180 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_220 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_221 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_236 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_237 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_238 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_239 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_277 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_278 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_279 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_280 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_295 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_296 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_297 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_298 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_336 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_337 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_338 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_339 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_354 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_355 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_356 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_357 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_395 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_396 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_397 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_398 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_413 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_414 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_415 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_416 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_454 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_455 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_456 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_457 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_472 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_473 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_474 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_475 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_513 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_514 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_515 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_516 = 1'h1; // @[Parameters.scala:684:29] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [127:0] get_data = 128'h0; // @[Edges.scala:460:17] wire [127:0] _atomics_WIRE_data = 128'h0; // @[mshrs.scala:439:46] wire [15:0] _atomics_WIRE_mask = 16'h0; // @[mshrs.scala:439:46] wire [31:0] _atomics_WIRE_address = 32'h0; // @[mshrs.scala:439:46] wire [3:0] _atomics_WIRE_size = 4'h0; // @[mshrs.scala:439:46] wire _io_req_ready_T; // @[mshrs.scala:427:25] wire _io_resp_valid_T_1; // @[mshrs.scala:461:43] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_mem_access_valid_T; // @[mshrs.scala:456:32] wire [2:0] _io_mem_access_bits_T_43_opcode; // @[mshrs.scala:457:29] wire [2:0] _io_mem_access_bits_T_43_param; // @[mshrs.scala:457:29] wire [3:0] _io_mem_access_bits_T_43_size; // @[mshrs.scala:457:29] wire [2:0] _io_mem_access_bits_T_43_source; // @[mshrs.scala:457:29] wire [31:0] _io_mem_access_bits_T_43_address; // @[mshrs.scala:457:29] wire [15:0] _io_mem_access_bits_T_43_mask; // @[mshrs.scala:457:29] wire [127:0] _io_mem_access_bits_T_43_data; // @[mshrs.scala:457:29] wire io_req_ready_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:402:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:402:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:402:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:402:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:402:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:402:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:402:7] wire io_resp_valid_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_opcode_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_param_0; // @[mshrs.scala:402:7] wire [3:0] io_mem_access_bits_size_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_source_0; // @[mshrs.scala:402:7] wire [31:0] io_mem_access_bits_address_0; // @[mshrs.scala:402:7] wire [15:0] io_mem_access_bits_mask_0; // @[mshrs.scala:402:7] wire [127:0] io_mem_access_bits_data_0; // @[mshrs.scala:402:7] wire io_mem_access_valid_0; // @[mshrs.scala:402:7] reg [6:0] req_uop_uopc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uopc_0 = req_uop_uopc; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_inst_0 = req_uop_inst; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_inst_0 = req_uop_debug_inst; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_rvc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_rvc_0 = req_uop_is_rvc; // @[mshrs.scala:402:7, :421:16] reg [39:0] req_uop_debug_pc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_pc_0 = req_uop_debug_pc; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_iq_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iq_type_0 = req_uop_iq_type; // @[mshrs.scala:402:7, :421:16] reg [9:0] req_uop_fu_code; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fu_code_0 = req_uop_fu_code; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_br_type_0 = req_uop_ctrl_br_type; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op1_sel_0 = req_uop_ctrl_op1_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op2_sel_0 = req_uop_ctrl_op2_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_imm_sel_0 = req_uop_ctrl_imm_sel; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op_fcn_0 = req_uop_ctrl_op_fcn; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_fcn_dw_0 = req_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_csr_cmd_0 = req_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_load; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_load_0 = req_uop_ctrl_is_load; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_sta; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_sta_0 = req_uop_ctrl_is_sta; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_std; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_std_0 = req_uop_ctrl_is_std; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_iw_state; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_state_0 = req_uop_iw_state; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p1_poisoned_0 = req_uop_iw_p1_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p2_poisoned_0 = req_uop_iw_p2_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_br; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_br_0 = req_uop_is_br; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jalr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jalr_0 = req_uop_is_jalr; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jal; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jal_0 = req_uop_is_jal; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sfb; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sfb_0 = req_uop_is_sfb; // @[mshrs.scala:402:7, :421:16] reg [15:0] req_uop_br_mask; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_mask_0 = req_uop_br_mask; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_br_tag; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_tag_0 = req_uop_br_tag; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ftq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ftq_idx_0 = req_uop_ftq_idx; // @[mshrs.scala:402:7, :421:16] reg req_uop_edge_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_edge_inst_0 = req_uop_edge_inst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pc_lob_0 = req_uop_pc_lob; // @[mshrs.scala:402:7, :421:16] reg req_uop_taken; // @[mshrs.scala:421:16] assign io_resp_bits_uop_taken_0 = req_uop_taken; // @[mshrs.scala:402:7, :421:16] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_imm_packed_0 = req_uop_imm_packed; // @[mshrs.scala:402:7, :421:16] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_csr_addr_0 = req_uop_csr_addr; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_rob_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rob_idx_0 = req_uop_rob_idx; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ldq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldq_idx_0 = req_uop_ldq_idx; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_stq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stq_idx_0 = req_uop_stq_idx; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rxq_idx_0 = req_uop_rxq_idx; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pdst_0 = req_uop_pdst; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_0 = req_uop_prs1; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_0 = req_uop_prs2; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_0 = req_uop_prs3; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ppred; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_0 = req_uop_ppred; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs1_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_busy_0 = req_uop_prs1_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs2_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_busy_0 = req_uop_prs2_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs3_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_busy_0 = req_uop_prs3_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_ppred_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_busy_0 = req_uop_ppred_busy; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stale_pdst_0 = req_uop_stale_pdst; // @[mshrs.scala:402:7, :421:16] reg req_uop_exception; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exception_0 = req_uop_exception; // @[mshrs.scala:402:7, :421:16] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exc_cause_0 = req_uop_exc_cause; // @[mshrs.scala:402:7, :421:16] reg req_uop_bypassable; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bypassable_0 = req_uop_bypassable; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_cmd_0 = req_uop_mem_cmd; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_mem_size; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_size_0 = req_uop_mem_size; // @[mshrs.scala:402:7, :421:16] wire [1:0] size = req_uop_mem_size; // @[AMOALU.scala:11:18] reg req_uop_mem_signed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_signed_0 = req_uop_mem_signed; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fence; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fence_0 = req_uop_is_fence; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fencei; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fencei_0 = req_uop_is_fencei; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_amo; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_amo_0 = req_uop_is_amo; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_ldq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_ldq_0 = req_uop_uses_ldq; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_stq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_stq_0 = req_uop_uses_stq; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sys_pc2epc_0 = req_uop_is_sys_pc2epc; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_unique; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_unique_0 = req_uop_is_unique; // @[mshrs.scala:402:7, :421:16] reg req_uop_flush_on_commit; // @[mshrs.scala:421:16] assign io_resp_bits_uop_flush_on_commit_0 = req_uop_flush_on_commit; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_is_rs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_is_rs1_0 = req_uop_ldst_is_rs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_ldst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_0 = req_uop_ldst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_0 = req_uop_lrs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_0 = req_uop_lrs2; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs3_0 = req_uop_lrs3; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_val_0 = req_uop_ldst_val; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_dst_rtype_0 = req_uop_dst_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_rtype_0 = req_uop_lrs1_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_rtype_0 = req_uop_lrs2_rtype; // @[mshrs.scala:402:7, :421:16] reg req_uop_frs3_en; // @[mshrs.scala:421:16] assign io_resp_bits_uop_frs3_en_0 = req_uop_frs3_en; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_val_0 = req_uop_fp_val; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_single; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_single_0 = req_uop_fp_single; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_pf_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_pf_if_0 = req_uop_xcpt_pf_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ae_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ae_if_0 = req_uop_xcpt_ae_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ma_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ma_if_0 = req_uop_xcpt_ma_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_debug_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_debug_if_0 = req_uop_bp_debug_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_xcpt_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_xcpt_if_0 = req_uop_bp_xcpt_if; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_fsrc_0 = req_uop_debug_fsrc; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_tsrc_0 = req_uop_debug_tsrc; // @[mshrs.scala:402:7, :421:16] reg [39:0] req_addr; // @[mshrs.scala:421:16] wire [39:0] _get_legal_T_14 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_14 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_4 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_63 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_122 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_181 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_240 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_299 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_358 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_417 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_476 = req_addr; // @[Parameters.scala:137:31] reg [63:0] req_data; // @[mshrs.scala:421:16] reg req_is_hella; // @[mshrs.scala:421:16] assign io_resp_bits_is_hella_0 = req_is_hella; // @[mshrs.scala:402:7, :421:16] reg [63:0] grant_word; // @[mshrs.scala:422:23] reg [1:0] state; // @[mshrs.scala:426:22] assign _io_req_ready_T = state == 2'h0; // @[mshrs.scala:426:22, :427:25] assign io_req_ready_0 = _io_req_ready_T; // @[mshrs.scala:402:7, :427:25] wire [127:0] a_data = {2{req_data}}; // @[mshrs.scala:421:16, :434:23] wire [127:0] put_data = a_data; // @[Edges.scala:480:17] wire [127:0] atomics_a_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_1_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_2_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_3_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_4_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_5_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_6_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_7_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_8_data = a_data; // @[Edges.scala:517:17] wire [39:0] _GEN = {req_addr[39:14], req_addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_62 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_0 = {req_addr[39:17], req_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31] assign _put_legal_T_63 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_35; // @[Parameters.scala:137:31] assign _atomics_legal_T_35 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_94; // @[Parameters.scala:137:31] assign _atomics_legal_T_94 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_153; // @[Parameters.scala:137:31] assign _atomics_legal_T_153 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_212; // @[Parameters.scala:137:31] assign _atomics_legal_T_212 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_271; // @[Parameters.scala:137:31] assign _atomics_legal_T_271 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_330; // @[Parameters.scala:137:31] assign _atomics_legal_T_330 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_389; // @[Parameters.scala:137:31] assign _atomics_legal_T_389 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_448; // @[Parameters.scala:137:31] assign _atomics_legal_T_448 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_507; // @[Parameters.scala:137:31] assign _atomics_legal_T_507 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {req_addr[39:26], req_addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {req_addr[39:28], req_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31] assign _put_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_45; // @[Parameters.scala:137:31] assign _atomics_legal_T_45 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_104; // @[Parameters.scala:137:31] assign _atomics_legal_T_104 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_163; // @[Parameters.scala:137:31] assign _atomics_legal_T_163 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_222; // @[Parameters.scala:137:31] assign _atomics_legal_T_222 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_281; // @[Parameters.scala:137:31] assign _atomics_legal_T_281 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_340; // @[Parameters.scala:137:31] assign _atomics_legal_T_340 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_399; // @[Parameters.scala:137:31] assign _atomics_legal_T_399 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_458; // @[Parameters.scala:137:31] assign _atomics_legal_T_458 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_517; // @[Parameters.scala:137:31] assign _atomics_legal_T_517 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {req_addr[39:29], req_addr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31] assign _get_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31] assign _put_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31] assign _atomics_legal_T_24 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31] assign _atomics_legal_T_142 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_201; // @[Parameters.scala:137:31] assign _atomics_legal_T_201 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_260; // @[Parameters.scala:137:31] assign _atomics_legal_T_260 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_319; // @[Parameters.scala:137:31] assign _atomics_legal_T_319 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_378; // @[Parameters.scala:137:31] assign _atomics_legal_T_378 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_437; // @[Parameters.scala:137:31] assign _atomics_legal_T_437 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_496; // @[Parameters.scala:137:31] assign _atomics_legal_T_496 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46] wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] get_address = req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] atomics_a_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [39:0] _GEN_4 = {req_addr[39:32], req_addr[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31] assign _get_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31] assign _put_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_50; // @[Parameters.scala:137:31] assign _atomics_legal_T_50 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_109; // @[Parameters.scala:137:31] assign _atomics_legal_T_109 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_168; // @[Parameters.scala:137:31] assign _atomics_legal_T_168 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_227; // @[Parameters.scala:137:31] assign _atomics_legal_T_227 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_286; // @[Parameters.scala:137:31] assign _atomics_legal_T_286 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_345; // @[Parameters.scala:137:31] assign _atomics_legal_T_345 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_404; // @[Parameters.scala:137:31] assign _atomics_legal_T_404 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_463; // @[Parameters.scala:137:31] assign _atomics_legal_T_463 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_522; // @[Parameters.scala:137:31] assign _atomics_legal_T_522 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46] wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_54 = _get_legal_T_18 \| _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_55 = _get_legal_T_54 \| _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_56 = _get_legal_T_55 \| _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_57 = _get_legal_T_56 \| _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_58 = _get_legal_T_57 \| _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_59 = _get_legal_T_58 \| _get_legal_T_48; // @[Parameters.scala:685:42] wire _get_legal_T_60 = _get_legal_T_59 \| _get_legal_T_53; // @[Parameters.scala:685:42] wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_62 \| _get_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [15:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [15:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_5 = {2'h0, req_uop_mem_size}; // @[Edges.scala:463:15] assign get_size = _GEN_5; // @[Edges.scala:460:17, :463:15] wire [3:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_5; // @[Misc.scala:202:34] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_5; // @[Edges.scala:463:15, :480:17] wire [3:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_5; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_size = get_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_sub_bit = req_addr[3]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_sub_bit = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_1 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_2 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_3 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_4 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_5 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_6 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_7 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_8 = req_addr[3]; // @[Misc.scala:210:26] wire _grant_word_shift_T = req_addr[3]; // @[package.scala:163:13] wire get_a_mask_sub_sub_sub_1_2 = get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_sub_nbit = ~get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_sub_0_2 = get_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_sub_acc_T = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_0_1 = _get_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _get_a_mask_sub_sub_sub_acc_T_1 = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_1_1 = _get_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = req_addr[2]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T = req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_2_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T_2 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_2_1 = get_a_mask_sub_sub_sub_1_1 \| _get_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_3_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_3 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_3_1 = get_a_mask_sub_sub_sub_1_1 \| _get_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = req_addr[1]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_3 = req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_4_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_4 = get_a_mask_sub_size & get_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_4_1 = get_a_mask_sub_sub_2_1 \| _get_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_5_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_5 = get_a_mask_sub_size & get_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_5_1 = get_a_mask_sub_sub_2_1 \| _get_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_6_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_6 = get_a_mask_sub_size & get_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_6_1 = get_a_mask_sub_sub_3_1 \| _get_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_7_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_7 = get_a_mask_sub_size & get_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_7_1 = get_a_mask_sub_sub_3_1 \| _get_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = req_addr[0]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_6 = req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 \| _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 \| _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_8 = get_a_mask_sub_4_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_8 = get_a_mask_size & get_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_8 = get_a_mask_sub_4_1 \| _get_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_9 = get_a_mask_sub_4_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_9 = get_a_mask_size & get_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_9 = get_a_mask_sub_4_1 \| _get_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_10 = get_a_mask_sub_5_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_10 = get_a_mask_size & get_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_10 = get_a_mask_sub_5_1 \| _get_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_11 = get_a_mask_sub_5_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_11 = get_a_mask_size & get_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_11 = get_a_mask_sub_5_1 \| _get_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_12 = get_a_mask_sub_6_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_12 = get_a_mask_size & get_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_12 = get_a_mask_sub_6_1 \| _get_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_13 = get_a_mask_sub_6_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_13 = get_a_mask_size & get_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_13 = get_a_mask_sub_6_1 \| _get_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_14 = get_a_mask_sub_7_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_14 = get_a_mask_size & get_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_14 = get_a_mask_sub_7_1 \| _get_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_15 = get_a_mask_sub_7_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_15 = get_a_mask_size & get_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_15 = get_a_mask_sub_7_1 \| _get_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_lo = {get_a_mask_lo_lo_hi, get_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_lo_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_hi = {get_a_mask_lo_hi_hi, get_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo_lo = {get_a_mask_acc_9, get_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_lo_hi = {get_a_mask_acc_11, get_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_lo = {get_a_mask_hi_lo_hi, get_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_hi_lo = {get_a_mask_acc_13, get_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi_hi = {get_a_mask_acc_15, get_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_hi = {get_a_mask_hi_hi_hi, get_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_69 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_6 = {req_addr[39:21], req_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31] assign _atomics_legal_T_68 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31] assign _atomics_legal_T_127 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31] assign _atomics_legal_T_186 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31] assign _atomics_legal_T_245 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31] assign _atomics_legal_T_304 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_363; // @[Parameters.scala:137:31] assign _atomics_legal_T_363 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_422; // @[Parameters.scala:137:31] assign _atomics_legal_T_422 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_481; // @[Parameters.scala:137:31] assign _atomics_legal_T_481 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_7 = {req_addr[39:26], req_addr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31] assign _atomics_legal_T_73 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31] assign _atomics_legal_T_132 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31] assign _atomics_legal_T_191 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31] assign _atomics_legal_T_250 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_309; // @[Parameters.scala:137:31] assign _atomics_legal_T_309 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_368; // @[Parameters.scala:137:31] assign _atomics_legal_T_368 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_427; // @[Parameters.scala:137:31] assign _atomics_legal_T_427 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_486; // @[Parameters.scala:137:31] assign _atomics_legal_T_486 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46] wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46] wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46] wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_54 = _put_legal_T_18 \| _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_55 = _put_legal_T_54 \| _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_56 = _put_legal_T_55 \| _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_57 = _put_legal_T_56 \| _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_58 = _put_legal_T_57 \| _put_legal_T_43; // @[Parameters.scala:685:42] wire _put_legal_T_59 = _put_legal_T_58 \| _put_legal_T_48; // @[Parameters.scala:685:42] wire _put_legal_T_60 = _put_legal_T_59 \| _put_legal_T_53; // @[Parameters.scala:685:42] wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46] wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_70 = _put_legal_T_69 \| _put_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_70; // @[Parameters.scala:686:26] wire [15:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [15:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_size = put_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_sub_1_2 = put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_sub_nbit = ~put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_sub_0_2 = put_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_sub_acc_T = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_0_1 = _put_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _put_a_mask_sub_sub_sub_acc_T_1 = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_1_1 = _put_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_2_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T_2 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_2_1 = put_a_mask_sub_sub_sub_1_1 \| _put_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_3_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_3 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_3_1 = put_a_mask_sub_sub_sub_1_1 \| _put_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_4_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_4 = put_a_mask_sub_size & put_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_4_1 = put_a_mask_sub_sub_2_1 \| _put_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_5_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_5 = put_a_mask_sub_size & put_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_5_1 = put_a_mask_sub_sub_2_1 \| _put_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_6_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_6 = put_a_mask_sub_size & put_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_6_1 = put_a_mask_sub_sub_3_1 \| _put_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_7_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_7 = put_a_mask_sub_size & put_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_7_1 = put_a_mask_sub_sub_3_1 \| _put_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 \| _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 \| _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_8 = put_a_mask_sub_4_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_8 = put_a_mask_size & put_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_8 = put_a_mask_sub_4_1 \| _put_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_9 = put_a_mask_sub_4_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_9 = put_a_mask_size & put_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_9 = put_a_mask_sub_4_1 \| _put_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_10 = put_a_mask_sub_5_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_10 = put_a_mask_size & put_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_10 = put_a_mask_sub_5_1 \| _put_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_11 = put_a_mask_sub_5_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_11 = put_a_mask_size & put_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_11 = put_a_mask_sub_5_1 \| _put_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_12 = put_a_mask_sub_6_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_12 = put_a_mask_size & put_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_12 = put_a_mask_sub_6_1 \| _put_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_13 = put_a_mask_sub_6_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_13 = put_a_mask_size & put_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_13 = put_a_mask_sub_6_1 \| _put_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_14 = put_a_mask_sub_7_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_14 = put_a_mask_size & put_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_14 = put_a_mask_sub_7_1 \| _put_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_15 = put_a_mask_sub_7_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_15 = put_a_mask_size & put_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_15 = put_a_mask_sub_7_1 \| _put_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_lo = {put_a_mask_lo_lo_hi, put_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_lo_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_hi = {put_a_mask_lo_hi_hi, put_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo_lo = {put_a_mask_acc_9, put_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_lo_hi = {put_a_mask_acc_11, put_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_lo = {put_a_mask_hi_lo_hi, put_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_hi_lo = {put_a_mask_acc_13, put_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi_hi = {put_a_mask_acc_15, put_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_hi = {put_a_mask_hi_hi_hi, put_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {req_addr[39:28], req_addr[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31] assign _atomics_legal_T_19 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31] assign _atomics_legal_T_78 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31] assign _atomics_legal_T_137 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31] assign _atomics_legal_T_196 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_255; // @[Parameters.scala:137:31] assign _atomics_legal_T_255 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_314; // @[Parameters.scala:137:31] assign _atomics_legal_T_314 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_373; // @[Parameters.scala:137:31] assign _atomics_legal_T_373 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_432; // @[Parameters.scala:137:31] assign _atomics_legal_T_432 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_491; // @[Parameters.scala:137:31] assign _atomics_legal_T_491 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46] wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46] wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_29 = _atomics_legal_T_8 \| _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_30 = _atomics_legal_T_29 \| _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_31 = _atomics_legal_T_30 \| _atomics_legal_T_23; // @[Parameters.scala:685:42] wire _atomics_legal_T_32 = _atomics_legal_T_31 \| _atomics_legal_T_28; // @[Parameters.scala:685:42] wire _atomics_legal_T_33 = _atomics_legal_T_32; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_57 = _atomics_legal_T_33; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_36 = {1'h0, _atomics_legal_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_38 = _atomics_legal_T_37; // @[Parameters.scala:137:46] wire _atomics_legal_T_39 = _atomics_legal_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_46 = {1'h0, _atomics_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_47 = _atomics_legal_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_48 = _atomics_legal_T_47; // @[Parameters.scala:137:46] wire _atomics_legal_T_49 = _atomics_legal_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_51 = {1'h0, _atomics_legal_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_52 = _atomics_legal_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_53 = _atomics_legal_T_52; // @[Parameters.scala:137:46] wire _atomics_legal_T_54 = _atomics_legal_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_55 = _atomics_legal_T_49 \| _atomics_legal_T_54; // @[Parameters.scala:685:42] wire _atomics_legal_T_56 = _atomics_legal_T_55; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_58 = _atomics_legal_T_57; // @[Parameters.scala:686:26] wire atomics_legal = _atomics_legal_T_58 \| _atomics_legal_T_56; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [15:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size = atomics_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit = ~atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1 = _atomics_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1 = atomics_a_mask_sub_sub_sub_1_1 \| _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1 = atomics_a_mask_sub_sub_sub_1_1 \| _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size & atomics_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1 = atomics_a_mask_sub_sub_2_1 \| _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size & atomics_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1 = atomics_a_mask_sub_sub_2_1 \| _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size & atomics_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1 = atomics_a_mask_sub_sub_3_1 \| _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size & atomics_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1 = atomics_a_mask_sub_sub_3_1 \| _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_4_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_4_1 \| _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_4_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_4_1 \| _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_5_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_5_1 \| _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_5_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_5_1 \| _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_6_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_6_1 \| _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_6_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_6_1 \| _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_7_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_7_1 \| _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_7_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_7_1 \| _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo = {atomics_a_mask_lo_lo_hi, atomics_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi = {atomics_a_mask_lo_hi_hi, atomics_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo = {atomics_a_mask_hi_lo_hi, atomics_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi = {atomics_a_mask_hi_hi_hi, atomics_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46] wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46] wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46] wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46] wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_88 = _atomics_legal_T_67 \| _atomics_legal_T_72; // @[Parameters.scala:685:42] wire _atomics_legal_T_89 = _atomics_legal_T_88 \| _atomics_legal_T_77; // @[Parameters.scala:685:42] wire _atomics_legal_T_90 = _atomics_legal_T_89 \| _atomics_legal_T_82; // @[Parameters.scala:685:42] wire _atomics_legal_T_91 = _atomics_legal_T_90 \| _atomics_legal_T_87; // @[Parameters.scala:685:42] wire _atomics_legal_T_92 = _atomics_legal_T_91; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_116 = _atomics_legal_T_92; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_95 = {1'h0, _atomics_legal_T_94}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_96 = _atomics_legal_T_95 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_97 = _atomics_legal_T_96; // @[Parameters.scala:137:46] wire _atomics_legal_T_98 = _atomics_legal_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_105 = {1'h0, _atomics_legal_T_104}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_106 = _atomics_legal_T_105 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_107 = _atomics_legal_T_106; // @[Parameters.scala:137:46] wire _atomics_legal_T_108 = _atomics_legal_T_107 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_110 = {1'h0, _atomics_legal_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_111 = _atomics_legal_T_110 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_112 = _atomics_legal_T_111; // @[Parameters.scala:137:46] wire _atomics_legal_T_113 = _atomics_legal_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_114 = _atomics_legal_T_108 \| _atomics_legal_T_113; // @[Parameters.scala:685:42] wire _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_117 = _atomics_legal_T_116; // @[Parameters.scala:686:26] wire atomics_legal_1 = _atomics_legal_T_117 \| _atomics_legal_T_115; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [15:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_1 = atomics_a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 \| _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 \| _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_1 = atomics_a_mask_sub_sub_2_1_1 \| _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_1 = atomics_a_mask_sub_sub_2_1_1 \| _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_1 = atomics_a_mask_sub_sub_3_1_1 \| _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_1 = atomics_a_mask_sub_sub_3_1_1 \| _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_1 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_1 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_1 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_1 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_1 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_1 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_1 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_1 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_1 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_4_1_1 \| _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_1 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_4_1_1 \| _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_1 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_5_1_1 \| _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_1 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_5_1_1 \| _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_1 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_6_1_1 \| _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_1 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_6_1_1 \| _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_1 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_7_1_1 \| _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_1 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_7_1_1 \| _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_1 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_1 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_lo_lo_hi_1, atomics_a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_1 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_1 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_lo_hi_hi_1, atomics_a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_1 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_1 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_hi_lo_hi_1, atomics_a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_1 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_1 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_hi_hi_hi_1, atomics_a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46] wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46] wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46] wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46] wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46] wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_147 = _atomics_legal_T_126 \| _atomics_legal_T_131; // @[Parameters.scala:685:42] wire _atomics_legal_T_148 = _atomics_legal_T_147 \| _atomics_legal_T_136; // @[Parameters.scala:685:42] wire _atomics_legal_T_149 = _atomics_legal_T_148 \| _atomics_legal_T_141; // @[Parameters.scala:685:42] wire _atomics_legal_T_150 = _atomics_legal_T_149 \| _atomics_legal_T_146; // @[Parameters.scala:685:42] wire _atomics_legal_T_151 = _atomics_legal_T_150; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_175 = _atomics_legal_T_151; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_154 = {1'h0, _atomics_legal_T_153}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_155 = _atomics_legal_T_154 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_156 = _atomics_legal_T_155; // @[Parameters.scala:137:46] wire _atomics_legal_T_157 = _atomics_legal_T_156 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_164 = {1'h0, _atomics_legal_T_163}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_165 = _atomics_legal_T_164 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_166 = _atomics_legal_T_165; // @[Parameters.scala:137:46] wire _atomics_legal_T_167 = _atomics_legal_T_166 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_169 = {1'h0, _atomics_legal_T_168}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_170 = _atomics_legal_T_169 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_171 = _atomics_legal_T_170; // @[Parameters.scala:137:46] wire _atomics_legal_T_172 = _atomics_legal_T_171 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_173 = _atomics_legal_T_167 \| _atomics_legal_T_172; // @[Parameters.scala:685:42] wire _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_176 = _atomics_legal_T_175; // @[Parameters.scala:686:26] wire atomics_legal_2 = _atomics_legal_T_176 \| _atomics_legal_T_174; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [15:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_2 = atomics_a_mask_sizeOH_2[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 \| _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 \| _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_4_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_2 = atomics_a_mask_sub_sub_2_1_2 \| _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_5_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_2 = atomics_a_mask_sub_sub_2_1_2 \| _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_6_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_2 = atomics_a_mask_sub_sub_3_1_2 \| _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_7_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_2 = atomics_a_mask_sub_sub_3_1_2 \| _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_2 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_2 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_2 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_2 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_2 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_2 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_2 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_2 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_2 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_4_1_2 \| _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_2 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_4_1_2 \| _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_2 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_5_1_2 \| _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_2 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_5_1_2 \| _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_2 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_6_1_2 \| _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_2 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_6_1_2 \| _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_2 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_7_1_2 \| _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_2 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_7_1_2 \| _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_2 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_2 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_lo_lo_hi_2, atomics_a_mask_lo_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_2 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_2 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_lo_hi_hi_2, atomics_a_mask_lo_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_2 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_2 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_hi_lo_hi_2, atomics_a_mask_hi_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_2 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_2 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_hi_hi_hi_2, atomics_a_mask_hi_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46] wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46] wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46] wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46] wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_202 = {1'h0, _atomics_legal_T_201}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_203 = _atomics_legal_T_202 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_204 = _atomics_legal_T_203; // @[Parameters.scala:137:46] wire _atomics_legal_T_205 = _atomics_legal_T_204 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_206 = _atomics_legal_T_185 \| _atomics_legal_T_190; // @[Parameters.scala:685:42] wire _atomics_legal_T_207 = _atomics_legal_T_206 \| _atomics_legal_T_195; // @[Parameters.scala:685:42] wire _atomics_legal_T_208 = _atomics_legal_T_207 \| _atomics_legal_T_200; // @[Parameters.scala:685:42] wire _atomics_legal_T_209 = _atomics_legal_T_208 \| _atomics_legal_T_205; // @[Parameters.scala:685:42] wire _atomics_legal_T_210 = _atomics_legal_T_209; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_234 = _atomics_legal_T_210; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_213 = {1'h0, _atomics_legal_T_212}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_214 = _atomics_legal_T_213 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_215 = _atomics_legal_T_214; // @[Parameters.scala:137:46] wire _atomics_legal_T_216 = _atomics_legal_T_215 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_223 = {1'h0, _atomics_legal_T_222}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_224 = _atomics_legal_T_223 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_225 = _atomics_legal_T_224; // @[Parameters.scala:137:46] wire _atomics_legal_T_226 = _atomics_legal_T_225 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_228 = {1'h0, _atomics_legal_T_227}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_229 = _atomics_legal_T_228 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_230 = _atomics_legal_T_229; // @[Parameters.scala:137:46] wire _atomics_legal_T_231 = _atomics_legal_T_230 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_232 = _atomics_legal_T_226 \| _atomics_legal_T_231; // @[Parameters.scala:685:42] wire _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_235 = _atomics_legal_T_234; // @[Parameters.scala:686:26] wire atomics_legal_3 = _atomics_legal_T_235 \| _atomics_legal_T_233; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [15:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_3 = atomics_a_mask_sizeOH_3[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 \| _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 \| _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_4_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_3 = atomics_a_mask_sub_sub_2_1_3 \| _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_5_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_3 = atomics_a_mask_sub_sub_2_1_3 \| _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_6_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_3 = atomics_a_mask_sub_sub_3_1_3 \| _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_7_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_3 = atomics_a_mask_sub_sub_3_1_3 \| _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_3 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_3 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_3 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_3 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_3 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_3 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_3 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_3 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_3 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_4_1_3 \| _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_3 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_4_1_3 \| _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_3 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_5_1_3 \| _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_3 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_5_1_3 \| _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_3 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_6_1_3 \| _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_3 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_6_1_3 \| _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_3 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_7_1_3 \| _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_3 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_7_1_3 \| _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_3 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_3 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_lo_lo_hi_3, atomics_a_mask_lo_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_3 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_3 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_lo_hi_hi_3, atomics_a_mask_lo_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_3 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_3 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_hi_lo_hi_3, atomics_a_mask_hi_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_3 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_3 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_hi_hi_hi_3, atomics_a_mask_hi_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46] wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46] wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46] wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_256 = {1'h0, _atomics_legal_T_255}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_257 = _atomics_legal_T_256 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_258 = _atomics_legal_T_257; // @[Parameters.scala:137:46] wire _atomics_legal_T_259 = _atomics_legal_T_258 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_261 = {1'h0, _atomics_legal_T_260}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_262 = _atomics_legal_T_261 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_263 = _atomics_legal_T_262; // @[Parameters.scala:137:46] wire _atomics_legal_T_264 = _atomics_legal_T_263 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_265 = _atomics_legal_T_244 \| _atomics_legal_T_249; // @[Parameters.scala:685:42] wire _atomics_legal_T_266 = _atomics_legal_T_265 \| _atomics_legal_T_254; // @[Parameters.scala:685:42] wire _atomics_legal_T_267 = _atomics_legal_T_266 \| _atomics_legal_T_259; // @[Parameters.scala:685:42] wire _atomics_legal_T_268 = _atomics_legal_T_267 \| _atomics_legal_T_264; // @[Parameters.scala:685:42] wire _atomics_legal_T_269 = _atomics_legal_T_268; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_293 = _atomics_legal_T_269; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_272 = {1'h0, _atomics_legal_T_271}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_273 = _atomics_legal_T_272 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_274 = _atomics_legal_T_273; // @[Parameters.scala:137:46] wire _atomics_legal_T_275 = _atomics_legal_T_274 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_282 = {1'h0, _atomics_legal_T_281}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_283 = _atomics_legal_T_282 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_284 = _atomics_legal_T_283; // @[Parameters.scala:137:46] wire _atomics_legal_T_285 = _atomics_legal_T_284 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_287 = {1'h0, _atomics_legal_T_286}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_288 = _atomics_legal_T_287 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_289 = _atomics_legal_T_288; // @[Parameters.scala:137:46] wire _atomics_legal_T_290 = _atomics_legal_T_289 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_291 = _atomics_legal_T_285 \| _atomics_legal_T_290; // @[Parameters.scala:685:42] wire _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_294 = _atomics_legal_T_293; // @[Parameters.scala:686:26] wire atomics_legal_4 = _atomics_legal_T_294 \| _atomics_legal_T_292; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [15:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_4 = atomics_a_mask_sizeOH_4[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_18 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 \| _atomics_a_mask_sub_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_19 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 \| _atomics_a_mask_sub_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_36 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_4_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_4 = atomics_a_mask_sub_sub_2_1_4 \| _atomics_a_mask_sub_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_37 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_5_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_4 = atomics_a_mask_sub_sub_2_1_4 \| _atomics_a_mask_sub_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_38 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_6_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_4 = atomics_a_mask_sub_sub_3_1_4 \| _atomics_a_mask_sub_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_39 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_7_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_4 = atomics_a_mask_sub_sub_3_1_4 \| _atomics_a_mask_sub_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_4 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_4 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_4 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_4 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_4 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_4 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_4 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_4 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_72 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_72 = atomics_a_mask_size_4 & atomics_a_mask_eq_72; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_72 = atomics_a_mask_sub_4_1_4 \| _atomics_a_mask_acc_T_72; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_73 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_73 = atomics_a_mask_size_4 & atomics_a_mask_eq_73; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_73 = atomics_a_mask_sub_4_1_4 \| _atomics_a_mask_acc_T_73; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_74 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_74 = atomics_a_mask_size_4 & atomics_a_mask_eq_74; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_74 = atomics_a_mask_sub_5_1_4 \| _atomics_a_mask_acc_T_74; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_75 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_75 = atomics_a_mask_size_4 & atomics_a_mask_eq_75; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_75 = atomics_a_mask_sub_5_1_4 \| _atomics_a_mask_acc_T_75; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_76 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_76 = atomics_a_mask_size_4 & atomics_a_mask_eq_76; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_76 = atomics_a_mask_sub_6_1_4 \| _atomics_a_mask_acc_T_76; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_77 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_77 = atomics_a_mask_size_4 & atomics_a_mask_eq_77; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_77 = atomics_a_mask_sub_6_1_4 \| _atomics_a_mask_acc_T_77; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_78 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_78 = atomics_a_mask_size_4 & atomics_a_mask_eq_78; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_78 = atomics_a_mask_sub_7_1_4 \| _atomics_a_mask_acc_T_78; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_79 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_79 = atomics_a_mask_size_4 & atomics_a_mask_eq_79; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_79 = atomics_a_mask_sub_7_1_4 \| _atomics_a_mask_acc_T_79; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_4 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_4 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_lo_lo_hi_4, atomics_a_mask_lo_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_4 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_4 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_lo_hi_hi_4, atomics_a_mask_lo_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_4 = {atomics_a_mask_acc_73, atomics_a_mask_acc_72}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_4 = {atomics_a_mask_acc_75, atomics_a_mask_acc_74}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_hi_lo_hi_4, atomics_a_mask_hi_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_4 = {atomics_a_mask_acc_77, atomics_a_mask_acc_76}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_4 = {atomics_a_mask_acc_79, atomics_a_mask_acc_78}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_hi_hi_hi_4, atomics_a_mask_hi_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46] wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46] wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_310 = {1'h0, _atomics_legal_T_309}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_311 = _atomics_legal_T_310 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_312 = _atomics_legal_T_311; // @[Parameters.scala:137:46] wire _atomics_legal_T_313 = _atomics_legal_T_312 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_315 = {1'h0, _atomics_legal_T_314}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_316 = _atomics_legal_T_315 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_317 = _atomics_legal_T_316; // @[Parameters.scala:137:46] wire _atomics_legal_T_318 = _atomics_legal_T_317 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_320 = {1'h0, _atomics_legal_T_319}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_321 = _atomics_legal_T_320 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_322 = _atomics_legal_T_321; // @[Parameters.scala:137:46] wire _atomics_legal_T_323 = _atomics_legal_T_322 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_324 = _atomics_legal_T_303 \| _atomics_legal_T_308; // @[Parameters.scala:685:42] wire _atomics_legal_T_325 = _atomics_legal_T_324 \| _atomics_legal_T_313; // @[Parameters.scala:685:42] wire _atomics_legal_T_326 = _atomics_legal_T_325 \| _atomics_legal_T_318; // @[Parameters.scala:685:42] wire _atomics_legal_T_327 = _atomics_legal_T_326 \| _atomics_legal_T_323; // @[Parameters.scala:685:42] wire _atomics_legal_T_328 = _atomics_legal_T_327; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_352 = _atomics_legal_T_328; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_331 = {1'h0, _atomics_legal_T_330}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_332 = _atomics_legal_T_331 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_333 = _atomics_legal_T_332; // @[Parameters.scala:137:46] wire _atomics_legal_T_334 = _atomics_legal_T_333 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_341 = {1'h0, _atomics_legal_T_340}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_342 = _atomics_legal_T_341 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_343 = _atomics_legal_T_342; // @[Parameters.scala:137:46] wire _atomics_legal_T_344 = _atomics_legal_T_343 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_346 = {1'h0, _atomics_legal_T_345}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_347 = _atomics_legal_T_346 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_348 = _atomics_legal_T_347; // @[Parameters.scala:137:46] wire _atomics_legal_T_349 = _atomics_legal_T_348 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_350 = _atomics_legal_T_344 \| _atomics_legal_T_349; // @[Parameters.scala:685:42] wire _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_353 = _atomics_legal_T_352; // @[Parameters.scala:686:26] wire atomics_legal_5 = _atomics_legal_T_353 \| _atomics_legal_T_351; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [15:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_5 = atomics_a_mask_sizeOH_5[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_20 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_21 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_22 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 \| _atomics_a_mask_sub_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_23 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 \| _atomics_a_mask_sub_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_40 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_41 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_42 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_43 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_44 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_4_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_5 = atomics_a_mask_sub_sub_2_1_5 \| _atomics_a_mask_sub_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_45 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_5_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_5 = atomics_a_mask_sub_sub_2_1_5 \| _atomics_a_mask_sub_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_46 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_6_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_5 = atomics_a_mask_sub_sub_3_1_5 \| _atomics_a_mask_sub_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_47 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_7_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_5 = atomics_a_mask_sub_sub_3_1_5 \| _atomics_a_mask_sub_acc_T_47; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_80 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_80 = atomics_a_mask_size_5 & atomics_a_mask_eq_80; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_80 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_80; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_81 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_81 = atomics_a_mask_size_5 & atomics_a_mask_eq_81; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_81 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_81; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_82 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_82 = atomics_a_mask_size_5 & atomics_a_mask_eq_82; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_82 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_82; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_83 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_83 = atomics_a_mask_size_5 & atomics_a_mask_eq_83; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_83 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_83; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_84 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_84 = atomics_a_mask_size_5 & atomics_a_mask_eq_84; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_84 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_84; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_85 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_85 = atomics_a_mask_size_5 & atomics_a_mask_eq_85; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_85 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_85; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_86 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_86 = atomics_a_mask_size_5 & atomics_a_mask_eq_86; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_86 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_86; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_87 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_87 = atomics_a_mask_size_5 & atomics_a_mask_eq_87; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_87 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_87; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_88 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_88 = atomics_a_mask_size_5 & atomics_a_mask_eq_88; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_88 = atomics_a_mask_sub_4_1_5 \| _atomics_a_mask_acc_T_88; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_89 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_89 = atomics_a_mask_size_5 & atomics_a_mask_eq_89; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_89 = atomics_a_mask_sub_4_1_5 \| _atomics_a_mask_acc_T_89; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_90 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_90 = atomics_a_mask_size_5 & atomics_a_mask_eq_90; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_90 = atomics_a_mask_sub_5_1_5 \| _atomics_a_mask_acc_T_90; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_91 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_91 = atomics_a_mask_size_5 & atomics_a_mask_eq_91; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_91 = atomics_a_mask_sub_5_1_5 \| _atomics_a_mask_acc_T_91; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_92 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_92 = atomics_a_mask_size_5 & atomics_a_mask_eq_92; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_92 = atomics_a_mask_sub_6_1_5 \| _atomics_a_mask_acc_T_92; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_93 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_93 = atomics_a_mask_size_5 & atomics_a_mask_eq_93; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_93 = atomics_a_mask_sub_6_1_5 \| _atomics_a_mask_acc_T_93; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_94 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_94 = atomics_a_mask_size_5 & atomics_a_mask_eq_94; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_94 = atomics_a_mask_sub_7_1_5 \| _atomics_a_mask_acc_T_94; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_95 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_95 = atomics_a_mask_size_5 & atomics_a_mask_eq_95; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_95 = atomics_a_mask_sub_7_1_5 \| _atomics_a_mask_acc_T_95; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_5 = {atomics_a_mask_acc_81, atomics_a_mask_acc_80}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_5 = {atomics_a_mask_acc_83, atomics_a_mask_acc_82}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_lo_lo_hi_5, atomics_a_mask_lo_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_5 = {atomics_a_mask_acc_85, atomics_a_mask_acc_84}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_5 = {atomics_a_mask_acc_87, atomics_a_mask_acc_86}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_lo_hi_hi_5, atomics_a_mask_lo_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_5 = {atomics_a_mask_acc_89, atomics_a_mask_acc_88}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_5 = {atomics_a_mask_acc_91, atomics_a_mask_acc_90}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_hi_lo_hi_5, atomics_a_mask_hi_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_5 = {atomics_a_mask_acc_93, atomics_a_mask_acc_92}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_5 = {atomics_a_mask_acc_95, atomics_a_mask_acc_94}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_hi_hi_hi_5, atomics_a_mask_hi_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46] wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_364 = {1'h0, _atomics_legal_T_363}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_365 = _atomics_legal_T_364 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_366 = _atomics_legal_T_365; // @[Parameters.scala:137:46] wire _atomics_legal_T_367 = _atomics_legal_T_366 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_369 = {1'h0, _atomics_legal_T_368}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_370 = _atomics_legal_T_369 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_371 = _atomics_legal_T_370; // @[Parameters.scala:137:46] wire _atomics_legal_T_372 = _atomics_legal_T_371 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_374 = {1'h0, _atomics_legal_T_373}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_375 = _atomics_legal_T_374 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_376 = _atomics_legal_T_375; // @[Parameters.scala:137:46] wire _atomics_legal_T_377 = _atomics_legal_T_376 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_379 = {1'h0, _atomics_legal_T_378}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_380 = _atomics_legal_T_379 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_381 = _atomics_legal_T_380; // @[Parameters.scala:137:46] wire _atomics_legal_T_382 = _atomics_legal_T_381 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_383 = _atomics_legal_T_362 \| _atomics_legal_T_367; // @[Parameters.scala:685:42] wire _atomics_legal_T_384 = _atomics_legal_T_383 \| _atomics_legal_T_372; // @[Parameters.scala:685:42] wire _atomics_legal_T_385 = _atomics_legal_T_384 \| _atomics_legal_T_377; // @[Parameters.scala:685:42] wire _atomics_legal_T_386 = _atomics_legal_T_385 \| _atomics_legal_T_382; // @[Parameters.scala:685:42] wire _atomics_legal_T_387 = _atomics_legal_T_386; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_411 = _atomics_legal_T_387; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_390 = {1'h0, _atomics_legal_T_389}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_391 = _atomics_legal_T_390 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_392 = _atomics_legal_T_391; // @[Parameters.scala:137:46] wire _atomics_legal_T_393 = _atomics_legal_T_392 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_400 = {1'h0, _atomics_legal_T_399}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_401 = _atomics_legal_T_400 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_402 = _atomics_legal_T_401; // @[Parameters.scala:137:46] wire _atomics_legal_T_403 = _atomics_legal_T_402 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_405 = {1'h0, _atomics_legal_T_404}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_406 = _atomics_legal_T_405 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_407 = _atomics_legal_T_406; // @[Parameters.scala:137:46] wire _atomics_legal_T_408 = _atomics_legal_T_407 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_409 = _atomics_legal_T_403 \| _atomics_legal_T_408; // @[Parameters.scala:685:42] wire _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_412 = _atomics_legal_T_411; // @[Parameters.scala:686:26] wire atomics_legal_6 = _atomics_legal_T_412 \| _atomics_legal_T_410; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [15:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_6 = atomics_a_mask_sizeOH_6[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_24 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_25 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_26 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 \| _atomics_a_mask_sub_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_27 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 \| _atomics_a_mask_sub_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_48 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_49 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_50 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_51 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_52 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_4_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_6 = atomics_a_mask_sub_sub_2_1_6 \| _atomics_a_mask_sub_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_53 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_5_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_6 = atomics_a_mask_sub_sub_2_1_6 \| _atomics_a_mask_sub_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_54 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_6_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_6 = atomics_a_mask_sub_sub_3_1_6 \| _atomics_a_mask_sub_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_55 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_7_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_6 = atomics_a_mask_sub_sub_3_1_6 \| _atomics_a_mask_sub_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_96 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_96 = atomics_a_mask_size_6 & atomics_a_mask_eq_96; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_96 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_96; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_97 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_97 = atomics_a_mask_size_6 & atomics_a_mask_eq_97; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_97 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_97; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_98 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_98 = atomics_a_mask_size_6 & atomics_a_mask_eq_98; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_98 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_98; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_99 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_99 = atomics_a_mask_size_6 & atomics_a_mask_eq_99; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_99 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_99; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_100 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_100 = atomics_a_mask_size_6 & atomics_a_mask_eq_100; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_100 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_100; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_101 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_101 = atomics_a_mask_size_6 & atomics_a_mask_eq_101; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_101 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_101; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_102 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_102 = atomics_a_mask_size_6 & atomics_a_mask_eq_102; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_102 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_102; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_103 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_103 = atomics_a_mask_size_6 & atomics_a_mask_eq_103; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_103 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_103; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_104 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_104 = atomics_a_mask_size_6 & atomics_a_mask_eq_104; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_104 = atomics_a_mask_sub_4_1_6 \| _atomics_a_mask_acc_T_104; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_105 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_105 = atomics_a_mask_size_6 & atomics_a_mask_eq_105; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_105 = atomics_a_mask_sub_4_1_6 \| _atomics_a_mask_acc_T_105; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_106 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_106 = atomics_a_mask_size_6 & atomics_a_mask_eq_106; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_106 = atomics_a_mask_sub_5_1_6 \| _atomics_a_mask_acc_T_106; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_107 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_107 = atomics_a_mask_size_6 & atomics_a_mask_eq_107; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_107 = atomics_a_mask_sub_5_1_6 \| _atomics_a_mask_acc_T_107; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_108 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_108 = atomics_a_mask_size_6 & atomics_a_mask_eq_108; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_108 = atomics_a_mask_sub_6_1_6 \| _atomics_a_mask_acc_T_108; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_109 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_109 = atomics_a_mask_size_6 & atomics_a_mask_eq_109; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_109 = atomics_a_mask_sub_6_1_6 \| _atomics_a_mask_acc_T_109; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_110 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_110 = atomics_a_mask_size_6 & atomics_a_mask_eq_110; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_110 = atomics_a_mask_sub_7_1_6 \| _atomics_a_mask_acc_T_110; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_111 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_111 = atomics_a_mask_size_6 & atomics_a_mask_eq_111; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_111 = atomics_a_mask_sub_7_1_6 \| _atomics_a_mask_acc_T_111; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_6 = {atomics_a_mask_acc_97, atomics_a_mask_acc_96}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_6 = {atomics_a_mask_acc_99, atomics_a_mask_acc_98}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_lo_lo_hi_6, atomics_a_mask_lo_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_6 = {atomics_a_mask_acc_101, atomics_a_mask_acc_100}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_6 = {atomics_a_mask_acc_103, atomics_a_mask_acc_102}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_lo_hi_hi_6, atomics_a_mask_lo_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_6 = {atomics_a_mask_acc_105, atomics_a_mask_acc_104}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_6 = {atomics_a_mask_acc_107, atomics_a_mask_acc_106}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_hi_lo_hi_6, atomics_a_mask_hi_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_6 = {atomics_a_mask_acc_109, atomics_a_mask_acc_108}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_6 = {atomics_a_mask_acc_111, atomics_a_mask_acc_110}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_hi_hi_hi_6, atomics_a_mask_hi_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_418 = {1'h0, _atomics_legal_T_417}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_419 = _atomics_legal_T_418 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_420 = _atomics_legal_T_419; // @[Parameters.scala:137:46] wire _atomics_legal_T_421 = _atomics_legal_T_420 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_423 = {1'h0, _atomics_legal_T_422}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_424 = _atomics_legal_T_423 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_425 = _atomics_legal_T_424; // @[Parameters.scala:137:46] wire _atomics_legal_T_426 = _atomics_legal_T_425 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_428 = {1'h0, _atomics_legal_T_427}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_429 = _atomics_legal_T_428 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_430 = _atomics_legal_T_429; // @[Parameters.scala:137:46] wire _atomics_legal_T_431 = _atomics_legal_T_430 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_433 = {1'h0, _atomics_legal_T_432}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_434 = _atomics_legal_T_433 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_435 = _atomics_legal_T_434; // @[Parameters.scala:137:46] wire _atomics_legal_T_436 = _atomics_legal_T_435 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_438 = {1'h0, _atomics_legal_T_437}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_440 = _atomics_legal_T_439; // @[Parameters.scala:137:46] wire _atomics_legal_T_441 = _atomics_legal_T_440 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_442 = _atomics_legal_T_421 \| _atomics_legal_T_426; // @[Parameters.scala:685:42] wire _atomics_legal_T_443 = _atomics_legal_T_442 \| _atomics_legal_T_431; // @[Parameters.scala:685:42] wire _atomics_legal_T_444 = _atomics_legal_T_443 \| _atomics_legal_T_436; // @[Parameters.scala:685:42] wire _atomics_legal_T_445 = _atomics_legal_T_444 \| _atomics_legal_T_441; // @[Parameters.scala:685:42] wire _atomics_legal_T_446 = _atomics_legal_T_445; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_470 = _atomics_legal_T_446; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_449 = {1'h0, _atomics_legal_T_448}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_450 = _atomics_legal_T_449 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_451 = _atomics_legal_T_450; // @[Parameters.scala:137:46] wire _atomics_legal_T_452 = _atomics_legal_T_451 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_459 = {1'h0, _atomics_legal_T_458}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_460 = _atomics_legal_T_459 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_461 = _atomics_legal_T_460; // @[Parameters.scala:137:46] wire _atomics_legal_T_462 = _atomics_legal_T_461 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_464 = {1'h0, _atomics_legal_T_463}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_465 = _atomics_legal_T_464 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_466 = _atomics_legal_T_465; // @[Parameters.scala:137:46] wire _atomics_legal_T_467 = _atomics_legal_T_466 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_468 = _atomics_legal_T_462 \| _atomics_legal_T_467; // @[Parameters.scala:685:42] wire _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_471 = _atomics_legal_T_470; // @[Parameters.scala:686:26] wire atomics_legal_7 = _atomics_legal_T_471 \| _atomics_legal_T_469; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [15:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_7 = atomics_a_mask_sizeOH_7[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_28 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_29 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_30 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 \| _atomics_a_mask_sub_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_31 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 \| _atomics_a_mask_sub_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_56 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_57 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_58 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_59 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_60 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_4_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_7 = atomics_a_mask_sub_sub_2_1_7 \| _atomics_a_mask_sub_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_61 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_5_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_7 = atomics_a_mask_sub_sub_2_1_7 \| _atomics_a_mask_sub_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_62 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_6_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_7 = atomics_a_mask_sub_sub_3_1_7 \| _atomics_a_mask_sub_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_63 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_7_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_7 = atomics_a_mask_sub_sub_3_1_7 \| _atomics_a_mask_sub_acc_T_63; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_112 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_112 = atomics_a_mask_size_7 & atomics_a_mask_eq_112; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_112 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_112; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_113 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_113 = atomics_a_mask_size_7 & atomics_a_mask_eq_113; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_113 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_113; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_114 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_114 = atomics_a_mask_size_7 & atomics_a_mask_eq_114; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_114 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_114; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_115 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_115 = atomics_a_mask_size_7 & atomics_a_mask_eq_115; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_115 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_115; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_116 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_116 = atomics_a_mask_size_7 & atomics_a_mask_eq_116; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_116 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_116; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_117 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_117 = atomics_a_mask_size_7 & atomics_a_mask_eq_117; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_117 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_117; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_118 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_118 = atomics_a_mask_size_7 & atomics_a_mask_eq_118; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_118 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_118; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_119 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_119 = atomics_a_mask_size_7 & atomics_a_mask_eq_119; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_119 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_119; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_120 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_120 = atomics_a_mask_size_7 & atomics_a_mask_eq_120; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_120 = atomics_a_mask_sub_4_1_7 \| _atomics_a_mask_acc_T_120; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_121 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_121 = atomics_a_mask_size_7 & atomics_a_mask_eq_121; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_121 = atomics_a_mask_sub_4_1_7 \| _atomics_a_mask_acc_T_121; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_122 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_122 = atomics_a_mask_size_7 & atomics_a_mask_eq_122; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_122 = atomics_a_mask_sub_5_1_7 \| _atomics_a_mask_acc_T_122; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_123 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_123 = atomics_a_mask_size_7 & atomics_a_mask_eq_123; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_123 = atomics_a_mask_sub_5_1_7 \| _atomics_a_mask_acc_T_123; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_124 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_124 = atomics_a_mask_size_7 & atomics_a_mask_eq_124; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_124 = atomics_a_mask_sub_6_1_7 \| _atomics_a_mask_acc_T_124; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_125 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_125 = atomics_a_mask_size_7 & atomics_a_mask_eq_125; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_125 = atomics_a_mask_sub_6_1_7 \| _atomics_a_mask_acc_T_125; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_126 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_126 = atomics_a_mask_size_7 & atomics_a_mask_eq_126; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_126 = atomics_a_mask_sub_7_1_7 \| _atomics_a_mask_acc_T_126; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_127 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_127 = atomics_a_mask_size_7 & atomics_a_mask_eq_127; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_127 = atomics_a_mask_sub_7_1_7 \| _atomics_a_mask_acc_T_127; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_7 = {atomics_a_mask_acc_113, atomics_a_mask_acc_112}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_7 = {atomics_a_mask_acc_115, atomics_a_mask_acc_114}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_lo_lo_hi_7, atomics_a_mask_lo_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_7 = {atomics_a_mask_acc_117, atomics_a_mask_acc_116}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_7 = {atomics_a_mask_acc_119, atomics_a_mask_acc_118}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_lo_hi_hi_7, atomics_a_mask_lo_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_7 = {atomics_a_mask_acc_121, atomics_a_mask_acc_120}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_7 = {atomics_a_mask_acc_123, atomics_a_mask_acc_122}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_hi_lo_hi_7, atomics_a_mask_hi_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_7 = {atomics_a_mask_acc_125, atomics_a_mask_acc_124}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_7 = {atomics_a_mask_acc_127, atomics_a_mask_acc_126}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_hi_hi_hi_7, atomics_a_mask_hi_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_477 = {1'h0, _atomics_legal_T_476}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_478 = _atomics_legal_T_477 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_479 = _atomics_legal_T_478; // @[Parameters.scala:137:46] wire _atomics_legal_T_480 = _atomics_legal_T_479 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_482 = {1'h0, _atomics_legal_T_481}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_483 = _atomics_legal_T_482 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_484 = _atomics_legal_T_483; // @[Parameters.scala:137:46] wire _atomics_legal_T_485 = _atomics_legal_T_484 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_487 = {1'h0, _atomics_legal_T_486}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_488 = _atomics_legal_T_487 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_489 = _atomics_legal_T_488; // @[Parameters.scala:137:46] wire _atomics_legal_T_490 = _atomics_legal_T_489 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_492 = {1'h0, _atomics_legal_T_491}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_493 = _atomics_legal_T_492 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_494 = _atomics_legal_T_493; // @[Parameters.scala:137:46] wire _atomics_legal_T_495 = _atomics_legal_T_494 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_497 = {1'h0, _atomics_legal_T_496}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_498 = _atomics_legal_T_497 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_499 = _atomics_legal_T_498; // @[Parameters.scala:137:46] wire _atomics_legal_T_500 = _atomics_legal_T_499 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_501 = _atomics_legal_T_480 \| _atomics_legal_T_485; // @[Parameters.scala:685:42] wire _atomics_legal_T_502 = _atomics_legal_T_501 \| _atomics_legal_T_490; // @[Parameters.scala:685:42] wire _atomics_legal_T_503 = _atomics_legal_T_502 \| _atomics_legal_T_495; // @[Parameters.scala:685:42] wire _atomics_legal_T_504 = _atomics_legal_T_503 \| _atomics_legal_T_500; // @[Parameters.scala:685:42] wire _atomics_legal_T_505 = _atomics_legal_T_504; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_529 = _atomics_legal_T_505; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_508 = {1'h0, _atomics_legal_T_507}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_509 = _atomics_legal_T_508 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_510 = _atomics_legal_T_509; // @[Parameters.scala:137:46] wire _atomics_legal_T_511 = _atomics_legal_T_510 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_518 = {1'h0, _atomics_legal_T_517}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_519 = _atomics_legal_T_518 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_520 = _atomics_legal_T_519; // @[Parameters.scala:137:46] wire _atomics_legal_T_521 = _atomics_legal_T_520 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_523 = {1'h0, _atomics_legal_T_522}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_524 = _atomics_legal_T_523 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_525 = _atomics_legal_T_524; // @[Parameters.scala:137:46] wire _atomics_legal_T_526 = _atomics_legal_T_525 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_527 = _atomics_legal_T_521 \| _atomics_legal_T_526; // @[Parameters.scala:685:42] wire _atomics_legal_T_528 = _atomics_legal_T_527; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_530 = _atomics_legal_T_529; // @[Parameters.scala:686:26] wire atomics_legal_8 = _atomics_legal_T_530 \| _atomics_legal_T_528; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [15:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_8 = atomics_a_mask_sizeOH_8[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_32 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_33 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_34 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 \| _atomics_a_mask_sub_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_35 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 \| _atomics_a_mask_sub_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_64 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_65 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_66 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_67 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_68 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_4_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_8 = atomics_a_mask_sub_sub_2_1_8 \| _atomics_a_mask_sub_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_69 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_5_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_8 = atomics_a_mask_sub_sub_2_1_8 \| _atomics_a_mask_sub_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_70 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_6_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_8 = atomics_a_mask_sub_sub_3_1_8 \| _atomics_a_mask_sub_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_71 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_7_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_8 = atomics_a_mask_sub_sub_3_1_8 \| _atomics_a_mask_sub_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_128 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_128 = atomics_a_mask_size_8 & atomics_a_mask_eq_128; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_128 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_128; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_129 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_129 = atomics_a_mask_size_8 & atomics_a_mask_eq_129; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_129 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_129; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_130 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_130 = atomics_a_mask_size_8 & atomics_a_mask_eq_130; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_130 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_130; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_131 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_131 = atomics_a_mask_size_8 & atomics_a_mask_eq_131; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_131 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_131; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_132 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_132 = atomics_a_mask_size_8 & atomics_a_mask_eq_132; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_132 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_132; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_133 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_133 = atomics_a_mask_size_8 & atomics_a_mask_eq_133; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_133 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_133; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_134 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_134 = atomics_a_mask_size_8 & atomics_a_mask_eq_134; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_134 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_134; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_135 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_135 = atomics_a_mask_size_8 & atomics_a_mask_eq_135; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_135 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_135; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_136 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_136 = atomics_a_mask_size_8 & atomics_a_mask_eq_136; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_136 = atomics_a_mask_sub_4_1_8 \| _atomics_a_mask_acc_T_136; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_137 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_137 = atomics_a_mask_size_8 & atomics_a_mask_eq_137; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_137 = atomics_a_mask_sub_4_1_8 \| _atomics_a_mask_acc_T_137; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_138 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_138 = atomics_a_mask_size_8 & atomics_a_mask_eq_138; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_138 = atomics_a_mask_sub_5_1_8 \| _atomics_a_mask_acc_T_138; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_139 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_139 = atomics_a_mask_size_8 & atomics_a_mask_eq_139; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_139 = atomics_a_mask_sub_5_1_8 \| _atomics_a_mask_acc_T_139; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_140 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_140 = atomics_a_mask_size_8 & atomics_a_mask_eq_140; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_140 = atomics_a_mask_sub_6_1_8 \| _atomics_a_mask_acc_T_140; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_141 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_141 = atomics_a_mask_size_8 & atomics_a_mask_eq_141; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_141 = atomics_a_mask_sub_6_1_8 \| _atomics_a_mask_acc_T_141; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_142 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_142 = atomics_a_mask_size_8 & atomics_a_mask_eq_142; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_142 = atomics_a_mask_sub_7_1_8 \| _atomics_a_mask_acc_T_142; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_143 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_143 = atomics_a_mask_size_8 & atomics_a_mask_eq_143; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_143 = atomics_a_mask_sub_7_1_8 \| _atomics_a_mask_acc_T_143; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_8 = {atomics_a_mask_acc_129, atomics_a_mask_acc_128}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_8 = {atomics_a_mask_acc_131, atomics_a_mask_acc_130}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_lo_lo_hi_8, atomics_a_mask_lo_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_8 = {atomics_a_mask_acc_133, atomics_a_mask_acc_132}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_8 = {atomics_a_mask_acc_135, atomics_a_mask_acc_134}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_lo_hi_hi_8, atomics_a_mask_lo_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_8 = {atomics_a_mask_acc_137, atomics_a_mask_acc_136}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_8 = {atomics_a_mask_acc_139, atomics_a_mask_acc_138}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_hi_lo_hi_8, atomics_a_mask_hi_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_8 = {atomics_a_mask_acc_141, atomics_a_mask_acc_140}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_8 = {atomics_a_mask_acc_143, atomics_a_mask_acc_142}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_hi_hi_hi_8, atomics_a_mask_hi_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire _T_17 = req_uop_mem_cmd == 5'h4; // @[mshrs.scala:421:16, :439:75] wire _atomics_T; // @[mshrs.scala:439:75] assign _atomics_T = _T_17; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T; // @[package.scala:16:47] assign _io_mem_access_bits_T = _T_17; // @[package.scala:16:47] wire _io_mem_access_bits_T_24; // @[package.scala:16:47] assign _io_mem_access_bits_T_24 = _T_17; // @[package.scala:16:47] wire _send_resp_T_7; // @[package.scala:16:47] assign _send_resp_T_7 = _T_17; // @[package.scala:16:47] wire [2:0] _GEN_9 = _atomics_T ? 3'h3 : 3'h0; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_opcode; // @[mshrs.scala:439:75] assign _atomics_T_1_opcode = _GEN_9; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_param; // @[mshrs.scala:439:75] assign _atomics_T_1_param = _GEN_9; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire [2:0] _atomics_T_1_source = _atomics_T ? 3'h5 : 3'h0; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [15:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 16'h0; // @[Edges.scala:534:17] wire [127:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 128'h0; // @[Edges.scala:534:17] wire _T_18 = req_uop_mem_cmd == 5'h9; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_2; // @[mshrs.scala:439:75] assign _atomics_T_2 = _T_18; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_1; // @[package.scala:16:47] assign _io_mem_access_bits_T_1 = _T_18; // @[package.scala:16:47] wire _io_mem_access_bits_T_25; // @[package.scala:16:47] assign _io_mem_access_bits_T_25 = _T_18; // @[package.scala:16:47] wire _send_resp_T_8; // @[package.scala:16:47] assign _send_resp_T_8 = _T_18; // @[package.scala:16:47] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire [2:0] _atomics_T_3_source = _atomics_T_2 ? 3'h5 : _atomics_T_1_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire _T_19 = req_uop_mem_cmd == 5'hA; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_4; // @[mshrs.scala:439:75] assign _atomics_T_4 = _T_19; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_2; // @[package.scala:16:47] assign _io_mem_access_bits_T_2 = _T_19; // @[package.scala:16:47] wire _io_mem_access_bits_T_26; // @[package.scala:16:47] assign _io_mem_access_bits_T_26 = _T_19; // @[package.scala:16:47] wire _send_resp_T_9; // @[package.scala:16:47] assign _send_resp_T_9 = _T_19; // @[package.scala:16:47] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire [2:0] _atomics_T_5_source = _atomics_T_4 ? 3'h5 : _atomics_T_3_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire _T_20 = req_uop_mem_cmd == 5'hB; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_6; // @[mshrs.scala:439:75] assign _atomics_T_6 = _T_20; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_3; // @[package.scala:16:47] assign _io_mem_access_bits_T_3 = _T_20; // @[package.scala:16:47] wire _io_mem_access_bits_T_27; // @[package.scala:16:47] assign _io_mem_access_bits_T_27 = _T_20; // @[package.scala:16:47] wire _send_resp_T_10; // @[package.scala:16:47] assign _send_resp_T_10 = _T_20; // @[package.scala:16:47] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire [2:0] _atomics_T_7_source = _atomics_T_6 ? 3'h5 : _atomics_T_5_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire _T_24 = req_uop_mem_cmd == 5'h8; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_8; // @[mshrs.scala:439:75] assign _atomics_T_8 = _T_24; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_7; // @[package.scala:16:47] assign _io_mem_access_bits_T_7 = _T_24; // @[package.scala:16:47] wire _io_mem_access_bits_T_31; // @[package.scala:16:47] assign _io_mem_access_bits_T_31 = _T_24; // @[package.scala:16:47] wire _send_resp_T_14; // @[package.scala:16:47] assign _send_resp_T_14 = _T_24; // @[package.scala:16:47] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_9_source = _atomics_T_8 ? 3'h5 : _atomics_T_7_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire _T_25 = req_uop_mem_cmd == 5'hC; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_10; // @[mshrs.scala:439:75] assign _atomics_T_10 = _T_25; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_8; // @[package.scala:16:47] assign _io_mem_access_bits_T_8 = _T_25; // @[package.scala:16:47] wire _io_mem_access_bits_T_32; // @[package.scala:16:47] assign _io_mem_access_bits_T_32 = _T_25; // @[package.scala:16:47] wire _send_resp_T_15; // @[package.scala:16:47] assign _send_resp_T_15 = _T_25; // @[package.scala:16:47] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_11_source = _atomics_T_10 ? 3'h5 : _atomics_T_9_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire _T_26 = req_uop_mem_cmd == 5'hD; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_12; // @[mshrs.scala:439:75] assign _atomics_T_12 = _T_26; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_9; // @[package.scala:16:47] assign _io_mem_access_bits_T_9 = _T_26; // @[package.scala:16:47] wire _io_mem_access_bits_T_33; // @[package.scala:16:47] assign _io_mem_access_bits_T_33 = _T_26; // @[package.scala:16:47] wire _send_resp_T_16; // @[package.scala:16:47] assign _send_resp_T_16 = _T_26; // @[package.scala:16:47] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_13_source = _atomics_T_12 ? 3'h5 : _atomics_T_11_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire _T_27 = req_uop_mem_cmd == 5'hE; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_14; // @[mshrs.scala:439:75] assign _atomics_T_14 = _T_27; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_10; // @[package.scala:16:47] assign _io_mem_access_bits_T_10 = _T_27; // @[package.scala:16:47] wire _io_mem_access_bits_T_34; // @[package.scala:16:47] assign _io_mem_access_bits_T_34 = _T_27; // @[package.scala:16:47] wire _send_resp_T_17; // @[package.scala:16:47] assign _send_resp_T_17 = _T_27; // @[package.scala:16:47] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_15_source = _atomics_T_14 ? 3'h5 : _atomics_T_13_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire _T_28 = req_uop_mem_cmd == 5'hF; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_16; // @[mshrs.scala:439:75] assign _atomics_T_16 = _T_28; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_11; // @[package.scala:16:47] assign _io_mem_access_bits_T_11 = _T_28; // @[package.scala:16:47] wire _io_mem_access_bits_T_35; // @[package.scala:16:47] assign _io_mem_access_bits_T_35 = _T_28; // @[package.scala:16:47] wire _send_resp_T_18; // @[package.scala:16:47] assign _send_resp_T_18 = _T_28; // @[package.scala:16:47] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[mshrs.scala:439:75] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[mshrs.scala:439:75] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire [2:0] atomics_source = _atomics_T_16 ? 3'h5 : _atomics_T_15_source; // @[mshrs.scala:439:75] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [15:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [127:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17]
Generate the Verilog code corresponding to this FIRRTL code module ALUUnit : input clock : Clock input reset : Reset output io : { flip kill : UInt<1>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, ftq_info : { valid : UInt<1>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<8>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>}[2], pred_data : UInt<1>, imm_data : UInt<64>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, brinfo : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}} connect io.resp.bits.fflags.valid, UInt<1>(0h0) invalidate io.resp.bits.fflags.bits connect io.resp.bits.predicated, UInt<1>(0h0) connect io.req.ready, UInt<1>(0h1) node _block_pc_T = not(io.req.bits.ftq_info[0].pc) node _block_pc_T_1 = or(_block_pc_T, UInt<6>(0h3f)) node block_pc = not(_block_pc_T_1) node _uop_pc_T = or(block_pc, io.req.bits.uop.pc_lob) node _uop_pc_T_1 = mux(io.req.bits.uop.edge_inst, UInt<2>(0h2), UInt<1>(0h0)) node _uop_pc_T_2 = sub(_uop_pc_T, _uop_pc_T_1) node uop_pc = tail(_uop_pc_T_2, 1) node _op1_shamt_T = eq(io.req.bits.uop.fcn_op, UInt<1>(0h0)) node _op1_shamt_T_1 = bits(io.req.bits.uop.pimm, 2, 1) node op1_shamt = mux(_op1_shamt_T, _op1_shamt_T_1, UInt<1>(0h0)) node _op1_shl_T = eq(io.req.bits.uop.fcn_dw, UInt<1>(0h0)) node _op1_shl_T_1 = bits(io.req.bits.rs1_data, 31, 0) node _op1_shl_T_2 = mux(_op1_shl_T, _op1_shl_T_1, io.req.bits.rs1_data) node op1_shl = dshl(_op1_shl_T_2, op1_shamt) node _op1_data_T = bits(uop_pc, 39, 39) node _op1_data_T_1 = mux(_op1_data_T, UInt<24>(0hffffff), UInt<24>(0h0)) node _op1_data_T_2 = cat(_op1_data_T_1, uop_pc) node _op1_data_T_3 = eq(UInt<2>(0h0), io.req.bits.uop.op1_sel) node _op1_data_T_4 = mux(_op1_data_T_3, io.req.bits.rs1_data, UInt<1>(0h0)) node _op1_data_T_5 = eq(UInt<2>(0h2), io.req.bits.uop.op1_sel) node _op1_data_T_6 = mux(_op1_data_T_5, _op1_data_T_2, _op1_data_T_4) node _op1_data_T_7 = eq(UInt<2>(0h3), io.req.bits.uop.op1_sel) node op1_data = mux(_op1_data_T_7, op1_shl, _op1_data_T_6) node _op2_oh_T = bits(io.req.bits.uop.op2_sel, 0, 0) node _op2_oh_T_1 = mux(_op2_oh_T, io.req.bits.rs2_data, io.req.bits.imm_data) node _op2_oh_T_2 = bits(_op2_oh_T_1, 5, 0) node op2_oh = dshl(UInt<1>(0h1), _op2_oh_T_2) node _op2_data_T = bits(io.req.bits.uop.prs1, 4, 0) node _op2_data_T_1 = mux(io.req.bits.uop.is_rvc, UInt<2>(0h2), UInt<3>(0h4)) node _op2_data_T_2 = eq(UInt<3>(0h1), io.req.bits.uop.op2_sel) node _op2_data_T_3 = mux(_op2_data_T_2, io.req.bits.imm_data, UInt<1>(0h0)) node _op2_data_T_4 = eq(UInt<3>(0h4), io.req.bits.uop.op2_sel) node _op2_data_T_5 = mux(_op2_data_T_4, _op2_data_T, _op2_data_T_3) node _op2_data_T_6 = eq(UInt<3>(0h0), io.req.bits.uop.op2_sel) node _op2_data_T_7 = mux(_op2_data_T_6, io.req.bits.rs2_data, _op2_data_T_5) node _op2_data_T_8 = eq(UInt<3>(0h3), io.req.bits.uop.op2_sel) node _op2_data_T_9 = mux(_op2_data_T_8, _op2_data_T_1, _op2_data_T_7) node _op2_data_T_10 = eq(UInt<3>(0h5), io.req.bits.uop.op2_sel) node _op2_data_T_11 = mux(_op2_data_T_10, op2_oh, _op2_data_T_9) node _op2_data_T_12 = eq(UInt<3>(0h6), io.req.bits.uop.op2_sel) node op2_data = mux(_op2_data_T_12, op2_oh, _op2_data_T_11) inst alu of ALU connect alu.clock, clock connect alu.reset, reset connect alu.io.in1, op1_data connect alu.io.in2, op2_data connect alu.io.fn, io.req.bits.uop.fcn_op node _alu_io_dw_T = eq(io.req.bits.uop.op1_sel, UInt<2>(0h3)) node _alu_io_dw_T_1 = mux(_alu_io_dw_T, UInt<1>(0h1), io.req.bits.uop.fcn_dw) connect alu.io.dw, _alu_io_dw_T_1 node br_eq = eq(io.req.bits.rs1_data, io.req.bits.rs2_data) node br_ltu = lt(io.req.bits.rs1_data, io.req.bits.rs2_data) node _br_lt_T = bits(io.req.bits.rs1_data, 63, 63) node _br_lt_T_1 = bits(io.req.bits.rs2_data, 63, 63) node _br_lt_T_2 = xor(_br_lt_T, _br_lt_T_1) node _br_lt_T_3 = not(_br_lt_T_2) node _br_lt_T_4 = and(_br_lt_T_3, br_ltu) node _br_lt_T_5 = bits(io.req.bits.rs1_data, 63, 63) node _br_lt_T_6 = bits(io.req.bits.rs2_data, 63, 63) node _br_lt_T_7 = not(_br_lt_T_6) node _br_lt_T_8 = and(_br_lt_T_5, _br_lt_T_7) node br_lt = or(_br_lt_T_4, _br_lt_T_8) node _pc_sel_T = eq(br_eq, UInt<1>(0h0)) node _pc_sel_T_1 = mux(_pc_sel_T, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_2 = mux(br_eq, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_3 = eq(br_lt, UInt<1>(0h0)) node _pc_sel_T_4 = mux(_pc_sel_T_3, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_5 = eq(br_ltu, UInt<1>(0h0)) node _pc_sel_T_6 = mux(_pc_sel_T_5, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_7 = mux(br_lt, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_8 = mux(br_ltu, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_9 = eq(UInt<4>(0h0), io.req.bits.uop.br_type) node _pc_sel_T_10 = mux(_pc_sel_T_9, UInt<2>(0h0), UInt<2>(0h0)) node _pc_sel_T_11 = eq(UInt<4>(0h1), io.req.bits.uop.br_type) node _pc_sel_T_12 = mux(_pc_sel_T_11, _pc_sel_T_1, _pc_sel_T_10) node _pc_sel_T_13 = eq(UInt<4>(0h2), io.req.bits.uop.br_type) node _pc_sel_T_14 = mux(_pc_sel_T_13, _pc_sel_T_2, _pc_sel_T_12) node _pc_sel_T_15 = eq(UInt<4>(0h3), io.req.bits.uop.br_type) node _pc_sel_T_16 = mux(_pc_sel_T_15, _pc_sel_T_4, _pc_sel_T_14) node _pc_sel_T_17 = eq(UInt<4>(0h4), io.req.bits.uop.br_type) node _pc_sel_T_18 = mux(_pc_sel_T_17, _pc_sel_T_6, _pc_sel_T_16) node _pc_sel_T_19 = eq(UInt<4>(0h5), io.req.bits.uop.br_type) node _pc_sel_T_20 = mux(_pc_sel_T_19, _pc_sel_T_7, _pc_sel_T_18) node _pc_sel_T_21 = eq(UInt<4>(0h6), io.req.bits.uop.br_type) node _pc_sel_T_22 = mux(_pc_sel_T_21, _pc_sel_T_8, _pc_sel_T_20) node _pc_sel_T_23 = eq(UInt<4>(0h7), io.req.bits.uop.br_type) node _pc_sel_T_24 = mux(_pc_sel_T_23, UInt<2>(0h1), _pc_sel_T_22) node _pc_sel_T_25 = eq(UInt<4>(0h8), io.req.bits.uop.br_type) node pc_sel = mux(_pc_sel_T_25, UInt<2>(0h2), _pc_sel_T_24) node _is_taken_T = neq(io.req.bits.uop.br_type, UInt<3>(0h3)) node _is_taken_T_1 = and(io.req.valid, _is_taken_T) node _is_taken_T_2 = neq(pc_sel, UInt<2>(0h0)) node is_taken = and(_is_taken_T_1, _is_taken_T_2) node _target_offset_T = bits(io.req.bits.imm_data, 20, 0) node target_offset = asSInt(_target_offset_T) wire mispredict : UInt<1> connect mispredict, UInt<1>(0h0) node _is_br_T = eq(io.req.bits.uop.br_type, UInt<4>(0h1)) node _is_br_T_1 = eq(io.req.bits.uop.br_type, UInt<4>(0h2)) node _is_br_T_2 = eq(io.req.bits.uop.br_type, UInt<4>(0h3)) node _is_br_T_3 = eq(io.req.bits.uop.br_type, UInt<4>(0h4)) node _is_br_T_4 = eq(io.req.bits.uop.br_type, UInt<4>(0h5)) node _is_br_T_5 = eq(io.req.bits.uop.br_type, UInt<4>(0h6)) node _is_br_T_6 = or(_is_br_T, _is_br_T_1) node _is_br_T_7 = or(_is_br_T_6, _is_br_T_2) node _is_br_T_8 = or(_is_br_T_7, _is_br_T_3) node _is_br_T_9 = or(_is_br_T_8, _is_br_T_4) node _is_br_T_10 = or(_is_br_T_9, _is_br_T_5) node _is_br_T_11 = and(io.req.valid, _is_br_T_10) node _is_br_T_12 = eq(io.req.bits.uop.is_sfb, UInt<1>(0h0)) node is_br = and(_is_br_T_11, _is_br_T_12) node _is_jal_T = eq(io.req.bits.uop.br_type, UInt<4>(0h7)) node is_jal = and(io.req.valid, _is_jal_T) node _is_jalr_T = eq(io.req.bits.uop.br_type, UInt<4>(0h8)) node is_jalr = and(io.req.valid, _is_jalr_T) node jalr_target_base = asSInt(io.req.bits.rs1_data) wire jalr_target_xlen : UInt<64> node _jalr_target_xlen_T = add(jalr_target_base, target_offset) node _jalr_target_xlen_T_1 = tail(_jalr_target_xlen_T, 1) node _jalr_target_xlen_T_2 = asSInt(_jalr_target_xlen_T_1) node _jalr_target_xlen_T_3 = asUInt(_jalr_target_xlen_T_2) connect jalr_target_xlen, _jalr_target_xlen_T_3 node _jalr_target_a_T = asSInt(jalr_target_xlen) node jalr_target_a = shr(_jalr_target_a_T, 39) node _jalr_target_msb_T = eq(jalr_target_a, asSInt(UInt<1>(0h0))) node _jalr_target_msb_T_1 = eq(jalr_target_a, asSInt(UInt<1>(0h1))) node _jalr_target_msb_T_2 = or(_jalr_target_msb_T, _jalr_target_msb_T_1) node _jalr_target_msb_T_3 = bits(jalr_target_xlen, 39, 39) node _jalr_target_msb_T_4 = bits(jalr_target_xlen, 38, 38) node _jalr_target_msb_T_5 = eq(_jalr_target_msb_T_4, UInt<1>(0h0)) node jalr_target_msb = mux(_jalr_target_msb_T_2, _jalr_target_msb_T_3, _jalr_target_msb_T_5) node _jalr_target_T = bits(jalr_target_xlen, 38, 0) node _jalr_target_T_1 = cat(jalr_target_msb, _jalr_target_T) node _jalr_target_T_2 = asSInt(_jalr_target_T_1) node _jalr_target_T_3 = and(_jalr_target_T_2, asSInt(UInt<2>(0h2))) node _jalr_target_T_4 = asSInt(_jalr_target_T_3) node jalr_target = asUInt(_jalr_target_T_4) node _cfi_idx_T = eq(io.req.bits.ftq_info[0].entry.start_bank, UInt<1>(0h1)) node _cfi_idx_T_1 = shl(UInt<1>(0h1), 3) node _cfi_idx_T_2 = mux(_cfi_idx_T, _cfi_idx_T_1, UInt<1>(0h0)) node _cfi_idx_T_3 = xor(io.req.bits.uop.pc_lob, _cfi_idx_T_2) node cfi_idx = bits(_cfi_idx_T_3, 3, 1) node _T = or(is_br, is_jalr) when _T : node _T_1 = eq(pc_sel, UInt<2>(0h0)) when _T_1 : connect mispredict, io.req.bits.uop.taken node _T_2 = eq(pc_sel, UInt<2>(0h1)) when _T_2 : node _mispredict_T = eq(io.req.bits.uop.taken, UInt<1>(0h0)) connect mispredict, _mispredict_T node _T_3 = eq(pc_sel, UInt<2>(0h2)) when _T_3 : node _mispredict_T_1 = eq(io.req.bits.ftq_info[1].valid, UInt<1>(0h0)) node _mispredict_T_2 = neq(io.req.bits.ftq_info[1].pc, jalr_target) node _mispredict_T_3 = or(_mispredict_T_1, _mispredict_T_2) node _mispredict_T_4 = eq(io.req.bits.ftq_info[0].entry.cfi_idx.valid, UInt<1>(0h0)) node _mispredict_T_5 = or(_mispredict_T_3, _mispredict_T_4) node _mispredict_T_6 = neq(io.req.bits.ftq_info[0].entry.cfi_idx.bits, cfi_idx) node _mispredict_T_7 = or(_mispredict_T_5, _mispredict_T_6) connect mispredict, _mispredict_T_7 wire brinfo : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}} node _brinfo_valid_T = or(is_br, is_jalr) connect brinfo.valid, _brinfo_valid_T connect brinfo.bits.mispredict, mispredict connect brinfo.bits.uop, io.req.bits.uop node _brinfo_bits_cfi_type_T = mux(is_br, UInt<3>(0h1), UInt<3>(0h0)) node _brinfo_bits_cfi_type_T_1 = mux(is_jalr, UInt<3>(0h3), _brinfo_bits_cfi_type_T) connect brinfo.bits.cfi_type, _brinfo_bits_cfi_type_T_1 connect brinfo.bits.taken, is_taken connect brinfo.bits.pc_sel, pc_sel invalidate brinfo.bits.jalr_target connect brinfo.bits.jalr_target, jalr_target connect brinfo.bits.target_offset, target_offset connect io.brinfo, brinfo node _alu_out_T = eq(io.req.bits.uop.br_type, UInt<4>(0h0)) node _alu_out_T_1 = and(_alu_out_T, io.req.bits.uop.is_sfb) node _alu_out_T_2 = and(_alu_out_T_1, UInt<1>(0h1)) node _alu_out_T_3 = and(_alu_out_T_2, io.req.bits.pred_data) node _alu_out_T_4 = mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data) node _alu_out_T_5 = mux(io.req.bits.uop.is_mov, io.req.bits.rs2_data, alu.io.out) node alu_out = mux(_alu_out_T_3, _alu_out_T_4, _alu_out_T_5) connect io.resp.valid, io.req.valid connect io.resp.bits.uop, io.req.bits.uop node _io_resp_bits_data_T = neq(io.req.bits.uop.br_type, UInt<4>(0h0)) node _io_resp_bits_data_T_1 = and(_io_resp_bits_data_T, io.req.bits.uop.is_sfb) node _io_resp_bits_data_T_2 = and(_io_resp_bits_data_T_1, UInt<1>(0h1)) node _io_resp_bits_data_T_3 = eq(pc_sel, UInt<2>(0h1)) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_2, _io_resp_bits_data_T_3, alu_out) connect io.resp.bits.data, _io_resp_bits_data_T_4 node _io_resp_bits_predicated_T = eq(io.req.bits.uop.br_type, UInt<4>(0h0)) node _io_resp_bits_predicated_T_1 = and(_io_resp_bits_predicated_T, io.req.bits.uop.is_sfb) node _io_resp_bits_predicated_T_2 = and(_io_resp_bits_predicated_T_1, UInt<1>(0h1)) node _io_resp_bits_predicated_T_3 = and(_io_resp_bits_predicated_T_2, io.req.bits.pred_data) connect io.resp.bits.predicated, _io_resp_bits_predicated_T_3 node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(io.resp.ready, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at functional-unit.scala:292 assert(io.resp.ready)\n") : printf assert(clock, io.resp.ready, UInt<1>(0h1), "") : assert	module ALUUnit( // @[functional-unit.scala:133:7] input clock, // @[functional-unit.scala:133:7] input reset, // @[functional-unit.scala:133:7] input io_kill, // @[functional-unit.scala:105:14] input io_req_valid, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_type, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_eret, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rocc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:105:14] input io_req_bits_uop_taken, // @[functional-unit.scala:105:14] input io_req_bits_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_op2_sel, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_req_bits_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:105:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:105:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:105:14] input io_req_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_fcn_op, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_typ, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_imm_data, // @[functional-unit.scala:105:14] output io_resp_valid, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:105:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_type, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_eret, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rocc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_mov, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:105:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:105:14] output io_resp_bits_uop_imm_rename, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_imm_sel, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_pimm, // @[functional-unit.scala:105:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_op1_sel, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_op2_sel, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:105:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:105:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_fcn_op, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_fp_rm, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_typ, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_data, // @[functional-unit.scala:105:14] input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:105:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_type, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_eret, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rocc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:105:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:105:14] input io_brupdate_b2_taken, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:105:14] input [20:0] io_brupdate_b2_target_offset // @[functional-unit.scala:105:14] ); wire [63:0] _alu_io_out; // @[functional-unit.scala:173:19] wire io_kill_0 = io_kill; // @[functional-unit.scala:133:7] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:133:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_br_type_0 = io_req_bits_uop_br_type; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_eret_0 = io_req_bits_uop_is_eret; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_mov_0 = io_req_bits_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:133:7] wire io_req_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_pimm_0 = io_req_bits_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:133:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:133:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_imm_data_0 = io_req_bits_imm_data; // @[functional-unit.scala:133:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:133:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:133:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:133:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:133:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:133:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:133:7] wire [3:0] _cfi_idx_T_1 = 4'h8; // @[functional-unit.scala:234:90] wire [39:0] _block_pc_T = 40'hFFFFFFFFFF; // @[util.scala:245:{7,11}] wire [39:0] _block_pc_T_1 = 40'hFFFFFFFFFF; // @[util.scala:245:{7,11}] wire [1:0] _pc_sel_T_10 = 2'h0; // @[functional-unit.scala:188:48] wire [3:0] _cfi_idx_T_2 = 4'h0; // @[functional-unit.scala:234:35] wire [4:0] io_req_bits_ftq_info_0_entry_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_0_ghist_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_1_entry_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_1_ghist_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_resp_bits_fflags_bits = 5'h0; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_ftq_info_0_entry_ras_top = 40'h0; // @[util.scala:245:5] wire [39:0] io_req_bits_ftq_info_0_pc = 40'h0; // @[util.scala:245:5] wire [39:0] io_req_bits_ftq_info_1_entry_ras_top = 40'h0; // @[util.scala:245:5] wire [39:0] io_req_bits_ftq_info_1_pc = 40'h0; // @[util.scala:245:5] wire [39:0] block_pc = 40'h0; // @[util.scala:245:5] wire [7:0] io_req_bits_ftq_info_0_entry_br_mask = 8'h0; // @[functional-unit.scala:105:14, :133:7] wire [7:0] io_req_bits_ftq_info_1_entry_br_mask = 8'h0; // @[functional-unit.scala:105:14, :133:7] wire [2:0] io_req_bits_ftq_info_0_entry_cfi_idx_bits = 3'h0; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_ftq_info_0_entry_cfi_type = 3'h0; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_ftq_info_1_entry_cfi_idx_bits = 3'h0; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_ftq_info_1_entry_cfi_type = 3'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_start_bank = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_start_bank = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:133:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:133:7] wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:133:7] wire _cfi_idx_T = 1'h0; // @[functional-unit.scala:234:77] wire _alu_out_T_3 = 1'h0; // @[functional-unit.scala:285:51] wire _io_resp_bits_predicated_T_3 = 1'h0; // @[functional-unit.scala:291:60] wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_ftq_info_0_ghist_old_history = 64'h0; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_ftq_info_1_ghist_old_history = 64'h0; // @[functional-unit.scala:133:7] wire io_req_ready = 1'h1; // @[functional-unit.scala:133:7] wire io_resp_ready = 1'h1; // @[functional-unit.scala:133:7] wire _mispredict_T_1 = 1'h1; // @[functional-unit.scala:245:22] wire _mispredict_T_3 = 1'h1; // @[functional-unit.scala:245:53] wire _mispredict_T_4 = 1'h1; // @[functional-unit.scala:247:22] wire _mispredict_T_5 = 1'h1; // @[functional-unit.scala:246:67] wire _mispredict_T_7 = 1'h1; // @[functional-unit.scala:247:67] wire io_resp_valid_0 = io_req_valid_0; // @[functional-unit.scala:133:7] wire [31:0] io_resp_bits_uop_inst_0 = io_req_bits_uop_inst_0; // @[functional-unit.scala:133:7] wire [31:0] brinfo_bits_uop_inst = io_req_bits_uop_inst_0; // @[functional-unit.scala:133:7, :252:20] wire [31:0] io_resp_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7] wire [31:0] brinfo_bits_uop_debug_inst = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_rvc = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7, :252:20] wire [39:0] io_resp_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7] wire [39:0] brinfo_bits_uop_debug_pc = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_0 = io_req_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_1 = io_req_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_2 = io_req_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_3 = io_req_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_0 = io_req_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_1 = io_req_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_2 = io_req_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_3 = io_req_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_4 = io_req_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_5 = io_req_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_6 = io_req_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_7 = io_req_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_8 = io_req_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_9 = io_req_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued = io_req_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued_partial_agen = io_req_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued_partial_dgen = io_req_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_iw_p1_speculative_child = io_req_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_iw_p2_speculative_child = io_req_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p1_bypass_hint = io_req_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p2_bypass_hint = io_req_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p3_bypass_hint = io_req_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_dis_col_sel = io_req_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [15:0] io_resp_bits_uop_br_mask_0 = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:133:7] wire [15:0] brinfo_bits_uop_br_mask = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_br_tag_0 = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_br_tag = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_br_type_0 = io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_br_type = io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sfb = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_fence_0 = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_fence = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_fencei = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sfence = io_req_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_amo_0 = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_amo = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_eret_0 = io_req_bits_uop_is_eret_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_eret = io_req_bits_uop_is_eret_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_rocc = io_req_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_mov_0 = io_req_bits_uop_is_mov_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_mov = io_req_bits_uop_is_mov_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ftq_idx = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_edge_inst = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7] wire [5:0] _cfi_idx_T_3 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7, :234:30] wire [5:0] brinfo_bits_uop_pc_lob = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_taken_0 = io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_taken = io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_imm_rename = io_req_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_imm_sel = io_req_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_pimm_0 = io_req_bits_uop_pimm_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_pimm = io_req_bits_uop_pimm_0; // @[functional-unit.scala:133:7, :252:20] wire [19:0] io_resp_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7] wire [19:0] brinfo_bits_uop_imm_packed = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_op1_sel = io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_op2_sel = io_req_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ldst = io_req_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_wen = io_req_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren1 = io_req_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren2 = io_req_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren3 = io_req_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_swap12 = io_req_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_swap23 = io_req_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_ctrl_typeTagIn = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_ctrl_typeTagOut = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fromint = io_req_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_toint = io_req_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fastpipe = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fma = io_req_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_div = io_req_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_sqrt = io_req_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_wflags = io_req_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_vec = io_req_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_rob_idx = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ldq_idx = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_stq_idx = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_rxq_idx = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_pdst_0 = io_req_bits_uop_pdst_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_pdst = io_req_bits_uop_pdst_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs1_0 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs1 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs2_0 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs2 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs3_0 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs3 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ppred_0 = io_req_bits_uop_ppred_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ppred = io_req_bits_uop_ppred_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs1_busy = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs2_busy = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs3_busy = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_ppred_busy = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_stale_pdst = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_exception_0 = io_req_bits_uop_exception_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_exception = io_req_bits_uop_exception_0; // @[functional-unit.scala:133:7, :252:20] wire [63:0] io_resp_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7] wire [63:0] brinfo_bits_uop_exc_cause = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_mem_cmd = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_mem_size_0 = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_mem_size = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_mem_signed = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_uses_ldq = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_uses_stq = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_unique_0 = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_unique = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_flush_on_commit = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_csr_cmd = io_req_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_ldst_0 = io_req_bits_uop_ldst_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_ldst = io_req_bits_uop_ldst_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs1_0 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs1 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs2_0 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs2 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs3_0 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs3 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_dst_rtype = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_lrs1_rtype = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_lrs2_rtype = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_frs3_en = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fcn_dw = io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_fcn_op = io_req_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_val_0 = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_val = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_fp_rm = io_req_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_typ = io_req_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_bp_debug_if = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_debug_fsrc = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_debug_tsrc = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7, :252:20] wire [63:0] jalr_target_base = io_req_bits_rs1_data_0; // @[functional-unit.scala:133:7, :229:47] wire [63:0] _io_resp_bits_data_T_4; // @[functional-unit.scala:290:27] wire brinfo_valid; // @[functional-unit.scala:252:20] wire brinfo_bits_mispredict; // @[functional-unit.scala:252:20] wire brinfo_bits_taken; // @[functional-unit.scala:252:20] wire [2:0] brinfo_bits_cfi_type; // @[functional-unit.scala:252:20] wire [1:0] brinfo_bits_pc_sel; // @[functional-unit.scala:252:20] wire [39:0] brinfo_bits_jalr_target; // @[functional-unit.scala:252:20] wire [20:0] brinfo_bits_target_offset; // @[functional-unit.scala:252:20] wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [31:0] io_brinfo_bits_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_brinfo_bits_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_brinfo_bits_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [15:0] io_brinfo_bits_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_br_type; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_fence; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_amo; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_eret; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_taken; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_brinfo_bits_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_op2_sel; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_rob_idx; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ppred; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_brinfo_bits_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_mem_size; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_unique; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_mispredict; // @[functional-unit.scala:133:7] wire io_brinfo_bits_taken; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_cfi_type; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_pc_sel; // @[functional-unit.scala:133:7] wire [39:0] io_brinfo_bits_jalr_target; // @[functional-unit.scala:133:7] wire [20:0] io_brinfo_bits_target_offset; // @[functional-unit.scala:133:7] wire io_brinfo_valid; // @[functional-unit.scala:133:7] wire [39:0] _uop_pc_T = {34'h0, io_req_bits_uop_pc_lob_0}; // @[functional-unit.scala:133:7, :150:26] wire [1:0] _uop_pc_T_1 = {io_req_bits_uop_edge_inst_0, 1'h0}; // @[functional-unit.scala:133:7, :150:45] wire [40:0] _uop_pc_T_2 = {1'h0, _uop_pc_T} - {39'h0, _uop_pc_T_1}; // @[functional-unit.scala:150:{26,40,45}] wire [39:0] uop_pc = _uop_pc_T_2[39:0]; // @[functional-unit.scala:150:40] wire _op1_shamt_T = io_req_bits_uop_fcn_op_0 == 5'h0; // @[functional-unit.scala:133:7, :151:34] wire [1:0] _op1_shamt_T_1 = io_req_bits_uop_pimm_0[2:1]; // @[functional-unit.scala:133:7, :151:66] wire [1:0] op1_shamt = _op1_shamt_T ? _op1_shamt_T_1 : 2'h0; // @[functional-unit.scala:151:{22,34,66}] wire _op1_shl_T = ~io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :152:32] wire [31:0] _op1_shl_T_1 = io_req_bits_rs1_data_0[31:0]; // @[functional-unit.scala:133:7, :153:25] wire [63:0] _op1_shl_T_2 = _op1_shl_T ? {32'h0, _op1_shl_T_1} : io_req_bits_rs1_data_0; // @[functional-unit.scala:133:7, :152:{20,32}, :153:25] wire [66:0] op1_shl = {3'h0, _op1_shl_T_2} << op1_shamt; // @[functional-unit.scala:151:22, :152:20, :153:55] wire _op1_data_T = uop_pc[39]; // @[util.scala:269:46] wire [23:0] _op1_data_T_1 = {24{_op1_data_T}}; // @[util.scala:269:{25,46}] wire [63:0] _op1_data_T_2 = {_op1_data_T_1, uop_pc}; // @[util.scala:269:{20,25}] wire _op1_data_T_3 = io_req_bits_uop_op1_sel_0 == 2'h0; // @[functional-unit.scala:133:7, :155:45] wire [63:0] _op1_data_T_4 = _op1_data_T_3 ? io_req_bits_rs1_data_0 : 64'h0; // @[functional-unit.scala:133:7, :155:45] wire _op1_data_T_5 = io_req_bits_uop_op1_sel_0 == 2'h2; // @[functional-unit.scala:133:7, :155:45] wire [63:0] _op1_data_T_6 = _op1_data_T_5 ? _op1_data_T_2 : _op1_data_T_4; // @[util.scala:269:20] wire _op1_data_T_7 = &io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :155:45] wire [66:0] op1_data = _op1_data_T_7 ? op1_shl : {3'h0, _op1_data_T_6}; // @[functional-unit.scala:153:55, :155:45] wire _op2_oh_T = io_req_bits_uop_op2_sel_0[0]; // @[functional-unit.scala:133:7, :162:40] wire [63:0] _op2_oh_T_1 = _op2_oh_T ? io_req_bits_rs2_data_0 : io_req_bits_imm_data_0; // @[functional-unit.scala:133:7, :162:{28,40}] wire [5:0] _op2_oh_T_2 = _op2_oh_T_1[5:0]; // @[functional-unit.scala:162:28, :163:38] wire [63:0] op2_oh = 64'h1 << _op2_oh_T_2; // @[OneHot.scala:58:35] wire [4:0] _op2_data_T = io_req_bits_uop_prs1_0[4:0]; // @[functional-unit.scala:133:7, :166:37] wire [2:0] _op2_data_T_1 = io_req_bits_uop_is_rvc_0 ? 3'h2 : 3'h4; // @[functional-unit.scala:133:7, :168:20] wire _op2_data_T_2 = io_req_bits_uop_op2_sel_0 == 3'h1; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_3 = _op2_data_T_2 ? io_req_bits_imm_data_0 : 64'h0; // @[functional-unit.scala:133:7, :164:45] wire _op2_data_T_4 = io_req_bits_uop_op2_sel_0 == 3'h4; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_5 = _op2_data_T_4 ? {59'h0, _op2_data_T} : _op2_data_T_3; // @[functional-unit.scala:164:45, :166:37] wire _op2_data_T_6 = io_req_bits_uop_op2_sel_0 == 3'h0; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_7 = _op2_data_T_6 ? io_req_bits_rs2_data_0 : _op2_data_T_5; // @[functional-unit.scala:133:7, :164:45] wire _op2_data_T_8 = io_req_bits_uop_op2_sel_0 == 3'h3; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_9 = _op2_data_T_8 ? {61'h0, _op2_data_T_1} : _op2_data_T_7; // @[functional-unit.scala:164:45, :168:20] wire _op2_data_T_10 = io_req_bits_uop_op2_sel_0 == 3'h5; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_11 = _op2_data_T_10 ? op2_oh : _op2_data_T_9; // @[OneHot.scala:58:35] wire _op2_data_T_12 = io_req_bits_uop_op2_sel_0 == 3'h6; // @[functional-unit.scala:133:7, :164:45] wire [63:0] op2_data = _op2_data_T_12 ? op2_oh : _op2_data_T_11; // @[OneHot.scala:58:35] wire _alu_io_dw_T = &io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :155:45, :178:33] wire _alu_io_dw_T_1 = _alu_io_dw_T \| io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :178:{20,33}] wire br_eq = io_req_bits_rs1_data_0 == io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :183:21] wire br_ltu = io_req_bits_rs1_data_0 < io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :184:28] wire _br_lt_T = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:133:7, :185:22] wire _br_lt_T_5 = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:133:7, :185:22, :186:20] wire _br_lt_T_1 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:133:7, :185:36] wire _br_lt_T_6 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:133:7, :185:36, :186:35] wire _br_lt_T_2 = _br_lt_T ^ _br_lt_T_1; // @[functional-unit.scala:185:{22,31,36}] wire _br_lt_T_3 = ~_br_lt_T_2; // @[functional-unit.scala:185:{17,31}] wire _br_lt_T_4 = _br_lt_T_3 & br_ltu; // @[functional-unit.scala:184:28, :185:{17,46}] wire _br_lt_T_7 = ~_br_lt_T_6; // @[functional-unit.scala:186:{31,35}] wire _br_lt_T_8 = _br_lt_T_5 & _br_lt_T_7; // @[functional-unit.scala:186:{20,29,31}] wire br_lt = _br_lt_T_4 \| _br_lt_T_8; // @[functional-unit.scala:185:{46,55}, :186:29] wire _pc_sel_T = ~br_eq; // @[functional-unit.scala:183:21, :190:38] wire [1:0] _pc_sel_T_1 = {1'h0, _pc_sel_T}; // @[functional-unit.scala:190:{37,38}] wire [1:0] _pc_sel_T_2 = {1'h0, br_eq}; // @[functional-unit.scala:183:21, :191:37] wire _pc_sel_T_3 = ~br_lt; // @[functional-unit.scala:185:55, :192:38] wire [1:0] _pc_sel_T_4 = {1'h0, _pc_sel_T_3}; // @[functional-unit.scala:192:{37,38}] wire _pc_sel_T_5 = ~br_ltu; // @[functional-unit.scala:184:28, :193:38] wire [1:0] _pc_sel_T_6 = {1'h0, _pc_sel_T_5}; // @[functional-unit.scala:193:{37,38}] wire [1:0] _pc_sel_T_7 = {1'h0, br_lt}; // @[functional-unit.scala:185:55, :194:37] wire [1:0] _pc_sel_T_8 = {1'h0, br_ltu}; // @[functional-unit.scala:184:28, :195:37] wire _pc_sel_T_9 = ~(\|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _GEN = io_req_bits_uop_br_type_0 == 4'h1; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_11; // @[functional-unit.scala:188:48] assign _pc_sel_T_11 = _GEN; // @[functional-unit.scala:188:48] wire _is_br_T; // @[package.scala:16:47] assign _is_br_T = _GEN; // @[package.scala:16:47] wire [1:0] _pc_sel_T_12 = _pc_sel_T_11 ? _pc_sel_T_1 : 2'h0; // @[functional-unit.scala:188:48, :190:37] wire _GEN_0 = io_req_bits_uop_br_type_0 == 4'h2; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_13; // @[functional-unit.scala:188:48] assign _pc_sel_T_13 = _GEN_0; // @[functional-unit.scala:188:48] wire _is_br_T_1; // @[package.scala:16:47] assign _is_br_T_1 = _GEN_0; // @[package.scala:16:47] wire [1:0] _pc_sel_T_14 = _pc_sel_T_13 ? _pc_sel_T_2 : _pc_sel_T_12; // @[functional-unit.scala:188:48, :191:37] wire _GEN_1 = io_req_bits_uop_br_type_0 == 4'h3; // @[functional-unit.scala:133:7, :188:48, :201:33] wire _pc_sel_T_15; // @[functional-unit.scala:188:48] assign _pc_sel_T_15 = _GEN_1; // @[functional-unit.scala:188:48] wire _is_br_T_2; // @[package.scala:16:47] assign _is_br_T_2 = _GEN_1; // @[package.scala:16:47] wire [1:0] _pc_sel_T_16 = _pc_sel_T_15 ? _pc_sel_T_4 : _pc_sel_T_14; // @[functional-unit.scala:188:48, :192:37] wire _GEN_2 = io_req_bits_uop_br_type_0 == 4'h4; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_17; // @[functional-unit.scala:188:48] assign _pc_sel_T_17 = _GEN_2; // @[functional-unit.scala:188:48] wire _is_br_T_3; // @[package.scala:16:47] assign _is_br_T_3 = _GEN_2; // @[package.scala:16:47] wire [1:0] _pc_sel_T_18 = _pc_sel_T_17 ? _pc_sel_T_6 : _pc_sel_T_16; // @[functional-unit.scala:188:48, :193:37] wire _GEN_3 = io_req_bits_uop_br_type_0 == 4'h5; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_19; // @[functional-unit.scala:188:48] assign _pc_sel_T_19 = _GEN_3; // @[functional-unit.scala:188:48] wire _is_br_T_4; // @[package.scala:16:47] assign _is_br_T_4 = _GEN_3; // @[package.scala:16:47] wire [1:0] _pc_sel_T_20 = _pc_sel_T_19 ? _pc_sel_T_7 : _pc_sel_T_18; // @[functional-unit.scala:188:48, :194:37] wire _GEN_4 = io_req_bits_uop_br_type_0 == 4'h6; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_21; // @[functional-unit.scala:188:48] assign _pc_sel_T_21 = _GEN_4; // @[functional-unit.scala:188:48] wire _is_br_T_5; // @[package.scala:16:47] assign _is_br_T_5 = _GEN_4; // @[package.scala:16:47] wire [1:0] _pc_sel_T_22 = _pc_sel_T_21 ? _pc_sel_T_8 : _pc_sel_T_20; // @[functional-unit.scala:188:48, :195:37] wire _GEN_5 = io_req_bits_uop_br_type_0 == 4'h7; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_23; // @[functional-unit.scala:188:48] assign _pc_sel_T_23 = _GEN_5; // @[functional-unit.scala:188:48] wire _is_jal_T; // @[micro-op.scala:118:34] assign _is_jal_T = _GEN_5; // @[functional-unit.scala:188:48] wire [1:0] _pc_sel_T_24 = _pc_sel_T_23 ? 2'h1 : _pc_sel_T_22; // @[functional-unit.scala:188:48] wire _GEN_6 = io_req_bits_uop_br_type_0 == 4'h8; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_25; // @[functional-unit.scala:188:48] assign _pc_sel_T_25 = _GEN_6; // @[functional-unit.scala:188:48] wire _is_jalr_T; // @[micro-op.scala:119:34] assign _is_jalr_T = _GEN_6; // @[functional-unit.scala:188:48] wire [1:0] pc_sel = _pc_sel_T_25 ? 2'h2 : _pc_sel_T_24; // @[functional-unit.scala:188:48] assign brinfo_bits_pc_sel = pc_sel; // @[functional-unit.scala:188:48, :252:20] wire _is_taken_T = io_req_bits_uop_br_type_0 != 4'h3; // @[functional-unit.scala:133:7, :201:33] wire _is_taken_T_1 = io_req_valid_0 & _is_taken_T; // @[functional-unit.scala:133:7, :200:31, :201:33] wire _is_taken_T_2 = \|pc_sel; // @[functional-unit.scala:188:48, :202:28] wire is_taken = _is_taken_T_1 & _is_taken_T_2; // @[functional-unit.scala:200:31, :201:43, :202:28] assign brinfo_bits_taken = is_taken; // @[functional-unit.scala:201:43, :252:20] wire [20:0] _target_offset_T = io_req_bits_imm_data_0[20:0]; // @[functional-unit.scala:133:7, :208:33] wire [20:0] target_offset = _target_offset_T; // @[functional-unit.scala:208:{33,40}] assign brinfo_bits_target_offset = target_offset; // @[functional-unit.scala:208:40, :252:20] wire mispredict; // @[functional-unit.scala:223:28] assign brinfo_bits_mispredict = mispredict; // @[functional-unit.scala:223:28, :252:20] wire _is_br_T_6 = _is_br_T \| _is_br_T_1; // @[package.scala:16:47, :81:59] wire _is_br_T_7 = _is_br_T_6 \| _is_br_T_2; // @[package.scala:16:47, :81:59] wire _is_br_T_8 = _is_br_T_7 \| _is_br_T_3; // @[package.scala:16:47, :81:59] wire _is_br_T_9 = _is_br_T_8 \| _is_br_T_4; // @[package.scala:16:47, :81:59] wire _is_br_T_10 = _is_br_T_9 \| _is_br_T_5; // @[package.scala:16:47, :81:59] wire _is_br_T_11 = io_req_valid_0 & _is_br_T_10; // @[package.scala:81:59] wire _is_br_T_12 = ~io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7, :225:53] wire is_br = _is_br_T_11 & _is_br_T_12; // @[functional-unit.scala:225:{37,50,53}] wire is_jal = io_req_valid_0 & _is_jal_T; // @[functional-unit.scala:133:7, :226:37] wire is_jalr = io_req_valid_0 & _is_jalr_T; // @[functional-unit.scala:133:7, :227:37] wire [63:0] _jalr_target_xlen_T_3; // @[functional-unit.scala:231:58] wire [63:0] jalr_target_xlen; // @[functional-unit.scala:230:30] wire [63:0] _jalr_target_a_T = jalr_target_xlen; // @[functional-unit.scala:215:16, :230:30] wire [64:0] _jalr_target_xlen_T = {jalr_target_base[63], jalr_target_base} + {{44{target_offset[20]}}, target_offset}; // @[functional-unit.scala:208:40, :229:47, :231:41] wire [63:0] _jalr_target_xlen_T_1 = _jalr_target_xlen_T[63:0]; // @[functional-unit.scala:231:41] wire [63:0] _jalr_target_xlen_T_2 = _jalr_target_xlen_T_1; // @[functional-unit.scala:231:41] assign _jalr_target_xlen_T_3 = _jalr_target_xlen_T_2; // @[functional-unit.scala:231:{41,58}] assign jalr_target_xlen = _jalr_target_xlen_T_3; // @[functional-unit.scala:230:30, :231:58] wire [24:0] jalr_target_a = _jalr_target_a_T[63:39]; // @[functional-unit.scala:215:{16,23}] wire _jalr_target_msb_T = jalr_target_a == 25'h0; // @[functional-unit.scala:215:23, :216:21] wire _jalr_target_msb_T_1 = &jalr_target_a; // @[functional-unit.scala:215:23, :216:34] wire _jalr_target_msb_T_2 = _jalr_target_msb_T \| _jalr_target_msb_T_1; // @[functional-unit.scala:216:{21,29,34}] wire _jalr_target_msb_T_3 = jalr_target_xlen[39]; // @[functional-unit.scala:216:46, :230:30] wire _jalr_target_msb_T_4 = jalr_target_xlen[38]; // @[functional-unit.scala:216:62, :230:30] wire _jalr_target_msb_T_5 = ~_jalr_target_msb_T_4; // @[functional-unit.scala:216:{59,62}] wire jalr_target_msb = _jalr_target_msb_T_2 ? _jalr_target_msb_T_3 : _jalr_target_msb_T_5; // @[functional-unit.scala:216:{18,29,46,59}] wire [38:0] _jalr_target_T = jalr_target_xlen[38:0]; // @[functional-unit.scala:217:16, :230:30] wire [39:0] _jalr_target_T_1 = {jalr_target_msb, _jalr_target_T}; // @[functional-unit.scala:216:18, :217:{8,16}] wire [39:0] _jalr_target_T_2 = _jalr_target_T_1; // @[functional-unit.scala:217:8, :232:79] wire [39:0] _jalr_target_T_3 = _jalr_target_T_2 & 40'hFFFFFFFFFE; // @[functional-unit.scala:232:{79,86}] wire [39:0] _jalr_target_T_4 = _jalr_target_T_3; // @[functional-unit.scala:232:86] wire [39:0] jalr_target = _jalr_target_T_4; // @[functional-unit.scala:232:{86,94}] assign brinfo_bits_jalr_target = jalr_target; // @[functional-unit.scala:232:94, :252:20] wire [2:0] cfi_idx = _cfi_idx_T_3[3:1]; // @[functional-unit.scala:234:{30,120}] wire _brinfo_valid_T = is_br \| is_jalr; // @[functional-unit.scala:225:50, :227:37, :237:15, :255:34] wire _mispredict_T = ~io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7, :242:21] wire _mispredict_T_2 = \|jalr_target; // @[functional-unit.scala:232:94, :246:50] wire _mispredict_T_6 = \|cfi_idx; // @[functional-unit.scala:234:120, :248:66] assign mispredict = _brinfo_valid_T & (pc_sel == 2'h2 \| (pc_sel == 2'h1 ? _mispredict_T : ~(\|pc_sel) & io_req_bits_uop_taken_0)); // @[functional-unit.scala:133:7, :188:48, :202:28, :223:28, :237:27, :238:{18,32}, :239:18, :241:{18,32}, :242:{18,21}, :244:{18,31}, :245:18, :255:34] assign io_brinfo_valid = brinfo_valid; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_inst = brinfo_bits_uop_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_inst = brinfo_bits_uop_debug_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_rvc = brinfo_bits_uop_is_rvc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_pc = brinfo_bits_uop_debug_pc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_0 = brinfo_bits_uop_iq_type_0; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_1 = brinfo_bits_uop_iq_type_1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_2 = brinfo_bits_uop_iq_type_2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_3 = brinfo_bits_uop_iq_type_3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_0 = brinfo_bits_uop_fu_code_0; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_1 = brinfo_bits_uop_fu_code_1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_2 = brinfo_bits_uop_fu_code_2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_3 = brinfo_bits_uop_fu_code_3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_4 = brinfo_bits_uop_fu_code_4; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_5 = brinfo_bits_uop_fu_code_5; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_6 = brinfo_bits_uop_fu_code_6; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_7 = brinfo_bits_uop_fu_code_7; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_8 = brinfo_bits_uop_fu_code_8; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_9 = brinfo_bits_uop_fu_code_9; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued = brinfo_bits_uop_iw_issued; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued_partial_agen = brinfo_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued_partial_dgen = brinfo_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p1_speculative_child = brinfo_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p2_speculative_child = brinfo_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p1_bypass_hint = brinfo_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p2_bypass_hint = brinfo_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p3_bypass_hint = brinfo_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_dis_col_sel = brinfo_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_mask = brinfo_bits_uop_br_mask; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_tag = brinfo_bits_uop_br_tag; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_type = brinfo_bits_uop_br_type; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sfb = brinfo_bits_uop_is_sfb; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_fence = brinfo_bits_uop_is_fence; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_fencei = brinfo_bits_uop_is_fencei; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sfence = brinfo_bits_uop_is_sfence; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_amo = brinfo_bits_uop_is_amo; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_eret = brinfo_bits_uop_is_eret; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sys_pc2epc = brinfo_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_rocc = brinfo_bits_uop_is_rocc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_mov = brinfo_bits_uop_is_mov; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ftq_idx = brinfo_bits_uop_ftq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_edge_inst = brinfo_bits_uop_edge_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pc_lob = brinfo_bits_uop_pc_lob; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_taken = brinfo_bits_uop_taken; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_rename = brinfo_bits_uop_imm_rename; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_sel = brinfo_bits_uop_imm_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pimm = brinfo_bits_uop_pimm; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_packed = brinfo_bits_uop_imm_packed; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_op1_sel = brinfo_bits_uop_op1_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_op2_sel = brinfo_bits_uop_op2_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ldst = brinfo_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_wen = brinfo_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren1 = brinfo_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren2 = brinfo_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren3 = brinfo_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_swap12 = brinfo_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_swap23 = brinfo_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_typeTagIn = brinfo_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_typeTagOut = brinfo_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fromint = brinfo_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_toint = brinfo_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fastpipe = brinfo_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fma = brinfo_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_div = brinfo_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_sqrt = brinfo_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_wflags = brinfo_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_vec = brinfo_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_rob_idx = brinfo_bits_uop_rob_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldq_idx = brinfo_bits_uop_ldq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_stq_idx = brinfo_bits_uop_stq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_rxq_idx = brinfo_bits_uop_rxq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pdst = brinfo_bits_uop_pdst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs1 = brinfo_bits_uop_prs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs2 = brinfo_bits_uop_prs2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs3 = brinfo_bits_uop_prs3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ppred = brinfo_bits_uop_ppred; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs1_busy = brinfo_bits_uop_prs1_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs2_busy = brinfo_bits_uop_prs2_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs3_busy = brinfo_bits_uop_prs3_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ppred_busy = brinfo_bits_uop_ppred_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_stale_pdst = brinfo_bits_uop_stale_pdst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_exception = brinfo_bits_uop_exception; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_exc_cause = brinfo_bits_uop_exc_cause; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_cmd = brinfo_bits_uop_mem_cmd; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_size = brinfo_bits_uop_mem_size; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_signed = brinfo_bits_uop_mem_signed; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_uses_ldq = brinfo_bits_uop_uses_ldq; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_uses_stq = brinfo_bits_uop_uses_stq; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_unique = brinfo_bits_uop_is_unique; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_flush_on_commit = brinfo_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_csr_cmd = brinfo_bits_uop_csr_cmd; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldst_is_rs1 = brinfo_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldst = brinfo_bits_uop_ldst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs1 = brinfo_bits_uop_lrs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs2 = brinfo_bits_uop_lrs2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs3 = brinfo_bits_uop_lrs3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_dst_rtype = brinfo_bits_uop_dst_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs1_rtype = brinfo_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs2_rtype = brinfo_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_frs3_en = brinfo_bits_uop_frs3_en; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fcn_dw = brinfo_bits_uop_fcn_dw; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fcn_op = brinfo_bits_uop_fcn_op; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_val = brinfo_bits_uop_fp_val; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_rm = brinfo_bits_uop_fp_rm; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_typ = brinfo_bits_uop_fp_typ; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_pf_if = brinfo_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_ae_if = brinfo_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_ma_if = brinfo_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_bp_debug_if = brinfo_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_bp_xcpt_if = brinfo_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_fsrc = brinfo_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_tsrc = brinfo_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_mispredict = brinfo_bits_mispredict; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_taken = brinfo_bits_taken; // @[functional-unit.scala:133:7, :252:20] wire [2:0] _brinfo_bits_cfi_type_T_1; // @[functional-unit.scala:258:36] assign io_brinfo_bits_cfi_type = brinfo_bits_cfi_type; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_pc_sel = brinfo_bits_pc_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_jalr_target = brinfo_bits_jalr_target; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_target_offset = brinfo_bits_target_offset; // @[functional-unit.scala:133:7, :252:20] assign brinfo_valid = _brinfo_valid_T; // @[functional-unit.scala:252:20, :255:34] wire [2:0] _brinfo_bits_cfi_type_T = {2'h0, is_br}; // @[functional-unit.scala:225:50, :259:36] assign _brinfo_bits_cfi_type_T_1 = is_jalr ? 3'h3 : _brinfo_bits_cfi_type_T; // @[functional-unit.scala:227:37, :258:36, :259:36] assign brinfo_bits_cfi_type = _brinfo_bits_cfi_type_T_1; // @[functional-unit.scala:252:20, :258:36] wire _alu_out_T = ~(\|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _alu_out_T_1 = _alu_out_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _alu_out_T_2 = _alu_out_T_1; // @[micro-op.scala:121:{42,52}] wire [63:0] _alu_out_T_4 = io_req_bits_uop_ldst_is_rs1_0 ? io_req_bits_rs1_data_0 : io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :286:10] wire [63:0] _alu_out_T_5 = io_req_bits_uop_is_mov_0 ? io_req_bits_rs2_data_0 : _alu_io_out; // @[functional-unit.scala:133:7, :173:19, :287:10] wire [63:0] alu_out = _alu_out_T_5; // @[functional-unit.scala:285:20, :287:10] wire _io_resp_bits_data_T = \|io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7, :188:48] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _io_resp_bits_data_T_2 = _io_resp_bits_data_T_1; // @[micro-op.scala:120:{42,52}] wire _io_resp_bits_data_T_3 = pc_sel == 2'h1; // @[functional-unit.scala:188:48, :290:62] assign _io_resp_bits_data_T_4 = _io_resp_bits_data_T_2 ? {63'h0, _io_resp_bits_data_T_3} : alu_out; // @[OneHot.scala:58:35] assign io_resp_bits_data_0 = _io_resp_bits_data_T_4; // @[functional-unit.scala:133:7, :290:27] wire _io_resp_bits_predicated_T = ~(\|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _io_resp_bits_predicated_T_1 = _io_resp_bits_predicated_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _io_resp_bits_predicated_T_2 = _io_resp_bits_predicated_T_1; // @[micro-op.scala:121:{42,52}] ALU alu ( // @[functional-unit.scala:173:19] .clock (clock), .reset (reset), .io_dw (_alu_io_dw_T_1), // @[functional-unit.scala:178:20] .io_fn (io_req_bits_uop_fcn_op_0), // @[functional-unit.scala:133:7] .io_in2 (op2_data), // @[functional-unit.scala:164:45] .io_in1 (op1_data[63:0]), // @[functional-unit.scala:155:45, :175:14] .io_out (_alu_io_out) ); // @[functional-unit.scala:173:19] assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_1 = io_resp_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_2 = io_resp_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_3 = io_resp_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_1 = io_resp_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_2 = io_resp_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_3 = io_resp_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_4 = io_resp_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_5 = io_resp_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_6 = io_resp_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_7 = io_resp_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_8 = io_resp_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_9 = io_resp_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued = io_resp_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued_partial_agen = io_resp_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued_partial_dgen = io_resp_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p1_speculative_child = io_resp_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p2_speculative_child = io_resp_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p1_bypass_hint = io_resp_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p2_bypass_hint = io_resp_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p3_bypass_hint = io_resp_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_dis_col_sel = io_resp_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_type = io_resp_bits_uop_br_type_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sfence = io_resp_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_eret = io_resp_bits_uop_is_eret_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_rocc = io_resp_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_mov = io_resp_bits_uop_is_mov_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_rename = io_resp_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_sel = io_resp_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pimm = io_resp_bits_uop_pimm_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_op1_sel = io_resp_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_op2_sel = io_resp_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ldst = io_resp_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_wen = io_resp_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren1 = io_resp_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren2 = io_resp_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren3 = io_resp_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_swap12 = io_resp_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_swap23 = io_resp_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_typeTagIn = io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_typeTagOut = io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fromint = io_resp_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_toint = io_resp_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fastpipe = io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fma = io_resp_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_div = io_resp_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_sqrt = io_resp_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_wflags = io_resp_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_vec = io_resp_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_csr_cmd = io_resp_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fcn_dw = io_resp_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fcn_op = io_resp_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_rm = io_resp_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_typ = io_resp_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:133:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_36 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_36( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_44 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_300 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_44( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_300 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_83 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_135 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_83( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_135 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_sbus_i2_o2_a32d32s6k3z4u : input clock : Clock input reset : Reset output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready inst monitor of TLMonitor connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_1 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}[2] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.mask, UInt<4>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<32>(0h0) connect _WIRE_4.bits.mask, UInt<4>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<6>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_16.bits.sink, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_18.bits.sink, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_20.bits.sink, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_22.bits.sink, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt connect in[1].a.bits.data, anonIn_1.a.bits.data connect in[1].a.bits.mask, anonIn_1.a.bits.mask connect in[1].a.bits.address, anonIn_1.a.bits.address connect in[1].a.bits.source, anonIn_1.a.bits.source connect in[1].a.bits.size, anonIn_1.a.bits.size connect in[1].a.bits.param, anonIn_1.a.bits.param connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode connect in[1].a.valid, anonIn_1.a.valid connect anonIn_1.a.ready, in[1].a.ready node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<6>(0h20)) connect in[1].a.bits.source, _in_1_a_bits_source_T wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.mask, UInt<4>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<32>(0h0) connect _WIRE_26.bits.mask, UInt<4>(0h0) connect _WIRE_26.bits.address, UInt<32>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<32>(0h0) connect _WIRE_28.bits.mask, UInt<4>(0h0) connect _WIRE_28.bits.address, UInt<32>(0h0) connect _WIRE_28.bits.source, UInt<6>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.ready, UInt<1>(0h1) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<32>(0h0) connect _WIRE_30.bits.mask, UInt<4>(0h0) connect _WIRE_30.bits.address, UInt<32>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<4>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.valid, UInt<1>(0h0) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<32>(0h0) connect _WIRE_32.bits.address, UInt<32>(0h0) connect _WIRE_32.bits.source, UInt<6>(0h0) connect _WIRE_32.bits.size, UInt<4>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<32>(0h0) connect _WIRE_34.bits.address, UInt<32>(0h0) connect _WIRE_34.bits.source, UInt<1>(0h0) connect _WIRE_34.bits.size, UInt<4>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<32>(0h0) connect _WIRE_36.bits.address, UInt<32>(0h0) connect _WIRE_36.bits.source, UInt<6>(0h0) connect _WIRE_36.bits.size, UInt<4>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.valid, UInt<1>(0h0) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<32>(0h0) connect _WIRE_38.bits.address, UInt<32>(0h0) connect _WIRE_38.bits.source, UInt<1>(0h0) connect _WIRE_38.bits.size, UInt<4>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.ready, UInt<1>(0h1) connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt connect anonIn_1.d.bits.data, in[1].d.bits.data connect anonIn_1.d.bits.denied, in[1].d.bits.denied connect anonIn_1.d.bits.sink, in[1].d.bits.sink connect anonIn_1.d.bits.source, in[1].d.bits.source connect anonIn_1.d.bits.size, in[1].d.bits.size connect anonIn_1.d.bits.param, in[1].d.bits.param connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode connect anonIn_1.d.valid, in[1].d.valid connect in[1].d.ready, anonIn_1.d.ready node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 0, 0) connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1 wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_40.bits.sink, UInt<3>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_42.bits.sink, UInt<3>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_44.bits.sink, UInt<3>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.valid, UInt<1>(0h0) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_46.bits.sink, UInt<3>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<32>(0h0) connect _WIRE_48.bits.mask, UInt<4>(0h0) connect _WIRE_48.bits.address, UInt<32>(0h0) connect _WIRE_48.bits.source, UInt<6>(0h0) connect _WIRE_48.bits.size, UInt<4>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<32>(0h0) connect _WIRE_50.bits.mask, UInt<4>(0h0) connect _WIRE_50.bits.address, UInt<29>(0h0) connect _WIRE_50.bits.source, UInt<6>(0h0) connect _WIRE_50.bits.size, UInt<4>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<32>(0h0) connect _WIRE_52.bits.mask, UInt<4>(0h0) connect _WIRE_52.bits.address, UInt<32>(0h0) connect _WIRE_52.bits.source, UInt<6>(0h0) connect _WIRE_52.bits.size, UInt<4>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<32>(0h0) connect _WIRE_54.bits.mask, UInt<4>(0h0) connect _WIRE_54.bits.address, UInt<29>(0h0) connect _WIRE_54.bits.source, UInt<6>(0h0) connect _WIRE_54.bits.size, UInt<4>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<32>(0h0) connect _WIRE_56.bits.address, UInt<32>(0h0) connect _WIRE_56.bits.source, UInt<6>(0h0) connect _WIRE_56.bits.size, UInt<4>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<32>(0h0) connect _WIRE_58.bits.address, UInt<29>(0h0) connect _WIRE_58.bits.source, UInt<6>(0h0) connect _WIRE_58.bits.size, UInt<4>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<32>(0h0) connect _WIRE_60.bits.address, UInt<32>(0h0) connect _WIRE_60.bits.source, UInt<6>(0h0) connect _WIRE_60.bits.size, UInt<4>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<32>(0h0) connect _WIRE_62.bits.address, UInt<29>(0h0) connect _WIRE_62.bits.source, UInt<6>(0h0) connect _WIRE_62.bits.size, UInt<4>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_64.bits.sink, UInt<3>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_68.bits.sink, UInt<3>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<32>(0h0) connect _WIRE_72.bits.mask, UInt<4>(0h0) connect _WIRE_72.bits.address, UInt<32>(0h0) connect _WIRE_72.bits.source, UInt<6>(0h0) connect _WIRE_72.bits.size, UInt<4>(0h0) connect _WIRE_72.bits.param, UInt<2>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.mask invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode invalidate _WIRE_73.valid invalidate _WIRE_73.ready wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_74.bits.corrupt, UInt<1>(0h0) connect _WIRE_74.bits.data, UInt<32>(0h0) connect _WIRE_74.bits.mask, UInt<4>(0h0) connect _WIRE_74.bits.address, UInt<32>(0h0) connect _WIRE_74.bits.source, UInt<6>(0h0) connect _WIRE_74.bits.size, UInt<3>(0h0) connect _WIRE_74.bits.param, UInt<2>(0h0) connect _WIRE_74.bits.opcode, UInt<3>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.corrupt invalidate _WIRE_75.bits.data invalidate _WIRE_75.bits.mask invalidate _WIRE_75.bits.address invalidate _WIRE_75.bits.source invalidate _WIRE_75.bits.size invalidate _WIRE_75.bits.param invalidate _WIRE_75.bits.opcode invalidate _WIRE_75.valid invalidate _WIRE_75.ready wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<32>(0h0) connect _WIRE_76.bits.mask, UInt<4>(0h0) connect _WIRE_76.bits.address, UInt<32>(0h0) connect _WIRE_76.bits.source, UInt<6>(0h0) connect _WIRE_76.bits.size, UInt<4>(0h0) connect _WIRE_76.bits.param, UInt<2>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready connect _WIRE_77.valid, UInt<1>(0h0) wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_78.bits.corrupt, UInt<1>(0h0) connect _WIRE_78.bits.data, UInt<32>(0h0) connect _WIRE_78.bits.mask, UInt<4>(0h0) connect _WIRE_78.bits.address, UInt<32>(0h0) connect _WIRE_78.bits.source, UInt<6>(0h0) connect _WIRE_78.bits.size, UInt<3>(0h0) connect _WIRE_78.bits.param, UInt<2>(0h0) connect _WIRE_78.bits.opcode, UInt<3>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready connect _WIRE_79.ready, UInt<1>(0h1) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<32>(0h0) connect _WIRE_80.bits.address, UInt<32>(0h0) connect _WIRE_80.bits.source, UInt<6>(0h0) connect _WIRE_80.bits.size, UInt<4>(0h0) connect _WIRE_80.bits.param, UInt<3>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode invalidate _WIRE_81.valid invalidate _WIRE_81.ready wire _WIRE_82 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_82.bits.corrupt, UInt<1>(0h0) connect _WIRE_82.bits.data, UInt<32>(0h0) connect _WIRE_82.bits.address, UInt<32>(0h0) connect _WIRE_82.bits.source, UInt<6>(0h0) connect _WIRE_82.bits.size, UInt<3>(0h0) connect _WIRE_82.bits.param, UInt<3>(0h0) connect _WIRE_82.bits.opcode, UInt<3>(0h0) connect _WIRE_82.valid, UInt<1>(0h0) connect _WIRE_82.ready, UInt<1>(0h0) wire _WIRE_83 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_83.bits, _WIRE_82.bits connect _WIRE_83.valid, _WIRE_82.valid connect _WIRE_83.ready, _WIRE_82.ready invalidate _WIRE_83.bits.corrupt invalidate _WIRE_83.bits.data invalidate _WIRE_83.bits.address invalidate _WIRE_83.bits.source invalidate _WIRE_83.bits.size invalidate _WIRE_83.bits.param invalidate _WIRE_83.bits.opcode invalidate _WIRE_83.valid invalidate _WIRE_83.ready wire _WIRE_84 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_84.bits.corrupt, UInt<1>(0h0) connect _WIRE_84.bits.data, UInt<32>(0h0) connect _WIRE_84.bits.address, UInt<32>(0h0) connect _WIRE_84.bits.source, UInt<6>(0h0) connect _WIRE_84.bits.size, UInt<4>(0h0) connect _WIRE_84.bits.param, UInt<3>(0h0) connect _WIRE_84.bits.opcode, UInt<3>(0h0) connect _WIRE_84.valid, UInt<1>(0h0) connect _WIRE_84.ready, UInt<1>(0h0) wire _WIRE_85 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_85.bits, _WIRE_84.bits connect _WIRE_85.valid, _WIRE_84.valid connect _WIRE_85.ready, _WIRE_84.ready connect _WIRE_85.ready, UInt<1>(0h1) wire _WIRE_86 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_86.bits.corrupt, UInt<1>(0h0) connect _WIRE_86.bits.data, UInt<32>(0h0) connect _WIRE_86.bits.address, UInt<32>(0h0) connect _WIRE_86.bits.source, UInt<6>(0h0) connect _WIRE_86.bits.size, UInt<3>(0h0) connect _WIRE_86.bits.param, UInt<3>(0h0) connect _WIRE_86.bits.opcode, UInt<3>(0h0) connect _WIRE_86.valid, UInt<1>(0h0) connect _WIRE_86.ready, UInt<1>(0h0) wire _WIRE_87 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_87.bits, _WIRE_86.bits connect _WIRE_87.valid, _WIRE_86.valid connect _WIRE_87.ready, _WIRE_86.ready connect _WIRE_87.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_88 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_88.bits.sink, UInt<3>(0h0) connect _WIRE_88.valid, UInt<1>(0h0) connect _WIRE_88.ready, UInt<1>(0h0) wire _WIRE_89 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_89.bits, _WIRE_88.bits connect _WIRE_89.valid, _WIRE_88.valid connect _WIRE_89.ready, _WIRE_88.ready invalidate _WIRE_89.bits.sink invalidate _WIRE_89.valid invalidate _WIRE_89.ready wire _WIRE_90 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_90.bits.sink, UInt<3>(0h0) connect _WIRE_90.valid, UInt<1>(0h0) connect _WIRE_90.ready, UInt<1>(0h0) wire _WIRE_91 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_91.bits, _WIRE_90.bits connect _WIRE_91.valid, _WIRE_90.valid connect _WIRE_91.ready, _WIRE_90.ready invalidate _WIRE_91.bits.sink invalidate _WIRE_91.valid invalidate _WIRE_91.ready wire _WIRE_92 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_92.bits.sink, UInt<3>(0h0) connect _WIRE_92.valid, UInt<1>(0h0) connect _WIRE_92.ready, UInt<1>(0h0) wire _WIRE_93 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_93.bits, _WIRE_92.bits connect _WIRE_93.valid, _WIRE_92.valid connect _WIRE_93.ready, _WIRE_92.ready connect _WIRE_93.ready, UInt<1>(0h1) wire _WIRE_94 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_94.bits.sink, UInt<3>(0h0) connect _WIRE_94.valid, UInt<1>(0h0) connect _WIRE_94.ready, UInt<1>(0h0) wire _WIRE_95 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_95.bits, _WIRE_94.bits connect _WIRE_95.valid, _WIRE_94.valid connect _WIRE_95.ready, _WIRE_94.ready connect _WIRE_95.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<32>(0h0) connect _addressC_WIRE.bits.address, UInt<32>(0h0) connect _addressC_WIRE.bits.source, UInt<6>(0h0) connect _addressC_WIRE.bits.size, UInt<4>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE_2.bits.data, UInt<32>(0h0) connect _addressC_WIRE_2.bits.address, UInt<32>(0h0) connect _addressC_WIRE_2.bits.source, UInt<6>(0h0) connect _addressC_WIRE_2.bits.size, UInt<4>(0h0) connect _addressC_WIRE_2.bits.param, UInt<3>(0h0) connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE_2.valid, UInt<1>(0h0) connect _addressC_WIRE_2.ready, UInt<1>(0h0) wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_11 = cvt(_requestAIO_T_10) node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_13 = asSInt(_requestAIO_T_12) node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0))) node _requestAIO_T_15 = or(_requestAIO_T_4, _requestAIO_T_9) node _requestAIO_T_16 = or(_requestAIO_T_15, _requestAIO_T_14) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_16) node _requestAIO_T_17 = xor(in[0].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_18 = cvt(_requestAIO_T_17) node _requestAIO_T_19 = and(_requestAIO_T_18, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_20 = asSInt(_requestAIO_T_19) node _requestAIO_T_21 = eq(_requestAIO_T_20, asSInt(UInt<1>(0h0))) node _requestAIO_T_22 = xor(in[0].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_23 = cvt(_requestAIO_T_22) node _requestAIO_T_24 = and(_requestAIO_T_23, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_25 = asSInt(_requestAIO_T_24) node _requestAIO_T_26 = eq(_requestAIO_T_25, asSInt(UInt<1>(0h0))) node _requestAIO_T_27 = or(_requestAIO_T_21, _requestAIO_T_26) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_27) node _requestAIO_T_28 = xor(in[1].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_29 = cvt(_requestAIO_T_28) node _requestAIO_T_30 = and(_requestAIO_T_29, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_31 = asSInt(_requestAIO_T_30) node _requestAIO_T_32 = eq(_requestAIO_T_31, asSInt(UInt<1>(0h0))) node _requestAIO_T_33 = xor(in[1].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_34 = cvt(_requestAIO_T_33) node _requestAIO_T_35 = and(_requestAIO_T_34, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_36 = asSInt(_requestAIO_T_35) node _requestAIO_T_37 = eq(_requestAIO_T_36, asSInt(UInt<1>(0h0))) node _requestAIO_T_38 = xor(in[1].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_39 = cvt(_requestAIO_T_38) node _requestAIO_T_40 = and(_requestAIO_T_39, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_41 = asSInt(_requestAIO_T_40) node _requestAIO_T_42 = eq(_requestAIO_T_41, asSInt(UInt<1>(0h0))) node _requestAIO_T_43 = or(_requestAIO_T_32, _requestAIO_T_37) node _requestAIO_T_44 = or(_requestAIO_T_43, _requestAIO_T_42) node requestAIO_1_0 = or(UInt<1>(0h0), _requestAIO_T_44) node _requestAIO_T_45 = xor(in[1].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_46 = cvt(_requestAIO_T_45) node _requestAIO_T_47 = and(_requestAIO_T_46, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_48 = asSInt(_requestAIO_T_47) node _requestAIO_T_49 = eq(_requestAIO_T_48, asSInt(UInt<1>(0h0))) node _requestAIO_T_50 = xor(in[1].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_51 = cvt(_requestAIO_T_50) node _requestAIO_T_52 = and(_requestAIO_T_51, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_53 = asSInt(_requestAIO_T_52) node _requestAIO_T_54 = eq(_requestAIO_T_53, asSInt(UInt<1>(0h0))) node _requestAIO_T_55 = or(_requestAIO_T_49, _requestAIO_T_54) node requestAIO_1_1 = or(UInt<1>(0h0), _requestAIO_T_55) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) node _requestCIO_T_10 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0)) node _requestCIO_T_11 = cvt(_requestCIO_T_10) node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0))) node _requestCIO_T_13 = asSInt(_requestCIO_T_12) node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0))) node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_14) node _requestCIO_T_15 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0)) node _requestCIO_T_16 = cvt(_requestCIO_T_15) node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0))) node _requestCIO_T_18 = asSInt(_requestCIO_T_17) node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0))) node requestCIO_1_1 = or(UInt<1>(0h1), _requestCIO_T_19) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<32>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<4>(0h0) connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE.bits.source, UInt<6>(0h0) connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 5) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<32>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<4>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<6>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<1>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 0, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 1) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<5>(0h10)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<1>(0h1)) node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9) wire _requestBOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_4.bits.data, UInt<32>(0h0) connect _requestBOI_WIRE_4.bits.mask, UInt<4>(0h0) connect _requestBOI_WIRE_4.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_4.bits.source, UInt<6>(0h0) connect _requestBOI_WIRE_4.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_4.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_4.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_4.valid, UInt<1>(0h0) connect _requestBOI_WIRE_4.ready, UInt<1>(0h0) wire _requestBOI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_5.bits, _requestBOI_WIRE_4.bits connect _requestBOI_WIRE_5.valid, _requestBOI_WIRE_4.valid connect _requestBOI_WIRE_5.ready, _requestBOI_WIRE_4.ready node _requestBOI_uncommonBits_T_2 = or(_requestBOI_WIRE_5.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 4, 0) node _requestBOI_T_10 = shr(_requestBOI_WIRE_5.bits.source, 5) node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h0)) node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2) node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12) node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<5>(0h1f)) node requestBOI_1_0 = and(_requestBOI_T_13, _requestBOI_T_14) wire _requestBOI_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_6.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_6.bits.data, UInt<32>(0h0) connect _requestBOI_WIRE_6.bits.mask, UInt<4>(0h0) connect _requestBOI_WIRE_6.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_6.bits.source, UInt<6>(0h0) connect _requestBOI_WIRE_6.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_6.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_6.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_6.valid, UInt<1>(0h0) connect _requestBOI_WIRE_6.ready, UInt<1>(0h0) wire _requestBOI_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_7.bits, _requestBOI_WIRE_6.bits connect _requestBOI_WIRE_7.valid, _requestBOI_WIRE_6.valid connect _requestBOI_WIRE_7.ready, _requestBOI_WIRE_6.ready node _requestBOI_uncommonBits_T_3 = or(_requestBOI_WIRE_7.bits.source, UInt<1>(0h0)) node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 0, 0) node _requestBOI_T_15 = shr(_requestBOI_WIRE_7.bits.source, 1) node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<5>(0h10)) node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3) node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17) node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<1>(0h1)) node requestBOI_1_1 = and(_requestBOI_T_18, _requestBOI_T_19) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0) node _requestDOI_T = shr(out[0].d.bits.source, 5) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<1>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 0, 0) node _requestDOI_T_5 = shr(out[0].d.bits.source, 1) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<5>(0h10)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<1>(0h1)) node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9) node _requestDOI_uncommonBits_T_2 = or(out[1].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 4, 0) node _requestDOI_T_10 = shr(out[1].d.bits.source, 5) node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h0)) node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2) node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12) node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<5>(0h1f)) node requestDOI_1_0 = and(_requestDOI_T_13, _requestDOI_T_14) node _requestDOI_uncommonBits_T_3 = or(out[1].d.bits.source, UInt<1>(0h0)) node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 0, 0) node _requestDOI_T_15 = shr(out[1].d.bits.source, 1) node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<5>(0h10)) node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3) node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17) node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<1>(0h1)) node requestDOI_1_1 = and(_requestDOI_T_18, _requestDOI_T_19) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE.bits.sink, UInt<3>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_2.bits.sink, UInt<3>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _requestEIO_uncommonBits_T = or(_requestEIO_WIRE_3.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0) node _requestEIO_T = shr(_requestEIO_WIRE_3.bits.sink, 3) node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0)) node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits) node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2) node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7)) node requestEIO_0_1 = and(_requestEIO_T_3, _requestEIO_T_4) wire _requestEIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_4.bits.sink, UInt<3>(0h0) connect _requestEIO_WIRE_4.valid, UInt<1>(0h0) connect _requestEIO_WIRE_4.ready, UInt<1>(0h0) wire _requestEIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_5.bits, _requestEIO_WIRE_4.bits connect _requestEIO_WIRE_5.valid, _requestEIO_WIRE_4.valid connect _requestEIO_WIRE_5.ready, _requestEIO_WIRE_4.ready wire _requestEIO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_6.bits.sink, UInt<3>(0h0) connect _requestEIO_WIRE_6.valid, UInt<1>(0h0) connect _requestEIO_WIRE_6.ready, UInt<1>(0h0) wire _requestEIO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_7.bits, _requestEIO_WIRE_6.bits connect _requestEIO_WIRE_7.valid, _requestEIO_WIRE_6.valid connect _requestEIO_WIRE_7.ready, _requestEIO_WIRE_6.ready node _requestEIO_uncommonBits_T_1 = or(_requestEIO_WIRE_7.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0) node _requestEIO_T_5 = shr(_requestEIO_WIRE_7.bits.sink, 3) node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0)) node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1) node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7) node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7)) node requestEIO_1_1 = and(_requestEIO_T_8, _requestEIO_T_9) node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 2) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 2) node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<32>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<4>(0h0) connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE.bits.source, UInt<6>(0h0) connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 2) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<32>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<4>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<6>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 2) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<32>(0h0) connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE.bits.source, UInt<6>(0h0) connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 2) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.data, UInt<32>(0h0) connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE_2.bits.source, UInt<6>(0h0) connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE_2.valid, UInt<1>(0h0) connect _beatsCI_WIRE_2.ready, UInt<1>(0h0) wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size) node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 2) node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0) node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 2) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 2) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _beatsEI_WIRE.bits.sink, UInt<3>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _beatsEI_WIRE_2.bits.sink, UInt<3>(0h0) connect _beatsEI_WIRE_2.valid, UInt<1>(0h0) connect _beatsEI_WIRE_2.ready, UInt<1>(0h0) wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsAOI_filtered_1[0].bits, in[1].a.bits node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 connect portsAOI_filtered_1[1].bits, in[1].a.bits node _portsAOI_filtered_1_valid_T_2 = or(requestAIO_1_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_1_valid_T_2) connect portsAOI_filtered_1[1].valid, _portsAOI_filtered_1_valid_T_3 node _portsAOI_in_1_a_ready_T = mux(requestAIO_1_0, portsAOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsAOI_in_1_a_ready_T_1 = mux(requestAIO_1_1, portsAOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsAOI_in_1_a_ready_T_2 = or(_portsAOI_in_1_a_ready_T, _portsAOI_in_1_a_ready_T_1) wire _portsAOI_in_1_a_ready_WIRE : UInt<1> connect _portsAOI_in_1_a_ready_WIRE, _portsAOI_in_1_a_ready_T_2 connect in[1].a.ready, _portsAOI_in_1_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<32>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<4>(0h0) connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE.bits.source, UInt<6>(0h0) connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T) connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1) wire _portsBIO_WIRE_2 : UInt<1> connect _portsBIO_WIRE_2, _portsBIO_T_2 connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2 wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_3.bits.data, UInt<32>(0h0) connect _portsBIO_WIRE_3.bits.mask, UInt<4>(0h0) connect _portsBIO_WIRE_3.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE_3.bits.source, UInt<6>(0h0) connect _portsBIO_WIRE_3.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE_3.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_3.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_3.valid, UInt<1>(0h0) connect _portsBIO_WIRE_3.ready, UInt<1>(0h0) wire _portsBIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _portsBIO_WIRE_4.bits, _portsBIO_WIRE_3.bits connect _portsBIO_WIRE_4.valid, _portsBIO_WIRE_3.valid connect _portsBIO_WIRE_4.ready, _portsBIO_WIRE_3.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_4.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_4.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect portsBIO_filtered_1[1].bits, _portsBIO_WIRE_4.bits node _portsBIO_filtered_1_valid_T_2 = or(requestBOI_1_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_3 = and(_portsBIO_WIRE_4.valid, _portsBIO_filtered_1_valid_T_2) connect portsBIO_filtered_1[1].valid, _portsBIO_filtered_1_valid_T_3 node _portsBIO_T_3 = mux(requestBOI_1_0, portsBIO_filtered_1[0].ready, UInt<1>(0h0)) node _portsBIO_T_4 = mux(requestBOI_1_1, portsBIO_filtered_1[1].ready, UInt<1>(0h0)) node _portsBIO_T_5 = or(_portsBIO_T_3, _portsBIO_T_4) wire _portsBIO_WIRE_5 : UInt<1> connect _portsBIO_WIRE_5, _portsBIO_T_5 connect _portsBIO_WIRE_4.ready, _portsBIO_WIRE_5 wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<32>(0h0) connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE.bits.source, UInt<6>(0h0) connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_2 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _portsCOI_WIRE_3.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE_3.bits.data, UInt<32>(0h0) connect _portsCOI_WIRE_3.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE_3.bits.source, UInt<6>(0h0) connect _portsCOI_WIRE_3.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE_3.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE_3.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE_3.valid, UInt<1>(0h0) connect _portsCOI_WIRE_3.ready, UInt<1>(0h0) wire _portsCOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _portsCOI_WIRE_4.bits, _portsCOI_WIRE_3.bits connect _portsCOI_WIRE_4.valid, _portsCOI_WIRE_3.valid connect _portsCOI_WIRE_4.ready, _portsCOI_WIRE_3.ready wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_4.bits node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_4.valid, _portsCOI_filtered_0_valid_T_2) connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 connect portsCOI_filtered_1[1].bits, _portsCOI_WIRE_4.bits node _portsCOI_filtered_1_valid_T_2 = or(requestCIO_1_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_3 = and(_portsCOI_WIRE_4.valid, _portsCOI_filtered_1_valid_T_2) connect portsCOI_filtered_1[1].valid, _portsCOI_filtered_1_valid_T_3 node _portsCOI_T_3 = mux(requestCIO_1_0, portsCOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsCOI_T_4 = mux(requestCIO_1_1, portsCOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsCOI_T_5 = or(_portsCOI_T_3, _portsCOI_T_4) wire _portsCOI_WIRE_5 : UInt<1> connect _portsCOI_WIRE_5, _portsCOI_T_5 connect _portsCOI_WIRE_4.ready, _portsCOI_WIRE_5 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[1].bits.data, out[0].d.bits.data connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[1].bits.source, out[0].d.bits.source connect portsDIO_filtered[1].bits.size, out[0].d.bits.size connect portsDIO_filtered[1].bits.param, out[0].d.bits.param connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) wire _portsDIO_out_0_d_ready_WIRE : UInt<1> connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect portsDIO_filtered_1[1].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[1].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[1].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[1].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[1].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[1].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[1].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[1].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_1_valid_T_2 = or(requestDOI_1_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_1_valid_T_2) connect portsDIO_filtered_1[1].valid, _portsDIO_filtered_1_valid_T_3 node _portsDIO_out_1_d_ready_T = mux(requestDOI_1_0, portsDIO_filtered_1[0].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_1 = mux(requestDOI_1_1, portsDIO_filtered_1[1].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_2 = or(_portsDIO_out_1_d_ready_T, _portsDIO_out_1_d_ready_T_1) wire _portsDIO_out_1_d_ready_WIRE : UInt<1> connect _portsDIO_out_1_d_ready_WIRE, _portsDIO_out_1_d_ready_T_2 connect out[1].d.ready, _portsDIO_out_1_d_ready_WIRE wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _portsEOI_WIRE.bits.sink, UInt<3>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(requestEIO_0_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(requestEIO_0_1, portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_2 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _portsEOI_WIRE_3.bits.sink, UInt<3>(0h0) connect _portsEOI_WIRE_3.valid, UInt<1>(0h0) connect _portsEOI_WIRE_3.ready, UInt<1>(0h0) wire _portsEOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _portsEOI_WIRE_4.bits, _portsEOI_WIRE_3.bits connect _portsEOI_WIRE_4.valid, _portsEOI_WIRE_3.valid connect _portsEOI_WIRE_4.ready, _portsEOI_WIRE_3.ready wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2] connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_4.bits node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_4.valid, _portsEOI_filtered_0_valid_T_2) connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 connect portsEOI_filtered_1[1].bits, _portsEOI_WIRE_4.bits node _portsEOI_filtered_1_valid_T_2 = or(requestEIO_1_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_3 = and(_portsEOI_WIRE_4.valid, _portsEOI_filtered_1_valid_T_2) connect portsEOI_filtered_1[1].valid, _portsEOI_filtered_1_valid_T_3 node _portsEOI_T_3 = mux(UInt<1>(0h0), portsEOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsEOI_T_4 = mux(requestEIO_1_1, portsEOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsEOI_T_5 = or(_portsEOI_T_3, _portsEOI_T_4) wire _portsEOI_WIRE_5 : UInt<1> connect _portsEOI_WIRE_5, _portsEOI_T_5 connect _portsEOI_WIRE_4.ready, _portsEOI_WIRE_5 regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, out[0].a.ready) node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsAOI_filtered[0].valid) node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) connect portsAOI_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) wire _out_0_a_valid_WIRE : UInt<1> connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) connect out[0].a.valid, _out_0_a_valid_T_4 wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) wire _out_0_a_bits_WIRE_1 : UInt<1> connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) wire _out_0_a_bits_WIRE_2 : UInt<32> connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) wire _out_0_a_bits_WIRE_3 : UInt<4> connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 wire _out_0_a_bits_WIRE_4 : { } connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 wire _out_0_a_bits_WIRE_5 : { } connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) wire _out_0_a_bits_WIRE_6 : UInt<32> connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11 connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6 node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) wire _out_0_a_bits_WIRE_7 : UInt<6> connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14 connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7 node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) wire _out_0_a_bits_WIRE_8 : UInt<4> connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17 connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8 node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) wire _out_0_a_bits_WIRE_9 : UInt<3> connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20 connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9 node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) wire _out_0_a_bits_WIRE_10 : UInt<3> connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23 connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10 connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt connect out[0].a.bits.data, _out_0_a_bits_WIRE.data connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask connect out[0].a.bits.address, _out_0_a_bits_WIRE.address connect out[0].a.bits.source, _out_0_a_bits_WIRE.source connect out[0].a.bits.size, _out_0_a_bits_WIRE.size connect out[0].a.bits.param, _out_0_a_bits_WIRE.param connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode wire _WIRE_96 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_96.bits.corrupt, UInt<1>(0h0) connect _WIRE_96.bits.data, UInt<32>(0h0) connect _WIRE_96.bits.address, UInt<32>(0h0) connect _WIRE_96.bits.source, UInt<6>(0h0) connect _WIRE_96.bits.size, UInt<4>(0h0) connect _WIRE_96.bits.param, UInt<3>(0h0) connect _WIRE_96.bits.opcode, UInt<3>(0h0) connect _WIRE_96.valid, UInt<1>(0h0) connect _WIRE_96.ready, UInt<1>(0h0) wire _WIRE_97 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_97.bits, _WIRE_96.bits connect _WIRE_97.valid, _WIRE_96.valid connect _WIRE_97.ready, _WIRE_96.ready invalidate _WIRE_97.bits.corrupt invalidate _WIRE_97.bits.data invalidate _WIRE_97.bits.address invalidate _WIRE_97.bits.source invalidate _WIRE_97.bits.size invalidate _WIRE_97.bits.param invalidate _WIRE_97.bits.opcode wire _WIRE_98 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_98.bits.sink, UInt<3>(0h0) connect _WIRE_98.valid, UInt<1>(0h0) connect _WIRE_98.ready, UInt<1>(0h0) wire _WIRE_99 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_99.bits, _WIRE_98.bits connect _WIRE_99.valid, _WIRE_98.valid connect _WIRE_99.ready, _WIRE_98.ready invalidate _WIRE_99.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0) node idle_1 = eq(beatsLeft_1, UInt<1>(0h0)) node latch_1 = and(idle_1, out[1].a.ready) node _readys_T_10 = cat(portsAOI_filtered_1[1].valid, portsAOI_filtered[1].valid) node readys_valid_1 = bits(_readys_T_10, 1, 0) node _readys_T_11 = eq(readys_valid_1, _readys_T_10) node _readys_T_12 = asUInt(reset) node _readys_T_13 = eq(_readys_T_12, UInt<1>(0h0)) when _readys_T_13 : node _readys_T_14 = eq(_readys_T_11, UInt<1>(0h0)) when _readys_T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_1 assert(clock, _readys_T_11, UInt<1>(0h1), "") : readys_assert_1 regreset readys_mask_1 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_2 = not(readys_mask_1) node _readys_filter_T_3 = and(readys_valid_1, _readys_filter_T_2) node readys_filter_1 = cat(_readys_filter_T_3, readys_valid_1) node _readys_unready_T_5 = shr(readys_filter_1, 1) node _readys_unready_T_6 = or(readys_filter_1, _readys_unready_T_5) node _readys_unready_T_7 = bits(_readys_unready_T_6, 3, 0) node _readys_unready_T_8 = shr(_readys_unready_T_7, 1) node _readys_unready_T_9 = shl(readys_mask_1, 2) node readys_unready_1 = or(_readys_unready_T_8, _readys_unready_T_9) node _readys_readys_T_3 = shr(readys_unready_1, 2) node _readys_readys_T_4 = bits(readys_unready_1, 1, 0) node _readys_readys_T_5 = and(_readys_readys_T_3, _readys_readys_T_4) node readys_readys_1 = not(_readys_readys_T_5) node _readys_T_15 = orr(readys_valid_1) node _readys_T_16 = and(latch_1, _readys_T_15) when _readys_T_16 : node _readys_mask_T_5 = and(readys_readys_1, readys_valid_1) node _readys_mask_T_6 = shl(_readys_mask_T_5, 1) node _readys_mask_T_7 = bits(_readys_mask_T_6, 1, 0) node _readys_mask_T_8 = or(_readys_mask_T_5, _readys_mask_T_7) node _readys_mask_T_9 = bits(_readys_mask_T_8, 1, 0) connect readys_mask_1, _readys_mask_T_9 node _readys_T_17 = bits(readys_readys_1, 1, 0) node _readys_T_18 = bits(_readys_T_17, 0, 0) node _readys_T_19 = bits(_readys_T_17, 1, 1) wire readys_1 : UInt<1>[2] connect readys_1[0], _readys_T_18 connect readys_1[1], _readys_T_19 node _winner_T_2 = and(readys_1[0], portsAOI_filtered[1].valid) node _winner_T_3 = and(readys_1[1], portsAOI_filtered_1[1].valid) wire winner_1 : UInt<1>[2] connect winner_1[0], _winner_T_2 connect winner_1[1], _winner_T_3 node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0]) node _prefixOR_T_1 = or(prefixOR_1_1, winner_1[1]) node _T_17 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_18 = eq(winner_1[0], UInt<1>(0h0)) node _T_19 = or(_T_17, _T_18) node _T_20 = eq(prefixOR_1_1, UInt<1>(0h0)) node _T_21 = eq(winner_1[1], UInt<1>(0h0)) node _T_22 = or(_T_20, _T_21) node _T_23 = and(_T_19, _T_22) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_2 assert(clock, _T_23, UInt<1>(0h1), "") : assert_2 node _T_27 = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid) node _T_28 = eq(_T_27, UInt<1>(0h0)) node _T_29 = or(winner_1[0], winner_1[1]) node _T_30 = or(_T_28, _T_29) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_3 assert(clock, _T_30, UInt<1>(0h1), "") : assert_3 node maskedBeats_0_1 = mux(winner_1[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1_1 = mux(winner_1[1], beatsAI_1, UInt<1>(0h0)) node initBeats_1 = or(maskedBeats_0_1, maskedBeats_1_1) node _beatsLeft_T_4 = and(out[1].a.ready, out[1].a.valid) node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4) node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1) node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6) connect beatsLeft_1, _beatsLeft_T_7 wire _state_WIRE_1 : UInt<1>[2] connect _state_WIRE_1[0], UInt<1>(0h0) connect _state_WIRE_1[1], UInt<1>(0h0) regreset state_1 : UInt<1>[2], clock, reset, _state_WIRE_1 node muxState_1 = mux(idle_1, winner_1, state_1) connect state_1, muxState_1 node allowed_1 = mux(idle_1, readys_1, state_1) node _filtered_1_ready_T = and(out[1].a.ready, allowed_1[0]) connect portsAOI_filtered[1].ready, _filtered_1_ready_T node _filtered_1_ready_T_1 = and(out[1].a.ready, allowed_1[1]) connect portsAOI_filtered_1[1].ready, _filtered_1_ready_T_1 node _out_1_a_valid_T = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid) node _out_1_a_valid_T_1 = mux(state_1[0], portsAOI_filtered[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_2 = mux(state_1[1], portsAOI_filtered_1[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_3 = or(_out_1_a_valid_T_1, _out_1_a_valid_T_2) wire _out_1_a_valid_WIRE : UInt<1> connect _out_1_a_valid_WIRE, _out_1_a_valid_T_3 node _out_1_a_valid_T_4 = mux(idle_1, _out_1_a_valid_T, _out_1_a_valid_WIRE) connect out[1].a.valid, _out_1_a_valid_T_4 wire _out_1_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} node _out_1_a_bits_T = mux(muxState_1[0], portsAOI_filtered[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_1 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_2 = or(_out_1_a_bits_T, _out_1_a_bits_T_1) wire _out_1_a_bits_WIRE_1 : UInt<1> connect _out_1_a_bits_WIRE_1, _out_1_a_bits_T_2 connect _out_1_a_bits_WIRE.corrupt, _out_1_a_bits_WIRE_1 node _out_1_a_bits_T_3 = mux(muxState_1[0], portsAOI_filtered[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_4 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_5 = or(_out_1_a_bits_T_3, _out_1_a_bits_T_4) wire _out_1_a_bits_WIRE_2 : UInt<32> connect _out_1_a_bits_WIRE_2, _out_1_a_bits_T_5 connect _out_1_a_bits_WIRE.data, _out_1_a_bits_WIRE_2 node _out_1_a_bits_T_6 = mux(muxState_1[0], portsAOI_filtered[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_7 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_8 = or(_out_1_a_bits_T_6, _out_1_a_bits_T_7) wire _out_1_a_bits_WIRE_3 : UInt<4> connect _out_1_a_bits_WIRE_3, _out_1_a_bits_T_8 connect _out_1_a_bits_WIRE.mask, _out_1_a_bits_WIRE_3 wire _out_1_a_bits_WIRE_4 : { } connect _out_1_a_bits_WIRE.echo, _out_1_a_bits_WIRE_4 wire _out_1_a_bits_WIRE_5 : { } connect _out_1_a_bits_WIRE.user, _out_1_a_bits_WIRE_5 node _out_1_a_bits_T_9 = mux(muxState_1[0], portsAOI_filtered[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_10 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_11 = or(_out_1_a_bits_T_9, _out_1_a_bits_T_10) wire _out_1_a_bits_WIRE_6 : UInt<32> connect _out_1_a_bits_WIRE_6, _out_1_a_bits_T_11 connect _out_1_a_bits_WIRE.address, _out_1_a_bits_WIRE_6 node _out_1_a_bits_T_12 = mux(muxState_1[0], portsAOI_filtered[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_13 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_14 = or(_out_1_a_bits_T_12, _out_1_a_bits_T_13) wire _out_1_a_bits_WIRE_7 : UInt<6> connect _out_1_a_bits_WIRE_7, _out_1_a_bits_T_14 connect _out_1_a_bits_WIRE.source, _out_1_a_bits_WIRE_7 node _out_1_a_bits_T_15 = mux(muxState_1[0], portsAOI_filtered[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_16 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_17 = or(_out_1_a_bits_T_15, _out_1_a_bits_T_16) wire _out_1_a_bits_WIRE_8 : UInt<4> connect _out_1_a_bits_WIRE_8, _out_1_a_bits_T_17 connect _out_1_a_bits_WIRE.size, _out_1_a_bits_WIRE_8 node _out_1_a_bits_T_18 = mux(muxState_1[0], portsAOI_filtered[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_19 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_20 = or(_out_1_a_bits_T_18, _out_1_a_bits_T_19) wire _out_1_a_bits_WIRE_9 : UInt<3> connect _out_1_a_bits_WIRE_9, _out_1_a_bits_T_20 connect _out_1_a_bits_WIRE.param, _out_1_a_bits_WIRE_9 node _out_1_a_bits_T_21 = mux(muxState_1[0], portsAOI_filtered[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_22 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_23 = or(_out_1_a_bits_T_21, _out_1_a_bits_T_22) wire _out_1_a_bits_WIRE_10 : UInt<3> connect _out_1_a_bits_WIRE_10, _out_1_a_bits_T_23 connect _out_1_a_bits_WIRE.opcode, _out_1_a_bits_WIRE_10 connect out[1].a.bits.corrupt, _out_1_a_bits_WIRE.corrupt connect out[1].a.bits.data, _out_1_a_bits_WIRE.data connect out[1].a.bits.mask, _out_1_a_bits_WIRE.mask connect out[1].a.bits.address, _out_1_a_bits_WIRE.address connect out[1].a.bits.source, _out_1_a_bits_WIRE.source connect out[1].a.bits.size, _out_1_a_bits_WIRE.size connect out[1].a.bits.param, _out_1_a_bits_WIRE.param connect out[1].a.bits.opcode, _out_1_a_bits_WIRE.opcode wire _WIRE_100 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_100.bits.corrupt, UInt<1>(0h0) connect _WIRE_100.bits.data, UInt<32>(0h0) connect _WIRE_100.bits.address, UInt<32>(0h0) connect _WIRE_100.bits.source, UInt<6>(0h0) connect _WIRE_100.bits.size, UInt<4>(0h0) connect _WIRE_100.bits.param, UInt<3>(0h0) connect _WIRE_100.bits.opcode, UInt<3>(0h0) connect _WIRE_100.valid, UInt<1>(0h0) connect _WIRE_100.ready, UInt<1>(0h0) wire _WIRE_101 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_101.bits, _WIRE_100.bits connect _WIRE_101.valid, _WIRE_100.valid connect _WIRE_101.ready, _WIRE_100.ready invalidate _WIRE_101.bits.corrupt invalidate _WIRE_101.bits.data invalidate _WIRE_101.bits.address invalidate _WIRE_101.bits.source invalidate _WIRE_101.bits.size invalidate _WIRE_101.bits.param invalidate _WIRE_101.bits.opcode wire _WIRE_102 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_102.bits.sink, UInt<3>(0h0) connect _WIRE_102.valid, UInt<1>(0h0) connect _WIRE_102.ready, UInt<1>(0h0) wire _WIRE_103 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_103.bits, _WIRE_102.bits connect _WIRE_103.valid, _WIRE_102.valid connect _WIRE_103.ready, _WIRE_102.ready invalidate _WIRE_103.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsCOI_filtered_1[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered_1[1].ready, UInt<1>(0h0) wire _WIRE_104 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_104.bits.corrupt, UInt<1>(0h0) connect _WIRE_104.bits.data, UInt<32>(0h0) connect _WIRE_104.bits.mask, UInt<4>(0h0) connect _WIRE_104.bits.address, UInt<32>(0h0) connect _WIRE_104.bits.source, UInt<6>(0h0) connect _WIRE_104.bits.size, UInt<4>(0h0) connect _WIRE_104.bits.param, UInt<2>(0h0) connect _WIRE_104.bits.opcode, UInt<3>(0h0) connect _WIRE_104.valid, UInt<1>(0h0) connect _WIRE_104.ready, UInt<1>(0h0) wire _WIRE_105 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_105.bits, _WIRE_104.bits connect _WIRE_105.valid, _WIRE_104.valid connect _WIRE_105.ready, _WIRE_104.ready invalidate _WIRE_105.bits.corrupt invalidate _WIRE_105.bits.data invalidate _WIRE_105.bits.mask invalidate _WIRE_105.bits.address invalidate _WIRE_105.bits.source invalidate _WIRE_105.bits.size invalidate _WIRE_105.bits.param invalidate _WIRE_105.bits.opcode regreset beatsLeft_2 : UInt, clock, reset, UInt<1>(0h0) node idle_2 = eq(beatsLeft_2, UInt<1>(0h0)) node latch_2 = and(idle_2, in[0].d.ready) node _readys_T_20 = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid_2 = bits(_readys_T_20, 1, 0) node _readys_T_21 = eq(readys_valid_2, _readys_T_20) node _readys_T_22 = asUInt(reset) node _readys_T_23 = eq(_readys_T_22, UInt<1>(0h0)) when _readys_T_23 : node _readys_T_24 = eq(_readys_T_21, UInt<1>(0h0)) when _readys_T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_2 assert(clock, _readys_T_21, UInt<1>(0h1), "") : readys_assert_2 regreset readys_mask_2 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_4 = not(readys_mask_2) node _readys_filter_T_5 = and(readys_valid_2, _readys_filter_T_4) node readys_filter_2 = cat(_readys_filter_T_5, readys_valid_2) node _readys_unready_T_10 = shr(readys_filter_2, 1) node _readys_unready_T_11 = or(readys_filter_2, _readys_unready_T_10) node _readys_unready_T_12 = bits(_readys_unready_T_11, 3, 0) node _readys_unready_T_13 = shr(_readys_unready_T_12, 1) node _readys_unready_T_14 = shl(readys_mask_2, 2) node readys_unready_2 = or(_readys_unready_T_13, _readys_unready_T_14) node _readys_readys_T_6 = shr(readys_unready_2, 2) node _readys_readys_T_7 = bits(readys_unready_2, 1, 0) node _readys_readys_T_8 = and(_readys_readys_T_6, _readys_readys_T_7) node readys_readys_2 = not(_readys_readys_T_8) node _readys_T_25 = orr(readys_valid_2) node _readys_T_26 = and(latch_2, _readys_T_25) when _readys_T_26 : node _readys_mask_T_10 = and(readys_readys_2, readys_valid_2) node _readys_mask_T_11 = shl(_readys_mask_T_10, 1) node _readys_mask_T_12 = bits(_readys_mask_T_11, 1, 0) node _readys_mask_T_13 = or(_readys_mask_T_10, _readys_mask_T_12) node _readys_mask_T_14 = bits(_readys_mask_T_13, 1, 0) connect readys_mask_2, _readys_mask_T_14 node _readys_T_27 = bits(readys_readys_2, 1, 0) node _readys_T_28 = bits(_readys_T_27, 0, 0) node _readys_T_29 = bits(_readys_T_27, 1, 1) wire readys_2 : UInt<1>[2] connect readys_2[0], _readys_T_28 connect readys_2[1], _readys_T_29 node _winner_T_4 = and(readys_2[0], portsDIO_filtered[0].valid) node _winner_T_5 = and(readys_2[1], portsDIO_filtered_1[0].valid) wire winner_2 : UInt<1>[2] connect winner_2[0], _winner_T_4 connect winner_2[1], _winner_T_5 node prefixOR_1_2 = or(UInt<1>(0h0), winner_2[0]) node _prefixOR_T_2 = or(prefixOR_1_2, winner_2[1]) node _T_34 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_35 = eq(winner_2[0], UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = eq(prefixOR_1_2, UInt<1>(0h0)) node _T_38 = eq(winner_2[1], UInt<1>(0h0)) node _T_39 = or(_T_37, _T_38) node _T_40 = and(_T_36, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_4 assert(clock, _T_40, UInt<1>(0h1), "") : assert_4 node _T_44 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_45 = eq(_T_44, UInt<1>(0h0)) node _T_46 = or(winner_2[0], winner_2[1]) node _T_47 = or(_T_45, _T_46) node _T_48 = asUInt(reset) node _T_49 = eq(_T_48, UInt<1>(0h0)) when _T_49 : node _T_50 = eq(_T_47, UInt<1>(0h0)) when _T_50 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_5 assert(clock, _T_47, UInt<1>(0h1), "") : assert_5 node maskedBeats_0_2 = mux(winner_2[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_2 = mux(winner_2[1], beatsDO_1, UInt<1>(0h0)) node initBeats_2 = or(maskedBeats_0_2, maskedBeats_1_2) node _beatsLeft_T_8 = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_9 = sub(beatsLeft_2, _beatsLeft_T_8) node _beatsLeft_T_10 = tail(_beatsLeft_T_9, 1) node _beatsLeft_T_11 = mux(latch_2, initBeats_2, _beatsLeft_T_10) connect beatsLeft_2, _beatsLeft_T_11 wire _state_WIRE_2 : UInt<1>[2] connect _state_WIRE_2[0], UInt<1>(0h0) connect _state_WIRE_2[1], UInt<1>(0h0) regreset state_2 : UInt<1>[2], clock, reset, _state_WIRE_2 node muxState_2 = mux(idle_2, winner_2, state_2) connect state_2, muxState_2 node allowed_2 = mux(idle_2, readys_2, state_2) node _filtered_0_ready_T_2 = and(in[0].d.ready, allowed_2[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T_2 node _filtered_0_ready_T_3 = and(in[0].d.ready, allowed_2[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_3 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state_2[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state_2[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle_2, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState_2[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState_2[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<32> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState_2[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState_2[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<3> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState_2[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<6> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState_2[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<4> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState_2[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState_2[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) wire _WIRE_106 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_106.bits.corrupt, UInt<1>(0h0) connect _WIRE_106.bits.data, UInt<32>(0h0) connect _WIRE_106.bits.mask, UInt<4>(0h0) connect _WIRE_106.bits.address, UInt<32>(0h0) connect _WIRE_106.bits.source, UInt<6>(0h0) connect _WIRE_106.bits.size, UInt<4>(0h0) connect _WIRE_106.bits.param, UInt<2>(0h0) connect _WIRE_106.bits.opcode, UInt<3>(0h0) connect _WIRE_106.valid, UInt<1>(0h0) connect _WIRE_106.ready, UInt<1>(0h0) wire _WIRE_107 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_107.bits, _WIRE_106.bits connect _WIRE_107.valid, _WIRE_106.valid connect _WIRE_107.ready, _WIRE_106.ready invalidate _WIRE_107.bits.corrupt invalidate _WIRE_107.bits.data invalidate _WIRE_107.bits.mask invalidate _WIRE_107.bits.address invalidate _WIRE_107.bits.source invalidate _WIRE_107.bits.size invalidate _WIRE_107.bits.param invalidate _WIRE_107.bits.opcode regreset beatsLeft_3 : UInt, clock, reset, UInt<1>(0h0) node idle_3 = eq(beatsLeft_3, UInt<1>(0h0)) node latch_3 = and(idle_3, in[1].d.ready) node _readys_T_30 = cat(portsDIO_filtered_1[1].valid, portsDIO_filtered[1].valid) node readys_valid_3 = bits(_readys_T_30, 1, 0) node _readys_T_31 = eq(readys_valid_3, _readys_T_30) node _readys_T_32 = asUInt(reset) node _readys_T_33 = eq(_readys_T_32, UInt<1>(0h0)) when _readys_T_33 : node _readys_T_34 = eq(_readys_T_31, UInt<1>(0h0)) when _readys_T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_3 assert(clock, _readys_T_31, UInt<1>(0h1), "") : readys_assert_3 regreset readys_mask_3 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_6 = not(readys_mask_3) node _readys_filter_T_7 = and(readys_valid_3, _readys_filter_T_6) node readys_filter_3 = cat(_readys_filter_T_7, readys_valid_3) node _readys_unready_T_15 = shr(readys_filter_3, 1) node _readys_unready_T_16 = or(readys_filter_3, _readys_unready_T_15) node _readys_unready_T_17 = bits(_readys_unready_T_16, 3, 0) node _readys_unready_T_18 = shr(_readys_unready_T_17, 1) node _readys_unready_T_19 = shl(readys_mask_3, 2) node readys_unready_3 = or(_readys_unready_T_18, _readys_unready_T_19) node _readys_readys_T_9 = shr(readys_unready_3, 2) node _readys_readys_T_10 = bits(readys_unready_3, 1, 0) node _readys_readys_T_11 = and(_readys_readys_T_9, _readys_readys_T_10) node readys_readys_3 = not(_readys_readys_T_11) node _readys_T_35 = orr(readys_valid_3) node _readys_T_36 = and(latch_3, _readys_T_35) when _readys_T_36 : node _readys_mask_T_15 = and(readys_readys_3, readys_valid_3) node _readys_mask_T_16 = shl(_readys_mask_T_15, 1) node _readys_mask_T_17 = bits(_readys_mask_T_16, 1, 0) node _readys_mask_T_18 = or(_readys_mask_T_15, _readys_mask_T_17) node _readys_mask_T_19 = bits(_readys_mask_T_18, 1, 0) connect readys_mask_3, _readys_mask_T_19 node _readys_T_37 = bits(readys_readys_3, 1, 0) node _readys_T_38 = bits(_readys_T_37, 0, 0) node _readys_T_39 = bits(_readys_T_37, 1, 1) wire readys_3 : UInt<1>[2] connect readys_3[0], _readys_T_38 connect readys_3[1], _readys_T_39 node _winner_T_6 = and(readys_3[0], portsDIO_filtered[1].valid) node _winner_T_7 = and(readys_3[1], portsDIO_filtered_1[1].valid) wire winner_3 : UInt<1>[2] connect winner_3[0], _winner_T_6 connect winner_3[1], _winner_T_7 node prefixOR_1_3 = or(UInt<1>(0h0), winner_3[0]) node _prefixOR_T_3 = or(prefixOR_1_3, winner_3[1]) node _T_51 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_52 = eq(winner_3[0], UInt<1>(0h0)) node _T_53 = or(_T_51, _T_52) node _T_54 = eq(prefixOR_1_3, UInt<1>(0h0)) node _T_55 = eq(winner_3[1], UInt<1>(0h0)) node _T_56 = or(_T_54, _T_55) node _T_57 = and(_T_53, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_6 assert(clock, _T_57, UInt<1>(0h1), "") : assert_6 node _T_61 = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid) node _T_62 = eq(_T_61, UInt<1>(0h0)) node _T_63 = or(winner_3[0], winner_3[1]) node _T_64 = or(_T_62, _T_63) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_7 assert(clock, _T_64, UInt<1>(0h1), "") : assert_7 node maskedBeats_0_3 = mux(winner_3[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_3 = mux(winner_3[1], beatsDO_1, UInt<1>(0h0)) node initBeats_3 = or(maskedBeats_0_3, maskedBeats_1_3) node _beatsLeft_T_12 = and(in[1].d.ready, in[1].d.valid) node _beatsLeft_T_13 = sub(beatsLeft_3, _beatsLeft_T_12) node _beatsLeft_T_14 = tail(_beatsLeft_T_13, 1) node _beatsLeft_T_15 = mux(latch_3, initBeats_3, _beatsLeft_T_14) connect beatsLeft_3, _beatsLeft_T_15 wire _state_WIRE_3 : UInt<1>[2] connect _state_WIRE_3[0], UInt<1>(0h0) connect _state_WIRE_3[1], UInt<1>(0h0) regreset state_3 : UInt<1>[2], clock, reset, _state_WIRE_3 node muxState_3 = mux(idle_3, winner_3, state_3) connect state_3, muxState_3 node allowed_3 = mux(idle_3, readys_3, state_3) node _filtered_1_ready_T_2 = and(in[1].d.ready, allowed_3[0]) connect portsDIO_filtered[1].ready, _filtered_1_ready_T_2 node _filtered_1_ready_T_3 = and(in[1].d.ready, allowed_3[1]) connect portsDIO_filtered_1[1].ready, _filtered_1_ready_T_3 node _in_1_d_valid_T = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid) node _in_1_d_valid_T_1 = mux(state_3[0], portsDIO_filtered[1].valid, UInt<1>(0h0)) node _in_1_d_valid_T_2 = mux(state_3[1], portsDIO_filtered_1[1].valid, UInt<1>(0h0)) node _in_1_d_valid_T_3 = or(_in_1_d_valid_T_1, _in_1_d_valid_T_2) wire _in_1_d_valid_WIRE : UInt<1> connect _in_1_d_valid_WIRE, _in_1_d_valid_T_3 node _in_1_d_valid_T_4 = mux(idle_3, _in_1_d_valid_T, _in_1_d_valid_WIRE) connect in[1].d.valid, _in_1_d_valid_T_4 wire _in_1_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} node _in_1_d_bits_T = mux(muxState_3[0], portsDIO_filtered[1].bits.corrupt, UInt<1>(0h0)) node _in_1_d_bits_T_1 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.corrupt, UInt<1>(0h0)) node _in_1_d_bits_T_2 = or(_in_1_d_bits_T, _in_1_d_bits_T_1) wire _in_1_d_bits_WIRE_1 : UInt<1> connect _in_1_d_bits_WIRE_1, _in_1_d_bits_T_2 connect _in_1_d_bits_WIRE.corrupt, _in_1_d_bits_WIRE_1 node _in_1_d_bits_T_3 = mux(muxState_3[0], portsDIO_filtered[1].bits.data, UInt<1>(0h0)) node _in_1_d_bits_T_4 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.data, UInt<1>(0h0)) node _in_1_d_bits_T_5 = or(_in_1_d_bits_T_3, _in_1_d_bits_T_4) wire _in_1_d_bits_WIRE_2 : UInt<32> connect _in_1_d_bits_WIRE_2, _in_1_d_bits_T_5 connect _in_1_d_bits_WIRE.data, _in_1_d_bits_WIRE_2 wire _in_1_d_bits_WIRE_3 : { } connect _in_1_d_bits_WIRE.echo, _in_1_d_bits_WIRE_3 wire _in_1_d_bits_WIRE_4 : { } connect _in_1_d_bits_WIRE.user, _in_1_d_bits_WIRE_4 node _in_1_d_bits_T_6 = mux(muxState_3[0], portsDIO_filtered[1].bits.denied, UInt<1>(0h0)) node _in_1_d_bits_T_7 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.denied, UInt<1>(0h0)) node _in_1_d_bits_T_8 = or(_in_1_d_bits_T_6, _in_1_d_bits_T_7) wire _in_1_d_bits_WIRE_5 : UInt<1> connect _in_1_d_bits_WIRE_5, _in_1_d_bits_T_8 connect _in_1_d_bits_WIRE.denied, _in_1_d_bits_WIRE_5 node _in_1_d_bits_T_9 = mux(muxState_3[0], portsDIO_filtered[1].bits.sink, UInt<1>(0h0)) node _in_1_d_bits_T_10 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.sink, UInt<1>(0h0)) node _in_1_d_bits_T_11 = or(_in_1_d_bits_T_9, _in_1_d_bits_T_10) wire _in_1_d_bits_WIRE_6 : UInt<3> connect _in_1_d_bits_WIRE_6, _in_1_d_bits_T_11 connect _in_1_d_bits_WIRE.sink, _in_1_d_bits_WIRE_6 node _in_1_d_bits_T_12 = mux(muxState_3[0], portsDIO_filtered[1].bits.source, UInt<1>(0h0)) node _in_1_d_bits_T_13 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.source, UInt<1>(0h0)) node _in_1_d_bits_T_14 = or(_in_1_d_bits_T_12, _in_1_d_bits_T_13) wire _in_1_d_bits_WIRE_7 : UInt<6> connect _in_1_d_bits_WIRE_7, _in_1_d_bits_T_14 connect _in_1_d_bits_WIRE.source, _in_1_d_bits_WIRE_7 node _in_1_d_bits_T_15 = mux(muxState_3[0], portsDIO_filtered[1].bits.size, UInt<1>(0h0)) node _in_1_d_bits_T_16 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.size, UInt<1>(0h0)) node _in_1_d_bits_T_17 = or(_in_1_d_bits_T_15, _in_1_d_bits_T_16) wire _in_1_d_bits_WIRE_8 : UInt<4> connect _in_1_d_bits_WIRE_8, _in_1_d_bits_T_17 connect _in_1_d_bits_WIRE.size, _in_1_d_bits_WIRE_8 node _in_1_d_bits_T_18 = mux(muxState_3[0], portsDIO_filtered[1].bits.param, UInt<1>(0h0)) node _in_1_d_bits_T_19 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.param, UInt<1>(0h0)) node _in_1_d_bits_T_20 = or(_in_1_d_bits_T_18, _in_1_d_bits_T_19) wire _in_1_d_bits_WIRE_9 : UInt<2> connect _in_1_d_bits_WIRE_9, _in_1_d_bits_T_20 connect _in_1_d_bits_WIRE.param, _in_1_d_bits_WIRE_9 node _in_1_d_bits_T_21 = mux(muxState_3[0], portsDIO_filtered[1].bits.opcode, UInt<1>(0h0)) node _in_1_d_bits_T_22 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.opcode, UInt<1>(0h0)) node _in_1_d_bits_T_23 = or(_in_1_d_bits_T_21, _in_1_d_bits_T_22) wire _in_1_d_bits_WIRE_10 : UInt<3> connect _in_1_d_bits_WIRE_10, _in_1_d_bits_T_23 connect _in_1_d_bits_WIRE.opcode, _in_1_d_bits_WIRE_10 connect in[1].d.bits.corrupt, _in_1_d_bits_WIRE.corrupt connect in[1].d.bits.data, _in_1_d_bits_WIRE.data connect in[1].d.bits.denied, _in_1_d_bits_WIRE.denied connect in[1].d.bits.sink, _in_1_d_bits_WIRE.sink connect in[1].d.bits.source, _in_1_d_bits_WIRE.source connect in[1].d.bits.size, _in_1_d_bits_WIRE.size connect in[1].d.bits.param, _in_1_d_bits_WIRE.param connect in[1].d.bits.opcode, _in_1_d_bits_WIRE.opcode connect portsBIO_filtered[1].ready, UInt<1>(0h0) connect portsBIO_filtered_1[1].ready, UInt<1>(0h0)	module TLXbar_sbus_i2_o2_a32d32s6k3z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [2:0] out_1_d_bits_sink; // @[Xbar.scala:216:19] wire [3:0] out_1_d_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [5:0] in_1_a_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param_0 = auto_anon_out_0_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink_0 = auto_anon_out_0_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire _readys_T_12 = reset; // @[Arbiter.scala:22:12] wire _readys_T_22 = reset; // @[Arbiter.scala:22:12] wire _readys_T_32 = reset; // @[Arbiter.scala:22:12] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire requestBOI_uncommonBits_1 = 1'h0; // @[Parameters.scala:52:56] wire _requestBOI_T_6 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_8 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:56:48] wire _requestBOI_WIRE_4_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_4_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_5_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_5_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_10 = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_6_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_6_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_6_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_7_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_7_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_7_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire requestBOI_uncommonBits_3 = 1'h0; // @[Parameters.scala:52:56] wire _requestBOI_T_16 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_18 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_1_1 = 1'h0; // @[Parameters.scala:56:48] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_4_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_4_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_5_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_5_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_6_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_6_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_7_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_7_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_4_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_4_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T_2 = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_T_3 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_4 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_5 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T_3 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_4 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_5 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_4_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_4_valid = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_1_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_2 = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T_3 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_4 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_5 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3_1 = 1'h0; // @[Arbiter.scala:88:34] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_14 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_19 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_11 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_13 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_14 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_19 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_14 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_19 = 1'h1; // @[Parameters.scala:57:20] wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_0_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_1_1 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_6_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_7_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestEIO_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _requestEIO_WIRE_1_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _requestEIO_WIRE_2_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _requestEIO_WIRE_3_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _requestEIO_uncommonBits_T = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestEIO_uncommonBits = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _requestEIO_WIRE_4_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _requestEIO_WIRE_5_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _requestEIO_WIRE_6_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _requestEIO_WIRE_7_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _requestEIO_uncommonBits_T_1 = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestEIO_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsEI_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _beatsEI_WIRE_1_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _beatsEI_WIRE_2_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _beatsEI_WIRE_3_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsEOI_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _portsEOI_WIRE_1_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] portsEOI_filtered_0_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_1_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsEOI_WIRE_3_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _portsEOI_WIRE_4_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] portsEOI_filtered_1_0_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_1_1_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_10 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_15 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_6_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_6_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_7_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_7_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _portsBIO_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _portsBIO_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_1_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsCOI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsCOI_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_1_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [5:0] _addressC_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _addressC_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _addressC_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _addressC_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _requestBOI_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _requestBOI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _requestBOI_uncommonBits_T = 6'h0; // @[Parameters.scala:52:29] wire [5:0] _requestBOI_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _requestBOI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _requestBOI_uncommonBits_T_1 = 6'h0; // @[Parameters.scala:52:29] wire [5:0] _requestBOI_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _requestBOI_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _requestBOI_uncommonBits_T_2 = 6'h0; // @[Parameters.scala:52:29] wire [5:0] _requestBOI_WIRE_6_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _requestBOI_WIRE_7_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _requestBOI_uncommonBits_T_3 = 6'h0; // @[Parameters.scala:52:29] wire [5:0] _beatsBO_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _beatsBO_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _beatsBO_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _beatsBO_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _beatsCI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _beatsCI_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _beatsCI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _portsBIO_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _portsBIO_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] portsBIO_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsBIO_filtered_1_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] _portsBIO_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _portsBIO_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] portsBIO_filtered_1_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsBIO_filtered_1_1_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] _portsCOI_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _portsCOI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] portsCOI_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsCOI_filtered_1_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] _portsCOI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _portsCOI_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] portsCOI_filtered_1_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsCOI_filtered_1_1_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_2_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_3_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_4_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_5_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_6_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_6_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_7_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_7_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_2_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_3_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] beatsBO_decode_1 = 4'h0; // @[Edges.scala:220:59] wire [3:0] beatsBO_1 = 4'h0; // @[Edges.scala:221:14] wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _portsBIO_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_0_bits_mask = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_mask = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsBIO_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_3_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _portsBIO_WIRE_4_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_0_bits_mask = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_1_bits_mask = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_1_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_4_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_5_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_6_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_7_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_4_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [9:0] beatsBO_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] beatsBO_0 = 10'h0; // @[Edges.scala:221:14] wire [9:0] beatsCI_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] beatsCI_0 = 10'h0; // @[Edges.scala:221:14] wire [9:0] beatsCI_decode_1 = 10'h0; // @[Edges.scala:220:59] wire [9:0] beatsCI_1 = 10'h0; // @[Edges.scala:221:14] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [20:0] _beatsBO_decode_T_3 = 21'h3F; // @[package.scala:243:71] wire [4:0] requestBOI_uncommonBits = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _requestBOI_T_5 = 5'h0; // @[Parameters.scala:54:10] wire [4:0] requestBOI_uncommonBits_2 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _requestBOI_T_15 = 5'h0; // @[Parameters.scala:54:10] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_11 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_12 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_13 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_16 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_18 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = auto_anon_out_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [4:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [31:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire [3:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69] assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [5:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [5:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [31:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [5:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [5:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [31:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [5:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [31:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_1_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_1_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [5:0] _in_1_a_bits_source_T; // @[Xbar.scala:166:55] wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_1_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_1_1_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_28 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_1_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_1_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_1_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_1_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_1_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_1_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_1_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_1_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [5:0] _in_1_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire _in_1_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [31:0] _in_1_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire _in_1_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire [5:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign _in_1_a_bits_source_T = {5'h10, anonIn_1_a_bits_source}; // @[Xbar.scala:166:55] assign in_1_a_bits_source = _in_1_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign _anonIn_d_bits_source_T_1 = in_1_d_bits_source[0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [5:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [5:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] _requestDOI_uncommonBits_T_1 = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [5:0] portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _out_1_a_valid_T_4; // @[Arbiter.scala:96:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19] wire [3:0] _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] wire [31:0] _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] wire _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_1_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_1_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_1_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [5:0] _requestDOI_uncommonBits_T_2 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] _requestDOI_uncommonBits_T_3 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [5:0] portsDIO_filtered_1_1_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_1_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_1_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsDIO_filtered_1_1_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_1_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire [3:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address[28:0]; // @[Xbar.scala:216:19, :222:41] assign out_0_d_bits_sink = {2'h0, _out_0_d_bits_sink_T}; // @[Xbar.scala:216:19, :251:{28,53}] assign x1_anonOut_a_bits_size = out_1_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41] assign out_1_d_bits_size = {1'h0, x1_anonOut_d_bits_size}; // @[Xbar.scala:216:19, :250:29] assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_5 = {in_0_a_bits_address[31:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_10 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_11 = {1'h0, _requestAIO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_12 = _requestAIO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_13 = _requestAIO_T_12; // @[Parameters.scala:137:46] wire _requestAIO_T_14 = _requestAIO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_15 = _requestAIO_T_4 \| _requestAIO_T_9; // @[Xbar.scala:291:92] wire _requestAIO_T_16 = _requestAIO_T_15 \| _requestAIO_T_14; // @[Xbar.scala:291:92] wire requestAIO_0_0 = _requestAIO_T_16; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_17 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_18 = {1'h0, _requestAIO_T_17}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_19 = _requestAIO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_20 = _requestAIO_T_19; // @[Parameters.scala:137:46] wire _requestAIO_T_21 = _requestAIO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_22 = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_23 = {1'h0, _requestAIO_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_24 = _requestAIO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_25 = _requestAIO_T_24; // @[Parameters.scala:137:46] wire _requestAIO_T_26 = _requestAIO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_27 = _requestAIO_T_21 \| _requestAIO_T_26; // @[Xbar.scala:291:92] wire requestAIO_0_1 = _requestAIO_T_27; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_29 = {1'h0, _requestAIO_T_28}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_30 = _requestAIO_T_29 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_31 = _requestAIO_T_30; // @[Parameters.scala:137:46] wire _requestAIO_T_32 = _requestAIO_T_31 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_33 = {in_1_a_bits_address[31:17], in_1_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_34 = {1'h0, _requestAIO_T_33}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_35 = _requestAIO_T_34 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_36 = _requestAIO_T_35; // @[Parameters.scala:137:46] wire _requestAIO_T_37 = _requestAIO_T_36 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_38 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_39 = {1'h0, _requestAIO_T_38}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_40 = _requestAIO_T_39 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_41 = _requestAIO_T_40; // @[Parameters.scala:137:46] wire _requestAIO_T_42 = _requestAIO_T_41 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_43 = _requestAIO_T_32 \| _requestAIO_T_37; // @[Xbar.scala:291:92] wire _requestAIO_T_44 = _requestAIO_T_43 \| _requestAIO_T_42; // @[Xbar.scala:291:92] wire requestAIO_1_0 = _requestAIO_T_44; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T_2 = requestAIO_1_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_45 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_46 = {1'h0, _requestAIO_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_47 = _requestAIO_T_46 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_48 = _requestAIO_T_47; // @[Parameters.scala:137:46] wire _requestAIO_T_49 = _requestAIO_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_50 = in_1_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_51 = {1'h0, _requestAIO_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_52 = _requestAIO_T_51 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_53 = _requestAIO_T_52; // @[Parameters.scala:137:46] wire _requestAIO_T_54 = _requestAIO_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_55 = _requestAIO_T_49 \| _requestAIO_T_54; // @[Xbar.scala:291:92] wire requestAIO_1_1 = _requestAIO_T_55; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T_2 = requestAIO_1_1; // @[Xbar.scala:307:107, :355:54] wire [4:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T = out_0_d_bits_source[5]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1[0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _requestDOI_T_5 = out_0_d_bits_source[5:1]; // @[Xbar.scala:216:19] wire _requestDOI_T_6 = _requestDOI_T_5 == 5'h10; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_8 = _requestDOI_T_6; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_1 = _requestDOI_T_8; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire [4:0] requestDOI_uncommonBits_2 = _requestDOI_uncommonBits_T_2[4:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_10 = out_1_d_bits_source[5]; // @[Xbar.scala:216:19] wire _requestDOI_T_11 = ~_requestDOI_T_10; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_13 = _requestDOI_T_11; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_0 = _requestDOI_T_13; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T_2 = requestDOI_1_0; // @[Xbar.scala:355:54] wire requestDOI_uncommonBits_3 = _requestDOI_uncommonBits_T_3[0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _requestDOI_T_15 = out_1_d_bits_source[5:1]; // @[Xbar.scala:216:19] wire _requestDOI_T_16 = _requestDOI_T_15 == 5'h10; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_18 = _requestDOI_T_16; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_1 = _requestDOI_T_18; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_1_valid_T_2 = requestDOI_1_1; // @[Xbar.scala:355:54] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] beatsAI_decode = _beatsAI_decode_T_2[11:2]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [9:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:2]; // @[package.scala:243:46] wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [9:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] beatsDO_decode = _beatsDO_decode_T_2[11:2]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [9:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [20:0] _beatsDO_decode_T_3 = 21'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [3:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:2]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [3:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 4'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_1_ready_T; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T \| _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_1; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:355:40] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_3 = in_1_a_valid & _portsAOI_filtered_0_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_3 = in_1_a_valid & _portsAOI_filtered_1_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_1_valid = _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_1_a_ready_T = requestAIO_1_0 & portsAOI_filtered_1_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_1_a_ready_T_1 = requestAIO_1_1 & portsAOI_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_1_a_ready_T_2 = _portsAOI_in_1_a_ready_T \| _portsAOI_in_1_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_1_a_ready_WIRE = _portsAOI_in_1_a_ready_T_2; // @[Mux.scala:30:73] assign in_1_a_ready = _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_2; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_2; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T \| _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_3; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_3; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:355:40] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] assign _portsDIO_filtered_0_valid_T_3 = out_1_d_valid & _portsDIO_filtered_0_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_3 = out_1_d_valid & _portsDIO_filtered_1_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_1_valid = _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_1_d_ready_T = requestDOI_1_0 & portsDIO_filtered_1_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_1 = requestDOI_1_1 & portsDIO_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_2 = _portsDIO_out_1_d_ready_T \| _portsDIO_out_1_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_1_d_ready_WIRE = _portsDIO_out_1_d_ready_T_2; // @[Mux.scala:30:73] assign out_1_d_ready = _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73] reg [9:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 10'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid \| portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire [9:0] maskedBeats_0 = winner_0 ? beatsAI_0 : 10'h0; // @[Edges.scala:221:14] wire [9:0] maskedBeats_1 = winner_1 ? beatsAI_1 : 10'h0; // @[Edges.scala:221:14] wire [9:0] initBeats = maskedBeats_0 \| maskedBeats_1; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T = out_0_a_ready & out_0_a_valid; // @[Decoupled.scala:51:35] wire [10:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {10'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_2 = _beatsLeft_T_1[9:0]; // @[Arbiter.scala:85:52] wire [9:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_0_ready_T = out_0_a_ready & allowed_0; // @[Xbar.scala:216:19] assign portsAOI_filtered_0_ready = _filtered_0_ready_T; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_1 = out_0_a_ready & allowed_1; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_0_ready = _filtered_0_ready_T_1; // @[Xbar.scala:352:24] wire _out_0_a_valid_T_1 = state_0 & portsAOI_filtered_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_2 = state_1 & portsAOI_filtered_1_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_3 = _out_0_a_valid_T_1 \| _out_0_a_valid_T_2; // @[Mux.scala:30:73] wire _out_0_a_valid_WIRE = _out_0_a_valid_T_3; // @[Mux.scala:30:73] assign _out_0_a_valid_T_4 = idle ? _out_0_a_valid_T : _out_0_a_valid_WIRE; // @[Mux.scala:30:73] assign out_0_a_valid = _out_0_a_valid_T_4; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73] assign out_0_a_bits_opcode = _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73] assign out_0_a_bits_param = _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73] assign out_0_a_bits_size = _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73] assign out_0_a_bits_source = _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73] assign out_0_a_bits_address = _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73] assign out_0_a_bits_mask = _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73] assign out_0_a_bits_data = _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73] assign out_0_a_bits_corrupt = _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T = muxState_0 & portsAOI_filtered_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = muxState_1 & portsAOI_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = _out_0_a_bits_T \| _out_0_a_bits_T_1; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_1 = _out_0_a_bits_T_2; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_corrupt = _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_3 = muxState_0 ? portsAOI_filtered_0_bits_data : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_4 = muxState_1 ? portsAOI_filtered_1_0_bits_data : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_5 = _out_0_a_bits_T_3 \| _out_0_a_bits_T_4; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_2 = _out_0_a_bits_T_5; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_data = _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_6 = muxState_0 ? portsAOI_filtered_0_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_7 = muxState_1 ? portsAOI_filtered_1_0_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_8 = _out_0_a_bits_T_6 \| _out_0_a_bits_T_7; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_3 = _out_0_a_bits_T_8; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_mask = _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_9 = muxState_0 ? portsAOI_filtered_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_10 = muxState_1 ? portsAOI_filtered_1_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_11 = _out_0_a_bits_T_9 \| _out_0_a_bits_T_10; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_6 = _out_0_a_bits_T_11; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_address = _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_T_12 = muxState_0 ? portsAOI_filtered_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_T_13 = muxState_1 ? portsAOI_filtered_1_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_T_14 = _out_0_a_bits_T_12 \| _out_0_a_bits_T_13; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_7 = _out_0_a_bits_T_14; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_source = _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_15 = muxState_0 ? portsAOI_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_16 = muxState_1 ? portsAOI_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_17 = _out_0_a_bits_T_15 \| _out_0_a_bits_T_16; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_8 = _out_0_a_bits_T_17; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_size = _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_18 = muxState_0 ? portsAOI_filtered_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_19 = muxState_1 ? portsAOI_filtered_1_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_20 = _out_0_a_bits_T_18 \| _out_0_a_bits_T_19; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_9 = _out_0_a_bits_T_20; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_param = _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_21 = muxState_0 ? portsAOI_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_22 = muxState_1 ? portsAOI_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_23 = _out_0_a_bits_T_21 \| _out_0_a_bits_T_22; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_10 = _out_0_a_bits_T_23; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_opcode = _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73] reg [9:0] beatsLeft_1; // @[Arbiter.scala:60:30] wire idle_1 = beatsLeft_1 == 10'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_1 = idle_1 & out_1_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T_10 = {portsAOI_filtered_1_1_valid, portsAOI_filtered_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_1 = _readys_T_10; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_11 = readys_valid_1 == _readys_T_10; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_13 = ~_readys_T_12; // @[Arbiter.scala:22:12] wire _readys_T_14 = ~_readys_T_11; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_1; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_2 = ~readys_mask_1; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_3 = readys_valid_1 & _readys_filter_T_2; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_1 = {_readys_filter_T_3, readys_valid_1}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_5 = readys_filter_1[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_6 = {readys_filter_1[3], readys_filter_1[2:0] \| _readys_unready_T_5}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_7 = _readys_unready_T_6; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_8 = _readys_unready_T_7[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_9 = {readys_mask_1, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_1 = {1'h0, _readys_unready_T_8} \| _readys_unready_T_9; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_3 = readys_unready_1[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_4 = readys_unready_1[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_5 = _readys_readys_T_3 & _readys_readys_T_4; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_1 = ~_readys_readys_T_5; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_17 = readys_readys_1; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_15 = \|readys_valid_1; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_16 = latch_1 & _readys_T_15; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_5 = readys_readys_1 & readys_valid_1; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_6 = {_readys_mask_T_5, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_7 = _readys_mask_T_6[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_8 = _readys_mask_T_5 \| _readys_mask_T_7; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_9 = _readys_mask_T_8; // @[package.scala:253:43, :254:17] wire _readys_T_18 = _readys_T_17[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_0 = _readys_T_18; // @[Arbiter.scala:68:{27,76}] wire _readys_T_19 = _readys_T_17[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_1 = _readys_T_19; // @[Arbiter.scala:68:{27,76}] wire _winner_T_2 = readys_1_0 & portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] wire winner_1_0 = _winner_T_2; // @[Arbiter.scala:71:{27,69}] wire _winner_T_3 = readys_1_1 & portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_1_1 = _winner_T_3; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_1 = prefixOR_1_1 \| winner_1_1; // @[Arbiter.scala:71:27, :76:48] wire _out_1_a_valid_T = portsAOI_filtered_1_valid \| portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire [9:0] maskedBeats_0_1 = winner_1_0 ? beatsAI_0 : 10'h0; // @[Edges.scala:221:14] wire [9:0] maskedBeats_1_1 = winner_1_1 ? beatsAI_1 : 10'h0; // @[Edges.scala:221:14] wire [9:0] initBeats_1 = maskedBeats_0_1 \| maskedBeats_1_1; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_4 = out_1_a_ready & out_1_a_valid; // @[Decoupled.scala:51:35] wire [10:0] _beatsLeft_T_5 = {1'h0, beatsLeft_1} - {10'h0, _beatsLeft_T_4}; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_6 = _beatsLeft_T_5[9:0]; // @[Arbiter.scala:85:52] wire [9:0] _beatsLeft_T_7 = latch_1 ? initBeats_1 : _beatsLeft_T_6; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_1_0; // @[Arbiter.scala:88:26] reg state_1_1; // @[Arbiter.scala:88:26] wire muxState_1_0 = idle_1 ? winner_1_0 : state_1_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_1_0 = idle_1 ? readys_1_0 : state_1_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1_1 = idle_1 ? readys_1_1 : state_1_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T = out_1_a_ready & allowed_1_0; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_ready = _filtered_1_ready_T; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_1 = out_1_a_ready & allowed_1_1; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_1_ready = _filtered_1_ready_T_1; // @[Xbar.scala:352:24] wire _out_1_a_valid_T_1 = state_1_0 & portsAOI_filtered_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_2 = state_1_1 & portsAOI_filtered_1_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_3 = _out_1_a_valid_T_1 \| _out_1_a_valid_T_2; // @[Mux.scala:30:73] wire _out_1_a_valid_WIRE = _out_1_a_valid_T_3; // @[Mux.scala:30:73] assign _out_1_a_valid_T_4 = idle_1 ? _out_1_a_valid_T : _out_1_a_valid_WIRE; // @[Mux.scala:30:73] assign out_1_a_valid = _out_1_a_valid_T_4; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73] assign out_1_a_bits_opcode = _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73] assign out_1_a_bits_param = _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73] assign out_1_a_bits_size = _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73] assign out_1_a_bits_source = _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73] assign out_1_a_bits_address = _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73] assign out_1_a_bits_mask = _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73] assign out_1_a_bits_data = _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73] assign out_1_a_bits_corrupt = _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T = muxState_1_0 & portsAOI_filtered_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_1 = muxState_1_1 & portsAOI_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_2 = _out_1_a_bits_T \| _out_1_a_bits_T_1; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_1 = _out_1_a_bits_T_2; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_corrupt = _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_3 = muxState_1_0 ? portsAOI_filtered_1_bits_data : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_4 = muxState_1_1 ? portsAOI_filtered_1_1_bits_data : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_5 = _out_1_a_bits_T_3 \| _out_1_a_bits_T_4; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_2 = _out_1_a_bits_T_5; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_data = _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_6 = muxState_1_0 ? portsAOI_filtered_1_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_7 = muxState_1_1 ? portsAOI_filtered_1_1_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_8 = _out_1_a_bits_T_6 \| _out_1_a_bits_T_7; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_3 = _out_1_a_bits_T_8; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_mask = _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_9 = muxState_1_0 ? portsAOI_filtered_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_10 = muxState_1_1 ? portsAOI_filtered_1_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_11 = _out_1_a_bits_T_9 \| _out_1_a_bits_T_10; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_6 = _out_1_a_bits_T_11; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_address = _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_T_12 = muxState_1_0 ? portsAOI_filtered_1_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_T_13 = muxState_1_1 ? portsAOI_filtered_1_1_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_T_14 = _out_1_a_bits_T_12 \| _out_1_a_bits_T_13; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_7 = _out_1_a_bits_T_14; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_source = _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_15 = muxState_1_0 ? portsAOI_filtered_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_16 = muxState_1_1 ? portsAOI_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_17 = _out_1_a_bits_T_15 \| _out_1_a_bits_T_16; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_8 = _out_1_a_bits_T_17; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_size = _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_18 = muxState_1_0 ? portsAOI_filtered_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_19 = muxState_1_1 ? portsAOI_filtered_1_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_20 = _out_1_a_bits_T_18 \| _out_1_a_bits_T_19; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_9 = _out_1_a_bits_T_20; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_param = _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_21 = muxState_1_0 ? portsAOI_filtered_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_22 = muxState_1_1 ? portsAOI_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_23 = _out_1_a_bits_T_21 \| _out_1_a_bits_T_22; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_10 = _out_1_a_bits_T_23; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_opcode = _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73] reg [9:0] beatsLeft_2; // @[Arbiter.scala:60:30] wire idle_2 = beatsLeft_2 == 10'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_2 = idle_2 & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_20 = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_2 = _readys_T_20; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_21 = readys_valid_2 == _readys_T_20; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_23 = ~_readys_T_22; // @[Arbiter.scala:22:12] wire _readys_T_24 = ~_readys_T_21; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_2; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_4 = ~readys_mask_2; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_5 = readys_valid_2 & _readys_filter_T_4; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_2 = {_readys_filter_T_5, readys_valid_2}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_10 = readys_filter_2[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_11 = {readys_filter_2[3], readys_filter_2[2:0] \| _readys_unready_T_10}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_12 = _readys_unready_T_11; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_13 = _readys_unready_T_12[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_14 = {readys_mask_2, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_2 = {1'h0, _readys_unready_T_13} \| _readys_unready_T_14; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_6 = readys_unready_2[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_7 = readys_unready_2[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_8 = _readys_readys_T_6 & _readys_readys_T_7; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_2 = ~_readys_readys_T_8; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_27 = readys_readys_2; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_25 = \|readys_valid_2; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_26 = latch_2 & _readys_T_25; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_10 = readys_readys_2 & readys_valid_2; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_11 = {_readys_mask_T_10, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_12 = _readys_mask_T_11[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_13 = _readys_mask_T_10 \| _readys_mask_T_12; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_14 = _readys_mask_T_13; // @[package.scala:253:43, :254:17] wire _readys_T_28 = _readys_T_27[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_0 = _readys_T_28; // @[Arbiter.scala:68:{27,76}] wire _readys_T_29 = _readys_T_27[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_1 = _readys_T_29; // @[Arbiter.scala:68:{27,76}] wire _winner_T_4 = readys_2_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_2_0 = _winner_T_4; // @[Arbiter.scala:71:{27,69}] wire _winner_T_5 = readys_2_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_2_1 = _winner_T_5; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_2 = winner_2_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_2 = prefixOR_1_2 \| winner_2_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid \| portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire [9:0] maskedBeats_0_2 = winner_2_0 ? beatsDO_0 : 10'h0; // @[Edges.scala:221:14] wire [3:0] maskedBeats_1_2 = winner_2_1 ? beatsDO_1 : 4'h0; // @[Edges.scala:221:14] wire [9:0] initBeats_2 = {maskedBeats_0_2[9:4], maskedBeats_0_2[3:0] \| maskedBeats_1_2}; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_8 = in_0_d_ready & in_0_d_valid; // @[Decoupled.scala:51:35] wire [10:0] _beatsLeft_T_9 = {1'h0, beatsLeft_2} - {10'h0, _beatsLeft_T_8}; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_10 = _beatsLeft_T_9[9:0]; // @[Arbiter.scala:85:52] wire [9:0] _beatsLeft_T_11 = latch_2 ? initBeats_2 : _beatsLeft_T_10; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_2_0; // @[Arbiter.scala:88:26] reg state_2_1; // @[Arbiter.scala:88:26] wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_2_0 = idle_2 ? readys_2_0 : state_2_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2_1 = idle_2 ? readys_2_1 : state_2_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_0_ready_T_2 = in_0_d_ready & allowed_2_0; // @[Xbar.scala:159:18] assign portsDIO_filtered_0_ready = _filtered_0_ready_T_2; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_3 = in_0_d_ready & allowed_2_1; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_0_ready = _filtered_0_ready_T_3; // @[Xbar.scala:352:24] wire _in_0_d_valid_T_1 = state_2_0 & portsDIO_filtered_0_valid; // @[Mux.scala:30:73] wire _in_0_d_valid_T_2 = state_2_1 & portsDIO_filtered_1_0_valid; // @[Mux.scala:30:73] wire _in_0_d_valid_T_3 = _in_0_d_valid_T_1 \| _in_0_d_valid_T_2; // @[Mux.scala:30:73] wire _in_0_d_valid_WIRE = _in_0_d_valid_T_3; // @[Mux.scala:30:73] assign _in_0_d_valid_T_4 = idle_2 ? _in_0_d_valid_T : _in_0_d_valid_WIRE; // @[Mux.scala:30:73] assign in_0_d_valid = _in_0_d_valid_T_4; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73] assign in_0_d_bits_opcode = _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73] assign in_0_d_bits_param = _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73] assign in_0_d_bits_size = _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73] assign in_0_d_bits_source = _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73] assign in_0_d_bits_sink = _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73] assign in_0_d_bits_denied = _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] wire [31:0] _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73] assign in_0_d_bits_data = _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73] assign in_0_d_bits_corrupt = _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T = muxState_2_0 & portsDIO_filtered_0_bits_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T_1 = muxState_2_1 & portsDIO_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = _in_0_d_bits_T \| _in_0_d_bits_T_1; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_1 = _in_0_d_bits_T_2; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_corrupt = _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73] wire [31:0] _in_0_d_bits_T_3 = muxState_2_0 ? portsDIO_filtered_0_bits_data : 32'h0; // @[Mux.scala:30:73] wire [31:0] _in_0_d_bits_T_4 = muxState_2_1 ? portsDIO_filtered_1_0_bits_data : 32'h0; // @[Mux.scala:30:73] wire [31:0] _in_0_d_bits_T_5 = _in_0_d_bits_T_3 \| _in_0_d_bits_T_4; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_2 = _in_0_d_bits_T_5; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_data = _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = muxState_2_0 & portsDIO_filtered_0_bits_denied; // @[Mux.scala:30:73] wire _in_0_d_bits_T_7 = muxState_2_1 & portsDIO_filtered_1_0_bits_denied; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = _in_0_d_bits_T_6 \| _in_0_d_bits_T_7; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_5 = _in_0_d_bits_T_8; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_denied = _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_9 = muxState_2_0 ? portsDIO_filtered_0_bits_sink : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_10 = muxState_2_1 ? portsDIO_filtered_1_0_bits_sink : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_11 = _in_0_d_bits_T_9 \| _in_0_d_bits_T_10; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_6 = _in_0_d_bits_T_11; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_sink = _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73] wire [5:0] _in_0_d_bits_T_12 = muxState_2_0 ? portsDIO_filtered_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _in_0_d_bits_T_13 = muxState_2_1 ? portsDIO_filtered_1_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _in_0_d_bits_T_14 = _in_0_d_bits_T_12 \| _in_0_d_bits_T_13; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_7 = _in_0_d_bits_T_14; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_source = _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_15 = muxState_2_0 ? portsDIO_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_16 = muxState_2_1 ? portsDIO_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_17 = _in_0_d_bits_T_15 \| _in_0_d_bits_T_16; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_8 = _in_0_d_bits_T_17; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_size = _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_18 = muxState_2_0 ? portsDIO_filtered_0_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_19 = muxState_2_1 ? portsDIO_filtered_1_0_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = _in_0_d_bits_T_18 \| _in_0_d_bits_T_19; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_9 = _in_0_d_bits_T_20; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_param = _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_21 = muxState_2_0 ? portsDIO_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_22 = muxState_2_1 ? portsDIO_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_23 = _in_0_d_bits_T_21 \| _in_0_d_bits_T_22; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_10 = _in_0_d_bits_T_23; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_opcode = _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73] reg [9:0] beatsLeft_3; // @[Arbiter.scala:60:30] wire idle_3 = beatsLeft_3 == 10'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_3 = idle_3 & in_1_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_30 = {portsDIO_filtered_1_1_valid, portsDIO_filtered_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_3 = _readys_T_30; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_31 = readys_valid_3 == _readys_T_30; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_33 = ~_readys_T_32; // @[Arbiter.scala:22:12] wire _readys_T_34 = ~_readys_T_31; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_3; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_6 = ~readys_mask_3; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_7 = readys_valid_3 & _readys_filter_T_6; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_3 = {_readys_filter_T_7, readys_valid_3}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_15 = readys_filter_3[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_16 = {readys_filter_3[3], readys_filter_3[2:0] \| _readys_unready_T_15}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_17 = _readys_unready_T_16; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_18 = _readys_unready_T_17[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_19 = {readys_mask_3, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_3 = {1'h0, _readys_unready_T_18} \| _readys_unready_T_19; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_9 = readys_unready_3[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_10 = readys_unready_3[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_11 = _readys_readys_T_9 & _readys_readys_T_10; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_3 = ~_readys_readys_T_11; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_37 = readys_readys_3; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_35 = \|readys_valid_3; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_36 = latch_3 & _readys_T_35; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_15 = readys_readys_3 & readys_valid_3; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_16 = {_readys_mask_T_15, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_17 = _readys_mask_T_16[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_18 = _readys_mask_T_15 \| _readys_mask_T_17; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_19 = _readys_mask_T_18; // @[package.scala:253:43, :254:17] wire _readys_T_38 = _readys_T_37[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_0 = _readys_T_38; // @[Arbiter.scala:68:{27,76}] wire _readys_T_39 = _readys_T_37[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_1 = _readys_T_39; // @[Arbiter.scala:68:{27,76}] wire _winner_T_6 = readys_3_0 & portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] wire winner_3_0 = _winner_T_6; // @[Arbiter.scala:71:{27,69}] wire _winner_T_7 = readys_3_1 & portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_3_1 = _winner_T_7; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_3 = winner_3_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_3 = prefixOR_1_3 \| winner_3_1; // @[Arbiter.scala:71:27, :76:48] wire _in_1_d_valid_T = portsDIO_filtered_1_valid \| portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to this FIRRTL code module TLCToNoC_11 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<129>, egress_id : UInt}}} inst q of Queue1_TLBundleC_a32d128s7k6z4c_11 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 4) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T) node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_4) node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_5) node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8) node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_10) node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_11) node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<7>(0h40)) node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16) node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<8>(0h80)) node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18) node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20) node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_22) node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_23) node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<8>(0hc0)) node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26) node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28) node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0he), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<5>(0h10), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h12), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h14), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h16), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h24)) connect q.io.enq.bits.source, _q_io_enq_bits_source_T	module TLCToNoC_11( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [7:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0; // @[package.scala:243:{46,71,76}] reg [7:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 8'h1 \| tail_beats1 == 8'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 8'h0; // @[Edges.scala:229:27] tail_counter <= 8'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0) : head_counter - 8'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_prcibus_i1_o2_a21d64s8k1z3u : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_62 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 7, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<21>(0h0) connect _WIRE_30.bits.source, UInt<8>(0h0) connect _WIRE_30.bits.size, UInt<3>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<21>(0h0) connect _WIRE_32.bits.source, UInt<8>(0h0) connect _WIRE_32.bits.size, UInt<3>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<21>(0h0) connect _WIRE_34.bits.source, UInt<8>(0h0) connect _WIRE_34.bits.size, UInt<3>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<21>(0h0) connect _WIRE_36.bits.source, UInt<8>(0h0) connect _WIRE_36.bits.size, UInt<3>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.ready, UInt<1>(0h1) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<21>(0h0) connect _WIRE_38.bits.source, UInt<8>(0h0) connect _WIRE_38.bits.size, UInt<3>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.ready, UInt<1>(0h1) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<21>(0h0) connect _WIRE_48.bits.source, UInt<8>(0h0) connect _WIRE_48.bits.size, UInt<3>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<21>(0h0) connect _WIRE_50.bits.source, UInt<8>(0h0) connect _WIRE_50.bits.size, UInt<3>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<21>(0h0) connect _WIRE_52.bits.source, UInt<8>(0h0) connect _WIRE_52.bits.size, UInt<3>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<21>(0h0) connect _WIRE_54.bits.source, UInt<8>(0h0) connect _WIRE_54.bits.size, UInt<3>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<21>(0h0) connect _WIRE_56.bits.source, UInt<8>(0h0) connect _WIRE_56.bits.size, UInt<3>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<21>(0h0) connect _WIRE_58.bits.source, UInt<8>(0h0) connect _WIRE_58.bits.size, UInt<3>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<21>(0h0) connect _WIRE_60.bits.source, UInt<8>(0h0) connect _WIRE_60.bits.size, UInt<3>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<21>(0h0) connect _WIRE_62.bits.source, UInt<8>(0h0) connect _WIRE_62.bits.size, UInt<3>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<21>(0h0) connect _addressC_WIRE.bits.source, UInt<8>(0h0) connect _addressC_WIRE.bits.size, UInt<3>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<18>(0h10000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<18>(0h10000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<21>(0h0) connect _requestBOI_WIRE.bits.source, UInt<8>(0h0) connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<8>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 7, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 8) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<8>(0hff)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<21>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<8>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 7, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 8) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<8>(0hff)) node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<8>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 7, 0) node _requestDOI_T = shr(out[0].d.bits.source, 8) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<8>(0hff)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<8>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 7, 0) node _requestDOI_T_5 = shr(out[1].d.bits.source, 8) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<8>(0hff)) node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<21>(0h0) connect _beatsBO_WIRE.bits.source, UInt<8>(0h0) connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<21>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<21>(0h0) connect _beatsCI_WIRE.bits.source, UInt<8>(0h0) connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<21>(0h0) connect _portsBIO_WIRE.bits.source, UInt<8>(0h0) connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.address, UInt<21>(0h0) connect _portsBIO_WIRE_2.bits.source, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<21>(0h0) connect _portsCOI_WIRE.bits.source, UInt<8>(0h0) connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_2 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect out[0].d.ready, portsDIO_filtered[0].ready wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect out[1].d.ready, portsDIO_filtered_1[0].ready wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_2 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 connect out[0].a, portsAOI_filtered[0] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.address, UInt<21>(0h0) connect _WIRE_72.bits.source, UInt<8>(0h0) connect _WIRE_72.bits.size, UInt<3>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_74.bits.sink, UInt<1>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect out[1].a, portsAOI_filtered[1] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.address, UInt<21>(0h0) connect _WIRE_76.bits.source, UInt<8>(0h0) connect _WIRE_76.bits.size, UInt<3>(0h0) connect _WIRE_76.bits.param, UInt<3>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_78.bits.sink, UInt<1>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<64>(0h0) connect _WIRE_80.bits.mask, UInt<8>(0h0) connect _WIRE_80.bits.address, UInt<21>(0h0) connect _WIRE_80.bits.source, UInt<8>(0h0) connect _WIRE_80.bits.size, UInt<3>(0h0) connect _WIRE_80.bits.param, UInt<2>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.mask invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, in[0].d.ready) node _readys_T = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsDIO_filtered[0].valid) node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<64> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<1> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<8> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<3> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)	module TLXbar_prcibus_i1_o2_a21d64s8k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire [7:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [63:0] auto_anon_out_1_d_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] out_1_d_bits_data = 64'h0; // @[Xbar.scala:216:19] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _in_0_d_bits_T_4 = 64'h0; // @[Mux.scala:30:73] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] x1_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] in_0_d_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_WIRE_param = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_19 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_in_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_d_bits_sink = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_denied = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _out_1_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_WIRE_sink = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_denied = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_7 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_10 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_11 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_6 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [20:0] _addressC_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _addressC_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _requestCIO_T = 21'h0; // @[Parameters.scala:137:31] wire [20:0] _requestCIO_T_5 = 21'h0; // @[Parameters.scala:137:31] wire [20:0] _requestBOI_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _requestBOI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _requestBOI_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _requestBOI_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsBO_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _beatsBO_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsBO_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _beatsBO_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsCI_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _beatsCI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _portsBIO_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _portsBIO_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] portsBIO_filtered_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] _portsBIO_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _portsBIO_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] portsBIO_filtered_1_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] _portsCOI_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _portsCOI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] portsCOI_filtered_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] portsCOI_filtered_1_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [7:0] _addressC_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _addressC_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _requestBOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_uncommonBits_T = 8'h0; // @[Parameters.scala:52:29] wire [7:0] requestBOI_uncommonBits = 8'h0; // @[Parameters.scala:52:56] wire [7:0] _requestBOI_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_uncommonBits_T_1 = 8'h0; // @[Parameters.scala:52:29] wire [7:0] requestBOI_uncommonBits_1 = 8'h0; // @[Parameters.scala:52:56] wire [7:0] _beatsBO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsCI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _beatsCI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _portsBIO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_source = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsCOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _portsCOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] portsCOI_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsCOI_filtered_1_bits_source = 8'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [21:0] _requestCIO_T_1 = 22'h0; // @[Parameters.scala:137:41] wire [21:0] _requestCIO_T_2 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_3 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_6 = 22'h0; // @[Parameters.scala:137:41] wire [21:0] _requestCIO_T_7 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_8 = 22'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [7:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [7:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [7:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [20:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [7:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [7:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [7:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [20:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [20:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [20:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [7:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [7:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [7:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [7:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [7:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [21:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [21:0] _requestAIO_T_2 = _requestAIO_T_1 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 22'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [20:0] _requestAIO_T_5 = {in_0_a_bits_address[20:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [21:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [21:0] _requestAIO_T_7 = _requestAIO_T_6 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 22'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [7:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [7:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T \| _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid \| portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_1 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T	module MulAddRecFNToRaw_preMul_e8_s24_1( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [8:0] rawC_exp = 9'h0; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _sNatCAlignDist_T = {sExpAlignedProd[10], sExpAlignedProd}; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero \| rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 \| _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN \| rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _sNatCAlignDist_T - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_14 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 55, 55) wire common_expOut : UInt<12> wire common_fractOut : UInt<52> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 11, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 11, 11) node roundMask_lsbs = bits(_roundMask_T_1, 10, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 10, 10) node roundMask_lsbs_1 = bits(roundMask_lsbs, 9, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 9, 9) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 8, 0) node roundMask_msb_3 = bits(roundMask_lsbs_2, 8, 8) node roundMask_lsbs_3 = bits(roundMask_lsbs_2, 7, 0) node roundMask_msb_4 = bits(roundMask_lsbs_3, 7, 7) node roundMask_lsbs_4 = bits(roundMask_lsbs_3, 6, 0) node roundMask_msb_5 = bits(roundMask_lsbs_4, 6, 6) node roundMask_lsbs_5 = bits(roundMask_lsbs_4, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_5) node _roundMask_T_2 = bits(roundMask_shift, 63, 13) node _roundMask_T_3 = bits(_roundMask_T_2, 31, 0) node _roundMask_T_4 = shl(UInt<16>(0hffff), 16) node _roundMask_T_5 = xor(UInt<32>(0hffffffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 16) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 15, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 16) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 23, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 8) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 8) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 23, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 8) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 27, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 4) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 4) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 27, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 4) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 29, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 2) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 2) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 29, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 2) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_35, 30, 0) node _roundMask_T_44 = shl(_roundMask_T_43, 1) node _roundMask_T_45 = xor(_roundMask_T_35, _roundMask_T_44) node _roundMask_T_46 = shr(_roundMask_T_42, 1) node _roundMask_T_47 = and(_roundMask_T_46, _roundMask_T_45) node _roundMask_T_48 = bits(_roundMask_T_42, 30, 0) node _roundMask_T_49 = shl(_roundMask_T_48, 1) node _roundMask_T_50 = not(_roundMask_T_45) node _roundMask_T_51 = and(_roundMask_T_49, _roundMask_T_50) node _roundMask_T_52 = or(_roundMask_T_47, _roundMask_T_51) node _roundMask_T_53 = bits(_roundMask_T_2, 50, 32) node _roundMask_T_54 = bits(_roundMask_T_53, 15, 0) node _roundMask_T_55 = shl(UInt<8>(0hff), 8) node _roundMask_T_56 = xor(UInt<16>(0hffff), _roundMask_T_55) node _roundMask_T_57 = shr(_roundMask_T_54, 8) node _roundMask_T_58 = and(_roundMask_T_57, _roundMask_T_56) node _roundMask_T_59 = bits(_roundMask_T_54, 7, 0) node _roundMask_T_60 = shl(_roundMask_T_59, 8) node _roundMask_T_61 = not(_roundMask_T_56) node _roundMask_T_62 = and(_roundMask_T_60, _roundMask_T_61) node _roundMask_T_63 = or(_roundMask_T_58, _roundMask_T_62) node _roundMask_T_64 = bits(_roundMask_T_56, 11, 0) node _roundMask_T_65 = shl(_roundMask_T_64, 4) node _roundMask_T_66 = xor(_roundMask_T_56, _roundMask_T_65) node _roundMask_T_67 = shr(_roundMask_T_63, 4) node _roundMask_T_68 = and(_roundMask_T_67, _roundMask_T_66) node _roundMask_T_69 = bits(_roundMask_T_63, 11, 0) node _roundMask_T_70 = shl(_roundMask_T_69, 4) node _roundMask_T_71 = not(_roundMask_T_66) node _roundMask_T_72 = and(_roundMask_T_70, _roundMask_T_71) node _roundMask_T_73 = or(_roundMask_T_68, _roundMask_T_72) node _roundMask_T_74 = bits(_roundMask_T_66, 13, 0) node _roundMask_T_75 = shl(_roundMask_T_74, 2) node _roundMask_T_76 = xor(_roundMask_T_66, _roundMask_T_75) node _roundMask_T_77 = shr(_roundMask_T_73, 2) node _roundMask_T_78 = and(_roundMask_T_77, _roundMask_T_76) node _roundMask_T_79 = bits(_roundMask_T_73, 13, 0) node _roundMask_T_80 = shl(_roundMask_T_79, 2) node _roundMask_T_81 = not(_roundMask_T_76) node _roundMask_T_82 = and(_roundMask_T_80, _roundMask_T_81) node _roundMask_T_83 = or(_roundMask_T_78, _roundMask_T_82) node _roundMask_T_84 = bits(_roundMask_T_76, 14, 0) node _roundMask_T_85 = shl(_roundMask_T_84, 1) node _roundMask_T_86 = xor(_roundMask_T_76, _roundMask_T_85) node _roundMask_T_87 = shr(_roundMask_T_83, 1) node _roundMask_T_88 = and(_roundMask_T_87, _roundMask_T_86) node _roundMask_T_89 = bits(_roundMask_T_83, 14, 0) node _roundMask_T_90 = shl(_roundMask_T_89, 1) node _roundMask_T_91 = not(_roundMask_T_86) node _roundMask_T_92 = and(_roundMask_T_90, _roundMask_T_91) node _roundMask_T_93 = or(_roundMask_T_88, _roundMask_T_92) node _roundMask_T_94 = bits(_roundMask_T_53, 18, 16) node _roundMask_T_95 = bits(_roundMask_T_94, 1, 0) node _roundMask_T_96 = bits(_roundMask_T_95, 0, 0) node _roundMask_T_97 = bits(_roundMask_T_95, 1, 1) node _roundMask_T_98 = cat(_roundMask_T_96, _roundMask_T_97) node _roundMask_T_99 = bits(_roundMask_T_94, 2, 2) node _roundMask_T_100 = cat(_roundMask_T_98, _roundMask_T_99) node _roundMask_T_101 = cat(_roundMask_T_93, _roundMask_T_100) node _roundMask_T_102 = cat(_roundMask_T_52, _roundMask_T_101) node _roundMask_T_103 = not(_roundMask_T_102) node _roundMask_T_104 = mux(roundMask_msb_5, UInt<1>(0h0), _roundMask_T_103) node _roundMask_T_105 = not(_roundMask_T_104) node _roundMask_T_106 = not(_roundMask_T_105) node _roundMask_T_107 = mux(roundMask_msb_4, UInt<1>(0h0), _roundMask_T_106) node _roundMask_T_108 = not(_roundMask_T_107) node _roundMask_T_109 = not(_roundMask_T_108) node _roundMask_T_110 = mux(roundMask_msb_3, UInt<1>(0h0), _roundMask_T_109) node _roundMask_T_111 = not(_roundMask_T_110) node _roundMask_T_112 = not(_roundMask_T_111) node _roundMask_T_113 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_112) node _roundMask_T_114 = not(_roundMask_T_113) node _roundMask_T_115 = cat(_roundMask_T_114, UInt<3>(0h7)) node roundMask_msb_6 = bits(roundMask_lsbs_1, 9, 9) node roundMask_lsbs_6 = bits(roundMask_lsbs_1, 8, 0) node roundMask_msb_7 = bits(roundMask_lsbs_6, 8, 8) node roundMask_lsbs_7 = bits(roundMask_lsbs_6, 7, 0) node roundMask_msb_8 = bits(roundMask_lsbs_7, 7, 7) node roundMask_lsbs_8 = bits(roundMask_lsbs_7, 6, 0) node roundMask_msb_9 = bits(roundMask_lsbs_8, 6, 6) node roundMask_lsbs_9 = bits(roundMask_lsbs_8, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_9) node _roundMask_T_116 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_117 = bits(_roundMask_T_116, 1, 0) node _roundMask_T_118 = bits(_roundMask_T_117, 0, 0) node _roundMask_T_119 = bits(_roundMask_T_117, 1, 1) node _roundMask_T_120 = cat(_roundMask_T_118, _roundMask_T_119) node _roundMask_T_121 = bits(_roundMask_T_116, 2, 2) node _roundMask_T_122 = cat(_roundMask_T_120, _roundMask_T_121) node _roundMask_T_123 = mux(roundMask_msb_9, _roundMask_T_122, UInt<1>(0h0)) node _roundMask_T_124 = mux(roundMask_msb_8, _roundMask_T_123, UInt<1>(0h0)) node _roundMask_T_125 = mux(roundMask_msb_7, _roundMask_T_124, UInt<1>(0h0)) node _roundMask_T_126 = mux(roundMask_msb_6, _roundMask_T_125, UInt<1>(0h0)) node _roundMask_T_127 = mux(roundMask_msb_1, _roundMask_T_115, _roundMask_T_126) node _roundMask_T_128 = mux(roundMask_msb, _roundMask_T_127, UInt<1>(0h0)) node _roundMask_T_129 = or(_roundMask_T_128, doShiftSigDown1) node roundMask = cat(_roundMask_T_129, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<55>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 53) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 11, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 52, 1) node _common_fractOut_T_1 = bits(roundedSig, 51, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 10) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<11>(0h3ce))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 54, 54) node _roundCarry_T_1 = bits(roundedSig, 53, 53) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 11) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<12>(0he00), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<12>(0h3ce)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<12>(0h400), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<12>(0h200), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<12>(0h3ce), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<12>(0hbff), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<12>(0hc00), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<12>(0he00), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<52>(0h8000000000000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<52>(0hfffffffffffff), UInt<52>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_14( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:58:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [31:0] _roundMask_T_5 = 32'hFFFF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_4 = 32'hFFFF0000; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_10 = 32'hFFFF0000; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_13 = 24'hFFFF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_14 = 32'hFFFF00; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_15 = 32'hFF00FF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_20 = 32'hFF00FF00; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_23 = 28'hFF00FF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_24 = 32'hFF00FF0; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_25 = 32'hF0F0F0F; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_30 = 32'hF0F0F0F0; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_33 = 30'hF0F0F0F; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_34 = 32'h3C3C3C3C; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_35 = 32'h33333333; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_40 = 32'hCCCCCCCC; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_43 = 31'h33333333; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_44 = 32'h66666666; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_45 = 32'h55555555; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_50 = 32'hAAAAAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_56 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_55 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_61 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_64 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_65 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_66 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_71 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_74 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_75 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_76 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_81 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_84 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_85 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_86 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_91 = 16'hAAAA; // @[primitives.scala:77:20] wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [55:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire _common_underflow_T_7 = io_detectTininess_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :222:49] wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[55]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [11:0] _roundMask_T = io_in_sExp_0[11:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [11:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[11]; // @[primitives.scala:52:21, :58:25] wire [10:0] roundMask_lsbs = _roundMask_T_1[10:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[10]; // @[primitives.scala:58:25, :59:26] wire [9:0] roundMask_lsbs_1 = roundMask_lsbs[9:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_6 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26] wire [8:0] roundMask_lsbs_2 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26] wire [8:0] roundMask_lsbs_6 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26] wire roundMask_msb_3 = roundMask_lsbs_2[8]; // @[primitives.scala:58:25, :59:26] wire [7:0] roundMask_lsbs_3 = roundMask_lsbs_2[7:0]; // @[primitives.scala:59:26] wire roundMask_msb_4 = roundMask_lsbs_3[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_4 = roundMask_lsbs_3[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_5 = roundMask_lsbs_4[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_5 = roundMask_lsbs_4[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_5); // @[primitives.scala:59:26, :76:56] wire [50:0] _roundMask_T_2 = roundMask_shift[63:13]; // @[primitives.scala:76:56, :78:22] wire [31:0] _roundMask_T_3 = _roundMask_T_2[31:0]; // @[primitives.scala:77:20, :78:22] wire [15:0] _roundMask_T_6 = _roundMask_T_3[31:16]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_7 = {16'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_8 = _roundMask_T_3[15:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_9 = {_roundMask_T_8, 16'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_11 = _roundMask_T_9 & 32'hFFFF0000; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_16 = _roundMask_T_12[31:8]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_17 = {8'h0, _roundMask_T_16 & 24'hFF00FF}; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_18 = _roundMask_T_12[23:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_19 = {_roundMask_T_18, 8'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_21 = _roundMask_T_19 & 32'hFF00FF00; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_26 = _roundMask_T_22[31:4]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_27 = {4'h0, _roundMask_T_26 & 28'hF0F0F0F}; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_28 = _roundMask_T_22[27:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_29 = {_roundMask_T_28, 4'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_31 = _roundMask_T_29 & 32'hF0F0F0F0; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_36 = _roundMask_T_32[31:2]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_37 = {2'h0, _roundMask_T_36 & 30'h33333333}; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_38 = _roundMask_T_32[29:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_39 = {_roundMask_T_38, 2'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_41 = _roundMask_T_39 & 32'hCCCCCCCC; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_46 = _roundMask_T_42[31:1]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_47 = {1'h0, _roundMask_T_46 & 31'h55555555}; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_48 = _roundMask_T_42[30:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_49 = {_roundMask_T_48, 1'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_51 = _roundMask_T_49 & 32'hAAAAAAAA; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_52 = _roundMask_T_47 \| _roundMask_T_51; // @[primitives.scala:77:20] wire [18:0] _roundMask_T_53 = _roundMask_T_2[50:32]; // @[primitives.scala:77:20, :78:22] wire [15:0] _roundMask_T_54 = _roundMask_T_53[15:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_57 = _roundMask_T_54[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_58 = {8'h0, _roundMask_T_57}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_59 = _roundMask_T_54[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_60 = {_roundMask_T_59, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_62 = _roundMask_T_60 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_63 = _roundMask_T_58 \| _roundMask_T_62; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_67 = _roundMask_T_63[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_68 = {4'h0, _roundMask_T_67 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_69 = _roundMask_T_63[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_70 = {_roundMask_T_69, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_72 = _roundMask_T_70 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_73 = _roundMask_T_68 \| _roundMask_T_72; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_77 = _roundMask_T_73[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_78 = {2'h0, _roundMask_T_77 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_79 = _roundMask_T_73[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_80 = {_roundMask_T_79, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_82 = _roundMask_T_80 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_83 = _roundMask_T_78 \| _roundMask_T_82; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_87 = _roundMask_T_83[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_88 = {1'h0, _roundMask_T_87 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_89 = _roundMask_T_83[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_90 = {_roundMask_T_89, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_92 = _roundMask_T_90 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_93 = _roundMask_T_88 \| _roundMask_T_92; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_94 = _roundMask_T_53[18:16]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_95 = _roundMask_T_94[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_96 = _roundMask_T_95[0]; // @[primitives.scala:77:20] wire _roundMask_T_97 = _roundMask_T_95[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_98 = {_roundMask_T_96, _roundMask_T_97}; // @[primitives.scala:77:20] wire _roundMask_T_99 = _roundMask_T_94[2]; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_100 = {_roundMask_T_98, _roundMask_T_99}; // @[primitives.scala:77:20] wire [18:0] _roundMask_T_101 = {_roundMask_T_93, _roundMask_T_100}; // @[primitives.scala:77:20] wire [50:0] _roundMask_T_102 = {_roundMask_T_52, _roundMask_T_101}; // @[primitives.scala:77:20] wire [50:0] _roundMask_T_103 = ~_roundMask_T_102; // @[primitives.scala:73:32, :77:20] wire [50:0] _roundMask_T_104 = roundMask_msb_5 ? 51'h0 : _roundMask_T_103; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_105 = ~_roundMask_T_104; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_106 = ~_roundMask_T_105; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_107 = roundMask_msb_4 ? 51'h0 : _roundMask_T_106; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_108 = ~_roundMask_T_107; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_109 = ~_roundMask_T_108; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_110 = roundMask_msb_3 ? 51'h0 : _roundMask_T_109; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_111 = ~_roundMask_T_110; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_112 = ~_roundMask_T_111; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_113 = roundMask_msb_2 ? 51'h0 : _roundMask_T_112; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_114 = ~_roundMask_T_113; // @[primitives.scala:73:{17,21}] wire [53:0] _roundMask_T_115 = {_roundMask_T_114, 3'h7}; // @[primitives.scala:68:58, :73:17] wire roundMask_msb_7 = roundMask_lsbs_6[8]; // @[primitives.scala:58:25, :59:26] wire [7:0] roundMask_lsbs_7 = roundMask_lsbs_6[7:0]; // @[primitives.scala:59:26] wire roundMask_msb_8 = roundMask_lsbs_7[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_8 = roundMask_lsbs_7[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_9 = roundMask_lsbs_8[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_9 = roundMask_lsbs_8[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_9); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_116 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_117 = _roundMask_T_116[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_118 = _roundMask_T_117[0]; // @[primitives.scala:77:20] wire _roundMask_T_119 = _roundMask_T_117[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_120 = {_roundMask_T_118, _roundMask_T_119}; // @[primitives.scala:77:20] wire _roundMask_T_121 = _roundMask_T_116[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_122 = {_roundMask_T_120, _roundMask_T_121}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_123 = roundMask_msb_9 ? _roundMask_T_122 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [2:0] _roundMask_T_124 = roundMask_msb_8 ? _roundMask_T_123 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [2:0] _roundMask_T_125 = roundMask_msb_7 ? _roundMask_T_124 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [2:0] _roundMask_T_126 = roundMask_msb_6 ? _roundMask_T_125 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [53:0] _roundMask_T_127 = roundMask_msb_1 ? _roundMask_T_115 : {51'h0, _roundMask_T_126}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [53:0] _roundMask_T_128 = roundMask_msb ? _roundMask_T_127 : 54'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [53:0] _roundMask_T_129 = {_roundMask_T_128[53:1], _roundMask_T_128[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [55:0] roundMask = {_roundMask_T_129, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [56:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [55:0] shiftedRoundMask = _shiftedRoundMask_T[56:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [55:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [55:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [55:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [55:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [55:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [54:0] _roundedSig_T_6 = roundMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [54:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [55:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [55:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [54:0] _roundedSig_T_14 = roundPosMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [54:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [13:0] sRoundedExp = {io_in_sExp_0[12], io_in_sExp_0} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[13:10]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 14'sh3CE; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[12:11]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_7 & _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:{49,77}, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [11:0] _expOut_T_5 = pegMinNonzeroMagOut ? 12'hC31 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [11:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [11:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [11:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 10'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [11:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [11:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [11:0] _expOut_T_14 = pegMinNonzeroMagOut ? 12'h3CE : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [11:0] _expOut_T_15 = _expOut_T_13 \| _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [11:0] _expOut_T_16 = pegMaxFiniteMagOut ? 12'hBFF : 12'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [11:0] _expOut_T_17 = _expOut_T_15 \| _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [11:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [11:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [51:0] _fractOut_T_4 = {52{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [51:0] fractOut = _fractOut_T_3 \| _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Router_15 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}}, flip ingress_nodes_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_15 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire debugNodeOut : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in connect auto.egress_nodes_out, egressNodesOut connect auto.debug_out, debugNodeOut inst input_unit_0_from_1 of InputUnit_15 connect input_unit_0_from_1.clock, clock connect input_unit_0_from_1.reset, reset inst ingress_unit_1_from_3 of IngressUnit_25 connect ingress_unit_1_from_3.clock, clock connect ingress_unit_1_from_3.reset, reset inst output_unit_0_to_3 of OutputUnit_15 connect output_unit_0_to_3.clock, clock connect output_unit_0_to_3.reset, reset inst egress_unit_1_to_3 of EgressUnit_21 connect egress_unit_1_to_3.clock, clock connect egress_unit_1_to_3.reset, reset inst switch of Switch_15 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_15 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_15 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_15 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_3 = bits(_fires_count_T_2, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_3 connect input_unit_0_from_1.io.in, destNodesIn connect ingress_unit_1_from_3.io.in, ingressNodesIn.flit connect output_unit_0_to_3.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_3.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_3.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_3.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_3.io.out.valid connect egress_unit_1_to_3.io.out.ready, egressNodesOut.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_1.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_3.io.router_req connect input_unit_0_from_1.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_3.io.router_resp, route_computer.io.resp.`1` connect vc_allocator.io.req.`0`, input_unit_0_from_1.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_3.io.vcalloc_req connect input_unit_0_from_1.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_3.io.vcalloc_resp, vc_allocator.io.resp.`1` connect output_unit_0_to_3.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_3.io.allocs, vc_allocator.io.out_allocs.`1` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_3.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_3.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_3.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_3.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_3.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_3.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_3.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_3.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_3.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_3.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_3.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_3.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_3.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_3.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_3.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_3.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_3.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_3.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_3.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_3.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_3.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_3.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_3.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_3.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_3.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_3.io.channel_status[0].occupied connect input_unit_0_from_1.io.out_credit_available.`0`[0], output_unit_0_to_3.io.credit_available[0] connect input_unit_0_from_1.io.out_credit_available.`0`[1], output_unit_0_to_3.io.credit_available[1] connect input_unit_0_from_1.io.out_credit_available.`0`[2], output_unit_0_to_3.io.credit_available[2] connect input_unit_0_from_1.io.out_credit_available.`0`[3], output_unit_0_to_3.io.credit_available[3] connect input_unit_0_from_1.io.out_credit_available.`1`[0], egress_unit_1_to_3.io.credit_available[0] connect ingress_unit_1_from_3.io.out_credit_available.`0`[0], output_unit_0_to_3.io.credit_available[0] connect ingress_unit_1_from_3.io.out_credit_available.`0`[1], output_unit_0_to_3.io.credit_available[1] connect ingress_unit_1_from_3.io.out_credit_available.`0`[2], output_unit_0_to_3.io.credit_available[2] connect ingress_unit_1_from_3.io.out_credit_available.`0`[3], output_unit_0_to_3.io.credit_available[3] connect ingress_unit_1_from_3.io.out_credit_available.`1`[0], egress_unit_1_to_3.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_1.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_3.io.salloc_req[0] connect output_unit_0_to_3.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_3.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_3.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_3.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_3.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_3.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_3.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_3.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect egress_unit_1_to_3.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_3.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_1.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_3.io.out[0] connect output_unit_0_to_3.io.in, switch.io.out.`0` connect egress_unit_1_to_3.io.in, switch.io.out.`1` reg REG : { `1` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect input_unit_0_from_1.io.block, UInt<1>(0h0) connect ingress_unit_1_from_3.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_1.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_3.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_1.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_3.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_33 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 1 2 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i3 2 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d 2 e3 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20	module Router_15( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_1_to_3_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_3_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_3_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_3_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _ingress_unit_1_from_3_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_1_from_3_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_3_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_in_ready; // @[Router.scala:116:13] wire [1:0] _input_unit_0_from_1_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_1_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_1_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_1_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_1_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_1_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_3_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_193 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_345 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_193( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_345 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_58 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<17>(0h10000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = and(_T_207, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = and(_T_206, _T_214) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_215, UInt<1>(0h1), "") : assert_26 node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(is_aligned, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_225 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(io.in.a.bits.mask, mask) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_229, UInt<1>(0h1), "") : assert_30 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_237 = shr(io.in.a.bits.source, 12) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_5) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = and(_T_245, _T_250) node _T_252 = or(UInt<1>(0h0), _T_251) node _T_253 = and(_T_244, _T_252) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_253, UInt<1>(0h1), "") : assert_31 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(is_aligned, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_263 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_263, UInt<1>(0h1), "") : assert_34 node _T_267 = not(mask) node _T_268 = and(io.in.a.bits.mask, _T_267) node _T_269 = eq(_T_268, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_269, UInt<1>(0h1), "") : assert_35 node _T_273 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_277 = shr(io.in.a.bits.source, 12) node _T_278 = eq(_T_277, UInt<1>(0h0)) node _T_279 = leq(UInt<1>(0h0), uncommonBits_6) node _T_280 = and(_T_278, _T_279) node _T_281 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_282 = and(_T_280, _T_281) node _T_283 = and(_T_276, _T_282) node _T_284 = or(UInt<1>(0h0), _T_283) node _T_285 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = and(_T_285, _T_290) node _T_292 = or(UInt<1>(0h0), _T_291) node _T_293 = and(_T_284, _T_292) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_293, UInt<1>(0h1), "") : assert_36 node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(is_aligned, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_303 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(_T_303, UInt<1>(0h0)) when _T_306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_303, UInt<1>(0h1), "") : assert_39 node _T_307 = eq(io.in.a.bits.mask, mask) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_307, UInt<1>(0h1), "") : assert_40 node _T_311 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_311 : node _T_312 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_313 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_315 = shr(io.in.a.bits.source, 12) node _T_316 = eq(_T_315, UInt<1>(0h0)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_7) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_320 = and(_T_318, _T_319) node _T_321 = and(_T_314, _T_320) node _T_322 = or(UInt<1>(0h0), _T_321) node _T_323 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = and(_T_323, _T_328) node _T_330 = or(UInt<1>(0h0), _T_329) node _T_331 = and(_T_322, _T_330) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_331, UInt<1>(0h1), "") : assert_41 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(is_aligned, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_341 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(_T_341, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_341, UInt<1>(0h1), "") : assert_44 node _T_345 = eq(io.in.a.bits.mask, mask) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_345, UInt<1>(0h1), "") : assert_45 node _T_349 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_349 : node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_352 = and(_T_350, _T_351) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_353 = shr(io.in.a.bits.source, 12) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = leq(UInt<1>(0h0), uncommonBits_8) node _T_356 = and(_T_354, _T_355) node _T_357 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_358 = and(_T_356, _T_357) node _T_359 = and(_T_352, _T_358) node _T_360 = or(UInt<1>(0h0), _T_359) node _T_361 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = and(_T_361, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = and(_T_360, _T_368) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_369, UInt<1>(0h1), "") : assert_46 node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(is_aligned, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_379 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_379, UInt<1>(0h1), "") : assert_49 node _T_383 = eq(io.in.a.bits.mask, mask) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_383, UInt<1>(0h1), "") : assert_50 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_387, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_391 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_391, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_395 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_395 : node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_399 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_399, UInt<1>(0h1), "") : assert_54 node _T_403 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_403, UInt<1>(0h1), "") : assert_55 node _T_407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_407, UInt<1>(0h1), "") : assert_56 node _T_411 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_411, UInt<1>(0h1), "") : assert_57 node _T_415 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_415 : node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(sink_ok, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_422 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_422, UInt<1>(0h1), "") : assert_60 node _T_426 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_426, UInt<1>(0h1), "") : assert_61 node _T_430 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_431 = asUInt(reset) node _T_432 = eq(_T_431, UInt<1>(0h0)) when _T_432 : node _T_433 = eq(_T_430, UInt<1>(0h0)) when _T_433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_430, UInt<1>(0h1), "") : assert_62 node _T_434 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_434, UInt<1>(0h1), "") : assert_63 node _T_438 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_439, UInt<1>(0h1), "") : assert_64 node _T_443 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_443 : node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(sink_ok, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_450 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_450, UInt<1>(0h1), "") : assert_67 node _T_454 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_454, UInt<1>(0h1), "") : assert_68 node _T_458 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(_T_458, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_458, UInt<1>(0h1), "") : assert_69 node _T_462 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_463 = or(_T_462, io.in.d.bits.corrupt) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_463, UInt<1>(0h1), "") : assert_70 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_468, UInt<1>(0h1), "") : assert_71 node _T_472 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_472 : node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_476 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_476, UInt<1>(0h1), "") : assert_73 node _T_480 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_480, UInt<1>(0h1), "") : assert_74 node _T_484 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_485, UInt<1>(0h1), "") : assert_75 node _T_489 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_493 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_493, UInt<1>(0h1), "") : assert_77 node _T_497 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_498 = or(_T_497, io.in.d.bits.corrupt) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_498, UInt<1>(0h1), "") : assert_78 node _T_502 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = asUInt(reset) node _T_505 = eq(_T_504, UInt<1>(0h0)) when _T_505 : node _T_506 = eq(_T_503, UInt<1>(0h0)) when _T_506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_503, UInt<1>(0h1), "") : assert_79 node _T_507 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_507 : node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_511 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(_T_511, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_511, UInt<1>(0h1), "") : assert_81 node _T_515 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(_T_515, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_515, UInt<1>(0h1), "") : assert_82 node _T_519 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_520, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_524 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_524, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_528 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_528, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_532 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_532, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_536 = eq(a_first, UInt<1>(0h0)) node _T_537 = and(io.in.a.valid, _T_536) when _T_537 : node _T_538 = eq(io.in.a.bits.opcode, opcode) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_538, UInt<1>(0h1), "") : assert_87 node _T_542 = eq(io.in.a.bits.param, param) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_542, UInt<1>(0h1), "") : assert_88 node _T_546 = eq(io.in.a.bits.size, size) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_546, UInt<1>(0h1), "") : assert_89 node _T_550 = eq(io.in.a.bits.source, source) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_550, UInt<1>(0h1), "") : assert_90 node _T_554 = eq(io.in.a.bits.address, address) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_554, UInt<1>(0h1), "") : assert_91 node _T_558 = and(io.in.a.ready, io.in.a.valid) node _T_559 = and(_T_558, a_first) when _T_559 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_560 = eq(d_first, UInt<1>(0h0)) node _T_561 = and(io.in.d.valid, _T_560) when _T_561 : node _T_562 = eq(io.in.d.bits.opcode, opcode_1) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_562, UInt<1>(0h1), "") : assert_92 node _T_566 = eq(io.in.d.bits.param, param_1) node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(_T_566, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_566, UInt<1>(0h1), "") : assert_93 node _T_570 = eq(io.in.d.bits.size, size_1) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_570, UInt<1>(0h1), "") : assert_94 node _T_574 = eq(io.in.d.bits.source, source_1) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_574, UInt<1>(0h1), "") : assert_95 node _T_578 = eq(io.in.d.bits.sink, sink) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_578, UInt<1>(0h1), "") : assert_96 node _T_582 = eq(io.in.d.bits.denied, denied) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_582, UInt<1>(0h1), "") : assert_97 node _T_586 = and(io.in.d.ready, io.in.d.valid) node _T_587 = and(_T_586, d_first) when _T_587 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_588 = and(io.in.a.valid, a_first_1) node _T_589 = and(_T_588, UInt<1>(0h1)) when _T_589 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_590 = and(io.in.a.ready, io.in.a.valid) node _T_591 = and(_T_590, a_first_1) node _T_592 = and(_T_591, UInt<1>(0h1)) when _T_592 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_593 = dshr(inflight, io.in.a.bits.source) node _T_594 = bits(_T_593, 0, 0) node _T_595 = eq(_T_594, UInt<1>(0h0)) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_595, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_599 = and(io.in.d.valid, d_first_1) node _T_600 = and(_T_599, UInt<1>(0h1)) node _T_601 = eq(d_release_ack, UInt<1>(0h0)) node _T_602 = and(_T_600, _T_601) when _T_602 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_603 = and(io.in.d.ready, io.in.d.valid) node _T_604 = and(_T_603, d_first_1) node _T_605 = and(_T_604, UInt<1>(0h1)) node _T_606 = eq(d_release_ack, UInt<1>(0h0)) node _T_607 = and(_T_605, _T_606) when _T_607 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_608 = and(io.in.d.valid, d_first_1) node _T_609 = and(_T_608, UInt<1>(0h1)) node _T_610 = eq(d_release_ack, UInt<1>(0h0)) node _T_611 = and(_T_609, _T_610) when _T_611 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_612 = dshr(inflight, io.in.d.bits.source) node _T_613 = bits(_T_612, 0, 0) node _T_614 = or(_T_613, same_cycle_resp) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_614, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_618 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_619 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_620 = or(_T_618, _T_619) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_620, UInt<1>(0h1), "") : assert_100 node _T_624 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_624, UInt<1>(0h1), "") : assert_101 else : node _T_628 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_629 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_630 = or(_T_628, _T_629) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_630, UInt<1>(0h1), "") : assert_102 node _T_634 = eq(io.in.d.bits.size, a_size_lookup) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_634, UInt<1>(0h1), "") : assert_103 node _T_638 = and(io.in.d.valid, d_first_1) node _T_639 = and(_T_638, a_first_1) node _T_640 = and(_T_639, io.in.a.valid) node _T_641 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_642 = and(_T_640, _T_641) node _T_643 = eq(d_release_ack, UInt<1>(0h0)) node _T_644 = and(_T_642, _T_643) when _T_644 : node _T_645 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_646 = or(_T_645, io.in.a.ready) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_646, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_118 node _T_650 = orr(inflight) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_653 = or(_T_651, _T_652) node _T_654 = lt(watchdog, plusarg_reader.out) node _T_655 = or(_T_653, _T_654) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_655, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_659 = and(io.in.a.ready, io.in.a.valid) node _T_660 = and(io.in.d.ready, io.in.d.valid) node _T_661 = or(_T_659, _T_660) when _T_661 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_662 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<17>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_663 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_664 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_665 = and(_T_663, _T_664) node _T_666 = and(_T_662, _T_665) when _T_666 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_667 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_668 = and(_T_667, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_669 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_673 = dshr(inflight_1, _WIRE_15.bits.source) node _T_674 = bits(_T_673, 0, 0) node _T_675 = eq(_T_674, UInt<1>(0h0)) node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(_T_675, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_675, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_679 = and(io.in.d.valid, d_first_2) node _T_680 = and(_T_679, UInt<1>(0h1)) node _T_681 = and(_T_680, d_release_ack_1) when _T_681 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_682 = and(io.in.d.ready, io.in.d.valid) node _T_683 = and(_T_682, d_first_2) node _T_684 = and(_T_683, UInt<1>(0h1)) node _T_685 = and(_T_684, d_release_ack_1) when _T_685 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_686 = and(io.in.d.valid, d_first_2) node _T_687 = and(_T_686, UInt<1>(0h1)) node _T_688 = and(_T_687, d_release_ack_1) when _T_688 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_689 = dshr(inflight_1, io.in.d.bits.source) node _T_690 = bits(_T_689, 0, 0) node _T_691 = or(_T_690, same_cycle_resp_1) node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(_T_691, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_691, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_695 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_696 = asUInt(reset) node _T_697 = eq(_T_696, UInt<1>(0h0)) when _T_697 : node _T_698 = eq(_T_695, UInt<1>(0h0)) when _T_698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_695, UInt<1>(0h1), "") : assert_108 else : node _T_699 = eq(io.in.d.bits.size, c_size_lookup) node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(_T_699, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_699, UInt<1>(0h1), "") : assert_109 node _T_703 = and(io.in.d.valid, d_first_2) node _T_704 = and(_T_703, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_705 = and(_T_704, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_706 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_707 = and(_T_705, _T_706) node _T_708 = and(_T_707, d_release_ack_1) node _T_709 = eq(c_probe_ack, UInt<1>(0h0)) node _T_710 = and(_T_708, _T_709) when _T_710 : node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_712 = or(_T_711, _WIRE_23.ready) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_119 node _T_716 = orr(inflight_1) node _T_717 = eq(_T_716, UInt<1>(0h0)) node _T_718 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_719 = or(_T_717, _T_718) node _T_720 = lt(watchdog_1, plusarg_reader_1.out) node _T_721 = or(_T_719, _T_720) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_721, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_725 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_726 = and(io.in.d.ready, io.in.d.valid) node _T_727 = or(_T_725, _T_726) when _T_727 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_58( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [8255:0] _inflight_opcodes_T_4 = 8256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [8255:0] _inflight_sizes_T_4 = 8256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [2063:0] _inflight_T_4 = 2064'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [8255:0] d_opcodes_clr_1 = 8256'h0; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1 = 8256'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2063:0] d_clr_1 = 2064'h0; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1 = 2064'h0; // @[Monitor.scala:775:34] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_659; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_592 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_4 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_605 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_12 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_21 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_12( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_21 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_Registered : output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut.sync, nodeIn	module IntSyncCrossingSource_n1x1_Registered(); // @[Crossing.scala:48:9] wire auto_in_0 = 1'h0; // @[Crossing.scala:48:9] wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:48:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_263 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_487 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_263( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_487 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BeatMerger : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { shift : UInt<6>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<8>, len : UInt<16>, block_stride : UInt<16>, spad_row_offset : UInt<9>, lg_len_req : UInt<3>, bytes_to_read : UInt<7>, cmd_id : UInt<3>}}, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<128>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<512>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, mask : UInt<1>[64], last : UInt<1>}}} reg req : { valid : UInt<1>, bits : { shift : UInt<6>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<8>, len : UInt<16>, block_stride : UInt<16>, spad_row_offset : UInt<9>, lg_len_req : UInt<3>, bytes_to_read : UInt<7>, cmd_id : UInt<3>}}, clock reg buffer : UInt<512>, clock node rowBytes = mux(req.bits.has_acc_bitwidth, UInt<7>(0h40), UInt<5>(0h10)) reg bytesSent : UInt<7>, clock reg bytesRead : UInt<7>, clock node _bytesReadAfterShift_T = gt(bytesRead, req.bits.shift) node _bytesReadAfterShift_T_1 = sub(bytesRead, req.bits.shift) node _bytesReadAfterShift_T_2 = tail(_bytesReadAfterShift_T_1, 1) node bytesReadAfterShift = mux(_bytesReadAfterShift_T, _bytesReadAfterShift_T_2, UInt<1>(0h0)) node _bytesDiscarded_T = sub(bytesRead, bytesReadAfterShift) node bytesDiscarded = tail(_bytesDiscarded_T, 1) node _usefulBytesRead_T = lt(bytesReadAfterShift, req.bits.bytes_to_read) node usefulBytesRead = mux(_usefulBytesRead_T, bytesReadAfterShift, req.bits.bytes_to_read) node _bytesSent_next_spad_row_offset_T = eq(bytesSent, UInt<1>(0h0)) node bytesSent_next_spad_row_offset = mux(_bytesSent_next_spad_row_offset_T, req.bits.spad_row_offset, UInt<1>(0h0)) node _bytesSent_next_T = sub(rowBytes, bytesSent_next_spad_row_offset) node _bytesSent_next_T_1 = tail(_bytesSent_next_T, 1) node _bytesSent_next_T_2 = add(bytesSent, _bytesSent_next_T_1) node _bytesSent_next_T_3 = gt(_bytesSent_next_T_2, req.bits.bytes_to_read) node _bytesSent_next_T_4 = add(bytesSent, _bytesSent_next_T_1) node _bytesSent_next_T_5 = tail(_bytesSent_next_T_4, 1) node bytesSent_next = mux(_bytesSent_next_T_3, req.bits.bytes_to_read, _bytesSent_next_T_5) node last_sending = eq(bytesSent_next, req.bits.bytes_to_read) node _last_reading_T = dshl(UInt<1>(0h1), req.bits.lg_len_req) node _last_reading_T_1 = sub(_last_reading_T, bytesRead) node _last_reading_T_2 = tail(_last_reading_T_1, 1) node last_reading = geq(UInt<5>(0h10), _last_reading_T_2) node _io_req_ready_T = eq(req.valid, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _io_in_ready_T = and(io.req.ready, io.req.valid) node _io_in_ready_T_1 = dshl(UInt<1>(0h1), req.bits.lg_len_req) node _io_in_ready_T_2 = neq(bytesRead, _io_in_ready_T_1) node _io_in_ready_T_3 = and(req.valid, _io_in_ready_T_2) node _io_in_ready_T_4 = or(_io_in_ready_T, _io_in_ready_T_3) connect io.in.ready, _io_in_ready_T_4 node _io_out_valid_T = gt(usefulBytesRead, bytesSent) node _io_out_valid_T_1 = and(req.valid, _io_out_valid_T) node _io_out_valid_T_2 = sub(usefulBytesRead, bytesSent) node _io_out_valid_T_3 = tail(_io_out_valid_T_2, 1) node _io_out_valid_T_4 = geq(_io_out_valid_T_3, rowBytes) node _io_out_valid_T_5 = eq(usefulBytesRead, req.bits.bytes_to_read) node _io_out_valid_T_6 = or(_io_out_valid_T_4, _io_out_valid_T_5) node _io_out_valid_T_7 = and(_io_out_valid_T_1, _io_out_valid_T_6) connect io.out.valid, _io_out_valid_T_7 node _io_out_bits_data_T = mul(bytesSent, UInt<4>(0h8)) node _io_out_bits_data_T_1 = dshr(buffer, _io_out_bits_data_T) node _io_out_bits_data_T_2 = eq(bytesSent, UInt<1>(0h0)) node _io_out_bits_data_T_3 = mul(req.bits.spad_row_offset, UInt<4>(0h8)) node _io_out_bits_data_T_4 = mux(_io_out_bits_data_T_2, _io_out_bits_data_T_3, UInt<1>(0h0)) node _io_out_bits_data_T_5 = dshl(_io_out_bits_data_T_1, _io_out_bits_data_T_4) connect io.out.bits.data, _io_out_bits_data_T_5 node _spad_row_offset_T = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset = mux(_spad_row_offset_T, req.bits.spad_row_offset, UInt<1>(0h0)) node _T = geq(UInt<1>(0h0), spad_row_offset) node _T_1 = sub(req.bits.bytes_to_read, bytesSent) node _T_2 = tail(_T_1, 1) node _T_3 = add(spad_row_offset, _T_2) node _T_4 = lt(UInt<1>(0h0), _T_3) node _T_5 = and(_T, _T_4) node _spad_row_offset_T_1 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_1 = mux(_spad_row_offset_T_1, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_6 = geq(UInt<1>(0h1), spad_row_offset_1) node _T_7 = sub(req.bits.bytes_to_read, bytesSent) node _T_8 = tail(_T_7, 1) node _T_9 = add(spad_row_offset_1, _T_8) node _T_10 = lt(UInt<1>(0h1), _T_9) node _T_11 = and(_T_6, _T_10) node _spad_row_offset_T_2 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_2 = mux(_spad_row_offset_T_2, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_12 = geq(UInt<2>(0h2), spad_row_offset_2) node _T_13 = sub(req.bits.bytes_to_read, bytesSent) node _T_14 = tail(_T_13, 1) node _T_15 = add(spad_row_offset_2, _T_14) node _T_16 = lt(UInt<2>(0h2), _T_15) node _T_17 = and(_T_12, _T_16) node _spad_row_offset_T_3 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_3 = mux(_spad_row_offset_T_3, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_18 = geq(UInt<2>(0h3), spad_row_offset_3) node _T_19 = sub(req.bits.bytes_to_read, bytesSent) node _T_20 = tail(_T_19, 1) node _T_21 = add(spad_row_offset_3, _T_20) node _T_22 = lt(UInt<2>(0h3), _T_21) node _T_23 = and(_T_18, _T_22) node _spad_row_offset_T_4 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_4 = mux(_spad_row_offset_T_4, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_24 = geq(UInt<3>(0h4), spad_row_offset_4) node _T_25 = sub(req.bits.bytes_to_read, bytesSent) node _T_26 = tail(_T_25, 1) node _T_27 = add(spad_row_offset_4, _T_26) node _T_28 = lt(UInt<3>(0h4), _T_27) node _T_29 = and(_T_24, _T_28) node _spad_row_offset_T_5 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_5 = mux(_spad_row_offset_T_5, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_30 = geq(UInt<3>(0h5), spad_row_offset_5) node _T_31 = sub(req.bits.bytes_to_read, bytesSent) node _T_32 = tail(_T_31, 1) node _T_33 = add(spad_row_offset_5, _T_32) node _T_34 = lt(UInt<3>(0h5), _T_33) node _T_35 = and(_T_30, _T_34) node _spad_row_offset_T_6 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_6 = mux(_spad_row_offset_T_6, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_36 = geq(UInt<3>(0h6), spad_row_offset_6) node _T_37 = sub(req.bits.bytes_to_read, bytesSent) node _T_38 = tail(_T_37, 1) node _T_39 = add(spad_row_offset_6, _T_38) node _T_40 = lt(UInt<3>(0h6), _T_39) node _T_41 = and(_T_36, _T_40) node _spad_row_offset_T_7 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_7 = mux(_spad_row_offset_T_7, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_42 = geq(UInt<3>(0h7), spad_row_offset_7) node _T_43 = sub(req.bits.bytes_to_read, bytesSent) node _T_44 = tail(_T_43, 1) node _T_45 = add(spad_row_offset_7, _T_44) node _T_46 = lt(UInt<3>(0h7), _T_45) node _T_47 = and(_T_42, _T_46) node _spad_row_offset_T_8 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_8 = mux(_spad_row_offset_T_8, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_48 = geq(UInt<4>(0h8), spad_row_offset_8) node _T_49 = sub(req.bits.bytes_to_read, bytesSent) node _T_50 = tail(_T_49, 1) node _T_51 = add(spad_row_offset_8, _T_50) node _T_52 = lt(UInt<4>(0h8), _T_51) node _T_53 = and(_T_48, _T_52) node _spad_row_offset_T_9 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_9 = mux(_spad_row_offset_T_9, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_54 = geq(UInt<4>(0h9), spad_row_offset_9) node _T_55 = sub(req.bits.bytes_to_read, bytesSent) node _T_56 = tail(_T_55, 1) node _T_57 = add(spad_row_offset_9, _T_56) node _T_58 = lt(UInt<4>(0h9), _T_57) node _T_59 = and(_T_54, _T_58) node _spad_row_offset_T_10 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_10 = mux(_spad_row_offset_T_10, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_60 = geq(UInt<4>(0ha), spad_row_offset_10) node _T_61 = sub(req.bits.bytes_to_read, bytesSent) node _T_62 = tail(_T_61, 1) node _T_63 = add(spad_row_offset_10, _T_62) node _T_64 = lt(UInt<4>(0ha), _T_63) node _T_65 = and(_T_60, _T_64) node _spad_row_offset_T_11 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_11 = mux(_spad_row_offset_T_11, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_66 = geq(UInt<4>(0hb), spad_row_offset_11) node _T_67 = sub(req.bits.bytes_to_read, bytesSent) node _T_68 = tail(_T_67, 1) node _T_69 = add(spad_row_offset_11, _T_68) node _T_70 = lt(UInt<4>(0hb), _T_69) node _T_71 = and(_T_66, _T_70) node _spad_row_offset_T_12 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_12 = mux(_spad_row_offset_T_12, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_72 = geq(UInt<4>(0hc), spad_row_offset_12) node _T_73 = sub(req.bits.bytes_to_read, bytesSent) node _T_74 = tail(_T_73, 1) node _T_75 = add(spad_row_offset_12, _T_74) node _T_76 = lt(UInt<4>(0hc), _T_75) node _T_77 = and(_T_72, _T_76) node _spad_row_offset_T_13 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_13 = mux(_spad_row_offset_T_13, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_78 = geq(UInt<4>(0hd), spad_row_offset_13) node _T_79 = sub(req.bits.bytes_to_read, bytesSent) node _T_80 = tail(_T_79, 1) node _T_81 = add(spad_row_offset_13, _T_80) node _T_82 = lt(UInt<4>(0hd), _T_81) node _T_83 = and(_T_78, _T_82) node _spad_row_offset_T_14 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_14 = mux(_spad_row_offset_T_14, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_84 = geq(UInt<4>(0he), spad_row_offset_14) node _T_85 = sub(req.bits.bytes_to_read, bytesSent) node _T_86 = tail(_T_85, 1) node _T_87 = add(spad_row_offset_14, _T_86) node _T_88 = lt(UInt<4>(0he), _T_87) node _T_89 = and(_T_84, _T_88) node _spad_row_offset_T_15 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_15 = mux(_spad_row_offset_T_15, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_90 = geq(UInt<4>(0hf), spad_row_offset_15) node _T_91 = sub(req.bits.bytes_to_read, bytesSent) node _T_92 = tail(_T_91, 1) node _T_93 = add(spad_row_offset_15, _T_92) node _T_94 = lt(UInt<4>(0hf), _T_93) node _T_95 = and(_T_90, _T_94) node _spad_row_offset_T_16 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_16 = mux(_spad_row_offset_T_16, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_96 = geq(UInt<5>(0h10), spad_row_offset_16) node _T_97 = sub(req.bits.bytes_to_read, bytesSent) node _T_98 = tail(_T_97, 1) node _T_99 = add(spad_row_offset_16, _T_98) node _T_100 = lt(UInt<5>(0h10), _T_99) node _T_101 = and(_T_96, _T_100) node _spad_row_offset_T_17 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_17 = mux(_spad_row_offset_T_17, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_102 = geq(UInt<5>(0h11), spad_row_offset_17) node _T_103 = sub(req.bits.bytes_to_read, bytesSent) node _T_104 = tail(_T_103, 1) node _T_105 = add(spad_row_offset_17, _T_104) node _T_106 = lt(UInt<5>(0h11), _T_105) node _T_107 = and(_T_102, _T_106) node _spad_row_offset_T_18 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_18 = mux(_spad_row_offset_T_18, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_108 = geq(UInt<5>(0h12), spad_row_offset_18) node _T_109 = sub(req.bits.bytes_to_read, bytesSent) node _T_110 = tail(_T_109, 1) node _T_111 = add(spad_row_offset_18, _T_110) node _T_112 = lt(UInt<5>(0h12), _T_111) node _T_113 = and(_T_108, _T_112) node _spad_row_offset_T_19 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_19 = mux(_spad_row_offset_T_19, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_114 = geq(UInt<5>(0h13), spad_row_offset_19) node _T_115 = sub(req.bits.bytes_to_read, bytesSent) node _T_116 = tail(_T_115, 1) node _T_117 = add(spad_row_offset_19, _T_116) node _T_118 = lt(UInt<5>(0h13), _T_117) node _T_119 = and(_T_114, _T_118) node _spad_row_offset_T_20 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_20 = mux(_spad_row_offset_T_20, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_120 = geq(UInt<5>(0h14), spad_row_offset_20) node _T_121 = sub(req.bits.bytes_to_read, bytesSent) node _T_122 = tail(_T_121, 1) node _T_123 = add(spad_row_offset_20, _T_122) node _T_124 = lt(UInt<5>(0h14), _T_123) node _T_125 = and(_T_120, _T_124) node _spad_row_offset_T_21 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_21 = mux(_spad_row_offset_T_21, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_126 = geq(UInt<5>(0h15), spad_row_offset_21) node _T_127 = sub(req.bits.bytes_to_read, bytesSent) node _T_128 = tail(_T_127, 1) node _T_129 = add(spad_row_offset_21, _T_128) node _T_130 = lt(UInt<5>(0h15), _T_129) node _T_131 = and(_T_126, _T_130) node _spad_row_offset_T_22 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_22 = mux(_spad_row_offset_T_22, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_132 = geq(UInt<5>(0h16), spad_row_offset_22) node _T_133 = sub(req.bits.bytes_to_read, bytesSent) node _T_134 = tail(_T_133, 1) node _T_135 = add(spad_row_offset_22, _T_134) node _T_136 = lt(UInt<5>(0h16), _T_135) node _T_137 = and(_T_132, _T_136) node _spad_row_offset_T_23 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_23 = mux(_spad_row_offset_T_23, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_138 = geq(UInt<5>(0h17), spad_row_offset_23) node _T_139 = sub(req.bits.bytes_to_read, bytesSent) node _T_140 = tail(_T_139, 1) node _T_141 = add(spad_row_offset_23, _T_140) node _T_142 = lt(UInt<5>(0h17), _T_141) node _T_143 = and(_T_138, _T_142) node _spad_row_offset_T_24 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_24 = mux(_spad_row_offset_T_24, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_144 = geq(UInt<5>(0h18), spad_row_offset_24) node _T_145 = sub(req.bits.bytes_to_read, bytesSent) node _T_146 = tail(_T_145, 1) node _T_147 = add(spad_row_offset_24, _T_146) node _T_148 = lt(UInt<5>(0h18), _T_147) node _T_149 = and(_T_144, _T_148) node _spad_row_offset_T_25 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_25 = mux(_spad_row_offset_T_25, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_150 = geq(UInt<5>(0h19), spad_row_offset_25) node _T_151 = sub(req.bits.bytes_to_read, bytesSent) node _T_152 = tail(_T_151, 1) node _T_153 = add(spad_row_offset_25, _T_152) node _T_154 = lt(UInt<5>(0h19), _T_153) node _T_155 = and(_T_150, _T_154) node _spad_row_offset_T_26 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_26 = mux(_spad_row_offset_T_26, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_156 = geq(UInt<5>(0h1a), spad_row_offset_26) node _T_157 = sub(req.bits.bytes_to_read, bytesSent) node _T_158 = tail(_T_157, 1) node _T_159 = add(spad_row_offset_26, _T_158) node _T_160 = lt(UInt<5>(0h1a), _T_159) node _T_161 = and(_T_156, _T_160) node _spad_row_offset_T_27 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_27 = mux(_spad_row_offset_T_27, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_162 = geq(UInt<5>(0h1b), spad_row_offset_27) node _T_163 = sub(req.bits.bytes_to_read, bytesSent) node _T_164 = tail(_T_163, 1) node _T_165 = add(spad_row_offset_27, _T_164) node _T_166 = lt(UInt<5>(0h1b), _T_165) node _T_167 = and(_T_162, _T_166) node _spad_row_offset_T_28 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_28 = mux(_spad_row_offset_T_28, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_168 = geq(UInt<5>(0h1c), spad_row_offset_28) node _T_169 = sub(req.bits.bytes_to_read, bytesSent) node _T_170 = tail(_T_169, 1) node _T_171 = add(spad_row_offset_28, _T_170) node _T_172 = lt(UInt<5>(0h1c), _T_171) node _T_173 = and(_T_168, _T_172) node _spad_row_offset_T_29 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_29 = mux(_spad_row_offset_T_29, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_174 = geq(UInt<5>(0h1d), spad_row_offset_29) node _T_175 = sub(req.bits.bytes_to_read, bytesSent) node _T_176 = tail(_T_175, 1) node _T_177 = add(spad_row_offset_29, _T_176) node _T_178 = lt(UInt<5>(0h1d), _T_177) node _T_179 = and(_T_174, _T_178) node _spad_row_offset_T_30 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_30 = mux(_spad_row_offset_T_30, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_180 = geq(UInt<5>(0h1e), spad_row_offset_30) node _T_181 = sub(req.bits.bytes_to_read, bytesSent) node _T_182 = tail(_T_181, 1) node _T_183 = add(spad_row_offset_30, _T_182) node _T_184 = lt(UInt<5>(0h1e), _T_183) node _T_185 = and(_T_180, _T_184) node _spad_row_offset_T_31 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_31 = mux(_spad_row_offset_T_31, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_186 = geq(UInt<5>(0h1f), spad_row_offset_31) node _T_187 = sub(req.bits.bytes_to_read, bytesSent) node _T_188 = tail(_T_187, 1) node _T_189 = add(spad_row_offset_31, _T_188) node _T_190 = lt(UInt<5>(0h1f), _T_189) node _T_191 = and(_T_186, _T_190) node _spad_row_offset_T_32 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_32 = mux(_spad_row_offset_T_32, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_192 = geq(UInt<6>(0h20), spad_row_offset_32) node _T_193 = sub(req.bits.bytes_to_read, bytesSent) node _T_194 = tail(_T_193, 1) node _T_195 = add(spad_row_offset_32, _T_194) node _T_196 = lt(UInt<6>(0h20), _T_195) node _T_197 = and(_T_192, _T_196) node _spad_row_offset_T_33 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_33 = mux(_spad_row_offset_T_33, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_198 = geq(UInt<6>(0h21), spad_row_offset_33) node _T_199 = sub(req.bits.bytes_to_read, bytesSent) node _T_200 = tail(_T_199, 1) node _T_201 = add(spad_row_offset_33, _T_200) node _T_202 = lt(UInt<6>(0h21), _T_201) node _T_203 = and(_T_198, _T_202) node _spad_row_offset_T_34 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_34 = mux(_spad_row_offset_T_34, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_204 = geq(UInt<6>(0h22), spad_row_offset_34) node _T_205 = sub(req.bits.bytes_to_read, bytesSent) node _T_206 = tail(_T_205, 1) node _T_207 = add(spad_row_offset_34, _T_206) node _T_208 = lt(UInt<6>(0h22), _T_207) node _T_209 = and(_T_204, _T_208) node _spad_row_offset_T_35 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_35 = mux(_spad_row_offset_T_35, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_210 = geq(UInt<6>(0h23), spad_row_offset_35) node _T_211 = sub(req.bits.bytes_to_read, bytesSent) node _T_212 = tail(_T_211, 1) node _T_213 = add(spad_row_offset_35, _T_212) node _T_214 = lt(UInt<6>(0h23), _T_213) node _T_215 = and(_T_210, _T_214) node _spad_row_offset_T_36 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_36 = mux(_spad_row_offset_T_36, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_216 = geq(UInt<6>(0h24), spad_row_offset_36) node _T_217 = sub(req.bits.bytes_to_read, bytesSent) node _T_218 = tail(_T_217, 1) node _T_219 = add(spad_row_offset_36, _T_218) node _T_220 = lt(UInt<6>(0h24), _T_219) node _T_221 = and(_T_216, _T_220) node _spad_row_offset_T_37 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_37 = mux(_spad_row_offset_T_37, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_222 = geq(UInt<6>(0h25), spad_row_offset_37) node _T_223 = sub(req.bits.bytes_to_read, bytesSent) node _T_224 = tail(_T_223, 1) node _T_225 = add(spad_row_offset_37, _T_224) node _T_226 = lt(UInt<6>(0h25), _T_225) node _T_227 = and(_T_222, _T_226) node _spad_row_offset_T_38 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_38 = mux(_spad_row_offset_T_38, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_228 = geq(UInt<6>(0h26), spad_row_offset_38) node _T_229 = sub(req.bits.bytes_to_read, bytesSent) node _T_230 = tail(_T_229, 1) node _T_231 = add(spad_row_offset_38, _T_230) node _T_232 = lt(UInt<6>(0h26), _T_231) node _T_233 = and(_T_228, _T_232) node _spad_row_offset_T_39 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_39 = mux(_spad_row_offset_T_39, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_234 = geq(UInt<6>(0h27), spad_row_offset_39) node _T_235 = sub(req.bits.bytes_to_read, bytesSent) node _T_236 = tail(_T_235, 1) node _T_237 = add(spad_row_offset_39, _T_236) node _T_238 = lt(UInt<6>(0h27), _T_237) node _T_239 = and(_T_234, _T_238) node _spad_row_offset_T_40 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_40 = mux(_spad_row_offset_T_40, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_240 = geq(UInt<6>(0h28), spad_row_offset_40) node _T_241 = sub(req.bits.bytes_to_read, bytesSent) node _T_242 = tail(_T_241, 1) node _T_243 = add(spad_row_offset_40, _T_242) node _T_244 = lt(UInt<6>(0h28), _T_243) node _T_245 = and(_T_240, _T_244) node _spad_row_offset_T_41 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_41 = mux(_spad_row_offset_T_41, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_246 = geq(UInt<6>(0h29), spad_row_offset_41) node _T_247 = sub(req.bits.bytes_to_read, bytesSent) node _T_248 = tail(_T_247, 1) node _T_249 = add(spad_row_offset_41, _T_248) node _T_250 = lt(UInt<6>(0h29), _T_249) node _T_251 = and(_T_246, _T_250) node _spad_row_offset_T_42 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_42 = mux(_spad_row_offset_T_42, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_252 = geq(UInt<6>(0h2a), spad_row_offset_42) node _T_253 = sub(req.bits.bytes_to_read, bytesSent) node _T_254 = tail(_T_253, 1) node _T_255 = add(spad_row_offset_42, _T_254) node _T_256 = lt(UInt<6>(0h2a), _T_255) node _T_257 = and(_T_252, _T_256) node _spad_row_offset_T_43 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_43 = mux(_spad_row_offset_T_43, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_258 = geq(UInt<6>(0h2b), spad_row_offset_43) node _T_259 = sub(req.bits.bytes_to_read, bytesSent) node _T_260 = tail(_T_259, 1) node _T_261 = add(spad_row_offset_43, _T_260) node _T_262 = lt(UInt<6>(0h2b), _T_261) node _T_263 = and(_T_258, _T_262) node _spad_row_offset_T_44 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_44 = mux(_spad_row_offset_T_44, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_264 = geq(UInt<6>(0h2c), spad_row_offset_44) node _T_265 = sub(req.bits.bytes_to_read, bytesSent) node _T_266 = tail(_T_265, 1) node _T_267 = add(spad_row_offset_44, _T_266) node _T_268 = lt(UInt<6>(0h2c), _T_267) node _T_269 = and(_T_264, _T_268) node _spad_row_offset_T_45 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_45 = mux(_spad_row_offset_T_45, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_270 = geq(UInt<6>(0h2d), spad_row_offset_45) node _T_271 = sub(req.bits.bytes_to_read, bytesSent) node _T_272 = tail(_T_271, 1) node _T_273 = add(spad_row_offset_45, _T_272) node _T_274 = lt(UInt<6>(0h2d), _T_273) node _T_275 = and(_T_270, _T_274) node _spad_row_offset_T_46 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_46 = mux(_spad_row_offset_T_46, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_276 = geq(UInt<6>(0h2e), spad_row_offset_46) node _T_277 = sub(req.bits.bytes_to_read, bytesSent) node _T_278 = tail(_T_277, 1) node _T_279 = add(spad_row_offset_46, _T_278) node _T_280 = lt(UInt<6>(0h2e), _T_279) node _T_281 = and(_T_276, _T_280) node _spad_row_offset_T_47 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_47 = mux(_spad_row_offset_T_47, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_282 = geq(UInt<6>(0h2f), spad_row_offset_47) node _T_283 = sub(req.bits.bytes_to_read, bytesSent) node _T_284 = tail(_T_283, 1) node _T_285 = add(spad_row_offset_47, _T_284) node _T_286 = lt(UInt<6>(0h2f), _T_285) node _T_287 = and(_T_282, _T_286) node _spad_row_offset_T_48 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_48 = mux(_spad_row_offset_T_48, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_288 = geq(UInt<6>(0h30), spad_row_offset_48) node _T_289 = sub(req.bits.bytes_to_read, bytesSent) node _T_290 = tail(_T_289, 1) node _T_291 = add(spad_row_offset_48, _T_290) node _T_292 = lt(UInt<6>(0h30), _T_291) node _T_293 = and(_T_288, _T_292) node _spad_row_offset_T_49 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_49 = mux(_spad_row_offset_T_49, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_294 = geq(UInt<6>(0h31), spad_row_offset_49) node _T_295 = sub(req.bits.bytes_to_read, bytesSent) node _T_296 = tail(_T_295, 1) node _T_297 = add(spad_row_offset_49, _T_296) node _T_298 = lt(UInt<6>(0h31), _T_297) node _T_299 = and(_T_294, _T_298) node _spad_row_offset_T_50 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_50 = mux(_spad_row_offset_T_50, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_300 = geq(UInt<6>(0h32), spad_row_offset_50) node _T_301 = sub(req.bits.bytes_to_read, bytesSent) node _T_302 = tail(_T_301, 1) node _T_303 = add(spad_row_offset_50, _T_302) node _T_304 = lt(UInt<6>(0h32), _T_303) node _T_305 = and(_T_300, _T_304) node _spad_row_offset_T_51 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_51 = mux(_spad_row_offset_T_51, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_306 = geq(UInt<6>(0h33), spad_row_offset_51) node _T_307 = sub(req.bits.bytes_to_read, bytesSent) node _T_308 = tail(_T_307, 1) node _T_309 = add(spad_row_offset_51, _T_308) node _T_310 = lt(UInt<6>(0h33), _T_309) node _T_311 = and(_T_306, _T_310) node _spad_row_offset_T_52 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_52 = mux(_spad_row_offset_T_52, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_312 = geq(UInt<6>(0h34), spad_row_offset_52) node _T_313 = sub(req.bits.bytes_to_read, bytesSent) node _T_314 = tail(_T_313, 1) node _T_315 = add(spad_row_offset_52, _T_314) node _T_316 = lt(UInt<6>(0h34), _T_315) node _T_317 = and(_T_312, _T_316) node _spad_row_offset_T_53 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_53 = mux(_spad_row_offset_T_53, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_318 = geq(UInt<6>(0h35), spad_row_offset_53) node _T_319 = sub(req.bits.bytes_to_read, bytesSent) node _T_320 = tail(_T_319, 1) node _T_321 = add(spad_row_offset_53, _T_320) node _T_322 = lt(UInt<6>(0h35), _T_321) node _T_323 = and(_T_318, _T_322) node _spad_row_offset_T_54 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_54 = mux(_spad_row_offset_T_54, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_324 = geq(UInt<6>(0h36), spad_row_offset_54) node _T_325 = sub(req.bits.bytes_to_read, bytesSent) node _T_326 = tail(_T_325, 1) node _T_327 = add(spad_row_offset_54, _T_326) node _T_328 = lt(UInt<6>(0h36), _T_327) node _T_329 = and(_T_324, _T_328) node _spad_row_offset_T_55 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_55 = mux(_spad_row_offset_T_55, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_330 = geq(UInt<6>(0h37), spad_row_offset_55) node _T_331 = sub(req.bits.bytes_to_read, bytesSent) node _T_332 = tail(_T_331, 1) node _T_333 = add(spad_row_offset_55, _T_332) node _T_334 = lt(UInt<6>(0h37), _T_333) node _T_335 = and(_T_330, _T_334) node _spad_row_offset_T_56 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_56 = mux(_spad_row_offset_T_56, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_336 = geq(UInt<6>(0h38), spad_row_offset_56) node _T_337 = sub(req.bits.bytes_to_read, bytesSent) node _T_338 = tail(_T_337, 1) node _T_339 = add(spad_row_offset_56, _T_338) node _T_340 = lt(UInt<6>(0h38), _T_339) node _T_341 = and(_T_336, _T_340) node _spad_row_offset_T_57 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_57 = mux(_spad_row_offset_T_57, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_342 = geq(UInt<6>(0h39), spad_row_offset_57) node _T_343 = sub(req.bits.bytes_to_read, bytesSent) node _T_344 = tail(_T_343, 1) node _T_345 = add(spad_row_offset_57, _T_344) node _T_346 = lt(UInt<6>(0h39), _T_345) node _T_347 = and(_T_342, _T_346) node _spad_row_offset_T_58 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_58 = mux(_spad_row_offset_T_58, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_348 = geq(UInt<6>(0h3a), spad_row_offset_58) node _T_349 = sub(req.bits.bytes_to_read, bytesSent) node _T_350 = tail(_T_349, 1) node _T_351 = add(spad_row_offset_58, _T_350) node _T_352 = lt(UInt<6>(0h3a), _T_351) node _T_353 = and(_T_348, _T_352) node _spad_row_offset_T_59 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_59 = mux(_spad_row_offset_T_59, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_354 = geq(UInt<6>(0h3b), spad_row_offset_59) node _T_355 = sub(req.bits.bytes_to_read, bytesSent) node _T_356 = tail(_T_355, 1) node _T_357 = add(spad_row_offset_59, _T_356) node _T_358 = lt(UInt<6>(0h3b), _T_357) node _T_359 = and(_T_354, _T_358) node _spad_row_offset_T_60 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_60 = mux(_spad_row_offset_T_60, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_360 = geq(UInt<6>(0h3c), spad_row_offset_60) node _T_361 = sub(req.bits.bytes_to_read, bytesSent) node _T_362 = tail(_T_361, 1) node _T_363 = add(spad_row_offset_60, _T_362) node _T_364 = lt(UInt<6>(0h3c), _T_363) node _T_365 = and(_T_360, _T_364) node _spad_row_offset_T_61 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_61 = mux(_spad_row_offset_T_61, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_366 = geq(UInt<6>(0h3d), spad_row_offset_61) node _T_367 = sub(req.bits.bytes_to_read, bytesSent) node _T_368 = tail(_T_367, 1) node _T_369 = add(spad_row_offset_61, _T_368) node _T_370 = lt(UInt<6>(0h3d), _T_369) node _T_371 = and(_T_366, _T_370) node _spad_row_offset_T_62 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_62 = mux(_spad_row_offset_T_62, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_372 = geq(UInt<6>(0h3e), spad_row_offset_62) node _T_373 = sub(req.bits.bytes_to_read, bytesSent) node _T_374 = tail(_T_373, 1) node _T_375 = add(spad_row_offset_62, _T_374) node _T_376 = lt(UInt<6>(0h3e), _T_375) node _T_377 = and(_T_372, _T_376) node _spad_row_offset_T_63 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_63 = mux(_spad_row_offset_T_63, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_378 = geq(UInt<6>(0h3f), spad_row_offset_63) node _T_379 = sub(req.bits.bytes_to_read, bytesSent) node _T_380 = tail(_T_379, 1) node _T_381 = add(spad_row_offset_63, _T_380) node _T_382 = lt(UInt<6>(0h3f), _T_381) node _T_383 = and(_T_378, _T_382) wire _WIRE : UInt<1>[64] connect _WIRE[0], _T_5 connect _WIRE[1], _T_11 connect _WIRE[2], _T_17 connect _WIRE[3], _T_23 connect _WIRE[4], _T_29 connect _WIRE[5], _T_35 connect _WIRE[6], _T_41 connect _WIRE[7], _T_47 connect _WIRE[8], _T_53 connect _WIRE[9], _T_59 connect _WIRE[10], _T_65 connect _WIRE[11], _T_71 connect _WIRE[12], _T_77 connect _WIRE[13], _T_83 connect _WIRE[14], _T_89 connect _WIRE[15], _T_95 connect _WIRE[16], _T_101 connect _WIRE[17], _T_107 connect _WIRE[18], _T_113 connect _WIRE[19], _T_119 connect _WIRE[20], _T_125 connect _WIRE[21], _T_131 connect _WIRE[22], _T_137 connect _WIRE[23], _T_143 connect _WIRE[24], _T_149 connect _WIRE[25], _T_155 connect _WIRE[26], _T_161 connect _WIRE[27], _T_167 connect _WIRE[28], _T_173 connect _WIRE[29], _T_179 connect _WIRE[30], _T_185 connect _WIRE[31], _T_191 connect _WIRE[32], _T_197 connect _WIRE[33], _T_203 connect _WIRE[34], _T_209 connect _WIRE[35], _T_215 connect _WIRE[36], _T_221 connect _WIRE[37], _T_227 connect _WIRE[38], _T_233 connect _WIRE[39], _T_239 connect _WIRE[40], _T_245 connect _WIRE[41], _T_251 connect _WIRE[42], _T_257 connect _WIRE[43], _T_263 connect _WIRE[44], _T_269 connect _WIRE[45], _T_275 connect _WIRE[46], _T_281 connect _WIRE[47], _T_287 connect _WIRE[48], _T_293 connect _WIRE[49], _T_299 connect _WIRE[50], _T_305 connect _WIRE[51], _T_311 connect _WIRE[52], _T_317 connect _WIRE[53], _T_323 connect _WIRE[54], _T_329 connect _WIRE[55], _T_335 connect _WIRE[56], _T_341 connect _WIRE[57], _T_347 connect _WIRE[58], _T_353 connect _WIRE[59], _T_359 connect _WIRE[60], _T_365 connect _WIRE[61], _T_371 connect _WIRE[62], _T_377 connect _WIRE[63], _T_383 connect io.out.bits.mask, _WIRE node _io_out_bits_addr_total_bytes_sent_T = add(req.bits.spad_row_offset, bytesSent) node io_out_bits_addr_total_bytes_sent = tail(_io_out_bits_addr_total_bytes_sent_T, 1) node _io_out_bits_addr_T = div(io_out_bits_addr_total_bytes_sent, UInt<9>(0h40)) node _io_out_bits_addr_T_1 = div(io_out_bits_addr_total_bytes_sent, UInt<9>(0h10)) node _io_out_bits_addr_T_2 = mux(req.bits.has_acc_bitwidth, _io_out_bits_addr_T, _io_out_bits_addr_T_1) node _io_out_bits_addr_T_3 = mul(req.bits.block_stride, _io_out_bits_addr_T_2) node _io_out_bits_addr_T_4 = add(req.bits.addr, _io_out_bits_addr_T_3) node _io_out_bits_addr_T_5 = tail(_io_out_bits_addr_T_4, 1) connect io.out.bits.addr, _io_out_bits_addr_T_5 connect io.out.bits.is_acc, req.bits.is_acc connect io.out.bits.accumulate, req.bits.accumulate connect io.out.bits.has_acc_bitwidth, req.bits.has_acc_bitwidth connect io.out.bits.last, last_sending connect io.out.bits.accumulate, req.bits.accumulate connect io.out.bits.has_acc_bitwidth, req.bits.has_acc_bitwidth node _T_384 = dshl(UInt<1>(0h1), req.bits.lg_len_req) node _T_385 = eq(bytesRead, _T_384) node _T_386 = eq(bytesSent, req.bits.bytes_to_read) node _T_387 = and(_T_385, _T_386) when _T_387 : connect req.valid, UInt<1>(0h0) node _T_388 = and(io.out.ready, io.out.valid) when _T_388 : connect bytesSent, bytesSent_next node _T_389 = dshl(UInt<1>(0h1), req.bits.lg_len_req) node _T_390 = eq(bytesRead, _T_389) node _T_391 = and(last_sending, _T_390) when _T_391 : connect req.valid, UInt<1>(0h0) connect io.req.ready, UInt<1>(0h1) node _T_392 = and(io.req.ready, io.req.valid) when _T_392 : connect req.valid, UInt<1>(0h1) connect req.bits, io.req.bits connect bytesRead, UInt<1>(0h0) connect bytesSent, UInt<1>(0h0) node _T_393 = and(io.in.ready, io.in.valid) when _T_393 : node _current_bytesRead_T = and(io.req.ready, io.req.valid) node current_bytesRead = mux(_current_bytesRead_T, UInt<1>(0h0), bytesRead) node _current_bytesDiscarded_T = and(io.req.ready, io.req.valid) node current_bytesDiscarded = mux(_current_bytesDiscarded_T, UInt<1>(0h0), bytesDiscarded) node _current_usefulBytesRead_T = and(io.req.ready, io.req.valid) node current_usefulBytesRead = mux(_current_usefulBytesRead_T, UInt<1>(0h0), usefulBytesRead) node _current_shift_T = and(io.req.ready, io.req.valid) node current_shift = mux(_current_shift_T, io.req.bits.shift, req.bits.shift) node _current_lg_len_req_T = and(io.req.ready, io.req.valid) node current_lg_len_req = mux(_current_lg_len_req_T, io.req.bits.lg_len_req, req.bits.lg_len_req) node current_len_req = dshl(UInt<1>(0h1), current_lg_len_req) node _T_394 = sub(current_shift, current_bytesDiscarded) node _T_395 = tail(_T_394, 1) node _T_396 = leq(_T_395, UInt<5>(0h10)) when _T_396 : node _rshift_T = sub(current_shift, current_bytesDiscarded) node _rshift_T_1 = tail(_rshift_T, 1) node rshift = mul(_rshift_T_1, UInt<4>(0h8)) node lshift = mul(current_usefulBytesRead, UInt<4>(0h8)) node _mask_T = not(UInt<128>(0h0)) node _mask_T_1 = dshr(_mask_T, rshift) node _mask_T_2 = dshl(_mask_T_1, lshift) node mask = not(_mask_T_2) node _buffer_T = and(buffer, mask) node _buffer_T_1 = dshr(io.in.bits, rshift) node _buffer_T_2 = dshl(_buffer_T_1, lshift) node _buffer_T_3 = or(_buffer_T, _buffer_T_2) connect buffer, _buffer_T_3 node _bytesRead_T = add(current_bytesRead, UInt<5>(0h10)) node _bytesRead_T_1 = gt(_bytesRead_T, current_len_req) node _bytesRead_T_2 = add(current_bytesRead, UInt<5>(0h10)) node _bytesRead_T_3 = tail(_bytesRead_T_2, 1) node _bytesRead_T_4 = mux(_bytesRead_T_1, current_len_req, _bytesRead_T_3) connect bytesRead, _bytesRead_T_4 node _T_397 = and(io.req.ready, io.req.valid) node _T_398 = eq(_T_397, UInt<1>(0h0)) node _T_399 = eq(bytesSent, req.bits.bytes_to_read) node _T_400 = and(_T_398, _T_399) node _T_401 = and(_T_400, last_reading) when _T_401 : connect req.valid, UInt<1>(0h0) node _T_402 = asUInt(reset) when _T_402 : connect req.valid, UInt<1>(0h0)	module BeatMerger( // @[BeatMerger.scala:30:7] input clock, // @[BeatMerger.scala:30:7] input reset, // @[BeatMerger.scala:30:7] output io_req_ready, // @[BeatMerger.scala:33:14] input io_req_valid, // @[BeatMerger.scala:33:14] input [5:0] io_req_bits_shift, // @[BeatMerger.scala:33:14] input [13:0] io_req_bits_addr, // @[BeatMerger.scala:33:14] input io_req_bits_is_acc, // @[BeatMerger.scala:33:14] input io_req_bits_accumulate, // @[BeatMerger.scala:33:14] input io_req_bits_has_acc_bitwidth, // @[BeatMerger.scala:33:14] input [31:0] io_req_bits_scale, // @[BeatMerger.scala:33:14] input [15:0] io_req_bits_repeats, // @[BeatMerger.scala:33:14] input [7:0] io_req_bits_pixel_repeats, // @[BeatMerger.scala:33:14] input [15:0] io_req_bits_len, // @[BeatMerger.scala:33:14] input [15:0] io_req_bits_block_stride, // @[BeatMerger.scala:33:14] input [8:0] io_req_bits_spad_row_offset, // @[BeatMerger.scala:33:14] input [2:0] io_req_bits_lg_len_req, // @[BeatMerger.scala:33:14] input [6:0] io_req_bits_bytes_to_read, // @[BeatMerger.scala:33:14] input [2:0] io_req_bits_cmd_id, // @[BeatMerger.scala:33:14] output io_in_ready, // @[BeatMerger.scala:33:14] input io_in_valid, // @[BeatMerger.scala:33:14] input [127:0] io_in_bits, // @[BeatMerger.scala:33:14] input io_out_ready, // @[BeatMerger.scala:33:14] output io_out_valid, // @[BeatMerger.scala:33:14] output [511:0] io_out_bits_data, // @[BeatMerger.scala:33:14] output [13:0] io_out_bits_addr, // @[BeatMerger.scala:33:14] output io_out_bits_is_acc, // @[BeatMerger.scala:33:14] output io_out_bits_accumulate, // @[BeatMerger.scala:33:14] output io_out_bits_has_acc_bitwidth, // @[BeatMerger.scala:33:14] output io_out_bits_mask_0, // @[BeatMerger.scala:33:14] output io_out_bits_mask_1, // @[BeatMerger.scala:33:14] output io_out_bits_mask_2, // @[BeatMerger.scala:33:14] output io_out_bits_mask_3, // @[BeatMerger.scala:33:14] output io_out_bits_mask_4, // @[BeatMerger.scala:33:14] output io_out_bits_mask_5, // @[BeatMerger.scala:33:14] output io_out_bits_mask_6, // @[BeatMerger.scala:33:14] output io_out_bits_mask_7, // @[BeatMerger.scala:33:14] output io_out_bits_mask_8, // @[BeatMerger.scala:33:14] output io_out_bits_mask_9, // @[BeatMerger.scala:33:14] output io_out_bits_mask_10, // @[BeatMerger.scala:33:14] output io_out_bits_mask_11, // @[BeatMerger.scala:33:14] output io_out_bits_mask_12, // @[BeatMerger.scala:33:14] output io_out_bits_mask_13, // @[BeatMerger.scala:33:14] output io_out_bits_mask_14, // @[BeatMerger.scala:33:14] output io_out_bits_mask_15, // @[BeatMerger.scala:33:14] output io_out_bits_mask_16, // @[BeatMerger.scala:33:14] output io_out_bits_mask_17, // @[BeatMerger.scala:33:14] output io_out_bits_mask_18, // @[BeatMerger.scala:33:14] output io_out_bits_mask_19, // @[BeatMerger.scala:33:14] output io_out_bits_mask_20, // @[BeatMerger.scala:33:14] output io_out_bits_mask_21, // @[BeatMerger.scala:33:14] output io_out_bits_mask_22, // @[BeatMerger.scala:33:14] output io_out_bits_mask_23, // @[BeatMerger.scala:33:14] output io_out_bits_mask_24, // @[BeatMerger.scala:33:14] output io_out_bits_mask_25, // @[BeatMerger.scala:33:14] output io_out_bits_mask_26, // @[BeatMerger.scala:33:14] output io_out_bits_mask_27, // @[BeatMerger.scala:33:14] output io_out_bits_mask_28, // @[BeatMerger.scala:33:14] output io_out_bits_mask_29, // @[BeatMerger.scala:33:14] output io_out_bits_mask_30, // @[BeatMerger.scala:33:14] output io_out_bits_mask_31, // @[BeatMerger.scala:33:14] output io_out_bits_mask_32, // @[BeatMerger.scala:33:14] output io_out_bits_mask_33, // @[BeatMerger.scala:33:14] output io_out_bits_mask_34, // @[BeatMerger.scala:33:14] output io_out_bits_mask_35, // @[BeatMerger.scala:33:14] output io_out_bits_mask_36, // @[BeatMerger.scala:33:14] output io_out_bits_mask_37, // @[BeatMerger.scala:33:14] output io_out_bits_mask_38, // @[BeatMerger.scala:33:14] output io_out_bits_mask_39, // @[BeatMerger.scala:33:14] output io_out_bits_mask_40, // @[BeatMerger.scala:33:14] output io_out_bits_mask_41, // @[BeatMerger.scala:33:14] output io_out_bits_mask_42, // @[BeatMerger.scala:33:14] output io_out_bits_mask_43, // @[BeatMerger.scala:33:14] output io_out_bits_mask_44, // @[BeatMerger.scala:33:14] output io_out_bits_mask_45, // @[BeatMerger.scala:33:14] output io_out_bits_mask_46, // @[BeatMerger.scala:33:14] output io_out_bits_mask_47, // @[BeatMerger.scala:33:14] output io_out_bits_mask_48, // @[BeatMerger.scala:33:14] output io_out_bits_mask_49, // @[BeatMerger.scala:33:14] output io_out_bits_mask_50, // @[BeatMerger.scala:33:14] output io_out_bits_mask_51, // @[BeatMerger.scala:33:14] output io_out_bits_mask_52, // @[BeatMerger.scala:33:14] output io_out_bits_mask_53, // @[BeatMerger.scala:33:14] output io_out_bits_mask_54, // @[BeatMerger.scala:33:14] output io_out_bits_mask_55, // @[BeatMerger.scala:33:14] output io_out_bits_mask_56, // @[BeatMerger.scala:33:14] output io_out_bits_mask_57, // @[BeatMerger.scala:33:14] output io_out_bits_mask_58, // @[BeatMerger.scala:33:14] output io_out_bits_mask_59, // @[BeatMerger.scala:33:14] output io_out_bits_mask_60, // @[BeatMerger.scala:33:14] output io_out_bits_mask_61, // @[BeatMerger.scala:33:14] output io_out_bits_mask_62, // @[BeatMerger.scala:33:14] output io_out_bits_mask_63, // @[BeatMerger.scala:33:14] output io_out_bits_last // @[BeatMerger.scala:33:14] ); wire io_req_valid_0 = io_req_valid; // @[BeatMerger.scala:30:7] wire [5:0] io_req_bits_shift_0 = io_req_bits_shift; // @[BeatMerger.scala:30:7] wire [13:0] io_req_bits_addr_0 = io_req_bits_addr; // @[BeatMerger.scala:30:7] wire io_req_bits_is_acc_0 = io_req_bits_is_acc; // @[BeatMerger.scala:30:7] wire io_req_bits_accumulate_0 = io_req_bits_accumulate; // @[BeatMerger.scala:30:7] wire io_req_bits_has_acc_bitwidth_0 = io_req_bits_has_acc_bitwidth; // @[BeatMerger.scala:30:7] wire [31:0] io_req_bits_scale_0 = io_req_bits_scale; // @[BeatMerger.scala:30:7] wire [15:0] io_req_bits_repeats_0 = io_req_bits_repeats; // @[BeatMerger.scala:30:7] wire [7:0] io_req_bits_pixel_repeats_0 = io_req_bits_pixel_repeats; // @[BeatMerger.scala:30:7] wire [15:0] io_req_bits_len_0 = io_req_bits_len; // @[BeatMerger.scala:30:7] wire [15:0] io_req_bits_block_stride_0 = io_req_bits_block_stride; // @[BeatMerger.scala:30:7] wire [8:0] io_req_bits_spad_row_offset_0 = io_req_bits_spad_row_offset; // @[BeatMerger.scala:30:7] wire [2:0] io_req_bits_lg_len_req_0 = io_req_bits_lg_len_req; // @[BeatMerger.scala:30:7] wire [6:0] io_req_bits_bytes_to_read_0 = io_req_bits_bytes_to_read; // @[BeatMerger.scala:30:7] wire [2:0] io_req_bits_cmd_id_0 = io_req_bits_cmd_id; // @[BeatMerger.scala:30:7] wire io_in_valid_0 = io_in_valid; // @[BeatMerger.scala:30:7] wire [127:0] io_in_bits_0 = io_in_bits; // @[BeatMerger.scala:30:7] wire io_out_ready_0 = io_out_ready; // @[BeatMerger.scala:30:7] wire [127:0] _mask_T = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[BeatMerger.scala:126:23] wire _io_in_ready_T_4; // @[BeatMerger.scala:66:30] wire _io_out_valid_T_7; // @[BeatMerger.scala:68:60] wire last_sending; // @[BeatMerger.scala:61:37] wire io_req_ready_0; // @[BeatMerger.scala:30:7] wire io_in_ready_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_0_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_1_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_2_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_3_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_4_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_5_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_6_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_7_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_8_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_9_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_10_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_11_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_12_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_13_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_14_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_15_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_16_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_17_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_18_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_19_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_20_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_21_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_22_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_23_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_24_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_25_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_26_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_27_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_28_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_29_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_30_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_31_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_32_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_33_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_34_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_35_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_36_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_37_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_38_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_39_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_40_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_41_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_42_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_43_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_44_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_45_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_46_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_47_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_48_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_49_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_50_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_51_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_52_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_53_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_54_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_55_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_56_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_57_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_58_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_59_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_60_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_61_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_62_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_63_0; // @[BeatMerger.scala:30:7] wire [511:0] io_out_bits_data_0; // @[BeatMerger.scala:30:7] wire [13:0] io_out_bits_addr_0; // @[BeatMerger.scala:30:7] wire io_out_bits_is_acc_0; // @[BeatMerger.scala:30:7] wire io_out_bits_accumulate_0; // @[BeatMerger.scala:30:7] wire io_out_bits_has_acc_bitwidth_0; // @[BeatMerger.scala:30:7] wire io_out_bits_last_0; // @[BeatMerger.scala:30:7] wire io_out_valid_0; // @[BeatMerger.scala:30:7] reg req_valid; // @[BeatMerger.scala:43:16] reg [5:0] req_bits_shift; // @[BeatMerger.scala:43:16] reg [13:0] req_bits_addr; // @[BeatMerger.scala:43:16] reg req_bits_is_acc; // @[BeatMerger.scala:43:16] assign io_out_bits_is_acc_0 = req_bits_is_acc; // @[BeatMerger.scala:30:7, :43:16] reg req_bits_accumulate; // @[BeatMerger.scala:43:16] assign io_out_bits_accumulate_0 = req_bits_accumulate; // @[BeatMerger.scala:30:7, :43:16] reg req_bits_has_acc_bitwidth; // @[BeatMerger.scala:43:16] assign io_out_bits_has_acc_bitwidth_0 = req_bits_has_acc_bitwidth; // @[BeatMerger.scala:30:7, :43:16] reg [31:0] req_bits_scale; // @[BeatMerger.scala:43:16] reg [15:0] req_bits_repeats; // @[BeatMerger.scala:43:16] reg [7:0] req_bits_pixel_repeats; // @[BeatMerger.scala:43:16] reg [15:0] req_bits_len; // @[BeatMerger.scala:43:16] reg [15:0] req_bits_block_stride; // @[BeatMerger.scala:43:16] reg [8:0] req_bits_spad_row_offset; // @[BeatMerger.scala:43:16] reg [2:0] req_bits_lg_len_req; // @[BeatMerger.scala:43:16] reg [6:0] req_bits_bytes_to_read; // @[BeatMerger.scala:43:16] reg [2:0] req_bits_cmd_id; // @[BeatMerger.scala:43:16] reg [511:0] buffer; // @[BeatMerger.scala:46:19] wire [6:0] rowBytes = req_bits_has_acc_bitwidth ? 7'h40 : 7'h10; // @[BeatMerger.scala:43:16, :48:21, :121:50] reg [6:0] bytesSent; // @[BeatMerger.scala:50:22] reg [6:0] bytesRead; // @[BeatMerger.scala:51:22] wire _bytesReadAfterShift_T = bytesRead > {1'h0, req_bits_shift}; // @[BeatMerger.scala:43:16, :51:22, :52:43] wire [7:0] _GEN = {1'h0, bytesRead}; // @[BeatMerger.scala:51:22, :52:71] wire [7:0] _bytesReadAfterShift_T_1 = _GEN - {2'h0, req_bits_shift}; // @[BeatMerger.scala:43:16, :52:71] wire [6:0] _bytesReadAfterShift_T_2 = _bytesReadAfterShift_T_1[6:0]; // @[BeatMerger.scala:52:71] wire [6:0] bytesReadAfterShift = _bytesReadAfterShift_T ? _bytesReadAfterShift_T_2 : 7'h0; // @[BeatMerger.scala:52:{32,43,71}] wire [7:0] _bytesDiscarded_T = _GEN - {1'h0, bytesReadAfterShift}; // @[BeatMerger.scala:52:{32,71}, :53:34] wire [6:0] bytesDiscarded = _bytesDiscarded_T[6:0]; // @[BeatMerger.scala:53:34] wire _usefulBytesRead_T = bytesReadAfterShift < req_bits_bytes_to_read; // @[Util.scala:109:12] wire [6:0] usefulBytesRead = _usefulBytesRead_T ? bytesReadAfterShift : req_bits_bytes_to_read; // @[Util.scala:109:{8,12}] wire _GEN_0 = bytesSent == 7'h0; // @[BeatMerger.scala:50:22, :57:41] wire _bytesSent_next_spad_row_offset_T; // @[BeatMerger.scala:57:41] assign _bytesSent_next_spad_row_offset_T = _GEN_0; // @[BeatMerger.scala:57:41] wire _io_out_bits_data_T_2; // @[BeatMerger.scala:70:70] assign _io_out_bits_data_T_2 = _GEN_0; // @[BeatMerger.scala:57:41, :70:70] wire _spad_row_offset_T; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_1; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_1 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_2; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_2 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_3; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_3 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_4; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_4 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_5; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_5 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_6; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_6 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_7; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_7 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_8; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_8 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_9; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_9 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_10; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_10 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_11; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_11 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_12; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_12 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_13; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_13 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_14; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_14 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_15; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_15 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_16; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_16 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_17; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_17 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_18; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_18 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_19; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_19 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_20; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_20 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_21; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_21 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_22; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_22 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_23; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_23 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_24; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_24 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_25; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_25 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_26; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_26 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_27; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_27 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_28; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_28 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_29; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_29 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_30; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_30 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_31; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_31 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_32; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_32 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_33; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_33 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_34; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_34 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_35; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_35 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_36; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_36 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_37; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_37 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_38; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_38 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_39; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_39 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_40; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_40 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_41; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_41 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_42; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_42 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_43; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_43 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_44; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_44 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_45; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_45 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_46; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_46 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_47; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_47 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_48; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_48 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_49; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_49 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_50; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_50 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_51; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_51 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_52; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_52 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_53; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_53 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_54; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_54 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_55; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_55 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_56; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_56 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_57; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_57 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_58; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_58 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_59; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_59 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_60; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_60 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_61; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_61 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_62; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_62 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_63; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_63 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire [8:0] bytesSent_next_spad_row_offset = _bytesSent_next_spad_row_offset_T ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :57:{30,41}] wire [9:0] _bytesSent_next_T = {3'h0, rowBytes} - {1'h0, bytesSent_next_spad_row_offset}; // @[BeatMerger.scala:48:21, :57:30, :58:32] wire [8:0] _bytesSent_next_T_1 = _bytesSent_next_T[8:0]; // @[BeatMerger.scala:58:32] wire [9:0] _GEN_1 = {3'h0, bytesSent}; // @[Util.scala:35:11] wire [9:0] _GEN_2 = _GEN_1 + {1'h0, _bytesSent_next_T_1}; // @[Util.scala:35:11] wire [9:0] _bytesSent_next_T_2; // @[Util.scala:35:11] assign _bytesSent_next_T_2 = _GEN_2; // @[Util.scala:35:11] wire [9:0] _bytesSent_next_T_4; // @[Util.scala:35:30] assign _bytesSent_next_T_4 = _GEN_2; // @[Util.scala:35:{11,30}] wire _bytesSent_next_T_3 = _bytesSent_next_T_2 > {3'h0, req_bits_bytes_to_read}; // @[Util.scala:35:{11,16}] wire [8:0] _bytesSent_next_T_5 = _bytesSent_next_T_4[8:0]; // @[Util.scala:35:30] wire [8:0] _GEN_3 = {2'h0, req_bits_bytes_to_read}; // @[Util.scala:35:8] wire [8:0] bytesSent_next = _bytesSent_next_T_3 ? _GEN_3 : _bytesSent_next_T_5; // @[Util.scala:35:{8,16,30}] assign last_sending = bytesSent_next == _GEN_3; // @[Util.scala:35:8] assign io_out_bits_last_0 = last_sending; // @[BeatMerger.scala:30:7, :61:37] wire [7:0] _T_389 = 8'h1 << req_bits_lg_len_req; // @[BeatMerger.scala:43:16, :62:42] wire [7:0] _last_reading_T; // @[BeatMerger.scala:62:42] assign _last_reading_T = _T_389; // @[BeatMerger.scala:62:42] wire [7:0] _io_in_ready_T_1; // @[BeatMerger.scala:66:66] assign _io_in_ready_T_1 = _T_389; // @[BeatMerger.scala:62:42, :66:66] wire [8:0] _last_reading_T_1 = {1'h0, _last_reading_T} - {2'h0, bytesRead}; // @[BeatMerger.scala:51:22, :52:71, :62:{42,73}] wire [7:0] _last_reading_T_2 = _last_reading_T_1[7:0]; // @[BeatMerger.scala:62:73] wire last_reading = _last_reading_T_2 < 8'h11; // @[BeatMerger.scala:62:{34,73}] wire _io_req_ready_T = ~req_valid; // @[BeatMerger.scala:43:16, :64:19] wire _T_397 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire _io_in_ready_T; // @[Decoupled.scala:51:35] assign _io_in_ready_T = _T_397; // @[Decoupled.scala:51:35] wire _current_bytesRead_T; // @[Decoupled.scala:51:35] assign _current_bytesRead_T = _T_397; // @[Decoupled.scala:51:35] wire _current_bytesDiscarded_T; // @[Decoupled.scala:51:35] assign _current_bytesDiscarded_T = _T_397; // @[Decoupled.scala:51:35] wire _current_usefulBytesRead_T; // @[Decoupled.scala:51:35] assign _current_usefulBytesRead_T = _T_397; // @[Decoupled.scala:51:35] wire _current_shift_T; // @[Decoupled.scala:51:35] assign _current_shift_T = _T_397; // @[Decoupled.scala:51:35] wire _current_lg_len_req_T; // @[Decoupled.scala:51:35] assign _current_lg_len_req_T = _T_397; // @[Decoupled.scala:51:35] wire _io_in_ready_T_2 = _GEN != _io_in_ready_T_1; // @[BeatMerger.scala:52:71, :66:{57,66}] wire _io_in_ready_T_3 = req_valid & _io_in_ready_T_2; // @[BeatMerger.scala:43:16, :66:{44,57}] assign _io_in_ready_T_4 = _io_in_ready_T \| _io_in_ready_T_3; // @[Decoupled.scala:51:35] assign io_in_ready_0 = _io_in_ready_T_4; // @[BeatMerger.scala:30:7, :66:30] wire _io_out_valid_T = usefulBytesRead > bytesSent; // @[Util.scala:109:8] wire _io_out_valid_T_1 = req_valid & _io_out_valid_T; // @[BeatMerger.scala:43:16, :68:{29,48}] wire [7:0] _io_out_valid_T_2 = {1'h0, usefulBytesRead} - {1'h0, bytesSent}; // @[Util.scala:109:8] wire [6:0] _io_out_valid_T_3 = _io_out_valid_T_2[6:0]; // @[BeatMerger.scala:68:80] wire _io_out_valid_T_4 = _io_out_valid_T_3 >= rowBytes; // @[BeatMerger.scala:48:21, :68:{80,92}] wire _io_out_valid_T_5 = usefulBytesRead == req_bits_bytes_to_read; // @[Util.scala:109:8] wire _io_out_valid_T_6 = _io_out_valid_T_4 \| _io_out_valid_T_5; // @[BeatMerger.scala:68:{92,104}, :69:21] assign _io_out_valid_T_7 = _io_out_valid_T_1 & _io_out_valid_T_6; // @[BeatMerger.scala:68:{29,60,104}] assign io_out_valid_0 = _io_out_valid_T_7; // @[BeatMerger.scala:30:7, :68:60] wire [10:0] _io_out_bits_data_T = {1'h0, bytesSent, 3'h0}; // @[BeatMerger.scala:50:22, :70:45] wire [511:0] _io_out_bits_data_T_1 = buffer >> _io_out_bits_data_T; // @[BeatMerger.scala:46:19, :70:{31,45}] wire [12:0] _io_out_bits_data_T_3 = {1'h0, req_bits_spad_row_offset, 3'h0}; // @[BeatMerger.scala:43:16, :70:104] wire [12:0] _io_out_bits_data_T_4 = _io_out_bits_data_T_2 ? _io_out_bits_data_T_3 : 13'h0; // @[BeatMerger.scala:70:{59,70,104}] wire [8702:0] _io_out_bits_data_T_5 = {8191'h0, _io_out_bits_data_T_1} << _io_out_bits_data_T_4; // @[BeatMerger.scala:70:{31,53,59}] assign io_out_bits_data_0 = _io_out_bits_data_T_5[511:0]; // @[BeatMerger.scala:30:7, :70:{20,53}] wire [8:0] spad_row_offset = _spad_row_offset_T ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _GEN_4 = {3'h0, req_bits_bytes_to_read - bytesSent}; // @[BeatMerger.scala:43:16, :50:22, :74:{29,56}] assign io_out_bits_mask_0_0 = spad_row_offset == 9'h0 & (\|({1'h0, spad_row_offset} + _GEN_4)); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_1 = _spad_row_offset_T_1 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_9 = {1'h0, spad_row_offset_1} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_1_0 = spad_row_offset_1 < 9'h2 & (\|(_T_9[9:1])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_2 = _spad_row_offset_T_2 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_2_0 = spad_row_offset_2 < 9'h3 & {1'h0, spad_row_offset_2} + _GEN_4 > 10'h2; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_3 = _spad_row_offset_T_3 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_21 = {1'h0, spad_row_offset_3} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_3_0 = spad_row_offset_3 < 9'h4 & (\|(_T_21[9:2])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_4 = _spad_row_offset_T_4 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_4_0 = spad_row_offset_4 < 9'h5 & {1'h0, spad_row_offset_4} + _GEN_4 > 10'h4; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_5 = _spad_row_offset_T_5 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_5_0 = spad_row_offset_5 < 9'h6 & {1'h0, spad_row_offset_5} + _GEN_4 > 10'h5; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_6 = _spad_row_offset_T_6 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_6_0 = spad_row_offset_6 < 9'h7 & {1'h0, spad_row_offset_6} + _GEN_4 > 10'h6; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_7 = _spad_row_offset_T_7 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_45 = {1'h0, spad_row_offset_7} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_7_0 = spad_row_offset_7 < 9'h8 & (\|(_T_45[9:3])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_8 = _spad_row_offset_T_8 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_8_0 = spad_row_offset_8 < 9'h9 & {1'h0, spad_row_offset_8} + _GEN_4 > 10'h8; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_9 = _spad_row_offset_T_9 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_9_0 = spad_row_offset_9 < 9'hA & {1'h0, spad_row_offset_9} + _GEN_4 > 10'h9; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_10 = _spad_row_offset_T_10 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_10_0 = spad_row_offset_10 < 9'hB & {1'h0, spad_row_offset_10} + _GEN_4 > 10'hA; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_11 = _spad_row_offset_T_11 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_11_0 = spad_row_offset_11 < 9'hC & {1'h0, spad_row_offset_11} + _GEN_4 > 10'hB; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_12 = _spad_row_offset_T_12 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_12_0 = spad_row_offset_12 < 9'hD & {1'h0, spad_row_offset_12} + _GEN_4 > 10'hC; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_13 = _spad_row_offset_T_13 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_13_0 = spad_row_offset_13 < 9'hE & {1'h0, spad_row_offset_13} + _GEN_4 > 10'hD; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_14 = _spad_row_offset_T_14 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_14_0 = spad_row_offset_14 < 9'hF & {1'h0, spad_row_offset_14} + _GEN_4 > 10'hE; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_15 = _spad_row_offset_T_15 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_93 = {1'h0, spad_row_offset_15} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_15_0 = spad_row_offset_15 < 9'h10 & (\|(_T_93[9:4])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_16 = _spad_row_offset_T_16 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_16_0 = spad_row_offset_16 < 9'h11 & {1'h0, spad_row_offset_16} + _GEN_4 > 10'h10; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_17 = _spad_row_offset_T_17 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_17_0 = spad_row_offset_17 < 9'h12 & {1'h0, spad_row_offset_17} + _GEN_4 > 10'h11; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_18 = _spad_row_offset_T_18 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_18_0 = spad_row_offset_18 < 9'h13 & {1'h0, spad_row_offset_18} + _GEN_4 > 10'h12; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_19 = _spad_row_offset_T_19 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_19_0 = spad_row_offset_19 < 9'h14 & {1'h0, spad_row_offset_19} + _GEN_4 > 10'h13; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_20 = _spad_row_offset_T_20 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_20_0 = spad_row_offset_20 < 9'h15 & {1'h0, spad_row_offset_20} + _GEN_4 > 10'h14; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_21 = _spad_row_offset_T_21 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_21_0 = spad_row_offset_21 < 9'h16 & {1'h0, spad_row_offset_21} + _GEN_4 > 10'h15; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_22 = _spad_row_offset_T_22 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_22_0 = spad_row_offset_22 < 9'h17 & {1'h0, spad_row_offset_22} + _GEN_4 > 10'h16; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_23 = _spad_row_offset_T_23 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_23_0 = spad_row_offset_23 < 9'h18 & {1'h0, spad_row_offset_23} + _GEN_4 > 10'h17; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_24 = _spad_row_offset_T_24 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_24_0 = spad_row_offset_24 < 9'h19 & {1'h0, spad_row_offset_24} + _GEN_4 > 10'h18; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_25 = _spad_row_offset_T_25 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_25_0 = spad_row_offset_25 < 9'h1A & {1'h0, spad_row_offset_25} + _GEN_4 > 10'h19; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_26 = _spad_row_offset_T_26 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_26_0 = spad_row_offset_26 < 9'h1B & {1'h0, spad_row_offset_26} + _GEN_4 > 10'h1A; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_27 = _spad_row_offset_T_27 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_27_0 = spad_row_offset_27 < 9'h1C & {1'h0, spad_row_offset_27} + _GEN_4 > 10'h1B; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_28 = _spad_row_offset_T_28 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_28_0 = spad_row_offset_28 < 9'h1D & {1'h0, spad_row_offset_28} + _GEN_4 > 10'h1C; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_29 = _spad_row_offset_T_29 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_29_0 = spad_row_offset_29 < 9'h1E & {1'h0, spad_row_offset_29} + _GEN_4 > 10'h1D; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_30 = _spad_row_offset_T_30 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_30_0 = spad_row_offset_30 < 9'h1F & {1'h0, spad_row_offset_30} + _GEN_4 > 10'h1E; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_31 = _spad_row_offset_T_31 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_189 = {1'h0, spad_row_offset_31} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_31_0 = spad_row_offset_31 < 9'h20 & (\|(_T_189[9:5])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_32 = _spad_row_offset_T_32 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_32_0 = spad_row_offset_32 < 9'h21 & {1'h0, spad_row_offset_32} + _GEN_4 > 10'h20; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_33 = _spad_row_offset_T_33 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_33_0 = spad_row_offset_33 < 9'h22 & {1'h0, spad_row_offset_33} + _GEN_4 > 10'h21; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_34 = _spad_row_offset_T_34 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_34_0 = spad_row_offset_34 < 9'h23 & {1'h0, spad_row_offset_34} + _GEN_4 > 10'h22; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_35 = _spad_row_offset_T_35 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_35_0 = spad_row_offset_35 < 9'h24 & {1'h0, spad_row_offset_35} + _GEN_4 > 10'h23; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_36 = _spad_row_offset_T_36 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_36_0 = spad_row_offset_36 < 9'h25 & {1'h0, spad_row_offset_36} + _GEN_4 > 10'h24; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_37 = _spad_row_offset_T_37 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_37_0 = spad_row_offset_37 < 9'h26 & {1'h0, spad_row_offset_37} + _GEN_4 > 10'h25; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_38 = _spad_row_offset_T_38 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_38_0 = spad_row_offset_38 < 9'h27 & {1'h0, spad_row_offset_38} + _GEN_4 > 10'h26; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_39 = _spad_row_offset_T_39 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_39_0 = spad_row_offset_39 < 9'h28 & {1'h0, spad_row_offset_39} + _GEN_4 > 10'h27; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_40 = _spad_row_offset_T_40 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_40_0 = spad_row_offset_40 < 9'h29 & {1'h0, spad_row_offset_40} + _GEN_4 > 10'h28; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_41 = _spad_row_offset_T_41 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_41_0 = spad_row_offset_41 < 9'h2A & {1'h0, spad_row_offset_41} + _GEN_4 > 10'h29; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_42 = _spad_row_offset_T_42 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_42_0 = spad_row_offset_42 < 9'h2B & {1'h0, spad_row_offset_42} + _GEN_4 > 10'h2A; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_43 = _spad_row_offset_T_43 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_43_0 = spad_row_offset_43 < 9'h2C & {1'h0, spad_row_offset_43} + _GEN_4 > 10'h2B; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_44 = _spad_row_offset_T_44 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_44_0 = spad_row_offset_44 < 9'h2D & {1'h0, spad_row_offset_44} + _GEN_4 > 10'h2C; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_45 = _spad_row_offset_T_45 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_45_0 = spad_row_offset_45 < 9'h2E & {1'h0, spad_row_offset_45} + _GEN_4 > 10'h2D; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_46 = _spad_row_offset_T_46 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_46_0 = spad_row_offset_46 < 9'h2F & {1'h0, spad_row_offset_46} + _GEN_4 > 10'h2E; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_47 = _spad_row_offset_T_47 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_47_0 = spad_row_offset_47 < 9'h30 & {1'h0, spad_row_offset_47} + _GEN_4 > 10'h2F; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_48 = _spad_row_offset_T_48 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_48_0 = spad_row_offset_48 < 9'h31 & {1'h0, spad_row_offset_48} + _GEN_4 > 10'h30; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_49 = _spad_row_offset_T_49 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_49_0 = spad_row_offset_49 < 9'h32 & {1'h0, spad_row_offset_49} + _GEN_4 > 10'h31; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_50 = _spad_row_offset_T_50 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_50_0 = spad_row_offset_50 < 9'h33 & {1'h0, spad_row_offset_50} + _GEN_4 > 10'h32; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_51 = _spad_row_offset_T_51 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_51_0 = spad_row_offset_51 < 9'h34 & {1'h0, spad_row_offset_51} + _GEN_4 > 10'h33; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_52 = _spad_row_offset_T_52 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_52_0 = spad_row_offset_52 < 9'h35 & {1'h0, spad_row_offset_52} + _GEN_4 > 10'h34; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_53 = _spad_row_offset_T_53 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_53_0 = spad_row_offset_53 < 9'h36 & {1'h0, spad_row_offset_53} + _GEN_4 > 10'h35; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_54 = _spad_row_offset_T_54 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_54_0 = spad_row_offset_54 < 9'h37 & {1'h0, spad_row_offset_54} + _GEN_4 > 10'h36; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_55 = _spad_row_offset_T_55 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_55_0 = spad_row_offset_55 < 9'h38 & {1'h0, spad_row_offset_55} + _GEN_4 > 10'h37; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_56 = _spad_row_offset_T_56 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_56_0 = spad_row_offset_56 < 9'h39 & {1'h0, spad_row_offset_56} + _GEN_4 > 10'h38; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_57 = _spad_row_offset_T_57 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_57_0 = spad_row_offset_57 < 9'h3A & {1'h0, spad_row_offset_57} + _GEN_4 > 10'h39; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_58 = _spad_row_offset_T_58 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_58_0 = spad_row_offset_58 < 9'h3B & {1'h0, spad_row_offset_58} + _GEN_4 > 10'h3A; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_59 = _spad_row_offset_T_59 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_59_0 = spad_row_offset_59 < 9'h3C & {1'h0, spad_row_offset_59} + _GEN_4 > 10'h3B; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_60 = _spad_row_offset_T_60 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_60_0 = spad_row_offset_60 < 9'h3D & {1'h0, spad_row_offset_60} + _GEN_4 > 10'h3C; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_61 = _spad_row_offset_T_61 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_61_0 = spad_row_offset_61 < 9'h3E & {1'h0, spad_row_offset_61} + _GEN_4 > 10'h3D; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_62 = _spad_row_offset_T_62 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_62_0 = spad_row_offset_62 < 9'h3F & {1'h0, spad_row_offset_62} + _GEN_4 > 10'h3E; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_63 = _spad_row_offset_T_63 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_381 = {1'h0, spad_row_offset_63} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_63_0 = spad_row_offset_63 < 9'h40 & (\|(_T_381[9:6])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [9:0] _io_out_bits_addr_total_bytes_sent_T = {1'h0, req_bits_spad_row_offset} + _GEN_1; // @[Util.scala:35:11] wire [8:0] io_out_bits_addr_total_bytes_sent = _io_out_bits_addr_total_bytes_sent_T[8:0]; // @[BeatMerger.scala:77:53] wire [8:0] _io_out_bits_addr_T = io_out_bits_addr_total_bytes_sent / 9'h40; // @[BeatMerger.scala:77:53, :82:84] wire [8:0] _io_out_bits_addr_T_1 = io_out_bits_addr_total_bytes_sent / 9'h10; // @[BeatMerger.scala:77:53, :83:85] wire [8:0] _io_out_bits_addr_T_2 = req_bits_has_acc_bitwidth ? _io_out_bits_addr_T : _io_out_bits_addr_T_1; // @[BeatMerger.scala:43:16, :78:8, :82:84, :83:85] wire [24:0] _io_out_bits_addr_T_3 = {9'h0, req_bits_block_stride} * {16'h0, _io_out_bits_addr_T_2}; // @[BeatMerger.scala:43:16, :76:61, :78:8] wire [25:0] _io_out_bits_addr_T_4 = {12'h0, req_bits_addr} + {1'h0, _io_out_bits_addr_T_3}; // @[BeatMerger.scala:43:16, :76:{37,61}] wire [24:0] _io_out_bits_addr_T_5 = _io_out_bits_addr_T_4[24:0]; // @[BeatMerger.scala:76:37] assign io_out_bits_addr_0 = _io_out_bits_addr_T_5[13:0]; // @[BeatMerger.scala:30:7, :76:{20,37}] wire _T_388 = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] wire _T_391 = last_sending & _GEN == _T_389; // @[BeatMerger.scala:52:71, :61:37, :62:42, :101:{24,37}] assign io_req_ready_0 = _T_388 & _T_391 \| _io_req_ready_T; // @[Decoupled.scala:51:35] wire [6:0] current_bytesRead = _current_bytesRead_T ? 7'h0 : bytesRead; // @[Decoupled.scala:51:35] wire [6:0] current_bytesDiscarded = _current_bytesDiscarded_T ? 7'h0 : bytesDiscarded; // @[Decoupled.scala:51:35] wire [6:0] current_usefulBytesRead = _current_usefulBytesRead_T ? 7'h0 : usefulBytesRead; // @[Decoupled.scala:51:35] wire [5:0] current_shift = _current_shift_T ? io_req_bits_shift_0 : req_bits_shift; // @[Decoupled.scala:51:35] wire [2:0] current_lg_len_req = _current_lg_len_req_T ? io_req_bits_lg_len_req_0 : req_bits_lg_len_req; // @[Decoupled.scala:51:35] wire [7:0] current_len_req = 8'h1 << current_lg_len_req; // @[BeatMerger.scala:118:33, :119:32] wire [7:0] _rshift_T = {2'h0, current_shift} - {1'h0, current_bytesDiscarded}; // @[BeatMerger.scala:52:71, :115:37, :117:28, :121:25, :124:35] wire [6:0] _rshift_T_1 = _rshift_T[6:0]; // @[BeatMerger.scala:124:35] wire [10:0] rshift = {1'h0, _rshift_T_1, 3'h0}; // @[BeatMerger.scala:124:{35,61}] wire [10:0] lshift = {1'h0, current_usefulBytesRead, 3'h0}; // @[BeatMerger.scala:116:38, :125:44] wire [127:0] _GEN_5 = {117'h0, rshift}; // @[BeatMerger.scala:124:61, :126:41] wire [127:0] _mask_T_1 = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF >> _GEN_5; // @[BeatMerger.scala:126:41] wire [2174:0] _GEN_6 = {2164'h0, lshift}; // @[BeatMerger.scala:125:44, :126:52] wire [2174:0] _mask_T_2 = {2047'h0, _mask_T_1} << _GEN_6; // @[BeatMerger.scala:126:{41,52}] wire [2174:0] mask = ~_mask_T_2; // @[BeatMerger.scala:126:{19,52}] wire [2174:0] _buffer_T = {1663'h0, mask[511:0] & buffer}; // @[BeatMerger.scala:46:19, :126:19, :128:25] wire [127:0] _buffer_T_1 = io_in_bits_0 >> _GEN_5; // @[BeatMerger.scala:30:7, :126:41, :128:48] wire [2174:0] _buffer_T_2 = {2047'h0, _buffer_T_1} << _GEN_6; // @[BeatMerger.scala:126:52, :128:{48,59}] wire [2174:0] _buffer_T_3 = _buffer_T \| _buffer_T_2; // @[BeatMerger.scala:128:{25,33,59}] wire [7:0] _GEN_7 = {1'h0, current_bytesRead} + 8'h10; // @[Util.scala:35:11] wire [7:0] _bytesRead_T; // @[Util.scala:35:11] assign _bytesRead_T = _GEN_7; // @[Util.scala:35:11] wire [7:0] _bytesRead_T_2; // @[Util.scala:35:30] assign _bytesRead_T_2 = _GEN_7; // @[Util.scala:35:{11,30}] wire _bytesRead_T_1 = _bytesRead_T > current_len_req; // @[Util.scala:35:{11,16}] wire [6:0] _bytesRead_T_3 = _bytesRead_T_2[6:0]; // @[Util.scala:35:30] wire [7:0] _bytesRead_T_4 = _bytesRead_T_1 ? current_len_req : {1'h0, _bytesRead_T_3}; // @[Util.scala:35:{8,16,30}] wire _T_399 = bytesSent == req_bits_bytes_to_read; // @[BeatMerger.scala:43:16, :50:22, :94:15] wire _T_387 = _GEN == _T_389 & _T_399; // @[BeatMerger.scala:52:71, :62:42, :93:{19,59}, :94:15] wire _T_393 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[BeatMerger.scala:30:7] req_valid <= ~(reset \| _T_393 & ~_T_397 & _T_399 & last_reading) & (_T_397 \| (_T_388 ? ~(_T_391 \| _T_387) & req_valid : ~_T_387 & req_valid)); // @[Decoupled.scala:51:35] if (_T_397) begin // @[Decoupled.scala:51:35] req_bits_shift <= io_req_bits_shift_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_addr <= io_req_bits_addr_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_is_acc <= io_req_bits_is_acc_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_accumulate <= io_req_bits_accumulate_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_has_acc_bitwidth <= io_req_bits_has_acc_bitwidth_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_scale <= io_req_bits_scale_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_repeats <= io_req_bits_repeats_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_pixel_repeats <= io_req_bits_pixel_repeats_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_len <= io_req_bits_len_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_block_stride <= io_req_bits_block_stride_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_spad_row_offset <= io_req_bits_spad_row_offset_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_lg_len_req <= io_req_bits_lg_len_req_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_bytes_to_read <= io_req_bits_bytes_to_read_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_cmd_id <= io_req_bits_cmd_id_0; // @[BeatMerger.scala:30:7, :43:16] bytesSent <= 7'h0; // @[BeatMerger.scala:50:22] end else if (_T_388) // @[Decoupled.scala:51:35] bytesSent <= bytesSent_next[6:0]; // @[Util.scala:35:8] if (_T_393 & _rshift_T[6:0] < 7'h11) // @[Decoupled.scala:51:35] buffer <= _buffer_T_3[511:0]; // @[BeatMerger.scala:46:19, :128:{14,33}] if (_T_393) // @[Decoupled.scala:51:35] bytesRead <= _bytesRead_T_4[6:0]; // @[Util.scala:35:8] else if (_T_397) // @[Decoupled.scala:51:35] bytesRead <= 7'h0; // @[BeatMerger.scala:51:22] always @(posedge) assign io_req_ready = io_req_ready_0; // @[BeatMerger.scala:30:7] assign io_in_ready = io_in_ready_0; // @[BeatMerger.scala:30:7] assign io_out_valid = io_out_valid_0; // @[BeatMerger.scala:30:7] assign io_out_bits_data = io_out_bits_data_0; // @[BeatMerger.scala:30:7] assign io_out_bits_addr = io_out_bits_addr_0; // @[BeatMerger.scala:30:7] assign io_out_bits_is_acc = io_out_bits_is_acc_0; // @[BeatMerger.scala:30:7] assign io_out_bits_accumulate = io_out_bits_accumulate_0; // @[BeatMerger.scala:30:7] assign io_out_bits_has_acc_bitwidth = io_out_bits_has_acc_bitwidth_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_0 = io_out_bits_mask_0_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_1 = io_out_bits_mask_1_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_2 = io_out_bits_mask_2_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_3 = io_out_bits_mask_3_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_4 = io_out_bits_mask_4_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_5 = io_out_bits_mask_5_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_6 = io_out_bits_mask_6_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_7 = io_out_bits_mask_7_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_8 = io_out_bits_mask_8_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_9 = io_out_bits_mask_9_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_10 = io_out_bits_mask_10_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_11 = io_out_bits_mask_11_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_12 = io_out_bits_mask_12_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_13 = io_out_bits_mask_13_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_14 = io_out_bits_mask_14_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_15 = io_out_bits_mask_15_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_16 = io_out_bits_mask_16_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_17 = io_out_bits_mask_17_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_18 = io_out_bits_mask_18_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_19 = io_out_bits_mask_19_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_20 = io_out_bits_mask_20_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_21 = io_out_bits_mask_21_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_22 = io_out_bits_mask_22_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_23 = io_out_bits_mask_23_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_24 = io_out_bits_mask_24_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_25 = io_out_bits_mask_25_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_26 = io_out_bits_mask_26_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_27 = io_out_bits_mask_27_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_28 = io_out_bits_mask_28_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_29 = io_out_bits_mask_29_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_30 = io_out_bits_mask_30_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_31 = io_out_bits_mask_31_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_32 = io_out_bits_mask_32_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_33 = io_out_bits_mask_33_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_34 = io_out_bits_mask_34_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_35 = io_out_bits_mask_35_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_36 = io_out_bits_mask_36_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_37 = io_out_bits_mask_37_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_38 = io_out_bits_mask_38_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_39 = io_out_bits_mask_39_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_40 = io_out_bits_mask_40_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_41 = io_out_bits_mask_41_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_42 = io_out_bits_mask_42_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_43 = io_out_bits_mask_43_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_44 = io_out_bits_mask_44_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_45 = io_out_bits_mask_45_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_46 = io_out_bits_mask_46_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_47 = io_out_bits_mask_47_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_48 = io_out_bits_mask_48_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_49 = io_out_bits_mask_49_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_50 = io_out_bits_mask_50_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_51 = io_out_bits_mask_51_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_52 = io_out_bits_mask_52_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_53 = io_out_bits_mask_53_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_54 = io_out_bits_mask_54_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_55 = io_out_bits_mask_55_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_56 = io_out_bits_mask_56_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_57 = io_out_bits_mask_57_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_58 = io_out_bits_mask_58_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_59 = io_out_bits_mask_59_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_60 = io_out_bits_mask_60_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_61 = io_out_bits_mask_61_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_62 = io_out_bits_mask_62_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_63 = io_out_bits_mask_63_0; // @[BeatMerger.scala:30:7] assign io_out_bits_last = io_out_bits_last_0; // @[BeatMerger.scala:30:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLDFromBeat_SerialRAM_a64d64s8k8z8c : input clock : Clock input reset : Reset output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip beat : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<65>, head : UInt<1>, tail : UInt<1>}}} wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect io.protocol, protocol regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1) reg const_reg : UInt<30>, clock node const = mux(io.beat.bits.head, io.beat.bits.payload, const_reg) node _io_beat_ready_T = eq(io.beat.bits.tail, UInt<1>(0h0)) node _io_beat_ready_T_1 = and(is_const, _io_beat_ready_T) node _io_beat_ready_T_2 = or(_io_beat_ready_T_1, protocol.ready) connect io.beat.ready, _io_beat_ready_T_2 node _protocol_valid_T = eq(is_const, UInt<1>(0h0)) node _protocol_valid_T_1 = or(_protocol_valid_T, io.beat.bits.tail) node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.beat.valid) connect protocol.valid, _protocol_valid_T_2 wire _protocol_bits_denied_WIRE : UInt<1> connect _protocol_bits_denied_WIRE, const connect protocol.bits.denied, _protocol_bits_denied_WIRE node _T = shr(const, 1) wire _protocol_bits_sink_WIRE : UInt<8> connect _protocol_bits_sink_WIRE, _T connect protocol.bits.sink, _protocol_bits_sink_WIRE node _T_1 = shr(_T, 8) wire _protocol_bits_echo_WIRE : { } wire _protocol_bits_echo_WIRE_1 : UInt<0> connect _protocol_bits_echo_WIRE_1, _T_1 connect protocol.bits.echo, _protocol_bits_echo_WIRE node _T_2 = shr(_T_1, 0) wire _protocol_bits_user_WIRE : { } wire _protocol_bits_user_WIRE_1 : UInt<0> connect _protocol_bits_user_WIRE_1, _T_2 connect protocol.bits.user, _protocol_bits_user_WIRE node _T_3 = shr(_T_2, 0) wire _protocol_bits_source_WIRE : UInt<8> connect _protocol_bits_source_WIRE, _T_3 connect protocol.bits.source, _protocol_bits_source_WIRE node _T_4 = shr(_T_3, 8) wire _protocol_bits_size_WIRE : UInt<8> connect _protocol_bits_size_WIRE, _T_4 connect protocol.bits.size, _protocol_bits_size_WIRE node _T_5 = shr(_T_4, 8) wire _protocol_bits_param_WIRE : UInt<2> connect _protocol_bits_param_WIRE, _T_5 connect protocol.bits.param, _protocol_bits_param_WIRE node _T_6 = shr(_T_5, 2) wire _protocol_bits_opcode_WIRE : UInt<3> connect _protocol_bits_opcode_WIRE, _T_6 connect protocol.bits.opcode, _protocol_bits_opcode_WIRE node _T_7 = shr(_T_6, 3) wire _protocol_bits_corrupt_WIRE : UInt<1> connect _protocol_bits_corrupt_WIRE, io.beat.bits.payload connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE node _T_8 = shr(io.beat.bits.payload, 1) wire _protocol_bits_data_WIRE : UInt<64> connect _protocol_bits_data_WIRE, _T_8 connect protocol.bits.data, _protocol_bits_data_WIRE node _T_9 = shr(_T_8, 64) node _T_10 = and(io.beat.ready, io.beat.valid) node _T_11 = and(_T_10, io.beat.bits.head) when _T_11 : connect is_const, UInt<1>(0h0) connect const_reg, io.beat.bits.payload node _T_12 = and(io.beat.ready, io.beat.valid) node _T_13 = and(_T_12, io.beat.bits.tail) when _T_13 : connect is_const, UInt<1>(0h1)	module TLDFromBeat_SerialRAM_a64d64s8k8z8c( // @[TLChannelCompactor.scala:134:7] input clock, // @[TLChannelCompactor.scala:134:7] input reset, // @[TLChannelCompactor.scala:134:7] input io_protocol_ready, // @[TLChannelCompactor.scala:75:14] output io_protocol_valid, // @[TLChannelCompactor.scala:75:14] output [2:0] io_protocol_bits_opcode, // @[TLChannelCompactor.scala:75:14] output [1:0] io_protocol_bits_param, // @[TLChannelCompactor.scala:75:14] output [7:0] io_protocol_bits_size, // @[TLChannelCompactor.scala:75:14] output [7:0] io_protocol_bits_source, // @[TLChannelCompactor.scala:75:14] output [7:0] io_protocol_bits_sink, // @[TLChannelCompactor.scala:75:14] output io_protocol_bits_denied, // @[TLChannelCompactor.scala:75:14] output [63:0] io_protocol_bits_data, // @[TLChannelCompactor.scala:75:14] output io_protocol_bits_corrupt, // @[TLChannelCompactor.scala:75:14] output io_beat_ready, // @[TLChannelCompactor.scala:75:14] input io_beat_valid, // @[TLChannelCompactor.scala:75:14] input [64:0] io_beat_bits_payload, // @[TLChannelCompactor.scala:75:14] input io_beat_bits_head, // @[TLChannelCompactor.scala:75:14] input io_beat_bits_tail // @[TLChannelCompactor.scala:75:14] ); wire io_protocol_ready_0 = io_protocol_ready; // @[TLChannelCompactor.scala:134:7] wire io_beat_valid_0 = io_beat_valid; // @[TLChannelCompactor.scala:134:7] wire [64:0] io_beat_bits_payload_0 = io_beat_bits_payload; // @[TLChannelCompactor.scala:134:7] wire io_beat_bits_head_0 = io_beat_bits_head; // @[TLChannelCompactor.scala:134:7] wire io_beat_bits_tail_0 = io_beat_bits_tail; // @[TLChannelCompactor.scala:134:7] wire protocol_ready = io_protocol_ready_0; // @[TLChannelCompactor.scala:83:22, :134:7] wire protocol_valid; // @[TLChannelCompactor.scala:83:22] wire [2:0] protocol_bits_opcode; // @[TLChannelCompactor.scala:83:22] wire [1:0] protocol_bits_param; // @[TLChannelCompactor.scala:83:22] wire [7:0] protocol_bits_size; // @[TLChannelCompactor.scala:83:22] wire [7:0] protocol_bits_source; // @[TLChannelCompactor.scala:83:22] wire [7:0] protocol_bits_sink; // @[TLChannelCompactor.scala:83:22] wire protocol_bits_denied; // @[TLChannelCompactor.scala:83:22] wire [63:0] protocol_bits_data; // @[TLChannelCompactor.scala:83:22] wire protocol_bits_corrupt; // @[TLChannelCompactor.scala:83:22] wire _io_beat_ready_T_2; // @[TLChannelCompactor.scala:91:53] wire [2:0] io_protocol_bits_opcode_0; // @[TLChannelCompactor.scala:134:7] wire [1:0] io_protocol_bits_param_0; // @[TLChannelCompactor.scala:134:7] wire [7:0] io_protocol_bits_size_0; // @[TLChannelCompactor.scala:134:7] wire [7:0] io_protocol_bits_source_0; // @[TLChannelCompactor.scala:134:7] wire [7:0] io_protocol_bits_sink_0; // @[TLChannelCompactor.scala:134:7] wire io_protocol_bits_denied_0; // @[TLChannelCompactor.scala:134:7] wire [63:0] io_protocol_bits_data_0; // @[TLChannelCompactor.scala:134:7] wire io_protocol_bits_corrupt_0; // @[TLChannelCompactor.scala:134:7] wire io_protocol_valid_0; // @[TLChannelCompactor.scala:134:7] wire io_beat_ready_0; // @[TLChannelCompactor.scala:134:7] wire _protocol_valid_T_2; // @[TLChannelCompactor.scala:92:54] assign io_protocol_valid_0 = protocol_valid; // @[TLChannelCompactor.scala:83:22, :134:7] wire [2:0] _protocol_bits_opcode_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_opcode_0 = protocol_bits_opcode; // @[TLChannelCompactor.scala:83:22, :134:7] wire [1:0] _protocol_bits_param_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_param_0 = protocol_bits_param; // @[TLChannelCompactor.scala:83:22, :134:7] wire [7:0] _protocol_bits_size_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_size_0 = protocol_bits_size; // @[TLChannelCompactor.scala:83:22, :134:7] wire [7:0] _protocol_bits_source_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_source_0 = protocol_bits_source; // @[TLChannelCompactor.scala:83:22, :134:7] wire [7:0] _protocol_bits_sink_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_sink_0 = protocol_bits_sink; // @[TLChannelCompactor.scala:83:22, :134:7] wire _protocol_bits_denied_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_denied_0 = protocol_bits_denied; // @[TLChannelCompactor.scala:83:22, :134:7] wire [63:0] _protocol_bits_data_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_data_0 = protocol_bits_data; // @[TLChannelCompactor.scala:83:22, :134:7] wire _protocol_bits_corrupt_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_corrupt_0 = protocol_bits_corrupt; // @[TLChannelCompactor.scala:83:22, :134:7] reg is_const; // @[TLChannelCompactor.scala:88:25] reg [29:0] const_reg; // @[TLChannelCompactor.scala:89:22] wire [64:0] const_0 = io_beat_bits_head_0 ? io_beat_bits_payload_0 : {35'h0, const_reg}; // @[TLChannelCompactor.scala:89:22, :90:18, :134:7] wire _io_beat_ready_T = ~io_beat_bits_tail_0; // @[TLChannelCompactor.scala:91:33, :134:7] wire _io_beat_ready_T_1 = is_const & _io_beat_ready_T; // @[TLChannelCompactor.scala:88:25, :91:{30,33}] assign _io_beat_ready_T_2 = _io_beat_ready_T_1 \| protocol_ready; // @[TLChannelCompactor.scala:83:22, :91:{30,53}] assign io_beat_ready_0 = _io_beat_ready_T_2; // @[TLChannelCompactor.scala:91:53, :134:7] wire _protocol_valid_T = ~is_const; // @[TLChannelCompactor.scala:88:25, :92:22] wire _protocol_valid_T_1 = _protocol_valid_T \| io_beat_bits_tail_0; // @[TLChannelCompactor.scala:92:{22,32}, :134:7] assign _protocol_valid_T_2 = _protocol_valid_T_1 & io_beat_valid_0; // @[TLChannelCompactor.scala:92:{32,54}, :134:7] assign protocol_valid = _protocol_valid_T_2; // @[TLChannelCompactor.scala:83:22, :92:54] assign protocol_bits_denied = _protocol_bits_denied_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_denied_WIRE = const_0[0]; // @[TLChannelCompactor.scala:90:18, :97:22] assign protocol_bits_sink = _protocol_bits_sink_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_sink_WIRE = const_0[8:1]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13] assign protocol_bits_source = _protocol_bits_source_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_source_WIRE = const_0[16:9]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13] assign protocol_bits_size = _protocol_bits_size_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_size_WIRE = const_0[24:17]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13] assign protocol_bits_param = _protocol_bits_param_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_param_WIRE = const_0[26:25]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13] assign protocol_bits_opcode = _protocol_bits_opcode_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_opcode_WIRE = const_0[29:27]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13] assign protocol_bits_corrupt = _protocol_bits_corrupt_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_corrupt_WIRE = io_beat_bits_payload_0[0]; // @[TLChannelCompactor.scala:97:22, :134:7] assign _protocol_bits_data_WIRE = io_beat_bits_payload_0[64:1]; // @[TLChannelCompactor.scala:97:22, :98:13, :134:7] assign protocol_bits_data = _protocol_bits_data_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] wire _T_12 = io_beat_ready_0 & io_beat_valid_0; // @[Decoupled.scala:51:35] wire _T_11 = _T_12 & io_beat_bits_head_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TLChannelCompactor.scala:134:7] if (reset) // @[TLChannelCompactor.scala:134:7] is_const <= 1'h1; // @[TLChannelCompactor.scala:88:25] else // @[TLChannelCompactor.scala:134:7] is_const <= _T_12 & io_beat_bits_tail_0 \| ~_T_11 & is_const; // @[Decoupled.scala:51:35] if (_T_11) // @[TLChannelCompactor.scala:104:22] const_reg <= io_beat_bits_payload_0[29:0]; // @[TLChannelCompactor.scala:89:22, :104:77, :134:7] always @(posedge) assign io_protocol_valid = io_protocol_valid_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_opcode = io_protocol_bits_opcode_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_param = io_protocol_bits_param_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_size = io_protocol_bits_size_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_source = io_protocol_bits_source_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_sink = io_protocol_bits_sink_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_denied = io_protocol_bits_denied_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_data = io_protocol_bits_data_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_corrupt = io_protocol_bits_corrupt_0; // @[TLChannelCompactor.scala:134:7] assign io_beat_ready = io_beat_ready_0; // @[TLChannelCompactor.scala:134:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_234 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_234( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_28 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, in_vc : UInt<0>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_56 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_28 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0ha), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _T_2 = eq(UInt<4>(0hc), io.in.bits.egress_id) node _T_3 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<3>(0h5) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h0) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0ha), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<4>(0hc), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0hb), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0hc), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0ha), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<4>(0hc), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h5)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) node _T_16 = eq(UInt<3>(0h6), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_18 = and(route_q.io.enq.valid, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_57 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_28 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] node _T_23 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_24 = and(vcalloc_q.io.enq.valid, _T_23) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_25, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _c_T = cat(c_hi, c_lo) node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node _c_T_2 = cat(c_hi_1, c_lo_1) node _c_T_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_channel_oh_0 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 2) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 1, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node _out_bundle_bits_out_virt_channel_T_3 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 1) node _out_bundle_bits_out_virt_channel_T_4 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_3) node _out_bundle_bits_out_virt_channel_T_5 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_4, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_6 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_7 = or(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_6) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<2> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_7 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_28( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [36:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [36:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [3:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [36:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [36:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 4'hA; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'hB; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 4'hC; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 4'hD; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 4'h9 : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'hA : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hB : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'hC : 4'h0); // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h5; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h5; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_acd_router_1ClockSinkDomain : output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_1 connect routers.clock, childClock connect routers.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0 connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1 connect auto.routers_egress_nodes_out.flit.bits, routers.auto.egress_nodes_out.flit.bits connect auto.routers_egress_nodes_out.flit.valid, routers.auto.egress_nodes_out.flit.valid connect routers.auto.egress_nodes_out.flit.ready, auto.routers_egress_nodes_out.flit.ready connect auto.routers_debug_out, routers.auto.debug_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset	module TLSplitACDxBENoC_acd_router_1ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_1 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_egress_nodes_out_flit_ready (auto_routers_egress_nodes_out_flit_ready), .auto_egress_nodes_out_flit_valid (auto_routers_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (auto_routers_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (auto_routers_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (auto_routers_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_18 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_18( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_6 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_6( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN \| ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN \| ~_T_12 \| p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_171 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_171( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_6 : input clock : Clock input reset : Reset output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}} node _legal_address_T = xor(io.paddr, UInt<1>(0h0)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(io.paddr, UInt<21>(0h100000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) node _legal_address_T_25 = xor(io.paddr, UInt<21>(0h110000)) node _legal_address_T_26 = cvt(_legal_address_T_25) node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) node _legal_address_T_28 = asSInt(_legal_address_T_27) node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) node _legal_address_T_30 = xor(io.paddr, UInt<26>(0h2000000)) node _legal_address_T_31 = cvt(_legal_address_T_30) node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000))) node _legal_address_T_33 = asSInt(_legal_address_T_32) node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) node _legal_address_T_35 = xor(io.paddr, UInt<26>(0h2010000)) node _legal_address_T_36 = cvt(_legal_address_T_35) node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) node _legal_address_T_38 = asSInt(_legal_address_T_37) node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) node _legal_address_T_40 = xor(io.paddr, UInt<28>(0h8000000)) node _legal_address_T_41 = cvt(_legal_address_T_40) node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000))) node _legal_address_T_43 = asSInt(_legal_address_T_42) node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) node _legal_address_T_45 = xor(io.paddr, UInt<28>(0hc000000)) node _legal_address_T_46 = cvt(_legal_address_T_45) node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000))) node _legal_address_T_48 = asSInt(_legal_address_T_47) node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10020000)) node _legal_address_T_51 = cvt(_legal_address_T_50) node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) node _legal_address_T_53 = asSInt(_legal_address_T_52) node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) node _legal_address_T_55 = xor(io.paddr, UInt<32>(0h80000000)) node _legal_address_T_56 = cvt(_legal_address_T_55) node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<29>(0h10000000))) node _legal_address_T_58 = asSInt(_legal_address_T_57) node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[12] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 connect _legal_address_WIRE[5], _legal_address_T_29 connect _legal_address_WIRE[6], _legal_address_T_34 connect _legal_address_WIRE[7], _legal_address_T_39 connect _legal_address_WIRE[8], _legal_address_T_44 connect _legal_address_WIRE[9], _legal_address_T_49 connect _legal_address_WIRE[10], _legal_address_T_54 connect _legal_address_WIRE[11], _legal_address_T_59 node _legal_address_T_60 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_61 = or(_legal_address_T_60, _legal_address_WIRE[2]) node _legal_address_T_62 = or(_legal_address_T_61, _legal_address_WIRE[3]) node _legal_address_T_63 = or(_legal_address_T_62, _legal_address_WIRE[4]) node _legal_address_T_64 = or(_legal_address_T_63, _legal_address_WIRE[5]) node _legal_address_T_65 = or(_legal_address_T_64, _legal_address_WIRE[6]) node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[7]) node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[8]) node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[9]) node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[10]) node legal_address = or(_legal_address_T_69, _legal_address_WIRE[11]) node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T) node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2) node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5) node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c011000))) node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7) node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10) node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12) node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_15 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9) node _io_resp_cacheable_T_16 = or(_io_resp_cacheable_T_15, _io_resp_cacheable_T_14) node _io_resp_cacheable_T_17 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_cacheable_T_18 = cvt(_io_resp_cacheable_T_17) node _io_resp_cacheable_T_19 = and(_io_resp_cacheable_T_18, asSInt(UInt<33>(0h8c010000))) node _io_resp_cacheable_T_20 = asSInt(_io_resp_cacheable_T_19) node _io_resp_cacheable_T_21 = eq(_io_resp_cacheable_T_20, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_22 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_cacheable_T_23 = cvt(_io_resp_cacheable_T_22) node _io_resp_cacheable_T_24 = and(_io_resp_cacheable_T_23, asSInt(UInt<33>(0h80000000))) node _io_resp_cacheable_T_25 = asSInt(_io_resp_cacheable_T_24) node _io_resp_cacheable_T_26 = eq(_io_resp_cacheable_T_25, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_27 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_26) node _io_resp_cacheable_T_28 = mux(_io_resp_cacheable_T_16, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_cacheable_T_29 = mux(_io_resp_cacheable_T_27, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_cacheable_T_30 = or(_io_resp_cacheable_T_28, _io_resp_cacheable_T_29) wire _io_resp_cacheable_WIRE : UInt<1> connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_30 node _io_resp_cacheable_T_31 = and(legal_address, _io_resp_cacheable_WIRE) connect io.resp.cacheable, _io_resp_cacheable_T_31 node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_r_T_1 = cvt(_io_resp_r_T) node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0))) node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2) node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0))) node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1)) connect io.resp.r, _io_resp_r_T_5 node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_w_T_1 = cvt(_io_resp_w_T) node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2) node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0))) node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_w_T_6 = cvt(_io_resp_w_T_5) node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7) node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0))) node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_w_T_11 = cvt(_io_resp_w_T_10) node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12) node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0))) node _io_resp_w_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_16 = cvt(_io_resp_w_T_15) node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17) node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0))) node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_21 = cvt(_io_resp_w_T_20) node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22) node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0))) node _io_resp_w_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_w_T_26 = cvt(_io_resp_w_T_25) node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27) node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0))) node _io_resp_w_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_w_T_31 = cvt(_io_resp_w_T_30) node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32) node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0))) node _io_resp_w_T_35 = or(_io_resp_w_T_4, _io_resp_w_T_9) node _io_resp_w_T_36 = or(_io_resp_w_T_35, _io_resp_w_T_14) node _io_resp_w_T_37 = or(_io_resp_w_T_36, _io_resp_w_T_19) node _io_resp_w_T_38 = or(_io_resp_w_T_37, _io_resp_w_T_24) node _io_resp_w_T_39 = or(_io_resp_w_T_38, _io_resp_w_T_29) node _io_resp_w_T_40 = or(_io_resp_w_T_39, _io_resp_w_T_34) node _io_resp_w_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_w_T_42 = cvt(_io_resp_w_T_41) node _io_resp_w_T_43 = and(_io_resp_w_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_44 = asSInt(_io_resp_w_T_43) node _io_resp_w_T_45 = eq(_io_resp_w_T_44, asSInt(UInt<1>(0h0))) node _io_resp_w_T_46 = mux(_io_resp_w_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_w_T_47 = mux(_io_resp_w_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_w_T_48 = or(_io_resp_w_T_46, _io_resp_w_T_47) wire _io_resp_w_WIRE : UInt<1> connect _io_resp_w_WIRE, _io_resp_w_T_48 node _io_resp_w_T_49 = and(legal_address, _io_resp_w_WIRE) connect io.resp.w, _io_resp_w_T_49 node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_pp_T_1 = cvt(_io_resp_pp_T) node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2) node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5) node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7) node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10) node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12) node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15) node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17) node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20) node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22) node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25) node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27) node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30) node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32) node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_35 = or(_io_resp_pp_T_4, _io_resp_pp_T_9) node _io_resp_pp_T_36 = or(_io_resp_pp_T_35, _io_resp_pp_T_14) node _io_resp_pp_T_37 = or(_io_resp_pp_T_36, _io_resp_pp_T_19) node _io_resp_pp_T_38 = or(_io_resp_pp_T_37, _io_resp_pp_T_24) node _io_resp_pp_T_39 = or(_io_resp_pp_T_38, _io_resp_pp_T_29) node _io_resp_pp_T_40 = or(_io_resp_pp_T_39, _io_resp_pp_T_34) node _io_resp_pp_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_pp_T_42 = cvt(_io_resp_pp_T_41) node _io_resp_pp_T_43 = and(_io_resp_pp_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_44 = asSInt(_io_resp_pp_T_43) node _io_resp_pp_T_45 = eq(_io_resp_pp_T_44, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_46 = mux(_io_resp_pp_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_pp_T_47 = mux(_io_resp_pp_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_pp_T_48 = or(_io_resp_pp_T_46, _io_resp_pp_T_47) wire _io_resp_pp_WIRE : UInt<1> connect _io_resp_pp_WIRE, _io_resp_pp_T_48 node _io_resp_pp_T_49 = and(legal_address, _io_resp_pp_WIRE) connect io.resp.pp, _io_resp_pp_T_49 node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_al_T_1 = cvt(_io_resp_al_T) node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2) node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0))) node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_al_T_6 = cvt(_io_resp_al_T_5) node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7) node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0))) node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_al_T_11 = cvt(_io_resp_al_T_10) node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12) node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0))) node _io_resp_al_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_16 = cvt(_io_resp_al_T_15) node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17) node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0))) node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_21 = cvt(_io_resp_al_T_20) node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22) node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0))) node _io_resp_al_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_al_T_26 = cvt(_io_resp_al_T_25) node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27) node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0))) node _io_resp_al_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_al_T_31 = cvt(_io_resp_al_T_30) node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32) node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0))) node _io_resp_al_T_35 = or(_io_resp_al_T_4, _io_resp_al_T_9) node _io_resp_al_T_36 = or(_io_resp_al_T_35, _io_resp_al_T_14) node _io_resp_al_T_37 = or(_io_resp_al_T_36, _io_resp_al_T_19) node _io_resp_al_T_38 = or(_io_resp_al_T_37, _io_resp_al_T_24) node _io_resp_al_T_39 = or(_io_resp_al_T_38, _io_resp_al_T_29) node _io_resp_al_T_40 = or(_io_resp_al_T_39, _io_resp_al_T_34) node _io_resp_al_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_al_T_42 = cvt(_io_resp_al_T_41) node _io_resp_al_T_43 = and(_io_resp_al_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_44 = asSInt(_io_resp_al_T_43) node _io_resp_al_T_45 = eq(_io_resp_al_T_44, asSInt(UInt<1>(0h0))) node _io_resp_al_T_46 = mux(_io_resp_al_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_al_T_47 = mux(_io_resp_al_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_al_T_48 = or(_io_resp_al_T_46, _io_resp_al_T_47) wire _io_resp_al_WIRE : UInt<1> connect _io_resp_al_WIRE, _io_resp_al_T_48 node _io_resp_al_T_49 = and(legal_address, _io_resp_al_WIRE) connect io.resp.al, _io_resp_al_T_49 node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_aa_T_1 = cvt(_io_resp_aa_T) node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2) node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5) node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7) node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10) node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12) node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15) node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17) node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20) node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22) node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25) node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27) node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30) node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32) node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_35 = or(_io_resp_aa_T_4, _io_resp_aa_T_9) node _io_resp_aa_T_36 = or(_io_resp_aa_T_35, _io_resp_aa_T_14) node _io_resp_aa_T_37 = or(_io_resp_aa_T_36, _io_resp_aa_T_19) node _io_resp_aa_T_38 = or(_io_resp_aa_T_37, _io_resp_aa_T_24) node _io_resp_aa_T_39 = or(_io_resp_aa_T_38, _io_resp_aa_T_29) node _io_resp_aa_T_40 = or(_io_resp_aa_T_39, _io_resp_aa_T_34) node _io_resp_aa_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_aa_T_42 = cvt(_io_resp_aa_T_41) node _io_resp_aa_T_43 = and(_io_resp_aa_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_44 = asSInt(_io_resp_aa_T_43) node _io_resp_aa_T_45 = eq(_io_resp_aa_T_44, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_46 = mux(_io_resp_aa_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_aa_T_47 = mux(_io_resp_aa_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_aa_T_48 = or(_io_resp_aa_T_46, _io_resp_aa_T_47) wire _io_resp_aa_WIRE : UInt<1> connect _io_resp_aa_WIRE, _io_resp_aa_T_48 node _io_resp_aa_T_49 = and(legal_address, _io_resp_aa_WIRE) connect io.resp.aa, _io_resp_aa_T_49 node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_x_T_1 = cvt(_io_resp_x_T) node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2) node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0))) node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_x_T_6 = cvt(_io_resp_x_T_5) node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7) node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0))) node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_x_T_11 = cvt(_io_resp_x_T_10) node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12) node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0))) node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_x_T_16 = cvt(_io_resp_x_T_15) node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17) node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0))) node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_x_T_21 = cvt(_io_resp_x_T_20) node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0h90000000))) node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22) node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0))) node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9) node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14) node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19) node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24) node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000)) node _io_resp_x_T_30 = cvt(_io_resp_x_T_29) node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31) node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0))) node _io_resp_x_T_34 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_x_T_35 = cvt(_io_resp_x_T_34) node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0h9e103000))) node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36) node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0))) node _io_resp_x_T_39 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_x_T_40 = cvt(_io_resp_x_T_39) node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41) node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0))) node _io_resp_x_T_44 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_x_T_45 = cvt(_io_resp_x_T_44) node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46) node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0))) node _io_resp_x_T_49 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_x_T_50 = cvt(_io_resp_x_T_49) node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0h9c000000))) node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51) node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0))) node _io_resp_x_T_54 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_x_T_55 = cvt(_io_resp_x_T_54) node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56) node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0))) node _io_resp_x_T_59 = or(_io_resp_x_T_33, _io_resp_x_T_38) node _io_resp_x_T_60 = or(_io_resp_x_T_59, _io_resp_x_T_43) node _io_resp_x_T_61 = or(_io_resp_x_T_60, _io_resp_x_T_48) node _io_resp_x_T_62 = or(_io_resp_x_T_61, _io_resp_x_T_53) node _io_resp_x_T_63 = or(_io_resp_x_T_62, _io_resp_x_T_58) node _io_resp_x_T_64 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_x_T_65 = mux(_io_resp_x_T_63, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_x_T_66 = or(_io_resp_x_T_64, _io_resp_x_T_65) wire _io_resp_x_WIRE : UInt<1> connect _io_resp_x_WIRE, _io_resp_x_T_66 node _io_resp_x_T_67 = and(legal_address, _io_resp_x_WIRE) connect io.resp.x, _io_resp_x_T_67 node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_eff_T_1 = cvt(_io_resp_eff_T) node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0h9e112000))) node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2) node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5) node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0h9e103000))) node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7) node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10) node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12) node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15) node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17) node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_20 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20) node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0h9c000000))) node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22) node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25) node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27) node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_30 = or(_io_resp_eff_T_4, _io_resp_eff_T_9) node _io_resp_eff_T_31 = or(_io_resp_eff_T_30, _io_resp_eff_T_14) node _io_resp_eff_T_32 = or(_io_resp_eff_T_31, _io_resp_eff_T_19) node _io_resp_eff_T_33 = or(_io_resp_eff_T_32, _io_resp_eff_T_24) node _io_resp_eff_T_34 = or(_io_resp_eff_T_33, _io_resp_eff_T_29) node _io_resp_eff_T_35 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_eff_T_36 = cvt(_io_resp_eff_T_35) node _io_resp_eff_T_37 = and(_io_resp_eff_T_36, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_38 = asSInt(_io_resp_eff_T_37) node _io_resp_eff_T_39 = eq(_io_resp_eff_T_38, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_40 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_eff_T_41 = cvt(_io_resp_eff_T_40) node _io_resp_eff_T_42 = and(_io_resp_eff_T_41, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_43 = asSInt(_io_resp_eff_T_42) node _io_resp_eff_T_44 = eq(_io_resp_eff_T_43, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_45 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_eff_T_46 = cvt(_io_resp_eff_T_45) node _io_resp_eff_T_47 = and(_io_resp_eff_T_46, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_48 = asSInt(_io_resp_eff_T_47) node _io_resp_eff_T_49 = eq(_io_resp_eff_T_48, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_50 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_eff_T_51 = cvt(_io_resp_eff_T_50) node _io_resp_eff_T_52 = and(_io_resp_eff_T_51, asSInt(UInt<33>(0h90000000))) node _io_resp_eff_T_53 = asSInt(_io_resp_eff_T_52) node _io_resp_eff_T_54 = eq(_io_resp_eff_T_53, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_55 = or(_io_resp_eff_T_39, _io_resp_eff_T_44) node _io_resp_eff_T_56 = or(_io_resp_eff_T_55, _io_resp_eff_T_49) node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_54) node _io_resp_eff_T_58 = mux(_io_resp_eff_T_34, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59) wire _io_resp_eff_WIRE : UInt<1> connect _io_resp_eff_WIRE, _io_resp_eff_T_60 node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE) connect io.resp.eff, _io_resp_eff_T_61	module PMAChecker_6( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [39:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73] wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19] wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_49; // @[PMA.scala:39:19] wire _io_resp_pp_T_49; // @[PMA.scala:39:19] wire _io_resp_al_T_49; // @[PMA.scala:39:19] wire _io_resp_aa_T_49; // @[PMA.scala:39:19] wire _io_resp_x_T_67; // @[PMA.scala:39:19] wire _io_resp_eff_T_61; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31] assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_41; // @[Parameters.scala:137:31] assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31] assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_41; // @[Parameters.scala:137:31] assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31] assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31] assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31] assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31] assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_50 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31] assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31] assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31] assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31] assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31] assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire _legal_address_T_60 = _legal_address_WIRE_0 \| _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_61 = _legal_address_T_60 \| _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_T_61 \| _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 \| _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_64 = _legal_address_T_63 \| _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_65 = _legal_address_T_64 \| _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_66 = _legal_address_T_65 \| _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_67 = _legal_address_T_66 \| _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_68 = _legal_address_T_67 \| _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_69 = _legal_address_T_68 \| _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_69 \| _legal_address_WIRE_11; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 \| _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 \| _io_resp_cacheable_T_14; // @[Parameters.scala:629:89] wire [40:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 \| _io_resp_cacheable_T_26; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46] wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_35 = _io_resp_w_T_4 \| _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_36 = _io_resp_w_T_35 \| _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_37 = _io_resp_w_T_36 \| _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_38 = _io_resp_w_T_37 \| _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_39 = _io_resp_w_T_38 \| _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_40 = _io_resp_w_T_39 \| _io_resp_w_T_34; // @[Parameters.scala:629:89] wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46] wire _io_resp_w_T_45 = _io_resp_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73] assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_35 = _io_resp_pp_T_4 \| _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_36 = _io_resp_pp_T_35 \| _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_37 = _io_resp_pp_T_36 \| _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_38 = _io_resp_pp_T_37 \| _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 \| _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_40 = _io_resp_pp_T_39 \| _io_resp_pp_T_34; // @[Parameters.scala:629:89] wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46] wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73] assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46] wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_35 = _io_resp_al_T_4 \| _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_36 = _io_resp_al_T_35 \| _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_37 = _io_resp_al_T_36 \| _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_38 = _io_resp_al_T_37 \| _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_39 = _io_resp_al_T_38 \| _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_40 = _io_resp_al_T_39 \| _io_resp_al_T_34; // @[Parameters.scala:629:89] wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46] wire _io_resp_al_T_45 = _io_resp_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73] assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_35 = _io_resp_aa_T_4 \| _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_36 = _io_resp_aa_T_35 \| _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_37 = _io_resp_aa_T_36 \| _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_38 = _io_resp_aa_T_37 \| _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 \| _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_40 = _io_resp_aa_T_39 \| _io_resp_aa_T_34; // @[Parameters.scala:629:89] wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46] wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73] assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 \| _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 \| _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 \| _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 \| _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_59 = _io_resp_x_T_33 \| _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_60 = _io_resp_x_T_59 \| _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_61 = _io_resp_x_T_60 \| _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_62 = _io_resp_x_T_61 \| _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_63 = _io_resp_x_T_62 \| _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73] assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_30 = _io_resp_eff_T_4 \| _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_31 = _io_resp_eff_T_30 \| _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_32 = _io_resp_eff_T_31 \| _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_33 = _io_resp_eff_T_32 \| _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 \| _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73] wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46] wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46] wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46] wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_55 = _io_resp_eff_T_39 \| _io_resp_eff_T_44; // @[Parameters.scala:629:89] wire _io_resp_eff_T_56 = _io_resp_eff_T_55 \| _io_resp_eff_T_49; // @[Parameters.scala:629:89] wire _io_resp_eff_T_57 = _io_resp_eff_T_56 \| _io_resp_eff_T_54; // @[Parameters.scala:629:89] wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73] assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_216 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_216( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_409 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_153 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_409( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_153 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_37 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_77 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_37( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_77 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_127 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_144 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_127( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_144 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_1 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _source_ok_T_2 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 connect _source_ok_WIRE[2], _source_ok_T_2 node _source_ok_T_3 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_3, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_23 = cvt(_T_22) node _T_24 = and(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = asSInt(_T_24) node _T_26 = eq(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = or(_T_21, _T_26) node _T_28 = and(_T_11, _T_19) node _T_29 = and(_T_28, _T_27) node _T_30 = asUInt(reset) node _T_31 = eq(_T_30, UInt<1>(0h0)) when _T_31 : node _T_32 = eq(_T_29, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_29, UInt<1>(0h1), "") : assert_1 node _T_33 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_33 : node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_38 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_40 = or(_T_37, _T_38) node _T_41 = or(_T_40, _T_39) node _T_42 = and(_T_36, _T_41) node _T_43 = or(UInt<1>(0h0), _T_42) node _T_44 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<14>(0h2000))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<13>(0h1000))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<17>(0h10000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<18>(0h2f000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<13>(0h1000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<27>(0h4000000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = or(_T_49, _T_54) node _T_86 = or(_T_85, _T_59) node _T_87 = or(_T_86, _T_64) node _T_88 = or(_T_87, _T_69) node _T_89 = or(_T_88, _T_74) node _T_90 = or(_T_89, _T_79) node _T_91 = or(_T_90, _T_84) node _T_92 = and(_T_44, _T_91) node _T_93 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<29>(0h10000000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = and(_T_94, _T_105) node _T_107 = or(UInt<1>(0h0), _T_92) node _T_108 = or(_T_107, _T_106) node _T_109 = and(_T_43, _T_108) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_109, UInt<1>(0h1), "") : assert_2 node _T_113 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_115 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_113 connect _WIRE[1], _T_114 connect _WIRE[2], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_120 = or(_T_117, _T_118) node _T_121 = or(_T_120, _T_119) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_121 node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = or(UInt<1>(0h0), _T_124) node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = or(_T_130, _T_135) node _T_177 = or(_T_176, _T_140) node _T_178 = or(_T_177, _T_145) node _T_179 = or(_T_178, _T_150) node _T_180 = or(_T_179, _T_155) node _T_181 = or(_T_180, _T_160) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_170) node _T_184 = or(_T_183, _T_175) node _T_185 = and(_T_125, _T_184) node _T_186 = or(UInt<1>(0h0), _T_185) node _T_187 = and(_WIRE_1, _T_186) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_187, UInt<1>(0h1), "") : assert_3 node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(source_ok, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_194 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_194, UInt<1>(0h1), "") : assert_5 node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(is_aligned, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_201, UInt<1>(0h1), "") : assert_7 node _T_205 = not(io.in.a.bits.mask) node _T_206 = eq(_T_205, UInt<1>(0h0)) node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_T_206, UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_206, UInt<1>(0h1), "") : assert_8 node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_210, UInt<1>(0h1), "") : assert_9 node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_214 : node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_219 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_220 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_221 = or(_T_218, _T_219) node _T_222 = or(_T_221, _T_220) node _T_223 = and(_T_217, _T_222) node _T_224 = or(UInt<1>(0h0), _T_223) node _T_225 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<14>(0h2000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<18>(0h2f000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<27>(0h4000000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_230, _T_235) node _T_267 = or(_T_266, _T_240) node _T_268 = or(_T_267, _T_245) node _T_269 = or(_T_268, _T_250) node _T_270 = or(_T_269, _T_255) node _T_271 = or(_T_270, _T_260) node _T_272 = or(_T_271, _T_265) node _T_273 = and(_T_225, _T_272) node _T_274 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<29>(0h10000000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_280, _T_285) node _T_287 = and(_T_275, _T_286) node _T_288 = or(UInt<1>(0h0), _T_273) node _T_289 = or(_T_288, _T_287) node _T_290 = and(_T_224, _T_289) node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(_T_290, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_290, UInt<1>(0h1), "") : assert_10 node _T_294 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_295 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_296 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_294 connect _WIRE_2[1], _T_295 connect _WIRE_2[2], _T_296 node _T_297 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_298 = mux(_WIRE_2[0], _T_297, UInt<1>(0h0)) node _T_299 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_300 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = or(_T_298, _T_299) node _T_302 = or(_T_301, _T_300) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_302 node _T_303 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_304 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_305 = and(_T_303, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<14>(0h2000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_313 = cvt(_T_312) node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000))) node _T_315 = asSInt(_T_314) node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_318 = cvt(_T_317) node _T_319 = and(_T_318, asSInt(UInt<17>(0h10000))) node _T_320 = asSInt(_T_319) node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0))) node _T_322 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<18>(0h2f000))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<17>(0h10000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<27>(0h4000000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<13>(0h1000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<29>(0h10000000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = or(_T_311, _T_316) node _T_358 = or(_T_357, _T_321) node _T_359 = or(_T_358, _T_326) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_336) node _T_362 = or(_T_361, _T_341) node _T_363 = or(_T_362, _T_346) node _T_364 = or(_T_363, _T_351) node _T_365 = or(_T_364, _T_356) node _T_366 = and(_T_306, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_WIRE_3, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_368, UInt<1>(0h1), "") : assert_11 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(source_ok, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_375 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_375, UInt<1>(0h1), "") : assert_13 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(is_aligned, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_382 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_382, UInt<1>(0h1), "") : assert_15 node _T_386 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_386, UInt<1>(0h1), "") : assert_16 node _T_390 = not(io.in.a.bits.mask) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_391, UInt<1>(0h1), "") : assert_17 node _T_395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_395, UInt<1>(0h1), "") : assert_18 node _T_399 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_399 : node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_404 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_405 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_406 = or(_T_403, _T_404) node _T_407 = or(_T_406, _T_405) node _T_408 = and(_T_402, _T_407) node _T_409 = or(UInt<1>(0h0), _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_409, UInt<1>(0h1), "") : assert_19 node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = and(_T_416, _T_421) node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_433 = cvt(_T_432) node _T_434 = and(_T_433, asSInt(UInt<17>(0h10000))) node _T_435 = asSInt(_T_434) node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0))) node _T_437 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_438 = cvt(_T_437) node _T_439 = and(_T_438, asSInt(UInt<18>(0h2f000))) node _T_440 = asSInt(_T_439) node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0))) node _T_442 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_443 = cvt(_T_442) node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000))) node _T_445 = asSInt(_T_444) node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0))) node _T_447 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_453 = cvt(_T_452) node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000))) node _T_455 = asSInt(_T_454) node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0))) node _T_457 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<27>(0h4000000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<29>(0h10000000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = or(_T_431, _T_436) node _T_473 = or(_T_472, _T_441) node _T_474 = or(_T_473, _T_446) node _T_475 = or(_T_474, _T_451) node _T_476 = or(_T_475, _T_456) node _T_477 = or(_T_476, _T_461) node _T_478 = or(_T_477, _T_466) node _T_479 = or(_T_478, _T_471) node _T_480 = and(_T_426, _T_479) node _T_481 = or(UInt<1>(0h0), _T_422) node _T_482 = or(_T_481, _T_480) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_482, UInt<1>(0h1), "") : assert_20 node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(source_ok, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(is_aligned, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_492, UInt<1>(0h1), "") : assert_23 node _T_496 = eq(io.in.a.bits.mask, mask) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_496, UInt<1>(0h1), "") : assert_24 node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_500, UInt<1>(0h1), "") : assert_25 node _T_504 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_504 : node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_509 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_510 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_511 = or(_T_508, _T_509) node _T_512 = or(_T_511, _T_510) node _T_513 = and(_T_507, _T_512) node _T_514 = or(UInt<1>(0h0), _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = and(_T_518, _T_523) node _T_525 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_526 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_527 = and(_T_525, _T_526) node _T_528 = or(UInt<1>(0h0), _T_527) node _T_529 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<14>(0h2000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<18>(0h2f000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<17>(0h10000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<27>(0h4000000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<29>(0h10000000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = or(_T_533, _T_538) node _T_570 = or(_T_569, _T_543) node _T_571 = or(_T_570, _T_548) node _T_572 = or(_T_571, _T_553) node _T_573 = or(_T_572, _T_558) node _T_574 = or(_T_573, _T_563) node _T_575 = or(_T_574, _T_568) node _T_576 = and(_T_528, _T_575) node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = and(_T_577, _T_582) node _T_584 = or(UInt<1>(0h0), _T_524) node _T_585 = or(_T_584, _T_576) node _T_586 = or(_T_585, _T_583) node _T_587 = and(_T_514, _T_586) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_587, UInt<1>(0h1), "") : assert_26 node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(source_ok, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(is_aligned, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_597 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_597, UInt<1>(0h1), "") : assert_29 node _T_601 = eq(io.in.a.bits.mask, mask) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_601, UInt<1>(0h1), "") : assert_30 node _T_605 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_605 : node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_608 = and(_T_606, _T_607) node _T_609 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_610 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_611 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_612 = or(_T_609, _T_610) node _T_613 = or(_T_612, _T_611) node _T_614 = and(_T_608, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<27>(0h4000000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<29>(0h10000000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = or(_T_634, _T_639) node _T_671 = or(_T_670, _T_644) node _T_672 = or(_T_671, _T_649) node _T_673 = or(_T_672, _T_654) node _T_674 = or(_T_673, _T_659) node _T_675 = or(_T_674, _T_664) node _T_676 = or(_T_675, _T_669) node _T_677 = and(_T_629, _T_676) node _T_678 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_680 = cvt(_T_679) node _T_681 = and(_T_680, asSInt(UInt<17>(0h10000))) node _T_682 = asSInt(_T_681) node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0))) node _T_684 = and(_T_678, _T_683) node _T_685 = or(UInt<1>(0h0), _T_625) node _T_686 = or(_T_685, _T_677) node _T_687 = or(_T_686, _T_684) node _T_688 = and(_T_615, _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_688, UInt<1>(0h1), "") : assert_31 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(source_ok, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(is_aligned, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_698, UInt<1>(0h1), "") : assert_34 node _T_702 = not(mask) node _T_703 = and(io.in.a.bits.mask, _T_702) node _T_704 = eq(_T_703, UInt<1>(0h0)) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_704, UInt<1>(0h1), "") : assert_35 node _T_708 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_708 : node _T_709 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_710 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_711 = and(_T_709, _T_710) node _T_712 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_713 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_714 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_715 = or(_T_712, _T_713) node _T_716 = or(_T_715, _T_714) node _T_717 = and(_T_711, _T_716) node _T_718 = or(UInt<1>(0h0), _T_717) node _T_719 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_720 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<14>(0h2000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_749 = cvt(_T_748) node _T_750 = and(_T_749, asSInt(UInt<17>(0h10000))) node _T_751 = asSInt(_T_750) node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0))) node _T_753 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<27>(0h4000000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_764 = cvt(_T_763) node _T_765 = and(_T_764, asSInt(UInt<29>(0h10000000))) node _T_766 = asSInt(_T_765) node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0))) node _T_768 = or(_T_727, _T_732) node _T_769 = or(_T_768, _T_737) node _T_770 = or(_T_769, _T_742) node _T_771 = or(_T_770, _T_747) node _T_772 = or(_T_771, _T_752) node _T_773 = or(_T_772, _T_757) node _T_774 = or(_T_773, _T_762) node _T_775 = or(_T_774, _T_767) node _T_776 = and(_T_722, _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_776) node _T_785 = or(_T_784, _T_783) node _T_786 = and(_T_718, _T_785) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_786, UInt<1>(0h1), "") : assert_36 node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(source_ok, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(is_aligned, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_796 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_796, UInt<1>(0h1), "") : assert_39 node _T_800 = eq(io.in.a.bits.mask, mask) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_800, UInt<1>(0h1), "") : assert_40 node _T_804 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_809 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_810 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_811 = or(_T_808, _T_809) node _T_812 = or(_T_811, _T_810) node _T_813 = and(_T_807, _T_812) node _T_814 = or(UInt<1>(0h0), _T_813) node _T_815 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_816 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_817 = and(_T_815, _T_816) node _T_818 = or(UInt<1>(0h0), _T_817) node _T_819 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<14>(0h2000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<18>(0h2f000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<17>(0h10000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<29>(0h10000000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = or(_T_823, _T_828) node _T_865 = or(_T_864, _T_833) node _T_866 = or(_T_865, _T_838) node _T_867 = or(_T_866, _T_843) node _T_868 = or(_T_867, _T_848) node _T_869 = or(_T_868, _T_853) node _T_870 = or(_T_869, _T_858) node _T_871 = or(_T_870, _T_863) node _T_872 = and(_T_818, _T_871) node _T_873 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_874 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<17>(0h10000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = and(_T_873, _T_878) node _T_880 = or(UInt<1>(0h0), _T_872) node _T_881 = or(_T_880, _T_879) node _T_882 = and(_T_814, _T_881) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_882, UInt<1>(0h1), "") : assert_41 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(is_aligned, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_892, UInt<1>(0h1), "") : assert_44 node _T_896 = eq(io.in.a.bits.mask, mask) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_896, UInt<1>(0h1), "") : assert_45 node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_905 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_906 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_907 = or(_T_904, _T_905) node _T_908 = or(_T_907, _T_906) node _T_909 = and(_T_903, _T_908) node _T_910 = or(UInt<1>(0h0), _T_909) node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_912 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_913 = and(_T_911, _T_912) node _T_914 = or(UInt<1>(0h0), _T_913) node _T_915 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<13>(0h1000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = and(_T_914, _T_919) node _T_921 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<14>(0h2000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_948 = cvt(_T_947) node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000))) node _T_950 = asSInt(_T_949) node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0))) node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_953 = cvt(_T_952) node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000))) node _T_955 = asSInt(_T_954) node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0))) node _T_957 = or(_T_926, _T_931) node _T_958 = or(_T_957, _T_936) node _T_959 = or(_T_958, _T_941) node _T_960 = or(_T_959, _T_946) node _T_961 = or(_T_960, _T_951) node _T_962 = or(_T_961, _T_956) node _T_963 = and(_T_921, _T_962) node _T_964 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_965 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_966 = and(_T_964, _T_965) node _T_967 = or(UInt<1>(0h0), _T_966) node _T_968 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_969 = cvt(_T_968) node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000))) node _T_971 = asSInt(_T_970) node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0))) node _T_973 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_974 = cvt(_T_973) node _T_975 = and(_T_974, asSInt(UInt<29>(0h10000000))) node _T_976 = asSInt(_T_975) node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0))) node _T_978 = or(_T_972, _T_977) node _T_979 = and(_T_967, _T_978) node _T_980 = or(UInt<1>(0h0), _T_920) node _T_981 = or(_T_980, _T_963) node _T_982 = or(_T_981, _T_979) node _T_983 = and(_T_910, _T_982) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_983, UInt<1>(0h1), "") : assert_46 node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(source_ok, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(is_aligned, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_993 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_993, UInt<1>(0h1), "") : assert_49 node _T_997 = eq(io.in.a.bits.mask, mask) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_997, UInt<1>(0h1), "") : assert_50 node _T_1001 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1005 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_52 node _source_ok_T_4 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.d.bits.source, UInt<1>(0h1)) node _source_ok_T_6 = eq(io.in.d.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_4 connect _source_ok_WIRE_1[1], _source_ok_T_5 connect _source_ok_WIRE_1[2], _source_ok_T_6 node _source_ok_T_7 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_7, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1009 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1009 : node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(source_ok_1, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_54 node _T_1017 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_55 node _T_1021 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_56 node _T_1025 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_57 node _T_1029 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1029 : node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(source_ok_1, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(sink_ok, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1036 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_60 node _T_1040 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_61 node _T_1044 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_62 node _T_1048 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_63 node _T_1052 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1053 = or(UInt<1>(0h1), _T_1052) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_64 node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1057 : node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(source_ok_1, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(sink_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1064 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_67 node _T_1068 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_68 node _T_1072 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_69 node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1077 = or(_T_1076, io.in.d.bits.corrupt) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_70 node _T_1081 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1082 = or(UInt<1>(0h1), _T_1081) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_71 node _T_1086 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1086 : node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(source_ok_1, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1090 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_73 node _T_1094 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_74 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(UInt<1>(0h1), _T_1098) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_75 node _T_1103 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1103 : node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(source_ok_1, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1107 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_T_1107, UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1107, UInt<1>(0h1), "") : assert_77 node _T_1111 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1112 = or(_T_1111, io.in.d.bits.corrupt) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_78 node _T_1116 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1117 = or(UInt<1>(0h1), _T_1116) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_79 node _T_1121 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1121 : node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(source_ok_1, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1125 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_81 node _T_1129 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_82 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(UInt<1>(0h1), _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1138 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_84 node _T_1142 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) node _T_1144 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = or(_T_1143, _T_1148) node _T_1150 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<1>(0h0))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = or(_T_1151, _T_1156) node _T_1158 = eq(io.in.b.bits.source, UInt<2>(0h2)) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) node _T_1160 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1161 = cvt(_T_1160) node _T_1162 = and(_T_1161, asSInt(UInt<1>(0h0))) node _T_1163 = asSInt(_T_1162) node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0))) node _T_1165 = or(_T_1159, _T_1164) node _T_1166 = and(_T_1149, _T_1157) node _T_1167 = and(_T_1166, _T_1165) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _legal_source_T_2 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 connect _legal_source_WIRE[2], _legal_source_T_2 node _legal_source_T_3 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_4 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_5 = mux(_legal_source_WIRE[2], UInt<2>(0h2), UInt<1>(0h0)) node _legal_source_T_6 = or(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_7 = or(_legal_source_T_6, _legal_source_T_5) wire _legal_source_WIRE_1 : UInt<2> connect _legal_source_WIRE_1, _legal_source_T_7 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1171 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1171 : node _T_1172 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1173 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1174 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1172 connect _WIRE_4[1], _T_1173 connect _WIRE_4[2], _T_1174 node _T_1175 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1176 = mux(_WIRE_4[0], _T_1175, UInt<1>(0h0)) node _T_1177 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1178 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1179 = or(_T_1176, _T_1177) node _T_1180 = or(_T_1179, _T_1178) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1180 node _T_1181 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1182 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1183 = and(_T_1181, _T_1182) node _T_1184 = or(UInt<1>(0h0), _T_1183) node _T_1185 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1186 = cvt(_T_1185) node _T_1187 = and(_T_1186, asSInt(UInt<14>(0h2000))) node _T_1188 = asSInt(_T_1187) node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0))) node _T_1190 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<13>(0h1000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<17>(0h10000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1201 = cvt(_T_1200) node _T_1202 = and(_T_1201, asSInt(UInt<18>(0h2f000))) node _T_1203 = asSInt(_T_1202) node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0))) node _T_1205 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1206 = cvt(_T_1205) node _T_1207 = and(_T_1206, asSInt(UInt<17>(0h10000))) node _T_1208 = asSInt(_T_1207) node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0))) node _T_1210 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1211 = cvt(_T_1210) node _T_1212 = and(_T_1211, asSInt(UInt<13>(0h1000))) node _T_1213 = asSInt(_T_1212) node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1216 = cvt(_T_1215) node _T_1217 = and(_T_1216, asSInt(UInt<17>(0h10000))) node _T_1218 = asSInt(_T_1217) node _T_1219 = eq(_T_1218, asSInt(UInt<1>(0h0))) node _T_1220 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<27>(0h4000000))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<29>(0h10000000))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1189, _T_1194) node _T_1236 = or(_T_1235, _T_1199) node _T_1237 = or(_T_1236, _T_1204) node _T_1238 = or(_T_1237, _T_1209) node _T_1239 = or(_T_1238, _T_1214) node _T_1240 = or(_T_1239, _T_1219) node _T_1241 = or(_T_1240, _T_1224) node _T_1242 = or(_T_1241, _T_1229) node _T_1243 = or(_T_1242, _T_1234) node _T_1244 = and(_T_1184, _T_1243) node _T_1245 = or(UInt<1>(0h0), _T_1244) node _T_1246 = and(_WIRE_5, _T_1245) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_86 node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(address_ok, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(legal_source, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1259 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_90 node _T_1263 = eq(io.in.b.bits.mask, mask_1) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_91 node _T_1267 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(_T_1267, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1267, UInt<1>(0h1), "") : assert_92 node _T_1271 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1271 : node _T_1272 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1273 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1274 = and(_T_1272, _T_1273) node _T_1275 = or(UInt<1>(0h0), _T_1274) node _T_1276 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1277 = cvt(_T_1276) node _T_1278 = and(_T_1277, asSInt(UInt<14>(0h2000))) node _T_1279 = asSInt(_T_1278) node _T_1280 = eq(_T_1279, asSInt(UInt<1>(0h0))) node _T_1281 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1282 = cvt(_T_1281) node _T_1283 = and(_T_1282, asSInt(UInt<13>(0h1000))) node _T_1284 = asSInt(_T_1283) node _T_1285 = eq(_T_1284, asSInt(UInt<1>(0h0))) node _T_1286 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1287 = cvt(_T_1286) node _T_1288 = and(_T_1287, asSInt(UInt<17>(0h10000))) node _T_1289 = asSInt(_T_1288) node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0))) node _T_1291 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1292 = cvt(_T_1291) node _T_1293 = and(_T_1292, asSInt(UInt<18>(0h2f000))) node _T_1294 = asSInt(_T_1293) node _T_1295 = eq(_T_1294, asSInt(UInt<1>(0h0))) node _T_1296 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1297 = cvt(_T_1296) node _T_1298 = and(_T_1297, asSInt(UInt<17>(0h10000))) node _T_1299 = asSInt(_T_1298) node _T_1300 = eq(_T_1299, asSInt(UInt<1>(0h0))) node _T_1301 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1302 = cvt(_T_1301) node _T_1303 = and(_T_1302, asSInt(UInt<13>(0h1000))) node _T_1304 = asSInt(_T_1303) node _T_1305 = eq(_T_1304, asSInt(UInt<1>(0h0))) node _T_1306 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1307 = cvt(_T_1306) node _T_1308 = and(_T_1307, asSInt(UInt<17>(0h10000))) node _T_1309 = asSInt(_T_1308) node _T_1310 = eq(_T_1309, asSInt(UInt<1>(0h0))) node _T_1311 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1312 = cvt(_T_1311) node _T_1313 = and(_T_1312, asSInt(UInt<27>(0h4000000))) node _T_1314 = asSInt(_T_1313) node _T_1315 = eq(_T_1314, asSInt(UInt<1>(0h0))) node _T_1316 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1317 = cvt(_T_1316) node _T_1318 = and(_T_1317, asSInt(UInt<13>(0h1000))) node _T_1319 = asSInt(_T_1318) node _T_1320 = eq(_T_1319, asSInt(UInt<1>(0h0))) node _T_1321 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1322 = cvt(_T_1321) node _T_1323 = and(_T_1322, asSInt(UInt<29>(0h10000000))) node _T_1324 = asSInt(_T_1323) node _T_1325 = eq(_T_1324, asSInt(UInt<1>(0h0))) node _T_1326 = or(_T_1280, _T_1285) node _T_1327 = or(_T_1326, _T_1290) node _T_1328 = or(_T_1327, _T_1295) node _T_1329 = or(_T_1328, _T_1300) node _T_1330 = or(_T_1329, _T_1305) node _T_1331 = or(_T_1330, _T_1310) node _T_1332 = or(_T_1331, _T_1315) node _T_1333 = or(_T_1332, _T_1320) node _T_1334 = or(_T_1333, _T_1325) node _T_1335 = and(_T_1275, _T_1334) node _T_1336 = or(UInt<1>(0h0), _T_1335) node _T_1337 = and(UInt<1>(0h0), _T_1336) node _T_1338 = asUInt(reset) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) when _T_1339 : node _T_1340 = eq(_T_1337, UInt<1>(0h0)) when _T_1340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1337, UInt<1>(0h1), "") : assert_93 node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(address_ok, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(legal_source, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1350 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_97 node _T_1354 = eq(io.in.b.bits.mask, mask_1) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_98 node _T_1358 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_99 node _T_1362 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1362 : node _T_1363 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1364 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1365 = and(_T_1363, _T_1364) node _T_1366 = or(UInt<1>(0h0), _T_1365) node _T_1367 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1368 = cvt(_T_1367) node _T_1369 = and(_T_1368, asSInt(UInt<14>(0h2000))) node _T_1370 = asSInt(_T_1369) node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0))) node _T_1372 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1373 = cvt(_T_1372) node _T_1374 = and(_T_1373, asSInt(UInt<13>(0h1000))) node _T_1375 = asSInt(_T_1374) node _T_1376 = eq(_T_1375, asSInt(UInt<1>(0h0))) node _T_1377 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h10000))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<18>(0h2f000))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1388 = cvt(_T_1387) node _T_1389 = and(_T_1388, asSInt(UInt<17>(0h10000))) node _T_1390 = asSInt(_T_1389) node _T_1391 = eq(_T_1390, asSInt(UInt<1>(0h0))) node _T_1392 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1393 = cvt(_T_1392) node _T_1394 = and(_T_1393, asSInt(UInt<13>(0h1000))) node _T_1395 = asSInt(_T_1394) node _T_1396 = eq(_T_1395, asSInt(UInt<1>(0h0))) node _T_1397 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1398 = cvt(_T_1397) node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000))) node _T_1400 = asSInt(_T_1399) node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0))) node _T_1402 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1403 = cvt(_T_1402) node _T_1404 = and(_T_1403, asSInt(UInt<27>(0h4000000))) node _T_1405 = asSInt(_T_1404) node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0))) node _T_1407 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1408 = cvt(_T_1407) node _T_1409 = and(_T_1408, asSInt(UInt<13>(0h1000))) node _T_1410 = asSInt(_T_1409) node _T_1411 = eq(_T_1410, asSInt(UInt<1>(0h0))) node _T_1412 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1413 = cvt(_T_1412) node _T_1414 = and(_T_1413, asSInt(UInt<29>(0h10000000))) node _T_1415 = asSInt(_T_1414) node _T_1416 = eq(_T_1415, asSInt(UInt<1>(0h0))) node _T_1417 = or(_T_1371, _T_1376) node _T_1418 = or(_T_1417, _T_1381) node _T_1419 = or(_T_1418, _T_1386) node _T_1420 = or(_T_1419, _T_1391) node _T_1421 = or(_T_1420, _T_1396) node _T_1422 = or(_T_1421, _T_1401) node _T_1423 = or(_T_1422, _T_1406) node _T_1424 = or(_T_1423, _T_1411) node _T_1425 = or(_T_1424, _T_1416) node _T_1426 = and(_T_1366, _T_1425) node _T_1427 = or(UInt<1>(0h0), _T_1426) node _T_1428 = and(UInt<1>(0h0), _T_1427) node _T_1429 = asUInt(reset) node _T_1430 = eq(_T_1429, UInt<1>(0h0)) when _T_1430 : node _T_1431 = eq(_T_1428, UInt<1>(0h0)) when _T_1431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1428, UInt<1>(0h1), "") : assert_100 node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(address_ok, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1435 = asUInt(reset) node _T_1436 = eq(_T_1435, UInt<1>(0h0)) when _T_1436 : node _T_1437 = eq(legal_source, UInt<1>(0h0)) when _T_1437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1441 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_104 node _T_1445 = eq(io.in.b.bits.mask, mask_1) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_105 node _T_1449 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1449 : node _T_1450 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1451 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1452 = and(_T_1450, _T_1451) node _T_1453 = or(UInt<1>(0h0), _T_1452) node _T_1454 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1455 = cvt(_T_1454) node _T_1456 = and(_T_1455, asSInt(UInt<14>(0h2000))) node _T_1457 = asSInt(_T_1456) node _T_1458 = eq(_T_1457, asSInt(UInt<1>(0h0))) node _T_1459 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1460 = cvt(_T_1459) node _T_1461 = and(_T_1460, asSInt(UInt<13>(0h1000))) node _T_1462 = asSInt(_T_1461) node _T_1463 = eq(_T_1462, asSInt(UInt<1>(0h0))) node _T_1464 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1465 = cvt(_T_1464) node _T_1466 = and(_T_1465, asSInt(UInt<17>(0h10000))) node _T_1467 = asSInt(_T_1466) node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0))) node _T_1469 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1470 = cvt(_T_1469) node _T_1471 = and(_T_1470, asSInt(UInt<18>(0h2f000))) node _T_1472 = asSInt(_T_1471) node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0))) node _T_1474 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<17>(0h10000))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1480 = cvt(_T_1479) node _T_1481 = and(_T_1480, asSInt(UInt<13>(0h1000))) node _T_1482 = asSInt(_T_1481) node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0))) node _T_1484 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1485 = cvt(_T_1484) node _T_1486 = and(_T_1485, asSInt(UInt<17>(0h10000))) node _T_1487 = asSInt(_T_1486) node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0))) node _T_1489 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<27>(0h4000000))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1495 = cvt(_T_1494) node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000))) node _T_1497 = asSInt(_T_1496) node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0))) node _T_1499 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1500 = cvt(_T_1499) node _T_1501 = and(_T_1500, asSInt(UInt<29>(0h10000000))) node _T_1502 = asSInt(_T_1501) node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0))) node _T_1504 = or(_T_1458, _T_1463) node _T_1505 = or(_T_1504, _T_1468) node _T_1506 = or(_T_1505, _T_1473) node _T_1507 = or(_T_1506, _T_1478) node _T_1508 = or(_T_1507, _T_1483) node _T_1509 = or(_T_1508, _T_1488) node _T_1510 = or(_T_1509, _T_1493) node _T_1511 = or(_T_1510, _T_1498) node _T_1512 = or(_T_1511, _T_1503) node _T_1513 = and(_T_1453, _T_1512) node _T_1514 = or(UInt<1>(0h0), _T_1513) node _T_1515 = and(UInt<1>(0h0), _T_1514) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_106 node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(address_ok, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(legal_source, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1528 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_110 node _T_1532 = not(mask_1) node _T_1533 = and(io.in.b.bits.mask, _T_1532) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_111 node _T_1538 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1538 : node _T_1539 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1540 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1541 = and(_T_1539, _T_1540) node _T_1542 = or(UInt<1>(0h0), _T_1541) node _T_1543 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1544 = cvt(_T_1543) node _T_1545 = and(_T_1544, asSInt(UInt<14>(0h2000))) node _T_1546 = asSInt(_T_1545) node _T_1547 = eq(_T_1546, asSInt(UInt<1>(0h0))) node _T_1548 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1549 = cvt(_T_1548) node _T_1550 = and(_T_1549, asSInt(UInt<13>(0h1000))) node _T_1551 = asSInt(_T_1550) node _T_1552 = eq(_T_1551, asSInt(UInt<1>(0h0))) node _T_1553 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1554 = cvt(_T_1553) node _T_1555 = and(_T_1554, asSInt(UInt<17>(0h10000))) node _T_1556 = asSInt(_T_1555) node _T_1557 = eq(_T_1556, asSInt(UInt<1>(0h0))) node _T_1558 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1559 = cvt(_T_1558) node _T_1560 = and(_T_1559, asSInt(UInt<18>(0h2f000))) node _T_1561 = asSInt(_T_1560) node _T_1562 = eq(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1564 = cvt(_T_1563) node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000))) node _T_1566 = asSInt(_T_1565) node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0))) node _T_1568 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<13>(0h1000))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1574 = cvt(_T_1573) node _T_1575 = and(_T_1574, asSInt(UInt<17>(0h10000))) node _T_1576 = asSInt(_T_1575) node _T_1577 = eq(_T_1576, asSInt(UInt<1>(0h0))) node _T_1578 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1579 = cvt(_T_1578) node _T_1580 = and(_T_1579, asSInt(UInt<27>(0h4000000))) node _T_1581 = asSInt(_T_1580) node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0))) node _T_1583 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1584 = cvt(_T_1583) node _T_1585 = and(_T_1584, asSInt(UInt<13>(0h1000))) node _T_1586 = asSInt(_T_1585) node _T_1587 = eq(_T_1586, asSInt(UInt<1>(0h0))) node _T_1588 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1589 = cvt(_T_1588) node _T_1590 = and(_T_1589, asSInt(UInt<29>(0h10000000))) node _T_1591 = asSInt(_T_1590) node _T_1592 = eq(_T_1591, asSInt(UInt<1>(0h0))) node _T_1593 = or(_T_1547, _T_1552) node _T_1594 = or(_T_1593, _T_1557) node _T_1595 = or(_T_1594, _T_1562) node _T_1596 = or(_T_1595, _T_1567) node _T_1597 = or(_T_1596, _T_1572) node _T_1598 = or(_T_1597, _T_1577) node _T_1599 = or(_T_1598, _T_1582) node _T_1600 = or(_T_1599, _T_1587) node _T_1601 = or(_T_1600, _T_1592) node _T_1602 = and(_T_1542, _T_1601) node _T_1603 = or(UInt<1>(0h0), _T_1602) node _T_1604 = and(UInt<1>(0h0), _T_1603) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_112 node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(address_ok, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(legal_source, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1617 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_116 node _T_1621 = eq(io.in.b.bits.mask, mask_1) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_117 node _T_1625 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1625 : node _T_1626 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1627 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1628 = and(_T_1626, _T_1627) node _T_1629 = or(UInt<1>(0h0), _T_1628) node _T_1630 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1631 = cvt(_T_1630) node _T_1632 = and(_T_1631, asSInt(UInt<14>(0h2000))) node _T_1633 = asSInt(_T_1632) node _T_1634 = eq(_T_1633, asSInt(UInt<1>(0h0))) node _T_1635 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1636 = cvt(_T_1635) node _T_1637 = and(_T_1636, asSInt(UInt<13>(0h1000))) node _T_1638 = asSInt(_T_1637) node _T_1639 = eq(_T_1638, asSInt(UInt<1>(0h0))) node _T_1640 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1641 = cvt(_T_1640) node _T_1642 = and(_T_1641, asSInt(UInt<17>(0h10000))) node _T_1643 = asSInt(_T_1642) node _T_1644 = eq(_T_1643, asSInt(UInt<1>(0h0))) node _T_1645 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1646 = cvt(_T_1645) node _T_1647 = and(_T_1646, asSInt(UInt<18>(0h2f000))) node _T_1648 = asSInt(_T_1647) node _T_1649 = eq(_T_1648, asSInt(UInt<1>(0h0))) node _T_1650 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1651 = cvt(_T_1650) node _T_1652 = and(_T_1651, asSInt(UInt<17>(0h10000))) node _T_1653 = asSInt(_T_1652) node _T_1654 = eq(_T_1653, asSInt(UInt<1>(0h0))) node _T_1655 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1656 = cvt(_T_1655) node _T_1657 = and(_T_1656, asSInt(UInt<13>(0h1000))) node _T_1658 = asSInt(_T_1657) node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0))) node _T_1660 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1661 = cvt(_T_1660) node _T_1662 = and(_T_1661, asSInt(UInt<17>(0h10000))) node _T_1663 = asSInt(_T_1662) node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0))) node _T_1665 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1666 = cvt(_T_1665) node _T_1667 = and(_T_1666, asSInt(UInt<27>(0h4000000))) node _T_1668 = asSInt(_T_1667) node _T_1669 = eq(_T_1668, asSInt(UInt<1>(0h0))) node _T_1670 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1671 = cvt(_T_1670) node _T_1672 = and(_T_1671, asSInt(UInt<13>(0h1000))) node _T_1673 = asSInt(_T_1672) node _T_1674 = eq(_T_1673, asSInt(UInt<1>(0h0))) node _T_1675 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1676 = cvt(_T_1675) node _T_1677 = and(_T_1676, asSInt(UInt<29>(0h10000000))) node _T_1678 = asSInt(_T_1677) node _T_1679 = eq(_T_1678, asSInt(UInt<1>(0h0))) node _T_1680 = or(_T_1634, _T_1639) node _T_1681 = or(_T_1680, _T_1644) node _T_1682 = or(_T_1681, _T_1649) node _T_1683 = or(_T_1682, _T_1654) node _T_1684 = or(_T_1683, _T_1659) node _T_1685 = or(_T_1684, _T_1664) node _T_1686 = or(_T_1685, _T_1669) node _T_1687 = or(_T_1686, _T_1674) node _T_1688 = or(_T_1687, _T_1679) node _T_1689 = and(_T_1629, _T_1688) node _T_1690 = or(UInt<1>(0h0), _T_1689) node _T_1691 = and(UInt<1>(0h0), _T_1690) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_118 node _T_1695 = asUInt(reset) node _T_1696 = eq(_T_1695, UInt<1>(0h0)) when _T_1696 : node _T_1697 = eq(address_ok, UInt<1>(0h0)) when _T_1697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1698 = asUInt(reset) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) when _T_1699 : node _T_1700 = eq(legal_source, UInt<1>(0h0)) when _T_1700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1701 = asUInt(reset) node _T_1702 = eq(_T_1701, UInt<1>(0h0)) when _T_1702 : node _T_1703 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1704 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(_T_1704, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1704, UInt<1>(0h1), "") : assert_122 node _T_1708 = eq(io.in.b.bits.mask, mask_1) node _T_1709 = asUInt(reset) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(_T_1708, UInt<1>(0h0)) when _T_1711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1708, UInt<1>(0h1), "") : assert_123 node _T_1712 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1712 : node _T_1713 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1714 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1715 = and(_T_1713, _T_1714) node _T_1716 = or(UInt<1>(0h0), _T_1715) node _T_1717 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1718 = cvt(_T_1717) node _T_1719 = and(_T_1718, asSInt(UInt<14>(0h2000))) node _T_1720 = asSInt(_T_1719) node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0))) node _T_1722 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1723 = cvt(_T_1722) node _T_1724 = and(_T_1723, asSInt(UInt<13>(0h1000))) node _T_1725 = asSInt(_T_1724) node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0))) node _T_1727 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1728 = cvt(_T_1727) node _T_1729 = and(_T_1728, asSInt(UInt<17>(0h10000))) node _T_1730 = asSInt(_T_1729) node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0))) node _T_1732 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1733 = cvt(_T_1732) node _T_1734 = and(_T_1733, asSInt(UInt<18>(0h2f000))) node _T_1735 = asSInt(_T_1734) node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0))) node _T_1737 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1738 = cvt(_T_1737) node _T_1739 = and(_T_1738, asSInt(UInt<17>(0h10000))) node _T_1740 = asSInt(_T_1739) node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0))) node _T_1742 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1743 = cvt(_T_1742) node _T_1744 = and(_T_1743, asSInt(UInt<13>(0h1000))) node _T_1745 = asSInt(_T_1744) node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1748 = cvt(_T_1747) node _T_1749 = and(_T_1748, asSInt(UInt<17>(0h10000))) node _T_1750 = asSInt(_T_1749) node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0))) node _T_1752 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<27>(0h4000000))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1758 = cvt(_T_1757) node _T_1759 = and(_T_1758, asSInt(UInt<13>(0h1000))) node _T_1760 = asSInt(_T_1759) node _T_1761 = eq(_T_1760, asSInt(UInt<1>(0h0))) node _T_1762 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<29>(0h10000000))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1721, _T_1726) node _T_1768 = or(_T_1767, _T_1731) node _T_1769 = or(_T_1768, _T_1736) node _T_1770 = or(_T_1769, _T_1741) node _T_1771 = or(_T_1770, _T_1746) node _T_1772 = or(_T_1771, _T_1751) node _T_1773 = or(_T_1772, _T_1756) node _T_1774 = or(_T_1773, _T_1761) node _T_1775 = or(_T_1774, _T_1766) node _T_1776 = and(_T_1716, _T_1775) node _T_1777 = or(UInt<1>(0h0), _T_1776) node _T_1778 = and(UInt<1>(0h0), _T_1777) node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(_T_1778, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1778, UInt<1>(0h1), "") : assert_124 node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(address_ok, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1785 = asUInt(reset) node _T_1786 = eq(_T_1785, UInt<1>(0h0)) when _T_1786 : node _T_1787 = eq(legal_source, UInt<1>(0h0)) when _T_1787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1791 = eq(io.in.b.bits.mask, mask_1) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_128 node _T_1795 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1796 = asUInt(reset) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) when _T_1797 : node _T_1798 = eq(_T_1795, UInt<1>(0h0)) when _T_1798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1795, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1799 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_130 node _source_ok_T_8 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_9 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _source_ok_T_10 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_8 connect _source_ok_WIRE_2[1], _source_ok_T_9 connect _source_ok_WIRE_2[2], _source_ok_T_10 node _source_ok_T_11 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_11, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _T_1803 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) node _T_1805 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1806 = cvt(_T_1805) node _T_1807 = and(_T_1806, asSInt(UInt<1>(0h0))) node _T_1808 = asSInt(_T_1807) node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0))) node _T_1810 = or(_T_1804, _T_1809) node _T_1811 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1812 = eq(_T_1811, UInt<1>(0h0)) node _T_1813 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1814 = cvt(_T_1813) node _T_1815 = and(_T_1814, asSInt(UInt<1>(0h0))) node _T_1816 = asSInt(_T_1815) node _T_1817 = eq(_T_1816, asSInt(UInt<1>(0h0))) node _T_1818 = or(_T_1812, _T_1817) node _T_1819 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1820 = eq(_T_1819, UInt<1>(0h0)) node _T_1821 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1822 = cvt(_T_1821) node _T_1823 = and(_T_1822, asSInt(UInt<1>(0h0))) node _T_1824 = asSInt(_T_1823) node _T_1825 = eq(_T_1824, asSInt(UInt<1>(0h0))) node _T_1826 = or(_T_1820, _T_1825) node _T_1827 = and(_T_1810, _T_1818) node _T_1828 = and(_T_1827, _T_1826) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_131 node _T_1832 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1832 : node _T_1833 = asUInt(reset) node _T_1834 = eq(_T_1833, UInt<1>(0h0)) when _T_1834 : node _T_1835 = eq(address_ok_1, UInt<1>(0h0)) when _T_1835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1836 = asUInt(reset) node _T_1837 = eq(_T_1836, UInt<1>(0h0)) when _T_1837 : node _T_1838 = eq(source_ok_2, UInt<1>(0h0)) when _T_1838 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1839 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1840 = asUInt(reset) node _T_1841 = eq(_T_1840, UInt<1>(0h0)) when _T_1841 : node _T_1842 = eq(_T_1839, UInt<1>(0h0)) when _T_1842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1839, UInt<1>(0h1), "") : assert_134 node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1846 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_136 node _T_1850 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(_T_1850, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1850, UInt<1>(0h1), "") : assert_137 node _T_1854 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1854 : node _T_1855 = asUInt(reset) node _T_1856 = eq(_T_1855, UInt<1>(0h0)) when _T_1856 : node _T_1857 = eq(address_ok_1, UInt<1>(0h0)) when _T_1857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(source_ok_2, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1861 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(_T_1861, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1861, UInt<1>(0h1), "") : assert_140 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1868 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_142 node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1872 : node _T_1873 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1874 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1875 = and(_T_1873, _T_1874) node _T_1876 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1877 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1878 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1879 = or(_T_1876, _T_1877) node _T_1880 = or(_T_1879, _T_1878) node _T_1881 = and(_T_1875, _T_1880) node _T_1882 = or(UInt<1>(0h0), _T_1881) node _T_1883 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1884 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1885 = cvt(_T_1884) node _T_1886 = and(_T_1885, asSInt(UInt<14>(0h2000))) node _T_1887 = asSInt(_T_1886) node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0))) node _T_1889 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1890 = cvt(_T_1889) node _T_1891 = and(_T_1890, asSInt(UInt<13>(0h1000))) node _T_1892 = asSInt(_T_1891) node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1895 = cvt(_T_1894) node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000))) node _T_1897 = asSInt(_T_1896) node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0))) node _T_1899 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1900 = cvt(_T_1899) node _T_1901 = and(_T_1900, asSInt(UInt<18>(0h2f000))) node _T_1902 = asSInt(_T_1901) node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1905 = cvt(_T_1904) node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000))) node _T_1907 = asSInt(_T_1906) node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1910 = cvt(_T_1909) node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000))) node _T_1912 = asSInt(_T_1911) node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0))) node _T_1914 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1915 = cvt(_T_1914) node _T_1916 = and(_T_1915, asSInt(UInt<27>(0h4000000))) node _T_1917 = asSInt(_T_1916) node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0))) node _T_1919 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1920 = cvt(_T_1919) node _T_1921 = and(_T_1920, asSInt(UInt<13>(0h1000))) node _T_1922 = asSInt(_T_1921) node _T_1923 = eq(_T_1922, asSInt(UInt<1>(0h0))) node _T_1924 = or(_T_1888, _T_1893) node _T_1925 = or(_T_1924, _T_1898) node _T_1926 = or(_T_1925, _T_1903) node _T_1927 = or(_T_1926, _T_1908) node _T_1928 = or(_T_1927, _T_1913) node _T_1929 = or(_T_1928, _T_1918) node _T_1930 = or(_T_1929, _T_1923) node _T_1931 = and(_T_1883, _T_1930) node _T_1932 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1933 = or(UInt<1>(0h0), _T_1932) node _T_1934 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1935 = cvt(_T_1934) node _T_1936 = and(_T_1935, asSInt(UInt<17>(0h10000))) node _T_1937 = asSInt(_T_1936) node _T_1938 = eq(_T_1937, asSInt(UInt<1>(0h0))) node _T_1939 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1940 = cvt(_T_1939) node _T_1941 = and(_T_1940, asSInt(UInt<29>(0h10000000))) node _T_1942 = asSInt(_T_1941) node _T_1943 = eq(_T_1942, asSInt(UInt<1>(0h0))) node _T_1944 = or(_T_1938, _T_1943) node _T_1945 = and(_T_1933, _T_1944) node _T_1946 = or(UInt<1>(0h0), _T_1931) node _T_1947 = or(_T_1946, _T_1945) node _T_1948 = and(_T_1882, _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_143 node _T_1952 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1953 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1954 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_1952 connect _WIRE_6[1], _T_1953 connect _WIRE_6[2], _T_1954 node _T_1955 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1956 = mux(_WIRE_6[0], _T_1955, UInt<1>(0h0)) node _T_1957 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1958 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1959 = or(_T_1956, _T_1957) node _T_1960 = or(_T_1959, _T_1958) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1960 node _T_1961 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1962 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1963 = and(_T_1961, _T_1962) node _T_1964 = or(UInt<1>(0h0), _T_1963) node _T_1965 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1966 = cvt(_T_1965) node _T_1967 = and(_T_1966, asSInt(UInt<14>(0h2000))) node _T_1968 = asSInt(_T_1967) node _T_1969 = eq(_T_1968, asSInt(UInt<1>(0h0))) node _T_1970 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1971 = cvt(_T_1970) node _T_1972 = and(_T_1971, asSInt(UInt<13>(0h1000))) node _T_1973 = asSInt(_T_1972) node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0))) node _T_1975 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<17>(0h10000))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1981 = cvt(_T_1980) node _T_1982 = and(_T_1981, asSInt(UInt<18>(0h2f000))) node _T_1983 = asSInt(_T_1982) node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0))) node _T_1985 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1986 = cvt(_T_1985) node _T_1987 = and(_T_1986, asSInt(UInt<17>(0h10000))) node _T_1988 = asSInt(_T_1987) node _T_1989 = eq(_T_1988, asSInt(UInt<1>(0h0))) node _T_1990 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1991 = cvt(_T_1990) node _T_1992 = and(_T_1991, asSInt(UInt<13>(0h1000))) node _T_1993 = asSInt(_T_1992) node _T_1994 = eq(_T_1993, asSInt(UInt<1>(0h0))) node _T_1995 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1996 = cvt(_T_1995) node _T_1997 = and(_T_1996, asSInt(UInt<17>(0h10000))) node _T_1998 = asSInt(_T_1997) node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0))) node _T_2000 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2001 = cvt(_T_2000) node _T_2002 = and(_T_2001, asSInt(UInt<27>(0h4000000))) node _T_2003 = asSInt(_T_2002) node _T_2004 = eq(_T_2003, asSInt(UInt<1>(0h0))) node _T_2005 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2006 = cvt(_T_2005) node _T_2007 = and(_T_2006, asSInt(UInt<13>(0h1000))) node _T_2008 = asSInt(_T_2007) node _T_2009 = eq(_T_2008, asSInt(UInt<1>(0h0))) node _T_2010 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2011 = cvt(_T_2010) node _T_2012 = and(_T_2011, asSInt(UInt<29>(0h10000000))) node _T_2013 = asSInt(_T_2012) node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0))) node _T_2015 = or(_T_1969, _T_1974) node _T_2016 = or(_T_2015, _T_1979) node _T_2017 = or(_T_2016, _T_1984) node _T_2018 = or(_T_2017, _T_1989) node _T_2019 = or(_T_2018, _T_1994) node _T_2020 = or(_T_2019, _T_1999) node _T_2021 = or(_T_2020, _T_2004) node _T_2022 = or(_T_2021, _T_2009) node _T_2023 = or(_T_2022, _T_2014) node _T_2024 = and(_T_1964, _T_2023) node _T_2025 = or(UInt<1>(0h0), _T_2024) node _T_2026 = and(_WIRE_7, _T_2025) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_144 node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(source_ok_2, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2033 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_146 node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2040 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_148 node _T_2044 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_149 node _T_2048 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2048 : node _T_2049 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2050 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2051 = and(_T_2049, _T_2050) node _T_2052 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2053 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2054 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_2055 = or(_T_2052, _T_2053) node _T_2056 = or(_T_2055, _T_2054) node _T_2057 = and(_T_2051, _T_2056) node _T_2058 = or(UInt<1>(0h0), _T_2057) node _T_2059 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2060 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<14>(0h2000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<13>(0h1000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<17>(0h10000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<18>(0h2f000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<17>(0h10000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = or(_T_2064, _T_2069) node _T_2101 = or(_T_2100, _T_2074) node _T_2102 = or(_T_2101, _T_2079) node _T_2103 = or(_T_2102, _T_2084) node _T_2104 = or(_T_2103, _T_2089) node _T_2105 = or(_T_2104, _T_2094) node _T_2106 = or(_T_2105, _T_2099) node _T_2107 = and(_T_2059, _T_2106) node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2109 = or(UInt<1>(0h0), _T_2108) node _T_2110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2111 = cvt(_T_2110) node _T_2112 = and(_T_2111, asSInt(UInt<17>(0h10000))) node _T_2113 = asSInt(_T_2112) node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0))) node _T_2115 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2116 = cvt(_T_2115) node _T_2117 = and(_T_2116, asSInt(UInt<29>(0h10000000))) node _T_2118 = asSInt(_T_2117) node _T_2119 = eq(_T_2118, asSInt(UInt<1>(0h0))) node _T_2120 = or(_T_2114, _T_2119) node _T_2121 = and(_T_2109, _T_2120) node _T_2122 = or(UInt<1>(0h0), _T_2107) node _T_2123 = or(_T_2122, _T_2121) node _T_2124 = and(_T_2058, _T_2123) node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(_T_2124, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2124, UInt<1>(0h1), "") : assert_150 node _T_2128 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2130 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2128 connect _WIRE_8[1], _T_2129 connect _WIRE_8[2], _T_2130 node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2132 = mux(_WIRE_8[0], _T_2131, UInt<1>(0h0)) node _T_2133 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2134 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2135 = or(_T_2132, _T_2133) node _T_2136 = or(_T_2135, _T_2134) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2136 node _T_2137 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2138 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2139 = and(_T_2137, _T_2138) node _T_2140 = or(UInt<1>(0h0), _T_2139) node _T_2141 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2142 = cvt(_T_2141) node _T_2143 = and(_T_2142, asSInt(UInt<14>(0h2000))) node _T_2144 = asSInt(_T_2143) node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0))) node _T_2146 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2147 = cvt(_T_2146) node _T_2148 = and(_T_2147, asSInt(UInt<13>(0h1000))) node _T_2149 = asSInt(_T_2148) node _T_2150 = eq(_T_2149, asSInt(UInt<1>(0h0))) node _T_2151 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2152 = cvt(_T_2151) node _T_2153 = and(_T_2152, asSInt(UInt<17>(0h10000))) node _T_2154 = asSInt(_T_2153) node _T_2155 = eq(_T_2154, asSInt(UInt<1>(0h0))) node _T_2156 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2157 = cvt(_T_2156) node _T_2158 = and(_T_2157, asSInt(UInt<18>(0h2f000))) node _T_2159 = asSInt(_T_2158) node _T_2160 = eq(_T_2159, asSInt(UInt<1>(0h0))) node _T_2161 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2162 = cvt(_T_2161) node _T_2163 = and(_T_2162, asSInt(UInt<17>(0h10000))) node _T_2164 = asSInt(_T_2163) node _T_2165 = eq(_T_2164, asSInt(UInt<1>(0h0))) node _T_2166 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2167 = cvt(_T_2166) node _T_2168 = and(_T_2167, asSInt(UInt<13>(0h1000))) node _T_2169 = asSInt(_T_2168) node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0))) node _T_2171 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2172 = cvt(_T_2171) node _T_2173 = and(_T_2172, asSInt(UInt<17>(0h10000))) node _T_2174 = asSInt(_T_2173) node _T_2175 = eq(_T_2174, asSInt(UInt<1>(0h0))) node _T_2176 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2177 = cvt(_T_2176) node _T_2178 = and(_T_2177, asSInt(UInt<27>(0h4000000))) node _T_2179 = asSInt(_T_2178) node _T_2180 = eq(_T_2179, asSInt(UInt<1>(0h0))) node _T_2181 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2182 = cvt(_T_2181) node _T_2183 = and(_T_2182, asSInt(UInt<13>(0h1000))) node _T_2184 = asSInt(_T_2183) node _T_2185 = eq(_T_2184, asSInt(UInt<1>(0h0))) node _T_2186 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2187 = cvt(_T_2186) node _T_2188 = and(_T_2187, asSInt(UInt<29>(0h10000000))) node _T_2189 = asSInt(_T_2188) node _T_2190 = eq(_T_2189, asSInt(UInt<1>(0h0))) node _T_2191 = or(_T_2145, _T_2150) node _T_2192 = or(_T_2191, _T_2155) node _T_2193 = or(_T_2192, _T_2160) node _T_2194 = or(_T_2193, _T_2165) node _T_2195 = or(_T_2194, _T_2170) node _T_2196 = or(_T_2195, _T_2175) node _T_2197 = or(_T_2196, _T_2180) node _T_2198 = or(_T_2197, _T_2185) node _T_2199 = or(_T_2198, _T_2190) node _T_2200 = and(_T_2140, _T_2199) node _T_2201 = or(UInt<1>(0h0), _T_2200) node _T_2202 = and(_WIRE_9, _T_2201) node _T_2203 = asUInt(reset) node _T_2204 = eq(_T_2203, UInt<1>(0h0)) when _T_2204 : node _T_2205 = eq(_T_2202, UInt<1>(0h0)) when _T_2205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2202, UInt<1>(0h1), "") : assert_151 node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : node _T_2208 = eq(source_ok_2, UInt<1>(0h0)) when _T_2208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2209 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_153 node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2216 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2217 = asUInt(reset) node _T_2218 = eq(_T_2217, UInt<1>(0h0)) when _T_2218 : node _T_2219 = eq(_T_2216, UInt<1>(0h0)) when _T_2219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2216, UInt<1>(0h1), "") : assert_155 node _T_2220 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2220 : node _T_2221 = asUInt(reset) node _T_2222 = eq(_T_2221, UInt<1>(0h0)) when _T_2222 : node _T_2223 = eq(address_ok_1, UInt<1>(0h0)) when _T_2223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(source_ok_2, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2230 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_159 node _T_2234 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2235 = asUInt(reset) node _T_2236 = eq(_T_2235, UInt<1>(0h0)) when _T_2236 : node _T_2237 = eq(_T_2234, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2234, UInt<1>(0h1), "") : assert_160 node _T_2238 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2238 : node _T_2239 = asUInt(reset) node _T_2240 = eq(_T_2239, UInt<1>(0h0)) when _T_2240 : node _T_2241 = eq(address_ok_1, UInt<1>(0h0)) when _T_2241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(source_ok_2, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2248 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_164 node _T_2252 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2252 : node _T_2253 = asUInt(reset) node _T_2254 = eq(_T_2253, UInt<1>(0h0)) when _T_2254 : node _T_2255 = eq(address_ok_1, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2256 = asUInt(reset) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) when _T_2257 : node _T_2258 = eq(source_ok_2, UInt<1>(0h0)) when _T_2258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2262 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_168 node _T_2266 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(_T_2266, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2266, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2273 = eq(a_first, UInt<1>(0h0)) node _T_2274 = and(io.in.a.valid, _T_2273) when _T_2274 : node _T_2275 = eq(io.in.a.bits.opcode, opcode) node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : node _T_2278 = eq(_T_2275, UInt<1>(0h0)) when _T_2278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2275, UInt<1>(0h1), "") : assert_171 node _T_2279 = eq(io.in.a.bits.param, param) node _T_2280 = asUInt(reset) node _T_2281 = eq(_T_2280, UInt<1>(0h0)) when _T_2281 : node _T_2282 = eq(_T_2279, UInt<1>(0h0)) when _T_2282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2279, UInt<1>(0h1), "") : assert_172 node _T_2283 = eq(io.in.a.bits.size, size) node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(_T_2283, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2283, UInt<1>(0h1), "") : assert_173 node _T_2287 = eq(io.in.a.bits.source, source) node _T_2288 = asUInt(reset) node _T_2289 = eq(_T_2288, UInt<1>(0h0)) when _T_2289 : node _T_2290 = eq(_T_2287, UInt<1>(0h0)) when _T_2290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2287, UInt<1>(0h1), "") : assert_174 node _T_2291 = eq(io.in.a.bits.address, address) node _T_2292 = asUInt(reset) node _T_2293 = eq(_T_2292, UInt<1>(0h0)) when _T_2293 : node _T_2294 = eq(_T_2291, UInt<1>(0h0)) when _T_2294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2291, UInt<1>(0h1), "") : assert_175 node _T_2295 = and(io.in.a.ready, io.in.a.valid) node _T_2296 = and(_T_2295, a_first) when _T_2296 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2297 = eq(d_first, UInt<1>(0h0)) node _T_2298 = and(io.in.d.valid, _T_2297) when _T_2298 : node _T_2299 = eq(io.in.d.bits.opcode, opcode_1) node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : node _T_2302 = eq(_T_2299, UInt<1>(0h0)) when _T_2302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2299, UInt<1>(0h1), "") : assert_176 node _T_2303 = eq(io.in.d.bits.param, param_1) node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(_T_2303, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2303, UInt<1>(0h1), "") : assert_177 node _T_2307 = eq(io.in.d.bits.size, size_1) node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : node _T_2310 = eq(_T_2307, UInt<1>(0h0)) when _T_2310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2307, UInt<1>(0h1), "") : assert_178 node _T_2311 = eq(io.in.d.bits.source, source_1) node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : node _T_2314 = eq(_T_2311, UInt<1>(0h0)) when _T_2314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2311, UInt<1>(0h1), "") : assert_179 node _T_2315 = eq(io.in.d.bits.sink, sink) node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : node _T_2318 = eq(_T_2315, UInt<1>(0h0)) when _T_2318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2315, UInt<1>(0h1), "") : assert_180 node _T_2319 = eq(io.in.d.bits.denied, denied) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_181 node _T_2323 = and(io.in.d.ready, io.in.d.valid) node _T_2324 = and(_T_2323, d_first) when _T_2324 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2325 = eq(b_first, UInt<1>(0h0)) node _T_2326 = and(io.in.b.valid, _T_2325) when _T_2326 : node _T_2327 = eq(io.in.b.bits.opcode, opcode_2) node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : node _T_2330 = eq(_T_2327, UInt<1>(0h0)) when _T_2330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2327, UInt<1>(0h1), "") : assert_182 node _T_2331 = eq(io.in.b.bits.param, param_2) node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(_T_2331, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2331, UInt<1>(0h1), "") : assert_183 node _T_2335 = eq(io.in.b.bits.size, size_2) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_184 node _T_2339 = eq(io.in.b.bits.source, source_2) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_185 node _T_2343 = eq(io.in.b.bits.address, address_1) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_186 node _T_2347 = and(io.in.b.ready, io.in.b.valid) node _T_2348 = and(_T_2347, b_first) when _T_2348 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2349 = eq(c_first, UInt<1>(0h0)) node _T_2350 = and(io.in.c.valid, _T_2349) when _T_2350 : node _T_2351 = eq(io.in.c.bits.opcode, opcode_3) node _T_2352 = asUInt(reset) node _T_2353 = eq(_T_2352, UInt<1>(0h0)) when _T_2353 : node _T_2354 = eq(_T_2351, UInt<1>(0h0)) when _T_2354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2351, UInt<1>(0h1), "") : assert_187 node _T_2355 = eq(io.in.c.bits.param, param_3) node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(_T_2355, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2355, UInt<1>(0h1), "") : assert_188 node _T_2359 = eq(io.in.c.bits.size, size_3) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(_T_2359, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2359, UInt<1>(0h1), "") : assert_189 node _T_2363 = eq(io.in.c.bits.source, source_3) node _T_2364 = asUInt(reset) node _T_2365 = eq(_T_2364, UInt<1>(0h0)) when _T_2365 : node _T_2366 = eq(_T_2363, UInt<1>(0h0)) when _T_2366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2363, UInt<1>(0h1), "") : assert_190 node _T_2367 = eq(io.in.c.bits.address, address_2) node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(_T_2367, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2367, UInt<1>(0h1), "") : assert_191 node _T_2371 = and(io.in.c.ready, io.in.c.valid) node _T_2372 = and(_T_2371, c_first) when _T_2372 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes : UInt<24>, clock, reset, UInt<24>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<3> connect a_set, UInt<3>(0h0) wire a_set_wo_ready : UInt<3> connect a_set_wo_ready, UInt<3>(0h0) wire a_opcodes_set : UInt<12> connect a_opcodes_set, UInt<12>(0h0) wire a_sizes_set : UInt<24> connect a_sizes_set, UInt<24>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2373 = and(io.in.a.valid, a_first_1) node _T_2374 = and(_T_2373, UInt<1>(0h1)) when _T_2374 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2375 = and(io.in.a.ready, io.in.a.valid) node _T_2376 = and(_T_2375, a_first_1) node _T_2377 = and(_T_2376, UInt<1>(0h1)) when _T_2377 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2378 = dshr(inflight, io.in.a.bits.source) node _T_2379 = bits(_T_2378, 0, 0) node _T_2380 = eq(_T_2379, UInt<1>(0h0)) node _T_2381 = asUInt(reset) node _T_2382 = eq(_T_2381, UInt<1>(0h0)) when _T_2382 : node _T_2383 = eq(_T_2380, UInt<1>(0h0)) when _T_2383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2380, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<3> connect d_clr, UInt<3>(0h0) wire d_clr_wo_ready : UInt<3> connect d_clr_wo_ready, UInt<3>(0h0) wire d_opcodes_clr : UInt<12> connect d_opcodes_clr, UInt<12>(0h0) wire d_sizes_clr : UInt<24> connect d_sizes_clr, UInt<24>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2384 = and(io.in.d.valid, d_first_1) node _T_2385 = and(_T_2384, UInt<1>(0h1)) node _T_2386 = eq(d_release_ack, UInt<1>(0h0)) node _T_2387 = and(_T_2385, _T_2386) when _T_2387 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2388 = and(io.in.d.ready, io.in.d.valid) node _T_2389 = and(_T_2388, d_first_1) node _T_2390 = and(_T_2389, UInt<1>(0h1)) node _T_2391 = eq(d_release_ack, UInt<1>(0h0)) node _T_2392 = and(_T_2390, _T_2391) when _T_2392 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2393 = and(io.in.d.valid, d_first_1) node _T_2394 = and(_T_2393, UInt<1>(0h1)) node _T_2395 = eq(d_release_ack, UInt<1>(0h0)) node _T_2396 = and(_T_2394, _T_2395) when _T_2396 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2397 = dshr(inflight, io.in.d.bits.source) node _T_2398 = bits(_T_2397, 0, 0) node _T_2399 = or(_T_2398, same_cycle_resp) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2403 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2404 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2405 = or(_T_2403, _T_2404) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_194 node _T_2409 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_195 else : node _T_2413 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2414 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2415 = or(_T_2413, _T_2414) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_196 node _T_2419 = eq(io.in.d.bits.size, a_size_lookup) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_197 node _T_2423 = and(io.in.d.valid, d_first_1) node _T_2424 = and(_T_2423, a_first_1) node _T_2425 = and(_T_2424, io.in.a.valid) node _T_2426 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2427 = and(_T_2425, _T_2426) node _T_2428 = eq(d_release_ack, UInt<1>(0h0)) node _T_2429 = and(_T_2427, _T_2428) when _T_2429 : node _T_2430 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2431 = or(_T_2430, io.in.a.ready) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_198 node _T_2435 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2436 = orr(a_set_wo_ready) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) node _T_2438 = or(_T_2435, _T_2437) node _T_2439 = asUInt(reset) node _T_2440 = eq(_T_2439, UInt<1>(0h0)) when _T_2440 : node _T_2441 = eq(_T_2438, UInt<1>(0h0)) when _T_2441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2438, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_2 node _T_2442 = orr(inflight) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) node _T_2444 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2445 = or(_T_2443, _T_2444) node _T_2446 = lt(watchdog, plusarg_reader.out) node _T_2447 = or(_T_2445, _T_2446) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2451 = and(io.in.a.ready, io.in.a.valid) node _T_2452 = and(io.in.d.ready, io.in.d.valid) node _T_2453 = or(_T_2451, _T_2452) when _T_2453 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes_1 : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes_1 : UInt<24>, clock, reset, UInt<24>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<3> connect c_set, UInt<3>(0h0) wire c_set_wo_ready : UInt<3> connect c_set_wo_ready, UInt<3>(0h0) wire c_opcodes_set : UInt<12> connect c_opcodes_set, UInt<12>(0h0) wire c_sizes_set : UInt<24> connect c_sizes_set, UInt<24>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2454 = and(io.in.c.valid, c_first_1) node _T_2455 = bits(io.in.c.bits.opcode, 2, 2) node _T_2456 = bits(io.in.c.bits.opcode, 1, 1) node _T_2457 = and(_T_2455, _T_2456) node _T_2458 = and(_T_2454, _T_2457) when _T_2458 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2459 = and(io.in.c.ready, io.in.c.valid) node _T_2460 = and(_T_2459, c_first_1) node _T_2461 = bits(io.in.c.bits.opcode, 2, 2) node _T_2462 = bits(io.in.c.bits.opcode, 1, 1) node _T_2463 = and(_T_2461, _T_2462) node _T_2464 = and(_T_2460, _T_2463) when _T_2464 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2465 = dshr(inflight_1, io.in.c.bits.source) node _T_2466 = bits(_T_2465, 0, 0) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<3> connect d_clr_1, UInt<3>(0h0) wire d_clr_wo_ready_1 : UInt<3> connect d_clr_wo_ready_1, UInt<3>(0h0) wire d_opcodes_clr_1 : UInt<12> connect d_opcodes_clr_1, UInt<12>(0h0) wire d_sizes_clr_1 : UInt<24> connect d_sizes_clr_1, UInt<24>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2471 = and(io.in.d.valid, d_first_2) node _T_2472 = and(_T_2471, UInt<1>(0h1)) node _T_2473 = and(_T_2472, d_release_ack_1) when _T_2473 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2474 = and(io.in.d.ready, io.in.d.valid) node _T_2475 = and(_T_2474, d_first_2) node _T_2476 = and(_T_2475, UInt<1>(0h1)) node _T_2477 = and(_T_2476, d_release_ack_1) when _T_2477 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2478 = and(io.in.d.valid, d_first_2) node _T_2479 = and(_T_2478, UInt<1>(0h1)) node _T_2480 = and(_T_2479, d_release_ack_1) when _T_2480 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2481 = dshr(inflight_1, io.in.d.bits.source) node _T_2482 = bits(_T_2481, 0, 0) node _T_2483 = or(_T_2482, same_cycle_resp_1) node _T_2484 = asUInt(reset) node _T_2485 = eq(_T_2484, UInt<1>(0h0)) when _T_2485 : node _T_2486 = eq(_T_2483, UInt<1>(0h0)) when _T_2486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2483, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2487 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2488 = asUInt(reset) node _T_2489 = eq(_T_2488, UInt<1>(0h0)) when _T_2489 : node _T_2490 = eq(_T_2487, UInt<1>(0h0)) when _T_2490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2487, UInt<1>(0h1), "") : assert_203 else : node _T_2491 = eq(io.in.d.bits.size, c_size_lookup) node _T_2492 = asUInt(reset) node _T_2493 = eq(_T_2492, UInt<1>(0h0)) when _T_2493 : node _T_2494 = eq(_T_2491, UInt<1>(0h0)) when _T_2494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2491, UInt<1>(0h1), "") : assert_204 node _T_2495 = and(io.in.d.valid, d_first_2) node _T_2496 = and(_T_2495, c_first_1) node _T_2497 = and(_T_2496, io.in.c.valid) node _T_2498 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2499 = and(_T_2497, _T_2498) node _T_2500 = and(_T_2499, d_release_ack_1) node _T_2501 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2502 = and(_T_2500, _T_2501) when _T_2502 : node _T_2503 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2504 = or(_T_2503, io.in.c.ready) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_205 node _T_2508 = orr(c_set_wo_ready) when _T_2508 : node _T_2509 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_3 node _T_2513 = orr(inflight_1) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) node _T_2515 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2516 = or(_T_2514, _T_2515) node _T_2517 = lt(watchdog_1, plusarg_reader_1.out) node _T_2518 = or(_T_2516, _T_2517) node _T_2519 = asUInt(reset) node _T_2520 = eq(_T_2519, UInt<1>(0h0)) when _T_2520 : node _T_2521 = eq(_T_2518, UInt<1>(0h0)) when _T_2521 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2518, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2522 = and(io.in.c.ready, io.in.c.valid) node _T_2523 = and(io.in.d.ready, io.in.d.valid) node _T_2524 = or(_T_2522, _T_2523) when _T_2524 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2525 = and(io.in.d.ready, io.in.d.valid) node _T_2526 = and(_T_2525, d_first_3) node _T_2527 = bits(io.in.d.bits.opcode, 2, 2) node _T_2528 = bits(io.in.d.bits.opcode, 1, 1) node _T_2529 = eq(_T_2528, UInt<1>(0h0)) node _T_2530 = and(_T_2527, _T_2529) node _T_2531 = and(_T_2526, _T_2530) when _T_2531 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2532 = dshr(inflight_2, io.in.d.bits.sink) node _T_2533 = bits(_T_2532, 0, 0) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) node _T_2535 = asUInt(reset) node _T_2536 = eq(_T_2535, UInt<1>(0h0)) when _T_2536 : node _T_2537 = eq(_T_2534, UInt<1>(0h0)) when _T_2537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2534, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2538 = and(io.in.e.ready, io.in.e.valid) node _T_2539 = and(_T_2538, UInt<1>(0h1)) node _T_2540 = and(_T_2539, UInt<1>(0h1)) when _T_2540 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2541 = or(d_set, inflight_2) node _T_2542 = dshr(_T_2541, io.in.e.bits.sink) node _T_2543 = bits(_T_2542, 0, 0) node _T_2544 = asUInt(reset) node _T_2545 = eq(_T_2544, UInt<1>(0h0)) when _T_2545 : node _T_2546 = eq(_T_2543, UInt<1>(0h0)) when _T_2546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2543, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [1:0] io_in_b_bits_source = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _legal_source_T_5 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1 = 2'h0; // @[Mux.scala:30:73] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_1 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73] wire _legal_source_T_4 = 1'h0; // @[Mux.scala:30:73] wire _legal_source_T_6 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35] wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_20 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46] wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_22 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_23 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_24 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_24; // @[OneHot.scala:58:35] assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _GEN_25 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module TLDebugModuleInnerAsync : output auto : { flip dmiXing_in : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}, dmInner_sb2tlOpt_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, flip dmInner_custom_in : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>}, flip dmInner_tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip debug_clock : Clock, flip debug_reset : Reset, flip tl_clock : Clock, flip tl_reset : Reset, flip dmactive : UInt<1>, flip innerCtrl : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[8], hrmask : UInt<1>[8]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip debugUnavail : UInt<1>[8], hgDebugInt : UInt<1>[8], flip hartIsInReset : UInt<1>[8]} input rf_reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst dmInner of TLDebugModuleInner connect dmInner.clock, childClock connect dmInner.reset, childReset inst dmiXing of TLAsyncCrossingSink_a9d32s1k1z2u connect dmiXing.clock, childClock connect dmiXing.reset, childReset connect dmInner.auto.dmi_in, dmiXing.auto.out connect dmInner.auto.tl_in, auto.dmInner_tl_in connect dmInner.auto.custom_in, auto.dmInner_custom_in connect dmInner.auto.sb2tlOpt_out.d, auto.dmInner_sb2tlOpt_out.d connect auto.dmInner_sb2tlOpt_out.a.bits, dmInner.auto.sb2tlOpt_out.a.bits connect auto.dmInner_sb2tlOpt_out.a.valid, dmInner.auto.sb2tlOpt_out.a.valid connect dmInner.auto.sb2tlOpt_out.a.ready, auto.dmInner_sb2tlOpt_out.a.ready connect dmiXing.auto.in, auto.dmiXing_in connect childClock, io.debug_clock connect childReset, io.debug_reset inst dmactive_synced_dmactive_synced_dmactiveSync of AsyncResetSynchronizerShiftReg_w1_d3_i0_34 connect dmactive_synced_dmactive_synced_dmactiveSync.clock, childClock connect dmactive_synced_dmactive_synced_dmactiveSync.reset, childReset connect dmactive_synced_dmactive_synced_dmactiveSync.io.d, io.dmactive wire dmactive_synced : UInt<1> connect dmactive_synced, dmactive_synced_dmactive_synced_dmactiveSync.io.q connect dmInner.clock, io.debug_clock connect dmInner.reset, io.debug_reset connect dmInner.io.tl_clock, io.tl_clock connect dmInner.io.tl_reset, io.tl_reset connect dmInner.io.dmactive, dmactive_synced inst dmactive_synced_dmInner_io_innerCtrl_sink of AsyncQueueSink_DebugInternalBundle connect dmactive_synced_dmInner_io_innerCtrl_sink.clock, childClock connect dmactive_synced_dmInner_io_innerCtrl_sink.reset, childReset connect dmactive_synced_dmInner_io_innerCtrl_sink.io.async, io.innerCtrl connect dmInner.io.innerCtrl, dmactive_synced_dmInner_io_innerCtrl_sink.io.deq connect dmInner.io.debugUnavail[0], io.debugUnavail[0] connect dmInner.io.debugUnavail[1], io.debugUnavail[1] connect dmInner.io.debugUnavail[2], io.debugUnavail[2] connect dmInner.io.debugUnavail[3], io.debugUnavail[3] connect dmInner.io.debugUnavail[4], io.debugUnavail[4] connect dmInner.io.debugUnavail[5], io.debugUnavail[5] connect dmInner.io.debugUnavail[6], io.debugUnavail[6] connect dmInner.io.debugUnavail[7], io.debugUnavail[7] connect io.hgDebugInt, dmInner.io.hgDebugInt connect dmInner.io.hartIsInReset[0], io.hartIsInReset[0] connect dmInner.io.hartIsInReset[1], io.hartIsInReset[1] connect dmInner.io.hartIsInReset[2], io.hartIsInReset[2] connect dmInner.io.hartIsInReset[3], io.hartIsInReset[3] connect dmInner.io.hartIsInReset[4], io.hartIsInReset[4] connect dmInner.io.hartIsInReset[5], io.hartIsInReset[5] connect dmInner.io.hartIsInReset[6], io.hartIsInReset[6] connect dmInner.io.hartIsInReset[7], io.hartIsInReset[7]	module TLDebugModuleInnerAsync( // @[Debug.scala:1871:9] input [2:0] auto_dmiXing_in_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmiXing_in_a_mem_0_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmiXing_in_a_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_ridx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_widx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmiXing_in_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmiXing_in_d_mem_0_size, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_mem_0_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmiXing_in_d_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_ridx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_widx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_dmInner_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_dmInner_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_dmInner_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmInner_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_dmInner_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_dmInner_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_debug_clock, // @[Debug.scala:1877:16] input io_debug_reset, // @[Debug.scala:1877:16] input io_tl_clock, // @[Debug.scala:1877:16] input io_tl_reset, // @[Debug.scala:1877:16] input io_dmactive, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_resumereq, // @[Debug.scala:1877:16] input [9:0] io_innerCtrl_mem_0_hartsel, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_ackhavereset, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hasel, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_0, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_1, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_2, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_3, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_4, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_5, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_6, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_7, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_0, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_1, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_2, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_3, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_4, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_5, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_6, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_7, // @[Debug.scala:1877:16] output io_innerCtrl_ridx, // @[Debug.scala:1877:16] input io_innerCtrl_widx, // @[Debug.scala:1877:16] output io_innerCtrl_safe_ridx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_widx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_source_reset_n, // @[Debug.scala:1877:16] output io_innerCtrl_safe_sink_reset_n, // @[Debug.scala:1877:16] output io_hgDebugInt_0, // @[Debug.scala:1877:16] output io_hgDebugInt_1, // @[Debug.scala:1877:16] output io_hgDebugInt_2, // @[Debug.scala:1877:16] output io_hgDebugInt_3, // @[Debug.scala:1877:16] output io_hgDebugInt_4, // @[Debug.scala:1877:16] output io_hgDebugInt_5, // @[Debug.scala:1877:16] output io_hgDebugInt_6, // @[Debug.scala:1877:16] output io_hgDebugInt_7, // @[Debug.scala:1877:16] input io_hartIsInReset_0, // @[Debug.scala:1877:16] input io_hartIsInReset_1, // @[Debug.scala:1877:16] input io_hartIsInReset_2, // @[Debug.scala:1877:16] input io_hartIsInReset_3, // @[Debug.scala:1877:16] input io_hartIsInReset_4, // @[Debug.scala:1877:16] input io_hartIsInReset_5, // @[Debug.scala:1877:16] input io_hartIsInReset_6, // @[Debug.scala:1877:16] input io_hartIsInReset_7, // @[Debug.scala:1877:16] input rf_reset // @[Debug.scala:1904:22] ); wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[AsyncQueue.scala:211:22] wire [9:0] _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_1; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_2; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_3; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_4; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_5; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_6; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_7; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_1; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_2; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_3; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_4; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_5; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_6; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_7; // @[AsyncQueue.scala:211:22] wire _dmiXing_auto_out_a_valid; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_opcode; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_param; // @[Debug.scala:1858:27] wire [1:0] _dmiXing_auto_out_a_bits_size; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_source; // @[Debug.scala:1858:27] wire [8:0] _dmiXing_auto_out_a_bits_address; // @[Debug.scala:1858:27] wire [3:0] _dmiXing_auto_out_a_bits_mask; // @[Debug.scala:1858:27] wire [31:0] _dmiXing_auto_out_a_bits_data; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_corrupt; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_d_ready; // @[Debug.scala:1858:27] wire _dmInner_auto_dmi_in_a_ready; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_valid; // @[Debug.scala:1857:27] wire [2:0] _dmInner_auto_dmi_in_d_bits_opcode; // @[Debug.scala:1857:27] wire [1:0] _dmInner_auto_dmi_in_d_bits_size; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_bits_source; // @[Debug.scala:1857:27] wire [31:0] _dmInner_auto_dmi_in_d_bits_data; // @[Debug.scala:1857:27] wire [2:0] auto_dmiXing_in_a_mem_0_opcode_0 = auto_dmiXing_in_a_mem_0_opcode; // @[Debug.scala:1871:9] wire [8:0] auto_dmiXing_in_a_mem_0_address_0 = auto_dmiXing_in_a_mem_0_address; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_a_mem_0_data_0 = auto_dmiXing_in_a_mem_0_data; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_widx_0 = auto_dmiXing_in_a_widx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_widx_valid_0 = auto_dmiXing_in_a_safe_widx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_source_reset_n_0 = auto_dmiXing_in_a_safe_source_reset_n; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_ridx_0 = auto_dmiXing_in_d_ridx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_ridx_valid_0 = auto_dmiXing_in_d_safe_ridx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_sink_reset_n_0 = auto_dmiXing_in_d_safe_sink_reset_n; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_ready_0 = auto_dmInner_sb2tlOpt_out_a_ready; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_valid_0 = auto_dmInner_sb2tlOpt_out_d_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode_0 = auto_dmInner_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param_0 = auto_dmInner_sb2tlOpt_out_d_bits_param; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size_0 = auto_dmInner_sb2tlOpt_out_d_bits_size; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_d_bits_sink_0 = auto_dmInner_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_denied_0 = auto_dmInner_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data_0 = auto_dmInner_sb2tlOpt_out_d_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0 = auto_dmInner_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_valid_0 = auto_dmInner_tl_in_a_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_opcode_0 = auto_dmInner_tl_in_a_bits_opcode; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_param_0 = auto_dmInner_tl_in_a_bits_param; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_a_bits_size_0 = auto_dmInner_tl_in_a_bits_size; // @[Debug.scala:1871:9] wire [10:0] auto_dmInner_tl_in_a_bits_source_0 = auto_dmInner_tl_in_a_bits_source; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_a_bits_address_0 = auto_dmInner_tl_in_a_bits_address; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_tl_in_a_bits_mask_0 = auto_dmInner_tl_in_a_bits_mask; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_a_bits_data_0 = auto_dmInner_tl_in_a_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_bits_corrupt_0 = auto_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_ready_0 = auto_dmInner_tl_in_d_ready; // @[Debug.scala:1871:9] wire io_debug_clock_0 = io_debug_clock; // @[Debug.scala:1871:9] wire io_debug_reset_0 = io_debug_reset; // @[Debug.scala:1871:9] wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:1871:9] wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:1871:9] wire io_dmactive_0 = io_dmactive; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_resumereq_0 = io_innerCtrl_mem_0_resumereq; // @[Debug.scala:1871:9] wire [9:0] io_innerCtrl_mem_0_hartsel_0 = io_innerCtrl_mem_0_hartsel; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_ackhavereset_0 = io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hasel_0 = io_innerCtrl_mem_0_hasel; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_0_0 = io_innerCtrl_mem_0_hamask_0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_1_0 = io_innerCtrl_mem_0_hamask_1; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_2_0 = io_innerCtrl_mem_0_hamask_2; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_3_0 = io_innerCtrl_mem_0_hamask_3; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_4_0 = io_innerCtrl_mem_0_hamask_4; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_5_0 = io_innerCtrl_mem_0_hamask_5; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_6_0 = io_innerCtrl_mem_0_hamask_6; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_7_0 = io_innerCtrl_mem_0_hamask_7; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_0_0 = io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_1_0 = io_innerCtrl_mem_0_hrmask_1; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_2_0 = io_innerCtrl_mem_0_hrmask_2; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_3_0 = io_innerCtrl_mem_0_hrmask_3; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_4_0 = io_innerCtrl_mem_0_hrmask_4; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_5_0 = io_innerCtrl_mem_0_hrmask_5; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_6_0 = io_innerCtrl_mem_0_hrmask_6; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_7_0 = io_innerCtrl_mem_0_hrmask_7; // @[Debug.scala:1871:9] wire io_innerCtrl_widx_0 = io_innerCtrl_widx; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_widx_valid_0 = io_innerCtrl_safe_widx_valid; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_source_reset_n_0 = io_innerCtrl_safe_source_reset_n; // @[Debug.scala:1871:9] wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:1871:9] wire io_hartIsInReset_1_0 = io_hartIsInReset_1; // @[Debug.scala:1871:9] wire io_hartIsInReset_2_0 = io_hartIsInReset_2; // @[Debug.scala:1871:9] wire io_hartIsInReset_3_0 = io_hartIsInReset_3; // @[Debug.scala:1871:9] wire io_hartIsInReset_4_0 = io_hartIsInReset_4; // @[Debug.scala:1871:9] wire io_hartIsInReset_5_0 = io_hartIsInReset_5; // @[Debug.scala:1871:9] wire io_hartIsInReset_6_0 = io_hartIsInReset_6; // @[Debug.scala:1871:9] wire io_hartIsInReset_7_0 = io_hartIsInReset_7; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_addr = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_ready = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_1 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_2 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_3 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_4 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_5 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_6 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_7 = 1'h0; // @[Debug.scala:1871:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire auto_dmInner_sb2tlOpt_out_a_bits_mask = 1'h1; // @[AsyncQueue.scala:211:22] wire [31:0] auto_dmiXing_in_b_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [31:0] auto_dmiXing_in_c_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [3:0] auto_dmiXing_in_b_mem_0_mask = 4'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_b_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_c_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_c_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_param = 2'h0; // @[Debug.scala:1871:9] wire [3:0] auto_dmiXing_in_a_mem_0_mask = 4'hF; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_a_mem_0_size = 2'h2; // @[Debug.scala:1858:27, :1871:9] wire [2:0] auto_dmiXing_in_a_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_b_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:1871:9] wire childClock = io_debug_clock_0; // @[Debug.scala:1871:9] wire childReset = io_debug_reset_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] wire [10:0] auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_0_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_1_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_2_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_3_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_4_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_5_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_6_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_7_0; // @[Debug.scala:1871:9] wire dmactive_synced; // @[ShiftReg.scala:48:24] TLDebugModuleInner dmInner ( // @[Debug.scala:1857:27] .clock (io_debug_clock_0), // @[Debug.scala:1871:9] .reset (io_debug_reset_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_ready (auto_dmInner_sb2tlOpt_out_a_ready_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_valid (auto_dmInner_sb2tlOpt_out_a_valid_0), .auto_sb2tlOpt_out_a_bits_opcode (auto_dmInner_sb2tlOpt_out_a_bits_opcode_0), .auto_sb2tlOpt_out_a_bits_size (auto_dmInner_sb2tlOpt_out_a_bits_size_0), .auto_sb2tlOpt_out_a_bits_address (auto_dmInner_sb2tlOpt_out_a_bits_address_0), .auto_sb2tlOpt_out_a_bits_data (auto_dmInner_sb2tlOpt_out_a_bits_data_0), .auto_sb2tlOpt_out_d_ready (auto_dmInner_sb2tlOpt_out_d_ready_0), .auto_sb2tlOpt_out_d_valid (auto_dmInner_sb2tlOpt_out_d_valid_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_opcode (auto_dmInner_sb2tlOpt_out_d_bits_opcode_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_param (auto_dmInner_sb2tlOpt_out_d_bits_param_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_size (auto_dmInner_sb2tlOpt_out_d_bits_size_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_sink (auto_dmInner_sb2tlOpt_out_d_bits_sink_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_denied (auto_dmInner_sb2tlOpt_out_d_bits_denied_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_data (auto_dmInner_sb2tlOpt_out_d_bits_data_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_corrupt (auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_a_ready (auto_dmInner_tl_in_a_ready_0), .auto_tl_in_a_valid (auto_dmInner_tl_in_a_valid_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_opcode (auto_dmInner_tl_in_a_bits_opcode_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_param (auto_dmInner_tl_in_a_bits_param_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_size (auto_dmInner_tl_in_a_bits_size_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_source (auto_dmInner_tl_in_a_bits_source_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_address (auto_dmInner_tl_in_a_bits_address_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_mask (auto_dmInner_tl_in_a_bits_mask_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_data (auto_dmInner_tl_in_a_bits_data_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_corrupt (auto_dmInner_tl_in_a_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_d_ready (auto_dmInner_tl_in_d_ready_0), // @[Debug.scala:1871:9] .auto_tl_in_d_valid (auto_dmInner_tl_in_d_valid_0), .auto_tl_in_d_bits_opcode (auto_dmInner_tl_in_d_bits_opcode_0), .auto_tl_in_d_bits_size (auto_dmInner_tl_in_d_bits_size_0), .auto_tl_in_d_bits_source (auto_dmInner_tl_in_d_bits_source_0), .auto_tl_in_d_bits_data (auto_dmInner_tl_in_d_bits_data_0), .auto_dmi_in_a_ready (_dmInner_auto_dmi_in_a_ready), .auto_dmi_in_a_valid (_dmiXing_auto_out_a_valid), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_param (_dmiXing_auto_out_a_bits_param), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_size (_dmiXing_auto_out_a_bits_size), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_source (_dmiXing_auto_out_a_bits_source), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_address (_dmiXing_auto_out_a_bits_address), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_mask (_dmiXing_auto_out_a_bits_mask), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_data (_dmiXing_auto_out_a_bits_data), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), // @[Debug.scala:1858:27] .auto_dmi_in_d_ready (_dmiXing_auto_out_d_ready), // @[Debug.scala:1858:27] .auto_dmi_in_d_valid (_dmInner_auto_dmi_in_d_valid), .auto_dmi_in_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), .auto_dmi_in_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), .auto_dmi_in_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), .auto_dmi_in_d_bits_data (_dmInner_auto_dmi_in_d_bits_data), .io_dmactive (dmactive_synced), // @[ShiftReg.scala:48:24] .io_innerCtrl_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_1), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_2), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_3), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_4 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_4), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_5 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_5), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_6 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_6), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_7 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_7), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_1), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_2), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_3), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_4 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_4), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_5 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_5), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_6 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_6), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_7 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_7), // @[AsyncQueue.scala:211:22] .io_hgDebugInt_0 (io_hgDebugInt_0_0), .io_hgDebugInt_1 (io_hgDebugInt_1_0), .io_hgDebugInt_2 (io_hgDebugInt_2_0), .io_hgDebugInt_3 (io_hgDebugInt_3_0), .io_hgDebugInt_4 (io_hgDebugInt_4_0), .io_hgDebugInt_5 (io_hgDebugInt_5_0), .io_hgDebugInt_6 (io_hgDebugInt_6_0), .io_hgDebugInt_7 (io_hgDebugInt_7_0), .io_hartIsInReset_0 (io_hartIsInReset_0_0), // @[Debug.scala:1871:9] .io_hartIsInReset_1 (io_hartIsInReset_1_0), // @[Debug.scala:1871:9] .io_hartIsInReset_2 (io_hartIsInReset_2_0), // @[Debug.scala:1871:9] .io_hartIsInReset_3 (io_hartIsInReset_3_0), // @[Debug.scala:1871:9] .io_hartIsInReset_4 (io_hartIsInReset_4_0), // @[Debug.scala:1871:9] .io_hartIsInReset_5 (io_hartIsInReset_5_0), // @[Debug.scala:1871:9] .io_hartIsInReset_6 (io_hartIsInReset_6_0), // @[Debug.scala:1871:9] .io_hartIsInReset_7 (io_hartIsInReset_7_0), // @[Debug.scala:1871:9] .io_tl_clock (io_tl_clock_0), // @[Debug.scala:1871:9] .io_tl_reset (io_tl_reset_0) // @[Debug.scala:1871:9] ); // @[Debug.scala:1857:27] TLAsyncCrossingSink_a9d32s1k1z2u dmiXing ( // @[Debug.scala:1858:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_mem_0_opcode (auto_dmiXing_in_a_mem_0_opcode_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_address (auto_dmiXing_in_a_mem_0_address_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_data (auto_dmiXing_in_a_mem_0_data_0), // @[Debug.scala:1871:9] .auto_in_a_ridx (auto_dmiXing_in_a_ridx_0), .auto_in_a_widx (auto_dmiXing_in_a_widx_0), // @[Debug.scala:1871:9] .auto_in_a_safe_ridx_valid (auto_dmiXing_in_a_safe_ridx_valid_0), .auto_in_a_safe_widx_valid (auto_dmiXing_in_a_safe_widx_valid_0), // @[Debug.scala:1871:9] .auto_in_a_safe_source_reset_n (auto_dmiXing_in_a_safe_source_reset_n_0), // @[Debug.scala:1871:9] .auto_in_a_safe_sink_reset_n (auto_dmiXing_in_a_safe_sink_reset_n_0), .auto_in_d_mem_0_opcode (auto_dmiXing_in_d_mem_0_opcode_0), .auto_in_d_mem_0_size (auto_dmiXing_in_d_mem_0_size_0), .auto_in_d_mem_0_source (auto_dmiXing_in_d_mem_0_source_0), .auto_in_d_mem_0_data (auto_dmiXing_in_d_mem_0_data_0), .auto_in_d_ridx (auto_dmiXing_in_d_ridx_0), // @[Debug.scala:1871:9] .auto_in_d_widx (auto_dmiXing_in_d_widx_0), .auto_in_d_safe_ridx_valid (auto_dmiXing_in_d_safe_ridx_valid_0), // @[Debug.scala:1871:9] .auto_in_d_safe_widx_valid (auto_dmiXing_in_d_safe_widx_valid_0), .auto_in_d_safe_source_reset_n (auto_dmiXing_in_d_safe_source_reset_n_0), .auto_in_d_safe_sink_reset_n (auto_dmiXing_in_d_safe_sink_reset_n_0), // @[Debug.scala:1871:9] .auto_out_a_ready (_dmInner_auto_dmi_in_a_ready), // @[Debug.scala:1857:27] .auto_out_a_valid (_dmiXing_auto_out_a_valid), .auto_out_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), .auto_out_a_bits_param (_dmiXing_auto_out_a_bits_param), .auto_out_a_bits_size (_dmiXing_auto_out_a_bits_size), .auto_out_a_bits_source (_dmiXing_auto_out_a_bits_source), .auto_out_a_bits_address (_dmiXing_auto_out_a_bits_address), .auto_out_a_bits_mask (_dmiXing_auto_out_a_bits_mask), .auto_out_a_bits_data (_dmiXing_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), .auto_out_d_ready (_dmiXing_auto_out_d_ready), .auto_out_d_valid (_dmInner_auto_dmi_in_d_valid), // @[Debug.scala:1857:27] .auto_out_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), // @[Debug.scala:1857:27] .auto_out_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), // @[Debug.scala:1857:27] .auto_out_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), // @[Debug.scala:1857:27] .auto_out_d_bits_data (_dmInner_auto_dmi_in_d_bits_data) // @[Debug.scala:1857:27] ); // @[Debug.scala:1858:27] AsyncResetSynchronizerShiftReg_w1_d3_i0_34 dmactive_synced_dmactive_synced_dmactiveSync ( // @[ShiftReg.scala:45:23] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_d (io_dmactive_0), // @[Debug.scala:1871:9] .io_q (dmactive_synced) ); // @[ShiftReg.scala:45:23] AsyncQueueSink_DebugInternalBundle dmactive_synced_dmInner_io_innerCtrl_sink ( // @[AsyncQueue.scala:211:22] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_deq_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), .io_deq_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), .io_deq_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), .io_deq_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), .io_deq_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), .io_deq_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), .io_deq_bits_hamask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_1), .io_deq_bits_hamask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_2), .io_deq_bits_hamask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_3), .io_deq_bits_hamask_4 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_4), .io_deq_bits_hamask_5 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_5), .io_deq_bits_hamask_6 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_6), .io_deq_bits_hamask_7 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_7), .io_deq_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), .io_deq_bits_hrmask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_1), .io_deq_bits_hrmask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_2), .io_deq_bits_hrmask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_3), .io_deq_bits_hrmask_4 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_4), .io_deq_bits_hrmask_5 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_5), .io_deq_bits_hrmask_6 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_6), .io_deq_bits_hrmask_7 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_7), .io_async_mem_0_resumereq (io_innerCtrl_mem_0_resumereq_0), // @[Debug.scala:1871:9] .io_async_mem_0_hartsel (io_innerCtrl_mem_0_hartsel_0), // @[Debug.scala:1871:9] .io_async_mem_0_ackhavereset (io_innerCtrl_mem_0_ackhavereset_0), // @[Debug.scala:1871:9] .io_async_mem_0_hasel (io_innerCtrl_mem_0_hasel_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_0 (io_innerCtrl_mem_0_hamask_0_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_1 (io_innerCtrl_mem_0_hamask_1_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_2 (io_innerCtrl_mem_0_hamask_2_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_3 (io_innerCtrl_mem_0_hamask_3_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_4 (io_innerCtrl_mem_0_hamask_4_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_5 (io_innerCtrl_mem_0_hamask_5_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_6 (io_innerCtrl_mem_0_hamask_6_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_7 (io_innerCtrl_mem_0_hamask_7_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_0 (io_innerCtrl_mem_0_hrmask_0_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_1 (io_innerCtrl_mem_0_hrmask_1_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_2 (io_innerCtrl_mem_0_hrmask_2_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_3 (io_innerCtrl_mem_0_hrmask_3_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_4 (io_innerCtrl_mem_0_hrmask_4_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_5 (io_innerCtrl_mem_0_hrmask_5_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_6 (io_innerCtrl_mem_0_hrmask_6_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_7 (io_innerCtrl_mem_0_hrmask_7_0), // @[Debug.scala:1871:9] .io_async_ridx (io_innerCtrl_ridx_0), .io_async_widx (io_innerCtrl_widx_0), // @[Debug.scala:1871:9] .io_async_safe_ridx_valid (io_innerCtrl_safe_ridx_valid_0), .io_async_safe_widx_valid (io_innerCtrl_safe_widx_valid_0), // @[Debug.scala:1871:9] .io_async_safe_source_reset_n (io_innerCtrl_safe_source_reset_n_0), // @[Debug.scala:1871:9] .io_async_safe_sink_reset_n (io_innerCtrl_safe_sink_reset_n_0) ); // @[AsyncQueue.scala:211:22] assign auto_dmiXing_in_a_ridx = auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_ridx_valid = auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_sink_reset_n = auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_opcode = auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_size = auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_source = auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_data = auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_widx = auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_widx_valid = auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_source_reset_n = auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_valid = auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_opcode = auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_size = auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_address = auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_data = auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_d_ready = auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_a_ready = auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_valid = auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_opcode = auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_size = auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_source = auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_data = auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] assign io_innerCtrl_ridx = io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_ridx_valid = io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_sink_reset_n = io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_0 = io_hgDebugInt_0_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_1 = io_hgDebugInt_1_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_2 = io_hgDebugInt_2_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_3 = io_hgDebugInt_3_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_4 = io_hgDebugInt_4_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_5 = io_hgDebugInt_5_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_6 = io_hgDebugInt_6_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_7 = io_hgDebugInt_7_0; // @[Debug.scala:1871:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_22 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] connect auto.out, nodeOut connect nodeIn, auto.in inst reg of AsyncResetRegVec_w1_i0_22 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] connect reg.io.en, UInt<1>(0h1) node _T = bits(reg.io.q, 0, 0) connect nodeOut.sync[0], _T	module IntSyncCrossingSource_n1x1_22( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset // @[Crossing.scala:41:9] ); wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9] wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:41:9] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] AsyncResetRegVec_w1_i0_22 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset) ); // @[AsyncResetReg.scala:86:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a32d256s5k3z4u_2 : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)	module Repeater_TLBundleA_a32d256s5k3z4u_2( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [4:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [255:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [4:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output [255:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [4:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [255:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [4:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [255:0] io_deq_bits_data_0; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [4:0] saved_source; // @[Repeater.scala:21:18] reg [31:0] saved_address; // @[Repeater.scala:21:18] reg [31:0] saved_mask; // @[Repeater.scala:21:18] reg [255:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 \| full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 \| full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_52 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<17>(0h10000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = and(_T_207, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = and(_T_206, _T_214) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_215, UInt<1>(0h1), "") : assert_26 node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(is_aligned, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_225 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(io.in.a.bits.mask, mask) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_229, UInt<1>(0h1), "") : assert_30 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_237 = shr(io.in.a.bits.source, 11) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_5) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = and(_T_245, _T_250) node _T_252 = or(UInt<1>(0h0), _T_251) node _T_253 = and(_T_244, _T_252) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_253, UInt<1>(0h1), "") : assert_31 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(is_aligned, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_263 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_263, UInt<1>(0h1), "") : assert_34 node _T_267 = not(mask) node _T_268 = and(io.in.a.bits.mask, _T_267) node _T_269 = eq(_T_268, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_269, UInt<1>(0h1), "") : assert_35 node _T_273 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_277 = shr(io.in.a.bits.source, 11) node _T_278 = eq(_T_277, UInt<1>(0h0)) node _T_279 = leq(UInt<1>(0h0), uncommonBits_6) node _T_280 = and(_T_278, _T_279) node _T_281 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_282 = and(_T_280, _T_281) node _T_283 = and(_T_276, _T_282) node _T_284 = or(UInt<1>(0h0), _T_283) node _T_285 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = and(_T_285, _T_290) node _T_292 = or(UInt<1>(0h0), _T_291) node _T_293 = and(_T_284, _T_292) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_293, UInt<1>(0h1), "") : assert_36 node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(is_aligned, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_303 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(_T_303, UInt<1>(0h0)) when _T_306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_303, UInt<1>(0h1), "") : assert_39 node _T_307 = eq(io.in.a.bits.mask, mask) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_307, UInt<1>(0h1), "") : assert_40 node _T_311 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_311 : node _T_312 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_313 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_315 = shr(io.in.a.bits.source, 11) node _T_316 = eq(_T_315, UInt<1>(0h0)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_7) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_320 = and(_T_318, _T_319) node _T_321 = and(_T_314, _T_320) node _T_322 = or(UInt<1>(0h0), _T_321) node _T_323 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = and(_T_323, _T_328) node _T_330 = or(UInt<1>(0h0), _T_329) node _T_331 = and(_T_322, _T_330) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_331, UInt<1>(0h1), "") : assert_41 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(is_aligned, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_341 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(_T_341, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_341, UInt<1>(0h1), "") : assert_44 node _T_345 = eq(io.in.a.bits.mask, mask) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_345, UInt<1>(0h1), "") : assert_45 node _T_349 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_349 : node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_352 = and(_T_350, _T_351) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_353 = shr(io.in.a.bits.source, 11) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = leq(UInt<1>(0h0), uncommonBits_8) node _T_356 = and(_T_354, _T_355) node _T_357 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_358 = and(_T_356, _T_357) node _T_359 = and(_T_352, _T_358) node _T_360 = or(UInt<1>(0h0), _T_359) node _T_361 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = and(_T_361, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = and(_T_360, _T_368) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_369, UInt<1>(0h1), "") : assert_46 node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(is_aligned, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_379 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_379, UInt<1>(0h1), "") : assert_49 node _T_383 = eq(io.in.a.bits.mask, mask) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_383, UInt<1>(0h1), "") : assert_50 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_387, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_391 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_391, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_395 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_395 : node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_399 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_399, UInt<1>(0h1), "") : assert_54 node _T_403 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_403, UInt<1>(0h1), "") : assert_55 node _T_407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_407, UInt<1>(0h1), "") : assert_56 node _T_411 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_411, UInt<1>(0h1), "") : assert_57 node _T_415 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_415 : node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(sink_ok, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_422 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_422, UInt<1>(0h1), "") : assert_60 node _T_426 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_426, UInt<1>(0h1), "") : assert_61 node _T_430 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_431 = asUInt(reset) node _T_432 = eq(_T_431, UInt<1>(0h0)) when _T_432 : node _T_433 = eq(_T_430, UInt<1>(0h0)) when _T_433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_430, UInt<1>(0h1), "") : assert_62 node _T_434 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_434, UInt<1>(0h1), "") : assert_63 node _T_438 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_439, UInt<1>(0h1), "") : assert_64 node _T_443 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_443 : node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(sink_ok, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_450 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_450, UInt<1>(0h1), "") : assert_67 node _T_454 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_454, UInt<1>(0h1), "") : assert_68 node _T_458 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(_T_458, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_458, UInt<1>(0h1), "") : assert_69 node _T_462 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_463 = or(_T_462, io.in.d.bits.corrupt) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_463, UInt<1>(0h1), "") : assert_70 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_468, UInt<1>(0h1), "") : assert_71 node _T_472 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_472 : node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_476 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_476, UInt<1>(0h1), "") : assert_73 node _T_480 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_480, UInt<1>(0h1), "") : assert_74 node _T_484 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_485, UInt<1>(0h1), "") : assert_75 node _T_489 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_493 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_493, UInt<1>(0h1), "") : assert_77 node _T_497 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_498 = or(_T_497, io.in.d.bits.corrupt) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_498, UInt<1>(0h1), "") : assert_78 node _T_502 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = asUInt(reset) node _T_505 = eq(_T_504, UInt<1>(0h0)) when _T_505 : node _T_506 = eq(_T_503, UInt<1>(0h0)) when _T_506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_503, UInt<1>(0h1), "") : assert_79 node _T_507 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_507 : node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_511 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(_T_511, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_511, UInt<1>(0h1), "") : assert_81 node _T_515 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(_T_515, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_515, UInt<1>(0h1), "") : assert_82 node _T_519 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_520, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_524 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_524, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_528 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_528, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_532 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_532, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_536 = eq(a_first, UInt<1>(0h0)) node _T_537 = and(io.in.a.valid, _T_536) when _T_537 : node _T_538 = eq(io.in.a.bits.opcode, opcode) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_538, UInt<1>(0h1), "") : assert_87 node _T_542 = eq(io.in.a.bits.param, param) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_542, UInt<1>(0h1), "") : assert_88 node _T_546 = eq(io.in.a.bits.size, size) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_546, UInt<1>(0h1), "") : assert_89 node _T_550 = eq(io.in.a.bits.source, source) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_550, UInt<1>(0h1), "") : assert_90 node _T_554 = eq(io.in.a.bits.address, address) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_554, UInt<1>(0h1), "") : assert_91 node _T_558 = and(io.in.a.ready, io.in.a.valid) node _T_559 = and(_T_558, a_first) when _T_559 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_560 = eq(d_first, UInt<1>(0h0)) node _T_561 = and(io.in.d.valid, _T_560) when _T_561 : node _T_562 = eq(io.in.d.bits.opcode, opcode_1) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_562, UInt<1>(0h1), "") : assert_92 node _T_566 = eq(io.in.d.bits.param, param_1) node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(_T_566, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_566, UInt<1>(0h1), "") : assert_93 node _T_570 = eq(io.in.d.bits.size, size_1) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_570, UInt<1>(0h1), "") : assert_94 node _T_574 = eq(io.in.d.bits.source, source_1) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_574, UInt<1>(0h1), "") : assert_95 node _T_578 = eq(io.in.d.bits.sink, sink) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_578, UInt<1>(0h1), "") : assert_96 node _T_582 = eq(io.in.d.bits.denied, denied) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_582, UInt<1>(0h1), "") : assert_97 node _T_586 = and(io.in.d.ready, io.in.d.valid) node _T_587 = and(_T_586, d_first) when _T_587 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_588 = and(io.in.a.valid, a_first_1) node _T_589 = and(_T_588, UInt<1>(0h1)) when _T_589 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_590 = and(io.in.a.ready, io.in.a.valid) node _T_591 = and(_T_590, a_first_1) node _T_592 = and(_T_591, UInt<1>(0h1)) when _T_592 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_593 = dshr(inflight, io.in.a.bits.source) node _T_594 = bits(_T_593, 0, 0) node _T_595 = eq(_T_594, UInt<1>(0h0)) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_595, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_599 = and(io.in.d.valid, d_first_1) node _T_600 = and(_T_599, UInt<1>(0h1)) node _T_601 = eq(d_release_ack, UInt<1>(0h0)) node _T_602 = and(_T_600, _T_601) when _T_602 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_603 = and(io.in.d.ready, io.in.d.valid) node _T_604 = and(_T_603, d_first_1) node _T_605 = and(_T_604, UInt<1>(0h1)) node _T_606 = eq(d_release_ack, UInt<1>(0h0)) node _T_607 = and(_T_605, _T_606) when _T_607 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_608 = and(io.in.d.valid, d_first_1) node _T_609 = and(_T_608, UInt<1>(0h1)) node _T_610 = eq(d_release_ack, UInt<1>(0h0)) node _T_611 = and(_T_609, _T_610) when _T_611 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_612 = dshr(inflight, io.in.d.bits.source) node _T_613 = bits(_T_612, 0, 0) node _T_614 = or(_T_613, same_cycle_resp) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_614, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_618 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_619 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_620 = or(_T_618, _T_619) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_620, UInt<1>(0h1), "") : assert_100 node _T_624 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_624, UInt<1>(0h1), "") : assert_101 else : node _T_628 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_629 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_630 = or(_T_628, _T_629) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_630, UInt<1>(0h1), "") : assert_102 node _T_634 = eq(io.in.d.bits.size, a_size_lookup) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_634, UInt<1>(0h1), "") : assert_103 node _T_638 = and(io.in.d.valid, d_first_1) node _T_639 = and(_T_638, a_first_1) node _T_640 = and(_T_639, io.in.a.valid) node _T_641 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_642 = and(_T_640, _T_641) node _T_643 = eq(d_release_ack, UInt<1>(0h0)) node _T_644 = and(_T_642, _T_643) when _T_644 : node _T_645 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_646 = or(_T_645, io.in.a.ready) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_646, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_105 node _T_650 = orr(inflight) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_653 = or(_T_651, _T_652) node _T_654 = lt(watchdog, plusarg_reader.out) node _T_655 = or(_T_653, _T_654) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_655, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_659 = and(io.in.a.ready, io.in.a.valid) node _T_660 = and(io.in.d.ready, io.in.d.valid) node _T_661 = or(_T_659, _T_660) when _T_661 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_662 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<17>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_663 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_664 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_665 = and(_T_663, _T_664) node _T_666 = and(_T_662, _T_665) when _T_666 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_667 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_668 = and(_T_667, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_669 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_673 = dshr(inflight_1, _WIRE_15.bits.source) node _T_674 = bits(_T_673, 0, 0) node _T_675 = eq(_T_674, UInt<1>(0h0)) node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(_T_675, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_675, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_679 = and(io.in.d.valid, d_first_2) node _T_680 = and(_T_679, UInt<1>(0h1)) node _T_681 = and(_T_680, d_release_ack_1) when _T_681 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_682 = and(io.in.d.ready, io.in.d.valid) node _T_683 = and(_T_682, d_first_2) node _T_684 = and(_T_683, UInt<1>(0h1)) node _T_685 = and(_T_684, d_release_ack_1) when _T_685 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_686 = and(io.in.d.valid, d_first_2) node _T_687 = and(_T_686, UInt<1>(0h1)) node _T_688 = and(_T_687, d_release_ack_1) when _T_688 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_689 = dshr(inflight_1, io.in.d.bits.source) node _T_690 = bits(_T_689, 0, 0) node _T_691 = or(_T_690, same_cycle_resp_1) node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(_T_691, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_691, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_695 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_696 = asUInt(reset) node _T_697 = eq(_T_696, UInt<1>(0h0)) when _T_697 : node _T_698 = eq(_T_695, UInt<1>(0h0)) when _T_698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_695, UInt<1>(0h1), "") : assert_108 else : node _T_699 = eq(io.in.d.bits.size, c_size_lookup) node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(_T_699, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_699, UInt<1>(0h1), "") : assert_109 node _T_703 = and(io.in.d.valid, d_first_2) node _T_704 = and(_T_703, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_705 = and(_T_704, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_706 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_707 = and(_T_705, _T_706) node _T_708 = and(_T_707, d_release_ack_1) node _T_709 = eq(c_probe_ack, UInt<1>(0h0)) node _T_710 = and(_T_708, _T_709) when _T_710 : node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_712 = or(_T_711, _WIRE_23.ready) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_106 node _T_716 = orr(inflight_1) node _T_717 = eq(_T_716, UInt<1>(0h0)) node _T_718 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_719 = or(_T_717, _T_718) node _T_720 = lt(watchdog_1, plusarg_reader_1.out) node _T_721 = or(_T_719, _T_720) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_721, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_725 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_726 = and(io.in.d.ready, io.in.d.valid) node _T_727 = or(_T_725, _T_726) when _T_727 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_52( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] reg [31:0] watchdog; // @[Monitor.scala:709:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_444 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_188 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_444( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_188 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BootROMClockSinkDomain : output auto : { flip bootrom_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst bootrom of TLROM connect bootrom.clock, childClock connect bootrom.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect bootrom.auto.in, auto.bootrom_in connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset	module BootROMClockSinkDomain( // @[ClockDomain.scala:14:9] output auto_bootrom_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bootrom_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bootrom_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bootrom_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_bootrom_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_bootrom_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [16:0] auto_bootrom_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bootrom_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_bootrom_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bootrom_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bootrom_in_d_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bootrom_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_bootrom_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bootrom_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); TLROM bootrom ( // @[BootROM.scala:86:17] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_a_ready (auto_bootrom_in_a_ready), .auto_in_a_valid (auto_bootrom_in_a_valid), .auto_in_a_bits_opcode (auto_bootrom_in_a_bits_opcode), .auto_in_a_bits_param (auto_bootrom_in_a_bits_param), .auto_in_a_bits_size (auto_bootrom_in_a_bits_size), .auto_in_a_bits_source (auto_bootrom_in_a_bits_source), .auto_in_a_bits_address (auto_bootrom_in_a_bits_address), .auto_in_a_bits_mask (auto_bootrom_in_a_bits_mask), .auto_in_a_bits_corrupt (auto_bootrom_in_a_bits_corrupt), .auto_in_d_ready (auto_bootrom_in_d_ready), .auto_in_d_valid (auto_bootrom_in_d_valid), .auto_in_d_bits_size (auto_bootrom_in_d_bits_size), .auto_in_d_bits_source (auto_bootrom_in_d_bits_source), .auto_in_d_bits_data (auto_bootrom_in_d_bits_data) ); // @[BootROM.scala:86:17] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_222 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_222( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_49 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_49 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module INToRecFN_i1_e8_s24_49(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_49 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_42 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h2)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<2>(0h3)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h2)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = and(_T_16, _T_24) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_25, UInt<1>(0h1), "") : assert_1 node _T_29 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_29 : node _T_30 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_31 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_32 = and(_T_30, _T_31) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_33 = shr(io.in.a.bits.source, 2) node _T_34 = eq(_T_33, UInt<1>(0h0)) node _T_35 = leq(UInt<1>(0h0), uncommonBits_1) node _T_36 = and(_T_34, _T_35) node _T_37 = leq(uncommonBits_1, UInt<2>(0h2)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_40 = or(_T_38, _T_39) node _T_41 = and(_T_32, _T_40) node _T_42 = or(UInt<1>(0h0), _T_41) node _T_43 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_44 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<14>(0h2000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<13>(0h1000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<18>(0h2f000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<27>(0h4000000))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_48, _T_53) node _T_85 = or(_T_84, _T_58) node _T_86 = or(_T_85, _T_63) node _T_87 = or(_T_86, _T_68) node _T_88 = or(_T_87, _T_73) node _T_89 = or(_T_88, _T_78) node _T_90 = or(_T_89, _T_83) node _T_91 = and(_T_43, _T_90) node _T_92 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_95 = cvt(_T_94) node _T_96 = and(_T_95, asSInt(UInt<17>(0h10000))) node _T_97 = asSInt(_T_96) node _T_98 = eq(_T_97, asSInt(UInt<1>(0h0))) node _T_99 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_100 = cvt(_T_99) node _T_101 = and(_T_100, asSInt(UInt<29>(0h10000000))) node _T_102 = asSInt(_T_101) node _T_103 = eq(_T_102, asSInt(UInt<1>(0h0))) node _T_104 = or(_T_98, _T_103) node _T_105 = and(_T_93, _T_104) node _T_106 = or(UInt<1>(0h0), _T_91) node _T_107 = or(_T_106, _T_105) node _T_108 = and(_T_42, _T_107) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_108, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_2) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_2, UInt<2>(0h2)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.a.bits.source, UInt<2>(0h3)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_117 connect _WIRE[1], _T_118 node _T_119 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_120 = mux(_WIRE[0], _T_119, UInt<1>(0h0)) node _T_121 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_122 = or(_T_120, _T_121) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_122 node _T_123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_125 = and(_T_123, _T_124) node _T_126 = or(UInt<1>(0h0), _T_125) node _T_127 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<14>(0h2000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<13>(0h1000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<17>(0h10000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<18>(0h2f000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<17>(0h10000))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<17>(0h10000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<27>(0h4000000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<29>(0h10000000))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = or(_T_131, _T_136) node _T_178 = or(_T_177, _T_141) node _T_179 = or(_T_178, _T_146) node _T_180 = or(_T_179, _T_151) node _T_181 = or(_T_180, _T_156) node _T_182 = or(_T_181, _T_161) node _T_183 = or(_T_182, _T_166) node _T_184 = or(_T_183, _T_171) node _T_185 = or(_T_184, _T_176) node _T_186 = and(_T_126, _T_185) node _T_187 = or(UInt<1>(0h0), _T_186) node _T_188 = and(_WIRE_1, _T_187) node _T_189 = asUInt(reset) node _T_190 = eq(_T_189, UInt<1>(0h0)) when _T_190 : node _T_191 = eq(_T_188, UInt<1>(0h0)) when _T_191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_188, UInt<1>(0h1), "") : assert_3 node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(source_ok, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_195 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(_T_195, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_195, UInt<1>(0h1), "") : assert_5 node _T_199 = asUInt(reset) node _T_200 = eq(_T_199, UInt<1>(0h0)) when _T_200 : node _T_201 = eq(is_aligned, UInt<1>(0h0)) when _T_201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_202 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_202, UInt<1>(0h1), "") : assert_7 node _T_206 = not(io.in.a.bits.mask) node _T_207 = eq(_T_206, UInt<1>(0h0)) node _T_208 = asUInt(reset) node _T_209 = eq(_T_208, UInt<1>(0h0)) when _T_209 : node _T_210 = eq(_T_207, UInt<1>(0h0)) when _T_210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_207, UInt<1>(0h1), "") : assert_8 node _T_211 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_211, UInt<1>(0h1), "") : assert_9 node _T_215 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_215 : node _T_216 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_217 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_218 = and(_T_216, _T_217) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_219 = shr(io.in.a.bits.source, 2) node _T_220 = eq(_T_219, UInt<1>(0h0)) node _T_221 = leq(UInt<1>(0h0), uncommonBits_3) node _T_222 = and(_T_220, _T_221) node _T_223 = leq(uncommonBits_3, UInt<2>(0h2)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_226 = or(_T_224, _T_225) node _T_227 = and(_T_218, _T_226) node _T_228 = or(UInt<1>(0h0), _T_227) node _T_229 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_230 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_231 = cvt(_T_230) node _T_232 = and(_T_231, asSInt(UInt<14>(0h2000))) node _T_233 = asSInt(_T_232) node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0))) node _T_235 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_236 = cvt(_T_235) node _T_237 = and(_T_236, asSInt(UInt<13>(0h1000))) node _T_238 = asSInt(_T_237) node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0))) node _T_240 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<17>(0h10000))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<18>(0h2f000))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<17>(0h10000))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_256 = cvt(_T_255) node _T_257 = and(_T_256, asSInt(UInt<13>(0h1000))) node _T_258 = asSInt(_T_257) node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0))) node _T_260 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_261 = cvt(_T_260) node _T_262 = and(_T_261, asSInt(UInt<27>(0h4000000))) node _T_263 = asSInt(_T_262) node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0))) node _T_265 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_266 = cvt(_T_265) node _T_267 = and(_T_266, asSInt(UInt<13>(0h1000))) node _T_268 = asSInt(_T_267) node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0))) node _T_270 = or(_T_234, _T_239) node _T_271 = or(_T_270, _T_244) node _T_272 = or(_T_271, _T_249) node _T_273 = or(_T_272, _T_254) node _T_274 = or(_T_273, _T_259) node _T_275 = or(_T_274, _T_264) node _T_276 = or(_T_275, _T_269) node _T_277 = and(_T_229, _T_276) node _T_278 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_279 = or(UInt<1>(0h0), _T_278) node _T_280 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_281 = cvt(_T_280) node _T_282 = and(_T_281, asSInt(UInt<17>(0h10000))) node _T_283 = asSInt(_T_282) node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_286 = cvt(_T_285) node _T_287 = and(_T_286, asSInt(UInt<29>(0h10000000))) node _T_288 = asSInt(_T_287) node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0))) node _T_290 = or(_T_284, _T_289) node _T_291 = and(_T_279, _T_290) node _T_292 = or(UInt<1>(0h0), _T_277) node _T_293 = or(_T_292, _T_291) node _T_294 = and(_T_228, _T_293) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_294, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_298 = shr(io.in.a.bits.source, 2) node _T_299 = eq(_T_298, UInt<1>(0h0)) node _T_300 = leq(UInt<1>(0h0), uncommonBits_4) node _T_301 = and(_T_299, _T_300) node _T_302 = leq(uncommonBits_4, UInt<2>(0h2)) node _T_303 = and(_T_301, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<2>(0h3)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_303 connect _WIRE_2[1], _T_304 node _T_305 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_306 = mux(_WIRE_2[0], _T_305, UInt<1>(0h0)) node _T_307 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_308 = or(_T_306, _T_307) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_308 node _T_309 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_310 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_311 = and(_T_309, _T_310) node _T_312 = or(UInt<1>(0h0), _T_311) node _T_313 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<14>(0h2000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<18>(0h2f000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<17>(0h10000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_344 = cvt(_T_343) node _T_345 = and(_T_344, asSInt(UInt<17>(0h10000))) node _T_346 = asSInt(_T_345) node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0))) node _T_348 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_349 = cvt(_T_348) node _T_350 = and(_T_349, asSInt(UInt<27>(0h4000000))) node _T_351 = asSInt(_T_350) node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0))) node _T_353 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_359 = cvt(_T_358) node _T_360 = and(_T_359, asSInt(UInt<29>(0h10000000))) node _T_361 = asSInt(_T_360) node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0))) node _T_363 = or(_T_317, _T_322) node _T_364 = or(_T_363, _T_327) node _T_365 = or(_T_364, _T_332) node _T_366 = or(_T_365, _T_337) node _T_367 = or(_T_366, _T_342) node _T_368 = or(_T_367, _T_347) node _T_369 = or(_T_368, _T_352) node _T_370 = or(_T_369, _T_357) node _T_371 = or(_T_370, _T_362) node _T_372 = and(_T_312, _T_371) node _T_373 = or(UInt<1>(0h0), _T_372) node _T_374 = and(_WIRE_3, _T_373) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_374, UInt<1>(0h1), "") : assert_11 node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(source_ok, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_381 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_381, UInt<1>(0h1), "") : assert_13 node _T_385 = asUInt(reset) node _T_386 = eq(_T_385, UInt<1>(0h0)) when _T_386 : node _T_387 = eq(is_aligned, UInt<1>(0h0)) when _T_387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_388 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(_T_388, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_388, UInt<1>(0h1), "") : assert_15 node _T_392 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_392, UInt<1>(0h1), "") : assert_16 node _T_396 = not(io.in.a.bits.mask) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_397, UInt<1>(0h1), "") : assert_17 node _T_401 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_T_401, UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_401, UInt<1>(0h1), "") : assert_18 node _T_405 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_405 : node _T_406 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_407 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_408 = and(_T_406, _T_407) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_5) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_5, UInt<2>(0h2)) node _T_414 = and(_T_412, _T_413) node _T_415 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_416 = or(_T_414, _T_415) node _T_417 = and(_T_408, _T_416) node _T_418 = or(UInt<1>(0h0), _T_417) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_418, UInt<1>(0h1), "") : assert_19 node _T_422 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_423 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_424 = and(_T_422, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = and(_T_425, _T_430) node _T_432 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_433 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_434 = and(_T_432, _T_433) node _T_435 = or(UInt<1>(0h0), _T_434) node _T_436 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<14>(0h2000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_447 = cvt(_T_446) node _T_448 = and(_T_447, asSInt(UInt<18>(0h2f000))) node _T_449 = asSInt(_T_448) node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0))) node _T_451 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<17>(0h10000))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<13>(0h1000))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<17>(0h10000))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<27>(0h4000000))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<29>(0h10000000))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_440, _T_445) node _T_482 = or(_T_481, _T_450) node _T_483 = or(_T_482, _T_455) node _T_484 = or(_T_483, _T_460) node _T_485 = or(_T_484, _T_465) node _T_486 = or(_T_485, _T_470) node _T_487 = or(_T_486, _T_475) node _T_488 = or(_T_487, _T_480) node _T_489 = and(_T_435, _T_488) node _T_490 = or(UInt<1>(0h0), _T_431) node _T_491 = or(_T_490, _T_489) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_491, UInt<1>(0h1), "") : assert_20 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(source_ok, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(is_aligned, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_501 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_501, UInt<1>(0h1), "") : assert_23 node _T_505 = eq(io.in.a.bits.mask, mask) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_505, UInt<1>(0h1), "") : assert_24 node _T_509 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_509, UInt<1>(0h1), "") : assert_25 node _T_513 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_513 : node _T_514 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_515 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_516 = and(_T_514, _T_515) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_517 = shr(io.in.a.bits.source, 2) node _T_518 = eq(_T_517, UInt<1>(0h0)) node _T_519 = leq(UInt<1>(0h0), uncommonBits_6) node _T_520 = and(_T_518, _T_519) node _T_521 = leq(uncommonBits_6, UInt<2>(0h2)) node _T_522 = and(_T_520, _T_521) node _T_523 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_524 = or(_T_522, _T_523) node _T_525 = and(_T_516, _T_524) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_528 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_529 = and(_T_527, _T_528) node _T_530 = or(UInt<1>(0h0), _T_529) node _T_531 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<13>(0h1000))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = and(_T_530, _T_535) node _T_537 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_538 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_539 = and(_T_537, _T_538) node _T_540 = or(UInt<1>(0h0), _T_539) node _T_541 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_542 = cvt(_T_541) node _T_543 = and(_T_542, asSInt(UInt<14>(0h2000))) node _T_544 = asSInt(_T_543) node _T_545 = eq(_T_544, asSInt(UInt<1>(0h0))) node _T_546 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_547 = cvt(_T_546) node _T_548 = and(_T_547, asSInt(UInt<18>(0h2f000))) node _T_549 = asSInt(_T_548) node _T_550 = eq(_T_549, asSInt(UInt<1>(0h0))) node _T_551 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_557 = cvt(_T_556) node _T_558 = and(_T_557, asSInt(UInt<13>(0h1000))) node _T_559 = asSInt(_T_558) node _T_560 = eq(_T_559, asSInt(UInt<1>(0h0))) node _T_561 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<17>(0h10000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_567 = cvt(_T_566) node _T_568 = and(_T_567, asSInt(UInt<27>(0h4000000))) node _T_569 = asSInt(_T_568) node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0))) node _T_571 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<13>(0h1000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<29>(0h10000000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = or(_T_545, _T_550) node _T_582 = or(_T_581, _T_555) node _T_583 = or(_T_582, _T_560) node _T_584 = or(_T_583, _T_565) node _T_585 = or(_T_584, _T_570) node _T_586 = or(_T_585, _T_575) node _T_587 = or(_T_586, _T_580) node _T_588 = and(_T_540, _T_587) node _T_589 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_590 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_591 = cvt(_T_590) node _T_592 = and(_T_591, asSInt(UInt<17>(0h10000))) node _T_593 = asSInt(_T_592) node _T_594 = eq(_T_593, asSInt(UInt<1>(0h0))) node _T_595 = and(_T_589, _T_594) node _T_596 = or(UInt<1>(0h0), _T_536) node _T_597 = or(_T_596, _T_588) node _T_598 = or(_T_597, _T_595) node _T_599 = and(_T_526, _T_598) node _T_600 = asUInt(reset) node _T_601 = eq(_T_600, UInt<1>(0h0)) when _T_601 : node _T_602 = eq(_T_599, UInt<1>(0h0)) when _T_602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_599, UInt<1>(0h1), "") : assert_26 node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(source_ok, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(is_aligned, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_609 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_610 = asUInt(reset) node _T_611 = eq(_T_610, UInt<1>(0h0)) when _T_611 : node _T_612 = eq(_T_609, UInt<1>(0h0)) when _T_612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_609, UInt<1>(0h1), "") : assert_29 node _T_613 = eq(io.in.a.bits.mask, mask) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_613, UInt<1>(0h1), "") : assert_30 node _T_617 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_617 : node _T_618 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_619 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_620 = and(_T_618, _T_619) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_621 = shr(io.in.a.bits.source, 2) node _T_622 = eq(_T_621, UInt<1>(0h0)) node _T_623 = leq(UInt<1>(0h0), uncommonBits_7) node _T_624 = and(_T_622, _T_623) node _T_625 = leq(uncommonBits_7, UInt<2>(0h2)) node _T_626 = and(_T_624, _T_625) node _T_627 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_628 = or(_T_626, _T_627) node _T_629 = and(_T_620, _T_628) node _T_630 = or(UInt<1>(0h0), _T_629) node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_633 = and(_T_631, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = and(_T_634, _T_639) node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_643 = and(_T_641, _T_642) node _T_644 = or(UInt<1>(0h0), _T_643) node _T_645 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<14>(0h2000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<18>(0h2f000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<17>(0h10000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<27>(0h4000000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<13>(0h1000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<29>(0h10000000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = or(_T_649, _T_654) node _T_686 = or(_T_685, _T_659) node _T_687 = or(_T_686, _T_664) node _T_688 = or(_T_687, _T_669) node _T_689 = or(_T_688, _T_674) node _T_690 = or(_T_689, _T_679) node _T_691 = or(_T_690, _T_684) node _T_692 = and(_T_644, _T_691) node _T_693 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_694 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_695 = cvt(_T_694) node _T_696 = and(_T_695, asSInt(UInt<17>(0h10000))) node _T_697 = asSInt(_T_696) node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0))) node _T_699 = and(_T_693, _T_698) node _T_700 = or(UInt<1>(0h0), _T_640) node _T_701 = or(_T_700, _T_692) node _T_702 = or(_T_701, _T_699) node _T_703 = and(_T_630, _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_703, UInt<1>(0h1), "") : assert_31 node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(source_ok, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(is_aligned, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_713 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_713, UInt<1>(0h1), "") : assert_34 node _T_717 = not(mask) node _T_718 = and(io.in.a.bits.mask, _T_717) node _T_719 = eq(_T_718, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_719, UInt<1>(0h1), "") : assert_35 node _T_723 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_723 : node _T_724 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_725 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_726 = and(_T_724, _T_725) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_727 = shr(io.in.a.bits.source, 2) node _T_728 = eq(_T_727, UInt<1>(0h0)) node _T_729 = leq(UInt<1>(0h0), uncommonBits_8) node _T_730 = and(_T_728, _T_729) node _T_731 = leq(uncommonBits_8, UInt<2>(0h2)) node _T_732 = and(_T_730, _T_731) node _T_733 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_734 = or(_T_732, _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<14>(0h2000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<13>(0h1000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<18>(0h2f000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_757 = cvt(_T_756) node _T_758 = and(_T_757, asSInt(UInt<17>(0h10000))) node _T_759 = asSInt(_T_758) node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0))) node _T_761 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_762 = cvt(_T_761) node _T_763 = and(_T_762, asSInt(UInt<13>(0h1000))) node _T_764 = asSInt(_T_763) node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) node _T_766 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<17>(0h10000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_772 = cvt(_T_771) node _T_773 = and(_T_772, asSInt(UInt<27>(0h4000000))) node _T_774 = asSInt(_T_773) node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0))) node _T_776 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<13>(0h1000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<29>(0h10000000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = or(_T_745, _T_750) node _T_787 = or(_T_786, _T_755) node _T_788 = or(_T_787, _T_760) node _T_789 = or(_T_788, _T_765) node _T_790 = or(_T_789, _T_770) node _T_791 = or(_T_790, _T_775) node _T_792 = or(_T_791, _T_780) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_740, _T_793) node _T_795 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_796 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_797 = cvt(_T_796) node _T_798 = and(_T_797, asSInt(UInt<17>(0h10000))) node _T_799 = asSInt(_T_798) node _T_800 = eq(_T_799, asSInt(UInt<1>(0h0))) node _T_801 = and(_T_795, _T_800) node _T_802 = or(UInt<1>(0h0), _T_794) node _T_803 = or(_T_802, _T_801) node _T_804 = and(_T_736, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_804, UInt<1>(0h1), "") : assert_36 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_814 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_814, UInt<1>(0h1), "") : assert_39 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_818, UInt<1>(0h1), "") : assert_40 node _T_822 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_822 : node _T_823 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_824 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<1>(0h0)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_9) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_9, UInt<2>(0h2)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_833 = or(_T_831, _T_832) node _T_834 = and(_T_825, _T_833) node _T_835 = or(UInt<1>(0h0), _T_834) node _T_836 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_837 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _T_839 = or(UInt<1>(0h0), _T_838) node _T_840 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<14>(0h2000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<13>(0h1000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<18>(0h2f000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_856 = cvt(_T_855) node _T_857 = and(_T_856, asSInt(UInt<17>(0h10000))) node _T_858 = asSInt(_T_857) node _T_859 = eq(_T_858, asSInt(UInt<1>(0h0))) node _T_860 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<13>(0h1000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_866 = cvt(_T_865) node _T_867 = and(_T_866, asSInt(UInt<17>(0h10000))) node _T_868 = asSInt(_T_867) node _T_869 = eq(_T_868, asSInt(UInt<1>(0h0))) node _T_870 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_871 = cvt(_T_870) node _T_872 = and(_T_871, asSInt(UInt<27>(0h4000000))) node _T_873 = asSInt(_T_872) node _T_874 = eq(_T_873, asSInt(UInt<1>(0h0))) node _T_875 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_876 = cvt(_T_875) node _T_877 = and(_T_876, asSInt(UInt<13>(0h1000))) node _T_878 = asSInt(_T_877) node _T_879 = eq(_T_878, asSInt(UInt<1>(0h0))) node _T_880 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_881 = cvt(_T_880) node _T_882 = and(_T_881, asSInt(UInt<29>(0h10000000))) node _T_883 = asSInt(_T_882) node _T_884 = eq(_T_883, asSInt(UInt<1>(0h0))) node _T_885 = or(_T_844, _T_849) node _T_886 = or(_T_885, _T_854) node _T_887 = or(_T_886, _T_859) node _T_888 = or(_T_887, _T_864) node _T_889 = or(_T_888, _T_869) node _T_890 = or(_T_889, _T_874) node _T_891 = or(_T_890, _T_879) node _T_892 = or(_T_891, _T_884) node _T_893 = and(_T_839, _T_892) node _T_894 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_895 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_896 = cvt(_T_895) node _T_897 = and(_T_896, asSInt(UInt<17>(0h10000))) node _T_898 = asSInt(_T_897) node _T_899 = eq(_T_898, asSInt(UInt<1>(0h0))) node _T_900 = and(_T_894, _T_899) node _T_901 = or(UInt<1>(0h0), _T_893) node _T_902 = or(_T_901, _T_900) node _T_903 = and(_T_835, _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_903, UInt<1>(0h1), "") : assert_41 node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(source_ok, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(is_aligned, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_913 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_913, UInt<1>(0h1), "") : assert_44 node _T_917 = eq(io.in.a.bits.mask, mask) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_917, UInt<1>(0h1), "") : assert_45 node _T_921 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_921 : node _T_922 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_923 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_924 = and(_T_922, _T_923) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_925 = shr(io.in.a.bits.source, 2) node _T_926 = eq(_T_925, UInt<1>(0h0)) node _T_927 = leq(UInt<1>(0h0), uncommonBits_10) node _T_928 = and(_T_926, _T_927) node _T_929 = leq(uncommonBits_10, UInt<2>(0h2)) node _T_930 = and(_T_928, _T_929) node _T_931 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_932 = or(_T_930, _T_931) node _T_933 = and(_T_924, _T_932) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_936 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_937 = and(_T_935, _T_936) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_940 = cvt(_T_939) node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000))) node _T_942 = asSInt(_T_941) node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0))) node _T_944 = and(_T_938, _T_943) node _T_945 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_947 = cvt(_T_946) node _T_948 = and(_T_947, asSInt(UInt<14>(0h2000))) node _T_949 = asSInt(_T_948) node _T_950 = eq(_T_949, asSInt(UInt<1>(0h0))) node _T_951 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_952 = cvt(_T_951) node _T_953 = and(_T_952, asSInt(UInt<17>(0h10000))) node _T_954 = asSInt(_T_953) node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0))) node _T_956 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_957 = cvt(_T_956) node _T_958 = and(_T_957, asSInt(UInt<18>(0h2f000))) node _T_959 = asSInt(_T_958) node _T_960 = eq(_T_959, asSInt(UInt<1>(0h0))) node _T_961 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_962 = cvt(_T_961) node _T_963 = and(_T_962, asSInt(UInt<17>(0h10000))) node _T_964 = asSInt(_T_963) node _T_965 = eq(_T_964, asSInt(UInt<1>(0h0))) node _T_966 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_967 = cvt(_T_966) node _T_968 = and(_T_967, asSInt(UInt<13>(0h1000))) node _T_969 = asSInt(_T_968) node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0))) node _T_971 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_972 = cvt(_T_971) node _T_973 = and(_T_972, asSInt(UInt<27>(0h4000000))) node _T_974 = asSInt(_T_973) node _T_975 = eq(_T_974, asSInt(UInt<1>(0h0))) node _T_976 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_977 = cvt(_T_976) node _T_978 = and(_T_977, asSInt(UInt<13>(0h1000))) node _T_979 = asSInt(_T_978) node _T_980 = eq(_T_979, asSInt(UInt<1>(0h0))) node _T_981 = or(_T_950, _T_955) node _T_982 = or(_T_981, _T_960) node _T_983 = or(_T_982, _T_965) node _T_984 = or(_T_983, _T_970) node _T_985 = or(_T_984, _T_975) node _T_986 = or(_T_985, _T_980) node _T_987 = and(_T_945, _T_986) node _T_988 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_989 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_990 = and(_T_988, _T_989) node _T_991 = or(UInt<1>(0h0), _T_990) node _T_992 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<29>(0h10000000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = or(_T_996, _T_1001) node _T_1003 = and(_T_991, _T_1002) node _T_1004 = or(UInt<1>(0h0), _T_944) node _T_1005 = or(_T_1004, _T_987) node _T_1006 = or(_T_1005, _T_1003) node _T_1007 = and(_T_934, _T_1006) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_46 node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(source_ok, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(is_aligned, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1017 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_49 node _T_1021 = eq(io.in.a.bits.mask, mask) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_50 node _T_1025 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1029 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.d.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h0)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h2)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = eq(io.in.d.bits.source, UInt<2>(0h3)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_12 connect _source_ok_WIRE_1[1], _source_ok_T_13 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1033 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1033 : node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(source_ok_1, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1037 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_54 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_55 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_56 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_57 node _T_1053 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(source_ok_1, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(sink_ok, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1060 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_60 node _T_1064 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_61 node _T_1068 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_62 node _T_1072 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_63 node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1077 = or(UInt<1>(0h1), _T_1076) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_64 node _T_1081 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1081 : node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(source_ok_1, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(sink_ok, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1088 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_67 node _T_1092 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_68 node _T_1096 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_69 node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1101 = or(_T_1100, io.in.d.bits.corrupt) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_70 node _T_1105 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1106 = or(UInt<1>(0h1), _T_1105) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_71 node _T_1110 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1110 : node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(source_ok_1, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1114 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_73 node _T_1118 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_74 node _T_1122 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1123 = or(UInt<1>(0h1), _T_1122) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_75 node _T_1127 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1127 : node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(source_ok_1, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1131 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_77 node _T_1135 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1136 = or(_T_1135, io.in.d.bits.corrupt) node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(_T_1136, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1136, UInt<1>(0h1), "") : assert_78 node _T_1140 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1141 = or(UInt<1>(0h1), _T_1140) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_79 node _T_1145 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1145 : node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(source_ok_1, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1149 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_81 node _T_1153 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_82 node _T_1157 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1158 = or(UInt<1>(0h1), _T_1157) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1162 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_1166 = shr(io.in.b.bits.source, 2) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) node _T_1168 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1169 = and(_T_1167, _T_1168) node _T_1170 = leq(uncommonBits_11, UInt<2>(0h2)) node _T_1171 = and(_T_1169, _T_1170) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) node _T_1173 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1174 = cvt(_T_1173) node _T_1175 = and(_T_1174, asSInt(UInt<1>(0h0))) node _T_1176 = asSInt(_T_1175) node _T_1177 = eq(_T_1176, asSInt(UInt<1>(0h0))) node _T_1178 = or(_T_1172, _T_1177) node _T_1179 = eq(io.in.b.bits.source, UInt<2>(0h3)) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) node _T_1181 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1182 = cvt(_T_1181) node _T_1183 = and(_T_1182, asSInt(UInt<1>(0h0))) node _T_1184 = asSInt(_T_1183) node _T_1185 = eq(_T_1184, asSInt(UInt<1>(0h0))) node _T_1186 = or(_T_1180, _T_1185) node _T_1187 = and(_T_1178, _T_1186) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T = shr(io.in.b.bits.source, 2) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<2>(0h2)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<2>(0h3)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 node _legal_source_T_7 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_8 = mux(_legal_source_WIRE[1], UInt<2>(0h3), UInt<1>(0h0)) node _legal_source_T_9 = or(_legal_source_T_7, _legal_source_T_8) wire _legal_source_WIRE_1 : UInt<2> connect _legal_source_WIRE_1, _legal_source_T_9 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1191 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1191 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_1192 = shr(io.in.b.bits.source, 2) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) node _T_1194 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = leq(uncommonBits_12, UInt<2>(0h2)) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = eq(io.in.b.bits.source, UInt<2>(0h3)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1197 connect _WIRE_4[1], _T_1198 node _T_1199 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1200 = mux(_WIRE_4[0], _T_1199, UInt<1>(0h0)) node _T_1201 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1202 = or(_T_1200, _T_1201) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1202 node _T_1203 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1204 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1205 = and(_T_1203, _T_1204) node _T_1206 = or(UInt<1>(0h0), _T_1205) node _T_1207 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1208 = cvt(_T_1207) node _T_1209 = and(_T_1208, asSInt(UInt<14>(0h2000))) node _T_1210 = asSInt(_T_1209) node _T_1211 = eq(_T_1210, asSInt(UInt<1>(0h0))) node _T_1212 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1213 = cvt(_T_1212) node _T_1214 = and(_T_1213, asSInt(UInt<13>(0h1000))) node _T_1215 = asSInt(_T_1214) node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1218 = cvt(_T_1217) node _T_1219 = and(_T_1218, asSInt(UInt<17>(0h10000))) node _T_1220 = asSInt(_T_1219) node _T_1221 = eq(_T_1220, asSInt(UInt<1>(0h0))) node _T_1222 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<18>(0h2f000))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1228 = cvt(_T_1227) node _T_1229 = and(_T_1228, asSInt(UInt<17>(0h10000))) node _T_1230 = asSInt(_T_1229) node _T_1231 = eq(_T_1230, asSInt(UInt<1>(0h0))) node _T_1232 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1233 = cvt(_T_1232) node _T_1234 = and(_T_1233, asSInt(UInt<13>(0h1000))) node _T_1235 = asSInt(_T_1234) node _T_1236 = eq(_T_1235, asSInt(UInt<1>(0h0))) node _T_1237 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1238 = cvt(_T_1237) node _T_1239 = and(_T_1238, asSInt(UInt<17>(0h10000))) node _T_1240 = asSInt(_T_1239) node _T_1241 = eq(_T_1240, asSInt(UInt<1>(0h0))) node _T_1242 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1243 = cvt(_T_1242) node _T_1244 = and(_T_1243, asSInt(UInt<27>(0h4000000))) node _T_1245 = asSInt(_T_1244) node _T_1246 = eq(_T_1245, asSInt(UInt<1>(0h0))) node _T_1247 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1248 = cvt(_T_1247) node _T_1249 = and(_T_1248, asSInt(UInt<13>(0h1000))) node _T_1250 = asSInt(_T_1249) node _T_1251 = eq(_T_1250, asSInt(UInt<1>(0h0))) node _T_1252 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1253 = cvt(_T_1252) node _T_1254 = and(_T_1253, asSInt(UInt<29>(0h10000000))) node _T_1255 = asSInt(_T_1254) node _T_1256 = eq(_T_1255, asSInt(UInt<1>(0h0))) node _T_1257 = or(_T_1211, _T_1216) node _T_1258 = or(_T_1257, _T_1221) node _T_1259 = or(_T_1258, _T_1226) node _T_1260 = or(_T_1259, _T_1231) node _T_1261 = or(_T_1260, _T_1236) node _T_1262 = or(_T_1261, _T_1241) node _T_1263 = or(_T_1262, _T_1246) node _T_1264 = or(_T_1263, _T_1251) node _T_1265 = or(_T_1264, _T_1256) node _T_1266 = and(_T_1206, _T_1265) node _T_1267 = or(UInt<1>(0h0), _T_1266) node _T_1268 = and(_WIRE_5, _T_1267) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_86 node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(address_ok, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1275 = asUInt(reset) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) when _T_1276 : node _T_1277 = eq(legal_source, UInt<1>(0h0)) when _T_1277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1281 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_90 node _T_1285 = eq(io.in.b.bits.mask, mask_1) node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(_T_1285, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1285, UInt<1>(0h1), "") : assert_91 node _T_1289 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_92 node _T_1293 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1293 : node _T_1294 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1295 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1296 = and(_T_1294, _T_1295) node _T_1297 = or(UInt<1>(0h0), _T_1296) node _T_1298 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1299 = cvt(_T_1298) node _T_1300 = and(_T_1299, asSInt(UInt<14>(0h2000))) node _T_1301 = asSInt(_T_1300) node _T_1302 = eq(_T_1301, asSInt(UInt<1>(0h0))) node _T_1303 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1304 = cvt(_T_1303) node _T_1305 = and(_T_1304, asSInt(UInt<13>(0h1000))) node _T_1306 = asSInt(_T_1305) node _T_1307 = eq(_T_1306, asSInt(UInt<1>(0h0))) node _T_1308 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1309 = cvt(_T_1308) node _T_1310 = and(_T_1309, asSInt(UInt<17>(0h10000))) node _T_1311 = asSInt(_T_1310) node _T_1312 = eq(_T_1311, asSInt(UInt<1>(0h0))) node _T_1313 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1314 = cvt(_T_1313) node _T_1315 = and(_T_1314, asSInt(UInt<18>(0h2f000))) node _T_1316 = asSInt(_T_1315) node _T_1317 = eq(_T_1316, asSInt(UInt<1>(0h0))) node _T_1318 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1319 = cvt(_T_1318) node _T_1320 = and(_T_1319, asSInt(UInt<17>(0h10000))) node _T_1321 = asSInt(_T_1320) node _T_1322 = eq(_T_1321, asSInt(UInt<1>(0h0))) node _T_1323 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1324 = cvt(_T_1323) node _T_1325 = and(_T_1324, asSInt(UInt<13>(0h1000))) node _T_1326 = asSInt(_T_1325) node _T_1327 = eq(_T_1326, asSInt(UInt<1>(0h0))) node _T_1328 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1329 = cvt(_T_1328) node _T_1330 = and(_T_1329, asSInt(UInt<17>(0h10000))) node _T_1331 = asSInt(_T_1330) node _T_1332 = eq(_T_1331, asSInt(UInt<1>(0h0))) node _T_1333 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1334 = cvt(_T_1333) node _T_1335 = and(_T_1334, asSInt(UInt<27>(0h4000000))) node _T_1336 = asSInt(_T_1335) node _T_1337 = eq(_T_1336, asSInt(UInt<1>(0h0))) node _T_1338 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1339 = cvt(_T_1338) node _T_1340 = and(_T_1339, asSInt(UInt<13>(0h1000))) node _T_1341 = asSInt(_T_1340) node _T_1342 = eq(_T_1341, asSInt(UInt<1>(0h0))) node _T_1343 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1344 = cvt(_T_1343) node _T_1345 = and(_T_1344, asSInt(UInt<29>(0h10000000))) node _T_1346 = asSInt(_T_1345) node _T_1347 = eq(_T_1346, asSInt(UInt<1>(0h0))) node _T_1348 = or(_T_1302, _T_1307) node _T_1349 = or(_T_1348, _T_1312) node _T_1350 = or(_T_1349, _T_1317) node _T_1351 = or(_T_1350, _T_1322) node _T_1352 = or(_T_1351, _T_1327) node _T_1353 = or(_T_1352, _T_1332) node _T_1354 = or(_T_1353, _T_1337) node _T_1355 = or(_T_1354, _T_1342) node _T_1356 = or(_T_1355, _T_1347) node _T_1357 = and(_T_1297, _T_1356) node _T_1358 = or(UInt<1>(0h0), _T_1357) node _T_1359 = and(UInt<1>(0h0), _T_1358) node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(_T_1359, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1359, UInt<1>(0h1), "") : assert_93 node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(address_ok, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(legal_source, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1372 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_97 node _T_1376 = eq(io.in.b.bits.mask, mask_1) node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(_T_1376, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1376, UInt<1>(0h1), "") : assert_98 node _T_1380 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1381 = asUInt(reset) node _T_1382 = eq(_T_1381, UInt<1>(0h0)) when _T_1382 : node _T_1383 = eq(_T_1380, UInt<1>(0h0)) when _T_1383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1380, UInt<1>(0h1), "") : assert_99 node _T_1384 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1384 : node _T_1385 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1386 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1387 = and(_T_1385, _T_1386) node _T_1388 = or(UInt<1>(0h0), _T_1387) node _T_1389 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1390 = cvt(_T_1389) node _T_1391 = and(_T_1390, asSInt(UInt<14>(0h2000))) node _T_1392 = asSInt(_T_1391) node _T_1393 = eq(_T_1392, asSInt(UInt<1>(0h0))) node _T_1394 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1395 = cvt(_T_1394) node _T_1396 = and(_T_1395, asSInt(UInt<13>(0h1000))) node _T_1397 = asSInt(_T_1396) node _T_1398 = eq(_T_1397, asSInt(UInt<1>(0h0))) node _T_1399 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1400 = cvt(_T_1399) node _T_1401 = and(_T_1400, asSInt(UInt<17>(0h10000))) node _T_1402 = asSInt(_T_1401) node _T_1403 = eq(_T_1402, asSInt(UInt<1>(0h0))) node _T_1404 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1405 = cvt(_T_1404) node _T_1406 = and(_T_1405, asSInt(UInt<18>(0h2f000))) node _T_1407 = asSInt(_T_1406) node _T_1408 = eq(_T_1407, asSInt(UInt<1>(0h0))) node _T_1409 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1410 = cvt(_T_1409) node _T_1411 = and(_T_1410, asSInt(UInt<17>(0h10000))) node _T_1412 = asSInt(_T_1411) node _T_1413 = eq(_T_1412, asSInt(UInt<1>(0h0))) node _T_1414 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1415 = cvt(_T_1414) node _T_1416 = and(_T_1415, asSInt(UInt<13>(0h1000))) node _T_1417 = asSInt(_T_1416) node _T_1418 = eq(_T_1417, asSInt(UInt<1>(0h0))) node _T_1419 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1420 = cvt(_T_1419) node _T_1421 = and(_T_1420, asSInt(UInt<17>(0h10000))) node _T_1422 = asSInt(_T_1421) node _T_1423 = eq(_T_1422, asSInt(UInt<1>(0h0))) node _T_1424 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1425 = cvt(_T_1424) node _T_1426 = and(_T_1425, asSInt(UInt<27>(0h4000000))) node _T_1427 = asSInt(_T_1426) node _T_1428 = eq(_T_1427, asSInt(UInt<1>(0h0))) node _T_1429 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1430 = cvt(_T_1429) node _T_1431 = and(_T_1430, asSInt(UInt<13>(0h1000))) node _T_1432 = asSInt(_T_1431) node _T_1433 = eq(_T_1432, asSInt(UInt<1>(0h0))) node _T_1434 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1435 = cvt(_T_1434) node _T_1436 = and(_T_1435, asSInt(UInt<29>(0h10000000))) node _T_1437 = asSInt(_T_1436) node _T_1438 = eq(_T_1437, asSInt(UInt<1>(0h0))) node _T_1439 = or(_T_1393, _T_1398) node _T_1440 = or(_T_1439, _T_1403) node _T_1441 = or(_T_1440, _T_1408) node _T_1442 = or(_T_1441, _T_1413) node _T_1443 = or(_T_1442, _T_1418) node _T_1444 = or(_T_1443, _T_1423) node _T_1445 = or(_T_1444, _T_1428) node _T_1446 = or(_T_1445, _T_1433) node _T_1447 = or(_T_1446, _T_1438) node _T_1448 = and(_T_1388, _T_1447) node _T_1449 = or(UInt<1>(0h0), _T_1448) node _T_1450 = and(UInt<1>(0h0), _T_1449) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_100 node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(address_ok, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(legal_source, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1463 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_104 node _T_1467 = eq(io.in.b.bits.mask, mask_1) node _T_1468 = asUInt(reset) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(_T_1467, UInt<1>(0h0)) when _T_1470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1467, UInt<1>(0h1), "") : assert_105 node _T_1471 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1471 : node _T_1472 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1473 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1474 = and(_T_1472, _T_1473) node _T_1475 = or(UInt<1>(0h0), _T_1474) node _T_1476 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1477 = cvt(_T_1476) node _T_1478 = and(_T_1477, asSInt(UInt<14>(0h2000))) node _T_1479 = asSInt(_T_1478) node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0))) node _T_1481 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1482 = cvt(_T_1481) node _T_1483 = and(_T_1482, asSInt(UInt<13>(0h1000))) node _T_1484 = asSInt(_T_1483) node _T_1485 = eq(_T_1484, asSInt(UInt<1>(0h0))) node _T_1486 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1487 = cvt(_T_1486) node _T_1488 = and(_T_1487, asSInt(UInt<17>(0h10000))) node _T_1489 = asSInt(_T_1488) node _T_1490 = eq(_T_1489, asSInt(UInt<1>(0h0))) node _T_1491 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1492 = cvt(_T_1491) node _T_1493 = and(_T_1492, asSInt(UInt<18>(0h2f000))) node _T_1494 = asSInt(_T_1493) node _T_1495 = eq(_T_1494, asSInt(UInt<1>(0h0))) node _T_1496 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1497 = cvt(_T_1496) node _T_1498 = and(_T_1497, asSInt(UInt<17>(0h10000))) node _T_1499 = asSInt(_T_1498) node _T_1500 = eq(_T_1499, asSInt(UInt<1>(0h0))) node _T_1501 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1502 = cvt(_T_1501) node _T_1503 = and(_T_1502, asSInt(UInt<13>(0h1000))) node _T_1504 = asSInt(_T_1503) node _T_1505 = eq(_T_1504, asSInt(UInt<1>(0h0))) node _T_1506 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1507 = cvt(_T_1506) node _T_1508 = and(_T_1507, asSInt(UInt<17>(0h10000))) node _T_1509 = asSInt(_T_1508) node _T_1510 = eq(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1512 = cvt(_T_1511) node _T_1513 = and(_T_1512, asSInt(UInt<27>(0h4000000))) node _T_1514 = asSInt(_T_1513) node _T_1515 = eq(_T_1514, asSInt(UInt<1>(0h0))) node _T_1516 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1517 = cvt(_T_1516) node _T_1518 = and(_T_1517, asSInt(UInt<13>(0h1000))) node _T_1519 = asSInt(_T_1518) node _T_1520 = eq(_T_1519, asSInt(UInt<1>(0h0))) node _T_1521 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1522 = cvt(_T_1521) node _T_1523 = and(_T_1522, asSInt(UInt<29>(0h10000000))) node _T_1524 = asSInt(_T_1523) node _T_1525 = eq(_T_1524, asSInt(UInt<1>(0h0))) node _T_1526 = or(_T_1480, _T_1485) node _T_1527 = or(_T_1526, _T_1490) node _T_1528 = or(_T_1527, _T_1495) node _T_1529 = or(_T_1528, _T_1500) node _T_1530 = or(_T_1529, _T_1505) node _T_1531 = or(_T_1530, _T_1510) node _T_1532 = or(_T_1531, _T_1515) node _T_1533 = or(_T_1532, _T_1520) node _T_1534 = or(_T_1533, _T_1525) node _T_1535 = and(_T_1475, _T_1534) node _T_1536 = or(UInt<1>(0h0), _T_1535) node _T_1537 = and(UInt<1>(0h0), _T_1536) node _T_1538 = asUInt(reset) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) when _T_1539 : node _T_1540 = eq(_T_1537, UInt<1>(0h0)) when _T_1540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1537, UInt<1>(0h1), "") : assert_106 node _T_1541 = asUInt(reset) node _T_1542 = eq(_T_1541, UInt<1>(0h0)) when _T_1542 : node _T_1543 = eq(address_ok, UInt<1>(0h0)) when _T_1543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(legal_source, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1547 = asUInt(reset) node _T_1548 = eq(_T_1547, UInt<1>(0h0)) when _T_1548 : node _T_1549 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1550 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(_T_1550, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1550, UInt<1>(0h1), "") : assert_110 node _T_1554 = not(mask_1) node _T_1555 = and(io.in.b.bits.mask, _T_1554) node _T_1556 = eq(_T_1555, UInt<1>(0h0)) node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(_T_1556, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1556, UInt<1>(0h1), "") : assert_111 node _T_1560 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1560 : node _T_1561 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1562 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1563 = and(_T_1561, _T_1562) node _T_1564 = or(UInt<1>(0h0), _T_1563) node _T_1565 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1566 = cvt(_T_1565) node _T_1567 = and(_T_1566, asSInt(UInt<14>(0h2000))) node _T_1568 = asSInt(_T_1567) node _T_1569 = eq(_T_1568, asSInt(UInt<1>(0h0))) node _T_1570 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1571 = cvt(_T_1570) node _T_1572 = and(_T_1571, asSInt(UInt<13>(0h1000))) node _T_1573 = asSInt(_T_1572) node _T_1574 = eq(_T_1573, asSInt(UInt<1>(0h0))) node _T_1575 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1576 = cvt(_T_1575) node _T_1577 = and(_T_1576, asSInt(UInt<17>(0h10000))) node _T_1578 = asSInt(_T_1577) node _T_1579 = eq(_T_1578, asSInt(UInt<1>(0h0))) node _T_1580 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1581 = cvt(_T_1580) node _T_1582 = and(_T_1581, asSInt(UInt<18>(0h2f000))) node _T_1583 = asSInt(_T_1582) node _T_1584 = eq(_T_1583, asSInt(UInt<1>(0h0))) node _T_1585 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1586 = cvt(_T_1585) node _T_1587 = and(_T_1586, asSInt(UInt<17>(0h10000))) node _T_1588 = asSInt(_T_1587) node _T_1589 = eq(_T_1588, asSInt(UInt<1>(0h0))) node _T_1590 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1591 = cvt(_T_1590) node _T_1592 = and(_T_1591, asSInt(UInt<13>(0h1000))) node _T_1593 = asSInt(_T_1592) node _T_1594 = eq(_T_1593, asSInt(UInt<1>(0h0))) node _T_1595 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1596 = cvt(_T_1595) node _T_1597 = and(_T_1596, asSInt(UInt<17>(0h10000))) node _T_1598 = asSInt(_T_1597) node _T_1599 = eq(_T_1598, asSInt(UInt<1>(0h0))) node _T_1600 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1601 = cvt(_T_1600) node _T_1602 = and(_T_1601, asSInt(UInt<27>(0h4000000))) node _T_1603 = asSInt(_T_1602) node _T_1604 = eq(_T_1603, asSInt(UInt<1>(0h0))) node _T_1605 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1606 = cvt(_T_1605) node _T_1607 = and(_T_1606, asSInt(UInt<13>(0h1000))) node _T_1608 = asSInt(_T_1607) node _T_1609 = eq(_T_1608, asSInt(UInt<1>(0h0))) node _T_1610 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1611 = cvt(_T_1610) node _T_1612 = and(_T_1611, asSInt(UInt<29>(0h10000000))) node _T_1613 = asSInt(_T_1612) node _T_1614 = eq(_T_1613, asSInt(UInt<1>(0h0))) node _T_1615 = or(_T_1569, _T_1574) node _T_1616 = or(_T_1615, _T_1579) node _T_1617 = or(_T_1616, _T_1584) node _T_1618 = or(_T_1617, _T_1589) node _T_1619 = or(_T_1618, _T_1594) node _T_1620 = or(_T_1619, _T_1599) node _T_1621 = or(_T_1620, _T_1604) node _T_1622 = or(_T_1621, _T_1609) node _T_1623 = or(_T_1622, _T_1614) node _T_1624 = and(_T_1564, _T_1623) node _T_1625 = or(UInt<1>(0h0), _T_1624) node _T_1626 = and(UInt<1>(0h0), _T_1625) node _T_1627 = asUInt(reset) node _T_1628 = eq(_T_1627, UInt<1>(0h0)) when _T_1628 : node _T_1629 = eq(_T_1626, UInt<1>(0h0)) when _T_1629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1626, UInt<1>(0h1), "") : assert_112 node _T_1630 = asUInt(reset) node _T_1631 = eq(_T_1630, UInt<1>(0h0)) when _T_1631 : node _T_1632 = eq(address_ok, UInt<1>(0h0)) when _T_1632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1633 = asUInt(reset) node _T_1634 = eq(_T_1633, UInt<1>(0h0)) when _T_1634 : node _T_1635 = eq(legal_source, UInt<1>(0h0)) when _T_1635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1636 = asUInt(reset) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1639 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(_T_1639, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1639, UInt<1>(0h1), "") : assert_116 node _T_1643 = eq(io.in.b.bits.mask, mask_1) node _T_1644 = asUInt(reset) node _T_1645 = eq(_T_1644, UInt<1>(0h0)) when _T_1645 : node _T_1646 = eq(_T_1643, UInt<1>(0h0)) when _T_1646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1643, UInt<1>(0h1), "") : assert_117 node _T_1647 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1647 : node _T_1648 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1649 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1650 = and(_T_1648, _T_1649) node _T_1651 = or(UInt<1>(0h0), _T_1650) node _T_1652 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1653 = cvt(_T_1652) node _T_1654 = and(_T_1653, asSInt(UInt<14>(0h2000))) node _T_1655 = asSInt(_T_1654) node _T_1656 = eq(_T_1655, asSInt(UInt<1>(0h0))) node _T_1657 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1658 = cvt(_T_1657) node _T_1659 = and(_T_1658, asSInt(UInt<13>(0h1000))) node _T_1660 = asSInt(_T_1659) node _T_1661 = eq(_T_1660, asSInt(UInt<1>(0h0))) node _T_1662 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1663 = cvt(_T_1662) node _T_1664 = and(_T_1663, asSInt(UInt<17>(0h10000))) node _T_1665 = asSInt(_T_1664) node _T_1666 = eq(_T_1665, asSInt(UInt<1>(0h0))) node _T_1667 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1668 = cvt(_T_1667) node _T_1669 = and(_T_1668, asSInt(UInt<18>(0h2f000))) node _T_1670 = asSInt(_T_1669) node _T_1671 = eq(_T_1670, asSInt(UInt<1>(0h0))) node _T_1672 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1673 = cvt(_T_1672) node _T_1674 = and(_T_1673, asSInt(UInt<17>(0h10000))) node _T_1675 = asSInt(_T_1674) node _T_1676 = eq(_T_1675, asSInt(UInt<1>(0h0))) node _T_1677 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1678 = cvt(_T_1677) node _T_1679 = and(_T_1678, asSInt(UInt<13>(0h1000))) node _T_1680 = asSInt(_T_1679) node _T_1681 = eq(_T_1680, asSInt(UInt<1>(0h0))) node _T_1682 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1683 = cvt(_T_1682) node _T_1684 = and(_T_1683, asSInt(UInt<17>(0h10000))) node _T_1685 = asSInt(_T_1684) node _T_1686 = eq(_T_1685, asSInt(UInt<1>(0h0))) node _T_1687 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1688 = cvt(_T_1687) node _T_1689 = and(_T_1688, asSInt(UInt<27>(0h4000000))) node _T_1690 = asSInt(_T_1689) node _T_1691 = eq(_T_1690, asSInt(UInt<1>(0h0))) node _T_1692 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1693 = cvt(_T_1692) node _T_1694 = and(_T_1693, asSInt(UInt<13>(0h1000))) node _T_1695 = asSInt(_T_1694) node _T_1696 = eq(_T_1695, asSInt(UInt<1>(0h0))) node _T_1697 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1698 = cvt(_T_1697) node _T_1699 = and(_T_1698, asSInt(UInt<29>(0h10000000))) node _T_1700 = asSInt(_T_1699) node _T_1701 = eq(_T_1700, asSInt(UInt<1>(0h0))) node _T_1702 = or(_T_1656, _T_1661) node _T_1703 = or(_T_1702, _T_1666) node _T_1704 = or(_T_1703, _T_1671) node _T_1705 = or(_T_1704, _T_1676) node _T_1706 = or(_T_1705, _T_1681) node _T_1707 = or(_T_1706, _T_1686) node _T_1708 = or(_T_1707, _T_1691) node _T_1709 = or(_T_1708, _T_1696) node _T_1710 = or(_T_1709, _T_1701) node _T_1711 = and(_T_1651, _T_1710) node _T_1712 = or(UInt<1>(0h0), _T_1711) node _T_1713 = and(UInt<1>(0h0), _T_1712) node _T_1714 = asUInt(reset) node _T_1715 = eq(_T_1714, UInt<1>(0h0)) when _T_1715 : node _T_1716 = eq(_T_1713, UInt<1>(0h0)) when _T_1716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1713, UInt<1>(0h1), "") : assert_118 node _T_1717 = asUInt(reset) node _T_1718 = eq(_T_1717, UInt<1>(0h0)) when _T_1718 : node _T_1719 = eq(address_ok, UInt<1>(0h0)) when _T_1719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1720 = asUInt(reset) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) when _T_1721 : node _T_1722 = eq(legal_source, UInt<1>(0h0)) when _T_1722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1723 = asUInt(reset) node _T_1724 = eq(_T_1723, UInt<1>(0h0)) when _T_1724 : node _T_1725 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1726 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1727 = asUInt(reset) node _T_1728 = eq(_T_1727, UInt<1>(0h0)) when _T_1728 : node _T_1729 = eq(_T_1726, UInt<1>(0h0)) when _T_1729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1726, UInt<1>(0h1), "") : assert_122 node _T_1730 = eq(io.in.b.bits.mask, mask_1) node _T_1731 = asUInt(reset) node _T_1732 = eq(_T_1731, UInt<1>(0h0)) when _T_1732 : node _T_1733 = eq(_T_1730, UInt<1>(0h0)) when _T_1733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1730, UInt<1>(0h1), "") : assert_123 node _T_1734 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1734 : node _T_1735 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1736 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1737 = and(_T_1735, _T_1736) node _T_1738 = or(UInt<1>(0h0), _T_1737) node _T_1739 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1740 = cvt(_T_1739) node _T_1741 = and(_T_1740, asSInt(UInt<14>(0h2000))) node _T_1742 = asSInt(_T_1741) node _T_1743 = eq(_T_1742, asSInt(UInt<1>(0h0))) node _T_1744 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1745 = cvt(_T_1744) node _T_1746 = and(_T_1745, asSInt(UInt<13>(0h1000))) node _T_1747 = asSInt(_T_1746) node _T_1748 = eq(_T_1747, asSInt(UInt<1>(0h0))) node _T_1749 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1750 = cvt(_T_1749) node _T_1751 = and(_T_1750, asSInt(UInt<17>(0h10000))) node _T_1752 = asSInt(_T_1751) node _T_1753 = eq(_T_1752, asSInt(UInt<1>(0h0))) node _T_1754 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1755 = cvt(_T_1754) node _T_1756 = and(_T_1755, asSInt(UInt<18>(0h2f000))) node _T_1757 = asSInt(_T_1756) node _T_1758 = eq(_T_1757, asSInt(UInt<1>(0h0))) node _T_1759 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1760 = cvt(_T_1759) node _T_1761 = and(_T_1760, asSInt(UInt<17>(0h10000))) node _T_1762 = asSInt(_T_1761) node _T_1763 = eq(_T_1762, asSInt(UInt<1>(0h0))) node _T_1764 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1765 = cvt(_T_1764) node _T_1766 = and(_T_1765, asSInt(UInt<13>(0h1000))) node _T_1767 = asSInt(_T_1766) node _T_1768 = eq(_T_1767, asSInt(UInt<1>(0h0))) node _T_1769 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1770 = cvt(_T_1769) node _T_1771 = and(_T_1770, asSInt(UInt<17>(0h10000))) node _T_1772 = asSInt(_T_1771) node _T_1773 = eq(_T_1772, asSInt(UInt<1>(0h0))) node _T_1774 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1775 = cvt(_T_1774) node _T_1776 = and(_T_1775, asSInt(UInt<27>(0h4000000))) node _T_1777 = asSInt(_T_1776) node _T_1778 = eq(_T_1777, asSInt(UInt<1>(0h0))) node _T_1779 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1780 = cvt(_T_1779) node _T_1781 = and(_T_1780, asSInt(UInt<13>(0h1000))) node _T_1782 = asSInt(_T_1781) node _T_1783 = eq(_T_1782, asSInt(UInt<1>(0h0))) node _T_1784 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1785 = cvt(_T_1784) node _T_1786 = and(_T_1785, asSInt(UInt<29>(0h10000000))) node _T_1787 = asSInt(_T_1786) node _T_1788 = eq(_T_1787, asSInt(UInt<1>(0h0))) node _T_1789 = or(_T_1743, _T_1748) node _T_1790 = or(_T_1789, _T_1753) node _T_1791 = or(_T_1790, _T_1758) node _T_1792 = or(_T_1791, _T_1763) node _T_1793 = or(_T_1792, _T_1768) node _T_1794 = or(_T_1793, _T_1773) node _T_1795 = or(_T_1794, _T_1778) node _T_1796 = or(_T_1795, _T_1783) node _T_1797 = or(_T_1796, _T_1788) node _T_1798 = and(_T_1738, _T_1797) node _T_1799 = or(UInt<1>(0h0), _T_1798) node _T_1800 = and(UInt<1>(0h0), _T_1799) node _T_1801 = asUInt(reset) node _T_1802 = eq(_T_1801, UInt<1>(0h0)) when _T_1802 : node _T_1803 = eq(_T_1800, UInt<1>(0h0)) when _T_1803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1800, UInt<1>(0h1), "") : assert_124 node _T_1804 = asUInt(reset) node _T_1805 = eq(_T_1804, UInt<1>(0h0)) when _T_1805 : node _T_1806 = eq(address_ok, UInt<1>(0h0)) when _T_1806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1807 = asUInt(reset) node _T_1808 = eq(_T_1807, UInt<1>(0h0)) when _T_1808 : node _T_1809 = eq(legal_source, UInt<1>(0h0)) when _T_1809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1813 = eq(io.in.b.bits.mask, mask_1) node _T_1814 = asUInt(reset) node _T_1815 = eq(_T_1814, UInt<1>(0h0)) when _T_1815 : node _T_1816 = eq(_T_1813, UInt<1>(0h0)) when _T_1816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1813, UInt<1>(0h1), "") : assert_128 node _T_1817 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1818 = asUInt(reset) node _T_1819 = eq(_T_1818, UInt<1>(0h0)) when _T_1819 : node _T_1820 = eq(_T_1817, UInt<1>(0h0)) when _T_1820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1817, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1821 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1822 = asUInt(reset) node _T_1823 = eq(_T_1822, UInt<1>(0h0)) when _T_1823 : node _T_1824 = eq(_T_1821, UInt<1>(0h0)) when _T_1824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1821, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_14 = shr(io.in.c.bits.source, 2) node _source_ok_T_15 = eq(_source_ok_T_14, UInt<1>(0h0)) node _source_ok_T_16 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_T_18 = leq(source_ok_uncommonBits_2, UInt<2>(0h2)) node _source_ok_T_19 = and(_source_ok_T_17, _source_ok_T_18) node _source_ok_T_20 = eq(io.in.c.bits.source, UInt<2>(0h3)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_19 connect _source_ok_WIRE_2[1], _source_ok_T_20 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_1825 = shr(io.in.c.bits.source, 2) node _T_1826 = eq(_T_1825, UInt<1>(0h0)) node _T_1827 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1828 = and(_T_1826, _T_1827) node _T_1829 = leq(uncommonBits_13, UInt<2>(0h2)) node _T_1830 = and(_T_1828, _T_1829) node _T_1831 = eq(_T_1830, UInt<1>(0h0)) node _T_1832 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<1>(0h0))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = or(_T_1831, _T_1836) node _T_1838 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_1839 = eq(_T_1838, UInt<1>(0h0)) node _T_1840 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1841 = cvt(_T_1840) node _T_1842 = and(_T_1841, asSInt(UInt<1>(0h0))) node _T_1843 = asSInt(_T_1842) node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0))) node _T_1845 = or(_T_1839, _T_1844) node _T_1846 = and(_T_1837, _T_1845) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_131 node _T_1850 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1850 : node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(address_ok_1, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1854 = asUInt(reset) node _T_1855 = eq(_T_1854, UInt<1>(0h0)) when _T_1855 : node _T_1856 = eq(source_ok_2, UInt<1>(0h0)) when _T_1856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1857 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(_T_1857, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1857, UInt<1>(0h1), "") : assert_134 node _T_1861 = asUInt(reset) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : node _T_1863 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1864 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_136 node _T_1868 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_137 node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1872 : node _T_1873 = asUInt(reset) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) when _T_1874 : node _T_1875 = eq(address_ok_1, UInt<1>(0h0)) when _T_1875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1876 = asUInt(reset) node _T_1877 = eq(_T_1876, UInt<1>(0h0)) when _T_1877 : node _T_1878 = eq(source_ok_2, UInt<1>(0h0)) when _T_1878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1879 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_140 node _T_1883 = asUInt(reset) node _T_1884 = eq(_T_1883, UInt<1>(0h0)) when _T_1884 : node _T_1885 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1886 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1887 = asUInt(reset) node _T_1888 = eq(_T_1887, UInt<1>(0h0)) when _T_1888 : node _T_1889 = eq(_T_1886, UInt<1>(0h0)) when _T_1889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1886, UInt<1>(0h1), "") : assert_142 node _T_1890 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1890 : node _T_1891 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1892 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1893 = and(_T_1891, _T_1892) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_1894 = shr(io.in.c.bits.source, 2) node _T_1895 = eq(_T_1894, UInt<1>(0h0)) node _T_1896 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1897 = and(_T_1895, _T_1896) node _T_1898 = leq(uncommonBits_14, UInt<2>(0h2)) node _T_1899 = and(_T_1897, _T_1898) node _T_1900 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_1901 = or(_T_1899, _T_1900) node _T_1902 = and(_T_1893, _T_1901) node _T_1903 = or(UInt<1>(0h0), _T_1902) node _T_1904 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1905 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1906 = cvt(_T_1905) node _T_1907 = and(_T_1906, asSInt(UInt<14>(0h2000))) node _T_1908 = asSInt(_T_1907) node _T_1909 = eq(_T_1908, asSInt(UInt<1>(0h0))) node _T_1910 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1911 = cvt(_T_1910) node _T_1912 = and(_T_1911, asSInt(UInt<13>(0h1000))) node _T_1913 = asSInt(_T_1912) node _T_1914 = eq(_T_1913, asSInt(UInt<1>(0h0))) node _T_1915 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1916 = cvt(_T_1915) node _T_1917 = and(_T_1916, asSInt(UInt<17>(0h10000))) node _T_1918 = asSInt(_T_1917) node _T_1919 = eq(_T_1918, asSInt(UInt<1>(0h0))) node _T_1920 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1921 = cvt(_T_1920) node _T_1922 = and(_T_1921, asSInt(UInt<18>(0h2f000))) node _T_1923 = asSInt(_T_1922) node _T_1924 = eq(_T_1923, asSInt(UInt<1>(0h0))) node _T_1925 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1926 = cvt(_T_1925) node _T_1927 = and(_T_1926, asSInt(UInt<17>(0h10000))) node _T_1928 = asSInt(_T_1927) node _T_1929 = eq(_T_1928, asSInt(UInt<1>(0h0))) node _T_1930 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1931 = cvt(_T_1930) node _T_1932 = and(_T_1931, asSInt(UInt<13>(0h1000))) node _T_1933 = asSInt(_T_1932) node _T_1934 = eq(_T_1933, asSInt(UInt<1>(0h0))) node _T_1935 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1936 = cvt(_T_1935) node _T_1937 = and(_T_1936, asSInt(UInt<27>(0h4000000))) node _T_1938 = asSInt(_T_1937) node _T_1939 = eq(_T_1938, asSInt(UInt<1>(0h0))) node _T_1940 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1941 = cvt(_T_1940) node _T_1942 = and(_T_1941, asSInt(UInt<13>(0h1000))) node _T_1943 = asSInt(_T_1942) node _T_1944 = eq(_T_1943, asSInt(UInt<1>(0h0))) node _T_1945 = or(_T_1909, _T_1914) node _T_1946 = or(_T_1945, _T_1919) node _T_1947 = or(_T_1946, _T_1924) node _T_1948 = or(_T_1947, _T_1929) node _T_1949 = or(_T_1948, _T_1934) node _T_1950 = or(_T_1949, _T_1939) node _T_1951 = or(_T_1950, _T_1944) node _T_1952 = and(_T_1904, _T_1951) node _T_1953 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1954 = or(UInt<1>(0h0), _T_1953) node _T_1955 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1956 = cvt(_T_1955) node _T_1957 = and(_T_1956, asSInt(UInt<17>(0h10000))) node _T_1958 = asSInt(_T_1957) node _T_1959 = eq(_T_1958, asSInt(UInt<1>(0h0))) node _T_1960 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1961 = cvt(_T_1960) node _T_1962 = and(_T_1961, asSInt(UInt<29>(0h10000000))) node _T_1963 = asSInt(_T_1962) node _T_1964 = eq(_T_1963, asSInt(UInt<1>(0h0))) node _T_1965 = or(_T_1959, _T_1964) node _T_1966 = and(_T_1954, _T_1965) node _T_1967 = or(UInt<1>(0h0), _T_1952) node _T_1968 = or(_T_1967, _T_1966) node _T_1969 = and(_T_1903, _T_1968) node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(_T_1969, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1969, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_1973 = shr(io.in.c.bits.source, 2) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) node _T_1975 = leq(UInt<1>(0h0), uncommonBits_15) node _T_1976 = and(_T_1974, _T_1975) node _T_1977 = leq(uncommonBits_15, UInt<2>(0h2)) node _T_1978 = and(_T_1976, _T_1977) node _T_1979 = eq(io.in.c.bits.source, UInt<2>(0h3)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_1978 connect _WIRE_6[1], _T_1979 node _T_1980 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1981 = mux(_WIRE_6[0], _T_1980, UInt<1>(0h0)) node _T_1982 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1983 = or(_T_1981, _T_1982) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1983 node _T_1984 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1985 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1986 = and(_T_1984, _T_1985) node _T_1987 = or(UInt<1>(0h0), _T_1986) node _T_1988 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1989 = cvt(_T_1988) node _T_1990 = and(_T_1989, asSInt(UInt<14>(0h2000))) node _T_1991 = asSInt(_T_1990) node _T_1992 = eq(_T_1991, asSInt(UInt<1>(0h0))) node _T_1993 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1994 = cvt(_T_1993) node _T_1995 = and(_T_1994, asSInt(UInt<13>(0h1000))) node _T_1996 = asSInt(_T_1995) node _T_1997 = eq(_T_1996, asSInt(UInt<1>(0h0))) node _T_1998 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1999 = cvt(_T_1998) node _T_2000 = and(_T_1999, asSInt(UInt<17>(0h10000))) node _T_2001 = asSInt(_T_2000) node _T_2002 = eq(_T_2001, asSInt(UInt<1>(0h0))) node _T_2003 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2004 = cvt(_T_2003) node _T_2005 = and(_T_2004, asSInt(UInt<18>(0h2f000))) node _T_2006 = asSInt(_T_2005) node _T_2007 = eq(_T_2006, asSInt(UInt<1>(0h0))) node _T_2008 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2009 = cvt(_T_2008) node _T_2010 = and(_T_2009, asSInt(UInt<17>(0h10000))) node _T_2011 = asSInt(_T_2010) node _T_2012 = eq(_T_2011, asSInt(UInt<1>(0h0))) node _T_2013 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2014 = cvt(_T_2013) node _T_2015 = and(_T_2014, asSInt(UInt<13>(0h1000))) node _T_2016 = asSInt(_T_2015) node _T_2017 = eq(_T_2016, asSInt(UInt<1>(0h0))) node _T_2018 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2019 = cvt(_T_2018) node _T_2020 = and(_T_2019, asSInt(UInt<17>(0h10000))) node _T_2021 = asSInt(_T_2020) node _T_2022 = eq(_T_2021, asSInt(UInt<1>(0h0))) node _T_2023 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2024 = cvt(_T_2023) node _T_2025 = and(_T_2024, asSInt(UInt<27>(0h4000000))) node _T_2026 = asSInt(_T_2025) node _T_2027 = eq(_T_2026, asSInt(UInt<1>(0h0))) node _T_2028 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2029 = cvt(_T_2028) node _T_2030 = and(_T_2029, asSInt(UInt<13>(0h1000))) node _T_2031 = asSInt(_T_2030) node _T_2032 = eq(_T_2031, asSInt(UInt<1>(0h0))) node _T_2033 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2034 = cvt(_T_2033) node _T_2035 = and(_T_2034, asSInt(UInt<29>(0h10000000))) node _T_2036 = asSInt(_T_2035) node _T_2037 = eq(_T_2036, asSInt(UInt<1>(0h0))) node _T_2038 = or(_T_1992, _T_1997) node _T_2039 = or(_T_2038, _T_2002) node _T_2040 = or(_T_2039, _T_2007) node _T_2041 = or(_T_2040, _T_2012) node _T_2042 = or(_T_2041, _T_2017) node _T_2043 = or(_T_2042, _T_2022) node _T_2044 = or(_T_2043, _T_2027) node _T_2045 = or(_T_2044, _T_2032) node _T_2046 = or(_T_2045, _T_2037) node _T_2047 = and(_T_1987, _T_2046) node _T_2048 = or(UInt<1>(0h0), _T_2047) node _T_2049 = and(_WIRE_7, _T_2048) node _T_2050 = asUInt(reset) node _T_2051 = eq(_T_2050, UInt<1>(0h0)) when _T_2051 : node _T_2052 = eq(_T_2049, UInt<1>(0h0)) when _T_2052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2049, UInt<1>(0h1), "") : assert_144 node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(source_ok_2, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2056 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2057 = asUInt(reset) node _T_2058 = eq(_T_2057, UInt<1>(0h0)) when _T_2058 : node _T_2059 = eq(_T_2056, UInt<1>(0h0)) when _T_2059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2056, UInt<1>(0h1), "") : assert_146 node _T_2060 = asUInt(reset) node _T_2061 = eq(_T_2060, UInt<1>(0h0)) when _T_2061 : node _T_2062 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2063 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2064 = asUInt(reset) node _T_2065 = eq(_T_2064, UInt<1>(0h0)) when _T_2065 : node _T_2066 = eq(_T_2063, UInt<1>(0h0)) when _T_2066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2063, UInt<1>(0h1), "") : assert_148 node _T_2067 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2068 = asUInt(reset) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) when _T_2069 : node _T_2070 = eq(_T_2067, UInt<1>(0h0)) when _T_2070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2067, UInt<1>(0h1), "") : assert_149 node _T_2071 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2071 : node _T_2072 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2073 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2074 = and(_T_2072, _T_2073) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_2075 = shr(io.in.c.bits.source, 2) node _T_2076 = eq(_T_2075, UInt<1>(0h0)) node _T_2077 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2078 = and(_T_2076, _T_2077) node _T_2079 = leq(uncommonBits_16, UInt<2>(0h2)) node _T_2080 = and(_T_2078, _T_2079) node _T_2081 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_2082 = or(_T_2080, _T_2081) node _T_2083 = and(_T_2074, _T_2082) node _T_2084 = or(UInt<1>(0h0), _T_2083) node _T_2085 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2086 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2087 = cvt(_T_2086) node _T_2088 = and(_T_2087, asSInt(UInt<14>(0h2000))) node _T_2089 = asSInt(_T_2088) node _T_2090 = eq(_T_2089, asSInt(UInt<1>(0h0))) node _T_2091 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2092 = cvt(_T_2091) node _T_2093 = and(_T_2092, asSInt(UInt<13>(0h1000))) node _T_2094 = asSInt(_T_2093) node _T_2095 = eq(_T_2094, asSInt(UInt<1>(0h0))) node _T_2096 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2097 = cvt(_T_2096) node _T_2098 = and(_T_2097, asSInt(UInt<17>(0h10000))) node _T_2099 = asSInt(_T_2098) node _T_2100 = eq(_T_2099, asSInt(UInt<1>(0h0))) node _T_2101 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2102 = cvt(_T_2101) node _T_2103 = and(_T_2102, asSInt(UInt<18>(0h2f000))) node _T_2104 = asSInt(_T_2103) node _T_2105 = eq(_T_2104, asSInt(UInt<1>(0h0))) node _T_2106 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2107 = cvt(_T_2106) node _T_2108 = and(_T_2107, asSInt(UInt<17>(0h10000))) node _T_2109 = asSInt(_T_2108) node _T_2110 = eq(_T_2109, asSInt(UInt<1>(0h0))) node _T_2111 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2112 = cvt(_T_2111) node _T_2113 = and(_T_2112, asSInt(UInt<13>(0h1000))) node _T_2114 = asSInt(_T_2113) node _T_2115 = eq(_T_2114, asSInt(UInt<1>(0h0))) node _T_2116 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2117 = cvt(_T_2116) node _T_2118 = and(_T_2117, asSInt(UInt<27>(0h4000000))) node _T_2119 = asSInt(_T_2118) node _T_2120 = eq(_T_2119, asSInt(UInt<1>(0h0))) node _T_2121 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2122 = cvt(_T_2121) node _T_2123 = and(_T_2122, asSInt(UInt<13>(0h1000))) node _T_2124 = asSInt(_T_2123) node _T_2125 = eq(_T_2124, asSInt(UInt<1>(0h0))) node _T_2126 = or(_T_2090, _T_2095) node _T_2127 = or(_T_2126, _T_2100) node _T_2128 = or(_T_2127, _T_2105) node _T_2129 = or(_T_2128, _T_2110) node _T_2130 = or(_T_2129, _T_2115) node _T_2131 = or(_T_2130, _T_2120) node _T_2132 = or(_T_2131, _T_2125) node _T_2133 = and(_T_2085, _T_2132) node _T_2134 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2135 = or(UInt<1>(0h0), _T_2134) node _T_2136 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2137 = cvt(_T_2136) node _T_2138 = and(_T_2137, asSInt(UInt<17>(0h10000))) node _T_2139 = asSInt(_T_2138) node _T_2140 = eq(_T_2139, asSInt(UInt<1>(0h0))) node _T_2141 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2142 = cvt(_T_2141) node _T_2143 = and(_T_2142, asSInt(UInt<29>(0h10000000))) node _T_2144 = asSInt(_T_2143) node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0))) node _T_2146 = or(_T_2140, _T_2145) node _T_2147 = and(_T_2135, _T_2146) node _T_2148 = or(UInt<1>(0h0), _T_2133) node _T_2149 = or(_T_2148, _T_2147) node _T_2150 = and(_T_2084, _T_2149) node _T_2151 = asUInt(reset) node _T_2152 = eq(_T_2151, UInt<1>(0h0)) when _T_2152 : node _T_2153 = eq(_T_2150, UInt<1>(0h0)) when _T_2153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2150, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_2154 = shr(io.in.c.bits.source, 2) node _T_2155 = eq(_T_2154, UInt<1>(0h0)) node _T_2156 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2157 = and(_T_2155, _T_2156) node _T_2158 = leq(uncommonBits_17, UInt<2>(0h2)) node _T_2159 = and(_T_2157, _T_2158) node _T_2160 = eq(io.in.c.bits.source, UInt<2>(0h3)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2159 connect _WIRE_8[1], _T_2160 node _T_2161 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2162 = mux(_WIRE_8[0], _T_2161, UInt<1>(0h0)) node _T_2163 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2164 = or(_T_2162, _T_2163) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2164 node _T_2165 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2166 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2167 = and(_T_2165, _T_2166) node _T_2168 = or(UInt<1>(0h0), _T_2167) node _T_2169 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2170 = cvt(_T_2169) node _T_2171 = and(_T_2170, asSInt(UInt<14>(0h2000))) node _T_2172 = asSInt(_T_2171) node _T_2173 = eq(_T_2172, asSInt(UInt<1>(0h0))) node _T_2174 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2175 = cvt(_T_2174) node _T_2176 = and(_T_2175, asSInt(UInt<13>(0h1000))) node _T_2177 = asSInt(_T_2176) node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0))) node _T_2179 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2180 = cvt(_T_2179) node _T_2181 = and(_T_2180, asSInt(UInt<17>(0h10000))) node _T_2182 = asSInt(_T_2181) node _T_2183 = eq(_T_2182, asSInt(UInt<1>(0h0))) node _T_2184 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2185 = cvt(_T_2184) node _T_2186 = and(_T_2185, asSInt(UInt<18>(0h2f000))) node _T_2187 = asSInt(_T_2186) node _T_2188 = eq(_T_2187, asSInt(UInt<1>(0h0))) node _T_2189 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2190 = cvt(_T_2189) node _T_2191 = and(_T_2190, asSInt(UInt<17>(0h10000))) node _T_2192 = asSInt(_T_2191) node _T_2193 = eq(_T_2192, asSInt(UInt<1>(0h0))) node _T_2194 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2195 = cvt(_T_2194) node _T_2196 = and(_T_2195, asSInt(UInt<13>(0h1000))) node _T_2197 = asSInt(_T_2196) node _T_2198 = eq(_T_2197, asSInt(UInt<1>(0h0))) node _T_2199 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2200 = cvt(_T_2199) node _T_2201 = and(_T_2200, asSInt(UInt<17>(0h10000))) node _T_2202 = asSInt(_T_2201) node _T_2203 = eq(_T_2202, asSInt(UInt<1>(0h0))) node _T_2204 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2205 = cvt(_T_2204) node _T_2206 = and(_T_2205, asSInt(UInt<27>(0h4000000))) node _T_2207 = asSInt(_T_2206) node _T_2208 = eq(_T_2207, asSInt(UInt<1>(0h0))) node _T_2209 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2210 = cvt(_T_2209) node _T_2211 = and(_T_2210, asSInt(UInt<13>(0h1000))) node _T_2212 = asSInt(_T_2211) node _T_2213 = eq(_T_2212, asSInt(UInt<1>(0h0))) node _T_2214 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2215 = cvt(_T_2214) node _T_2216 = and(_T_2215, asSInt(UInt<29>(0h10000000))) node _T_2217 = asSInt(_T_2216) node _T_2218 = eq(_T_2217, asSInt(UInt<1>(0h0))) node _T_2219 = or(_T_2173, _T_2178) node _T_2220 = or(_T_2219, _T_2183) node _T_2221 = or(_T_2220, _T_2188) node _T_2222 = or(_T_2221, _T_2193) node _T_2223 = or(_T_2222, _T_2198) node _T_2224 = or(_T_2223, _T_2203) node _T_2225 = or(_T_2224, _T_2208) node _T_2226 = or(_T_2225, _T_2213) node _T_2227 = or(_T_2226, _T_2218) node _T_2228 = and(_T_2168, _T_2227) node _T_2229 = or(UInt<1>(0h0), _T_2228) node _T_2230 = and(_WIRE_9, _T_2229) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_151 node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : node _T_2236 = eq(source_ok_2, UInt<1>(0h0)) when _T_2236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2237 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_153 node _T_2241 = asUInt(reset) node _T_2242 = eq(_T_2241, UInt<1>(0h0)) when _T_2242 : node _T_2243 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2244 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(_T_2244, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2244, UInt<1>(0h1), "") : assert_155 node _T_2248 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2248 : node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(address_ok_1, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : node _T_2254 = eq(source_ok_2, UInt<1>(0h0)) when _T_2254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2255 = asUInt(reset) node _T_2256 = eq(_T_2255, UInt<1>(0h0)) when _T_2256 : node _T_2257 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2258 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(_T_2258, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2258, UInt<1>(0h1), "") : assert_159 node _T_2262 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_160 node _T_2266 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2266 : node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(address_ok_1, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(source_ok_2, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2273 = asUInt(reset) node _T_2274 = eq(_T_2273, UInt<1>(0h0)) when _T_2274 : node _T_2275 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2276 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2277 = asUInt(reset) node _T_2278 = eq(_T_2277, UInt<1>(0h0)) when _T_2278 : node _T_2279 = eq(_T_2276, UInt<1>(0h0)) when _T_2279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2276, UInt<1>(0h1), "") : assert_164 node _T_2280 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2280 : node _T_2281 = asUInt(reset) node _T_2282 = eq(_T_2281, UInt<1>(0h0)) when _T_2282 : node _T_2283 = eq(address_ok_1, UInt<1>(0h0)) when _T_2283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(source_ok_2, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2287 = asUInt(reset) node _T_2288 = eq(_T_2287, UInt<1>(0h0)) when _T_2288 : node _T_2289 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2290 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2291 = asUInt(reset) node _T_2292 = eq(_T_2291, UInt<1>(0h0)) when _T_2292 : node _T_2293 = eq(_T_2290, UInt<1>(0h0)) when _T_2293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2290, UInt<1>(0h1), "") : assert_168 node _T_2294 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2295 = asUInt(reset) node _T_2296 = eq(_T_2295, UInt<1>(0h0)) when _T_2296 : node _T_2297 = eq(_T_2294, UInt<1>(0h0)) when _T_2297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2294, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2298 = asUInt(reset) node _T_2299 = eq(_T_2298, UInt<1>(0h0)) when _T_2299 : node _T_2300 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2301 = eq(a_first, UInt<1>(0h0)) node _T_2302 = and(io.in.a.valid, _T_2301) when _T_2302 : node _T_2303 = eq(io.in.a.bits.opcode, opcode) node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(_T_2303, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2303, UInt<1>(0h1), "") : assert_171 node _T_2307 = eq(io.in.a.bits.param, param) node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : node _T_2310 = eq(_T_2307, UInt<1>(0h0)) when _T_2310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2307, UInt<1>(0h1), "") : assert_172 node _T_2311 = eq(io.in.a.bits.size, size) node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : node _T_2314 = eq(_T_2311, UInt<1>(0h0)) when _T_2314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2311, UInt<1>(0h1), "") : assert_173 node _T_2315 = eq(io.in.a.bits.source, source) node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : node _T_2318 = eq(_T_2315, UInt<1>(0h0)) when _T_2318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2315, UInt<1>(0h1), "") : assert_174 node _T_2319 = eq(io.in.a.bits.address, address) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_175 node _T_2323 = and(io.in.a.ready, io.in.a.valid) node _T_2324 = and(_T_2323, a_first) when _T_2324 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2325 = eq(d_first, UInt<1>(0h0)) node _T_2326 = and(io.in.d.valid, _T_2325) when _T_2326 : node _T_2327 = eq(io.in.d.bits.opcode, opcode_1) node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : node _T_2330 = eq(_T_2327, UInt<1>(0h0)) when _T_2330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2327, UInt<1>(0h1), "") : assert_176 node _T_2331 = eq(io.in.d.bits.param, param_1) node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(_T_2331, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2331, UInt<1>(0h1), "") : assert_177 node _T_2335 = eq(io.in.d.bits.size, size_1) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_178 node _T_2339 = eq(io.in.d.bits.source, source_1) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_179 node _T_2343 = eq(io.in.d.bits.sink, sink) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_180 node _T_2347 = eq(io.in.d.bits.denied, denied) node _T_2348 = asUInt(reset) node _T_2349 = eq(_T_2348, UInt<1>(0h0)) when _T_2349 : node _T_2350 = eq(_T_2347, UInt<1>(0h0)) when _T_2350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2347, UInt<1>(0h1), "") : assert_181 node _T_2351 = and(io.in.d.ready, io.in.d.valid) node _T_2352 = and(_T_2351, d_first) when _T_2352 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2353 = eq(b_first, UInt<1>(0h0)) node _T_2354 = and(io.in.b.valid, _T_2353) when _T_2354 : node _T_2355 = eq(io.in.b.bits.opcode, opcode_2) node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(_T_2355, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2355, UInt<1>(0h1), "") : assert_182 node _T_2359 = eq(io.in.b.bits.param, param_2) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(_T_2359, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2359, UInt<1>(0h1), "") : assert_183 node _T_2363 = eq(io.in.b.bits.size, size_2) node _T_2364 = asUInt(reset) node _T_2365 = eq(_T_2364, UInt<1>(0h0)) when _T_2365 : node _T_2366 = eq(_T_2363, UInt<1>(0h0)) when _T_2366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2363, UInt<1>(0h1), "") : assert_184 node _T_2367 = eq(io.in.b.bits.source, source_2) node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(_T_2367, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2367, UInt<1>(0h1), "") : assert_185 node _T_2371 = eq(io.in.b.bits.address, address_1) node _T_2372 = asUInt(reset) node _T_2373 = eq(_T_2372, UInt<1>(0h0)) when _T_2373 : node _T_2374 = eq(_T_2371, UInt<1>(0h0)) when _T_2374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2371, UInt<1>(0h1), "") : assert_186 node _T_2375 = and(io.in.b.ready, io.in.b.valid) node _T_2376 = and(_T_2375, b_first) when _T_2376 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2377 = eq(c_first, UInt<1>(0h0)) node _T_2378 = and(io.in.c.valid, _T_2377) when _T_2378 : node _T_2379 = eq(io.in.c.bits.opcode, opcode_3) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_187 node _T_2383 = eq(io.in.c.bits.param, param_3) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_188 node _T_2387 = eq(io.in.c.bits.size, size_3) node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(_T_2387, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2387, UInt<1>(0h1), "") : assert_189 node _T_2391 = eq(io.in.c.bits.source, source_3) node _T_2392 = asUInt(reset) node _T_2393 = eq(_T_2392, UInt<1>(0h0)) when _T_2393 : node _T_2394 = eq(_T_2391, UInt<1>(0h0)) when _T_2394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2391, UInt<1>(0h1), "") : assert_190 node _T_2395 = eq(io.in.c.bits.address, address_2) node _T_2396 = asUInt(reset) node _T_2397 = eq(_T_2396, UInt<1>(0h0)) when _T_2397 : node _T_2398 = eq(_T_2395, UInt<1>(0h0)) when _T_2398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2395, UInt<1>(0h1), "") : assert_191 node _T_2399 = and(io.in.c.ready, io.in.c.valid) node _T_2400 = and(_T_2399, c_first) when _T_2400 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes : UInt<32>, clock, reset, UInt<32>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<4> connect a_set, UInt<4>(0h0) wire a_set_wo_ready : UInt<4> connect a_set_wo_ready, UInt<4>(0h0) wire a_opcodes_set : UInt<16> connect a_opcodes_set, UInt<16>(0h0) wire a_sizes_set : UInt<32> connect a_sizes_set, UInt<32>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2401 = and(io.in.a.valid, a_first_1) node _T_2402 = and(_T_2401, UInt<1>(0h1)) when _T_2402 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2403 = and(io.in.a.ready, io.in.a.valid) node _T_2404 = and(_T_2403, a_first_1) node _T_2405 = and(_T_2404, UInt<1>(0h1)) when _T_2405 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2406 = dshr(inflight, io.in.a.bits.source) node _T_2407 = bits(_T_2406, 0, 0) node _T_2408 = eq(_T_2407, UInt<1>(0h0)) node _T_2409 = asUInt(reset) node _T_2410 = eq(_T_2409, UInt<1>(0h0)) when _T_2410 : node _T_2411 = eq(_T_2408, UInt<1>(0h0)) when _T_2411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2408, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<4> connect d_clr, UInt<4>(0h0) wire d_clr_wo_ready : UInt<4> connect d_clr_wo_ready, UInt<4>(0h0) wire d_opcodes_clr : UInt<16> connect d_opcodes_clr, UInt<16>(0h0) wire d_sizes_clr : UInt<32> connect d_sizes_clr, UInt<32>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2412 = and(io.in.d.valid, d_first_1) node _T_2413 = and(_T_2412, UInt<1>(0h1)) node _T_2414 = eq(d_release_ack, UInt<1>(0h0)) node _T_2415 = and(_T_2413, _T_2414) when _T_2415 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2416 = and(io.in.d.ready, io.in.d.valid) node _T_2417 = and(_T_2416, d_first_1) node _T_2418 = and(_T_2417, UInt<1>(0h1)) node _T_2419 = eq(d_release_ack, UInt<1>(0h0)) node _T_2420 = and(_T_2418, _T_2419) when _T_2420 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2421 = and(io.in.d.valid, d_first_1) node _T_2422 = and(_T_2421, UInt<1>(0h1)) node _T_2423 = eq(d_release_ack, UInt<1>(0h0)) node _T_2424 = and(_T_2422, _T_2423) when _T_2424 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2425 = dshr(inflight, io.in.d.bits.source) node _T_2426 = bits(_T_2425, 0, 0) node _T_2427 = or(_T_2426, same_cycle_resp) node _T_2428 = asUInt(reset) node _T_2429 = eq(_T_2428, UInt<1>(0h0)) when _T_2429 : node _T_2430 = eq(_T_2427, UInt<1>(0h0)) when _T_2430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2427, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2431 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2432 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2433 = or(_T_2431, _T_2432) node _T_2434 = asUInt(reset) node _T_2435 = eq(_T_2434, UInt<1>(0h0)) when _T_2435 : node _T_2436 = eq(_T_2433, UInt<1>(0h0)) when _T_2436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2433, UInt<1>(0h1), "") : assert_194 node _T_2437 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2438 = asUInt(reset) node _T_2439 = eq(_T_2438, UInt<1>(0h0)) when _T_2439 : node _T_2440 = eq(_T_2437, UInt<1>(0h0)) when _T_2440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2437, UInt<1>(0h1), "") : assert_195 else : node _T_2441 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2442 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2443 = or(_T_2441, _T_2442) node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(_T_2443, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2443, UInt<1>(0h1), "") : assert_196 node _T_2447 = eq(io.in.d.bits.size, a_size_lookup) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_197 node _T_2451 = and(io.in.d.valid, d_first_1) node _T_2452 = and(_T_2451, a_first_1) node _T_2453 = and(_T_2452, io.in.a.valid) node _T_2454 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2455 = and(_T_2453, _T_2454) node _T_2456 = eq(d_release_ack, UInt<1>(0h0)) node _T_2457 = and(_T_2455, _T_2456) when _T_2457 : node _T_2458 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2459 = or(_T_2458, io.in.a.ready) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_198 node _T_2463 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2464 = orr(a_set_wo_ready) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) node _T_2466 = or(_T_2463, _T_2465) node _T_2467 = asUInt(reset) node _T_2468 = eq(_T_2467, UInt<1>(0h0)) when _T_2468 : node _T_2469 = eq(_T_2466, UInt<1>(0h0)) when _T_2469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2466, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_84 node _T_2470 = orr(inflight) node _T_2471 = eq(_T_2470, UInt<1>(0h0)) node _T_2472 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2473 = or(_T_2471, _T_2472) node _T_2474 = lt(watchdog, plusarg_reader.out) node _T_2475 = or(_T_2473, _T_2474) node _T_2476 = asUInt(reset) node _T_2477 = eq(_T_2476, UInt<1>(0h0)) when _T_2477 : node _T_2478 = eq(_T_2475, UInt<1>(0h0)) when _T_2478 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2475, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2479 = and(io.in.a.ready, io.in.a.valid) node _T_2480 = and(io.in.d.ready, io.in.d.valid) node _T_2481 = or(_T_2479, _T_2480) when _T_2481 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes_1 : UInt<32>, clock, reset, UInt<32>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<4> connect c_set, UInt<4>(0h0) wire c_set_wo_ready : UInt<4> connect c_set_wo_ready, UInt<4>(0h0) wire c_opcodes_set : UInt<16> connect c_opcodes_set, UInt<16>(0h0) wire c_sizes_set : UInt<32> connect c_sizes_set, UInt<32>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2482 = and(io.in.c.valid, c_first_1) node _T_2483 = bits(io.in.c.bits.opcode, 2, 2) node _T_2484 = bits(io.in.c.bits.opcode, 1, 1) node _T_2485 = and(_T_2483, _T_2484) node _T_2486 = and(_T_2482, _T_2485) when _T_2486 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2487 = and(io.in.c.ready, io.in.c.valid) node _T_2488 = and(_T_2487, c_first_1) node _T_2489 = bits(io.in.c.bits.opcode, 2, 2) node _T_2490 = bits(io.in.c.bits.opcode, 1, 1) node _T_2491 = and(_T_2489, _T_2490) node _T_2492 = and(_T_2488, _T_2491) when _T_2492 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2493 = dshr(inflight_1, io.in.c.bits.source) node _T_2494 = bits(_T_2493, 0, 0) node _T_2495 = eq(_T_2494, UInt<1>(0h0)) node _T_2496 = asUInt(reset) node _T_2497 = eq(_T_2496, UInt<1>(0h0)) when _T_2497 : node _T_2498 = eq(_T_2495, UInt<1>(0h0)) when _T_2498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2495, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<4> connect d_clr_1, UInt<4>(0h0) wire d_clr_wo_ready_1 : UInt<4> connect d_clr_wo_ready_1, UInt<4>(0h0) wire d_opcodes_clr_1 : UInt<16> connect d_opcodes_clr_1, UInt<16>(0h0) wire d_sizes_clr_1 : UInt<32> connect d_sizes_clr_1, UInt<32>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2499 = and(io.in.d.valid, d_first_2) node _T_2500 = and(_T_2499, UInt<1>(0h1)) node _T_2501 = and(_T_2500, d_release_ack_1) when _T_2501 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2502 = and(io.in.d.ready, io.in.d.valid) node _T_2503 = and(_T_2502, d_first_2) node _T_2504 = and(_T_2503, UInt<1>(0h1)) node _T_2505 = and(_T_2504, d_release_ack_1) when _T_2505 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2506 = and(io.in.d.valid, d_first_2) node _T_2507 = and(_T_2506, UInt<1>(0h1)) node _T_2508 = and(_T_2507, d_release_ack_1) when _T_2508 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2509 = dshr(inflight_1, io.in.d.bits.source) node _T_2510 = bits(_T_2509, 0, 0) node _T_2511 = or(_T_2510, same_cycle_resp_1) node _T_2512 = asUInt(reset) node _T_2513 = eq(_T_2512, UInt<1>(0h0)) when _T_2513 : node _T_2514 = eq(_T_2511, UInt<1>(0h0)) when _T_2514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2511, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2515 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2516 = asUInt(reset) node _T_2517 = eq(_T_2516, UInt<1>(0h0)) when _T_2517 : node _T_2518 = eq(_T_2515, UInt<1>(0h0)) when _T_2518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2515, UInt<1>(0h1), "") : assert_203 else : node _T_2519 = eq(io.in.d.bits.size, c_size_lookup) node _T_2520 = asUInt(reset) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) when _T_2521 : node _T_2522 = eq(_T_2519, UInt<1>(0h0)) when _T_2522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2519, UInt<1>(0h1), "") : assert_204 node _T_2523 = and(io.in.d.valid, d_first_2) node _T_2524 = and(_T_2523, c_first_1) node _T_2525 = and(_T_2524, io.in.c.valid) node _T_2526 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2527 = and(_T_2525, _T_2526) node _T_2528 = and(_T_2527, d_release_ack_1) node _T_2529 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2530 = and(_T_2528, _T_2529) when _T_2530 : node _T_2531 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2532 = or(_T_2531, io.in.c.ready) node _T_2533 = asUInt(reset) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) when _T_2534 : node _T_2535 = eq(_T_2532, UInt<1>(0h0)) when _T_2535 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2532, UInt<1>(0h1), "") : assert_205 node _T_2536 = orr(c_set_wo_ready) when _T_2536 : node _T_2537 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_85 node _T_2541 = orr(inflight_1) node _T_2542 = eq(_T_2541, UInt<1>(0h0)) node _T_2543 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2544 = or(_T_2542, _T_2543) node _T_2545 = lt(watchdog_1, plusarg_reader_1.out) node _T_2546 = or(_T_2544, _T_2545) node _T_2547 = asUInt(reset) node _T_2548 = eq(_T_2547, UInt<1>(0h0)) when _T_2548 : node _T_2549 = eq(_T_2546, UInt<1>(0h0)) when _T_2549 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2546, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2550 = and(io.in.c.ready, io.in.c.valid) node _T_2551 = and(io.in.d.ready, io.in.d.valid) node _T_2552 = or(_T_2550, _T_2551) when _T_2552 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2553 = and(io.in.d.ready, io.in.d.valid) node _T_2554 = and(_T_2553, d_first_3) node _T_2555 = bits(io.in.d.bits.opcode, 2, 2) node _T_2556 = bits(io.in.d.bits.opcode, 1, 1) node _T_2557 = eq(_T_2556, UInt<1>(0h0)) node _T_2558 = and(_T_2555, _T_2557) node _T_2559 = and(_T_2554, _T_2558) when _T_2559 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2560 = dshr(inflight_2, io.in.d.bits.sink) node _T_2561 = bits(_T_2560, 0, 0) node _T_2562 = eq(_T_2561, UInt<1>(0h0)) node _T_2563 = asUInt(reset) node _T_2564 = eq(_T_2563, UInt<1>(0h0)) when _T_2564 : node _T_2565 = eq(_T_2562, UInt<1>(0h0)) when _T_2565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2562, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2566 = and(io.in.e.ready, io.in.e.valid) node _T_2567 = and(_T_2566, UInt<1>(0h1)) node _T_2568 = and(_T_2567, UInt<1>(0h1)) when _T_2568 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2569 = or(d_set, inflight_2) node _T_2570 = dshr(_T_2569, io.in.e.bits.sink) node _T_2571 = bits(_T_2570, 0, 0) node _T_2572 = asUInt(reset) node _T_2573 = eq(_T_2572, UInt<1>(0h0)) when _T_2573 : node _T_2574 = eq(_T_2571, UInt<1>(0h0)) when _T_2574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2571, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_86 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_87 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_42( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_7 = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T_7 = 1'h0; // @[Mux.scala:30:73] wire _source_ok_T_14 = 1'h0; // @[Parameters.scala:54:10] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = &io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_11 = source_ok_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_12 = _source_ok_T_11; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire _source_ok_T_13 = &io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_13; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [1:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_6 = &io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_4 = legal_source_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_4; // @[Parameters.scala:56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [1:0] _legal_source_T_8 = {2{_legal_source_WIRE_1}}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_9 = _legal_source_T_8; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_9; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [1:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = source_ok_uncommonBits_2 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_19 = _source_ok_T_18; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_19; // @[Parameters.scala:1138:31] wire _source_ok_T_20 = &io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_20; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_13 = _uncommonBits_T_13; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17; // @[Parameters.scala:52:{29,56}] wire _T_2479 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2479; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2479; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2553 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2553; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2550 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2550; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2550; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [3:0] inflight; // @[Monitor.scala:614:27] reg [15:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [31:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] a_set; // @[Monitor.scala:626:34] wire [3:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [15:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [31:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [31:0] _a_size_lookup_T_6 = {24'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [31:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = {2'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_22 = 4'h1 << _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_2405 = _T_2479 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2405 ? _a_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2405 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2405 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2405 ? _a_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2405 ? _a_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [3:0] d_clr; // @[Monitor.scala:664:34] wire [3:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [15:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [31:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2451 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_24 = {2'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_25 = 4'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2451 & ~d_release_ack ? _d_clr_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_2420 = _T_2553 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2420 ? _d_clr_T : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2420 ? _d_opcodes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2420 ? _d_sizes_clr_T_5[31:0] : 32'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [3:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [15:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [31:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [3:0] inflight_1; // @[Monitor.scala:726:35] reg [15:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [31:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_set; // @[Monitor.scala:738:34] wire [3:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [15:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [31:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = _c_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [31:0] _c_size_lookup_T_6 = {24'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [31:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_26 = {2'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_27 = 4'h1 << _GEN_26; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_2492 = _T_2550 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2492 ? _c_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2492 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2492 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2492 ? _c_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2492 ? _c_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [3:0] d_clr_1; // @[Monitor.scala:774:34] wire [3:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [15:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [31:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2523 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2523 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 4'h0; // @[OneHot.scala:58:35] wire _T_2505 = _T_2553 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2505 ? _d_clr_T_1 : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2505 ? _d_opcodes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2505 ? _d_sizes_clr_T_11[31:0] : 32'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [3:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [3:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [15:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [15:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [15:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [31:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [31:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2559 = _T_2553 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_28 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_28; // @[OneHot.scala:58:35] assign d_set = _T_2559 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2568 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_29 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_29; // @[OneHot.scala:58:35] assign e_clr = _T_2568 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_34 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_34( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module L2MemHelperLatencyInjection_14 : input clock : Clock input reset : Reset output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} output io : { flip userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip latency_inject_cycles : UInt<64>, flip sfence : UInt<1>, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip status : { valid : UInt<1>, bits : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect auto.master_out, masterNodeOut wire request_input : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}} connect request_input, io.userif.req wire response_output : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}} connect io.userif.resp, response_output reg status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock when io.status.valid : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "[raw_block_reader] setting status.dprv to: %x compare %x\n", io.status.bits.dprv, UInt<2>(0h3)) : printf_1 connect status, io.status.bits inst tlb of DTLB_16 connect tlb.clock, clock connect tlb.reset, reset connect tlb.io.req.valid, request_input.valid connect tlb.io.req.bits.vaddr, request_input.bits.addr connect tlb.io.req.bits.size, request_input.bits.size connect tlb.io.req.bits.cmd, request_input.bits.cmd connect tlb.io.req.bits.passthrough, UInt<1>(0h0) node _tlb_ready_T = eq(tlb.io.resp.miss, UInt<1>(0h0)) node tlb_ready = and(tlb.io.req.ready, _tlb_ready_T) invalidate tlb.io.req.bits.prv invalidate tlb.io.req.bits.v invalidate tlb.io.sfence.bits.hv invalidate tlb.io.sfence.bits.hg connect tlb.io.ptw.customCSRs, io.ptw.customCSRs connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] connect tlb.io.ptw.gstatus, io.ptw.gstatus connect tlb.io.ptw.hstatus, io.ptw.hstatus connect tlb.io.ptw.status, io.ptw.status connect tlb.io.ptw.vsatp, io.ptw.vsatp connect tlb.io.ptw.hgatp, io.ptw.hgatp connect tlb.io.ptw.ptbr, io.ptw.ptbr connect tlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, tlb.io.ptw.req.bits connect io.ptw.req.valid, tlb.io.ptw.req.valid connect tlb.io.ptw.req.ready, io.ptw.req.ready connect tlb.io.ptw.status.uie, status.uie connect tlb.io.ptw.status.sie, status.sie connect tlb.io.ptw.status.hie, status.hie connect tlb.io.ptw.status.mie, status.mie connect tlb.io.ptw.status.upie, status.upie connect tlb.io.ptw.status.spie, status.spie connect tlb.io.ptw.status.ube, status.ube connect tlb.io.ptw.status.mpie, status.mpie connect tlb.io.ptw.status.spp, status.spp connect tlb.io.ptw.status.vs, status.vs connect tlb.io.ptw.status.mpp, status.mpp connect tlb.io.ptw.status.fs, status.fs connect tlb.io.ptw.status.xs, status.xs connect tlb.io.ptw.status.mprv, status.mprv connect tlb.io.ptw.status.sum, status.sum connect tlb.io.ptw.status.mxr, status.mxr connect tlb.io.ptw.status.tvm, status.tvm connect tlb.io.ptw.status.tw, status.tw connect tlb.io.ptw.status.tsr, status.tsr connect tlb.io.ptw.status.zero1, status.zero1 connect tlb.io.ptw.status.sd_rv32, status.sd_rv32 connect tlb.io.ptw.status.uxl, status.uxl connect tlb.io.ptw.status.sxl, status.sxl connect tlb.io.ptw.status.sbe, status.sbe connect tlb.io.ptw.status.mbe, status.mbe connect tlb.io.ptw.status.gva, status.gva connect tlb.io.ptw.status.mpv, status.mpv connect tlb.io.ptw.status.zero2, status.zero2 connect tlb.io.ptw.status.sd, status.sd connect tlb.io.ptw.status.v, status.v connect tlb.io.ptw.status.prv, status.prv connect tlb.io.ptw.status.dv, status.dv connect tlb.io.ptw.status.dprv, status.dprv connect tlb.io.ptw.status.isa, status.isa connect tlb.io.ptw.status.wfi, status.wfi connect tlb.io.ptw.status.cease, status.cease connect tlb.io.ptw.status.debug, status.debug connect tlb.io.sfence.valid, io.sfence connect tlb.io.sfence.bits.rs1, UInt<1>(0h0) connect tlb.io.sfence.bits.rs2, UInt<1>(0h0) connect tlb.io.sfence.bits.addr, UInt<1>(0h0) connect tlb.io.sfence.bits.asid, UInt<1>(0h0) connect tlb.io.kill, UInt<1>(0h0) inst outstanding_req_addr of Queue128_L2InternalTracking_10 connect outstanding_req_addr.clock, clock connect outstanding_req_addr.reset, reset inst tags_for_issue_Q of Queue64_UInt5_10 connect tags_for_issue_Q.clock, clock connect tags_for_issue_Q.reset, reset connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h0) invalidate tags_for_issue_Q.io.enq.bits regreset tags_init_reg : UInt<6>, clock, reset, UInt<6>(0h0) node _T_4 = neq(tags_init_reg, UInt<6>(0h20)) when _T_4 : connect tags_for_issue_Q.io.enq.bits, tags_init_reg connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) when tags_for_issue_Q.io.enq.ready : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "[raw_block_reader] tags_for_issue_Q init with value %d\n", tags_for_issue_Q.io.enq.bits) : printf_3 node _tags_init_reg_T = add(tags_init_reg, UInt<1>(0h1)) node _tags_init_reg_T_1 = tail(_tags_init_reg_T, 1) connect tags_init_reg, _tags_init_reg_T_1 node _addr_mask_check_T = dshl(UInt<64>(0h1), request_input.bits.size) node _addr_mask_check_T_1 = sub(_addr_mask_check_T, UInt<1>(0h1)) node addr_mask_check = tail(_addr_mask_check_T_1, 1) node _assertcheck_T = eq(request_input.valid, UInt<1>(0h0)) node _assertcheck_T_1 = and(request_input.bits.addr, addr_mask_check) node _assertcheck_T_2 = eq(_assertcheck_T_1, UInt<1>(0h0)) node _assertcheck_T_3 = or(_assertcheck_T, _assertcheck_T_2) reg assertcheck : UInt<1>, clock connect assertcheck, _assertcheck_T_3 node _T_9 = eq(assertcheck, UInt<1>(0h0)) when _T_9 : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: access addr must be aligned to write width\n") : printf_5 node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(assertcheck, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed: [raw_block_reader] L2IF: access addr must be aligned to write width\n\n at L2MemHelperLatencyInjection.scala:114 assert(assertcheck,\n") : printf_6 assert(clock, assertcheck, UInt<1>(0h1), "") : assert regreset global_memop_accepted : UInt<64>, clock, reset, UInt<64>(0h0) node _T_17 = and(io.userif.req.ready, io.userif.req.valid) when _T_17 : node _global_memop_accepted_T = add(global_memop_accepted, UInt<1>(0h1)) node _global_memop_accepted_T_1 = tail(_global_memop_accepted_T, 1) connect global_memop_accepted, _global_memop_accepted_T_1 regreset global_memop_sent : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_ackd : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_resp_to_user : UInt<64>, clock, reset, UInt<64>(0h0) node _io_userif_no_memops_inflight_T = eq(global_memop_accepted, global_memop_ackd) connect io.userif.no_memops_inflight, _io_userif_no_memops_inflight_T node _free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _free_outstanding_op_slots_T_1 = tail(_free_outstanding_op_slots_T, 1) node free_outstanding_op_slots = lt(_free_outstanding_op_slots_T_1, UInt<6>(0h20)) node _assert_free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _assert_free_outstanding_op_slots_T_1 = tail(_assert_free_outstanding_op_slots_T, 1) node assert_free_outstanding_op_slots = leq(_assert_free_outstanding_op_slots_T_1, UInt<6>(0h20)) node _T_18 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_18 : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_7 node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: Too many outstanding requests for tag count.\n") : printf_8 node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed: [raw_block_reader] L2IF: Too many outstanding requests for tag count.\n\n at L2MemHelperLatencyInjection.scala:136 assert(assert_free_outstanding_op_slots,\n") : printf_9 assert(clock, assert_free_outstanding_op_slots, UInt<1>(0h1), "") : assert_1 node _T_26 = and(request_input.ready, request_input.valid) when _T_26 : node _global_memop_sent_T = add(global_memop_sent, UInt<1>(0h1)) node _global_memop_sent_T_1 = tail(_global_memop_sent_T, 1) connect global_memop_sent, _global_memop_sent_T_1 regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0) node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1)) node _cur_cycle_T_1 = tail(_cur_cycle_T, 1) connect cur_cycle, _cur_cycle_T_1 inst request_latency_injection_q of LatencyInjectionQueue_28 connect request_latency_injection_q.clock, clock connect request_latency_injection_q.reset, reset connect request_latency_injection_q.io.latency_cycles, io.latency_inject_cycles invalidate request_latency_injection_q.io.enq.bits.corrupt invalidate request_latency_injection_q.io.enq.bits.data invalidate request_latency_injection_q.io.enq.bits.mask invalidate request_latency_injection_q.io.enq.bits.address invalidate request_latency_injection_q.io.enq.bits.source invalidate request_latency_injection_q.io.enq.bits.size invalidate request_latency_injection_q.io.enq.bits.param invalidate request_latency_injection_q.io.enq.bits.opcode node _T_27 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_27 : node _legal_T = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_1 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_2 = and(_legal_T, _legal_T_1) node _legal_T_3 = or(UInt<1>(0h0), _legal_T_2) node _legal_T_4 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_5 = cvt(_legal_T_4) node _legal_T_6 = and(_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _legal_T_7 = asSInt(_legal_T_6) node _legal_T_8 = eq(_legal_T_7, asSInt(UInt<1>(0h0))) node _legal_T_9 = and(_legal_T_3, _legal_T_8) node _legal_T_10 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_11 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_12 = and(_legal_T_10, _legal_T_11) node _legal_T_13 = or(UInt<1>(0h0), _legal_T_12) node _legal_T_14 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_15 = cvt(_legal_T_14) node _legal_T_16 = and(_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _legal_T_17 = asSInt(_legal_T_16) node _legal_T_18 = eq(_legal_T_17, asSInt(UInt<1>(0h0))) node _legal_T_19 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_20 = cvt(_legal_T_19) node _legal_T_21 = and(_legal_T_20, asSInt(UInt<33>(0h98013000))) node _legal_T_22 = asSInt(_legal_T_21) node _legal_T_23 = eq(_legal_T_22, asSInt(UInt<1>(0h0))) node _legal_T_24 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_25 = cvt(_legal_T_24) node _legal_T_26 = and(_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _legal_T_27 = asSInt(_legal_T_26) node _legal_T_28 = eq(_legal_T_27, asSInt(UInt<1>(0h0))) node _legal_T_29 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_30 = cvt(_legal_T_29) node _legal_T_31 = and(_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _legal_T_32 = asSInt(_legal_T_31) node _legal_T_33 = eq(_legal_T_32, asSInt(UInt<1>(0h0))) node _legal_T_34 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_35 = cvt(_legal_T_34) node _legal_T_36 = and(_legal_T_35, asSInt(UInt<33>(0h98000000))) node _legal_T_37 = asSInt(_legal_T_36) node _legal_T_38 = eq(_legal_T_37, asSInt(UInt<1>(0h0))) node _legal_T_39 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_40 = cvt(_legal_T_39) node _legal_T_41 = and(_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _legal_T_42 = asSInt(_legal_T_41) node _legal_T_43 = eq(_legal_T_42, asSInt(UInt<1>(0h0))) node _legal_T_44 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_45 = cvt(_legal_T_44) node _legal_T_46 = and(_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _legal_T_47 = asSInt(_legal_T_46) node _legal_T_48 = eq(_legal_T_47, asSInt(UInt<1>(0h0))) node _legal_T_49 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_50 = cvt(_legal_T_49) node _legal_T_51 = and(_legal_T_50, asSInt(UInt<33>(0h90000000))) node _legal_T_52 = asSInt(_legal_T_51) node _legal_T_53 = eq(_legal_T_52, asSInt(UInt<1>(0h0))) node _legal_T_54 = or(_legal_T_18, _legal_T_23) node _legal_T_55 = or(_legal_T_54, _legal_T_28) node _legal_T_56 = or(_legal_T_55, _legal_T_33) node _legal_T_57 = or(_legal_T_56, _legal_T_38) node _legal_T_58 = or(_legal_T_57, _legal_T_43) node _legal_T_59 = or(_legal_T_58, _legal_T_48) node _legal_T_60 = or(_legal_T_59, _legal_T_53) node _legal_T_61 = and(_legal_T_13, _legal_T_60) node _legal_T_62 = or(UInt<1>(0h0), _legal_T_9) node legal = or(_legal_T_62, _legal_T_61) wire bundle : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle.opcode, UInt<3>(0h4) connect bundle.param, UInt<1>(0h0) connect bundle.size, request_input.bits.size connect bundle.source, tags_for_issue_Q.io.deq.bits connect bundle.address, tlb.io.resp.paddr node _a_mask_sizeOH_T = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T = pad(_a_mask_sizeOH_T, 3) node a_mask_sizeOH_shiftAmount = bits(_a_mask_sizeOH_shiftAmount_T, 2, 0) node _a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount) node _a_mask_sizeOH_T_2 = bits(_a_mask_sizeOH_T_1, 4, 0) node a_mask_sizeOH = or(_a_mask_sizeOH_T_2, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size = bits(a_mask_sizeOH, 4, 4) node a_mask_sub_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_0_2) node a_mask_sub_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit) node _a_mask_sub_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_1_2) node a_mask_sub_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_size = bits(a_mask_sizeOH, 3, 3) node a_mask_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_0_2) node a_mask_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_1_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_1_2) node a_mask_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_2_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_2_2) node a_mask_sub_sub_sub_2_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_3_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_3_2) node a_mask_sub_sub_sub_3_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_3) node a_mask_sub_sub_size = bits(a_mask_sizeOH, 2, 2) node a_mask_sub_sub_bit = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit = eq(a_mask_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_0_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T = and(a_mask_sub_sub_size, a_mask_sub_sub_0_2) node a_mask_sub_sub_0_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T) node a_mask_sub_sub_1_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_1 = and(a_mask_sub_sub_size, a_mask_sub_sub_1_2) node a_mask_sub_sub_1_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T_1) node a_mask_sub_sub_2_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_2 = and(a_mask_sub_sub_size, a_mask_sub_sub_2_2) node a_mask_sub_sub_2_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_2) node a_mask_sub_sub_3_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_3 = and(a_mask_sub_sub_size, a_mask_sub_sub_3_2) node a_mask_sub_sub_3_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_3) node a_mask_sub_sub_4_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_4 = and(a_mask_sub_sub_size, a_mask_sub_sub_4_2) node a_mask_sub_sub_4_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_4) node a_mask_sub_sub_5_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_5 = and(a_mask_sub_sub_size, a_mask_sub_sub_5_2) node a_mask_sub_sub_5_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_5) node a_mask_sub_sub_6_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_6 = and(a_mask_sub_sub_size, a_mask_sub_sub_6_2) node a_mask_sub_sub_6_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_6) node a_mask_sub_sub_7_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_7 = and(a_mask_sub_sub_size, a_mask_sub_sub_7_2) node a_mask_sub_sub_7_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_7) node a_mask_sub_size = bits(a_mask_sizeOH, 1, 1) node a_mask_sub_bit = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit = eq(a_mask_sub_bit, UInt<1>(0h0)) node a_mask_sub_0_2 = and(a_mask_sub_sub_0_2, a_mask_sub_nbit) node _a_mask_sub_acc_T = and(a_mask_sub_size, a_mask_sub_0_2) node a_mask_sub_0_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T) node a_mask_sub_1_2 = and(a_mask_sub_sub_0_2, a_mask_sub_bit) node _a_mask_sub_acc_T_1 = and(a_mask_sub_size, a_mask_sub_1_2) node a_mask_sub_1_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T_1) node a_mask_sub_2_2 = and(a_mask_sub_sub_1_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_2 = and(a_mask_sub_size, a_mask_sub_2_2) node a_mask_sub_2_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_2) node a_mask_sub_3_2 = and(a_mask_sub_sub_1_2, a_mask_sub_bit) node _a_mask_sub_acc_T_3 = and(a_mask_sub_size, a_mask_sub_3_2) node a_mask_sub_3_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_3) node a_mask_sub_4_2 = and(a_mask_sub_sub_2_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_4 = and(a_mask_sub_size, a_mask_sub_4_2) node a_mask_sub_4_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_4) node a_mask_sub_5_2 = and(a_mask_sub_sub_2_2, a_mask_sub_bit) node _a_mask_sub_acc_T_5 = and(a_mask_sub_size, a_mask_sub_5_2) node a_mask_sub_5_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_5) node a_mask_sub_6_2 = and(a_mask_sub_sub_3_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_6 = and(a_mask_sub_size, a_mask_sub_6_2) node a_mask_sub_6_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_6) node a_mask_sub_7_2 = and(a_mask_sub_sub_3_2, a_mask_sub_bit) node _a_mask_sub_acc_T_7 = and(a_mask_sub_size, a_mask_sub_7_2) node a_mask_sub_7_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_7) node a_mask_sub_8_2 = and(a_mask_sub_sub_4_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_8 = and(a_mask_sub_size, a_mask_sub_8_2) node a_mask_sub_8_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_8) node a_mask_sub_9_2 = and(a_mask_sub_sub_4_2, a_mask_sub_bit) node _a_mask_sub_acc_T_9 = and(a_mask_sub_size, a_mask_sub_9_2) node a_mask_sub_9_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_9) node a_mask_sub_10_2 = and(a_mask_sub_sub_5_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_10 = and(a_mask_sub_size, a_mask_sub_10_2) node a_mask_sub_10_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_10) node a_mask_sub_11_2 = and(a_mask_sub_sub_5_2, a_mask_sub_bit) node _a_mask_sub_acc_T_11 = and(a_mask_sub_size, a_mask_sub_11_2) node a_mask_sub_11_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_11) node a_mask_sub_12_2 = and(a_mask_sub_sub_6_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_12 = and(a_mask_sub_size, a_mask_sub_12_2) node a_mask_sub_12_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_12) node a_mask_sub_13_2 = and(a_mask_sub_sub_6_2, a_mask_sub_bit) node _a_mask_sub_acc_T_13 = and(a_mask_sub_size, a_mask_sub_13_2) node a_mask_sub_13_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_13) node a_mask_sub_14_2 = and(a_mask_sub_sub_7_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_14 = and(a_mask_sub_size, a_mask_sub_14_2) node a_mask_sub_14_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_14) node a_mask_sub_15_2 = and(a_mask_sub_sub_7_2, a_mask_sub_bit) node _a_mask_sub_acc_T_15 = and(a_mask_sub_size, a_mask_sub_15_2) node a_mask_sub_15_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_15) node a_mask_size = bits(a_mask_sizeOH, 0, 0) node a_mask_bit = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit = eq(a_mask_bit, UInt<1>(0h0)) node a_mask_eq = and(a_mask_sub_0_2, a_mask_nbit) node _a_mask_acc_T = and(a_mask_size, a_mask_eq) node a_mask_acc = or(a_mask_sub_0_1, _a_mask_acc_T) node a_mask_eq_1 = and(a_mask_sub_0_2, a_mask_bit) node _a_mask_acc_T_1 = and(a_mask_size, a_mask_eq_1) node a_mask_acc_1 = or(a_mask_sub_0_1, _a_mask_acc_T_1) node a_mask_eq_2 = and(a_mask_sub_1_2, a_mask_nbit) node _a_mask_acc_T_2 = and(a_mask_size, a_mask_eq_2) node a_mask_acc_2 = or(a_mask_sub_1_1, _a_mask_acc_T_2) node a_mask_eq_3 = and(a_mask_sub_1_2, a_mask_bit) node _a_mask_acc_T_3 = and(a_mask_size, a_mask_eq_3) node a_mask_acc_3 = or(a_mask_sub_1_1, _a_mask_acc_T_3) node a_mask_eq_4 = and(a_mask_sub_2_2, a_mask_nbit) node _a_mask_acc_T_4 = and(a_mask_size, a_mask_eq_4) node a_mask_acc_4 = or(a_mask_sub_2_1, _a_mask_acc_T_4) node a_mask_eq_5 = and(a_mask_sub_2_2, a_mask_bit) node _a_mask_acc_T_5 = and(a_mask_size, a_mask_eq_5) node a_mask_acc_5 = or(a_mask_sub_2_1, _a_mask_acc_T_5) node a_mask_eq_6 = and(a_mask_sub_3_2, a_mask_nbit) node _a_mask_acc_T_6 = and(a_mask_size, a_mask_eq_6) node a_mask_acc_6 = or(a_mask_sub_3_1, _a_mask_acc_T_6) node a_mask_eq_7 = and(a_mask_sub_3_2, a_mask_bit) node _a_mask_acc_T_7 = and(a_mask_size, a_mask_eq_7) node a_mask_acc_7 = or(a_mask_sub_3_1, _a_mask_acc_T_7) node a_mask_eq_8 = and(a_mask_sub_4_2, a_mask_nbit) node _a_mask_acc_T_8 = and(a_mask_size, a_mask_eq_8) node a_mask_acc_8 = or(a_mask_sub_4_1, _a_mask_acc_T_8) node a_mask_eq_9 = and(a_mask_sub_4_2, a_mask_bit) node _a_mask_acc_T_9 = and(a_mask_size, a_mask_eq_9) node a_mask_acc_9 = or(a_mask_sub_4_1, _a_mask_acc_T_9) node a_mask_eq_10 = and(a_mask_sub_5_2, a_mask_nbit) node _a_mask_acc_T_10 = and(a_mask_size, a_mask_eq_10) node a_mask_acc_10 = or(a_mask_sub_5_1, _a_mask_acc_T_10) node a_mask_eq_11 = and(a_mask_sub_5_2, a_mask_bit) node _a_mask_acc_T_11 = and(a_mask_size, a_mask_eq_11) node a_mask_acc_11 = or(a_mask_sub_5_1, _a_mask_acc_T_11) node a_mask_eq_12 = and(a_mask_sub_6_2, a_mask_nbit) node _a_mask_acc_T_12 = and(a_mask_size, a_mask_eq_12) node a_mask_acc_12 = or(a_mask_sub_6_1, _a_mask_acc_T_12) node a_mask_eq_13 = and(a_mask_sub_6_2, a_mask_bit) node _a_mask_acc_T_13 = and(a_mask_size, a_mask_eq_13) node a_mask_acc_13 = or(a_mask_sub_6_1, _a_mask_acc_T_13) node a_mask_eq_14 = and(a_mask_sub_7_2, a_mask_nbit) node _a_mask_acc_T_14 = and(a_mask_size, a_mask_eq_14) node a_mask_acc_14 = or(a_mask_sub_7_1, _a_mask_acc_T_14) node a_mask_eq_15 = and(a_mask_sub_7_2, a_mask_bit) node _a_mask_acc_T_15 = and(a_mask_size, a_mask_eq_15) node a_mask_acc_15 = or(a_mask_sub_7_1, _a_mask_acc_T_15) node a_mask_eq_16 = and(a_mask_sub_8_2, a_mask_nbit) node _a_mask_acc_T_16 = and(a_mask_size, a_mask_eq_16) node a_mask_acc_16 = or(a_mask_sub_8_1, _a_mask_acc_T_16) node a_mask_eq_17 = and(a_mask_sub_8_2, a_mask_bit) node _a_mask_acc_T_17 = and(a_mask_size, a_mask_eq_17) node a_mask_acc_17 = or(a_mask_sub_8_1, _a_mask_acc_T_17) node a_mask_eq_18 = and(a_mask_sub_9_2, a_mask_nbit) node _a_mask_acc_T_18 = and(a_mask_size, a_mask_eq_18) node a_mask_acc_18 = or(a_mask_sub_9_1, _a_mask_acc_T_18) node a_mask_eq_19 = and(a_mask_sub_9_2, a_mask_bit) node _a_mask_acc_T_19 = and(a_mask_size, a_mask_eq_19) node a_mask_acc_19 = or(a_mask_sub_9_1, _a_mask_acc_T_19) node a_mask_eq_20 = and(a_mask_sub_10_2, a_mask_nbit) node _a_mask_acc_T_20 = and(a_mask_size, a_mask_eq_20) node a_mask_acc_20 = or(a_mask_sub_10_1, _a_mask_acc_T_20) node a_mask_eq_21 = and(a_mask_sub_10_2, a_mask_bit) node _a_mask_acc_T_21 = and(a_mask_size, a_mask_eq_21) node a_mask_acc_21 = or(a_mask_sub_10_1, _a_mask_acc_T_21) node a_mask_eq_22 = and(a_mask_sub_11_2, a_mask_nbit) node _a_mask_acc_T_22 = and(a_mask_size, a_mask_eq_22) node a_mask_acc_22 = or(a_mask_sub_11_1, _a_mask_acc_T_22) node a_mask_eq_23 = and(a_mask_sub_11_2, a_mask_bit) node _a_mask_acc_T_23 = and(a_mask_size, a_mask_eq_23) node a_mask_acc_23 = or(a_mask_sub_11_1, _a_mask_acc_T_23) node a_mask_eq_24 = and(a_mask_sub_12_2, a_mask_nbit) node _a_mask_acc_T_24 = and(a_mask_size, a_mask_eq_24) node a_mask_acc_24 = or(a_mask_sub_12_1, _a_mask_acc_T_24) node a_mask_eq_25 = and(a_mask_sub_12_2, a_mask_bit) node _a_mask_acc_T_25 = and(a_mask_size, a_mask_eq_25) node a_mask_acc_25 = or(a_mask_sub_12_1, _a_mask_acc_T_25) node a_mask_eq_26 = and(a_mask_sub_13_2, a_mask_nbit) node _a_mask_acc_T_26 = and(a_mask_size, a_mask_eq_26) node a_mask_acc_26 = or(a_mask_sub_13_1, _a_mask_acc_T_26) node a_mask_eq_27 = and(a_mask_sub_13_2, a_mask_bit) node _a_mask_acc_T_27 = and(a_mask_size, a_mask_eq_27) node a_mask_acc_27 = or(a_mask_sub_13_1, _a_mask_acc_T_27) node a_mask_eq_28 = and(a_mask_sub_14_2, a_mask_nbit) node _a_mask_acc_T_28 = and(a_mask_size, a_mask_eq_28) node a_mask_acc_28 = or(a_mask_sub_14_1, _a_mask_acc_T_28) node a_mask_eq_29 = and(a_mask_sub_14_2, a_mask_bit) node _a_mask_acc_T_29 = and(a_mask_size, a_mask_eq_29) node a_mask_acc_29 = or(a_mask_sub_14_1, _a_mask_acc_T_29) node a_mask_eq_30 = and(a_mask_sub_15_2, a_mask_nbit) node _a_mask_acc_T_30 = and(a_mask_size, a_mask_eq_30) node a_mask_acc_30 = or(a_mask_sub_15_1, _a_mask_acc_T_30) node a_mask_eq_31 = and(a_mask_sub_15_2, a_mask_bit) node _a_mask_acc_T_31 = and(a_mask_size, a_mask_eq_31) node a_mask_acc_31 = or(a_mask_sub_15_1, _a_mask_acc_T_31) node a_mask_lo_lo_lo_lo = cat(a_mask_acc_1, a_mask_acc) node a_mask_lo_lo_lo_hi = cat(a_mask_acc_3, a_mask_acc_2) node a_mask_lo_lo_lo = cat(a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo) node a_mask_lo_lo_hi_lo = cat(a_mask_acc_5, a_mask_acc_4) node a_mask_lo_lo_hi_hi = cat(a_mask_acc_7, a_mask_acc_6) node a_mask_lo_lo_hi = cat(a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo) node a_mask_lo_lo = cat(a_mask_lo_lo_hi, a_mask_lo_lo_lo) node a_mask_lo_hi_lo_lo = cat(a_mask_acc_9, a_mask_acc_8) node a_mask_lo_hi_lo_hi = cat(a_mask_acc_11, a_mask_acc_10) node a_mask_lo_hi_lo = cat(a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo) node a_mask_lo_hi_hi_lo = cat(a_mask_acc_13, a_mask_acc_12) node a_mask_lo_hi_hi_hi = cat(a_mask_acc_15, a_mask_acc_14) node a_mask_lo_hi_hi = cat(a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo) node a_mask_lo_hi = cat(a_mask_lo_hi_hi, a_mask_lo_hi_lo) node a_mask_lo = cat(a_mask_lo_hi, a_mask_lo_lo) node a_mask_hi_lo_lo_lo = cat(a_mask_acc_17, a_mask_acc_16) node a_mask_hi_lo_lo_hi = cat(a_mask_acc_19, a_mask_acc_18) node a_mask_hi_lo_lo = cat(a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo) node a_mask_hi_lo_hi_lo = cat(a_mask_acc_21, a_mask_acc_20) node a_mask_hi_lo_hi_hi = cat(a_mask_acc_23, a_mask_acc_22) node a_mask_hi_lo_hi = cat(a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo) node a_mask_hi_lo = cat(a_mask_hi_lo_hi, a_mask_hi_lo_lo) node a_mask_hi_hi_lo_lo = cat(a_mask_acc_25, a_mask_acc_24) node a_mask_hi_hi_lo_hi = cat(a_mask_acc_27, a_mask_acc_26) node a_mask_hi_hi_lo = cat(a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo) node a_mask_hi_hi_hi_lo = cat(a_mask_acc_29, a_mask_acc_28) node a_mask_hi_hi_hi_hi = cat(a_mask_acc_31, a_mask_acc_30) node a_mask_hi_hi_hi = cat(a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo) node a_mask_hi_hi = cat(a_mask_hi_hi_hi, a_mask_hi_hi_lo) node a_mask_hi = cat(a_mask_hi_hi, a_mask_hi_lo) node _a_mask_T = cat(a_mask_hi, a_mask_lo) connect bundle.mask, _a_mask_T invalidate bundle.data connect bundle.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle.data connect request_latency_injection_q.io.enq.bits.mask, bundle.mask connect request_latency_injection_q.io.enq.bits.address, bundle.address connect request_latency_injection_q.io.enq.bits.source, bundle.source connect request_latency_injection_q.io.enq.bits.size, bundle.size connect request_latency_injection_q.io.enq.bits.param, bundle.param connect request_latency_injection_q.io.enq.bits.opcode, bundle.opcode else : node _T_28 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_28 : node _T_29 = bits(request_input.bits.addr, 4, 0) node _T_30 = shl(_T_29, 3) node _T_31 = dshl(request_input.bits.data, _T_30) node _legal_T_63 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_64 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_65 = and(_legal_T_63, _legal_T_64) node _legal_T_66 = or(UInt<1>(0h0), _legal_T_65) node _legal_T_67 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_68 = cvt(_legal_T_67) node _legal_T_69 = and(_legal_T_68, asSInt(UInt<33>(0h9a113000))) node _legal_T_70 = asSInt(_legal_T_69) node _legal_T_71 = eq(_legal_T_70, asSInt(UInt<1>(0h0))) node _legal_T_72 = and(_legal_T_66, _legal_T_71) node _legal_T_73 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_74 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_75 = and(_legal_T_73, _legal_T_74) node _legal_T_76 = or(UInt<1>(0h0), _legal_T_75) node _legal_T_77 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_78 = cvt(_legal_T_77) node _legal_T_79 = and(_legal_T_78, asSInt(UInt<33>(0h9a112000))) node _legal_T_80 = asSInt(_legal_T_79) node _legal_T_81 = eq(_legal_T_80, asSInt(UInt<1>(0h0))) node _legal_T_82 = xor(tlb.io.resp.paddr, UInt<21>(0h100000)) node _legal_T_83 = cvt(_legal_T_82) node _legal_T_84 = and(_legal_T_83, asSInt(UInt<33>(0h9a103000))) node _legal_T_85 = asSInt(_legal_T_84) node _legal_T_86 = eq(_legal_T_85, asSInt(UInt<1>(0h0))) node _legal_T_87 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_88 = cvt(_legal_T_87) node _legal_T_89 = and(_legal_T_88, asSInt(UInt<33>(0h9a110000))) node _legal_T_90 = asSInt(_legal_T_89) node _legal_T_91 = eq(_legal_T_90, asSInt(UInt<1>(0h0))) node _legal_T_92 = xor(tlb.io.resp.paddr, UInt<26>(0h2010000)) node _legal_T_93 = cvt(_legal_T_92) node _legal_T_94 = and(_legal_T_93, asSInt(UInt<33>(0h9a113000))) node _legal_T_95 = asSInt(_legal_T_94) node _legal_T_96 = eq(_legal_T_95, asSInt(UInt<1>(0h0))) node _legal_T_97 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_98 = cvt(_legal_T_97) node _legal_T_99 = and(_legal_T_98, asSInt(UInt<33>(0h98000000))) node _legal_T_100 = asSInt(_legal_T_99) node _legal_T_101 = eq(_legal_T_100, asSInt(UInt<1>(0h0))) node _legal_T_102 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_103 = cvt(_legal_T_102) node _legal_T_104 = and(_legal_T_103, asSInt(UInt<33>(0h9a110000))) node _legal_T_105 = asSInt(_legal_T_104) node _legal_T_106 = eq(_legal_T_105, asSInt(UInt<1>(0h0))) node _legal_T_107 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_108 = cvt(_legal_T_107) node _legal_T_109 = and(_legal_T_108, asSInt(UInt<33>(0h9a113000))) node _legal_T_110 = asSInt(_legal_T_109) node _legal_T_111 = eq(_legal_T_110, asSInt(UInt<1>(0h0))) node _legal_T_112 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_113 = cvt(_legal_T_112) node _legal_T_114 = and(_legal_T_113, asSInt(UInt<33>(0h90000000))) node _legal_T_115 = asSInt(_legal_T_114) node _legal_T_116 = eq(_legal_T_115, asSInt(UInt<1>(0h0))) node _legal_T_117 = or(_legal_T_81, _legal_T_86) node _legal_T_118 = or(_legal_T_117, _legal_T_91) node _legal_T_119 = or(_legal_T_118, _legal_T_96) node _legal_T_120 = or(_legal_T_119, _legal_T_101) node _legal_T_121 = or(_legal_T_120, _legal_T_106) node _legal_T_122 = or(_legal_T_121, _legal_T_111) node _legal_T_123 = or(_legal_T_122, _legal_T_116) node _legal_T_124 = and(_legal_T_76, _legal_T_123) node _legal_T_125 = or(UInt<1>(0h0), UInt<1>(0h0)) node _legal_T_126 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_127 = cvt(_legal_T_126) node _legal_T_128 = and(_legal_T_127, asSInt(UInt<33>(0h9a110000))) node _legal_T_129 = asSInt(_legal_T_128) node _legal_T_130 = eq(_legal_T_129, asSInt(UInt<1>(0h0))) node _legal_T_131 = and(_legal_T_125, _legal_T_130) node _legal_T_132 = or(UInt<1>(0h0), _legal_T_72) node _legal_T_133 = or(_legal_T_132, _legal_T_124) node legal_1 = or(_legal_T_133, _legal_T_131) wire bundle_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle_1.opcode, UInt<1>(0h0) connect bundle_1.param, UInt<1>(0h0) connect bundle_1.size, request_input.bits.size connect bundle_1.source, tags_for_issue_Q.io.deq.bits connect bundle_1.address, tlb.io.resp.paddr node _a_mask_sizeOH_T_3 = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T_1 = pad(_a_mask_sizeOH_T_3, 3) node a_mask_sizeOH_shiftAmount_1 = bits(_a_mask_sizeOH_shiftAmount_T_1, 2, 0) node _a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount_1) node _a_mask_sizeOH_T_5 = bits(_a_mask_sizeOH_T_4, 4, 0) node a_mask_sizeOH_1 = or(_a_mask_sizeOH_T_5, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 4, 4) node a_mask_sub_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_3) node a_mask_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 3, 3) node a_mask_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_4 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_4) node a_mask_sub_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_5 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_5) node a_mask_sub_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_6 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_2_2_1) node a_mask_sub_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_6) node a_mask_sub_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_7 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_3_2_1) node a_mask_sub_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_7) node a_mask_sub_sub_size_1 = bits(a_mask_sizeOH_1, 2, 2) node a_mask_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit_1 = eq(a_mask_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_8 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_0_2_1) node a_mask_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_8) node a_mask_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_9 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_1_2_1) node a_mask_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_9) node a_mask_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_10 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_2_2_1) node a_mask_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_10) node a_mask_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_11 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_3_2_1) node a_mask_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_11) node a_mask_sub_sub_4_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_12 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_4_2_1) node a_mask_sub_sub_4_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_12) node a_mask_sub_sub_5_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_13 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_5_2_1) node a_mask_sub_sub_5_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_13) node a_mask_sub_sub_6_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_14 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_6_2_1) node a_mask_sub_sub_6_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_14) node a_mask_sub_sub_7_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_15 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_7_2_1) node a_mask_sub_sub_7_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_15) node a_mask_sub_size_1 = bits(a_mask_sizeOH_1, 1, 1) node a_mask_sub_bit_1 = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit_1 = eq(a_mask_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_0_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_16 = and(a_mask_sub_size_1, a_mask_sub_0_2_1) node a_mask_sub_0_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_16) node a_mask_sub_1_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_17 = and(a_mask_sub_size_1, a_mask_sub_1_2_1) node a_mask_sub_1_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_17) node a_mask_sub_2_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_18 = and(a_mask_sub_size_1, a_mask_sub_2_2_1) node a_mask_sub_2_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_18) node a_mask_sub_3_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_19 = and(a_mask_sub_size_1, a_mask_sub_3_2_1) node a_mask_sub_3_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_19) node a_mask_sub_4_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_20 = and(a_mask_sub_size_1, a_mask_sub_4_2_1) node a_mask_sub_4_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_20) node a_mask_sub_5_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_21 = and(a_mask_sub_size_1, a_mask_sub_5_2_1) node a_mask_sub_5_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_21) node a_mask_sub_6_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_22 = and(a_mask_sub_size_1, a_mask_sub_6_2_1) node a_mask_sub_6_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_22) node a_mask_sub_7_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_23 = and(a_mask_sub_size_1, a_mask_sub_7_2_1) node a_mask_sub_7_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_23) node a_mask_sub_8_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_24 = and(a_mask_sub_size_1, a_mask_sub_8_2_1) node a_mask_sub_8_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_24) node a_mask_sub_9_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_25 = and(a_mask_sub_size_1, a_mask_sub_9_2_1) node a_mask_sub_9_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_25) node a_mask_sub_10_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_26 = and(a_mask_sub_size_1, a_mask_sub_10_2_1) node a_mask_sub_10_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_26) node a_mask_sub_11_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_27 = and(a_mask_sub_size_1, a_mask_sub_11_2_1) node a_mask_sub_11_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_27) node a_mask_sub_12_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_28 = and(a_mask_sub_size_1, a_mask_sub_12_2_1) node a_mask_sub_12_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_28) node a_mask_sub_13_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_29 = and(a_mask_sub_size_1, a_mask_sub_13_2_1) node a_mask_sub_13_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_29) node a_mask_sub_14_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_30 = and(a_mask_sub_size_1, a_mask_sub_14_2_1) node a_mask_sub_14_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_30) node a_mask_sub_15_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_31 = and(a_mask_sub_size_1, a_mask_sub_15_2_1) node a_mask_sub_15_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_31) node a_mask_size_1 = bits(a_mask_sizeOH_1, 0, 0) node a_mask_bit_1 = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit_1 = eq(a_mask_bit_1, UInt<1>(0h0)) node a_mask_eq_32 = and(a_mask_sub_0_2_1, a_mask_nbit_1) node _a_mask_acc_T_32 = and(a_mask_size_1, a_mask_eq_32) node a_mask_acc_32 = or(a_mask_sub_0_1_1, _a_mask_acc_T_32) node a_mask_eq_33 = and(a_mask_sub_0_2_1, a_mask_bit_1) node _a_mask_acc_T_33 = and(a_mask_size_1, a_mask_eq_33) node a_mask_acc_33 = or(a_mask_sub_0_1_1, _a_mask_acc_T_33) node a_mask_eq_34 = and(a_mask_sub_1_2_1, a_mask_nbit_1) node _a_mask_acc_T_34 = and(a_mask_size_1, a_mask_eq_34) node a_mask_acc_34 = or(a_mask_sub_1_1_1, _a_mask_acc_T_34) node a_mask_eq_35 = and(a_mask_sub_1_2_1, a_mask_bit_1) node _a_mask_acc_T_35 = and(a_mask_size_1, a_mask_eq_35) node a_mask_acc_35 = or(a_mask_sub_1_1_1, _a_mask_acc_T_35) node a_mask_eq_36 = and(a_mask_sub_2_2_1, a_mask_nbit_1) node _a_mask_acc_T_36 = and(a_mask_size_1, a_mask_eq_36) node a_mask_acc_36 = or(a_mask_sub_2_1_1, _a_mask_acc_T_36) node a_mask_eq_37 = and(a_mask_sub_2_2_1, a_mask_bit_1) node _a_mask_acc_T_37 = and(a_mask_size_1, a_mask_eq_37) node a_mask_acc_37 = or(a_mask_sub_2_1_1, _a_mask_acc_T_37) node a_mask_eq_38 = and(a_mask_sub_3_2_1, a_mask_nbit_1) node _a_mask_acc_T_38 = and(a_mask_size_1, a_mask_eq_38) node a_mask_acc_38 = or(a_mask_sub_3_1_1, _a_mask_acc_T_38) node a_mask_eq_39 = and(a_mask_sub_3_2_1, a_mask_bit_1) node _a_mask_acc_T_39 = and(a_mask_size_1, a_mask_eq_39) node a_mask_acc_39 = or(a_mask_sub_3_1_1, _a_mask_acc_T_39) node a_mask_eq_40 = and(a_mask_sub_4_2_1, a_mask_nbit_1) node _a_mask_acc_T_40 = and(a_mask_size_1, a_mask_eq_40) node a_mask_acc_40 = or(a_mask_sub_4_1_1, _a_mask_acc_T_40) node a_mask_eq_41 = and(a_mask_sub_4_2_1, a_mask_bit_1) node _a_mask_acc_T_41 = and(a_mask_size_1, a_mask_eq_41) node a_mask_acc_41 = or(a_mask_sub_4_1_1, _a_mask_acc_T_41) node a_mask_eq_42 = and(a_mask_sub_5_2_1, a_mask_nbit_1) node _a_mask_acc_T_42 = and(a_mask_size_1, a_mask_eq_42) node a_mask_acc_42 = or(a_mask_sub_5_1_1, _a_mask_acc_T_42) node a_mask_eq_43 = and(a_mask_sub_5_2_1, a_mask_bit_1) node _a_mask_acc_T_43 = and(a_mask_size_1, a_mask_eq_43) node a_mask_acc_43 = or(a_mask_sub_5_1_1, _a_mask_acc_T_43) node a_mask_eq_44 = and(a_mask_sub_6_2_1, a_mask_nbit_1) node _a_mask_acc_T_44 = and(a_mask_size_1, a_mask_eq_44) node a_mask_acc_44 = or(a_mask_sub_6_1_1, _a_mask_acc_T_44) node a_mask_eq_45 = and(a_mask_sub_6_2_1, a_mask_bit_1) node _a_mask_acc_T_45 = and(a_mask_size_1, a_mask_eq_45) node a_mask_acc_45 = or(a_mask_sub_6_1_1, _a_mask_acc_T_45) node a_mask_eq_46 = and(a_mask_sub_7_2_1, a_mask_nbit_1) node _a_mask_acc_T_46 = and(a_mask_size_1, a_mask_eq_46) node a_mask_acc_46 = or(a_mask_sub_7_1_1, _a_mask_acc_T_46) node a_mask_eq_47 = and(a_mask_sub_7_2_1, a_mask_bit_1) node _a_mask_acc_T_47 = and(a_mask_size_1, a_mask_eq_47) node a_mask_acc_47 = or(a_mask_sub_7_1_1, _a_mask_acc_T_47) node a_mask_eq_48 = and(a_mask_sub_8_2_1, a_mask_nbit_1) node _a_mask_acc_T_48 = and(a_mask_size_1, a_mask_eq_48) node a_mask_acc_48 = or(a_mask_sub_8_1_1, _a_mask_acc_T_48) node a_mask_eq_49 = and(a_mask_sub_8_2_1, a_mask_bit_1) node _a_mask_acc_T_49 = and(a_mask_size_1, a_mask_eq_49) node a_mask_acc_49 = or(a_mask_sub_8_1_1, _a_mask_acc_T_49) node a_mask_eq_50 = and(a_mask_sub_9_2_1, a_mask_nbit_1) node _a_mask_acc_T_50 = and(a_mask_size_1, a_mask_eq_50) node a_mask_acc_50 = or(a_mask_sub_9_1_1, _a_mask_acc_T_50) node a_mask_eq_51 = and(a_mask_sub_9_2_1, a_mask_bit_1) node _a_mask_acc_T_51 = and(a_mask_size_1, a_mask_eq_51) node a_mask_acc_51 = or(a_mask_sub_9_1_1, _a_mask_acc_T_51) node a_mask_eq_52 = and(a_mask_sub_10_2_1, a_mask_nbit_1) node _a_mask_acc_T_52 = and(a_mask_size_1, a_mask_eq_52) node a_mask_acc_52 = or(a_mask_sub_10_1_1, _a_mask_acc_T_52) node a_mask_eq_53 = and(a_mask_sub_10_2_1, a_mask_bit_1) node _a_mask_acc_T_53 = and(a_mask_size_1, a_mask_eq_53) node a_mask_acc_53 = or(a_mask_sub_10_1_1, _a_mask_acc_T_53) node a_mask_eq_54 = and(a_mask_sub_11_2_1, a_mask_nbit_1) node _a_mask_acc_T_54 = and(a_mask_size_1, a_mask_eq_54) node a_mask_acc_54 = or(a_mask_sub_11_1_1, _a_mask_acc_T_54) node a_mask_eq_55 = and(a_mask_sub_11_2_1, a_mask_bit_1) node _a_mask_acc_T_55 = and(a_mask_size_1, a_mask_eq_55) node a_mask_acc_55 = or(a_mask_sub_11_1_1, _a_mask_acc_T_55) node a_mask_eq_56 = and(a_mask_sub_12_2_1, a_mask_nbit_1) node _a_mask_acc_T_56 = and(a_mask_size_1, a_mask_eq_56) node a_mask_acc_56 = or(a_mask_sub_12_1_1, _a_mask_acc_T_56) node a_mask_eq_57 = and(a_mask_sub_12_2_1, a_mask_bit_1) node _a_mask_acc_T_57 = and(a_mask_size_1, a_mask_eq_57) node a_mask_acc_57 = or(a_mask_sub_12_1_1, _a_mask_acc_T_57) node a_mask_eq_58 = and(a_mask_sub_13_2_1, a_mask_nbit_1) node _a_mask_acc_T_58 = and(a_mask_size_1, a_mask_eq_58) node a_mask_acc_58 = or(a_mask_sub_13_1_1, _a_mask_acc_T_58) node a_mask_eq_59 = and(a_mask_sub_13_2_1, a_mask_bit_1) node _a_mask_acc_T_59 = and(a_mask_size_1, a_mask_eq_59) node a_mask_acc_59 = or(a_mask_sub_13_1_1, _a_mask_acc_T_59) node a_mask_eq_60 = and(a_mask_sub_14_2_1, a_mask_nbit_1) node _a_mask_acc_T_60 = and(a_mask_size_1, a_mask_eq_60) node a_mask_acc_60 = or(a_mask_sub_14_1_1, _a_mask_acc_T_60) node a_mask_eq_61 = and(a_mask_sub_14_2_1, a_mask_bit_1) node _a_mask_acc_T_61 = and(a_mask_size_1, a_mask_eq_61) node a_mask_acc_61 = or(a_mask_sub_14_1_1, _a_mask_acc_T_61) node a_mask_eq_62 = and(a_mask_sub_15_2_1, a_mask_nbit_1) node _a_mask_acc_T_62 = and(a_mask_size_1, a_mask_eq_62) node a_mask_acc_62 = or(a_mask_sub_15_1_1, _a_mask_acc_T_62) node a_mask_eq_63 = and(a_mask_sub_15_2_1, a_mask_bit_1) node _a_mask_acc_T_63 = and(a_mask_size_1, a_mask_eq_63) node a_mask_acc_63 = or(a_mask_sub_15_1_1, _a_mask_acc_T_63) node a_mask_lo_lo_lo_lo_1 = cat(a_mask_acc_33, a_mask_acc_32) node a_mask_lo_lo_lo_hi_1 = cat(a_mask_acc_35, a_mask_acc_34) node a_mask_lo_lo_lo_1 = cat(a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1) node a_mask_lo_lo_hi_lo_1 = cat(a_mask_acc_37, a_mask_acc_36) node a_mask_lo_lo_hi_hi_1 = cat(a_mask_acc_39, a_mask_acc_38) node a_mask_lo_lo_hi_1 = cat(a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1) node a_mask_lo_lo_1 = cat(a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1) node a_mask_lo_hi_lo_lo_1 = cat(a_mask_acc_41, a_mask_acc_40) node a_mask_lo_hi_lo_hi_1 = cat(a_mask_acc_43, a_mask_acc_42) node a_mask_lo_hi_lo_1 = cat(a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1) node a_mask_lo_hi_hi_lo_1 = cat(a_mask_acc_45, a_mask_acc_44) node a_mask_lo_hi_hi_hi_1 = cat(a_mask_acc_47, a_mask_acc_46) node a_mask_lo_hi_hi_1 = cat(a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1) node a_mask_lo_hi_1 = cat(a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1) node a_mask_lo_1 = cat(a_mask_lo_hi_1, a_mask_lo_lo_1) node a_mask_hi_lo_lo_lo_1 = cat(a_mask_acc_49, a_mask_acc_48) node a_mask_hi_lo_lo_hi_1 = cat(a_mask_acc_51, a_mask_acc_50) node a_mask_hi_lo_lo_1 = cat(a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1) node a_mask_hi_lo_hi_lo_1 = cat(a_mask_acc_53, a_mask_acc_52) node a_mask_hi_lo_hi_hi_1 = cat(a_mask_acc_55, a_mask_acc_54) node a_mask_hi_lo_hi_1 = cat(a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1) node a_mask_hi_lo_1 = cat(a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1) node a_mask_hi_hi_lo_lo_1 = cat(a_mask_acc_57, a_mask_acc_56) node a_mask_hi_hi_lo_hi_1 = cat(a_mask_acc_59, a_mask_acc_58) node a_mask_hi_hi_lo_1 = cat(a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1) node a_mask_hi_hi_hi_lo_1 = cat(a_mask_acc_61, a_mask_acc_60) node a_mask_hi_hi_hi_hi_1 = cat(a_mask_acc_63, a_mask_acc_62) node a_mask_hi_hi_hi_1 = cat(a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1) node a_mask_hi_hi_1 = cat(a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1) node a_mask_hi_1 = cat(a_mask_hi_hi_1, a_mask_hi_lo_1) node _a_mask_T_1 = cat(a_mask_hi_1, a_mask_lo_1) connect bundle_1.mask, _a_mask_T_1 connect bundle_1.data, _T_31 connect bundle_1.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle_1.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle_1.data connect request_latency_injection_q.io.enq.bits.mask, bundle_1.mask connect request_latency_injection_q.io.enq.bits.address, bundle_1.address connect request_latency_injection_q.io.enq.bits.source, bundle_1.source connect request_latency_injection_q.io.enq.bits.size, bundle_1.size connect request_latency_injection_q.io.enq.bits.param, bundle_1.param connect request_latency_injection_q.io.enq.bits.opcode, bundle_1.opcode else : when request_input.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_10 node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : printf(clock, UInt<1>(0h1), "[raw_block_reader] ERR") : printf_11 node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: ERR\n at L2MemHelperLatencyInjection.scala:178 assert(false.B, \"ERR\")\n") : printf_12 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_2 inst Queue4_L2RespInternal of Queue4_L2RespInternal_338 connect Queue4_L2RespInternal.clock, clock connect Queue4_L2RespInternal.reset, reset inst Queue4_L2RespInternal_1 of Queue4_L2RespInternal_339 connect Queue4_L2RespInternal_1.clock, clock connect Queue4_L2RespInternal_1.reset, reset inst Queue4_L2RespInternal_2 of Queue4_L2RespInternal_340 connect Queue4_L2RespInternal_2.clock, clock connect Queue4_L2RespInternal_2.reset, reset inst Queue4_L2RespInternal_3 of Queue4_L2RespInternal_341 connect Queue4_L2RespInternal_3.clock, clock connect Queue4_L2RespInternal_3.reset, reset inst Queue4_L2RespInternal_4 of Queue4_L2RespInternal_342 connect Queue4_L2RespInternal_4.clock, clock connect Queue4_L2RespInternal_4.reset, reset inst Queue4_L2RespInternal_5 of Queue4_L2RespInternal_343 connect Queue4_L2RespInternal_5.clock, clock connect Queue4_L2RespInternal_5.reset, reset inst Queue4_L2RespInternal_6 of Queue4_L2RespInternal_344 connect Queue4_L2RespInternal_6.clock, clock connect Queue4_L2RespInternal_6.reset, reset inst Queue4_L2RespInternal_7 of Queue4_L2RespInternal_345 connect Queue4_L2RespInternal_7.clock, clock connect Queue4_L2RespInternal_7.reset, reset inst Queue4_L2RespInternal_8 of Queue4_L2RespInternal_346 connect Queue4_L2RespInternal_8.clock, clock connect Queue4_L2RespInternal_8.reset, reset inst Queue4_L2RespInternal_9 of Queue4_L2RespInternal_347 connect Queue4_L2RespInternal_9.clock, clock connect Queue4_L2RespInternal_9.reset, reset inst Queue4_L2RespInternal_10 of Queue4_L2RespInternal_348 connect Queue4_L2RespInternal_10.clock, clock connect Queue4_L2RespInternal_10.reset, reset inst Queue4_L2RespInternal_11 of Queue4_L2RespInternal_349 connect Queue4_L2RespInternal_11.clock, clock connect Queue4_L2RespInternal_11.reset, reset inst Queue4_L2RespInternal_12 of Queue4_L2RespInternal_350 connect Queue4_L2RespInternal_12.clock, clock connect Queue4_L2RespInternal_12.reset, reset inst Queue4_L2RespInternal_13 of Queue4_L2RespInternal_351 connect Queue4_L2RespInternal_13.clock, clock connect Queue4_L2RespInternal_13.reset, reset inst Queue4_L2RespInternal_14 of Queue4_L2RespInternal_352 connect Queue4_L2RespInternal_14.clock, clock connect Queue4_L2RespInternal_14.reset, reset inst Queue4_L2RespInternal_15 of Queue4_L2RespInternal_353 connect Queue4_L2RespInternal_15.clock, clock connect Queue4_L2RespInternal_15.reset, reset inst Queue4_L2RespInternal_16 of Queue4_L2RespInternal_354 connect Queue4_L2RespInternal_16.clock, clock connect Queue4_L2RespInternal_16.reset, reset inst Queue4_L2RespInternal_17 of Queue4_L2RespInternal_355 connect Queue4_L2RespInternal_17.clock, clock connect Queue4_L2RespInternal_17.reset, reset inst Queue4_L2RespInternal_18 of Queue4_L2RespInternal_356 connect Queue4_L2RespInternal_18.clock, clock connect Queue4_L2RespInternal_18.reset, reset inst Queue4_L2RespInternal_19 of Queue4_L2RespInternal_357 connect Queue4_L2RespInternal_19.clock, clock connect Queue4_L2RespInternal_19.reset, reset inst Queue4_L2RespInternal_20 of Queue4_L2RespInternal_358 connect Queue4_L2RespInternal_20.clock, clock connect Queue4_L2RespInternal_20.reset, reset inst Queue4_L2RespInternal_21 of Queue4_L2RespInternal_359 connect Queue4_L2RespInternal_21.clock, clock connect Queue4_L2RespInternal_21.reset, reset inst Queue4_L2RespInternal_22 of Queue4_L2RespInternal_360 connect Queue4_L2RespInternal_22.clock, clock connect Queue4_L2RespInternal_22.reset, reset inst Queue4_L2RespInternal_23 of Queue4_L2RespInternal_361 connect Queue4_L2RespInternal_23.clock, clock connect Queue4_L2RespInternal_23.reset, reset inst Queue4_L2RespInternal_24 of Queue4_L2RespInternal_362 connect Queue4_L2RespInternal_24.clock, clock connect Queue4_L2RespInternal_24.reset, reset inst Queue4_L2RespInternal_25 of Queue4_L2RespInternal_363 connect Queue4_L2RespInternal_25.clock, clock connect Queue4_L2RespInternal_25.reset, reset inst Queue4_L2RespInternal_26 of Queue4_L2RespInternal_364 connect Queue4_L2RespInternal_26.clock, clock connect Queue4_L2RespInternal_26.reset, reset inst Queue4_L2RespInternal_27 of Queue4_L2RespInternal_365 connect Queue4_L2RespInternal_27.clock, clock connect Queue4_L2RespInternal_27.reset, reset inst Queue4_L2RespInternal_28 of Queue4_L2RespInternal_366 connect Queue4_L2RespInternal_28.clock, clock connect Queue4_L2RespInternal_28.reset, reset inst Queue4_L2RespInternal_29 of Queue4_L2RespInternal_367 connect Queue4_L2RespInternal_29.clock, clock connect Queue4_L2RespInternal_29.reset, reset inst Queue4_L2RespInternal_30 of Queue4_L2RespInternal_368 connect Queue4_L2RespInternal_30.clock, clock connect Queue4_L2RespInternal_30.reset, reset inst Queue4_L2RespInternal_31 of Queue4_L2RespInternal_369 connect Queue4_L2RespInternal_31.clock, clock connect Queue4_L2RespInternal_31.reset, reset node _current_request_tag_has_response_space_T = eq(UInt<1>(0h0), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _current_request_tag_has_response_space_T) node _current_request_tag_has_response_space_T_2 = eq(UInt<1>(0h1), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _current_request_tag_has_response_space_T_2) node _current_request_tag_has_response_space_T_4 = eq(UInt<2>(0h2), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _current_request_tag_has_response_space_T_4) node _current_request_tag_has_response_space_T_6 = eq(UInt<2>(0h3), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _current_request_tag_has_response_space_T_6) node _current_request_tag_has_response_space_T_8 = eq(UInt<3>(0h4), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_9 = and(Queue4_L2RespInternal_4.io.enq.ready, _current_request_tag_has_response_space_T_8) node _current_request_tag_has_response_space_T_10 = eq(UInt<3>(0h5), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_11 = and(Queue4_L2RespInternal_5.io.enq.ready, _current_request_tag_has_response_space_T_10) node _current_request_tag_has_response_space_T_12 = eq(UInt<3>(0h6), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_13 = and(Queue4_L2RespInternal_6.io.enq.ready, _current_request_tag_has_response_space_T_12) node _current_request_tag_has_response_space_T_14 = eq(UInt<3>(0h7), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_15 = and(Queue4_L2RespInternal_7.io.enq.ready, _current_request_tag_has_response_space_T_14) node _current_request_tag_has_response_space_T_16 = eq(UInt<4>(0h8), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_17 = and(Queue4_L2RespInternal_8.io.enq.ready, _current_request_tag_has_response_space_T_16) node _current_request_tag_has_response_space_T_18 = eq(UInt<4>(0h9), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_19 = and(Queue4_L2RespInternal_9.io.enq.ready, _current_request_tag_has_response_space_T_18) node _current_request_tag_has_response_space_T_20 = eq(UInt<4>(0ha), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_21 = and(Queue4_L2RespInternal_10.io.enq.ready, _current_request_tag_has_response_space_T_20) node _current_request_tag_has_response_space_T_22 = eq(UInt<4>(0hb), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_23 = and(Queue4_L2RespInternal_11.io.enq.ready, _current_request_tag_has_response_space_T_22) node _current_request_tag_has_response_space_T_24 = eq(UInt<4>(0hc), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_25 = and(Queue4_L2RespInternal_12.io.enq.ready, _current_request_tag_has_response_space_T_24) node _current_request_tag_has_response_space_T_26 = eq(UInt<4>(0hd), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_27 = and(Queue4_L2RespInternal_13.io.enq.ready, _current_request_tag_has_response_space_T_26) node _current_request_tag_has_response_space_T_28 = eq(UInt<4>(0he), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_29 = and(Queue4_L2RespInternal_14.io.enq.ready, _current_request_tag_has_response_space_T_28) node _current_request_tag_has_response_space_T_30 = eq(UInt<4>(0hf), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_31 = and(Queue4_L2RespInternal_15.io.enq.ready, _current_request_tag_has_response_space_T_30) node _current_request_tag_has_response_space_T_32 = eq(UInt<5>(0h10), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_33 = and(Queue4_L2RespInternal_16.io.enq.ready, _current_request_tag_has_response_space_T_32) node _current_request_tag_has_response_space_T_34 = eq(UInt<5>(0h11), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_35 = and(Queue4_L2RespInternal_17.io.enq.ready, _current_request_tag_has_response_space_T_34) node _current_request_tag_has_response_space_T_36 = eq(UInt<5>(0h12), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_37 = and(Queue4_L2RespInternal_18.io.enq.ready, _current_request_tag_has_response_space_T_36) node _current_request_tag_has_response_space_T_38 = eq(UInt<5>(0h13), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_39 = and(Queue4_L2RespInternal_19.io.enq.ready, _current_request_tag_has_response_space_T_38) node _current_request_tag_has_response_space_T_40 = eq(UInt<5>(0h14), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_41 = and(Queue4_L2RespInternal_20.io.enq.ready, _current_request_tag_has_response_space_T_40) node _current_request_tag_has_response_space_T_42 = eq(UInt<5>(0h15), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_43 = and(Queue4_L2RespInternal_21.io.enq.ready, _current_request_tag_has_response_space_T_42) node _current_request_tag_has_response_space_T_44 = eq(UInt<5>(0h16), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_45 = and(Queue4_L2RespInternal_22.io.enq.ready, _current_request_tag_has_response_space_T_44) node _current_request_tag_has_response_space_T_46 = eq(UInt<5>(0h17), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_47 = and(Queue4_L2RespInternal_23.io.enq.ready, _current_request_tag_has_response_space_T_46) node _current_request_tag_has_response_space_T_48 = eq(UInt<5>(0h18), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_49 = and(Queue4_L2RespInternal_24.io.enq.ready, _current_request_tag_has_response_space_T_48) node _current_request_tag_has_response_space_T_50 = eq(UInt<5>(0h19), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_51 = and(Queue4_L2RespInternal_25.io.enq.ready, _current_request_tag_has_response_space_T_50) node _current_request_tag_has_response_space_T_52 = eq(UInt<5>(0h1a), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_53 = and(Queue4_L2RespInternal_26.io.enq.ready, _current_request_tag_has_response_space_T_52) node _current_request_tag_has_response_space_T_54 = eq(UInt<5>(0h1b), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_55 = and(Queue4_L2RespInternal_27.io.enq.ready, _current_request_tag_has_response_space_T_54) node _current_request_tag_has_response_space_T_56 = eq(UInt<5>(0h1c), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_57 = and(Queue4_L2RespInternal_28.io.enq.ready, _current_request_tag_has_response_space_T_56) node _current_request_tag_has_response_space_T_58 = eq(UInt<5>(0h1d), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_59 = and(Queue4_L2RespInternal_29.io.enq.ready, _current_request_tag_has_response_space_T_58) node _current_request_tag_has_response_space_T_60 = eq(UInt<5>(0h1e), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_61 = and(Queue4_L2RespInternal_30.io.enq.ready, _current_request_tag_has_response_space_T_60) node _current_request_tag_has_response_space_T_62 = eq(UInt<5>(0h1f), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_63 = and(Queue4_L2RespInternal_31.io.enq.ready, _current_request_tag_has_response_space_T_62) node _current_request_tag_has_response_space_T_64 = or(_current_request_tag_has_response_space_T_1, _current_request_tag_has_response_space_T_3) node _current_request_tag_has_response_space_T_65 = or(_current_request_tag_has_response_space_T_64, _current_request_tag_has_response_space_T_5) node _current_request_tag_has_response_space_T_66 = or(_current_request_tag_has_response_space_T_65, _current_request_tag_has_response_space_T_7) node _current_request_tag_has_response_space_T_67 = or(_current_request_tag_has_response_space_T_66, _current_request_tag_has_response_space_T_9) node _current_request_tag_has_response_space_T_68 = or(_current_request_tag_has_response_space_T_67, _current_request_tag_has_response_space_T_11) node _current_request_tag_has_response_space_T_69 = or(_current_request_tag_has_response_space_T_68, _current_request_tag_has_response_space_T_13) node _current_request_tag_has_response_space_T_70 = or(_current_request_tag_has_response_space_T_69, _current_request_tag_has_response_space_T_15) node _current_request_tag_has_response_space_T_71 = or(_current_request_tag_has_response_space_T_70, _current_request_tag_has_response_space_T_17) node _current_request_tag_has_response_space_T_72 = or(_current_request_tag_has_response_space_T_71, _current_request_tag_has_response_space_T_19) node _current_request_tag_has_response_space_T_73 = or(_current_request_tag_has_response_space_T_72, _current_request_tag_has_response_space_T_21) node _current_request_tag_has_response_space_T_74 = or(_current_request_tag_has_response_space_T_73, _current_request_tag_has_response_space_T_23) node _current_request_tag_has_response_space_T_75 = or(_current_request_tag_has_response_space_T_74, _current_request_tag_has_response_space_T_25) node _current_request_tag_has_response_space_T_76 = or(_current_request_tag_has_response_space_T_75, _current_request_tag_has_response_space_T_27) node _current_request_tag_has_response_space_T_77 = or(_current_request_tag_has_response_space_T_76, _current_request_tag_has_response_space_T_29) node _current_request_tag_has_response_space_T_78 = or(_current_request_tag_has_response_space_T_77, _current_request_tag_has_response_space_T_31) node _current_request_tag_has_response_space_T_79 = or(_current_request_tag_has_response_space_T_78, _current_request_tag_has_response_space_T_33) node _current_request_tag_has_response_space_T_80 = or(_current_request_tag_has_response_space_T_79, _current_request_tag_has_response_space_T_35) node _current_request_tag_has_response_space_T_81 = or(_current_request_tag_has_response_space_T_80, _current_request_tag_has_response_space_T_37) node _current_request_tag_has_response_space_T_82 = or(_current_request_tag_has_response_space_T_81, _current_request_tag_has_response_space_T_39) node _current_request_tag_has_response_space_T_83 = or(_current_request_tag_has_response_space_T_82, _current_request_tag_has_response_space_T_41) node _current_request_tag_has_response_space_T_84 = or(_current_request_tag_has_response_space_T_83, _current_request_tag_has_response_space_T_43) node _current_request_tag_has_response_space_T_85 = or(_current_request_tag_has_response_space_T_84, _current_request_tag_has_response_space_T_45) node _current_request_tag_has_response_space_T_86 = or(_current_request_tag_has_response_space_T_85, _current_request_tag_has_response_space_T_47) node _current_request_tag_has_response_space_T_87 = or(_current_request_tag_has_response_space_T_86, _current_request_tag_has_response_space_T_49) node _current_request_tag_has_response_space_T_88 = or(_current_request_tag_has_response_space_T_87, _current_request_tag_has_response_space_T_51) node _current_request_tag_has_response_space_T_89 = or(_current_request_tag_has_response_space_T_88, _current_request_tag_has_response_space_T_53) node _current_request_tag_has_response_space_T_90 = or(_current_request_tag_has_response_space_T_89, _current_request_tag_has_response_space_T_55) node _current_request_tag_has_response_space_T_91 = or(_current_request_tag_has_response_space_T_90, _current_request_tag_has_response_space_T_57) node _current_request_tag_has_response_space_T_92 = or(_current_request_tag_has_response_space_T_91, _current_request_tag_has_response_space_T_59) node _current_request_tag_has_response_space_T_93 = or(_current_request_tag_has_response_space_T_92, _current_request_tag_has_response_space_T_61) node current_request_tag_has_response_space = or(_current_request_tag_has_response_space_T_93, _current_request_tag_has_response_space_T_63) node _outstanding_req_addr_io_enq_bits_addrindex_T = and(request_input.bits.addr, UInt<5>(0h1f)) connect outstanding_req_addr.io.enq.bits.addrindex, _outstanding_req_addr_io_enq_bits_addrindex_T connect outstanding_req_addr.io.enq.bits.tag, tags_for_issue_Q.io.deq.bits node _request_latency_injection_q_io_enq_valid_T = and(request_input.valid, tlb_ready) node _request_latency_injection_q_io_enq_valid_T_1 = and(_request_latency_injection_q_io_enq_valid_T, outstanding_req_addr.io.enq.ready) node _request_latency_injection_q_io_enq_valid_T_2 = and(_request_latency_injection_q_io_enq_valid_T_1, free_outstanding_op_slots) node _request_latency_injection_q_io_enq_valid_T_3 = and(_request_latency_injection_q_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _request_latency_injection_q_io_enq_valid_T_4 = and(_request_latency_injection_q_io_enq_valid_T_3, current_request_tag_has_response_space) connect request_latency_injection_q.io.enq.valid, _request_latency_injection_q_io_enq_valid_T_4 node _request_input_ready_T = and(request_latency_injection_q.io.enq.ready, tlb_ready) node _request_input_ready_T_1 = and(_request_input_ready_T, outstanding_req_addr.io.enq.ready) node _request_input_ready_T_2 = and(_request_input_ready_T_1, free_outstanding_op_slots) node _request_input_ready_T_3 = and(_request_input_ready_T_2, tags_for_issue_Q.io.deq.valid) node _request_input_ready_T_4 = and(_request_input_ready_T_3, current_request_tag_has_response_space) connect request_input.ready, _request_input_ready_T_4 node _outstanding_req_addr_io_enq_valid_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _outstanding_req_addr_io_enq_valid_T_1 = and(_outstanding_req_addr_io_enq_valid_T, tlb_ready) node _outstanding_req_addr_io_enq_valid_T_2 = and(_outstanding_req_addr_io_enq_valid_T_1, free_outstanding_op_slots) node _outstanding_req_addr_io_enq_valid_T_3 = and(_outstanding_req_addr_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _outstanding_req_addr_io_enq_valid_T_4 = and(_outstanding_req_addr_io_enq_valid_T_3, current_request_tag_has_response_space) connect outstanding_req_addr.io.enq.valid, _outstanding_req_addr_io_enq_valid_T_4 node _tags_for_issue_Q_io_deq_ready_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_1 = and(_tags_for_issue_Q_io_deq_ready_T, tlb_ready) node _tags_for_issue_Q_io_deq_ready_T_2 = and(_tags_for_issue_Q_io_deq_ready_T_1, outstanding_req_addr.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_3 = and(_tags_for_issue_Q_io_deq_ready_T_2, free_outstanding_op_slots) node _tags_for_issue_Q_io_deq_ready_T_4 = and(_tags_for_issue_Q_io_deq_ready_T_3, current_request_tag_has_response_space) connect tags_for_issue_Q.io.deq.ready, _tags_for_issue_Q_io_deq_ready_T_4 connect masterNodeOut.a.bits, request_latency_injection_q.io.deq.bits connect masterNodeOut.a.valid, request_latency_injection_q.io.deq.valid connect request_latency_injection_q.io.deq.ready, masterNodeOut.a.ready node _T_39 = and(masterNodeOut.a.ready, masterNodeOut.a.valid) when _T_39 : node _T_40 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_40 : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_13 node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_14 node _T_45 = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _T_46 = and(_T_45, tlb_ready) node _T_47 = and(_T_46, outstanding_req_addr.io.enq.ready) node _T_48 = and(_T_47, free_outstanding_op_slots) node _T_49 = and(_T_48, tags_for_issue_Q.io.deq.valid) node _T_50 = and(_T_49, current_request_tag_has_response_space) when _T_50 : node _T_51 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_51 : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _printf_T = asUInt(reset) node _printf_T_1 = eq(_printf_T, UInt<1>(0h0)) when _printf_T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_15 node _T_52 = asUInt(reset) node _T_53 = eq(_T_52, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "") : printf_16 node _printf_T_2 = asUInt(reset) node _printf_T_3 = eq(_printf_T_2, UInt<1>(0h0)) when _printf_T_3 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: req(write) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, data: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, request_input.bits.data, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_17 node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "") : printf_18 inst response_latency_injection_q of LatencyInjectionQueue_29 connect response_latency_injection_q.clock, clock connect response_latency_injection_q.reset, reset connect response_latency_injection_q.io.latency_cycles, io.latency_inject_cycles connect response_latency_injection_q.io.enq, masterNodeOut.d node _selectQready_T = eq(UInt<1>(0h0), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _selectQready_T) node _selectQready_T_2 = eq(UInt<1>(0h1), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _selectQready_T_2) node _selectQready_T_4 = eq(UInt<2>(0h2), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _selectQready_T_4) node _selectQready_T_6 = eq(UInt<2>(0h3), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _selectQready_T_6) node _selectQready_T_8 = eq(UInt<3>(0h4), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_9 = and(Queue4_L2RespInternal_4.io.enq.ready, _selectQready_T_8) node _selectQready_T_10 = eq(UInt<3>(0h5), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_11 = and(Queue4_L2RespInternal_5.io.enq.ready, _selectQready_T_10) node _selectQready_T_12 = eq(UInt<3>(0h6), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_13 = and(Queue4_L2RespInternal_6.io.enq.ready, _selectQready_T_12) node _selectQready_T_14 = eq(UInt<3>(0h7), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_15 = and(Queue4_L2RespInternal_7.io.enq.ready, _selectQready_T_14) node _selectQready_T_16 = eq(UInt<4>(0h8), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_17 = and(Queue4_L2RespInternal_8.io.enq.ready, _selectQready_T_16) node _selectQready_T_18 = eq(UInt<4>(0h9), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_19 = and(Queue4_L2RespInternal_9.io.enq.ready, _selectQready_T_18) node _selectQready_T_20 = eq(UInt<4>(0ha), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_21 = and(Queue4_L2RespInternal_10.io.enq.ready, _selectQready_T_20) node _selectQready_T_22 = eq(UInt<4>(0hb), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_23 = and(Queue4_L2RespInternal_11.io.enq.ready, _selectQready_T_22) node _selectQready_T_24 = eq(UInt<4>(0hc), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_25 = and(Queue4_L2RespInternal_12.io.enq.ready, _selectQready_T_24) node _selectQready_T_26 = eq(UInt<4>(0hd), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_27 = and(Queue4_L2RespInternal_13.io.enq.ready, _selectQready_T_26) node _selectQready_T_28 = eq(UInt<4>(0he), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_29 = and(Queue4_L2RespInternal_14.io.enq.ready, _selectQready_T_28) node _selectQready_T_30 = eq(UInt<4>(0hf), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_31 = and(Queue4_L2RespInternal_15.io.enq.ready, _selectQready_T_30) node _selectQready_T_32 = eq(UInt<5>(0h10), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_33 = and(Queue4_L2RespInternal_16.io.enq.ready, _selectQready_T_32) node _selectQready_T_34 = eq(UInt<5>(0h11), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_35 = and(Queue4_L2RespInternal_17.io.enq.ready, _selectQready_T_34) node _selectQready_T_36 = eq(UInt<5>(0h12), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_37 = and(Queue4_L2RespInternal_18.io.enq.ready, _selectQready_T_36) node _selectQready_T_38 = eq(UInt<5>(0h13), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_39 = and(Queue4_L2RespInternal_19.io.enq.ready, _selectQready_T_38) node _selectQready_T_40 = eq(UInt<5>(0h14), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_41 = and(Queue4_L2RespInternal_20.io.enq.ready, _selectQready_T_40) node _selectQready_T_42 = eq(UInt<5>(0h15), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_43 = and(Queue4_L2RespInternal_21.io.enq.ready, _selectQready_T_42) node _selectQready_T_44 = eq(UInt<5>(0h16), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_45 = and(Queue4_L2RespInternal_22.io.enq.ready, _selectQready_T_44) node _selectQready_T_46 = eq(UInt<5>(0h17), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_47 = and(Queue4_L2RespInternal_23.io.enq.ready, _selectQready_T_46) node _selectQready_T_48 = eq(UInt<5>(0h18), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_49 = and(Queue4_L2RespInternal_24.io.enq.ready, _selectQready_T_48) node _selectQready_T_50 = eq(UInt<5>(0h19), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_51 = and(Queue4_L2RespInternal_25.io.enq.ready, _selectQready_T_50) node _selectQready_T_52 = eq(UInt<5>(0h1a), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_53 = and(Queue4_L2RespInternal_26.io.enq.ready, _selectQready_T_52) node _selectQready_T_54 = eq(UInt<5>(0h1b), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_55 = and(Queue4_L2RespInternal_27.io.enq.ready, _selectQready_T_54) node _selectQready_T_56 = eq(UInt<5>(0h1c), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_57 = and(Queue4_L2RespInternal_28.io.enq.ready, _selectQready_T_56) node _selectQready_T_58 = eq(UInt<5>(0h1d), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_59 = and(Queue4_L2RespInternal_29.io.enq.ready, _selectQready_T_58) node _selectQready_T_60 = eq(UInt<5>(0h1e), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_61 = and(Queue4_L2RespInternal_30.io.enq.ready, _selectQready_T_60) node _selectQready_T_62 = eq(UInt<5>(0h1f), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_63 = and(Queue4_L2RespInternal_31.io.enq.ready, _selectQready_T_62) node _selectQready_T_64 = or(_selectQready_T_1, _selectQready_T_3) node _selectQready_T_65 = or(_selectQready_T_64, _selectQready_T_5) node _selectQready_T_66 = or(_selectQready_T_65, _selectQready_T_7) node _selectQready_T_67 = or(_selectQready_T_66, _selectQready_T_9) node _selectQready_T_68 = or(_selectQready_T_67, _selectQready_T_11) node _selectQready_T_69 = or(_selectQready_T_68, _selectQready_T_13) node _selectQready_T_70 = or(_selectQready_T_69, _selectQready_T_15) node _selectQready_T_71 = or(_selectQready_T_70, _selectQready_T_17) node _selectQready_T_72 = or(_selectQready_T_71, _selectQready_T_19) node _selectQready_T_73 = or(_selectQready_T_72, _selectQready_T_21) node _selectQready_T_74 = or(_selectQready_T_73, _selectQready_T_23) node _selectQready_T_75 = or(_selectQready_T_74, _selectQready_T_25) node _selectQready_T_76 = or(_selectQready_T_75, _selectQready_T_27) node _selectQready_T_77 = or(_selectQready_T_76, _selectQready_T_29) node _selectQready_T_78 = or(_selectQready_T_77, _selectQready_T_31) node _selectQready_T_79 = or(_selectQready_T_78, _selectQready_T_33) node _selectQready_T_80 = or(_selectQready_T_79, _selectQready_T_35) node _selectQready_T_81 = or(_selectQready_T_80, _selectQready_T_37) node _selectQready_T_82 = or(_selectQready_T_81, _selectQready_T_39) node _selectQready_T_83 = or(_selectQready_T_82, _selectQready_T_41) node _selectQready_T_84 = or(_selectQready_T_83, _selectQready_T_43) node _selectQready_T_85 = or(_selectQready_T_84, _selectQready_T_45) node _selectQready_T_86 = or(_selectQready_T_85, _selectQready_T_47) node _selectQready_T_87 = or(_selectQready_T_86, _selectQready_T_49) node _selectQready_T_88 = or(_selectQready_T_87, _selectQready_T_51) node _selectQready_T_89 = or(_selectQready_T_88, _selectQready_T_53) node _selectQready_T_90 = or(_selectQready_T_89, _selectQready_T_55) node _selectQready_T_91 = or(_selectQready_T_90, _selectQready_T_57) node _selectQready_T_92 = or(_selectQready_T_91, _selectQready_T_59) node _selectQready_T_93 = or(_selectQready_T_92, _selectQready_T_61) node selectQready = or(_selectQready_T_93, _selectQready_T_63) node _T_56 = and(selectQready, response_latency_injection_q.io.deq.valid) when _T_56 : connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) connect tags_for_issue_Q.io.enq.bits, response_latency_injection_q.io.deq.bits.source node _T_57 = and(selectQready, response_latency_injection_q.io.deq.valid) node _T_58 = and(_T_57, tags_for_issue_Q.io.enq.valid) when _T_58 : regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_19 node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "[raw_block_reader] tags_for_issue_Q add back tag %d\n", tags_for_issue_Q.io.enq.bits) : printf_20 node _response_latency_injection_q_io_deq_ready_T = and(selectQready, tags_for_issue_Q.io.enq.ready) connect response_latency_injection_q.io.deq.ready, _response_latency_injection_q_io_deq_ready_T node _T_63 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_64 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) connect Queue4_L2RespInternal.io.enq.valid, _T_65 connect Queue4_L2RespInternal.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_66 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_67 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h1)) node _T_68 = and(_T_66, _T_67) connect Queue4_L2RespInternal_1.io.enq.valid, _T_68 connect Queue4_L2RespInternal_1.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_69 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_70 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h2)) node _T_71 = and(_T_69, _T_70) connect Queue4_L2RespInternal_2.io.enq.valid, _T_71 connect Queue4_L2RespInternal_2.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_72 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_73 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h3)) node _T_74 = and(_T_72, _T_73) connect Queue4_L2RespInternal_3.io.enq.valid, _T_74 connect Queue4_L2RespInternal_3.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_75 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_76 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h4)) node _T_77 = and(_T_75, _T_76) connect Queue4_L2RespInternal_4.io.enq.valid, _T_77 connect Queue4_L2RespInternal_4.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_78 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_79 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h5)) node _T_80 = and(_T_78, _T_79) connect Queue4_L2RespInternal_5.io.enq.valid, _T_80 connect Queue4_L2RespInternal_5.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_81 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_82 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h6)) node _T_83 = and(_T_81, _T_82) connect Queue4_L2RespInternal_6.io.enq.valid, _T_83 connect Queue4_L2RespInternal_6.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_84 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_85 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h7)) node _T_86 = and(_T_84, _T_85) connect Queue4_L2RespInternal_7.io.enq.valid, _T_86 connect Queue4_L2RespInternal_7.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_87 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_88 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0h8)) node _T_89 = and(_T_87, _T_88) connect Queue4_L2RespInternal_8.io.enq.valid, _T_89 connect Queue4_L2RespInternal_8.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_90 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_91 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0h9)) node _T_92 = and(_T_90, _T_91) connect Queue4_L2RespInternal_9.io.enq.valid, _T_92 connect Queue4_L2RespInternal_9.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_93 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_94 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0ha)) node _T_95 = and(_T_93, _T_94) connect Queue4_L2RespInternal_10.io.enq.valid, _T_95 connect Queue4_L2RespInternal_10.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_96 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_97 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hb)) node _T_98 = and(_T_96, _T_97) connect Queue4_L2RespInternal_11.io.enq.valid, _T_98 connect Queue4_L2RespInternal_11.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_99 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_100 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) connect Queue4_L2RespInternal_12.io.enq.valid, _T_101 connect Queue4_L2RespInternal_12.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_102 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_103 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hd)) node _T_104 = and(_T_102, _T_103) connect Queue4_L2RespInternal_13.io.enq.valid, _T_104 connect Queue4_L2RespInternal_13.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_105 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_106 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0he)) node _T_107 = and(_T_105, _T_106) connect Queue4_L2RespInternal_14.io.enq.valid, _T_107 connect Queue4_L2RespInternal_14.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_108 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_109 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hf)) node _T_110 = and(_T_108, _T_109) connect Queue4_L2RespInternal_15.io.enq.valid, _T_110 connect Queue4_L2RespInternal_15.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_111 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_112 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h10)) node _T_113 = and(_T_111, _T_112) connect Queue4_L2RespInternal_16.io.enq.valid, _T_113 connect Queue4_L2RespInternal_16.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_114 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_115 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h11)) node _T_116 = and(_T_114, _T_115) connect Queue4_L2RespInternal_17.io.enq.valid, _T_116 connect Queue4_L2RespInternal_17.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_117 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_118 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h12)) node _T_119 = and(_T_117, _T_118) connect Queue4_L2RespInternal_18.io.enq.valid, _T_119 connect Queue4_L2RespInternal_18.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_120 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_121 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h13)) node _T_122 = and(_T_120, _T_121) connect Queue4_L2RespInternal_19.io.enq.valid, _T_122 connect Queue4_L2RespInternal_19.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_123 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_124 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h14)) node _T_125 = and(_T_123, _T_124) connect Queue4_L2RespInternal_20.io.enq.valid, _T_125 connect Queue4_L2RespInternal_20.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_126 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_127 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h15)) node _T_128 = and(_T_126, _T_127) connect Queue4_L2RespInternal_21.io.enq.valid, _T_128 connect Queue4_L2RespInternal_21.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_129 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_130 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h16)) node _T_131 = and(_T_129, _T_130) connect Queue4_L2RespInternal_22.io.enq.valid, _T_131 connect Queue4_L2RespInternal_22.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_132 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_133 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h17)) node _T_134 = and(_T_132, _T_133) connect Queue4_L2RespInternal_23.io.enq.valid, _T_134 connect Queue4_L2RespInternal_23.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_135 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_136 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h18)) node _T_137 = and(_T_135, _T_136) connect Queue4_L2RespInternal_24.io.enq.valid, _T_137 connect Queue4_L2RespInternal_24.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_138 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_139 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h19)) node _T_140 = and(_T_138, _T_139) connect Queue4_L2RespInternal_25.io.enq.valid, _T_140 connect Queue4_L2RespInternal_25.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_141 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_142 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1a)) node _T_143 = and(_T_141, _T_142) connect Queue4_L2RespInternal_26.io.enq.valid, _T_143 connect Queue4_L2RespInternal_26.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_144 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_145 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1b)) node _T_146 = and(_T_144, _T_145) connect Queue4_L2RespInternal_27.io.enq.valid, _T_146 connect Queue4_L2RespInternal_27.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_147 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_148 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1c)) node _T_149 = and(_T_147, _T_148) connect Queue4_L2RespInternal_28.io.enq.valid, _T_149 connect Queue4_L2RespInternal_28.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_150 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_151 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1d)) node _T_152 = and(_T_150, _T_151) connect Queue4_L2RespInternal_29.io.enq.valid, _T_152 connect Queue4_L2RespInternal_29.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_153 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_154 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1e)) node _T_155 = and(_T_153, _T_154) connect Queue4_L2RespInternal_30.io.enq.valid, _T_155 connect Queue4_L2RespInternal_30.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_156 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_157 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1f)) node _T_158 = and(_T_156, _T_157) connect Queue4_L2RespInternal_31.io.enq.valid, _T_158 connect Queue4_L2RespInternal_31.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _queueValid_T = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_1 = and(Queue4_L2RespInternal.io.deq.valid, _queueValid_T) node _queueValid_T_2 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_3 = and(Queue4_L2RespInternal_1.io.deq.valid, _queueValid_T_2) node _queueValid_T_4 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_5 = and(Queue4_L2RespInternal_2.io.deq.valid, _queueValid_T_4) node _queueValid_T_6 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_7 = and(Queue4_L2RespInternal_3.io.deq.valid, _queueValid_T_6) node _queueValid_T_8 = eq(UInt<3>(0h4), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_9 = and(Queue4_L2RespInternal_4.io.deq.valid, _queueValid_T_8) node _queueValid_T_10 = eq(UInt<3>(0h5), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_11 = and(Queue4_L2RespInternal_5.io.deq.valid, _queueValid_T_10) node _queueValid_T_12 = eq(UInt<3>(0h6), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_13 = and(Queue4_L2RespInternal_6.io.deq.valid, _queueValid_T_12) node _queueValid_T_14 = eq(UInt<3>(0h7), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_15 = and(Queue4_L2RespInternal_7.io.deq.valid, _queueValid_T_14) node _queueValid_T_16 = eq(UInt<4>(0h8), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_17 = and(Queue4_L2RespInternal_8.io.deq.valid, _queueValid_T_16) node _queueValid_T_18 = eq(UInt<4>(0h9), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_19 = and(Queue4_L2RespInternal_9.io.deq.valid, _queueValid_T_18) node _queueValid_T_20 = eq(UInt<4>(0ha), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_21 = and(Queue4_L2RespInternal_10.io.deq.valid, _queueValid_T_20) node _queueValid_T_22 = eq(UInt<4>(0hb), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_23 = and(Queue4_L2RespInternal_11.io.deq.valid, _queueValid_T_22) node _queueValid_T_24 = eq(UInt<4>(0hc), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_25 = and(Queue4_L2RespInternal_12.io.deq.valid, _queueValid_T_24) node _queueValid_T_26 = eq(UInt<4>(0hd), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_27 = and(Queue4_L2RespInternal_13.io.deq.valid, _queueValid_T_26) node _queueValid_T_28 = eq(UInt<4>(0he), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_29 = and(Queue4_L2RespInternal_14.io.deq.valid, _queueValid_T_28) node _queueValid_T_30 = eq(UInt<4>(0hf), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_31 = and(Queue4_L2RespInternal_15.io.deq.valid, _queueValid_T_30) node _queueValid_T_32 = eq(UInt<5>(0h10), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_33 = and(Queue4_L2RespInternal_16.io.deq.valid, _queueValid_T_32) node _queueValid_T_34 = eq(UInt<5>(0h11), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_35 = and(Queue4_L2RespInternal_17.io.deq.valid, _queueValid_T_34) node _queueValid_T_36 = eq(UInt<5>(0h12), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_37 = and(Queue4_L2RespInternal_18.io.deq.valid, _queueValid_T_36) node _queueValid_T_38 = eq(UInt<5>(0h13), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_39 = and(Queue4_L2RespInternal_19.io.deq.valid, _queueValid_T_38) node _queueValid_T_40 = eq(UInt<5>(0h14), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_41 = and(Queue4_L2RespInternal_20.io.deq.valid, _queueValid_T_40) node _queueValid_T_42 = eq(UInt<5>(0h15), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_43 = and(Queue4_L2RespInternal_21.io.deq.valid, _queueValid_T_42) node _queueValid_T_44 = eq(UInt<5>(0h16), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_45 = and(Queue4_L2RespInternal_22.io.deq.valid, _queueValid_T_44) node _queueValid_T_46 = eq(UInt<5>(0h17), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_47 = and(Queue4_L2RespInternal_23.io.deq.valid, _queueValid_T_46) node _queueValid_T_48 = eq(UInt<5>(0h18), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_49 = and(Queue4_L2RespInternal_24.io.deq.valid, _queueValid_T_48) node _queueValid_T_50 = eq(UInt<5>(0h19), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_51 = and(Queue4_L2RespInternal_25.io.deq.valid, _queueValid_T_50) node _queueValid_T_52 = eq(UInt<5>(0h1a), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_53 = and(Queue4_L2RespInternal_26.io.deq.valid, _queueValid_T_52) node _queueValid_T_54 = eq(UInt<5>(0h1b), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_55 = and(Queue4_L2RespInternal_27.io.deq.valid, _queueValid_T_54) node _queueValid_T_56 = eq(UInt<5>(0h1c), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_57 = and(Queue4_L2RespInternal_28.io.deq.valid, _queueValid_T_56) node _queueValid_T_58 = eq(UInt<5>(0h1d), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_59 = and(Queue4_L2RespInternal_29.io.deq.valid, _queueValid_T_58) node _queueValid_T_60 = eq(UInt<5>(0h1e), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_61 = and(Queue4_L2RespInternal_30.io.deq.valid, _queueValid_T_60) node _queueValid_T_62 = eq(UInt<5>(0h1f), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_63 = and(Queue4_L2RespInternal_31.io.deq.valid, _queueValid_T_62) node _queueValid_T_64 = or(_queueValid_T_1, _queueValid_T_3) node _queueValid_T_65 = or(_queueValid_T_64, _queueValid_T_5) node _queueValid_T_66 = or(_queueValid_T_65, _queueValid_T_7) node _queueValid_T_67 = or(_queueValid_T_66, _queueValid_T_9) node _queueValid_T_68 = or(_queueValid_T_67, _queueValid_T_11) node _queueValid_T_69 = or(_queueValid_T_68, _queueValid_T_13) node _queueValid_T_70 = or(_queueValid_T_69, _queueValid_T_15) node _queueValid_T_71 = or(_queueValid_T_70, _queueValid_T_17) node _queueValid_T_72 = or(_queueValid_T_71, _queueValid_T_19) node _queueValid_T_73 = or(_queueValid_T_72, _queueValid_T_21) node _queueValid_T_74 = or(_queueValid_T_73, _queueValid_T_23) node _queueValid_T_75 = or(_queueValid_T_74, _queueValid_T_25) node _queueValid_T_76 = or(_queueValid_T_75, _queueValid_T_27) node _queueValid_T_77 = or(_queueValid_T_76, _queueValid_T_29) node _queueValid_T_78 = or(_queueValid_T_77, _queueValid_T_31) node _queueValid_T_79 = or(_queueValid_T_78, _queueValid_T_33) node _queueValid_T_80 = or(_queueValid_T_79, _queueValid_T_35) node _queueValid_T_81 = or(_queueValid_T_80, _queueValid_T_37) node _queueValid_T_82 = or(_queueValid_T_81, _queueValid_T_39) node _queueValid_T_83 = or(_queueValid_T_82, _queueValid_T_41) node _queueValid_T_84 = or(_queueValid_T_83, _queueValid_T_43) node _queueValid_T_85 = or(_queueValid_T_84, _queueValid_T_45) node _queueValid_T_86 = or(_queueValid_T_85, _queueValid_T_47) node _queueValid_T_87 = or(_queueValid_T_86, _queueValid_T_49) node _queueValid_T_88 = or(_queueValid_T_87, _queueValid_T_51) node _queueValid_T_89 = or(_queueValid_T_88, _queueValid_T_53) node _queueValid_T_90 = or(_queueValid_T_89, _queueValid_T_55) node _queueValid_T_91 = or(_queueValid_T_90, _queueValid_T_57) node _queueValid_T_92 = or(_queueValid_T_91, _queueValid_T_59) node _queueValid_T_93 = or(_queueValid_T_92, _queueValid_T_61) node queueValid = or(_queueValid_T_93, _queueValid_T_63) node resultdata_is_current_q = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data : UInt<256> when resultdata_is_current_q : node _resultdata_data_T = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_1 = dshr(Queue4_L2RespInternal.io.deq.bits.data, _resultdata_data_T) connect resultdata_data, _resultdata_data_T_1 else : connect resultdata_data, UInt<1>(0h0) node resultdata_is_current_q_1 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_1 : UInt<256> when resultdata_is_current_q_1 : node _resultdata_data_T_2 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_3 = dshr(Queue4_L2RespInternal_1.io.deq.bits.data, _resultdata_data_T_2) connect resultdata_data_1, _resultdata_data_T_3 else : connect resultdata_data_1, UInt<1>(0h0) node resultdata_is_current_q_2 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_2 : UInt<256> when resultdata_is_current_q_2 : node _resultdata_data_T_4 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_5 = dshr(Queue4_L2RespInternal_2.io.deq.bits.data, _resultdata_data_T_4) connect resultdata_data_2, _resultdata_data_T_5 else : connect resultdata_data_2, UInt<1>(0h0) node resultdata_is_current_q_3 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_3 : UInt<256> when resultdata_is_current_q_3 : node _resultdata_data_T_6 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_7 = dshr(Queue4_L2RespInternal_3.io.deq.bits.data, _resultdata_data_T_6) connect resultdata_data_3, _resultdata_data_T_7 else : connect resultdata_data_3, UInt<1>(0h0) node resultdata_is_current_q_4 = eq(UInt<3>(0h4), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_4 : UInt<256> when resultdata_is_current_q_4 : node _resultdata_data_T_8 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_9 = dshr(Queue4_L2RespInternal_4.io.deq.bits.data, _resultdata_data_T_8) connect resultdata_data_4, _resultdata_data_T_9 else : connect resultdata_data_4, UInt<1>(0h0) node resultdata_is_current_q_5 = eq(UInt<3>(0h5), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_5 : UInt<256> when resultdata_is_current_q_5 : node _resultdata_data_T_10 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_11 = dshr(Queue4_L2RespInternal_5.io.deq.bits.data, _resultdata_data_T_10) connect resultdata_data_5, _resultdata_data_T_11 else : connect resultdata_data_5, UInt<1>(0h0) node resultdata_is_current_q_6 = eq(UInt<3>(0h6), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_6 : UInt<256> when resultdata_is_current_q_6 : node _resultdata_data_T_12 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_13 = dshr(Queue4_L2RespInternal_6.io.deq.bits.data, _resultdata_data_T_12) connect resultdata_data_6, _resultdata_data_T_13 else : connect resultdata_data_6, UInt<1>(0h0) node resultdata_is_current_q_7 = eq(UInt<3>(0h7), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_7 : UInt<256> when resultdata_is_current_q_7 : node _resultdata_data_T_14 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_15 = dshr(Queue4_L2RespInternal_7.io.deq.bits.data, _resultdata_data_T_14) connect resultdata_data_7, _resultdata_data_T_15 else : connect resultdata_data_7, UInt<1>(0h0) node resultdata_is_current_q_8 = eq(UInt<4>(0h8), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_8 : UInt<256> when resultdata_is_current_q_8 : node _resultdata_data_T_16 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_17 = dshr(Queue4_L2RespInternal_8.io.deq.bits.data, _resultdata_data_T_16) connect resultdata_data_8, _resultdata_data_T_17 else : connect resultdata_data_8, UInt<1>(0h0) node resultdata_is_current_q_9 = eq(UInt<4>(0h9), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_9 : UInt<256> when resultdata_is_current_q_9 : node _resultdata_data_T_18 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_19 = dshr(Queue4_L2RespInternal_9.io.deq.bits.data, _resultdata_data_T_18) connect resultdata_data_9, _resultdata_data_T_19 else : connect resultdata_data_9, UInt<1>(0h0) node resultdata_is_current_q_10 = eq(UInt<4>(0ha), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_10 : UInt<256> when resultdata_is_current_q_10 : node _resultdata_data_T_20 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_21 = dshr(Queue4_L2RespInternal_10.io.deq.bits.data, _resultdata_data_T_20) connect resultdata_data_10, _resultdata_data_T_21 else : connect resultdata_data_10, UInt<1>(0h0) node resultdata_is_current_q_11 = eq(UInt<4>(0hb), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_11 : UInt<256> when resultdata_is_current_q_11 : node _resultdata_data_T_22 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_23 = dshr(Queue4_L2RespInternal_11.io.deq.bits.data, _resultdata_data_T_22) connect resultdata_data_11, _resultdata_data_T_23 else : connect resultdata_data_11, UInt<1>(0h0) node resultdata_is_current_q_12 = eq(UInt<4>(0hc), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_12 : UInt<256> when resultdata_is_current_q_12 : node _resultdata_data_T_24 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_25 = dshr(Queue4_L2RespInternal_12.io.deq.bits.data, _resultdata_data_T_24) connect resultdata_data_12, _resultdata_data_T_25 else : connect resultdata_data_12, UInt<1>(0h0) node resultdata_is_current_q_13 = eq(UInt<4>(0hd), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_13 : UInt<256> when resultdata_is_current_q_13 : node _resultdata_data_T_26 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_27 = dshr(Queue4_L2RespInternal_13.io.deq.bits.data, _resultdata_data_T_26) connect resultdata_data_13, _resultdata_data_T_27 else : connect resultdata_data_13, UInt<1>(0h0) node resultdata_is_current_q_14 = eq(UInt<4>(0he), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_14 : UInt<256> when resultdata_is_current_q_14 : node _resultdata_data_T_28 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_29 = dshr(Queue4_L2RespInternal_14.io.deq.bits.data, _resultdata_data_T_28) connect resultdata_data_14, _resultdata_data_T_29 else : connect resultdata_data_14, UInt<1>(0h0) node resultdata_is_current_q_15 = eq(UInt<4>(0hf), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_15 : UInt<256> when resultdata_is_current_q_15 : node _resultdata_data_T_30 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_31 = dshr(Queue4_L2RespInternal_15.io.deq.bits.data, _resultdata_data_T_30) connect resultdata_data_15, _resultdata_data_T_31 else : connect resultdata_data_15, UInt<1>(0h0) node resultdata_is_current_q_16 = eq(UInt<5>(0h10), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_16 : UInt<256> when resultdata_is_current_q_16 : node _resultdata_data_T_32 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_33 = dshr(Queue4_L2RespInternal_16.io.deq.bits.data, _resultdata_data_T_32) connect resultdata_data_16, _resultdata_data_T_33 else : connect resultdata_data_16, UInt<1>(0h0) node resultdata_is_current_q_17 = eq(UInt<5>(0h11), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_17 : UInt<256> when resultdata_is_current_q_17 : node _resultdata_data_T_34 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_35 = dshr(Queue4_L2RespInternal_17.io.deq.bits.data, _resultdata_data_T_34) connect resultdata_data_17, _resultdata_data_T_35 else : connect resultdata_data_17, UInt<1>(0h0) node resultdata_is_current_q_18 = eq(UInt<5>(0h12), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_18 : UInt<256> when resultdata_is_current_q_18 : node _resultdata_data_T_36 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_37 = dshr(Queue4_L2RespInternal_18.io.deq.bits.data, _resultdata_data_T_36) connect resultdata_data_18, _resultdata_data_T_37 else : connect resultdata_data_18, UInt<1>(0h0) node resultdata_is_current_q_19 = eq(UInt<5>(0h13), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_19 : UInt<256> when resultdata_is_current_q_19 : node _resultdata_data_T_38 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_39 = dshr(Queue4_L2RespInternal_19.io.deq.bits.data, _resultdata_data_T_38) connect resultdata_data_19, _resultdata_data_T_39 else : connect resultdata_data_19, UInt<1>(0h0) node resultdata_is_current_q_20 = eq(UInt<5>(0h14), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_20 : UInt<256> when resultdata_is_current_q_20 : node _resultdata_data_T_40 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_41 = dshr(Queue4_L2RespInternal_20.io.deq.bits.data, _resultdata_data_T_40) connect resultdata_data_20, _resultdata_data_T_41 else : connect resultdata_data_20, UInt<1>(0h0) node resultdata_is_current_q_21 = eq(UInt<5>(0h15), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_21 : UInt<256> when resultdata_is_current_q_21 : node _resultdata_data_T_42 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_43 = dshr(Queue4_L2RespInternal_21.io.deq.bits.data, _resultdata_data_T_42) connect resultdata_data_21, _resultdata_data_T_43 else : connect resultdata_data_21, UInt<1>(0h0) node resultdata_is_current_q_22 = eq(UInt<5>(0h16), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_22 : UInt<256> when resultdata_is_current_q_22 : node _resultdata_data_T_44 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_45 = dshr(Queue4_L2RespInternal_22.io.deq.bits.data, _resultdata_data_T_44) connect resultdata_data_22, _resultdata_data_T_45 else : connect resultdata_data_22, UInt<1>(0h0) node resultdata_is_current_q_23 = eq(UInt<5>(0h17), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_23 : UInt<256> when resultdata_is_current_q_23 : node _resultdata_data_T_46 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_47 = dshr(Queue4_L2RespInternal_23.io.deq.bits.data, _resultdata_data_T_46) connect resultdata_data_23, _resultdata_data_T_47 else : connect resultdata_data_23, UInt<1>(0h0) node resultdata_is_current_q_24 = eq(UInt<5>(0h18), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_24 : UInt<256> when resultdata_is_current_q_24 : node _resultdata_data_T_48 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_49 = dshr(Queue4_L2RespInternal_24.io.deq.bits.data, _resultdata_data_T_48) connect resultdata_data_24, _resultdata_data_T_49 else : connect resultdata_data_24, UInt<1>(0h0) node resultdata_is_current_q_25 = eq(UInt<5>(0h19), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_25 : UInt<256> when resultdata_is_current_q_25 : node _resultdata_data_T_50 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_51 = dshr(Queue4_L2RespInternal_25.io.deq.bits.data, _resultdata_data_T_50) connect resultdata_data_25, _resultdata_data_T_51 else : connect resultdata_data_25, UInt<1>(0h0) node resultdata_is_current_q_26 = eq(UInt<5>(0h1a), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_26 : UInt<256> when resultdata_is_current_q_26 : node _resultdata_data_T_52 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_53 = dshr(Queue4_L2RespInternal_26.io.deq.bits.data, _resultdata_data_T_52) connect resultdata_data_26, _resultdata_data_T_53 else : connect resultdata_data_26, UInt<1>(0h0) node resultdata_is_current_q_27 = eq(UInt<5>(0h1b), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_27 : UInt<256> when resultdata_is_current_q_27 : node _resultdata_data_T_54 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_55 = dshr(Queue4_L2RespInternal_27.io.deq.bits.data, _resultdata_data_T_54) connect resultdata_data_27, _resultdata_data_T_55 else : connect resultdata_data_27, UInt<1>(0h0) node resultdata_is_current_q_28 = eq(UInt<5>(0h1c), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_28 : UInt<256> when resultdata_is_current_q_28 : node _resultdata_data_T_56 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_57 = dshr(Queue4_L2RespInternal_28.io.deq.bits.data, _resultdata_data_T_56) connect resultdata_data_28, _resultdata_data_T_57 else : connect resultdata_data_28, UInt<1>(0h0) node resultdata_is_current_q_29 = eq(UInt<5>(0h1d), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_29 : UInt<256> when resultdata_is_current_q_29 : node _resultdata_data_T_58 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_59 = dshr(Queue4_L2RespInternal_29.io.deq.bits.data, _resultdata_data_T_58) connect resultdata_data_29, _resultdata_data_T_59 else : connect resultdata_data_29, UInt<1>(0h0) node resultdata_is_current_q_30 = eq(UInt<5>(0h1e), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_30 : UInt<256> when resultdata_is_current_q_30 : node _resultdata_data_T_60 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_61 = dshr(Queue4_L2RespInternal_30.io.deq.bits.data, _resultdata_data_T_60) connect resultdata_data_30, _resultdata_data_T_61 else : connect resultdata_data_30, UInt<1>(0h0) node resultdata_is_current_q_31 = eq(UInt<5>(0h1f), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_31 : UInt<256> when resultdata_is_current_q_31 : node _resultdata_data_T_62 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_63 = dshr(Queue4_L2RespInternal_31.io.deq.bits.data, _resultdata_data_T_62) connect resultdata_data_31, _resultdata_data_T_63 else : connect resultdata_data_31, UInt<1>(0h0) node _resultdata_T = or(resultdata_data, resultdata_data_1) node _resultdata_T_1 = or(_resultdata_T, resultdata_data_2) node _resultdata_T_2 = or(_resultdata_T_1, resultdata_data_3) node _resultdata_T_3 = or(_resultdata_T_2, resultdata_data_4) node _resultdata_T_4 = or(_resultdata_T_3, resultdata_data_5) node _resultdata_T_5 = or(_resultdata_T_4, resultdata_data_6) node _resultdata_T_6 = or(_resultdata_T_5, resultdata_data_7) node _resultdata_T_7 = or(_resultdata_T_6, resultdata_data_8) node _resultdata_T_8 = or(_resultdata_T_7, resultdata_data_9) node _resultdata_T_9 = or(_resultdata_T_8, resultdata_data_10) node _resultdata_T_10 = or(_resultdata_T_9, resultdata_data_11) node _resultdata_T_11 = or(_resultdata_T_10, resultdata_data_12) node _resultdata_T_12 = or(_resultdata_T_11, resultdata_data_13) node _resultdata_T_13 = or(_resultdata_T_12, resultdata_data_14) node _resultdata_T_14 = or(_resultdata_T_13, resultdata_data_15) node _resultdata_T_15 = or(_resultdata_T_14, resultdata_data_16) node _resultdata_T_16 = or(_resultdata_T_15, resultdata_data_17) node _resultdata_T_17 = or(_resultdata_T_16, resultdata_data_18) node _resultdata_T_18 = or(_resultdata_T_17, resultdata_data_19) node _resultdata_T_19 = or(_resultdata_T_18, resultdata_data_20) node _resultdata_T_20 = or(_resultdata_T_19, resultdata_data_21) node _resultdata_T_21 = or(_resultdata_T_20, resultdata_data_22) node _resultdata_T_22 = or(_resultdata_T_21, resultdata_data_23) node _resultdata_T_23 = or(_resultdata_T_22, resultdata_data_24) node _resultdata_T_24 = or(_resultdata_T_23, resultdata_data_25) node _resultdata_T_25 = or(_resultdata_T_24, resultdata_data_26) node _resultdata_T_26 = or(_resultdata_T_25, resultdata_data_27) node _resultdata_T_27 = or(_resultdata_T_26, resultdata_data_28) node _resultdata_T_28 = or(_resultdata_T_27, resultdata_data_29) node _resultdata_T_29 = or(_resultdata_T_28, resultdata_data_30) node resultdata = or(_resultdata_T_29, resultdata_data_31) connect response_output.bits.data, resultdata node _response_output_valid_T = and(queueValid, outstanding_req_addr.io.deq.valid) connect response_output.valid, _response_output_valid_T node _outstanding_req_addr_io_deq_ready_T = and(queueValid, response_output.ready) connect outstanding_req_addr.io.deq.ready, _outstanding_req_addr_io_deq_ready_T node _T_159 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_160 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) connect Queue4_L2RespInternal.io.deq.ready, _T_161 node _T_162 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_163 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h1)) node _T_164 = and(_T_162, _T_163) connect Queue4_L2RespInternal_1.io.deq.ready, _T_164 node _T_165 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_166 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h2)) node _T_167 = and(_T_165, _T_166) connect Queue4_L2RespInternal_2.io.deq.ready, _T_167 node _T_168 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_169 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h3)) node _T_170 = and(_T_168, _T_169) connect Queue4_L2RespInternal_3.io.deq.ready, _T_170 node _T_171 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_172 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h4)) node _T_173 = and(_T_171, _T_172) connect Queue4_L2RespInternal_4.io.deq.ready, _T_173 node _T_174 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_175 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h5)) node _T_176 = and(_T_174, _T_175) connect Queue4_L2RespInternal_5.io.deq.ready, _T_176 node _T_177 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_178 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h6)) node _T_179 = and(_T_177, _T_178) connect Queue4_L2RespInternal_6.io.deq.ready, _T_179 node _T_180 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_181 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h7)) node _T_182 = and(_T_180, _T_181) connect Queue4_L2RespInternal_7.io.deq.ready, _T_182 node _T_183 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_184 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0h8)) node _T_185 = and(_T_183, _T_184) connect Queue4_L2RespInternal_8.io.deq.ready, _T_185 node _T_186 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_187 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0h9)) node _T_188 = and(_T_186, _T_187) connect Queue4_L2RespInternal_9.io.deq.ready, _T_188 node _T_189 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_190 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0ha)) node _T_191 = and(_T_189, _T_190) connect Queue4_L2RespInternal_10.io.deq.ready, _T_191 node _T_192 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_193 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hb)) node _T_194 = and(_T_192, _T_193) connect Queue4_L2RespInternal_11.io.deq.ready, _T_194 node _T_195 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_196 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hc)) node _T_197 = and(_T_195, _T_196) connect Queue4_L2RespInternal_12.io.deq.ready, _T_197 node _T_198 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_199 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hd)) node _T_200 = and(_T_198, _T_199) connect Queue4_L2RespInternal_13.io.deq.ready, _T_200 node _T_201 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_202 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0he)) node _T_203 = and(_T_201, _T_202) connect Queue4_L2RespInternal_14.io.deq.ready, _T_203 node _T_204 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_205 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hf)) node _T_206 = and(_T_204, _T_205) connect Queue4_L2RespInternal_15.io.deq.ready, _T_206 node _T_207 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_208 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h10)) node _T_209 = and(_T_207, _T_208) connect Queue4_L2RespInternal_16.io.deq.ready, _T_209 node _T_210 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_211 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h11)) node _T_212 = and(_T_210, _T_211) connect Queue4_L2RespInternal_17.io.deq.ready, _T_212 node _T_213 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_214 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h12)) node _T_215 = and(_T_213, _T_214) connect Queue4_L2RespInternal_18.io.deq.ready, _T_215 node _T_216 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_217 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h13)) node _T_218 = and(_T_216, _T_217) connect Queue4_L2RespInternal_19.io.deq.ready, _T_218 node _T_219 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_220 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h14)) node _T_221 = and(_T_219, _T_220) connect Queue4_L2RespInternal_20.io.deq.ready, _T_221 node _T_222 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_223 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h15)) node _T_224 = and(_T_222, _T_223) connect Queue4_L2RespInternal_21.io.deq.ready, _T_224 node _T_225 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_226 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h16)) node _T_227 = and(_T_225, _T_226) connect Queue4_L2RespInternal_22.io.deq.ready, _T_227 node _T_228 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_229 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h17)) node _T_230 = and(_T_228, _T_229) connect Queue4_L2RespInternal_23.io.deq.ready, _T_230 node _T_231 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_232 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h18)) node _T_233 = and(_T_231, _T_232) connect Queue4_L2RespInternal_24.io.deq.ready, _T_233 node _T_234 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_235 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h19)) node _T_236 = and(_T_234, _T_235) connect Queue4_L2RespInternal_25.io.deq.ready, _T_236 node _T_237 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_238 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1a)) node _T_239 = and(_T_237, _T_238) connect Queue4_L2RespInternal_26.io.deq.ready, _T_239 node _T_240 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_241 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1b)) node _T_242 = and(_T_240, _T_241) connect Queue4_L2RespInternal_27.io.deq.ready, _T_242 node _T_243 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_244 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1c)) node _T_245 = and(_T_243, _T_244) connect Queue4_L2RespInternal_28.io.deq.ready, _T_245 node _T_246 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_247 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1d)) node _T_248 = and(_T_246, _T_247) connect Queue4_L2RespInternal_29.io.deq.ready, _T_248 node _T_249 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_250 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1e)) node _T_251 = and(_T_249, _T_250) connect Queue4_L2RespInternal_30.io.deq.ready, _T_251 node _T_252 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_253 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1f)) node _T_254 = and(_T_252, _T_253) connect Queue4_L2RespInternal_31.io.deq.ready, _T_254 node _T_255 = and(masterNodeOut.d.ready, masterNodeOut.d.valid) when _T_255 : node opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) when opdata : regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_21 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n", masterNodeOut.d.bits.data, global_memop_ackd, masterNodeOut.d.bits.source) : printf_22 else : regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_23 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: resp(write) opnum: %d, gettag: %d\n", global_memop_ackd, masterNodeOut.d.bits.source) : printf_24 node _T_264 = and(response_output.ready, response_output.valid) when _T_264 : regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_25 node _T_267 = asUInt(reset) node _T_268 = eq(_T_267, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n", resultdata, global_memop_resp_to_user, outstanding_req_addr.io.deq.bits.tag) : printf_26 node _T_269 = and(response_latency_injection_q.io.deq.ready, response_latency_injection_q.io.deq.valid) when _T_269 : node _global_memop_ackd_T = add(global_memop_ackd, UInt<1>(0h1)) node _global_memop_ackd_T_1 = tail(_global_memop_ackd_T, 1) connect global_memop_ackd, _global_memop_ackd_T_1 node _T_270 = and(response_output.ready, response_output.valid) when _T_270 : node _global_memop_resp_to_user_T = add(global_memop_resp_to_user, UInt<1>(0h1)) node _global_memop_resp_to_user_T_1 = tail(_global_memop_resp_to_user_T, 1) connect global_memop_resp_to_user, _global_memop_resp_to_user_T_1 extmodule plusarg_reader_144 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_145 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module L2MemHelperLatencyInjection_14( // @[L2MemHelperLatencyInjection.scala:29:7] input clock, // @[L2MemHelperLatencyInjection.scala:29:7] input reset, // @[L2MemHelperLatencyInjection.scala:29:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_master_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_master_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [255:0] auto_master_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_master_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [255:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_userif_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [70:0] io_userif_req_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_resp_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [255:0] io_userif_resp_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_no_memops_inflight, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_latency_inject_cycles, // @[L2MemHelperLatencyInjection.scala:33:14] input io_sfence, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [26:0] io_ptw_req_bits_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_bits_bits_need_gpa, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_ptw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_final, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hx, // @[L2MemHelperLatencyInjection.scala:33:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_d, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_g, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_u, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_r, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_level, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_homogeneous, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_is_pte, // @[L2MemHelperLatencyInjection.scala:33:14] input [3:0] io_ptw_ptbr_mode, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_ptbr_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_status_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spvp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_gstatus_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_ptw_gstatus_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_ptw_gstatus_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_uie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_0_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_0_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_1_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_1_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_2_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_2_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_3_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_3_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_4_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_4_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_5_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_5_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_6_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_6_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_7_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_7_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_status_bits_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_status_bits_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_uxl, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd_rv32, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_status_bits_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_xs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_uie // @[L2MemHelperLatencyInjection.scala:33:14] ); wire _response_latency_injection_q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:245:44] wire [4:0] _response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44] wire [255:0] _response_latency_injection_q_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:245:44] wire _Queue4_L2RespInternal_31_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_31_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_31_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_30_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_29_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_28_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_27_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_26_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_25_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_24_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_23_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_22_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_21_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_20_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_19_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_18_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_17_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_16_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_15_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_14_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_13_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_12_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_11_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_10_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_9_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_8_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_7_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_6_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_5_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_4_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_3_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_2_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_1_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _request_latency_injection_q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:151:43] wire _tags_for_issue_Q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:94:32] wire _tags_for_issue_Q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:94:32] wire [4:0] _tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32] wire _outstanding_req_addr_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:91:36] wire _outstanding_req_addr_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_addrindex; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36] wire _tlb_io_req_ready; // @[L2MemHelperLatencyInjection.scala:68:19] wire _tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19] wire [31:0] _tlb_io_resp_paddr; // @[L2MemHelperLatencyInjection.scala:68:19] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_valid_0 = io_userif_req_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [70:0] io_userif_req_bits_addr_0 = io_userif_req_bits_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_ready_0 = io_userif_resp_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_latency_inject_cycles_0 = io_latency_inject_cycles; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_sfence_0 = io_sfence; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[L2MemHelperLatencyInjection.scala:29:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_valid_0 = io_status_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_debug_0 = io_status_bits_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_cease_0 = io_status_bits_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_wfi_0 = io_status_bits_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_status_bits_isa_0 = io_status_bits_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_dprv_0 = io_status_bits_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_dv_0 = io_status_bits_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_prv_0 = io_status_bits_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_v_0 = io_status_bits_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_0 = io_status_bits_sd; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_status_bits_zero2_0 = io_status_bits_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpv_0 = io_status_bits_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_gva_0 = io_status_bits_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mbe_0 = io_status_bits_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sbe_0 = io_status_bits_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_sxl_0 = io_status_bits_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_uxl_0 = io_status_bits_uxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_rv32_0 = io_status_bits_sd_rv32; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_status_bits_zero1_0 = io_status_bits_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tsr_0 = io_status_bits_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tw_0 = io_status_bits_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tvm_0 = io_status_bits_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mxr_0 = io_status_bits_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sum_0 = io_status_bits_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mprv_0 = io_status_bits_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_xs_0 = io_status_bits_xs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_fs_0 = io_status_bits_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_mpp_0 = io_status_bits_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_vs_0 = io_status_bits_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spp_0 = io_status_bits_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpie_0 = io_status_bits_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_ube_0 = io_status_bits_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spie_0 = io_status_bits_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_upie_0 = io_status_bits_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mie_0 = io_status_bits_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_hie_0 = io_status_bits_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sie_0 = io_status_bits_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_uie_0 = io_status_bits_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire _printf_T = reset; // @[annotations.scala:102:49] wire _printf_T_2 = reset; // @[annotations.scala:102:49] wire io_userif_req_bits_cmd = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_ube = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_upie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_hie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_uie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtw = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_hu = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire request_input_bits_cmd = 1'h0; // @[L2MemHelperLatencyInjection.scala:44:27] wire bundle_corrupt = 1'h0; // @[Edges.scala:460:17] wire a_mask_sub_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_T_125 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_131 = 1'h0; // @[Parameters.scala:684:54] wire bundle_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire a_mask_sub_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_acc_T_16 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_17 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_18 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_19 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_20 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_21 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_22 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_23 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_24 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_25 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_26 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_27 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_28 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_29 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_30 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_31 = 1'h0; // @[Misc.scala:215:38] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_valid = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_8_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_9_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_10_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_11_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_12_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_13_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_14_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_15_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_64 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_65 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_66 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_73 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_74 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_75 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_76 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_8_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_9_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_10_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_11_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_12_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_13_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_14_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_15_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc_32 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_33 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_34 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_35 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_36 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_37 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_38 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_39 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_40 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_41 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_42 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_43 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_44 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_45 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_46 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_47 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_48 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_49 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_50 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_51 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_52 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_53 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_54 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_55 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_56 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_57 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_58 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_59 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_60 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_61 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_62 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_63 = 1'h1; // @[Misc.scala:215:29] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] a_mask_lo_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_ptw_status_vs = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] _a_mask_sizeOH_T_2 = 5'h0; // @[OneHot.scala:65:27] wire [4:0] _a_mask_sizeOH_T_5 = 5'h0; // @[OneHot.scala:65:27] wire [2:0] io_userif_req_bits_size = 3'h5; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] request_input_bits_size = 3'h5; // @[L2MemHelperLatencyInjection.scala:44:27] wire [2:0] a_mask_sizeOH_shiftAmount = 3'h5; // @[OneHot.scala:64:49] wire [2:0] a_mask_sizeOH_shiftAmount_1 = 3'h5; // @[OneHot.scala:64:49] wire [255:0] io_userif_req_bits_data = 256'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] request_input_bits_data = 256'h0; // @[L2MemHelperLatencyInjection.scala:44:27] wire [255:0] bundle_data = 256'h0; // @[Edges.scala:460:17] wire [1:0] io_ptw_status_sxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] bundle_mask = 32'hFFFFFFFF; // @[Edges.scala:460:17] wire [31:0] _a_mask_T = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [31:0] bundle_1_mask = 32'hFFFFFFFF; // @[Edges.scala:480:17] wire [31:0] _a_mask_T_1 = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_lo = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_hi = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_lo_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_hi_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [4:0] a_mask_sizeOH = 5'h1; // @[Misc.scala:202:81] wire [4:0] a_mask_sizeOH_1 = 5'h1; // @[Misc.scala:202:81] wire [7:0] _a_mask_sizeOH_T_1 = 8'h20; // @[OneHot.scala:65:12] wire [7:0] _a_mask_sizeOH_T_4 = 8'h20; // @[OneHot.scala:65:12] wire [4:0] _a_mask_sizeOH_T = 5'h5; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T = 5'h5; // @[OneHot.scala:64:31] wire [4:0] _a_mask_sizeOH_T_3 = 5'h5; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T_1 = 5'h5; // @[OneHot.scala:64:31] wire [3:0] bundle_size = 4'h5; // @[Edges.scala:460:17] wire [3:0] bundle_1_size = 4'h5; // @[Edges.scala:480:17] wire [2:0] bundle_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] bundle_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_1_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_opcode = 3'h4; // @[Edges.scala:460:17] wire [70:0] addr_mask_check = 71'h1F; // @[L2MemHelperLatencyInjection.scala:108:64] wire [71:0] _addr_mask_check_T_1 = 72'h1F; // @[L2MemHelperLatencyInjection.scala:108:64] wire [70:0] _addr_mask_check_T = 71'h20; // @[L2MemHelperLatencyInjection.scala:108:36] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire request_input_ready; // @[L2MemHelperLatencyInjection.scala:44:27] wire request_input_valid = io_userif_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [70:0] request_input_bits_addr = io_userif_req_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire response_output_ready = io_userif_resp_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire response_output_valid; // @[L2MemHelperLatencyInjection.scala:53:29] wire [255:0] response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:53:29] wire _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:128:57] wire [2:0] auto_master_out_a_bits_opcode_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_a_bits_param_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_a_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_a_bits_source_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_address_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_mask_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_a_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_bits_corrupt_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_resp_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_no_memops_inflight_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_opcode_0 = masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_param_0 = masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_size_0 = masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_source_0 = masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_mask_0 = masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_data_0 = masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_corrupt_0 = masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_master_out_d_ready_0 = masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire _request_input_ready_T_4; // @[Misc.scala:26:53] assign io_userif_req_ready_0 = request_input_ready; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire _response_output_valid_T; // @[Misc.scala:26:53] assign io_userif_resp_valid_0 = response_output_valid; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire [255:0] resultdata; // @[L2MemHelperLatencyInjection.scala:307:15] assign io_userif_resp_bits_data_0 = response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] reg status_debug; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_cease; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_wfi; // @[L2MemHelperLatencyInjection.scala:62:19] reg [31:0] status_isa; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_dprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_dv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_prv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_v; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd; // @[L2MemHelperLatencyInjection.scala:62:19] reg [22:0] status_zero2; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_gva; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_sxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_uxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd_rv32; // @[L2MemHelperLatencyInjection.scala:62:19] reg [7:0] status_zero1; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tsr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tw; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tvm; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mxr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sum; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_xs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_fs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_mpp; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_vs; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spp; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_ube; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_upie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_hie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_uie; // @[L2MemHelperLatencyInjection.scala:62:19] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _tlb_ready_T = ~_tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19, :74:39] wire tlb_ready = _tlb_io_req_ready & _tlb_ready_T; // @[L2MemHelperLatencyInjection.scala:68:19, :74:{36,39}] reg [5:0] tags_init_reg; // @[L2MemHelperLatencyInjection.scala:98:30] wire _T_4 = tags_init_reg != 6'h20; // @[L2MemHelperLatencyInjection.scala:98:30, :99:23] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] wire [6:0] _tags_init_reg_T = {1'h0, tags_init_reg} + 7'h1; // @[L2MemHelperLatencyInjection.scala:98:30, :104:38] wire [5:0] _tags_init_reg_T_1 = _tags_init_reg_T[5:0]; // @[L2MemHelperLatencyInjection.scala:104:38] wire _assertcheck_T = ~request_input_valid; // @[L2MemHelperLatencyInjection.scala:44:27, :109:30] wire [70:0] _assertcheck_T_1 = request_input_bits_addr & 71'h1F; // @[L2MemHelperLatencyInjection.scala:44:27, :109:81] wire _assertcheck_T_2 = _assertcheck_T_1 == 71'h0; // @[L2MemHelperLatencyInjection.scala:109:{81,100}] wire _assertcheck_T_3 = _assertcheck_T \| _assertcheck_T_2; // @[L2MemHelperLatencyInjection.scala:109:{30,52,100}] reg assertcheck; // @[L2MemHelperLatencyInjection.scala:109:28] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] global_memop_accepted; // @[L2MemHelperLatencyInjection.scala:117:38] wire [64:0] _global_memop_accepted_T = {1'h0, global_memop_accepted} + 65'h1; // @[L2MemHelperLatencyInjection.scala:117:38, :119:52] wire [63:0] _global_memop_accepted_T_1 = _global_memop_accepted_T[63:0]; // @[L2MemHelperLatencyInjection.scala:119:52] reg [63:0] global_memop_sent; // @[L2MemHelperLatencyInjection.scala:122:34] reg [63:0] global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:124:34] reg [63:0] global_memop_resp_to_user; // @[L2MemHelperLatencyInjection.scala:126:42] assign _io_userif_no_memops_inflight_T = global_memop_accepted == global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:117:38, :124:34, :128:57] assign io_userif_no_memops_inflight_0 = _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:29:7, :128:57] wire [64:0] _GEN = {1'h0, global_memop_sent}; // @[L2MemHelperLatencyInjection.scala:122:34, :130:54] wire [64:0] _GEN_0 = {1'h0, global_memop_ackd}; // @[L2MemHelperLatencyInjection.scala:124:34, :130:54] wire [64:0] _GEN_1 = _GEN - _GEN_0; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:130:54] assign _free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _assert_free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:131:61] assign _assert_free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54, :131:61] wire [63:0] _free_outstanding_op_slots_T_1 = _free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:130:54] wire free_outstanding_op_slots = _free_outstanding_op_slots_T_1 < 64'h20; // @[L2MemHelperLatencyInjection.scala:130:{54,75}] wire [63:0] _assert_free_outstanding_op_slots_T_1 = _assert_free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:131:61] wire assert_free_outstanding_op_slots = _assert_free_outstanding_op_slots_T_1 < 64'h21; // @[L2MemHelperLatencyInjection.scala:131:{61,82}] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] wire [64:0] _global_memop_sent_T = _GEN + 65'h1; // @[L2MemHelperLatencyInjection.scala:130:54, :140:44] wire [63:0] _global_memop_sent_T_1 = _global_memop_sent_T[63:0]; // @[L2MemHelperLatencyInjection.scala:140:44] reg [63:0] cur_cycle; // @[L2MemHelperLatencyInjection.scala:146:26] wire [64:0] _cur_cycle_T = {1'h0, cur_cycle} + 65'h1; // @[L2MemHelperLatencyInjection.scala:146:26, :147:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[L2MemHelperLatencyInjection.scala:147:26] wire [31:0] _GEN_2 = {_tlb_io_resp_paddr[31:14], _tlb_io_resp_paddr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_4; // @[Parameters.scala:137:31] assign _legal_T_4 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _legal_T_67; // @[Parameters.scala:137:31] assign _legal_T_67 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_62 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [31:0] _legal_T_14; // @[Parameters.scala:137:31] wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_16 = _legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46] wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {_tlb_io_resp_paddr[31:17], _tlb_io_resp_paddr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_19; // @[Parameters.scala:137:31] assign _legal_T_19 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _legal_T_24; // @[Parameters.scala:137:31] assign _legal_T_24 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _legal_T_126; // @[Parameters.scala:137:31] assign _legal_T_126 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_21 = _legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46] wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_26 = _legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46] wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_29; // @[Parameters.scala:137:31] assign _legal_T_29 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_87; // @[Parameters.scala:137:31] assign _legal_T_87 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_31 = _legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46] wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_5 = {_tlb_io_resp_paddr[31:28], _tlb_io_resp_paddr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_34; // @[Parameters.scala:137:31] assign _legal_T_34 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_39; // @[Parameters.scala:137:31] assign _legal_T_39 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_97; // @[Parameters.scala:137:31] assign _legal_T_97 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_102; // @[Parameters.scala:137:31] assign _legal_T_102 = _GEN_5; // @[Parameters.scala:137:31] wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_36 = _legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46] wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_41 = _legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46] wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_6 = {_tlb_io_resp_paddr[31:29], _tlb_io_resp_paddr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_44; // @[Parameters.scala:137:31] assign _legal_T_44 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_107; // @[Parameters.scala:137:31] assign _legal_T_107 = _GEN_6; // @[Parameters.scala:137:31] wire [32:0] _legal_T_45 = {1'h0, _legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_46 = _legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_47 = _legal_T_46; // @[Parameters.scala:137:46] wire _legal_T_48 = _legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_7 = _tlb_io_resp_paddr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _legal_T_49; // @[Parameters.scala:137:31] assign _legal_T_49 = _GEN_7; // @[Parameters.scala:137:31] wire [31:0] _legal_T_112; // @[Parameters.scala:137:31] assign _legal_T_112 = _GEN_7; // @[Parameters.scala:137:31] wire [32:0] _legal_T_50 = {1'h0, _legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_51 = _legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_52 = _legal_T_51; // @[Parameters.scala:137:46] wire _legal_T_53 = _legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_54 = _legal_T_18 \| _legal_T_23; // @[Parameters.scala:685:42] wire _legal_T_55 = _legal_T_54 \| _legal_T_28; // @[Parameters.scala:685:42] wire _legal_T_56 = _legal_T_55 \| _legal_T_33; // @[Parameters.scala:685:42] wire _legal_T_57 = _legal_T_56 \| _legal_T_38; // @[Parameters.scala:685:42] wire _legal_T_58 = _legal_T_57 \| _legal_T_43; // @[Parameters.scala:685:42] wire _legal_T_59 = _legal_T_58 \| _legal_T_48; // @[Parameters.scala:685:42] wire _legal_T_60 = _legal_T_59 \| _legal_T_53; // @[Parameters.scala:685:42] wire _legal_T_61 = _legal_T_60; // @[Parameters.scala:684:54, :685:42] wire legal = _legal_T_62 \| _legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [4:0] bundle_source; // @[Edges.scala:460:17] wire [31:0] bundle_address; // @[Edges.scala:460:17] wire a_mask_sub_sub_sub_sub_bit = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_bit = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_2_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_3_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_bit = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_bit_1 = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_1_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_2_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_3_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_4_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_5_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_6_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_7_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_bit = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_bit_1 = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_4_2 = a_mask_sub_sub_2_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_5_2 = a_mask_sub_sub_2_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_6_2 = a_mask_sub_sub_3_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_7_2 = a_mask_sub_sub_3_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_8_2 = a_mask_sub_sub_4_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_9_2 = a_mask_sub_sub_4_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_10_2 = a_mask_sub_sub_5_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_11_2 = a_mask_sub_sub_5_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_12_2 = a_mask_sub_sub_6_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_13_2 = a_mask_sub_sub_6_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_14_2 = a_mask_sub_sub_7_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_15_2 = a_mask_sub_sub_7_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_bit = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_bit_1 = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_eq; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_8 = a_mask_sub_4_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_8 = a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_9 = a_mask_sub_4_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_9 = a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_10 = a_mask_sub_5_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_10 = a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_11 = a_mask_sub_5_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_11 = a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_12 = a_mask_sub_6_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_12 = a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_13 = a_mask_sub_6_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_13 = a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_14 = a_mask_sub_7_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_14 = a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_15 = a_mask_sub_7_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_15 = a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_16 = a_mask_sub_8_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_16 = a_mask_eq_16; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_17 = a_mask_sub_8_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_17 = a_mask_eq_17; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_18 = a_mask_sub_9_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_18 = a_mask_eq_18; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_19 = a_mask_sub_9_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_19 = a_mask_eq_19; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_20 = a_mask_sub_10_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_20 = a_mask_eq_20; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_21 = a_mask_sub_10_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_21 = a_mask_eq_21; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_22 = a_mask_sub_11_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_22 = a_mask_eq_22; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_23 = a_mask_sub_11_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_23 = a_mask_eq_23; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_24 = a_mask_sub_12_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_24 = a_mask_eq_24; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_25 = a_mask_sub_12_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_25 = a_mask_eq_25; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_26 = a_mask_sub_13_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_26 = a_mask_eq_26; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_27 = a_mask_sub_13_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_27 = a_mask_eq_27; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_28 = a_mask_sub_14_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_28 = a_mask_eq_28; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_29 = a_mask_sub_14_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_29 = a_mask_eq_29; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_30 = a_mask_sub_15_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_30 = a_mask_eq_30; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_31 = a_mask_sub_15_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_31 = a_mask_eq_31; // @[Misc.scala:214:27, :215:38] wire [510:0] _T_31 = 511'h0 << {503'h0, request_input_bits_addr[4:0], 3'h0}; // @[L2MemHelperLatencyInjection.scala:44:27, :172:{58,86}] wire [32:0] _legal_T_68 = {1'h0, _legal_T_67}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_69 = _legal_T_68 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_70 = _legal_T_69; // @[Parameters.scala:137:46] wire _legal_T_71 = _legal_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_72 = _legal_T_71; // @[Parameters.scala:684:54] wire _legal_T_132 = _legal_T_72; // @[Parameters.scala:684:54, :686:26] wire [31:0] _legal_T_77; // @[Parameters.scala:137:31] wire [32:0] _legal_T_78 = {1'h0, _legal_T_77}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_79 = _legal_T_78 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_80 = _legal_T_79; // @[Parameters.scala:137:46] wire _legal_T_81 = _legal_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_82 = {_tlb_io_resp_paddr[31:21], _tlb_io_resp_paddr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_83 = {1'h0, _legal_T_82}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_84 = _legal_T_83 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_85 = _legal_T_84; // @[Parameters.scala:137:46] wire _legal_T_86 = _legal_T_85 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_88 = {1'h0, _legal_T_87}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_89 = _legal_T_88 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_90 = _legal_T_89; // @[Parameters.scala:137:46] wire _legal_T_91 = _legal_T_90 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_92 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_93 = {1'h0, _legal_T_92}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_94 = _legal_T_93 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_95 = _legal_T_94; // @[Parameters.scala:137:46] wire _legal_T_96 = _legal_T_95 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_98 = {1'h0, _legal_T_97}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_99 = _legal_T_98 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_100 = _legal_T_99; // @[Parameters.scala:137:46] wire _legal_T_101 = _legal_T_100 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_103 = {1'h0, _legal_T_102}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_104 = _legal_T_103 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_105 = _legal_T_104; // @[Parameters.scala:137:46] wire _legal_T_106 = _legal_T_105 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_108 = {1'h0, _legal_T_107}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_109 = _legal_T_108 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_110 = _legal_T_109; // @[Parameters.scala:137:46] wire _legal_T_111 = _legal_T_110 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_113 = {1'h0, _legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_114 = _legal_T_113 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_115 = _legal_T_114; // @[Parameters.scala:137:46] wire _legal_T_116 = _legal_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_117 = _legal_T_81 \| _legal_T_86; // @[Parameters.scala:685:42] wire _legal_T_118 = _legal_T_117 \| _legal_T_91; // @[Parameters.scala:685:42] wire _legal_T_119 = _legal_T_118 \| _legal_T_96; // @[Parameters.scala:685:42] wire _legal_T_120 = _legal_T_119 \| _legal_T_101; // @[Parameters.scala:685:42] wire _legal_T_121 = _legal_T_120 \| _legal_T_106; // @[Parameters.scala:685:42] wire _legal_T_122 = _legal_T_121 \| _legal_T_111; // @[Parameters.scala:685:42] wire _legal_T_123 = _legal_T_122 \| _legal_T_116; // @[Parameters.scala:685:42] wire _legal_T_124 = _legal_T_123; // @[Parameters.scala:684:54, :685:42] wire [32:0] _legal_T_127 = {1'h0, _legal_T_126}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_128 = _legal_T_127 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_129 = _legal_T_128; // @[Parameters.scala:137:46] wire _legal_T_130 = _legal_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_133 = _legal_T_132 \| _legal_T_124; // @[Parameters.scala:684:54, :686:26] wire legal_1 = _legal_T_133; // @[Parameters.scala:686:26] wire [4:0] bundle_1_source; // @[Edges.scala:480:17] wire [31:0] bundle_1_address; // @[Edges.scala:480:17] wire [255:0] bundle_1_data; // @[Edges.scala:480:17] wire a_mask_sub_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_2_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_3_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_nbit_1 = ~a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_1_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_2_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_3_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_4_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_5_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_6_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_7_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_1_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_2_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_3_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_4_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_5_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_6_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_7_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_8_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_9_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_10_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_11_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_12_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_13_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_14_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_15_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_eq_32 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_32 = a_mask_eq_32; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_33 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_33 = a_mask_eq_33; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_34 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_34 = a_mask_eq_34; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_35 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_35 = a_mask_eq_35; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_36 = a_mask_sub_2_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_36 = a_mask_eq_36; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_37 = a_mask_sub_2_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_37 = a_mask_eq_37; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_38 = a_mask_sub_3_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_38 = a_mask_eq_38; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_39 = a_mask_sub_3_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_39 = a_mask_eq_39; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_40 = a_mask_sub_4_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_40 = a_mask_eq_40; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_41 = a_mask_sub_4_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_41 = a_mask_eq_41; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_42 = a_mask_sub_5_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_42 = a_mask_eq_42; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_43 = a_mask_sub_5_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_43 = a_mask_eq_43; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_44 = a_mask_sub_6_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_44 = a_mask_eq_44; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_45 = a_mask_sub_6_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_45 = a_mask_eq_45; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_46 = a_mask_sub_7_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_46 = a_mask_eq_46; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_47 = a_mask_sub_7_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_47 = a_mask_eq_47; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_48 = a_mask_sub_8_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_48 = a_mask_eq_48; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_49 = a_mask_sub_8_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_49 = a_mask_eq_49; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_50 = a_mask_sub_9_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_50 = a_mask_eq_50; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_51 = a_mask_sub_9_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_51 = a_mask_eq_51; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_52 = a_mask_sub_10_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_52 = a_mask_eq_52; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_53 = a_mask_sub_10_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_53 = a_mask_eq_53; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_54 = a_mask_sub_11_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_54 = a_mask_eq_54; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_55 = a_mask_sub_11_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_55 = a_mask_eq_55; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_56 = a_mask_sub_12_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_56 = a_mask_eq_56; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_57 = a_mask_sub_12_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_57 = a_mask_eq_57; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_58 = a_mask_sub_13_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_58 = a_mask_eq_58; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_59 = a_mask_sub_13_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_59 = a_mask_eq_59; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_60 = a_mask_sub_14_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_60 = a_mask_eq_60; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_61 = a_mask_sub_14_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_61 = a_mask_eq_61; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_62 = a_mask_sub_15_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_62 = a_mask_eq_62; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_63 = a_mask_sub_15_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_63 = a_mask_eq_63; // @[Misc.scala:214:27, :215:38] assign bundle_1_data = _T_31[255:0]; // @[Edges.scala:480:17, :489:15] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] wire _current_request_tag_has_response_space_T = _tags_for_issue_Q_io_deq_bits == 5'h0; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_1 = _Queue4_L2RespInternal_io_enq_ready & _current_request_tag_has_response_space_T; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_2 = _tags_for_issue_Q_io_deq_bits == 5'h1; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _current_request_tag_has_response_space_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_4 = _tags_for_issue_Q_io_deq_bits == 5'h2; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _current_request_tag_has_response_space_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_6 = _tags_for_issue_Q_io_deq_bits == 5'h3; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _current_request_tag_has_response_space_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_8 = _tags_for_issue_Q_io_deq_bits == 5'h4; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _current_request_tag_has_response_space_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_10 = _tags_for_issue_Q_io_deq_bits == 5'h5; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _current_request_tag_has_response_space_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_12 = _tags_for_issue_Q_io_deq_bits == 5'h6; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _current_request_tag_has_response_space_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_14 = _tags_for_issue_Q_io_deq_bits == 5'h7; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _current_request_tag_has_response_space_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_16 = _tags_for_issue_Q_io_deq_bits == 5'h8; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _current_request_tag_has_response_space_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_18 = _tags_for_issue_Q_io_deq_bits == 5'h9; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _current_request_tag_has_response_space_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_20 = _tags_for_issue_Q_io_deq_bits == 5'hA; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _current_request_tag_has_response_space_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_22 = _tags_for_issue_Q_io_deq_bits == 5'hB; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _current_request_tag_has_response_space_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_24 = _tags_for_issue_Q_io_deq_bits == 5'hC; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _current_request_tag_has_response_space_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_26 = _tags_for_issue_Q_io_deq_bits == 5'hD; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _current_request_tag_has_response_space_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_28 = _tags_for_issue_Q_io_deq_bits == 5'hE; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _current_request_tag_has_response_space_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_30 = _tags_for_issue_Q_io_deq_bits == 5'hF; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _current_request_tag_has_response_space_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_32 = _tags_for_issue_Q_io_deq_bits == 5'h10; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _current_request_tag_has_response_space_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_34 = _tags_for_issue_Q_io_deq_bits == 5'h11; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _current_request_tag_has_response_space_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_36 = _tags_for_issue_Q_io_deq_bits == 5'h12; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _current_request_tag_has_response_space_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_38 = _tags_for_issue_Q_io_deq_bits == 5'h13; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _current_request_tag_has_response_space_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_40 = _tags_for_issue_Q_io_deq_bits == 5'h14; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _current_request_tag_has_response_space_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_42 = _tags_for_issue_Q_io_deq_bits == 5'h15; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _current_request_tag_has_response_space_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_44 = _tags_for_issue_Q_io_deq_bits == 5'h16; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _current_request_tag_has_response_space_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_46 = _tags_for_issue_Q_io_deq_bits == 5'h17; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _current_request_tag_has_response_space_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_48 = _tags_for_issue_Q_io_deq_bits == 5'h18; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _current_request_tag_has_response_space_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_50 = _tags_for_issue_Q_io_deq_bits == 5'h19; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _current_request_tag_has_response_space_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_52 = _tags_for_issue_Q_io_deq_bits == 5'h1A; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _current_request_tag_has_response_space_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_54 = _tags_for_issue_Q_io_deq_bits == 5'h1B; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _current_request_tag_has_response_space_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_56 = _tags_for_issue_Q_io_deq_bits == 5'h1C; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _current_request_tag_has_response_space_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_58 = _tags_for_issue_Q_io_deq_bits == 5'h1D; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _current_request_tag_has_response_space_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_60 = _tags_for_issue_Q_io_deq_bits == 5'h1E; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _current_request_tag_has_response_space_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_62 = &_tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _current_request_tag_has_response_space_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_64 = _current_request_tag_has_response_space_T_1 \| _current_request_tag_has_response_space_T_3; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_65 = _current_request_tag_has_response_space_T_64 \| _current_request_tag_has_response_space_T_5; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_66 = _current_request_tag_has_response_space_T_65 \| _current_request_tag_has_response_space_T_7; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_67 = _current_request_tag_has_response_space_T_66 \| _current_request_tag_has_response_space_T_9; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_68 = _current_request_tag_has_response_space_T_67 \| _current_request_tag_has_response_space_T_11; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_69 = _current_request_tag_has_response_space_T_68 \| _current_request_tag_has_response_space_T_13; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_70 = _current_request_tag_has_response_space_T_69 \| _current_request_tag_has_response_space_T_15; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_71 = _current_request_tag_has_response_space_T_70 \| _current_request_tag_has_response_space_T_17; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_72 = _current_request_tag_has_response_space_T_71 \| _current_request_tag_has_response_space_T_19; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_73 = _current_request_tag_has_response_space_T_72 \| _current_request_tag_has_response_space_T_21; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_74 = _current_request_tag_has_response_space_T_73 \| _current_request_tag_has_response_space_T_23; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_75 = _current_request_tag_has_response_space_T_74 \| _current_request_tag_has_response_space_T_25; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_76 = _current_request_tag_has_response_space_T_75 \| _current_request_tag_has_response_space_T_27; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_77 = _current_request_tag_has_response_space_T_76 \| _current_request_tag_has_response_space_T_29; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_78 = _current_request_tag_has_response_space_T_77 \| _current_request_tag_has_response_space_T_31; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_79 = _current_request_tag_has_response_space_T_78 \| _current_request_tag_has_response_space_T_33; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_80 = _current_request_tag_has_response_space_T_79 \| _current_request_tag_has_response_space_T_35; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_81 = _current_request_tag_has_response_space_T_80 \| _current_request_tag_has_response_space_T_37; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_82 = _current_request_tag_has_response_space_T_81 \| _current_request_tag_has_response_space_T_39; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_83 = _current_request_tag_has_response_space_T_82 \| _current_request_tag_has_response_space_T_41; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_84 = _current_request_tag_has_response_space_T_83 \| _current_request_tag_has_response_space_T_43; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_85 = _current_request_tag_has_response_space_T_84 \| _current_request_tag_has_response_space_T_45; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_86 = _current_request_tag_has_response_space_T_85 \| _current_request_tag_has_response_space_T_47; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_87 = _current_request_tag_has_response_space_T_86 \| _current_request_tag_has_response_space_T_49; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_88 = _current_request_tag_has_response_space_T_87 \| _current_request_tag_has_response_space_T_51; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_89 = _current_request_tag_has_response_space_T_88 \| _current_request_tag_has_response_space_T_53; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_90 = _current_request_tag_has_response_space_T_89 \| _current_request_tag_has_response_space_T_55; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_91 = _current_request_tag_has_response_space_T_90 \| _current_request_tag_has_response_space_T_57; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_92 = _current_request_tag_has_response_space_T_91 \| _current_request_tag_has_response_space_T_59; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_93 = _current_request_tag_has_response_space_T_92 \| _current_request_tag_has_response_space_T_61; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire current_request_tag_has_response_space = _current_request_tag_has_response_space_T_93 \| _current_request_tag_has_response_space_T_63; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire [70:0] _outstanding_req_addr_io_enq_bits_addrindex_T = {66'h0, request_input_bits_addr[4:0]}; // @[L2MemHelperLatencyInjection.scala:44:27, :200:73] wire _request_latency_injection_q_io_enq_valid_T = request_input_valid & tlb_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_1 = _request_latency_injection_q_io_enq_valid_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_2 = _request_latency_injection_q_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_3 = _request_latency_injection_q_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_4 = _request_latency_injection_q_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _request_input_ready_T = _request_latency_injection_q_io_enq_ready & tlb_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_1 = _request_input_ready_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_2 = _request_input_ready_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_input_ready_T_3 = _request_input_ready_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] assign _request_input_ready_T_4 = _request_input_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] assign request_input_ready = _request_input_ready_T_4; // @[Misc.scala:26:53] wire _T_45 = request_input_valid & _request_latency_injection_q_io_enq_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T; // @[Misc.scala:26:53] assign _outstanding_req_addr_io_enq_valid_T = _T_45; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T; // @[Misc.scala:26:53] assign _tags_for_issue_Q_io_deq_ready_T = _T_45; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_1 = _outstanding_req_addr_io_enq_valid_T & tlb_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_2 = _outstanding_req_addr_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_3 = _outstanding_req_addr_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_4 = _outstanding_req_addr_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_1 = _tags_for_issue_Q_io_deq_ready_T & tlb_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_2 = _tags_for_issue_Q_io_deq_ready_T_1 & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_3 = _tags_for_issue_Q_io_deq_ready_T_2 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_4 = _tags_for_issue_Q_io_deq_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:26:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:26:33, :27:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:27:38] wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49] wire _printf_T_3 = ~_printf_T_2; // @[annotations.scala:102:49] wire _selectQready_T = _response_latency_injection_q_io_deq_bits_source == 5'h0; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_1 = _Queue4_L2RespInternal_io_enq_ready & _selectQready_T; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_2 = _response_latency_injection_q_io_deq_bits_source == 5'h1; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _selectQready_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_4 = _response_latency_injection_q_io_deq_bits_source == 5'h2; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _selectQready_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_6 = _response_latency_injection_q_io_deq_bits_source == 5'h3; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _selectQready_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_8 = _response_latency_injection_q_io_deq_bits_source == 5'h4; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _selectQready_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_10 = _response_latency_injection_q_io_deq_bits_source == 5'h5; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _selectQready_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_12 = _response_latency_injection_q_io_deq_bits_source == 5'h6; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _selectQready_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_14 = _response_latency_injection_q_io_deq_bits_source == 5'h7; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _selectQready_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_16 = _response_latency_injection_q_io_deq_bits_source == 5'h8; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _selectQready_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_18 = _response_latency_injection_q_io_deq_bits_source == 5'h9; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _selectQready_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_20 = _response_latency_injection_q_io_deq_bits_source == 5'hA; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _selectQready_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_22 = _response_latency_injection_q_io_deq_bits_source == 5'hB; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _selectQready_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_24 = _response_latency_injection_q_io_deq_bits_source == 5'hC; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _selectQready_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_26 = _response_latency_injection_q_io_deq_bits_source == 5'hD; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _selectQready_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_28 = _response_latency_injection_q_io_deq_bits_source == 5'hE; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _selectQready_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_30 = _response_latency_injection_q_io_deq_bits_source == 5'hF; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _selectQready_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_32 = _response_latency_injection_q_io_deq_bits_source == 5'h10; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _selectQready_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_34 = _response_latency_injection_q_io_deq_bits_source == 5'h11; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _selectQready_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_36 = _response_latency_injection_q_io_deq_bits_source == 5'h12; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _selectQready_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_38 = _response_latency_injection_q_io_deq_bits_source == 5'h13; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _selectQready_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_40 = _response_latency_injection_q_io_deq_bits_source == 5'h14; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _selectQready_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_42 = _response_latency_injection_q_io_deq_bits_source == 5'h15; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _selectQready_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_44 = _response_latency_injection_q_io_deq_bits_source == 5'h16; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _selectQready_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_46 = _response_latency_injection_q_io_deq_bits_source == 5'h17; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _selectQready_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_48 = _response_latency_injection_q_io_deq_bits_source == 5'h18; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _selectQready_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_50 = _response_latency_injection_q_io_deq_bits_source == 5'h19; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _selectQready_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_52 = _response_latency_injection_q_io_deq_bits_source == 5'h1A; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _selectQready_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_54 = _response_latency_injection_q_io_deq_bits_source == 5'h1B; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _selectQready_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_56 = _response_latency_injection_q_io_deq_bits_source == 5'h1C; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _selectQready_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_58 = _response_latency_injection_q_io_deq_bits_source == 5'h1D; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _selectQready_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_60 = _response_latency_injection_q_io_deq_bits_source == 5'h1E; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _selectQready_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_62 = &_response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _selectQready_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_64 = _selectQready_T_1 \| _selectQready_T_3; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_65 = _selectQready_T_64 \| _selectQready_T_5; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_66 = _selectQready_T_65 \| _selectQready_T_7; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_67 = _selectQready_T_66 \| _selectQready_T_9; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_68 = _selectQready_T_67 \| _selectQready_T_11; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_69 = _selectQready_T_68 \| _selectQready_T_13; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_70 = _selectQready_T_69 \| _selectQready_T_15; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_71 = _selectQready_T_70 \| _selectQready_T_17; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_72 = _selectQready_T_71 \| _selectQready_T_19; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_73 = _selectQready_T_72 \| _selectQready_T_21; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_74 = _selectQready_T_73 \| _selectQready_T_23; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_75 = _selectQready_T_74 \| _selectQready_T_25; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_76 = _selectQready_T_75 \| _selectQready_T_27; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_77 = _selectQready_T_76 \| _selectQready_T_29; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_78 = _selectQready_T_77 \| _selectQready_T_31; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_79 = _selectQready_T_78 \| _selectQready_T_33; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_80 = _selectQready_T_79 \| _selectQready_T_35; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_81 = _selectQready_T_80 \| _selectQready_T_37; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_82 = _selectQready_T_81 \| _selectQready_T_39; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_83 = _selectQready_T_82 \| _selectQready_T_41; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_84 = _selectQready_T_83 \| _selectQready_T_43; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_85 = _selectQready_T_84 \| _selectQready_T_45; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_86 = _selectQready_T_85 \| _selectQready_T_47; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_87 = _selectQready_T_86 \| _selectQready_T_49; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_88 = _selectQready_T_87 \| _selectQready_T_51; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_89 = _selectQready_T_88 \| _selectQready_T_53; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_90 = _selectQready_T_89 \| _selectQready_T_55; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_91 = _selectQready_T_90 \| _selectQready_T_57; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_92 = _selectQready_T_91 \| _selectQready_T_59; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_93 = _selectQready_T_92 \| _selectQready_T_61; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire selectQready = _selectQready_T_93 \| _selectQready_T_63; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _T_57 = selectQready & _response_latency_injection_q_io_deq_valid; // @[Misc.scala:26:53] wire tags_for_issue_Q_io_enq_valid = _T_57 \| _T_4; // @[Misc.scala:26:53] wire [4:0] tags_for_issue_Q_io_enq_bits = _T_57 ? _response_latency_injection_q_io_deq_bits_source : tags_init_reg[4:0]; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] wire _response_latency_injection_q_io_deq_ready_T = selectQready & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_156 = _response_latency_injection_q_io_deq_valid & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_160 = _outstanding_req_addr_io_deq_bits_tag == 5'h0; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T = _T_160; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q = _T_160; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_1 = _Queue4_L2RespInternal_io_deq_valid & _queueValid_T; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_163 = _outstanding_req_addr_io_deq_bits_tag == 5'h1; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_2 = _T_163; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_1; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_1 = _T_163; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_3 = _Queue4_L2RespInternal_1_io_deq_valid & _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_166 = _outstanding_req_addr_io_deq_bits_tag == 5'h2; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_4 = _T_166; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_2; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_2 = _T_166; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_5 = _Queue4_L2RespInternal_2_io_deq_valid & _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_169 = _outstanding_req_addr_io_deq_bits_tag == 5'h3; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_6 = _T_169; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_3; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_3 = _T_169; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_7 = _Queue4_L2RespInternal_3_io_deq_valid & _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_172 = _outstanding_req_addr_io_deq_bits_tag == 5'h4; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_8 = _T_172; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_4; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_4 = _T_172; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_9 = _Queue4_L2RespInternal_4_io_deq_valid & _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_175 = _outstanding_req_addr_io_deq_bits_tag == 5'h5; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_10 = _T_175; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_5; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_5 = _T_175; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_11 = _Queue4_L2RespInternal_5_io_deq_valid & _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_178 = _outstanding_req_addr_io_deq_bits_tag == 5'h6; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_12 = _T_178; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_6; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_6 = _T_178; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_13 = _Queue4_L2RespInternal_6_io_deq_valid & _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_181 = _outstanding_req_addr_io_deq_bits_tag == 5'h7; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_14 = _T_181; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_7; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_7 = _T_181; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_15 = _Queue4_L2RespInternal_7_io_deq_valid & _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_184 = _outstanding_req_addr_io_deq_bits_tag == 5'h8; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_16 = _T_184; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_8; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_8 = _T_184; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_17 = _Queue4_L2RespInternal_8_io_deq_valid & _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_187 = _outstanding_req_addr_io_deq_bits_tag == 5'h9; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_18 = _T_187; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_9; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_9 = _T_187; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_19 = _Queue4_L2RespInternal_9_io_deq_valid & _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_190 = _outstanding_req_addr_io_deq_bits_tag == 5'hA; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_20 = _T_190; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_10; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_10 = _T_190; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_21 = _Queue4_L2RespInternal_10_io_deq_valid & _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_193 = _outstanding_req_addr_io_deq_bits_tag == 5'hB; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_22 = _T_193; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_11; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_11 = _T_193; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_23 = _Queue4_L2RespInternal_11_io_deq_valid & _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_196 = _outstanding_req_addr_io_deq_bits_tag == 5'hC; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_24 = _T_196; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_12; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_12 = _T_196; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_25 = _Queue4_L2RespInternal_12_io_deq_valid & _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_199 = _outstanding_req_addr_io_deq_bits_tag == 5'hD; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_26 = _T_199; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_13; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_13 = _T_199; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_27 = _Queue4_L2RespInternal_13_io_deq_valid & _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_202 = _outstanding_req_addr_io_deq_bits_tag == 5'hE; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_28 = _T_202; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_14; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_14 = _T_202; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_29 = _Queue4_L2RespInternal_14_io_deq_valid & _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_205 = _outstanding_req_addr_io_deq_bits_tag == 5'hF; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_30 = _T_205; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_15; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_15 = _T_205; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_31 = _Queue4_L2RespInternal_15_io_deq_valid & _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_208 = _outstanding_req_addr_io_deq_bits_tag == 5'h10; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_32 = _T_208; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_16; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_16 = _T_208; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_33 = _Queue4_L2RespInternal_16_io_deq_valid & _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_211 = _outstanding_req_addr_io_deq_bits_tag == 5'h11; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_34 = _T_211; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_17; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_17 = _T_211; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_35 = _Queue4_L2RespInternal_17_io_deq_valid & _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_214 = _outstanding_req_addr_io_deq_bits_tag == 5'h12; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_36 = _T_214; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_18; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_18 = _T_214; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_37 = _Queue4_L2RespInternal_18_io_deq_valid & _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_217 = _outstanding_req_addr_io_deq_bits_tag == 5'h13; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_38 = _T_217; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_19; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_19 = _T_217; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_39 = _Queue4_L2RespInternal_19_io_deq_valid & _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_220 = _outstanding_req_addr_io_deq_bits_tag == 5'h14; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_40 = _T_220; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_20; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_20 = _T_220; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_41 = _Queue4_L2RespInternal_20_io_deq_valid & _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_223 = _outstanding_req_addr_io_deq_bits_tag == 5'h15; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_42 = _T_223; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_21; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_21 = _T_223; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_43 = _Queue4_L2RespInternal_21_io_deq_valid & _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_226 = _outstanding_req_addr_io_deq_bits_tag == 5'h16; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_44 = _T_226; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_22; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_22 = _T_226; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_45 = _Queue4_L2RespInternal_22_io_deq_valid & _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_229 = _outstanding_req_addr_io_deq_bits_tag == 5'h17; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_46 = _T_229; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_23; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_23 = _T_229; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_47 = _Queue4_L2RespInternal_23_io_deq_valid & _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_232 = _outstanding_req_addr_io_deq_bits_tag == 5'h18; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_48 = _T_232; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_24; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_24 = _T_232; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_49 = _Queue4_L2RespInternal_24_io_deq_valid & _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_235 = _outstanding_req_addr_io_deq_bits_tag == 5'h19; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_50 = _T_235; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_25; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_25 = _T_235; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_51 = _Queue4_L2RespInternal_25_io_deq_valid & _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_238 = _outstanding_req_addr_io_deq_bits_tag == 5'h1A; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_52 = _T_238; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_26; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_26 = _T_238; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_53 = _Queue4_L2RespInternal_26_io_deq_valid & _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_241 = _outstanding_req_addr_io_deq_bits_tag == 5'h1B; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_54 = _T_241; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_27; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_27 = _T_241; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_55 = _Queue4_L2RespInternal_27_io_deq_valid & _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_244 = _outstanding_req_addr_io_deq_bits_tag == 5'h1C; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_56 = _T_244; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_28; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_28 = _T_244; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_57 = _Queue4_L2RespInternal_28_io_deq_valid & _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_247 = _outstanding_req_addr_io_deq_bits_tag == 5'h1D; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_58 = _T_247; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_29; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_29 = _T_247; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_59 = _Queue4_L2RespInternal_29_io_deq_valid & _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_250 = _outstanding_req_addr_io_deq_bits_tag == 5'h1E; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_60 = _T_250; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_30; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_30 = _T_250; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_61 = _Queue4_L2RespInternal_30_io_deq_valid & _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_62 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_63 = _Queue4_L2RespInternal_31_io_deq_valid & _queueValid_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_64 = _queueValid_T_1 \| _queueValid_T_3; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_65 = _queueValid_T_64 \| _queueValid_T_5; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_66 = _queueValid_T_65 \| _queueValid_T_7; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_67 = _queueValid_T_66 \| _queueValid_T_9; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_68 = _queueValid_T_67 \| _queueValid_T_11; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_69 = _queueValid_T_68 \| _queueValid_T_13; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_70 = _queueValid_T_69 \| _queueValid_T_15; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_71 = _queueValid_T_70 \| _queueValid_T_17; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_72 = _queueValid_T_71 \| _queueValid_T_19; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_73 = _queueValid_T_72 \| _queueValid_T_21; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_74 = _queueValid_T_73 \| _queueValid_T_23; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_75 = _queueValid_T_74 \| _queueValid_T_25; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_76 = _queueValid_T_75 \| _queueValid_T_27; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_77 = _queueValid_T_76 \| _queueValid_T_29; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_78 = _queueValid_T_77 \| _queueValid_T_31; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_79 = _queueValid_T_78 \| _queueValid_T_33; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_80 = _queueValid_T_79 \| _queueValid_T_35; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_81 = _queueValid_T_80 \| _queueValid_T_37; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_82 = _queueValid_T_81 \| _queueValid_T_39; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_83 = _queueValid_T_82 \| _queueValid_T_41; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_84 = _queueValid_T_83 \| _queueValid_T_43; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_85 = _queueValid_T_84 \| _queueValid_T_45; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_86 = _queueValid_T_85 \| _queueValid_T_47; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_87 = _queueValid_T_86 \| _queueValid_T_49; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_88 = _queueValid_T_87 \| _queueValid_T_51; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_89 = _queueValid_T_88 \| _queueValid_T_53; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_90 = _queueValid_T_89 \| _queueValid_T_55; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_91 = _queueValid_T_90 \| _queueValid_T_57; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_92 = _queueValid_T_91 \| _queueValid_T_59; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_93 = _queueValid_T_92 \| _queueValid_T_61; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire queueValid = _queueValid_T_93 \| _queueValid_T_63; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire [255:0] resultdata_data; // @[L2MemHelperLatencyInjection.scala:300:20] wire [7:0] _GEN_8 = {_outstanding_req_addr_io_deq_bits_addrindex, 3'h0}; // @[L2MemHelperLatencyInjection.scala:91:36, :302:78] wire [7:0] _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_2 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_4 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_6 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_8 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_10 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_12 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_14 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_16 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_18 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_20 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_22 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_24 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_26 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_28 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_30 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_32 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_34 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_36 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_38 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_40 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_42 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_44 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_46 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_48 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_50 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_52 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_54 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_56 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_58 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_60 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_62 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [255:0] _resultdata_data_T_1 = _Queue4_L2RespInternal_io_deq_bits_data >> _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data = resultdata_is_current_q ? _resultdata_data_T_1 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_3 = _Queue4_L2RespInternal_1_io_deq_bits_data >> _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_1 = resultdata_is_current_q_1 ? _resultdata_data_T_3 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_5 = _Queue4_L2RespInternal_2_io_deq_bits_data >> _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_2 = resultdata_is_current_q_2 ? _resultdata_data_T_5 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_7 = _Queue4_L2RespInternal_3_io_deq_bits_data >> _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_3 = resultdata_is_current_q_3 ? _resultdata_data_T_7 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_9 = _Queue4_L2RespInternal_4_io_deq_bits_data >> _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_4 = resultdata_is_current_q_4 ? _resultdata_data_T_9 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_11 = _Queue4_L2RespInternal_5_io_deq_bits_data >> _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_5 = resultdata_is_current_q_5 ? _resultdata_data_T_11 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_13 = _Queue4_L2RespInternal_6_io_deq_bits_data >> _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_6 = resultdata_is_current_q_6 ? _resultdata_data_T_13 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_15 = _Queue4_L2RespInternal_7_io_deq_bits_data >> _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_7 = resultdata_is_current_q_7 ? _resultdata_data_T_15 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_17 = _Queue4_L2RespInternal_8_io_deq_bits_data >> _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_8 = resultdata_is_current_q_8 ? _resultdata_data_T_17 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_19 = _Queue4_L2RespInternal_9_io_deq_bits_data >> _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_9 = resultdata_is_current_q_9 ? _resultdata_data_T_19 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_21 = _Queue4_L2RespInternal_10_io_deq_bits_data >> _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_10 = resultdata_is_current_q_10 ? _resultdata_data_T_21 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_23 = _Queue4_L2RespInternal_11_io_deq_bits_data >> _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_11 = resultdata_is_current_q_11 ? _resultdata_data_T_23 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_25 = _Queue4_L2RespInternal_12_io_deq_bits_data >> _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_12 = resultdata_is_current_q_12 ? _resultdata_data_T_25 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_27 = _Queue4_L2RespInternal_13_io_deq_bits_data >> _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_13 = resultdata_is_current_q_13 ? _resultdata_data_T_27 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_29 = _Queue4_L2RespInternal_14_io_deq_bits_data >> _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_14 = resultdata_is_current_q_14 ? _resultdata_data_T_29 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_31 = _Queue4_L2RespInternal_15_io_deq_bits_data >> _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_15 = resultdata_is_current_q_15 ? _resultdata_data_T_31 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_33 = _Queue4_L2RespInternal_16_io_deq_bits_data >> _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_16 = resultdata_is_current_q_16 ? _resultdata_data_T_33 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_35 = _Queue4_L2RespInternal_17_io_deq_bits_data >> _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_17 = resultdata_is_current_q_17 ? _resultdata_data_T_35 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_37 = _Queue4_L2RespInternal_18_io_deq_bits_data >> _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_18 = resultdata_is_current_q_18 ? _resultdata_data_T_37 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_39 = _Queue4_L2RespInternal_19_io_deq_bits_data >> _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_19 = resultdata_is_current_q_19 ? _resultdata_data_T_39 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_41 = _Queue4_L2RespInternal_20_io_deq_bits_data >> _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_20 = resultdata_is_current_q_20 ? _resultdata_data_T_41 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_43 = _Queue4_L2RespInternal_21_io_deq_bits_data >> _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_21 = resultdata_is_current_q_21 ? _resultdata_data_T_43 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_45 = _Queue4_L2RespInternal_22_io_deq_bits_data >> _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_22 = resultdata_is_current_q_22 ? _resultdata_data_T_45 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_47 = _Queue4_L2RespInternal_23_io_deq_bits_data >> _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_23 = resultdata_is_current_q_23 ? _resultdata_data_T_47 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_49 = _Queue4_L2RespInternal_24_io_deq_bits_data >> _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_24 = resultdata_is_current_q_24 ? _resultdata_data_T_49 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_51 = _Queue4_L2RespInternal_25_io_deq_bits_data >> _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_25 = resultdata_is_current_q_25 ? _resultdata_data_T_51 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_53 = _Queue4_L2RespInternal_26_io_deq_bits_data >> _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_26 = resultdata_is_current_q_26 ? _resultdata_data_T_53 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_55 = _Queue4_L2RespInternal_27_io_deq_bits_data >> _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_27 = resultdata_is_current_q_27 ? _resultdata_data_T_55 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_57 = _Queue4_L2RespInternal_28_io_deq_bits_data >> _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_28 = resultdata_is_current_q_28 ? _resultdata_data_T_57 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_59 = _Queue4_L2RespInternal_29_io_deq_bits_data >> _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_29 = resultdata_is_current_q_29 ? _resultdata_data_T_59 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_61 = _Queue4_L2RespInternal_30_io_deq_bits_data >> _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_30 = resultdata_is_current_q_30 ? _resultdata_data_T_61 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire resultdata_is_current_q_31 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27, :299:31] wire [255:0] resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_63 = _Queue4_L2RespInternal_31_io_deq_bits_data >> _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_31 = resultdata_is_current_q_31 ? _resultdata_data_T_63 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] _resultdata_T = resultdata_data \| resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_1 = _resultdata_T \| resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_2 = _resultdata_T_1 \| resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_3 = _resultdata_T_2 \| resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_4 = _resultdata_T_3 \| resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_5 = _resultdata_T_4 \| resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_6 = _resultdata_T_5 \| resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_7 = _resultdata_T_6 \| resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_8 = _resultdata_T_7 \| resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_9 = _resultdata_T_8 \| resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_10 = _resultdata_T_9 \| resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_11 = _resultdata_T_10 \| resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_12 = _resultdata_T_11 \| resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_13 = _resultdata_T_12 \| resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_14 = _resultdata_T_13 \| resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_15 = _resultdata_T_14 \| resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_16 = _resultdata_T_15 \| resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_17 = _resultdata_T_16 \| resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_18 = _resultdata_T_17 \| resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_19 = _resultdata_T_18 \| resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_20 = _resultdata_T_19 \| resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_21 = _resultdata_T_20 \| resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_22 = _resultdata_T_21 \| resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_23 = _resultdata_T_22 \| resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_24 = _resultdata_T_23 \| resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_25 = _resultdata_T_24 \| resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_26 = _resultdata_T_25 \| resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_27 = _resultdata_T_26 \| resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_28 = _resultdata_T_27 \| resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_29 = _resultdata_T_28 \| resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign resultdata = _resultdata_T_29 \| resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign response_output_bits_data = resultdata; // @[L2MemHelperLatencyInjection.scala:53:29, :307:15] assign _response_output_valid_T = queueValid & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] assign response_output_valid = _response_output_valid_T; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_deq_ready_T = queueValid & response_output_ready; // @[Misc.scala:26:53] wire _T_252 = response_output_ready & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] wire opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] wire _T_270 = response_output_ready & response_output_valid; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e8_s24_i8_3 : input clock : Clock input reset : Reset output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<8>, intExceptionFlags : UInt<3>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node magGeOne = bits(rawIn.sExp, 8, 8) node posExp = bits(rawIn.sExp, 7, 0) node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0)) node _magJustBelowOne_T_1 = andr(posExp) node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1) node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _shiftedSig_T = bits(rawIn.sig, 22, 0) node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T) node _shiftedSig_T_2 = bits(rawIn.sExp, 2, 0) node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0)) node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3) node _alignedSig_T = shr(shiftedSig, 22) node _alignedSig_T_1 = bits(shiftedSig, 21, 0) node _alignedSig_T_2 = orr(_alignedSig_T_1) node alignedSig = cat(_alignedSig_T, _alignedSig_T_2) node _unroundedInt_T = shr(alignedSig, 2) node unroundedInt = or(UInt<8>(0h0), _unroundedInt_T) node _common_inexact_T = bits(alignedSig, 1, 0) node _common_inexact_T_1 = orr(_common_inexact_T) node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0)) node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2) node _roundIncr_near_even_T = bits(alignedSig, 2, 1) node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T) node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2) node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3) node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4) node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6) node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7) node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8) node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1) node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T) node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne) node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even) node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag) node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1) node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd) node _roundIncr_T_4 = and(rawIn.sign, common_inexact) node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4) node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5) node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0)) node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact) node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8) node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9) node _complUnroundedInt_T = not(unroundedInt) node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt) node _roundedInt_T = xor(roundIncr, rawIn.sign) node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1)) node _roundedInt_T_2 = tail(_roundedInt_T_1, 1) node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt) node _roundedInt_T_4 = and(roundingMode_odd, common_inexact) node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4) node magGeOne_atOverflowEdge = eq(posExp, UInt<3>(0h7)) node _roundCarryBut2_T = bits(unroundedInt, 5, 0) node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T) node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr) node _common_overflow_T = geq(posExp, UInt<4>(0h8)) node _common_overflow_T_1 = bits(unroundedInt, 6, 0) node _common_overflow_T_2 = orr(_common_overflow_T_1) node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr) node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3) node _common_overflow_T_5 = eq(posExp, UInt<3>(0h6)) node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2) node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6) node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7) node _common_overflow_T_9 = bits(unroundedInt, 6, 6) node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9) node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2) node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11) node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12) node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13) node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0)) node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign) node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr) node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17) node invalidExc = or(rawIn.isNaN, rawIn.isInf) node _overflow_T = eq(invalidExc, UInt<1>(0h0)) node overflow = and(_overflow_T, common_overflow) node _inexact_T = eq(invalidExc, UInt<1>(0h0)) node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0)) node _inexact_T_2 = and(_inexact_T, _inexact_T_1) node inexact = and(_inexact_T_2, common_inexact) node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0)) node excSign = and(_excSign_T, rawIn.sign) node _excOut_T = eq(io.signedOut, excSign) node _excOut_T_1 = mux(_excOut_T, UInt<8>(0h80), UInt<1>(0h0)) node _excOut_T_2 = eq(excSign, UInt<1>(0h0)) node _excOut_T_3 = mux(_excOut_T_2, UInt<7>(0h7f), UInt<1>(0h0)) node excOut = or(_excOut_T_1, _excOut_T_3) node _io_out_T = or(invalidExc, common_overflow) node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt) connect io.out, _io_out_T_1 node _io_intExceptionFlags_T = cat(invalidExc, overflow) node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact) connect io.intExceptionFlags, _io_intExceptionFlags_T_1	module RecFNToIN_e8_s24_i8_3( // @[RecFNToIN.scala:46:7] input clock, // @[RecFNToIN.scala:46:7] input reset, // @[RecFNToIN.scala:46:7] input [32:0] io_in, // @[RecFNToIN.scala:49:16] output [7:0] io_out, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7] wire roundingMode_minMag = 1'h0; // @[RecFNToIN.scala:68:53] wire roundingMode_min = 1'h0; // @[RecFNToIN.scala:69:53] wire roundingMode_max = 1'h0; // @[RecFNToIN.scala:70:53] wire roundingMode_near_maxMag = 1'h0; // @[RecFNToIN.scala:71:53] wire roundingMode_odd = 1'h0; // @[RecFNToIN.scala:72:53] wire _roundIncr_T_1 = 1'h0; // @[RecFNToIN.scala:99:35] wire _roundIncr_T_3 = 1'h0; // @[RecFNToIN.scala:100:28] wire _roundIncr_T_5 = 1'h0; // @[RecFNToIN.scala:100:49] wire _roundIncr_T_9 = 1'h0; // @[RecFNToIN.scala:102:27] wire _roundedInt_T_4 = 1'h0; // @[RecFNToIN.scala:108:31] wire _common_overflow_T_15 = 1'h0; // @[RecFNToIN.scala:128:13] wire _common_overflow_T_16 = 1'h0; // @[RecFNToIN.scala:128:27] wire _common_overflow_T_17 = 1'h0; // @[RecFNToIN.scala:128:41] wire io_signedOut = 1'h1; // @[RecFNToIN.scala:46:7] wire roundingMode_near_even = 1'h1; // @[RecFNToIN.scala:67:53] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToIN.scala:46:7] wire [7:0] _io_out_T_1; // @[RecFNToIN.scala:145:18] wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52] wire [7:0] io_out_0; // @[RecFNToIN.scala:46:7] wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire magGeOne = rawIn_sExp[8]; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] posExp = rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27] wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47] wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}] wire [22:0] _shiftedSig_T = rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}] wire [2:0] _shiftedSig_T_2 = rawIn_sExp[2:0]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 3'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27] wire [30:0] shiftedSig = {7'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16] wire [8:0] _alignedSig_T = shiftedSig[30:22]; // @[RecFNToIN.scala:83:49, :89:20] wire [21:0] _alignedSig_T_1 = shiftedSig[21:0]; // @[RecFNToIN.scala:83:49, :89:51] wire _alignedSig_T_2 = \|_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}] wire [9:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}] wire [7:0] _unroundedInt_T = alignedSig[9:2]; // @[RecFNToIN.scala:89:38, :90:52] wire [7:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}] wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50] wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64] wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39] wire _common_inexact_T_1 = \|_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}] wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}] wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39] wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}] wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}] wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 \| _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}] wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}] wire _roundIncr_near_even_T_7 = \|_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}] wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}] wire roundIncr_near_even = _roundIncr_near_even_T_5 \| _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26] wire _roundIncr_T = roundIncr_near_even; // @[RecFNToIN.scala:94:78, :98:35] wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56] wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}] wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 \| magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}] wire _roundIncr_T_2 = _roundIncr_T; // @[RecFNToIN.scala:98:{35,61}] wire _roundIncr_T_6 = _roundIncr_T_2; // @[RecFNToIN.scala:98:61, :99:61] wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23] wire roundIncr = _roundIncr_T_6; // @[RecFNToIN.scala:99:61, :101:46] wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}] wire [7:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45] wire [7:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23] wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 9'h1; // @[RecFNToIN.scala:103:32, :106:31] wire [7:0] _roundedInt_T_2 = _roundedInt_T_1[7:0]; // @[RecFNToIN.scala:106:31] wire [7:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31] wire [7:0] roundedInt = _roundedInt_T_3; // @[RecFNToIN.scala:105:12, :108:11] wire magGeOne_atOverflowEdge = posExp == 8'h7; // @[RecFNToIN.scala:62:28, :110:43] wire [5:0] _roundCarryBut2_T = unroundedInt[5:0]; // @[RecFNToIN.scala:90:40, :113:38] wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}] wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}] wire _common_overflow_T = \|(posExp[7:3]); // @[RecFNToIN.scala:62:28, :116:21] wire [6:0] _common_overflow_T_1 = unroundedInt[6:0]; // @[RecFNToIN.scala:90:40, :120:42] wire _common_overflow_T_2 = \|_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}] wire _common_overflow_T_3 = _common_overflow_T_2 \| roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}] wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64] wire _common_overflow_T_5 = posExp == 8'h6; // @[RecFNToIN.scala:62:28, :122:38] wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}] wire _common_overflow_T_7 = magGeOne_atOverflowEdge \| _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60] wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_13 = _common_overflow_T_8; // @[RecFNToIN.scala:117:20, :118:24] wire _common_overflow_T_9 = unroundedInt[6]; // @[RecFNToIN.scala:90:40, :126:42] wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42] wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57] wire _common_overflow_T_12 = rawIn_sign \| _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_14 = _common_overflow_T \| _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20] wire common_overflow = magGeOne & _common_overflow_T_14; // @[RecFNToIN.scala:61:30, :115:12, :116:36] wire invalidExc = rawIn_isNaN \| rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20] wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}] wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20] wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35] wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}] wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}] wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _excOut_T = excSign; // @[RecFNToIN.scala:137:32, :139:27] wire [7:0] _excOut_T_1 = {_excOut_T, 7'h0}; // @[RecFNToIN.scala:139:{12,27}] wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13] wire [6:0] _excOut_T_3 = {7{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}] wire [7:0] excOut = {_excOut_T_1[7], _excOut_T_1[6:0] \| _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12] wire _io_out_T = invalidExc \| common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30] assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}] assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18] wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40] assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}] assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52] assign io_out = io_out_0; // @[RecFNToIN.scala:46:7] assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_18 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}} wire _in_flight_WIRE : UInt<1>[8] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = or(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_16 = or(_T_15, UInt<1>(0h0)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_21 = or(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_21, UInt<1>(0h1), "") : assert_4 node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_28 = and(_T_26, _T_27) node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_32 = and(_T_30, _T_31) node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) node _T_40 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_41 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_42 = and(_T_40, _T_41) node _T_43 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_69 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_70 = and(_T_68, _T_69) node _T_71 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_74 = and(_T_72, _T_73) node _T_75 = or(_T_32, _T_39) node _T_76 = or(_T_75, _T_46) node _T_77 = or(_T_76, _T_53) node _T_78 = or(_T_77, _T_60) node _T_79 = or(_T_78, _T_67) node _T_80 = or(_T_79, _T_74) node _T_81 = or(_T_25, _T_80) node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(_T_81, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_81, UInt<1>(0h1), "") : assert_5 node _T_85 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_87 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_88 = and(_T_86, _T_87) node _T_89 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_90 = and(_T_88, _T_89) node _T_91 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_94 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_97 = and(_T_95, _T_96) node _T_98 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_101 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_102 = and(_T_100, _T_101) node _T_103 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_104 = and(_T_102, _T_103) node _T_105 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_108 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_109 = and(_T_107, _T_108) node _T_110 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_111 = and(_T_109, _T_110) node _T_112 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_115 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_116 = and(_T_114, _T_115) node _T_117 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_118 = and(_T_116, _T_117) node _T_119 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_122 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _T_124 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_125 = and(_T_123, _T_124) node _T_126 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_129 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_134 = and(_T_132, _T_133) node _T_135 = or(_T_92, _T_99) node _T_136 = or(_T_135, _T_106) node _T_137 = or(_T_136, _T_113) node _T_138 = or(_T_137, _T_120) node _T_139 = or(_T_138, _T_127) node _T_140 = or(_T_139, _T_134) node _T_141 = or(_T_85, _T_140) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_141, UInt<1>(0h1), "") : assert_6 node _T_145 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_146 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_147 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_148 = and(_T_146, _T_147) node _T_149 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_150 = and(_T_148, _T_149) node _T_151 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_152 = and(_T_150, _T_151) node _T_153 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_154 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_157 = and(_T_155, _T_156) node _T_158 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_161 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_168 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_169 = and(_T_167, _T_168) node _T_170 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_175 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_180 = and(_T_178, _T_179) node _T_181 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_182 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_187 = and(_T_185, _T_186) node _T_188 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_189 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_194 = and(_T_192, _T_193) node _T_195 = or(_T_152, _T_159) node _T_196 = or(_T_195, _T_166) node _T_197 = or(_T_196, _T_173) node _T_198 = or(_T_197, _T_180) node _T_199 = or(_T_198, _T_187) node _T_200 = or(_T_199, _T_194) node _T_201 = or(_T_145, _T_200) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_201, UInt<1>(0h1), "") : assert_7 node _T_205 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_206 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_207 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_208 = and(_T_206, _T_207) node _T_209 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_212 = and(_T_210, _T_211) node _T_213 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_214 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_215 = and(_T_213, _T_214) node _T_216 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_219 = and(_T_217, _T_218) node _T_220 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_221 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_226 = and(_T_224, _T_225) node _T_227 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_228 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_229 = and(_T_227, _T_228) node _T_230 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_233 = and(_T_231, _T_232) node _T_234 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_235 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_236 = and(_T_234, _T_235) node _T_237 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_240 = and(_T_238, _T_239) node _T_241 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_242 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_243 = and(_T_241, _T_242) node _T_244 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_247 = and(_T_245, _T_246) node _T_248 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_249 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_254 = and(_T_252, _T_253) node _T_255 = or(_T_212, _T_219) node _T_256 = or(_T_255, _T_226) node _T_257 = or(_T_256, _T_233) node _T_258 = or(_T_257, _T_240) node _T_259 = or(_T_258, _T_247) node _T_260 = or(_T_259, _T_254) node _T_261 = or(_T_205, _T_260) node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_T_261, UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_261, UInt<1>(0h1), "") : assert_8	module NoCMonitor_18( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s1k3z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_40 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k3z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k3z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLBuffer_a32d64s1k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready = 1'h1; // @[Decoupled.scala:362:21] wire nodeIn_d_ready = 1'h1; // @[Decoupled.scala:362:21] wire [63:0] auto_in_a_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] nodeIn_a_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [7:0] auto_in_a_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [7:0] nodeIn_a_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire auto_in_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire [3:0] auto_in_a_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeIn_a_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_opcode = 3'h4; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_opcode = 3'h4; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_40 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s1k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s1k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_85 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_137 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_85( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_137 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_246 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_502 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_246( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_502 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_31 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut	module MulFullRawFN_31( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T \| _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 \| io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 \| io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 \| _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 \| notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 \| io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_162 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_418 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_162( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_418 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_9 : input clock : Clock input reset : Reset output io : { flip inR : { bits : UInt<32>}, flip inD : { bits : UInt<32>}, outL : { bits : UInt<32>}, outU : { bits : UInt<32>}, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : { bits : UInt<32>}, clock when io.en : connect reg.bits, _reg_T_1.bits connect io.outU, reg connect io.outL, reg	module PE_9( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [31:0] io_inR_bits, // @[Transposer.scala:101:16] input [31:0] io_inD_bits, // @[Transposer.scala:101:16] output [31:0] io_outL_bits, // @[Transposer.scala:101:16] output [31:0] io_outU_bits, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [31:0] io_inR_bits_0 = io_inR_bits; // @[Transposer.scala:100:9] wire [31:0] io_inD_bits_0 = io_inD_bits; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [31:0] io_outL_bits_0; // @[Transposer.scala:100:9] wire [31:0] io_outU_bits_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [31:0] _reg_T_1_bits = _reg_T ? io_inR_bits_0 : io_inD_bits_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [31:0] reg_bits; // @[Transposer.scala:110:24] assign io_outL_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] assign io_outU_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_bits <= _reg_T_1_bits; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL_bits = io_outL_bits_0; // @[Transposer.scala:100:9] assign io_outU_bits = io_outU_bits_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_77 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_77( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BufferBRAM_2 : input clock : Clock input reset : Reset output io : { read : { flip en : UInt<1>, flip addr : UInt<10>, data : UInt<11>}, write : { flip en : UInt<1>, flip addr : UInt<10>, flip data : UInt<11>}} cmem ram : UInt<11> [600] regreset wen : UInt<1>, clock, reset, UInt<1>(0h0) connect wen, io.write.en reg waddr : UInt, clock connect waddr, io.write.addr reg wdata : UInt, clock connect wdata, io.write.data when wen : node _T = or(waddr, UInt<10>(0h0)) node _T_1 = bits(_T, 9, 0) write mport MPORT = ram[_T_1], clock connect MPORT, wdata read mport rread_data_MPORT = ram[io.read.addr], clock reg rread_data : UInt<11>, clock when io.read.en : connect rread_data, rread_data_MPORT node _rbypass_T = eq(io.read.addr, waddr) node _rbypass_T_1 = and(_rbypass_T, wen) reg rbypass : UInt<1>, clock when io.read.en : connect rbypass, _rbypass_T_1 reg rbypass_data : UInt, clock when io.read.en : connect rbypass_data, wdata node _io_read_data_T = mux(rbypass, rbypass_data, rread_data) connect io.read.data, _io_read_data_T	module BufferBRAM_2( // @[Buffer.scala:10:7] input clock, // @[Buffer.scala:10:7] input reset, // @[Buffer.scala:10:7] input io_read_en, // @[Buffer.scala:12:14] input [9:0] io_read_addr, // @[Buffer.scala:12:14] output [10:0] io_read_data, // @[Buffer.scala:12:14] input io_write_en, // @[Buffer.scala:12:14] input [9:0] io_write_addr, // @[Buffer.scala:12:14] input [10:0] io_write_data // @[Buffer.scala:12:14] ); wire [10:0] _ram_ext_R0_data; // @[Buffer.scala:27:16] wire io_read_en_0 = io_read_en; // @[Buffer.scala:10:7] wire [9:0] io_read_addr_0 = io_read_addr; // @[Buffer.scala:10:7] wire io_write_en_0 = io_write_en; // @[Buffer.scala:10:7] wire [9:0] io_write_addr_0 = io_write_addr; // @[Buffer.scala:10:7] wire [10:0] io_write_data_0 = io_write_data; // @[Buffer.scala:10:7] wire [10:0] _io_read_data_T; // @[Buffer.scala:39:22] wire [10:0] io_read_data_0; // @[Buffer.scala:10:7] reg wen; // @[Buffer.scala:29:20] reg [9:0] waddr; // @[Buffer.scala:30:22] reg [10:0] wdata; // @[Buffer.scala:31:22] reg [10:0] rread_data; // @[Buffer.scala:35:29] wire _rbypass_T = io_read_addr_0 == waddr; // @[Buffer.scala:10:7, :30:22, :36:40] wire _rbypass_T_1 = _rbypass_T & wen; // @[Buffer.scala:29:20, :36:{40,50}] reg rbypass; // @[Buffer.scala:36:26] reg [10:0] rbypass_data; // @[Buffer.scala:37:31] assign _io_read_data_T = rbypass ? rbypass_data : rread_data; // @[Buffer.scala:35:29, :36:26, :37:31, :39:22] assign io_read_data_0 = _io_read_data_T; // @[Buffer.scala:10:7, :39:22] always @(posedge clock) begin // @[Buffer.scala:10:7] if (reset) // @[Buffer.scala:10:7] wen <= 1'h0; // @[Buffer.scala:29:20] else // @[Buffer.scala:10:7] wen <= io_write_en_0; // @[Buffer.scala:10:7, :29:20] waddr <= io_write_addr_0; // @[Buffer.scala:10:7, :30:22] wdata <= io_write_data_0; // @[Buffer.scala:10:7, :31:22] if (io_read_en_0) begin // @[Buffer.scala:10:7] rread_data <= _ram_ext_R0_data; // @[Buffer.scala:27:16, :35:29] rbypass <= _rbypass_T_1; // @[Buffer.scala:36:{26,50}] rbypass_data <= wdata; // @[Buffer.scala:31:22, :37:31] end always @(posedge) ram_600x11 ram_ext ( // @[Buffer.scala:27:16] .R0_addr (io_read_addr_0), // @[Buffer.scala:10:7] .R0_en (1'h1), // @[Buffer.scala:10:7] .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (waddr), // @[Buffer.scala:30:22] .W0_en (wen), // @[Buffer.scala:29:20] .W0_clk (clock), .W0_data (wdata) // @[Buffer.scala:31:22] ); // @[Buffer.scala:27:16] assign io_read_data = io_read_data_0; // @[Buffer.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_100 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_100 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_100( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_100 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_42 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_377 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_378 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_379 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_380 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_42( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_377 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_378 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_379 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_380 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget1 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_11 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in node _hasData_opdata_T = bits(anonIn.a.bits.opcode, 2, 2) node hasData = eq(_hasData_opdata_T, UInt<1>(0h0)) node _limit_T = dshl(UInt<3>(0h7), anonIn.a.bits.size) node _limit_T_1 = bits(_limit_T, 2, 0) node _limit_T_2 = not(_limit_T_1) node limit = shr(_limit_T_2, 0) regreset count : UInt<3>, clock, reset, UInt<3>(0h0) node first = eq(count, UInt<1>(0h0)) node _last_T = eq(count, limit) node _last_T_1 = eq(hasData, UInt<1>(0h0)) node last = or(_last_T, _last_T_1) node _enable_T = xor(count, UInt<1>(0h0)) node _enable_T_1 = and(_enable_T, limit) node _enable_T_2 = orr(_enable_T_1) node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) node _enable_T_3 = xor(count, UInt<1>(0h1)) node _enable_T_4 = and(_enable_T_3, limit) node _enable_T_5 = orr(_enable_T_4) node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) node _enable_T_6 = xor(count, UInt<2>(0h2)) node _enable_T_7 = and(_enable_T_6, limit) node _enable_T_8 = orr(_enable_T_7) node enable_2 = eq(_enable_T_8, UInt<1>(0h0)) node _enable_T_9 = xor(count, UInt<2>(0h3)) node _enable_T_10 = and(_enable_T_9, limit) node _enable_T_11 = orr(_enable_T_10) node enable_3 = eq(_enable_T_11, UInt<1>(0h0)) node _enable_T_12 = xor(count, UInt<3>(0h4)) node _enable_T_13 = and(_enable_T_12, limit) node _enable_T_14 = orr(_enable_T_13) node enable_4 = eq(_enable_T_14, UInt<1>(0h0)) node _enable_T_15 = xor(count, UInt<3>(0h5)) node _enable_T_16 = and(_enable_T_15, limit) node _enable_T_17 = orr(_enable_T_16) node enable_5 = eq(_enable_T_17, UInt<1>(0h0)) node _enable_T_18 = xor(count, UInt<3>(0h6)) node _enable_T_19 = and(_enable_T_18, limit) node _enable_T_20 = orr(_enable_T_19) node enable_6 = eq(_enable_T_20, UInt<1>(0h0)) node _enable_T_21 = xor(count, UInt<3>(0h7)) node _enable_T_22 = and(_enable_T_21, limit) node _enable_T_23 = orr(_enable_T_22) node enable_7 = eq(_enable_T_23, UInt<1>(0h0)) regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) node corrupt_out = or(anonIn.a.bits.corrupt, corrupt_reg) node _T = and(anonIn.a.ready, anonIn.a.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 connect corrupt_reg, corrupt_out when last : connect count, UInt<1>(0h0) connect corrupt_reg, UInt<1>(0h0) node _anonIn_a_ready_T = eq(last, UInt<1>(0h0)) node _anonIn_a_ready_T_1 = or(anonOut.a.ready, _anonIn_a_ready_T) connect anonIn.a.ready, _anonIn_a_ready_T_1 node _anonOut_a_valid_T = and(anonIn.a.valid, last) connect anonOut.a.valid, _anonOut_a_valid_T connect anonOut.a.bits, anonIn.a.bits regreset anonOut_a_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonOut_a_bits_data_masked_enable_T = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_0 = or(enable_0, _anonOut_a_bits_data_masked_enable_T) node _anonOut_a_bits_data_masked_enable_T_1 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_1 = or(enable_1, _anonOut_a_bits_data_masked_enable_T_1) node _anonOut_a_bits_data_masked_enable_T_2 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_2 = or(enable_2, _anonOut_a_bits_data_masked_enable_T_2) node _anonOut_a_bits_data_masked_enable_T_3 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_3 = or(enable_3, _anonOut_a_bits_data_masked_enable_T_3) node _anonOut_a_bits_data_masked_enable_T_4 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_4 = or(enable_4, _anonOut_a_bits_data_masked_enable_T_4) node _anonOut_a_bits_data_masked_enable_T_5 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_5 = or(enable_5, _anonOut_a_bits_data_masked_enable_T_5) node _anonOut_a_bits_data_masked_enable_T_6 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_6 = or(enable_6, _anonOut_a_bits_data_masked_enable_T_6) node _anonOut_a_bits_data_masked_enable_T_7 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_7 = or(enable_7, _anonOut_a_bits_data_masked_enable_T_7) wire anonOut_a_bits_data_odata_0 : UInt connect anonOut_a_bits_data_odata_0, anonIn.a.bits.data wire anonOut_a_bits_data_odata_1 : UInt connect anonOut_a_bits_data_odata_1, anonIn.a.bits.data wire anonOut_a_bits_data_odata_2 : UInt connect anonOut_a_bits_data_odata_2, anonIn.a.bits.data wire anonOut_a_bits_data_odata_3 : UInt connect anonOut_a_bits_data_odata_3, anonIn.a.bits.data wire anonOut_a_bits_data_odata_4 : UInt connect anonOut_a_bits_data_odata_4, anonIn.a.bits.data wire anonOut_a_bits_data_odata_5 : UInt connect anonOut_a_bits_data_odata_5, anonIn.a.bits.data wire anonOut_a_bits_data_odata_6 : UInt connect anonOut_a_bits_data_odata_6, anonIn.a.bits.data wire anonOut_a_bits_data_odata_7 : UInt connect anonOut_a_bits_data_odata_7, anonIn.a.bits.data reg anonOut_a_bits_data_rdata : UInt<8>[7], clock node anonOut_a_bits_data_mdata_0 = mux(anonOut_a_bits_data_masked_enable_0, anonOut_a_bits_data_odata_0, anonOut_a_bits_data_rdata[0]) node anonOut_a_bits_data_mdata_1 = mux(anonOut_a_bits_data_masked_enable_1, anonOut_a_bits_data_odata_1, anonOut_a_bits_data_rdata[1]) node anonOut_a_bits_data_mdata_2 = mux(anonOut_a_bits_data_masked_enable_2, anonOut_a_bits_data_odata_2, anonOut_a_bits_data_rdata[2]) node anonOut_a_bits_data_mdata_3 = mux(anonOut_a_bits_data_masked_enable_3, anonOut_a_bits_data_odata_3, anonOut_a_bits_data_rdata[3]) node anonOut_a_bits_data_mdata_4 = mux(anonOut_a_bits_data_masked_enable_4, anonOut_a_bits_data_odata_4, anonOut_a_bits_data_rdata[4]) node anonOut_a_bits_data_mdata_5 = mux(anonOut_a_bits_data_masked_enable_5, anonOut_a_bits_data_odata_5, anonOut_a_bits_data_rdata[5]) node anonOut_a_bits_data_mdata_6 = mux(anonOut_a_bits_data_masked_enable_6, anonOut_a_bits_data_odata_6, anonOut_a_bits_data_rdata[6]) node anonOut_a_bits_data_mdata_7 = mux(anonOut_a_bits_data_masked_enable_7, anonOut_a_bits_data_odata_7, anonIn.a.bits.data) node _anonOut_a_bits_data_T = and(anonIn.a.ready, anonIn.a.valid) node _anonOut_a_bits_data_T_1 = eq(last, UInt<1>(0h0)) node _anonOut_a_bits_data_T_2 = and(_anonOut_a_bits_data_T, _anonOut_a_bits_data_T_1) when _anonOut_a_bits_data_T_2 : connect anonOut_a_bits_data_rdata_written_once, UInt<1>(0h1) connect anonOut_a_bits_data_rdata[0], anonOut_a_bits_data_mdata_0 connect anonOut_a_bits_data_rdata[1], anonOut_a_bits_data_mdata_1 connect anonOut_a_bits_data_rdata[2], anonOut_a_bits_data_mdata_2 connect anonOut_a_bits_data_rdata[3], anonOut_a_bits_data_mdata_3 connect anonOut_a_bits_data_rdata[4], anonOut_a_bits_data_mdata_4 connect anonOut_a_bits_data_rdata[5], anonOut_a_bits_data_mdata_5 connect anonOut_a_bits_data_rdata[6], anonOut_a_bits_data_mdata_6 node anonOut_a_bits_data_lo_lo = cat(anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0) node anonOut_a_bits_data_lo_hi = cat(anonOut_a_bits_data_mdata_3, anonOut_a_bits_data_mdata_2) node anonOut_a_bits_data_lo = cat(anonOut_a_bits_data_lo_hi, anonOut_a_bits_data_lo_lo) node anonOut_a_bits_data_hi_lo = cat(anonOut_a_bits_data_mdata_5, anonOut_a_bits_data_mdata_4) node anonOut_a_bits_data_hi_hi = cat(anonOut_a_bits_data_mdata_7, anonOut_a_bits_data_mdata_6) node anonOut_a_bits_data_hi = cat(anonOut_a_bits_data_hi_hi, anonOut_a_bits_data_hi_lo) node _anonOut_a_bits_data_T_3 = cat(anonOut_a_bits_data_hi, anonOut_a_bits_data_lo) connect anonOut.a.bits.data, _anonOut_a_bits_data_T_3 connect anonOut.a.bits.corrupt, corrupt_out node _anonOut_a_bits_mask_sizeOH_T = or(anonOut.a.bits.size, UInt<3>(0h0)) node anonOut_a_bits_mask_sizeOH_shiftAmount = bits(_anonOut_a_bits_mask_sizeOH_T, 1, 0) node _anonOut_a_bits_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), anonOut_a_bits_mask_sizeOH_shiftAmount) node _anonOut_a_bits_mask_sizeOH_T_2 = bits(_anonOut_a_bits_mask_sizeOH_T_1, 2, 0) node anonOut_a_bits_mask_sizeOH = or(_anonOut_a_bits_mask_sizeOH_T_2, UInt<1>(0h1)) node anonOut_a_bits_mask_sub_sub_sub_0_1 = geq(anonOut.a.bits.size, UInt<2>(0h3)) node anonOut_a_bits_mask_sub_sub_size = bits(anonOut_a_bits_mask_sizeOH, 2, 2) node anonOut_a_bits_mask_sub_sub_bit = bits(anonOut.a.bits.address, 2, 2) node anonOut_a_bits_mask_sub_sub_nbit = eq(anonOut_a_bits_mask_sub_sub_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_sub_sub_0_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_nbit) node _anonOut_a_bits_mask_sub_sub_acc_T = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_0_2) node anonOut_a_bits_mask_sub_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T) node anonOut_a_bits_mask_sub_sub_1_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_bit) node _anonOut_a_bits_mask_sub_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_1_2) node anonOut_a_bits_mask_sub_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T_1) node anonOut_a_bits_mask_sub_size = bits(anonOut_a_bits_mask_sizeOH, 1, 1) node anonOut_a_bits_mask_sub_bit = bits(anonOut.a.bits.address, 1, 1) node anonOut_a_bits_mask_sub_nbit = eq(anonOut_a_bits_mask_sub_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_sub_0_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_nbit) node _anonOut_a_bits_mask_sub_acc_T = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_0_2) node anonOut_a_bits_mask_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T) node anonOut_a_bits_mask_sub_1_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_bit) node _anonOut_a_bits_mask_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_1_2) node anonOut_a_bits_mask_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T_1) node anonOut_a_bits_mask_sub_2_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_nbit) node _anonOut_a_bits_mask_sub_acc_T_2 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_2_2) node anonOut_a_bits_mask_sub_2_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_2) node anonOut_a_bits_mask_sub_3_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_bit) node _anonOut_a_bits_mask_sub_acc_T_3 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_3_2) node anonOut_a_bits_mask_sub_3_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_3) node anonOut_a_bits_mask_size = bits(anonOut_a_bits_mask_sizeOH, 0, 0) node anonOut_a_bits_mask_bit = bits(anonOut.a.bits.address, 0, 0) node anonOut_a_bits_mask_nbit = eq(anonOut_a_bits_mask_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_eq = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq) node anonOut_a_bits_mask_acc = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T) node anonOut_a_bits_mask_eq_1 = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_1 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_1) node anonOut_a_bits_mask_acc_1 = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T_1) node anonOut_a_bits_mask_eq_2 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_2 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_2) node anonOut_a_bits_mask_acc_2 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_2) node anonOut_a_bits_mask_eq_3 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_3 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_3) node anonOut_a_bits_mask_acc_3 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_3) node anonOut_a_bits_mask_eq_4 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_4 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_4) node anonOut_a_bits_mask_acc_4 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_4) node anonOut_a_bits_mask_eq_5 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_5 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_5) node anonOut_a_bits_mask_acc_5 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_5) node anonOut_a_bits_mask_eq_6 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_6 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_6) node anonOut_a_bits_mask_acc_6 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_6) node anonOut_a_bits_mask_eq_7 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_7 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_7) node anonOut_a_bits_mask_acc_7 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_7) node anonOut_a_bits_mask_lo_lo = cat(anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc) node anonOut_a_bits_mask_lo_hi = cat(anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2) node anonOut_a_bits_mask_lo = cat(anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo) node anonOut_a_bits_mask_hi_lo = cat(anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4) node anonOut_a_bits_mask_hi_hi = cat(anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6) node anonOut_a_bits_mask_hi = cat(anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo) node _anonOut_a_bits_mask_T = cat(anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo) regreset anonOut_a_bits_mask_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonOut_a_bits_mask_masked_enable_T = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_0 = or(enable_0, _anonOut_a_bits_mask_masked_enable_T) node _anonOut_a_bits_mask_masked_enable_T_1 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_1 = or(enable_1, _anonOut_a_bits_mask_masked_enable_T_1) node _anonOut_a_bits_mask_masked_enable_T_2 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_2 = or(enable_2, _anonOut_a_bits_mask_masked_enable_T_2) node _anonOut_a_bits_mask_masked_enable_T_3 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_3 = or(enable_3, _anonOut_a_bits_mask_masked_enable_T_3) node _anonOut_a_bits_mask_masked_enable_T_4 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_4 = or(enable_4, _anonOut_a_bits_mask_masked_enable_T_4) node _anonOut_a_bits_mask_masked_enable_T_5 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_5 = or(enable_5, _anonOut_a_bits_mask_masked_enable_T_5) node _anonOut_a_bits_mask_masked_enable_T_6 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_6 = or(enable_6, _anonOut_a_bits_mask_masked_enable_T_6) node _anonOut_a_bits_mask_masked_enable_T_7 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_7 = or(enable_7, _anonOut_a_bits_mask_masked_enable_T_7) wire anonOut_a_bits_mask_odata_0 : UInt connect anonOut_a_bits_mask_odata_0, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_1 : UInt connect anonOut_a_bits_mask_odata_1, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_2 : UInt connect anonOut_a_bits_mask_odata_2, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_3 : UInt connect anonOut_a_bits_mask_odata_3, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_4 : UInt connect anonOut_a_bits_mask_odata_4, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_5 : UInt connect anonOut_a_bits_mask_odata_5, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_6 : UInt connect anonOut_a_bits_mask_odata_6, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_7 : UInt connect anonOut_a_bits_mask_odata_7, anonIn.a.bits.mask reg anonOut_a_bits_mask_rdata : UInt<1>[7], clock node anonOut_a_bits_mask_mdata_0 = mux(anonOut_a_bits_mask_masked_enable_0, anonOut_a_bits_mask_odata_0, anonOut_a_bits_mask_rdata[0]) node anonOut_a_bits_mask_mdata_1 = mux(anonOut_a_bits_mask_masked_enable_1, anonOut_a_bits_mask_odata_1, anonOut_a_bits_mask_rdata[1]) node anonOut_a_bits_mask_mdata_2 = mux(anonOut_a_bits_mask_masked_enable_2, anonOut_a_bits_mask_odata_2, anonOut_a_bits_mask_rdata[2]) node anonOut_a_bits_mask_mdata_3 = mux(anonOut_a_bits_mask_masked_enable_3, anonOut_a_bits_mask_odata_3, anonOut_a_bits_mask_rdata[3]) node anonOut_a_bits_mask_mdata_4 = mux(anonOut_a_bits_mask_masked_enable_4, anonOut_a_bits_mask_odata_4, anonOut_a_bits_mask_rdata[4]) node anonOut_a_bits_mask_mdata_5 = mux(anonOut_a_bits_mask_masked_enable_5, anonOut_a_bits_mask_odata_5, anonOut_a_bits_mask_rdata[5]) node anonOut_a_bits_mask_mdata_6 = mux(anonOut_a_bits_mask_masked_enable_6, anonOut_a_bits_mask_odata_6, anonOut_a_bits_mask_rdata[6]) node anonOut_a_bits_mask_mdata_7 = mux(anonOut_a_bits_mask_masked_enable_7, anonOut_a_bits_mask_odata_7, anonIn.a.bits.mask) node _anonOut_a_bits_mask_T_1 = and(anonIn.a.ready, anonIn.a.valid) node _anonOut_a_bits_mask_T_2 = eq(last, UInt<1>(0h0)) node _anonOut_a_bits_mask_T_3 = and(_anonOut_a_bits_mask_T_1, _anonOut_a_bits_mask_T_2) when _anonOut_a_bits_mask_T_3 : connect anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h1) connect anonOut_a_bits_mask_rdata[0], anonOut_a_bits_mask_mdata_0 connect anonOut_a_bits_mask_rdata[1], anonOut_a_bits_mask_mdata_1 connect anonOut_a_bits_mask_rdata[2], anonOut_a_bits_mask_mdata_2 connect anonOut_a_bits_mask_rdata[3], anonOut_a_bits_mask_mdata_3 connect anonOut_a_bits_mask_rdata[4], anonOut_a_bits_mask_mdata_4 connect anonOut_a_bits_mask_rdata[5], anonOut_a_bits_mask_mdata_5 connect anonOut_a_bits_mask_rdata[6], anonOut_a_bits_mask_mdata_6 node anonOut_a_bits_mask_lo_lo_1 = cat(anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0) node anonOut_a_bits_mask_lo_hi_1 = cat(anonOut_a_bits_mask_mdata_3, anonOut_a_bits_mask_mdata_2) node anonOut_a_bits_mask_lo_1 = cat(anonOut_a_bits_mask_lo_hi_1, anonOut_a_bits_mask_lo_lo_1) node anonOut_a_bits_mask_hi_lo_1 = cat(anonOut_a_bits_mask_mdata_5, anonOut_a_bits_mask_mdata_4) node anonOut_a_bits_mask_hi_hi_1 = cat(anonOut_a_bits_mask_mdata_7, anonOut_a_bits_mask_mdata_6) node anonOut_a_bits_mask_hi_1 = cat(anonOut_a_bits_mask_hi_hi_1, anonOut_a_bits_mask_hi_lo_1) node _anonOut_a_bits_mask_T_4 = cat(anonOut_a_bits_mask_hi_1, anonOut_a_bits_mask_lo_1) node _anonOut_a_bits_mask_T_5 = not(UInt<8>(0h0)) node _anonOut_a_bits_mask_T_6 = mux(hasData, _anonOut_a_bits_mask_T_4, _anonOut_a_bits_mask_T_5) node _anonOut_a_bits_mask_T_7 = and(_anonOut_a_bits_mask_T, _anonOut_a_bits_mask_T_6) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T_7 wire repeat : UInt<1> inst repeated_repeater of Repeater_TLBundleD_a32d64s1k3z4u connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat connect repeated_repeater.io.enq, anonOut.d wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect cated.bits, repeated_repeater.io.deq.bits connect cated.valid, repeated_repeater.io.deq.valid connect repeated_repeater.io.deq.ready, cated.ready node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 63, 8) node _cated_bits_data_T_1 = bits(anonOut.d.bits.data, 7, 0) node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) connect cated.bits.data, _cated_bits_data_T_2 node repeat_hasData = bits(cated.bits.opcode, 0, 0) node _repeat_limit_T = dshl(UInt<3>(0h7), cated.bits.size) node _repeat_limit_T_1 = bits(_repeat_limit_T, 2, 0) node _repeat_limit_T_2 = not(_repeat_limit_T_1) node repeat_limit = shr(_repeat_limit_T_2, 0) regreset repeat_count : UInt<3>, clock, reset, UInt<3>(0h0) node repeat_first = eq(repeat_count, UInt<1>(0h0)) node _repeat_last_T = eq(repeat_count, repeat_limit) node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) node repeat_last = or(_repeat_last_T, _repeat_last_T_1) node _repeat_T = and(anonIn.d.ready, anonIn.d.valid) when _repeat_T : node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) node _repeat_count_T_1 = tail(_repeat_count_T, 1) connect repeat_count, _repeat_count_T_1 when repeat_last : connect repeat_count, UInt<1>(0h0) reg repeat_sel_sel_sources : UInt<3>[1], clock node repeat_sel_sel_a_sel = bits(anonIn.a.bits.address, 2, 0) node _repeat_sel_sel_T = and(anonIn.a.ready, anonIn.a.valid) when _repeat_sel_sel_T : connect repeat_sel_sel_sources[0], repeat_sel_sel_a_sel node _repeat_sel_sel_bypass_T = eq(anonIn.a.bits.source, UInt<0>(0h0)) node repeat_sel_sel_bypass = and(anonIn.a.valid, _repeat_sel_sel_bypass_T) reg repeat_sel_hold_r : UInt<3>, clock when repeat_first : connect repeat_sel_hold_r, repeat_sel_sel_sources[0] node repeat_sel_hold = mux(repeat_first, repeat_sel_sel_sources[0], repeat_sel_hold_r) node _repeat_sel_T = not(repeat_limit) node repeat_sel = and(repeat_sel_hold, _repeat_sel_T) node repeat_index = or(repeat_sel, repeat_count) connect anonIn.d.bits.corrupt, cated.bits.corrupt connect anonIn.d.bits.data, cated.bits.data connect anonIn.d.bits.denied, cated.bits.denied connect anonIn.d.bits.sink, cated.bits.sink connect anonIn.d.bits.source, cated.bits.source connect anonIn.d.bits.size, cated.bits.size connect anonIn.d.bits.param, cated.bits.param connect anonIn.d.bits.opcode, cated.bits.opcode connect anonIn.d.valid, cated.valid connect cated.ready, anonIn.d.ready node _repeat_anonIn_d_bits_data_mux_T = bits(cated.bits.data, 7, 0) node _repeat_anonIn_d_bits_data_mux_T_1 = bits(cated.bits.data, 15, 8) node _repeat_anonIn_d_bits_data_mux_T_2 = bits(cated.bits.data, 23, 16) node _repeat_anonIn_d_bits_data_mux_T_3 = bits(cated.bits.data, 31, 24) node _repeat_anonIn_d_bits_data_mux_T_4 = bits(cated.bits.data, 39, 32) node _repeat_anonIn_d_bits_data_mux_T_5 = bits(cated.bits.data, 47, 40) node _repeat_anonIn_d_bits_data_mux_T_6 = bits(cated.bits.data, 55, 48) node _repeat_anonIn_d_bits_data_mux_T_7 = bits(cated.bits.data, 63, 56) wire repeat_anonIn_d_bits_data_mux : UInt<8>[8] connect repeat_anonIn_d_bits_data_mux[0], _repeat_anonIn_d_bits_data_mux_T connect repeat_anonIn_d_bits_data_mux[1], _repeat_anonIn_d_bits_data_mux_T_1 connect repeat_anonIn_d_bits_data_mux[2], _repeat_anonIn_d_bits_data_mux_T_2 connect repeat_anonIn_d_bits_data_mux[3], _repeat_anonIn_d_bits_data_mux_T_3 connect repeat_anonIn_d_bits_data_mux[4], _repeat_anonIn_d_bits_data_mux_T_4 connect repeat_anonIn_d_bits_data_mux[5], _repeat_anonIn_d_bits_data_mux_T_5 connect repeat_anonIn_d_bits_data_mux[6], _repeat_anonIn_d_bits_data_mux_T_6 connect repeat_anonIn_d_bits_data_mux[7], _repeat_anonIn_d_bits_data_mux_T_7 connect anonIn.d.bits.data, repeat_anonIn_d_bits_data_mux[repeat_index] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) connect repeat, _repeat_T_1 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<8>(0h0) connect _WIRE.bits.mask, UInt<1>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLWidthWidget1( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [63:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [7:0] _anonOut_a_bits_mask_T_5 = 8'hFF; // @[WidthWidget.scala:85:119] wire auto_anon_in_a_bits_mask = 1'h1; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_mask = 1'h1; // @[MixedNode.scala:551:17] wire anonOut_a_bits_mask_odata_0 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_1 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_2 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_3 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_4 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_5 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_6 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_7 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_mdata_7 = 1'h1; // @[WidthWidget.scala:68:88] wire _repeat_sel_sel_bypass_T = 1'h1; // @[WidthWidget.scala:200:53] wire [2:0] auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] anonOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire cated_bits_source = 1'h0; // @[WidthWidget.scala:161:25] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] wire _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire repeat_sel_sel_bypass = anonIn_a_valid; // @[WidthWidget.scala:200:33] assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] anonOut_a_bits_data_odata_0 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_1 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_2 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_3 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_4 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_5 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_6 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_7 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire cated_ready = anonIn_d_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_sink; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] wire cated_bits_denied; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_a_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] _anonOut_a_bits_mask_sizeOH_T = anonOut_a_bits_size; // @[Misc.scala:202:34] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] wire _hasData_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [17:0] _limit_T = 18'h7 << anonIn_a_bits_size; // @[package.scala:243:71] wire [2:0] _limit_T_1 = _limit_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire [2:0] limit = _limit_T_2; // @[package.scala:243:46] reg [2:0] count; // @[WidthWidget.scala:40:27] wire [2:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = count == 3'h0; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T \| _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire [2:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = \|_enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_3 = {count[2:1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = \|_enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_6 = {count[2], count[1:0] ^ 2'h2}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_8 = \|_enable_T_7; // @[WidthWidget.scala:43:{63,72}] wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_9 = {count[2], ~(count[1:0])}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_11 = \|_enable_T_10; // @[WidthWidget.scala:43:{63,72}] wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_12 = count ^ 3'h4; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_13 = _enable_T_12 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_14 = \|_enable_T_13; // @[WidthWidget.scala:43:{63,72}] wire enable_4 = ~_enable_T_14; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_15 = count ^ 3'h5; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_16 = _enable_T_15 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_17 = \|_enable_T_16; // @[WidthWidget.scala:43:{63,72}] wire enable_5 = ~_enable_T_17; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_18 = count ^ 3'h6; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_19 = _enable_T_18 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_20 = \|_enable_T_19; // @[WidthWidget.scala:43:{63,72}] wire enable_6 = ~_enable_T_20; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_21 = ~count; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_22 = _enable_T_21 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_23 = \|_enable_T_22; // @[WidthWidget.scala:43:{63,72}] wire enable_7 = ~_enable_T_23; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonOut_a_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _T = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35] wire _anonOut_a_bits_data_T; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_data_T = _T; // @[Decoupled.scala:51:35] wire _anonOut_a_bits_mask_T_1; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_mask_T_1 = _T; // @[Decoupled.scala:51:35] wire _repeat_sel_sel_T; // @[Decoupled.scala:51:35] assign _repeat_sel_sel_T = _T; // @[Decoupled.scala:51:35] wire [3:0] _count_T = {1'h0, count} + 4'h1; // @[WidthWidget.scala:40:27, :50:24] wire [2:0] _count_T_1 = _count_T[2:0]; // @[WidthWidget.scala:50:24] wire _anonIn_a_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonIn_a_ready_T_1 = anonOut_a_ready \| _anonIn_a_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonIn_a_ready = _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonOut_a_valid_T = anonIn_a_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonOut_a_valid = _anonOut_a_valid_T; // @[WidthWidget.scala:77:29] reg anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonOut_a_bits_data_masked_enable_T = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_0 = enable_0 \| _anonOut_a_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_1 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_1 = enable_1 \| _anonOut_a_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_2 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_2 = enable_2 \| _anonOut_a_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_3 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_3 = enable_3 \| _anonOut_a_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_4 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_4 = enable_4 \| _anonOut_a_bits_data_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_5 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_5 = enable_5 \| _anonOut_a_bits_data_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_6 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_6 = enable_6 \| _anonOut_a_bits_data_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_7 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_7 = enable_7 \| _anonOut_a_bits_data_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [7:0] anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:66:24] wire [7:0] anonOut_a_bits_data_mdata_0 = anonOut_a_bits_data_masked_enable_0 ? anonOut_a_bits_data_odata_0 : anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_1 = anonOut_a_bits_data_masked_enable_1 ? anonOut_a_bits_data_odata_1 : anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_2 = anonOut_a_bits_data_masked_enable_2 ? anonOut_a_bits_data_odata_2 : anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_3 = anonOut_a_bits_data_masked_enable_3 ? anonOut_a_bits_data_odata_3 : anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_4 = anonOut_a_bits_data_masked_enable_4 ? anonOut_a_bits_data_odata_4 : anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_5 = anonOut_a_bits_data_masked_enable_5 ? anonOut_a_bits_data_odata_5 : anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_6 = anonOut_a_bits_data_masked_enable_6 ? anonOut_a_bits_data_odata_6 : anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_7 = anonOut_a_bits_data_masked_enable_7 ? anonOut_a_bits_data_odata_7 : anonIn_a_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonOut_a_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonOut_a_bits_data_T_2 = _anonOut_a_bits_data_T & _anonOut_a_bits_data_T_1; // @[Decoupled.scala:51:35] wire [15:0] anonOut_a_bits_data_lo_lo = {anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [15:0] anonOut_a_bits_data_lo_hi = {anonOut_a_bits_data_mdata_3, anonOut_a_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] wire [31:0] anonOut_a_bits_data_lo = {anonOut_a_bits_data_lo_hi, anonOut_a_bits_data_lo_lo}; // @[WidthWidget.scala:73:12] wire [15:0] anonOut_a_bits_data_hi_lo = {anonOut_a_bits_data_mdata_5, anonOut_a_bits_data_mdata_4}; // @[WidthWidget.scala:68:88, :73:12] wire [15:0] anonOut_a_bits_data_hi_hi = {anonOut_a_bits_data_mdata_7, anonOut_a_bits_data_mdata_6}; // @[WidthWidget.scala:68:88, :73:12] wire [31:0] anonOut_a_bits_data_hi = {anonOut_a_bits_data_hi_hi, anonOut_a_bits_data_hi_lo}; // @[WidthWidget.scala:73:12] assign _anonOut_a_bits_data_T_3 = {anonOut_a_bits_data_hi, anonOut_a_bits_data_lo}; // @[WidthWidget.scala:73:12] assign anonOut_a_bits_data = _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12] wire [1:0] anonOut_a_bits_mask_sizeOH_shiftAmount = _anonOut_a_bits_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _anonOut_a_bits_mask_sizeOH_T_1 = 4'h1 << anonOut_a_bits_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _anonOut_a_bits_mask_sizeOH_T_2 = _anonOut_a_bits_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] anonOut_a_bits_mask_sizeOH = {_anonOut_a_bits_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire anonOut_a_bits_mask_sub_sub_sub_0_1 = anonOut_a_bits_size > 4'h2; // @[Misc.scala:206:21] wire anonOut_a_bits_mask_sub_sub_size = anonOut_a_bits_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_sub_bit = anonOut_a_bits_address[2]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_sub_1_2 = anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire anonOut_a_bits_mask_sub_sub_nbit = ~anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_sub_0_2 = anonOut_a_bits_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_sub_acc_T = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_0_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 \| _anonOut_a_bits_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _anonOut_a_bits_mask_sub_sub_acc_T_1 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_1_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 \| _anonOut_a_bits_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire anonOut_a_bits_mask_sub_size = anonOut_a_bits_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_bit = anonOut_a_bits_address[1]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_nbit = ~anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_0_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_0_1 = anonOut_a_bits_mask_sub_sub_0_1 \| _anonOut_a_bits_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_1_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_1 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_1_1 = anonOut_a_bits_mask_sub_sub_0_1 \| _anonOut_a_bits_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_2_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_2 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_2_1 = anonOut_a_bits_mask_sub_sub_1_1 \| _anonOut_a_bits_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_3_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_3 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_3_1 = anonOut_a_bits_mask_sub_sub_1_1 \| _anonOut_a_bits_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_size = anonOut_a_bits_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_bit = anonOut_a_bits_address[0]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_nbit = ~anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_eq = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc = anonOut_a_bits_mask_sub_0_1 \| _anonOut_a_bits_mask_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_1 = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_1 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_1 = anonOut_a_bits_mask_sub_0_1 \| _anonOut_a_bits_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_2 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_2 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_2 = anonOut_a_bits_mask_sub_1_1 \| _anonOut_a_bits_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_3 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_3 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_3 = anonOut_a_bits_mask_sub_1_1 \| _anonOut_a_bits_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_4 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_4 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_4 = anonOut_a_bits_mask_sub_2_1 \| _anonOut_a_bits_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_5 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_5 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_5 = anonOut_a_bits_mask_sub_2_1 \| _anonOut_a_bits_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_6 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_6 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_6 = anonOut_a_bits_mask_sub_3_1 \| _anonOut_a_bits_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_7 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_7 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_7 = anonOut_a_bits_mask_sub_3_1 \| _anonOut_a_bits_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] anonOut_a_bits_mask_lo_lo = {anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_lo_hi = {anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_lo = {anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] anonOut_a_bits_mask_hi_lo = {anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_hi_hi = {anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_hi = {anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] _anonOut_a_bits_mask_T = {anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo}; // @[Misc.scala:222:10] reg anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonOut_a_bits_mask_masked_enable_T = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_0 = enable_0 \| _anonOut_a_bits_mask_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_1 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_1 = enable_1 \| _anonOut_a_bits_mask_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_2 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_2 = enable_2 \| _anonOut_a_bits_mask_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_3 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_3 = enable_3 \| _anonOut_a_bits_mask_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_4 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_4 = enable_4 \| _anonOut_a_bits_mask_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_5 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_5 = enable_5 \| _anonOut_a_bits_mask_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_6 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_6 = enable_6 \| _anonOut_a_bits_mask_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_7 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_7 = enable_7 \| _anonOut_a_bits_mask_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}] reg anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_1; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_2; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_3; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_4; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_5; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_6; // @[WidthWidget.scala:66:24] wire anonOut_a_bits_mask_mdata_0 = anonOut_a_bits_mask_masked_enable_0 \| anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_1 = anonOut_a_bits_mask_masked_enable_1 \| anonOut_a_bits_mask_rdata_1; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_2 = anonOut_a_bits_mask_masked_enable_2 \| anonOut_a_bits_mask_rdata_2; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_3 = anonOut_a_bits_mask_masked_enable_3 \| anonOut_a_bits_mask_rdata_3; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_4 = anonOut_a_bits_mask_masked_enable_4 \| anonOut_a_bits_mask_rdata_4; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_5 = anonOut_a_bits_mask_masked_enable_5 \| anonOut_a_bits_mask_rdata_5; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_6 = anonOut_a_bits_mask_masked_enable_6 \| anonOut_a_bits_mask_rdata_6; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire _anonOut_a_bits_mask_T_2 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonOut_a_bits_mask_T_3 = _anonOut_a_bits_mask_T_1 & _anonOut_a_bits_mask_T_2; // @[Decoupled.scala:51:35] wire [1:0] anonOut_a_bits_mask_lo_lo_1 = {anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [1:0] anonOut_a_bits_mask_lo_hi_1 = {anonOut_a_bits_mask_mdata_3, anonOut_a_bits_mask_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] wire [3:0] anonOut_a_bits_mask_lo_1 = {anonOut_a_bits_mask_lo_hi_1, anonOut_a_bits_mask_lo_lo_1}; // @[WidthWidget.scala:73:12] wire [1:0] anonOut_a_bits_mask_hi_lo_1 = {anonOut_a_bits_mask_mdata_5, anonOut_a_bits_mask_mdata_4}; // @[WidthWidget.scala:68:88, :73:12] wire [1:0] anonOut_a_bits_mask_hi_hi_1 = {1'h1, anonOut_a_bits_mask_mdata_6}; // @[WidthWidget.scala:68:88, :73:12] wire [3:0] anonOut_a_bits_mask_hi_1 = {anonOut_a_bits_mask_hi_hi_1, anonOut_a_bits_mask_hi_lo_1}; // @[WidthWidget.scala:73:12] wire [7:0] _anonOut_a_bits_mask_T_4 = {anonOut_a_bits_mask_hi_1, anonOut_a_bits_mask_lo_1}; // @[WidthWidget.scala:73:12] wire [7:0] _anonOut_a_bits_mask_T_6 = hasData ? _anonOut_a_bits_mask_T_4 : 8'hFF; // @[WidthWidget.scala:73:12, :85:93] assign _anonOut_a_bits_mask_T_7 = _anonOut_a_bits_mask_T & _anonOut_a_bits_mask_T_6; // @[Misc.scala:222:10] assign anonOut_a_bits_mask = _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonIn_d_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_sink = cated_bits_sink; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_denied = cated_bits_denied; // @[WidthWidget.scala:161:25] wire [63:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonIn_d_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [63:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [55:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[63:8]; // @[Repeater.scala:36:26] wire [7:0] _cated_bits_data_T_1 = anonOut_d_bits_data[7:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire repeat_hasData = cated_bits_opcode[0]; // @[WidthWidget.scala:161:25] wire [17:0] _repeat_limit_T = 18'h7 << cated_bits_size; // @[package.scala:243:71] wire [2:0] _repeat_limit_T_1 = _repeat_limit_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire [2:0] repeat_limit = _repeat_limit_T_2; // @[package.scala:243:46] reg [2:0] repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = repeat_count == 3'h0; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T \| _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35] wire [3:0] _repeat_count_T = {1'h0, repeat_count} + 4'h1; // @[WidthWidget.scala:105:26, :110:24] wire [2:0] _repeat_count_T_1 = _repeat_count_T[2:0]; // @[WidthWidget.scala:110:24] reg [2:0] repeat_sel_sel_sources_0; // @[WidthWidget.scala:187:27] wire [2:0] repeat_sel_sel_a_sel = anonIn_a_bits_address[2:0]; // @[WidthWidget.scala:188:38] reg [2:0] repeat_sel_hold_r; // @[WidthWidget.scala:121:47] wire [2:0] repeat_sel_hold = repeat_first ? repeat_sel_sel_sources_0 : repeat_sel_hold_r; // @[WidthWidget.scala:106:25, :121:{25,47}, :187:27] wire [2:0] _repeat_sel_T = ~repeat_limit; // @[WidthWidget.scala:103:47, :122:18] wire [2:0] repeat_sel = repeat_sel_hold & _repeat_sel_T; // @[WidthWidget.scala:121:25, :122:{16,18}] wire [2:0] repeat_index = repeat_sel \| repeat_count; // @[WidthWidget.scala:105:26, :122:16, :126:24] wire [7:0] _repeat_anonIn_d_bits_data_mux_T = cated_bits_data[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_0 = _repeat_anonIn_d_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_1 = cated_bits_data[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_1 = _repeat_anonIn_d_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_2 = cated_bits_data[23:16]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_2 = _repeat_anonIn_d_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_3 = cated_bits_data[31:24]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_3 = _repeat_anonIn_d_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_4 = cated_bits_data[39:32]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_4 = _repeat_anonIn_d_bits_data_mux_T_4; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_5 = cated_bits_data[47:40]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_5 = _repeat_anonIn_d_bits_data_mux_T_5; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_6 = cated_bits_data[55:48]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_6 = _repeat_anonIn_d_bits_data_mux_T_6; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_7 = cated_bits_data[63:56]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_7 = _repeat_anonIn_d_bits_data_mux_T_7; // @[WidthWidget.scala:128:{43,55}] wire [7:0][7:0] _GEN = {{repeat_anonIn_d_bits_data_mux_7}, {repeat_anonIn_d_bits_data_mux_6}, {repeat_anonIn_d_bits_data_mux_5}, {repeat_anonIn_d_bits_data_mux_4}, {repeat_anonIn_d_bits_data_mux_3}, {repeat_anonIn_d_bits_data_mux_2}, {repeat_anonIn_d_bits_data_mux_1}, {repeat_anonIn_d_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30] assign anonIn_d_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] count <= 3'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonOut_a_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] anonOut_a_bits_mask_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] repeat_count <= 3'h0; // @[WidthWidget.scala:105:26] end else begin // @[WidthWidget.scala:27:9] if (_T) begin // @[Decoupled.scala:51:35] count <= last ? 3'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23] end anonOut_a_bits_data_rdata_written_once <= _anonOut_a_bits_data_T_2 \| anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] anonOut_a_bits_mask_rdata_written_once <= _anonOut_a_bits_mask_T_3 \| anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= repeat_last ? 3'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] end if (_anonOut_a_bits_data_T_2) begin // @[WidthWidget.scala:69:23] anonOut_a_bits_data_rdata_0 <= anonOut_a_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_1 <= anonOut_a_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_2 <= anonOut_a_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_3 <= anonOut_a_bits_data_mdata_3; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_4 <= anonOut_a_bits_data_mdata_4; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_5 <= anonOut_a_bits_data_mdata_5; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_6 <= anonOut_a_bits_data_mdata_6; // @[WidthWidget.scala:66:24, :68:88] end if (_anonOut_a_bits_mask_T_3) begin // @[WidthWidget.scala:69:23] anonOut_a_bits_mask_rdata_0 <= anonOut_a_bits_mask_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_1 <= anonOut_a_bits_mask_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_2 <= anonOut_a_bits_mask_mdata_2; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_3 <= anonOut_a_bits_mask_mdata_3; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_4 <= anonOut_a_bits_mask_mdata_4; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_5 <= anonOut_a_bits_mask_mdata_5; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_6 <= anonOut_a_bits_mask_mdata_6; // @[WidthWidget.scala:66:24, :68:88] end if (_repeat_sel_sel_T) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_0 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (repeat_first) // @[WidthWidget.scala:106:25] repeat_sel_hold_r <= repeat_sel_sel_sources_0; // @[WidthWidget.scala:121:47, :187:27] always @(posedge) TLMonitor_11 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleD_a32d64s1k3z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonOut_d_ready), .io_enq_valid (anonOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (anonOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (anonOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (anonOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_sink (anonOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (anonOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (anonOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (anonOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_sink (cated_bits_sink), .io_deq_bits_denied (cated_bits_denied), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_54 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_108 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_109 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_110 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 1 parameter FORMAT = "uart_tx=%d" parameter WIDTH = 32 extmodule plusarg_reader_111 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "uart_tx_printf=%d" parameter WIDTH = 32	module TLMonitor_54( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_6 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}} wire _in_flight_WIRE : UInt<1>[10] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) connect _in_flight_WIRE[8], UInt<1>(0h0) connect _in_flight_WIRE[9], UInt<1>(0h0) regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_33 = and(_T_31, _T_32) node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_40 = and(_T_38, _T_39) node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_49 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_66 = and(_T_64, _T_65) node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_71 = and(_T_69, _T_70) node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_73 = and(_T_71, _T_72) node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_75 = and(_T_73, _T_74) node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_78 = and(_T_76, _T_77) node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(_T_12, _T_19) node _T_91 = or(_T_90, _T_26) node _T_92 = or(_T_91, _T_33) node _T_93 = or(_T_92, _T_40) node _T_94 = or(_T_93, _T_47) node _T_95 = or(_T_94, _T_54) node _T_96 = or(_T_95, _T_61) node _T_97 = or(_T_96, _T_68) node _T_98 = or(_T_97, _T_75) node _T_99 = or(_T_98, _T_82) node _T_100 = or(_T_99, _T_89) node _T_101 = or(_T_5, _T_100) node _T_102 = asUInt(reset) node _T_103 = eq(_T_102, UInt<1>(0h0)) when _T_103 : node _T_104 = eq(_T_101, UInt<1>(0h0)) when _T_104 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_101, UInt<1>(0h1), "") : assert_1 node _T_105 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_107 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_112 = and(_T_110, _T_111) node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_114 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_121 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_122 = and(_T_120, _T_121) node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_128 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_135 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_136 = and(_T_134, _T_135) node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_142 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_145 = and(_T_143, _T_144) node _T_146 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_149 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_150 = and(_T_148, _T_149) node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_152 = and(_T_150, _T_151) node _T_153 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_156 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_157 = and(_T_155, _T_156) node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_163 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_170 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_177 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_180 = and(_T_178, _T_179) node _T_181 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_184 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_187 = and(_T_185, _T_186) node _T_188 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = or(_T_112, _T_119) node _T_191 = or(_T_190, _T_126) node _T_192 = or(_T_191, _T_133) node _T_193 = or(_T_192, _T_140) node _T_194 = or(_T_193, _T_147) node _T_195 = or(_T_194, _T_154) node _T_196 = or(_T_195, _T_161) node _T_197 = or(_T_196, _T_168) node _T_198 = or(_T_197, _T_175) node _T_199 = or(_T_198, _T_182) node _T_200 = or(_T_199, _T_189) node _T_201 = or(_T_105, _T_200) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_201, UInt<1>(0h1), "") : assert_2 node _T_205 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_206 = or(_T_205, UInt<1>(0h0)) node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_T_206, UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_206, UInt<1>(0h1), "") : assert_3 node _T_210 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_211 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_212 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_213 = and(_T_211, _T_212) node _T_214 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_215 = and(_T_213, _T_214) node _T_216 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_219 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_220 = and(_T_218, _T_219) node _T_221 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_226 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_229 = and(_T_227, _T_228) node _T_230 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_233 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_236 = and(_T_234, _T_235) node _T_237 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_240 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _T_242 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_243 = and(_T_241, _T_242) node _T_244 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_247 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_248 = and(_T_246, _T_247) node _T_249 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_254 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_255 = and(_T_253, _T_254) node _T_256 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_257 = and(_T_255, _T_256) node _T_258 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_261 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_268 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_269 = and(_T_267, _T_268) node _T_270 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_271 = and(_T_269, _T_270) node _T_272 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_273 = and(_T_271, _T_272) node _T_274 = or(_T_217, _T_224) node _T_275 = or(_T_274, _T_231) node _T_276 = or(_T_275, _T_238) node _T_277 = or(_T_276, _T_245) node _T_278 = or(_T_277, _T_252) node _T_279 = or(_T_278, _T_259) node _T_280 = or(_T_279, _T_266) node _T_281 = or(_T_280, _T_273) node _T_282 = or(_T_210, _T_281) node _T_283 = asUInt(reset) node _T_284 = eq(_T_283, UInt<1>(0h0)) when _T_284 : node _T_285 = eq(_T_282, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_282, UInt<1>(0h1), "") : assert_4 node _T_286 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_287 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_288 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_289 = and(_T_287, _T_288) node _T_290 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_291 = and(_T_289, _T_290) node _T_292 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_295 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_302 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_303 = and(_T_301, _T_302) node _T_304 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_305 = and(_T_303, _T_304) node _T_306 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_309 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_310 = and(_T_308, _T_309) node _T_311 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_312 = and(_T_310, _T_311) node _T_313 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_316 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_317 = and(_T_315, _T_316) node _T_318 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_323 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_328 = and(_T_326, _T_327) node _T_329 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_330 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_331 = and(_T_329, _T_330) node _T_332 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_335 = and(_T_333, _T_334) node _T_336 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_337 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_338 = and(_T_336, _T_337) node _T_339 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_340 = and(_T_338, _T_339) node _T_341 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_342 = and(_T_340, _T_341) node _T_343 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_344 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_345 = and(_T_343, _T_344) node _T_346 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_349 = and(_T_347, _T_348) node _T_350 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_351 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_354 = and(_T_352, _T_353) node _T_355 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_356 = and(_T_354, _T_355) node _T_357 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_358 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_359 = and(_T_357, _T_358) node _T_360 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_361 = and(_T_359, _T_360) node _T_362 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_363 = and(_T_361, _T_362) node _T_364 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_365 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_366 = and(_T_364, _T_365) node _T_367 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_368 = and(_T_366, _T_367) node _T_369 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(_T_293, _T_300) node _T_372 = or(_T_371, _T_307) node _T_373 = or(_T_372, _T_314) node _T_374 = or(_T_373, _T_321) node _T_375 = or(_T_374, _T_328) node _T_376 = or(_T_375, _T_335) node _T_377 = or(_T_376, _T_342) node _T_378 = or(_T_377, _T_349) node _T_379 = or(_T_378, _T_356) node _T_380 = or(_T_379, _T_363) node _T_381 = or(_T_380, _T_370) node _T_382 = or(_T_286, _T_381) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_382, UInt<1>(0h1), "") : assert_5 node _T_386 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_387 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_388 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_389 = and(_T_387, _T_388) node _T_390 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_391 = and(_T_389, _T_390) node _T_392 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_395 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_398 = and(_T_396, _T_397) node _T_399 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_400 = and(_T_398, _T_399) node _T_401 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_402 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_405 = and(_T_403, _T_404) node _T_406 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_409 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_414 = and(_T_412, _T_413) node _T_415 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_416 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_421 = and(_T_419, _T_420) node _T_422 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_423 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_428 = and(_T_426, _T_427) node _T_429 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_430 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_435 = and(_T_433, _T_434) node _T_436 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_437 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_440 = and(_T_438, _T_439) node _T_441 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_442 = and(_T_440, _T_441) node _T_443 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_444 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_445 = and(_T_443, _T_444) node _T_446 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_447 = and(_T_445, _T_446) node _T_448 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_449 = and(_T_447, _T_448) node _T_450 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_451 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_452 = and(_T_450, _T_451) node _T_453 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_454 = and(_T_452, _T_453) node _T_455 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_456 = and(_T_454, _T_455) node _T_457 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_458 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_461 = and(_T_459, _T_460) node _T_462 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_463 = and(_T_461, _T_462) node _T_464 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_465 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_466 = and(_T_464, _T_465) node _T_467 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_470 = and(_T_468, _T_469) node _T_471 = or(_T_393, _T_400) node _T_472 = or(_T_471, _T_407) node _T_473 = or(_T_472, _T_414) node _T_474 = or(_T_473, _T_421) node _T_475 = or(_T_474, _T_428) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_442) node _T_478 = or(_T_477, _T_449) node _T_479 = or(_T_478, _T_456) node _T_480 = or(_T_479, _T_463) node _T_481 = or(_T_480, _T_470) node _T_482 = or(_T_386, _T_481) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_482, UInt<1>(0h1), "") : assert_6 node _T_486 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_487 = or(_T_486, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_487, UInt<1>(0h1), "") : assert_7 node _T_491 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_492 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_493 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_496 = and(_T_494, _T_495) node _T_497 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_498 = and(_T_496, _T_497) node _T_499 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_500 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_503 = and(_T_501, _T_502) node _T_504 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_505 = and(_T_503, _T_504) node _T_506 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_507 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_510 = and(_T_508, _T_509) node _T_511 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_512 = and(_T_510, _T_511) node _T_513 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_514 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_517 = and(_T_515, _T_516) node _T_518 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_519 = and(_T_517, _T_518) node _T_520 = or(_T_498, _T_505) node _T_521 = or(_T_520, _T_512) node _T_522 = or(_T_521, _T_519) node _T_523 = or(_T_491, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_523, UInt<1>(0h1), "") : assert_8 node _T_527 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_528 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_529 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_530 = and(_T_528, _T_529) node _T_531 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_532 = and(_T_530, _T_531) node _T_533 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_534 = and(_T_532, _T_533) node _T_535 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_536 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_539 = and(_T_537, _T_538) node _T_540 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_541 = and(_T_539, _T_540) node _T_542 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_543 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _T_547 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_548 = and(_T_546, _T_547) node _T_549 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_550 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_553 = and(_T_551, _T_552) node _T_554 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) node _T_556 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_557 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_558 = and(_T_556, _T_557) node _T_559 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_560 = and(_T_558, _T_559) node _T_561 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_562 = and(_T_560, _T_561) node _T_563 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_564 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_565 = and(_T_563, _T_564) node _T_566 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_567 = and(_T_565, _T_566) node _T_568 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_571 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_572 = and(_T_570, _T_571) node _T_573 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_574 = and(_T_572, _T_573) node _T_575 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_576 = and(_T_574, _T_575) node _T_577 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_578 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_579 = and(_T_577, _T_578) node _T_580 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_581 = and(_T_579, _T_580) node _T_582 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_583 = and(_T_581, _T_582) node _T_584 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_585 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_588 = and(_T_586, _T_587) node _T_589 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_590 = and(_T_588, _T_589) node _T_591 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_592 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_593 = and(_T_591, _T_592) node _T_594 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_595 = and(_T_593, _T_594) node _T_596 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_597 = and(_T_595, _T_596) node _T_598 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_599 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_600 = and(_T_598, _T_599) node _T_601 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_602 = and(_T_600, _T_601) node _T_603 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_604 = and(_T_602, _T_603) node _T_605 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_606 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_609 = and(_T_607, _T_608) node _T_610 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_611 = and(_T_609, _T_610) node _T_612 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_613 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_614 = and(_T_612, _T_613) node _T_615 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_616 = and(_T_614, _T_615) node _T_617 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_620 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_621 = and(_T_619, _T_620) node _T_622 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_623 = and(_T_621, _T_622) node _T_624 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_625 = and(_T_623, _T_624) node _T_626 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_627 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_628 = and(_T_626, _T_627) node _T_629 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_630 = and(_T_628, _T_629) node _T_631 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_632 = and(_T_630, _T_631) node _T_633 = or(_T_534, _T_541) node _T_634 = or(_T_633, _T_548) node _T_635 = or(_T_634, _T_555) node _T_636 = or(_T_635, _T_562) node _T_637 = or(_T_636, _T_569) node _T_638 = or(_T_637, _T_576) node _T_639 = or(_T_638, _T_583) node _T_640 = or(_T_639, _T_590) node _T_641 = or(_T_640, _T_597) node _T_642 = or(_T_641, _T_604) node _T_643 = or(_T_642, _T_611) node _T_644 = or(_T_643, _T_618) node _T_645 = or(_T_644, _T_625) node _T_646 = or(_T_645, _T_632) node _T_647 = or(_T_527, _T_646) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_9 assert(clock, _T_647, UInt<1>(0h1), "") : assert_9 node _T_651 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9)) node _T_652 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_653 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_654 = and(_T_652, _T_653) node _T_655 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_656 = and(_T_654, _T_655) node _T_657 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_658 = and(_T_656, _T_657) node _T_659 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_660 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_661 = and(_T_659, _T_660) node _T_662 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_663 = and(_T_661, _T_662) node _T_664 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_665 = and(_T_663, _T_664) node _T_666 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_667 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_668 = and(_T_666, _T_667) node _T_669 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_670 = and(_T_668, _T_669) node _T_671 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_672 = and(_T_670, _T_671) node _T_673 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_674 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_675 = and(_T_673, _T_674) node _T_676 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_677 = and(_T_675, _T_676) node _T_678 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_679 = and(_T_677, _T_678) node _T_680 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_681 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_682 = and(_T_680, _T_681) node _T_683 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_684 = and(_T_682, _T_683) node _T_685 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_686 = and(_T_684, _T_685) node _T_687 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_688 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_689 = and(_T_687, _T_688) node _T_690 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_691 = and(_T_689, _T_690) node _T_692 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_693 = and(_T_691, _T_692) node _T_694 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_695 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_696 = and(_T_694, _T_695) node _T_697 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_698 = and(_T_696, _T_697) node _T_699 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_700 = and(_T_698, _T_699) node _T_701 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_702 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_703 = and(_T_701, _T_702) node _T_704 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_705 = and(_T_703, _T_704) node _T_706 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_707 = and(_T_705, _T_706) node _T_708 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_709 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_710 = and(_T_708, _T_709) node _T_711 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_714 = and(_T_712, _T_713) node _T_715 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_716 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_717 = and(_T_715, _T_716) node _T_718 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_719 = and(_T_717, _T_718) node _T_720 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_721 = and(_T_719, _T_720) node _T_722 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_723 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_726 = and(_T_724, _T_725) node _T_727 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_728 = and(_T_726, _T_727) node _T_729 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_730 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_731 = and(_T_729, _T_730) node _T_732 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_733 = and(_T_731, _T_732) node _T_734 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_735 = and(_T_733, _T_734) node _T_736 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_737 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_738 = and(_T_736, _T_737) node _T_739 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_740 = and(_T_738, _T_739) node _T_741 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_742 = and(_T_740, _T_741) node _T_743 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_744 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_745 = and(_T_743, _T_744) node _T_746 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_751 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_756 = and(_T_754, _T_755) node _T_757 = or(_T_658, _T_665) node _T_758 = or(_T_757, _T_672) node _T_759 = or(_T_758, _T_679) node _T_760 = or(_T_759, _T_686) node _T_761 = or(_T_760, _T_693) node _T_762 = or(_T_761, _T_700) node _T_763 = or(_T_762, _T_707) node _T_764 = or(_T_763, _T_714) node _T_765 = or(_T_764, _T_721) node _T_766 = or(_T_765, _T_728) node _T_767 = or(_T_766, _T_735) node _T_768 = or(_T_767, _T_742) node _T_769 = or(_T_768, _T_749) node _T_770 = or(_T_769, _T_756) node _T_771 = or(_T_651, _T_770) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_10 assert(clock, _T_771, UInt<1>(0h1), "") : assert_10	module NoCMonitor_6( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h2; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h6; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module TestHarness : input clock : Clock input reset : UInt<1> output io : { success : UInt<1>} wire harnessBinderClock : Clock wire harnessBinderReset : Reset wire success : UInt<1> connect success, UInt<1>(0h0) connect io.success, success inst chiptop0 of ChipTop inst uart_sim_0_uartno0 of UARTAdapter connect uart_sim_0_uartno0.clock, harnessBinderClock connect uart_sim_0_uartno0.reset, harnessBinderReset connect uart_sim_0_uartno0.io.uart.txd, chiptop0.uart_0.txd connect chiptop0.uart_0.rxd, uart_sim_0_uartno0.io.uart.rxd inst simdram of SimDRAM connect simdram.clock, chiptop0.axi4_mem_0.clock node _simdram_io_reset_T = asAsyncReset(harnessBinderReset) connect simdram.reset, _simdram_io_reset_T connect chiptop0.axi4_mem_0.bits.r.bits.last, simdram.axi.r.bits.last connect chiptop0.axi4_mem_0.bits.r.bits.resp, simdram.axi.r.bits.resp connect chiptop0.axi4_mem_0.bits.r.bits.data, simdram.axi.r.bits.data connect chiptop0.axi4_mem_0.bits.r.bits.id, simdram.axi.r.bits.id connect chiptop0.axi4_mem_0.bits.r.valid, simdram.axi.r.valid connect simdram.axi.r.ready, chiptop0.axi4_mem_0.bits.r.ready connect simdram.axi.ar.bits.qos, chiptop0.axi4_mem_0.bits.ar.bits.qos connect simdram.axi.ar.bits.prot, chiptop0.axi4_mem_0.bits.ar.bits.prot connect simdram.axi.ar.bits.cache, chiptop0.axi4_mem_0.bits.ar.bits.cache connect simdram.axi.ar.bits.lock, chiptop0.axi4_mem_0.bits.ar.bits.lock connect simdram.axi.ar.bits.burst, chiptop0.axi4_mem_0.bits.ar.bits.burst connect simdram.axi.ar.bits.size, chiptop0.axi4_mem_0.bits.ar.bits.size connect simdram.axi.ar.bits.len, chiptop0.axi4_mem_0.bits.ar.bits.len connect simdram.axi.ar.bits.addr, chiptop0.axi4_mem_0.bits.ar.bits.addr connect simdram.axi.ar.bits.id, chiptop0.axi4_mem_0.bits.ar.bits.id connect simdram.axi.ar.valid, chiptop0.axi4_mem_0.bits.ar.valid connect chiptop0.axi4_mem_0.bits.ar.ready, simdram.axi.ar.ready connect chiptop0.axi4_mem_0.bits.b.bits.resp, simdram.axi.b.bits.resp connect chiptop0.axi4_mem_0.bits.b.bits.id, simdram.axi.b.bits.id connect chiptop0.axi4_mem_0.bits.b.valid, simdram.axi.b.valid connect simdram.axi.b.ready, chiptop0.axi4_mem_0.bits.b.ready connect simdram.axi.w.bits.last, chiptop0.axi4_mem_0.bits.w.bits.last connect simdram.axi.w.bits.strb, chiptop0.axi4_mem_0.bits.w.bits.strb connect simdram.axi.w.bits.data, chiptop0.axi4_mem_0.bits.w.bits.data connect simdram.axi.w.valid, chiptop0.axi4_mem_0.bits.w.valid connect chiptop0.axi4_mem_0.bits.w.ready, simdram.axi.w.ready connect simdram.axi.aw.bits.qos, chiptop0.axi4_mem_0.bits.aw.bits.qos connect simdram.axi.aw.bits.prot, chiptop0.axi4_mem_0.bits.aw.bits.prot connect simdram.axi.aw.bits.cache, chiptop0.axi4_mem_0.bits.aw.bits.cache connect simdram.axi.aw.bits.lock, chiptop0.axi4_mem_0.bits.aw.bits.lock connect simdram.axi.aw.bits.burst, chiptop0.axi4_mem_0.bits.aw.bits.burst connect simdram.axi.aw.bits.size, chiptop0.axi4_mem_0.bits.aw.bits.size connect simdram.axi.aw.bits.len, chiptop0.axi4_mem_0.bits.aw.bits.len connect simdram.axi.aw.bits.addr, chiptop0.axi4_mem_0.bits.aw.bits.addr connect simdram.axi.aw.bits.id, chiptop0.axi4_mem_0.bits.aw.bits.id connect simdram.axi.aw.valid, chiptop0.axi4_mem_0.bits.aw.valid connect chiptop0.axi4_mem_0.bits.aw.ready, simdram.axi.aw.ready inst simdram_1 of SimDRAM_1 connect simdram_1.clock, chiptop0.axi4_mem_1.clock node _simdram_io_reset_T_1 = asAsyncReset(harnessBinderReset) connect simdram_1.reset, _simdram_io_reset_T_1 connect chiptop0.axi4_mem_1.bits.r.bits.last, simdram_1.axi.r.bits.last connect chiptop0.axi4_mem_1.bits.r.bits.resp, simdram_1.axi.r.bits.resp connect chiptop0.axi4_mem_1.bits.r.bits.data, simdram_1.axi.r.bits.data connect chiptop0.axi4_mem_1.bits.r.bits.id, simdram_1.axi.r.bits.id connect chiptop0.axi4_mem_1.bits.r.valid, simdram_1.axi.r.valid connect simdram_1.axi.r.ready, chiptop0.axi4_mem_1.bits.r.ready connect simdram_1.axi.ar.bits.qos, chiptop0.axi4_mem_1.bits.ar.bits.qos connect simdram_1.axi.ar.bits.prot, chiptop0.axi4_mem_1.bits.ar.bits.prot connect simdram_1.axi.ar.bits.cache, chiptop0.axi4_mem_1.bits.ar.bits.cache connect simdram_1.axi.ar.bits.lock, chiptop0.axi4_mem_1.bits.ar.bits.lock connect simdram_1.axi.ar.bits.burst, chiptop0.axi4_mem_1.bits.ar.bits.burst connect simdram_1.axi.ar.bits.size, chiptop0.axi4_mem_1.bits.ar.bits.size connect simdram_1.axi.ar.bits.len, chiptop0.axi4_mem_1.bits.ar.bits.len connect simdram_1.axi.ar.bits.addr, chiptop0.axi4_mem_1.bits.ar.bits.addr connect simdram_1.axi.ar.bits.id, chiptop0.axi4_mem_1.bits.ar.bits.id connect simdram_1.axi.ar.valid, chiptop0.axi4_mem_1.bits.ar.valid connect chiptop0.axi4_mem_1.bits.ar.ready, simdram_1.axi.ar.ready connect chiptop0.axi4_mem_1.bits.b.bits.resp, simdram_1.axi.b.bits.resp connect chiptop0.axi4_mem_1.bits.b.bits.id, simdram_1.axi.b.bits.id connect chiptop0.axi4_mem_1.bits.b.valid, simdram_1.axi.b.valid connect simdram_1.axi.b.ready, chiptop0.axi4_mem_1.bits.b.ready connect simdram_1.axi.w.bits.last, chiptop0.axi4_mem_1.bits.w.bits.last connect simdram_1.axi.w.bits.strb, chiptop0.axi4_mem_1.bits.w.bits.strb connect simdram_1.axi.w.bits.data, chiptop0.axi4_mem_1.bits.w.bits.data connect simdram_1.axi.w.valid, chiptop0.axi4_mem_1.bits.w.valid connect chiptop0.axi4_mem_1.bits.w.ready, simdram_1.axi.w.ready connect simdram_1.axi.aw.bits.qos, chiptop0.axi4_mem_1.bits.aw.bits.qos connect simdram_1.axi.aw.bits.prot, chiptop0.axi4_mem_1.bits.aw.bits.prot connect simdram_1.axi.aw.bits.cache, chiptop0.axi4_mem_1.bits.aw.bits.cache connect simdram_1.axi.aw.bits.lock, chiptop0.axi4_mem_1.bits.aw.bits.lock connect simdram_1.axi.aw.bits.burst, chiptop0.axi4_mem_1.bits.aw.bits.burst connect simdram_1.axi.aw.bits.size, chiptop0.axi4_mem_1.bits.aw.bits.size connect simdram_1.axi.aw.bits.len, chiptop0.axi4_mem_1.bits.aw.bits.len connect simdram_1.axi.aw.bits.addr, chiptop0.axi4_mem_1.bits.aw.bits.addr connect simdram_1.axi.aw.bits.id, chiptop0.axi4_mem_1.bits.aw.bits.id connect simdram_1.axi.aw.valid, chiptop0.axi4_mem_1.bits.aw.valid connect chiptop0.axi4_mem_1.bits.aw.ready, simdram_1.axi.aw.ready inst simdram_2 of SimDRAM_2 connect simdram_2.clock, chiptop0.axi4_mem_2.clock node _simdram_io_reset_T_2 = asAsyncReset(harnessBinderReset) connect simdram_2.reset, _simdram_io_reset_T_2 connect chiptop0.axi4_mem_2.bits.r.bits.last, simdram_2.axi.r.bits.last connect chiptop0.axi4_mem_2.bits.r.bits.resp, simdram_2.axi.r.bits.resp connect chiptop0.axi4_mem_2.bits.r.bits.data, simdram_2.axi.r.bits.data connect chiptop0.axi4_mem_2.bits.r.bits.id, simdram_2.axi.r.bits.id connect chiptop0.axi4_mem_2.bits.r.valid, simdram_2.axi.r.valid connect simdram_2.axi.r.ready, chiptop0.axi4_mem_2.bits.r.ready connect simdram_2.axi.ar.bits.qos, chiptop0.axi4_mem_2.bits.ar.bits.qos connect simdram_2.axi.ar.bits.prot, chiptop0.axi4_mem_2.bits.ar.bits.prot connect simdram_2.axi.ar.bits.cache, chiptop0.axi4_mem_2.bits.ar.bits.cache connect simdram_2.axi.ar.bits.lock, chiptop0.axi4_mem_2.bits.ar.bits.lock connect simdram_2.axi.ar.bits.burst, chiptop0.axi4_mem_2.bits.ar.bits.burst connect simdram_2.axi.ar.bits.size, chiptop0.axi4_mem_2.bits.ar.bits.size connect simdram_2.axi.ar.bits.len, chiptop0.axi4_mem_2.bits.ar.bits.len connect simdram_2.axi.ar.bits.addr, chiptop0.axi4_mem_2.bits.ar.bits.addr connect simdram_2.axi.ar.bits.id, chiptop0.axi4_mem_2.bits.ar.bits.id connect simdram_2.axi.ar.valid, chiptop0.axi4_mem_2.bits.ar.valid connect chiptop0.axi4_mem_2.bits.ar.ready, simdram_2.axi.ar.ready connect chiptop0.axi4_mem_2.bits.b.bits.resp, simdram_2.axi.b.bits.resp connect chiptop0.axi4_mem_2.bits.b.bits.id, simdram_2.axi.b.bits.id connect chiptop0.axi4_mem_2.bits.b.valid, simdram_2.axi.b.valid connect simdram_2.axi.b.ready, chiptop0.axi4_mem_2.bits.b.ready connect simdram_2.axi.w.bits.last, chiptop0.axi4_mem_2.bits.w.bits.last connect simdram_2.axi.w.bits.strb, chiptop0.axi4_mem_2.bits.w.bits.strb connect simdram_2.axi.w.bits.data, chiptop0.axi4_mem_2.bits.w.bits.data connect simdram_2.axi.w.valid, chiptop0.axi4_mem_2.bits.w.valid connect chiptop0.axi4_mem_2.bits.w.ready, simdram_2.axi.w.ready connect simdram_2.axi.aw.bits.qos, chiptop0.axi4_mem_2.bits.aw.bits.qos connect simdram_2.axi.aw.bits.prot, chiptop0.axi4_mem_2.bits.aw.bits.prot connect simdram_2.axi.aw.bits.cache, chiptop0.axi4_mem_2.bits.aw.bits.cache connect simdram_2.axi.aw.bits.lock, chiptop0.axi4_mem_2.bits.aw.bits.lock connect simdram_2.axi.aw.bits.burst, chiptop0.axi4_mem_2.bits.aw.bits.burst connect simdram_2.axi.aw.bits.size, chiptop0.axi4_mem_2.bits.aw.bits.size connect simdram_2.axi.aw.bits.len, chiptop0.axi4_mem_2.bits.aw.bits.len connect simdram_2.axi.aw.bits.addr, chiptop0.axi4_mem_2.bits.aw.bits.addr connect simdram_2.axi.aw.bits.id, chiptop0.axi4_mem_2.bits.aw.bits.id connect simdram_2.axi.aw.valid, chiptop0.axi4_mem_2.bits.aw.valid connect chiptop0.axi4_mem_2.bits.aw.ready, simdram_2.axi.aw.ready inst simdram_3 of SimDRAM_3 connect simdram_3.clock, chiptop0.axi4_mem_3.clock node _simdram_io_reset_T_3 = asAsyncReset(harnessBinderReset) connect simdram_3.reset, _simdram_io_reset_T_3 connect chiptop0.axi4_mem_3.bits.r.bits.last, simdram_3.axi.r.bits.last connect chiptop0.axi4_mem_3.bits.r.bits.resp, simdram_3.axi.r.bits.resp connect chiptop0.axi4_mem_3.bits.r.bits.data, simdram_3.axi.r.bits.data connect chiptop0.axi4_mem_3.bits.r.bits.id, simdram_3.axi.r.bits.id connect chiptop0.axi4_mem_3.bits.r.valid, simdram_3.axi.r.valid connect simdram_3.axi.r.ready, chiptop0.axi4_mem_3.bits.r.ready connect simdram_3.axi.ar.bits.qos, chiptop0.axi4_mem_3.bits.ar.bits.qos connect simdram_3.axi.ar.bits.prot, chiptop0.axi4_mem_3.bits.ar.bits.prot connect simdram_3.axi.ar.bits.cache, chiptop0.axi4_mem_3.bits.ar.bits.cache connect simdram_3.axi.ar.bits.lock, chiptop0.axi4_mem_3.bits.ar.bits.lock connect simdram_3.axi.ar.bits.burst, chiptop0.axi4_mem_3.bits.ar.bits.burst connect simdram_3.axi.ar.bits.size, chiptop0.axi4_mem_3.bits.ar.bits.size connect simdram_3.axi.ar.bits.len, chiptop0.axi4_mem_3.bits.ar.bits.len connect simdram_3.axi.ar.bits.addr, chiptop0.axi4_mem_3.bits.ar.bits.addr connect simdram_3.axi.ar.bits.id, chiptop0.axi4_mem_3.bits.ar.bits.id connect simdram_3.axi.ar.valid, chiptop0.axi4_mem_3.bits.ar.valid connect chiptop0.axi4_mem_3.bits.ar.ready, simdram_3.axi.ar.ready connect chiptop0.axi4_mem_3.bits.b.bits.resp, simdram_3.axi.b.bits.resp connect chiptop0.axi4_mem_3.bits.b.bits.id, simdram_3.axi.b.bits.id connect chiptop0.axi4_mem_3.bits.b.valid, simdram_3.axi.b.valid connect simdram_3.axi.b.ready, chiptop0.axi4_mem_3.bits.b.ready connect simdram_3.axi.w.bits.last, chiptop0.axi4_mem_3.bits.w.bits.last connect simdram_3.axi.w.bits.strb, chiptop0.axi4_mem_3.bits.w.bits.strb connect simdram_3.axi.w.bits.data, chiptop0.axi4_mem_3.bits.w.bits.data connect simdram_3.axi.w.valid, chiptop0.axi4_mem_3.bits.w.valid connect chiptop0.axi4_mem_3.bits.w.ready, simdram_3.axi.w.ready connect simdram_3.axi.aw.bits.qos, chiptop0.axi4_mem_3.bits.aw.bits.qos connect simdram_3.axi.aw.bits.prot, chiptop0.axi4_mem_3.bits.aw.bits.prot connect simdram_3.axi.aw.bits.cache, chiptop0.axi4_mem_3.bits.aw.bits.cache connect simdram_3.axi.aw.bits.lock, chiptop0.axi4_mem_3.bits.aw.bits.lock connect simdram_3.axi.aw.bits.burst, chiptop0.axi4_mem_3.bits.aw.bits.burst connect simdram_3.axi.aw.bits.size, chiptop0.axi4_mem_3.bits.aw.bits.size connect simdram_3.axi.aw.bits.len, chiptop0.axi4_mem_3.bits.aw.bits.len connect simdram_3.axi.aw.bits.addr, chiptop0.axi4_mem_3.bits.aw.bits.addr connect simdram_3.axi.aw.bits.id, chiptop0.axi4_mem_3.bits.aw.bits.id connect simdram_3.axi.aw.valid, chiptop0.axi4_mem_3.bits.aw.valid connect chiptop0.axi4_mem_3.bits.aw.ready, simdram_3.axi.aw.ready inst plusarg_reader of plusarg_reader_215 connect chiptop0.custom_boot, plusarg_reader.out wire dtm_success : UInt<1> connect dtm_success, UInt<1>(0h0) when dtm_success : connect success, UInt<1>(0h1) wire jtag_wire : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}} connect jtag_wire.TDO.data, chiptop0.jtag.TDO connect jtag_wire.TDO.driven, UInt<1>(0h1) connect chiptop0.jtag.TCK, jtag_wire.TCK connect chiptop0.jtag.TMS, jtag_wire.TMS connect chiptop0.jtag.TDI, jtag_wire.TDI inst jtag of SimJTAG node _T = asUInt(harnessBinderReset) node _T_1 = asUInt(harnessBinderReset) node _T_2 = not(_T_1) connect jtag_wire.TCK, jtag.jtag.TCK connect jtag_wire.TMS, jtag.jtag.TMS connect jtag_wire.TDI, jtag.jtag.TDI connect jtag.jtag.TDO.driven, jtag_wire.TDO.driven connect jtag.jtag.TDO.data, jtag_wire.TDO.data connect jtag.clock, harnessBinderClock connect jtag.reset, _T inst plusarg_reader_1 of plusarg_reader_216 connect jtag.enable, plusarg_reader_1.out connect jtag.init_done, _T_2 node _dtm_success_T = eq(jtag.exit, UInt<1>(0h1)) connect dtm_success, _dtm_success_T node _T_3 = lt(jtag.exit, UInt<2>(0h2)) node _T_4 = dshr(jtag.exit, UInt<1>(0h1)) node _T_5 = asUInt(harnessBinderReset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_3, UInt<1>(0h0)) when _T_7 : printf(harnessBinderClock, UInt<1>(0h1), "Assertion failed: * FAILED * (exit code = %d)\n\n at Periphery.scala:236 assert(io.exit < 2.U, \"* FAILED * (exit code = %%%%d)\\n\", io.exit >> 1.U)\n", _T_4) : printf assert(harnessBinderClock, _T_3, UInt<1>(0h1), "") : assert wire chiptop0_clock_uncore_clock : Clock connect chiptop0.clock_uncore, chiptop0_clock_uncore_clock node _chiptop0_reset_io_T = asAsyncReset(reset) connect chiptop0.reset_io, _chiptop0_reset_io_T connect chiptop0.serial_tl_0.clock_in, harnessBinderClock inst ram of SerialRAM connect ram.clock, harnessBinderClock connect ram.reset, harnessBinderReset connect ram.io.ser.in, chiptop0.serial_tl_0.out connect chiptop0.serial_tl_0.in, ram.io.ser.out inst success_exit_sim of SimTSI connect success_exit_sim.clock, harnessBinderClock connect success_exit_sim.reset, harnessBinderReset connect success_exit_sim.tsi.out.bits, ram.io.tsi.out.bits connect success_exit_sim.tsi.out.valid, ram.io.tsi.out.valid connect ram.io.tsi.out.ready, success_exit_sim.tsi.out.ready connect ram.io.tsi.in.bits, success_exit_sim.tsi.in.bits connect ram.io.tsi.in.valid, success_exit_sim.tsi.in.valid connect success_exit_sim.tsi.in.ready, ram.io.tsi.in.ready node success_1 = eq(success_exit_sim.exit, UInt<1>(0h1)) node success_error = geq(success_exit_sim.exit, UInt<2>(0h2)) node _success_T = eq(success_error, UInt<1>(0h0)) node _success_T_1 = dshr(success_exit_sim.exit, UInt<1>(0h1)) node _success_T_2 = asUInt(harnessBinderReset) node _success_T_3 = eq(_success_T_2, UInt<1>(0h0)) when _success_T_3 : node _success_T_4 = eq(_success_T, UInt<1>(0h0)) when _success_T_4 : printf(harnessBinderClock, UInt<1>(0h1), "Assertion failed: * FAILED * (exit code = %d)\n\n at SimTSI.scala:21 assert(!error, \"* FAILED * (exit code = %%%%d)\\n\", exit >> 1.U)\n", _success_T_1) : success_printf assert(harnessBinderClock, _success_T, UInt<1>(0h1), "") : success_assert when success_1 : connect success, UInt<1>(0h1) wire harnessBinderClk : Clock connect harnessBinderClock, harnessBinderClk inst harnessBinderReset_catcher of ResetCatchAndSync_d3_4 connect harnessBinderReset_catcher.clock, harnessBinderClk connect harnessBinderReset_catcher.reset, reset wire _harnessBinderReset_catcher_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>} connect _harnessBinderReset_catcher_io_psd_WIRE.test_mode_reset, UInt<1>(0h0) connect _harnessBinderReset_catcher_io_psd_WIRE.test_mode, UInt<1>(0h0) wire _harnessBinderReset_catcher_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>} connect _harnessBinderReset_catcher_io_psd_WIRE_1, _harnessBinderReset_catcher_io_psd_WIRE connect harnessBinderReset_catcher.io.psd, _harnessBinderReset_catcher_io_psd_WIRE_1 connect harnessBinderReset, harnessBinderReset_catcher.io.sync_reset inst source of ClockSourceAtFreqMHz connect source.power, UInt<1>(0h1) connect source.gate, UInt<1>(0h0) connect chiptop0_clock_uncore_clock, source.clk inst source_1 of ClockSourceAtFreqMHz_1 connect source_1.power, UInt<1>(0h1) connect source_1.gate, UInt<1>(0h0) connect harnessBinderClk, source_1.clk	module TestHarness( // @[TestHarness.scala:19:7] input clock, // @[TestHarness.scala:19:7] input reset, // @[TestHarness.scala:19:7] output io_success // @[TestHarness.scala:20:14] ); wire _success_exit_sim_tsi_in_valid; // @[SimTSI.scala:12:23] wire [31:0] _success_exit_sim_tsi_in_bits; // @[SimTSI.scala:12:23] wire _success_exit_sim_tsi_out_ready; // @[SimTSI.scala:12:23] wire [31:0] _success_exit_sim_exit; // @[SimTSI.scala:12:23] wire _ram_io_ser_in_ready; // @[HarnessBinders.scala:253:27] wire _ram_io_ser_out_valid; // @[HarnessBinders.scala:253:27] wire [31:0] _ram_io_ser_out_bits_phit; // @[HarnessBinders.scala:253:27] wire _ram_io_tsi_in_ready; // @[HarnessBinders.scala:253:27] wire _ram_io_tsi_out_valid; // @[HarnessBinders.scala:253:27] wire [31:0] _ram_io_tsi_out_bits; // @[HarnessBinders.scala:253:27] wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _jtag_exit; // @[HarnessBinders.scala:184:22] wire _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _simdram_3_axi_aw_ready; // @[HarnessBinders.scala:123:21] wire _simdram_3_axi_w_ready; // @[HarnessBinders.scala:123:21] wire _simdram_3_axi_b_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_3_axi_b_bits_id; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_3_axi_b_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_3_axi_ar_ready; // @[HarnessBinders.scala:123:21] wire _simdram_3_axi_r_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_3_axi_r_bits_id; // @[HarnessBinders.scala:123:21] wire [63:0] _simdram_3_axi_r_bits_data; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_3_axi_r_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_3_axi_r_bits_last; // @[HarnessBinders.scala:123:21] wire _simdram_2_axi_aw_ready; // @[HarnessBinders.scala:123:21] wire _simdram_2_axi_w_ready; // @[HarnessBinders.scala:123:21] wire _simdram_2_axi_b_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_2_axi_b_bits_id; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_2_axi_b_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_2_axi_ar_ready; // @[HarnessBinders.scala:123:21] wire _simdram_2_axi_r_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_2_axi_r_bits_id; // @[HarnessBinders.scala:123:21] wire [63:0] _simdram_2_axi_r_bits_data; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_2_axi_r_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_2_axi_r_bits_last; // @[HarnessBinders.scala:123:21] wire _simdram_1_axi_aw_ready; // @[HarnessBinders.scala:123:21] wire _simdram_1_axi_w_ready; // @[HarnessBinders.scala:123:21] wire _simdram_1_axi_b_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_1_axi_b_bits_id; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_1_axi_b_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_1_axi_ar_ready; // @[HarnessBinders.scala:123:21] wire _simdram_1_axi_r_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_1_axi_r_bits_id; // @[HarnessBinders.scala:123:21] wire [63:0] _simdram_1_axi_r_bits_data; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_1_axi_r_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_1_axi_r_bits_last; // @[HarnessBinders.scala:123:21] wire _simdram_axi_aw_ready; // @[HarnessBinders.scala:123:21] wire _simdram_axi_w_ready; // @[HarnessBinders.scala:123:21] wire _simdram_axi_b_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_axi_b_bits_id; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_axi_b_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_axi_ar_ready; // @[HarnessBinders.scala:123:21] wire _simdram_axi_r_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_axi_r_bits_id; // @[HarnessBinders.scala:123:21] wire [63:0] _simdram_axi_r_bits_data; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_axi_r_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_axi_r_bits_last; // @[HarnessBinders.scala:123:21] wire _uart_sim_0_uartno0_io_uart_rxd; // @[SimUART.scala:76:28] wire _chiptop0_uart_0_txd; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_clock; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_aw_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_0_bits_aw_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_0_bits_aw_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_0_bits_aw_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_0_bits_aw_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_0_bits_aw_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_aw_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_aw_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_0_bits_aw_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_aw_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_w_valid; // @[HasHarnessInstantiators.scala:87:40] wire [63:0] _chiptop0_axi4_mem_0_bits_w_bits_data; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_0_bits_w_bits_strb; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_w_bits_last; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_b_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_ar_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_0_bits_ar_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_0_bits_ar_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_0_bits_ar_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_0_bits_ar_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_0_bits_ar_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_ar_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_ar_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_0_bits_ar_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_ar_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_r_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_clock; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_aw_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_1_bits_aw_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_1_bits_aw_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_1_bits_aw_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_1_bits_aw_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_1_bits_aw_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_aw_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_1_bits_aw_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_1_bits_aw_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_1_bits_aw_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_w_valid; // @[HasHarnessInstantiators.scala:87:40] wire [63:0] _chiptop0_axi4_mem_1_bits_w_bits_data; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_1_bits_w_bits_strb; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_w_bits_last; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_b_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_ar_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_1_bits_ar_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_1_bits_ar_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_1_bits_ar_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_1_bits_ar_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_1_bits_ar_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_ar_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_1_bits_ar_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_1_bits_ar_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_1_bits_ar_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_r_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_clock; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_aw_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_2_bits_aw_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_2_bits_aw_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_2_bits_aw_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_2_bits_aw_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_2_bits_aw_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_aw_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_2_bits_aw_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_2_bits_aw_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_2_bits_aw_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_w_valid; // @[HasHarnessInstantiators.scala:87:40] wire [63:0] _chiptop0_axi4_mem_2_bits_w_bits_data; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_2_bits_w_bits_strb; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_w_bits_last; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_b_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_ar_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_2_bits_ar_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_2_bits_ar_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_2_bits_ar_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_2_bits_ar_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_2_bits_ar_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_ar_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_2_bits_ar_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_2_bits_ar_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_2_bits_ar_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_r_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_clock; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_aw_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_3_bits_aw_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_3_bits_aw_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_3_bits_aw_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_3_bits_aw_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_3_bits_aw_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_aw_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_3_bits_aw_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_3_bits_aw_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_3_bits_aw_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_w_valid; // @[HasHarnessInstantiators.scala:87:40] wire [63:0] _chiptop0_axi4_mem_3_bits_w_bits_data; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_3_bits_w_bits_strb; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_w_bits_last; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_b_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_ar_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_3_bits_ar_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_3_bits_ar_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_3_bits_ar_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_3_bits_ar_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_3_bits_ar_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_ar_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_3_bits_ar_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_3_bits_ar_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_3_bits_ar_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_r_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_serial_tl_0_in_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_serial_tl_0_out_valid; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_serial_tl_0_out_bits_phit; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_reset_io_T = reset; // @[HarnessBinders.scala:325:34] wire _harnessBinderReset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63] wire _harnessBinderReset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63] wire _harnessBinderReset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50] wire _harnessBinderReset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50] wire success; // @[TestHarness.scala:23:25] wire jtag_wire_TDO_driven = 1'h1; // @[Periphery.scala:236:11] wire io_success_0; // @[TestHarness.scala:19:7] wire harnessBinderClk; // @[HarnessClocks.scala:28:23] wire harnessBinderClock; // @[HasHarnessInstantiators.scala:57:32] wire harnessBinderReset; // @[HasHarnessInstantiators.scala:58:32] wire _simdram_io_reset_T = harnessBinderReset; // @[HasHarnessInstantiators.scala:58:32] wire _simdram_io_reset_T_1 = harnessBinderReset; // @[HasHarnessInstantiators.scala:58:32] wire _simdram_io_reset_T_2 = harnessBinderReset; // @[HasHarnessInstantiators.scala:58:32] wire _simdram_io_reset_T_3 = harnessBinderReset; // @[HasHarnessInstantiators.scala:58:32] wire _success_T_2 = harnessBinderReset; // @[SimTSI.scala:21:11] assign io_success_0 = success; // @[TestHarness.scala:19:7, :23:25] wire _dtm_success_T; // @[Periphery.scala:235:26] wire dtm_success; // @[HarnessBinders.scala:176:31] wire jtag_wire_TDO_data; // @[HarnessBinders.scala:178:25] wire jtag_wire_TCK; // @[HarnessBinders.scala:178:25] wire jtag_wire_TMS; // @[HarnessBinders.scala:178:25] wire jtag_wire_TDI; // @[HarnessBinders.scala:178:25] assign _dtm_success_T = _jtag_exit == 32'h1; // @[Periphery.scala:235:26] assign dtm_success = _dtm_success_T; // @[Periphery.scala:235:26] wire chiptop0_clock_uncore_clock; // @[HarnessClocks.scala:28:23] wire success_1 = _success_exit_sim_exit == 32'h1; // @[SimTSI.scala:12:23, :19:24] wire success_error = \|(_success_exit_sim_exit[31:1]); // @[SimTSI.scala:12:23, :20:22] wire _success_T = ~success_error; // @[SimTSI.scala:20:22, :21:12] wire [31:0] _success_T_1 = {1'h0, _success_exit_sim_exit[31:1]}; // @[SimTSI.scala:12:23, :20:22, :21:62] wire _success_T_3 = ~_success_T_2; // @[SimTSI.scala:21:11] wire _success_T_4 = ~_success_T; // @[SimTSI.scala:21:{11,12}]
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_pbus_out_i1_o2_a29d64s10k1z3u : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_20 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<10>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<10>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<10>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 9, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<13>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<13>(0h0) connect _WIRE_30.bits.source, UInt<10>(0h0) connect _WIRE_30.bits.size, UInt<3>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<29>(0h0) connect _WIRE_32.bits.source, UInt<10>(0h0) connect _WIRE_32.bits.size, UInt<3>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<13>(0h0) connect _WIRE_34.bits.source, UInt<10>(0h0) connect _WIRE_34.bits.size, UInt<3>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<29>(0h0) connect _WIRE_36.bits.source, UInt<10>(0h0) connect _WIRE_36.bits.size, UInt<3>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.ready, UInt<1>(0h1) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<13>(0h0) connect _WIRE_38.bits.source, UInt<10>(0h0) connect _WIRE_38.bits.size, UInt<3>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.ready, UInt<1>(0h1) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<29>(0h0) connect _WIRE_48.bits.source, UInt<10>(0h0) connect _WIRE_48.bits.size, UInt<3>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<29>(0h0) connect _WIRE_50.bits.source, UInt<10>(0h0) connect _WIRE_50.bits.size, UInt<3>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<29>(0h0) connect _WIRE_52.bits.source, UInt<10>(0h0) connect _WIRE_52.bits.size, UInt<3>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<29>(0h0) connect _WIRE_54.bits.source, UInt<10>(0h0) connect _WIRE_54.bits.size, UInt<3>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<29>(0h0) connect _WIRE_56.bits.source, UInt<10>(0h0) connect _WIRE_56.bits.size, UInt<3>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<29>(0h0) connect _WIRE_58.bits.source, UInt<10>(0h0) connect _WIRE_58.bits.size, UInt<3>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<29>(0h0) connect _WIRE_60.bits.source, UInt<10>(0h0) connect _WIRE_60.bits.size, UInt<3>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<29>(0h0) connect _WIRE_62.bits.source, UInt<10>(0h0) connect _WIRE_62.bits.size, UInt<3>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<29>(0h0) connect _addressC_WIRE.bits.source, UInt<10>(0h0) connect _addressC_WIRE.bits.size, UInt<3>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<30>(0h10000000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<29>(0h10000000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<30>(0h10000000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<29>(0h0) connect _requestBOI_WIRE.bits.source, UInt<10>(0h0) connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<10>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 9, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 10) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<10>(0h3ff)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<29>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<10>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<10>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 9, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 10) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<10>(0h3ff)) node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<10>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 9, 0) node _requestDOI_T = shr(out[0].d.bits.source, 10) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<10>(0h3ff)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<10>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 9, 0) node _requestDOI_T_5 = shr(out[1].d.bits.source, 10) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<10>(0h3ff)) node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<29>(0h0) connect _beatsBO_WIRE.bits.source, UInt<10>(0h0) connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<29>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<10>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<29>(0h0) connect _beatsCI_WIRE.bits.source, UInt<10>(0h0) connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<29>(0h0) connect _portsBIO_WIRE.bits.source, UInt<10>(0h0) connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.address, UInt<29>(0h0) connect _portsBIO_WIRE_2.bits.source, UInt<10>(0h0) connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<29>(0h0) connect _portsCOI_WIRE.bits.source, UInt<10>(0h0) connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_2 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect out[0].d.ready, portsDIO_filtered[0].ready wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect out[1].d.ready, portsDIO_filtered_1[0].ready wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_2 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 connect out[0].a, portsAOI_filtered[0] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.address, UInt<29>(0h0) connect _WIRE_72.bits.source, UInt<10>(0h0) connect _WIRE_72.bits.size, UInt<3>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_74.bits.sink, UInt<1>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect out[1].a, portsAOI_filtered[1] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.address, UInt<29>(0h0) connect _WIRE_76.bits.source, UInt<10>(0h0) connect _WIRE_76.bits.size, UInt<3>(0h0) connect _WIRE_76.bits.param, UInt<3>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_78.bits.sink, UInt<1>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<64>(0h0) connect _WIRE_80.bits.mask, UInt<8>(0h0) connect _WIRE_80.bits.address, UInt<29>(0h0) connect _WIRE_80.bits.source, UInt<10>(0h0) connect _WIRE_80.bits.size, UInt<3>(0h0) connect _WIRE_80.bits.param, UInt<2>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.mask invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, in[0].d.ready) node _readys_T = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsDIO_filtered[0].valid) node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<64> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<1> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<10> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<3> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) extmodule plusarg_reader_42 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_43 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLXbar_pbus_out_i1_o2_a29d64s10k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [12:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire [9:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [9:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] x1_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] in_0_d_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_WIRE_param = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_19 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_in_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_d_bits_sink = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_denied = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _out_1_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_WIRE_sink = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_denied = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_7 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_10 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_11 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_6 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [28:0] _addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _requestCIO_T = 29'h0; // @[Parameters.scala:137:31] wire [28:0] _requestCIO_T_5 = 29'h0; // @[Parameters.scala:137:31] wire [28:0] _requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _requestBOI_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _requestBOI_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _beatsBO_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _beatsBO_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] _portsBIO_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _portsBIO_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] portsBIO_filtered_1_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] _portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] portsCOI_filtered_1_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [9:0] _addressC_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _addressC_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _requestBOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _requestBOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _requestBOI_uncommonBits_T = 10'h0; // @[Parameters.scala:52:29] wire [9:0] requestBOI_uncommonBits = 10'h0; // @[Parameters.scala:52:56] wire [9:0] _requestBOI_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _requestBOI_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _requestBOI_uncommonBits_T_1 = 10'h0; // @[Parameters.scala:52:29] wire [9:0] requestBOI_uncommonBits_1 = 10'h0; // @[Parameters.scala:52:56] wire [9:0] _beatsBO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _beatsBO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _beatsBO_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _beatsBO_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _beatsCI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _beatsCI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _portsBIO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _portsBIO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] portsBIO_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] _portsBIO_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _portsBIO_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] portsBIO_filtered_1_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] _portsCOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _portsCOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] portsCOI_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] portsCOI_filtered_1_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [29:0] _requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] _requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_6 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] _requestCIO_T_7 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_8 = 30'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [9:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [12:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [12:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [9:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [28:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [9:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [9:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [9:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [9:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [28:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [28:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [28:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [9:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [9:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [9:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [9:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [9:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [28:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address[12:0]; // @[Xbar.scala:216:19, :222:41] wire [29:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] _requestAIO_T_2 = _requestAIO_T_1 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [28:0] _requestAIO_T_5 = in_0_a_bits_address ^ 29'h10000000; // @[Xbar.scala:159:18] wire [29:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [29:0] _requestAIO_T_7 = _requestAIO_T_6 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [9:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [9:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T \| _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid \| portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to this FIRRTL code module PE_422 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_166 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_422( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_166 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s6k1z3u_1 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_80 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a28d64s6k1z3u_1 connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a28d64s6k1z3u_1 connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLBuffer_a28d64s6k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [5:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_80 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s6k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s6k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (2'h0), // @[Decoupled.scala:362:21] .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (1'h0), // @[Decoupled.scala:362:21] .io_enq_bits_denied (1'h0), // @[Decoupled.scala:362:21] .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (1'h0), // @[Decoupled.scala:362:21] .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_34 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h13)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h13)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_86 = shr(io.in.a.bits.source, 5) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<5>(0h13)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_152 = shr(io.in.a.bits.source, 5) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<5>(0h13)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_199 = shr(io.in.a.bits.source, 5) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<5>(0h13)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_240 = shr(io.in.a.bits.source, 5) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<5>(0h13)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_283 = shr(io.in.a.bits.source, 5) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<5>(0h13)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_321 = shr(io.in.a.bits.source, 5) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<5>(0h13)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_359 = shr(io.in.a.bits.source, 5) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<5>(0h13)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0) regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<20> connect a_set, UInt<20>(0h0) wire a_set_wo_ready : UInt<20> connect a_set_wo_ready, UInt<20>(0h0) wire a_opcodes_set : UInt<80> connect a_opcodes_set, UInt<80>(0h0) wire a_sizes_set : UInt<80> connect a_sizes_set, UInt<80>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<20> connect d_clr, UInt<20>(0h0) wire d_clr_wo_ready : UInt<20> connect d_clr_wo_ready, UInt<20>(0h0) wire d_opcodes_clr : UInt<80> connect d_opcodes_clr, UInt<80>(0h0) wire d_sizes_clr : UInt<80> connect d_sizes_clr, UInt<80>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_68 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0) regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<20> connect c_set, UInt<20>(0h0) wire c_set_wo_ready : UInt<20> connect c_set_wo_ready, UInt<20>(0h0) wire c_opcodes_set : UInt<80> connect c_opcodes_set, UInt<80>(0h0) wire c_sizes_set : UInt<80> connect c_sizes_set, UInt<80>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<20> connect d_clr_1, UInt<20>(0h0) wire d_clr_wo_ready_1 : UInt<20> connect d_clr_wo_ready_1, UInt<20>(0h0) wire d_opcodes_clr_1 : UInt<80> connect d_opcodes_clr_1, UInt<80>(0h0) wire d_sizes_clr_1 : UInt<80> connect d_sizes_clr_1, UInt<80>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_69 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_34( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34] wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34] wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34] wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [19:0] inflight; // @[Monitor.scala:614:27] reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [19:0] a_set; // @[Monitor.scala:626:34] wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [79:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [19:0] d_clr; // @[Monitor.scala:664:34] wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [19:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [79:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [79:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [19:0] inflight_1; // @[Monitor.scala:726:35] wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [19:0] d_clr_1; // @[Monitor.scala:774:34] wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_31 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_31 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module INToRecFN_i1_e8_s24_31(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_31 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_133 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_389 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_133( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_389 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMasterACDToNoC_10 : input clock : Clock input reset : Reset output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst a of TLAToNoC_10 connect a.clock, clock connect a.reset, reset inst c of TLCToNoC_10 connect c.clock, clock connect c.reset, reset inst d of TLDFromNoC_10 connect d.clock, clock connect d.reset, reset connect a.io.protocol, io.tilelink.a connect c.io.protocol, io.tilelink.c connect io.tilelink.d.bits, d.io.protocol.bits connect io.tilelink.d.valid, d.io.protocol.valid connect d.io.protocol.ready, io.tilelink.d.ready connect io.flits.a.bits, a.io.flit.bits connect io.flits.a.valid, a.io.flit.valid connect a.io.flit.ready, io.flits.a.ready connect io.flits.c.bits, c.io.flit.bits connect io.flits.c.valid, c.io.flit.valid connect c.io.flit.ready, io.flits.c.ready connect d.io.flit, io.flits.d	module TLMasterACDToNoC_10( // @[Tilelink.scala:72:7] input clock, // @[Tilelink.scala:72:7] input reset, // @[Tilelink.scala:72:7] output io_tilelink_a_ready, // @[Tilelink.scala:79:14] input io_tilelink_a_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:79:14] input [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:79:14] input [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:79:14] input [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:79:14] output io_tilelink_c_ready, // @[Tilelink.scala:79:14] input io_tilelink_c_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:79:14] input [6:0] io_tilelink_c_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:79:14] input [127:0] io_tilelink_c_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:79:14] input io_tilelink_d_ready, // @[Tilelink.scala:79:14] output io_tilelink_d_valid, // @[Tilelink.scala:79:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:79:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:79:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:79:14] output [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:79:14] output [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:79:14] output [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:79:14] input io_flits_a_ready, // @[Tilelink.scala:79:14] output io_flits_a_valid, // @[Tilelink.scala:79:14] output io_flits_a_bits_head, // @[Tilelink.scala:79:14] output io_flits_a_bits_tail, // @[Tilelink.scala:79:14] output [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:79:14] input io_flits_c_ready, // @[Tilelink.scala:79:14] output io_flits_c_valid, // @[Tilelink.scala:79:14] output io_flits_c_bits_head, // @[Tilelink.scala:79:14] output io_flits_c_bits_tail, // @[Tilelink.scala:79:14] output [144:0] io_flits_c_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:79:14] output io_flits_d_ready, // @[Tilelink.scala:79:14] input io_flits_d_valid, // @[Tilelink.scala:79:14] input io_flits_d_bits_head, // @[Tilelink.scala:79:14] input io_flits_d_bits_tail, // @[Tilelink.scala:79:14] input [144:0] io_flits_d_bits_payload // @[Tilelink.scala:79:14] ); wire [128:0] _c_io_flit_bits_payload; // @[Tilelink.scala:89:17] TLAToNoC_10 a ( // @[Tilelink.scala:88:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:88:17] TLCToNoC_10 c ( // @[Tilelink.scala:89:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:89:17] TLDFromNoC_1 d ( // @[Tilelink.scala:90:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[128:0]) // @[Tilelink.scala:97:14] ); // @[Tilelink.scala:90:17] assign io_flits_c_bits_payload = {16'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:72:7, :89:17, :96:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OutputUnit_1 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[6], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[6], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[6], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[6], out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}} reg states : { `5` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}, `4` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}, `3` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}, `2` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}, `1` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}, `0` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, clock connect io.channel_status[0].occupied, states.`0`.occupied connect io.channel_status[0].flow, states.`0`.flow connect io.channel_status[1].occupied, states.`1`.occupied connect io.channel_status[1].flow, states.`1`.flow connect io.channel_status[2].occupied, states.`2`.occupied connect io.channel_status[2].flow, states.`2`.flow connect io.channel_status[3].occupied, states.`3`.occupied connect io.channel_status[3].flow, states.`3`.flow connect io.channel_status[4].occupied, states.`4`.occupied connect io.channel_status[4].flow, states.`4`.flow connect io.channel_status[5].occupied, states.`5`.occupied connect io.channel_status[5].flow, states.`5`.flow connect io.out.flit, io.in node _T = bits(io.out.vc_free, 0, 0) when _T : node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(states.`0`.occupied, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf assert(clock, states.`0`.occupied, UInt<1>(0h1), "") : assert connect states.`0`.occupied, UInt<1>(0h0) node _T_4 = bits(io.out.vc_free, 1, 1) when _T_4 : node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(states.`1`.occupied, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_1 assert(clock, states.`1`.occupied, UInt<1>(0h1), "") : assert_1 connect states.`1`.occupied, UInt<1>(0h0) node _T_8 = bits(io.out.vc_free, 2, 2) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : node _T_11 = eq(states.`2`.occupied, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_2 assert(clock, states.`2`.occupied, UInt<1>(0h1), "") : assert_2 connect states.`2`.occupied, UInt<1>(0h0) node _T_12 = bits(io.out.vc_free, 3, 3) when _T_12 : node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(states.`3`.occupied, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_3 assert(clock, states.`3`.occupied, UInt<1>(0h1), "") : assert_3 connect states.`3`.occupied, UInt<1>(0h0) node _T_16 = bits(io.out.vc_free, 4, 4) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(states.`4`.occupied, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_4 assert(clock, states.`4`.occupied, UInt<1>(0h1), "") : assert_4 connect states.`4`.occupied, UInt<1>(0h0) node _T_20 = bits(io.out.vc_free, 5, 5) when _T_20 : node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(states.`5`.occupied, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_5 assert(clock, states.`5`.occupied, UInt<1>(0h1), "") : assert_5 connect states.`5`.occupied, UInt<1>(0h0) when io.allocs[0].alloc : connect states.`0`.occupied, UInt<1>(0h1) connect states.`0`.flow, io.allocs[0].flow when io.allocs[1].alloc : connect states.`1`.occupied, UInt<1>(0h1) connect states.`1`.flow, io.allocs[1].flow when io.allocs[2].alloc : connect states.`2`.occupied, UInt<1>(0h1) connect states.`2`.flow, io.allocs[2].flow when io.allocs[3].alloc : connect states.`3`.occupied, UInt<1>(0h1) connect states.`3`.flow, io.allocs[3].flow when io.allocs[4].alloc : connect states.`4`.occupied, UInt<1>(0h1) connect states.`4`.flow, io.allocs[4].flow when io.allocs[5].alloc : connect states.`5`.occupied, UInt<1>(0h1) connect states.`5`.flow, io.allocs[5].flow node _io_credit_available_0_T = neq(states.`0`.c, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_credit_available_1_T = neq(states.`1`.c, UInt<1>(0h0)) connect io.credit_available[1], _io_credit_available_1_T node _io_credit_available_2_T = neq(states.`2`.c, UInt<1>(0h0)) connect io.credit_available[2], _io_credit_available_2_T node _io_credit_available_3_T = neq(states.`3`.c, UInt<1>(0h0)) connect io.credit_available[3], _io_credit_available_3_T node _io_credit_available_4_T = neq(states.`4`.c, UInt<1>(0h0)) connect io.credit_available[4], _io_credit_available_4_T node _io_credit_available_5_T = neq(states.`5`.c, UInt<1>(0h0)) connect io.credit_available[5], _io_credit_available_5_T node free = bits(io.out.credit_return, 0, 0) node _states_0_c_T = add(states.`0`.c, free) node _states_0_c_T_1 = sub(_states_0_c_T, io.credit_alloc[0].alloc) node _states_0_c_T_2 = tail(_states_0_c_T_1, 1) connect states.`0`.c, _states_0_c_T_2 node free_1 = bits(io.out.credit_return, 1, 1) node _states_1_c_T = add(states.`1`.c, free_1) node _states_1_c_T_1 = sub(_states_1_c_T, io.credit_alloc[1].alloc) node _states_1_c_T_2 = tail(_states_1_c_T_1, 1) connect states.`1`.c, _states_1_c_T_2 node free_2 = bits(io.out.credit_return, 2, 2) node _states_2_c_T = add(states.`2`.c, free_2) node _states_2_c_T_1 = sub(_states_2_c_T, io.credit_alloc[2].alloc) node _states_2_c_T_2 = tail(_states_2_c_T_1, 1) connect states.`2`.c, _states_2_c_T_2 node free_3 = bits(io.out.credit_return, 3, 3) node _states_3_c_T = add(states.`3`.c, free_3) node _states_3_c_T_1 = sub(_states_3_c_T, io.credit_alloc[3].alloc) node _states_3_c_T_2 = tail(_states_3_c_T_1, 1) connect states.`3`.c, _states_3_c_T_2 node free_4 = bits(io.out.credit_return, 4, 4) node _states_4_c_T = add(states.`4`.c, free_4) node _states_4_c_T_1 = sub(_states_4_c_T, io.credit_alloc[4].alloc) node _states_4_c_T_2 = tail(_states_4_c_T_1, 1) connect states.`4`.c, _states_4_c_T_2 node free_5 = bits(io.out.credit_return, 5, 5) node _states_5_c_T = add(states.`5`.c, free_5) node _states_5_c_T_1 = sub(_states_5_c_T, io.credit_alloc[5].alloc) node _states_5_c_T_2 = tail(_states_5_c_T_1, 1) connect states.`5`.c, _states_5_c_T_2 node _T_24 = asUInt(reset) when _T_24 : connect states.`0`.occupied, UInt<1>(0h0) connect states.`1`.occupied, UInt<1>(0h0) connect states.`2`.occupied, UInt<1>(0h0) connect states.`3`.occupied, UInt<1>(0h0) connect states.`4`.occupied, UInt<1>(0h0) connect states.`5`.occupied, UInt<1>(0h0) connect states.`0`.c, UInt<3>(0h4) connect states.`1`.c, UInt<3>(0h4) connect states.`2`.c, UInt<3>(0h4) connect states.`3`.c, UInt<3>(0h4) connect states.`4`.c, UInt<3>(0h4) connect states.`5`.c, UInt<3>(0h4)	module OutputUnit_1( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [72:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_0, // @[OutputUnit.scala:58:14] output io_credit_available_1, // @[OutputUnit.scala:58:14] output io_credit_available_2, // @[OutputUnit.scala:58:14] output io_credit_available_3, // @[OutputUnit.scala:58:14] output io_credit_available_4, // @[OutputUnit.scala:58:14] output io_credit_available_5, // @[OutputUnit.scala:58:14] output io_channel_status_0_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_1_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_2_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_3_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_4_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_5_occupied, // @[OutputUnit.scala:58:14] input io_allocs_0_alloc, // @[OutputUnit.scala:58:14] input io_allocs_1_alloc, // @[OutputUnit.scala:58:14] input io_allocs_2_alloc, // @[OutputUnit.scala:58:14] input io_allocs_3_alloc, // @[OutputUnit.scala:58:14] input io_allocs_4_alloc, // @[OutputUnit.scala:58:14] input io_allocs_5_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_0_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_1_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_2_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_3_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_4_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_5_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [72:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [5:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [5:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_5_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_5_c; // @[OutputUnit.scala:66:19] reg states_4_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_4_c; // @[OutputUnit.scala:66:19] reg states_3_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_3_c; // @[OutputUnit.scala:66:19] reg states_2_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_2_c; // @[OutputUnit.scala:66:19] reg states_1_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_1_c; // @[OutputUnit.scala:66:19] reg states_0_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_0_c; // @[OutputUnit.scala:66:19]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_170 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_191 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_170( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_191 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w55 : input clock : Clock input reset : Reset output io : { flip d : UInt<55>, q : UInt<55>, flip en : UInt<1>} reg cdc_reg : UInt<55>, clock when io.en : connect cdc_reg, io.d connect io.q, cdc_reg	module ClockCrossingReg_w55( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [54:0] io_d, // @[SynchronizerReg.scala:195:14] output [54:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [54:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [54:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [54:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_123 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_123 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_123( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_123 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_106 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_106( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_347 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_91 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_347( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_91 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[12] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 node _source_ok_T_32 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[2]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[3]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[4]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[5]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[6]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[7]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[8]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[9]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[10]) node source_ok = or(_source_ok_T_41, _source_ok_WIRE[11]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = and(_T_11, _T_24) node _T_121 = and(_T_120, _T_37) node _T_122 = and(_T_121, _T_50) node _T_123 = and(_T_122, _T_63) node _T_124 = and(_T_123, _T_71) node _T_125 = and(_T_124, _T_79) node _T_126 = and(_T_125, _T_87) node _T_127 = and(_T_126, _T_95) node _T_128 = and(_T_127, _T_103) node _T_129 = and(_T_128, _T_111) node _T_130 = and(_T_129, _T_119) node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(_T_130, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_130, UInt<1>(0h1), "") : assert_1 node _T_134 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_134 : node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_136 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_139 = shr(io.in.a.bits.source, 2) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = leq(UInt<1>(0h0), uncommonBits_4) node _T_142 = and(_T_140, _T_141) node _T_143 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_144 = and(_T_142, _T_143) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_145 = shr(io.in.a.bits.source, 2) node _T_146 = eq(_T_145, UInt<1>(0h1)) node _T_147 = leq(UInt<1>(0h0), uncommonBits_5) node _T_148 = and(_T_146, _T_147) node _T_149 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_150 = and(_T_148, _T_149) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_151 = shr(io.in.a.bits.source, 2) node _T_152 = eq(_T_151, UInt<2>(0h2)) node _T_153 = leq(UInt<1>(0h0), uncommonBits_6) node _T_154 = and(_T_152, _T_153) node _T_155 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_156 = and(_T_154, _T_155) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_157 = shr(io.in.a.bits.source, 2) node _T_158 = eq(_T_157, UInt<2>(0h3)) node _T_159 = leq(UInt<1>(0h0), uncommonBits_7) node _T_160 = and(_T_158, _T_159) node _T_161 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_166 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_167 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_169 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_170 = or(_T_138, _T_144) node _T_171 = or(_T_170, _T_150) node _T_172 = or(_T_171, _T_156) node _T_173 = or(_T_172, _T_162) node _T_174 = or(_T_173, _T_163) node _T_175 = or(_T_174, _T_164) node _T_176 = or(_T_175, _T_165) node _T_177 = or(_T_176, _T_166) node _T_178 = or(_T_177, _T_167) node _T_179 = or(_T_178, _T_168) node _T_180 = or(_T_179, _T_169) node _T_181 = and(_T_137, _T_180) node _T_182 = or(UInt<1>(0h0), _T_181) node _T_183 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_184 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<13>(0h1000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = and(_T_183, _T_188) node _T_190 = or(UInt<1>(0h0), _T_189) node _T_191 = and(_T_182, _T_190) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_191, UInt<1>(0h1), "") : assert_2 node _T_195 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_196 = shr(io.in.a.bits.source, 2) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = leq(UInt<1>(0h0), uncommonBits_8) node _T_199 = and(_T_197, _T_198) node _T_200 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_201 = and(_T_199, _T_200) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_202 = shr(io.in.a.bits.source, 2) node _T_203 = eq(_T_202, UInt<1>(0h1)) node _T_204 = leq(UInt<1>(0h0), uncommonBits_9) node _T_205 = and(_T_203, _T_204) node _T_206 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_207 = and(_T_205, _T_206) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_208 = shr(io.in.a.bits.source, 2) node _T_209 = eq(_T_208, UInt<2>(0h2)) node _T_210 = leq(UInt<1>(0h0), uncommonBits_10) node _T_211 = and(_T_209, _T_210) node _T_212 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_213 = and(_T_211, _T_212) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_214 = shr(io.in.a.bits.source, 2) node _T_215 = eq(_T_214, UInt<2>(0h3)) node _T_216 = leq(UInt<1>(0h0), uncommonBits_11) node _T_217 = and(_T_215, _T_216) node _T_218 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_219 = and(_T_217, _T_218) node _T_220 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_221 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_222 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_223 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_225 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_226 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[12] connect _WIRE[0], _T_195 connect _WIRE[1], _T_201 connect _WIRE[2], _T_207 connect _WIRE[3], _T_213 connect _WIRE[4], _T_219 connect _WIRE[5], _T_220 connect _WIRE[6], _T_221 connect _WIRE[7], _T_222 connect _WIRE[8], _T_223 connect _WIRE[9], _T_224 connect _WIRE[10], _T_225 connect _WIRE[11], _T_226 node _T_227 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_228 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_229 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_230 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_231 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_232 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_233 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_234 = mux(_WIRE[5], _T_227, UInt<1>(0h0)) node _T_235 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_236 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_237 = mux(_WIRE[8], _T_228, UInt<1>(0h0)) node _T_238 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_239 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_240 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = or(_T_229, _T_230) node _T_242 = or(_T_241, _T_231) node _T_243 = or(_T_242, _T_232) node _T_244 = or(_T_243, _T_233) node _T_245 = or(_T_244, _T_234) node _T_246 = or(_T_245, _T_235) node _T_247 = or(_T_246, _T_236) node _T_248 = or(_T_247, _T_237) node _T_249 = or(_T_248, _T_238) node _T_250 = or(_T_249, _T_239) node _T_251 = or(_T_250, _T_240) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_251 node _T_252 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_253 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_254 = and(_T_252, _T_253) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<13>(0h1000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = and(_T_255, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = and(_WIRE_1, _T_262) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_263, UInt<1>(0h1), "") : assert_3 node _T_267 = asUInt(reset) node _T_268 = eq(_T_267, UInt<1>(0h0)) when _T_268 : node _T_269 = eq(source_ok, UInt<1>(0h0)) when _T_269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_270 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_270, UInt<1>(0h1), "") : assert_5 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(is_aligned, UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_277 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_277, UInt<1>(0h1), "") : assert_7 node _T_281 = not(io.in.a.bits.mask) node _T_282 = eq(_T_281, UInt<1>(0h0)) node _T_283 = asUInt(reset) node _T_284 = eq(_T_283, UInt<1>(0h0)) when _T_284 : node _T_285 = eq(_T_282, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_282, UInt<1>(0h1), "") : assert_8 node _T_286 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_287 = asUInt(reset) node _T_288 = eq(_T_287, UInt<1>(0h0)) when _T_288 : node _T_289 = eq(_T_286, UInt<1>(0h0)) when _T_289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_286, UInt<1>(0h1), "") : assert_9 node _T_290 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_290 : node _T_291 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_292 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_295 = shr(io.in.a.bits.source, 2) node _T_296 = eq(_T_295, UInt<1>(0h0)) node _T_297 = leq(UInt<1>(0h0), uncommonBits_12) node _T_298 = and(_T_296, _T_297) node _T_299 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_300 = and(_T_298, _T_299) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<1>(0h1)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_13) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<2>(0h2)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_14) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<2>(0h3)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_15) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_321 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_322 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_323 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_324 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_325 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_326 = or(_T_294, _T_300) node _T_327 = or(_T_326, _T_306) node _T_328 = or(_T_327, _T_312) node _T_329 = or(_T_328, _T_318) node _T_330 = or(_T_329, _T_319) node _T_331 = or(_T_330, _T_320) node _T_332 = or(_T_331, _T_321) node _T_333 = or(_T_332, _T_322) node _T_334 = or(_T_333, _T_323) node _T_335 = or(_T_334, _T_324) node _T_336 = or(_T_335, _T_325) node _T_337 = and(_T_293, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<13>(0h1000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = and(_T_339, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = and(_T_338, _T_346) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_347, UInt<1>(0h1), "") : assert_10 node _T_351 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_352 = shr(io.in.a.bits.source, 2) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = leq(UInt<1>(0h0), uncommonBits_16) node _T_355 = and(_T_353, _T_354) node _T_356 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_357 = and(_T_355, _T_356) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_358 = shr(io.in.a.bits.source, 2) node _T_359 = eq(_T_358, UInt<1>(0h1)) node _T_360 = leq(UInt<1>(0h0), uncommonBits_17) node _T_361 = and(_T_359, _T_360) node _T_362 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_363 = and(_T_361, _T_362) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_364 = shr(io.in.a.bits.source, 2) node _T_365 = eq(_T_364, UInt<2>(0h2)) node _T_366 = leq(UInt<1>(0h0), uncommonBits_18) node _T_367 = and(_T_365, _T_366) node _T_368 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_369 = and(_T_367, _T_368) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_370 = shr(io.in.a.bits.source, 2) node _T_371 = eq(_T_370, UInt<2>(0h3)) node _T_372 = leq(UInt<1>(0h0), uncommonBits_19) node _T_373 = and(_T_371, _T_372) node _T_374 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_375 = and(_T_373, _T_374) node _T_376 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_377 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_378 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_379 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_380 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_381 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_382 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[12] connect _WIRE_2[0], _T_351 connect _WIRE_2[1], _T_357 connect _WIRE_2[2], _T_363 connect _WIRE_2[3], _T_369 connect _WIRE_2[4], _T_375 connect _WIRE_2[5], _T_376 connect _WIRE_2[6], _T_377 connect _WIRE_2[7], _T_378 connect _WIRE_2[8], _T_379 connect _WIRE_2[9], _T_380 connect _WIRE_2[10], _T_381 connect _WIRE_2[11], _T_382 node _T_383 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_384 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_385 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_387 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_388 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_389 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_390 = mux(_WIRE_2[5], _T_383, UInt<1>(0h0)) node _T_391 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_392 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_393 = mux(_WIRE_2[8], _T_384, UInt<1>(0h0)) node _T_394 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_395 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_396 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_397 = or(_T_385, _T_386) node _T_398 = or(_T_397, _T_387) node _T_399 = or(_T_398, _T_388) node _T_400 = or(_T_399, _T_389) node _T_401 = or(_T_400, _T_390) node _T_402 = or(_T_401, _T_391) node _T_403 = or(_T_402, _T_392) node _T_404 = or(_T_403, _T_393) node _T_405 = or(_T_404, _T_394) node _T_406 = or(_T_405, _T_395) node _T_407 = or(_T_406, _T_396) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_407 node _T_408 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_409 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_410 = and(_T_408, _T_409) node _T_411 = or(UInt<1>(0h0), _T_410) node _T_412 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_413 = cvt(_T_412) node _T_414 = and(_T_413, asSInt(UInt<13>(0h1000))) node _T_415 = asSInt(_T_414) node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0))) node _T_417 = and(_T_411, _T_416) node _T_418 = or(UInt<1>(0h0), _T_417) node _T_419 = and(_WIRE_3, _T_418) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_419, UInt<1>(0h1), "") : assert_11 node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(source_ok, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_426 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_426, UInt<1>(0h1), "") : assert_13 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(is_aligned, UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_433 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_433, UInt<1>(0h1), "") : assert_15 node _T_437 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_437, UInt<1>(0h1), "") : assert_16 node _T_441 = not(io.in.a.bits.mask) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_442, UInt<1>(0h1), "") : assert_17 node _T_446 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_446, UInt<1>(0h1), "") : assert_18 node _T_450 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_450 : node _T_451 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_452 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_453 = and(_T_451, _T_452) node _T_454 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_455 = shr(io.in.a.bits.source, 2) node _T_456 = eq(_T_455, UInt<1>(0h0)) node _T_457 = leq(UInt<1>(0h0), uncommonBits_20) node _T_458 = and(_T_456, _T_457) node _T_459 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_460 = and(_T_458, _T_459) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_461 = shr(io.in.a.bits.source, 2) node _T_462 = eq(_T_461, UInt<1>(0h1)) node _T_463 = leq(UInt<1>(0h0), uncommonBits_21) node _T_464 = and(_T_462, _T_463) node _T_465 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_466 = and(_T_464, _T_465) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_467 = shr(io.in.a.bits.source, 2) node _T_468 = eq(_T_467, UInt<2>(0h2)) node _T_469 = leq(UInt<1>(0h0), uncommonBits_22) node _T_470 = and(_T_468, _T_469) node _T_471 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_472 = and(_T_470, _T_471) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_473 = shr(io.in.a.bits.source, 2) node _T_474 = eq(_T_473, UInt<2>(0h3)) node _T_475 = leq(UInt<1>(0h0), uncommonBits_23) node _T_476 = and(_T_474, _T_475) node _T_477 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_480 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_483 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_484 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_485 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_486 = or(_T_454, _T_460) node _T_487 = or(_T_486, _T_466) node _T_488 = or(_T_487, _T_472) node _T_489 = or(_T_488, _T_478) node _T_490 = or(_T_489, _T_479) node _T_491 = or(_T_490, _T_480) node _T_492 = or(_T_491, _T_481) node _T_493 = or(_T_492, _T_482) node _T_494 = or(_T_493, _T_483) node _T_495 = or(_T_494, _T_484) node _T_496 = or(_T_495, _T_485) node _T_497 = and(_T_453, _T_496) node _T_498 = or(UInt<1>(0h0), _T_497) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_498, UInt<1>(0h1), "") : assert_19 node _T_502 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_503 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_504 = and(_T_502, _T_503) node _T_505 = or(UInt<1>(0h0), _T_504) node _T_506 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<13>(0h1000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = and(_T_505, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_512, UInt<1>(0h1), "") : assert_20 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_522, UInt<1>(0h1), "") : assert_23 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_526, UInt<1>(0h1), "") : assert_24 node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_530, UInt<1>(0h1), "") : assert_25 node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_534 : node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_539 = shr(io.in.a.bits.source, 2) node _T_540 = eq(_T_539, UInt<1>(0h0)) node _T_541 = leq(UInt<1>(0h0), uncommonBits_24) node _T_542 = and(_T_540, _T_541) node _T_543 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_544 = and(_T_542, _T_543) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_545 = shr(io.in.a.bits.source, 2) node _T_546 = eq(_T_545, UInt<1>(0h1)) node _T_547 = leq(UInt<1>(0h0), uncommonBits_25) node _T_548 = and(_T_546, _T_547) node _T_549 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_550 = and(_T_548, _T_549) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_551 = shr(io.in.a.bits.source, 2) node _T_552 = eq(_T_551, UInt<2>(0h2)) node _T_553 = leq(UInt<1>(0h0), uncommonBits_26) node _T_554 = and(_T_552, _T_553) node _T_555 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_556 = and(_T_554, _T_555) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_557 = shr(io.in.a.bits.source, 2) node _T_558 = eq(_T_557, UInt<2>(0h3)) node _T_559 = leq(UInt<1>(0h0), uncommonBits_27) node _T_560 = and(_T_558, _T_559) node _T_561 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_562 = and(_T_560, _T_561) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_569 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_570 = or(_T_538, _T_544) node _T_571 = or(_T_570, _T_550) node _T_572 = or(_T_571, _T_556) node _T_573 = or(_T_572, _T_562) node _T_574 = or(_T_573, _T_563) node _T_575 = or(_T_574, _T_564) node _T_576 = or(_T_575, _T_565) node _T_577 = or(_T_576, _T_566) node _T_578 = or(_T_577, _T_567) node _T_579 = or(_T_578, _T_568) node _T_580 = or(_T_579, _T_569) node _T_581 = and(_T_537, _T_580) node _T_582 = or(UInt<1>(0h0), _T_581) node _T_583 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_584 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_585 = and(_T_583, _T_584) node _T_586 = or(UInt<1>(0h0), _T_585) node _T_587 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_588 = cvt(_T_587) node _T_589 = and(_T_588, asSInt(UInt<13>(0h1000))) node _T_590 = asSInt(_T_589) node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0))) node _T_592 = and(_T_586, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = and(_T_582, _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_594, UInt<1>(0h1), "") : assert_26 node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(source_ok, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_601 = asUInt(reset) node _T_602 = eq(_T_601, UInt<1>(0h0)) when _T_602 : node _T_603 = eq(is_aligned, UInt<1>(0h0)) when _T_603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_604 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_604, UInt<1>(0h1), "") : assert_29 node _T_608 = eq(io.in.a.bits.mask, mask) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_608, UInt<1>(0h1), "") : assert_30 node _T_612 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_612 : node _T_613 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_614 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_615 = and(_T_613, _T_614) node _T_616 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_617 = shr(io.in.a.bits.source, 2) node _T_618 = eq(_T_617, UInt<1>(0h0)) node _T_619 = leq(UInt<1>(0h0), uncommonBits_28) node _T_620 = and(_T_618, _T_619) node _T_621 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_622 = and(_T_620, _T_621) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_623 = shr(io.in.a.bits.source, 2) node _T_624 = eq(_T_623, UInt<1>(0h1)) node _T_625 = leq(UInt<1>(0h0), uncommonBits_29) node _T_626 = and(_T_624, _T_625) node _T_627 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_629 = shr(io.in.a.bits.source, 2) node _T_630 = eq(_T_629, UInt<2>(0h2)) node _T_631 = leq(UInt<1>(0h0), uncommonBits_30) node _T_632 = and(_T_630, _T_631) node _T_633 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_634 = and(_T_632, _T_633) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_635 = shr(io.in.a.bits.source, 2) node _T_636 = eq(_T_635, UInt<2>(0h3)) node _T_637 = leq(UInt<1>(0h0), uncommonBits_31) node _T_638 = and(_T_636, _T_637) node _T_639 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_640 = and(_T_638, _T_639) node _T_641 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_642 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_643 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_616, _T_622) node _T_649 = or(_T_648, _T_628) node _T_650 = or(_T_649, _T_634) node _T_651 = or(_T_650, _T_640) node _T_652 = or(_T_651, _T_641) node _T_653 = or(_T_652, _T_642) node _T_654 = or(_T_653, _T_643) node _T_655 = or(_T_654, _T_644) node _T_656 = or(_T_655, _T_645) node _T_657 = or(_T_656, _T_646) node _T_658 = or(_T_657, _T_647) node _T_659 = and(_T_615, _T_658) node _T_660 = or(UInt<1>(0h0), _T_659) node _T_661 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_662 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_663 = and(_T_661, _T_662) node _T_664 = or(UInt<1>(0h0), _T_663) node _T_665 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<13>(0h1000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = and(_T_664, _T_669) node _T_671 = or(UInt<1>(0h0), _T_670) node _T_672 = and(_T_660, _T_671) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_672, UInt<1>(0h1), "") : assert_31 node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(source_ok, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(is_aligned, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_682 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_T_682, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_682, UInt<1>(0h1), "") : assert_34 node _T_686 = not(mask) node _T_687 = and(io.in.a.bits.mask, _T_686) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_688, UInt<1>(0h1), "") : assert_35 node _T_692 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_692 : node _T_693 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_694 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_695 = and(_T_693, _T_694) node _T_696 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<1>(0h0)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_32) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_703 = shr(io.in.a.bits.source, 2) node _T_704 = eq(_T_703, UInt<1>(0h1)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_33) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_708 = and(_T_706, _T_707) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_709 = shr(io.in.a.bits.source, 2) node _T_710 = eq(_T_709, UInt<2>(0h2)) node _T_711 = leq(UInt<1>(0h0), uncommonBits_34) node _T_712 = and(_T_710, _T_711) node _T_713 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_714 = and(_T_712, _T_713) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_715 = shr(io.in.a.bits.source, 2) node _T_716 = eq(_T_715, UInt<2>(0h3)) node _T_717 = leq(UInt<1>(0h0), uncommonBits_35) node _T_718 = and(_T_716, _T_717) node _T_719 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_720 = and(_T_718, _T_719) node _T_721 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_722 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_725 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_726 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_727 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_728 = or(_T_696, _T_702) node _T_729 = or(_T_728, _T_708) node _T_730 = or(_T_729, _T_714) node _T_731 = or(_T_730, _T_720) node _T_732 = or(_T_731, _T_721) node _T_733 = or(_T_732, _T_722) node _T_734 = or(_T_733, _T_723) node _T_735 = or(_T_734, _T_724) node _T_736 = or(_T_735, _T_725) node _T_737 = or(_T_736, _T_726) node _T_738 = or(_T_737, _T_727) node _T_739 = and(_T_695, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_742 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_743 = cvt(_T_742) node _T_744 = and(_T_743, asSInt(UInt<13>(0h1000))) node _T_745 = asSInt(_T_744) node _T_746 = eq(_T_745, asSInt(UInt<1>(0h0))) node _T_747 = and(_T_741, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = and(_T_740, _T_748) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_749, UInt<1>(0h1), "") : assert_36 node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(source_ok, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(is_aligned, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_759 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_759, UInt<1>(0h1), "") : assert_39 node _T_763 = eq(io.in.a.bits.mask, mask) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_763, UInt<1>(0h1), "") : assert_40 node _T_767 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_767 : node _T_768 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_769 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_770 = and(_T_768, _T_769) node _T_771 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<1>(0h0)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_36) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<1>(0h1)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_37) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_784 = shr(io.in.a.bits.source, 2) node _T_785 = eq(_T_784, UInt<2>(0h2)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_38) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_789 = and(_T_787, _T_788) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_790 = shr(io.in.a.bits.source, 2) node _T_791 = eq(_T_790, UInt<2>(0h3)) node _T_792 = leq(UInt<1>(0h0), uncommonBits_39) node _T_793 = and(_T_791, _T_792) node _T_794 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_802 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_803 = or(_T_771, _T_777) node _T_804 = or(_T_803, _T_783) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_795) node _T_807 = or(_T_806, _T_796) node _T_808 = or(_T_807, _T_797) node _T_809 = or(_T_808, _T_798) node _T_810 = or(_T_809, _T_799) node _T_811 = or(_T_810, _T_800) node _T_812 = or(_T_811, _T_801) node _T_813 = or(_T_812, _T_802) node _T_814 = and(_T_770, _T_813) node _T_815 = or(UInt<1>(0h0), _T_814) node _T_816 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_817 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_818 = cvt(_T_817) node _T_819 = and(_T_818, asSInt(UInt<13>(0h1000))) node _T_820 = asSInt(_T_819) node _T_821 = eq(_T_820, asSInt(UInt<1>(0h0))) node _T_822 = and(_T_816, _T_821) node _T_823 = or(UInt<1>(0h0), _T_822) node _T_824 = and(_T_815, _T_823) node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(_T_824, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_824, UInt<1>(0h1), "") : assert_41 node _T_828 = asUInt(reset) node _T_829 = eq(_T_828, UInt<1>(0h0)) when _T_829 : node _T_830 = eq(source_ok, UInt<1>(0h0)) when _T_830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(is_aligned, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_834 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_834, UInt<1>(0h1), "") : assert_44 node _T_838 = eq(io.in.a.bits.mask, mask) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_838, UInt<1>(0h1), "") : assert_45 node _T_842 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_842 : node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_847 = shr(io.in.a.bits.source, 2) node _T_848 = eq(_T_847, UInt<1>(0h0)) node _T_849 = leq(UInt<1>(0h0), uncommonBits_40) node _T_850 = and(_T_848, _T_849) node _T_851 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<1>(0h1)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_41) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<2>(0h2)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_42) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_865 = shr(io.in.a.bits.source, 2) node _T_866 = eq(_T_865, UInt<2>(0h3)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_43) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_870 = and(_T_868, _T_869) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_873 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_874 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_875 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_876 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_878 = or(_T_846, _T_852) node _T_879 = or(_T_878, _T_858) node _T_880 = or(_T_879, _T_864) node _T_881 = or(_T_880, _T_870) node _T_882 = or(_T_881, _T_871) node _T_883 = or(_T_882, _T_872) node _T_884 = or(_T_883, _T_873) node _T_885 = or(_T_884, _T_874) node _T_886 = or(_T_885, _T_875) node _T_887 = or(_T_886, _T_876) node _T_888 = or(_T_887, _T_877) node _T_889 = and(_T_845, _T_888) node _T_890 = or(UInt<1>(0h0), _T_889) node _T_891 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_892 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), _T_897) node _T_899 = and(_T_890, _T_898) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_899, UInt<1>(0h1), "") : assert_46 node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(source_ok, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(is_aligned, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_909 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(_T_909, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_909, UInt<1>(0h1), "") : assert_49 node _T_913 = eq(io.in.a.bits.mask, mask) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_913, UInt<1>(0h1), "") : assert_50 node _T_917 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_917, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_921 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_921, UInt<1>(0h1), "") : assert_52 node _source_ok_T_42 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h0)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<1>(0h1)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h2)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<2>(0h3)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_68 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[12] connect _source_ok_WIRE_1[0], _source_ok_T_42 connect _source_ok_WIRE_1[1], _source_ok_T_48 connect _source_ok_WIRE_1[2], _source_ok_T_54 connect _source_ok_WIRE_1[3], _source_ok_T_60 connect _source_ok_WIRE_1[4], _source_ok_T_66 connect _source_ok_WIRE_1[5], _source_ok_T_67 connect _source_ok_WIRE_1[6], _source_ok_T_68 connect _source_ok_WIRE_1[7], _source_ok_T_69 connect _source_ok_WIRE_1[8], _source_ok_T_70 connect _source_ok_WIRE_1[9], _source_ok_T_71 connect _source_ok_WIRE_1[10], _source_ok_T_72 connect _source_ok_WIRE_1[11], _source_ok_T_73 node _source_ok_T_74 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[2]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[3]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[4]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[5]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[6]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[7]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[8]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[9]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[10]) node source_ok_1 = or(_source_ok_T_83, _source_ok_WIRE_1[11]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_925 : node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(source_ok_1, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_929 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_929, UInt<1>(0h1), "") : assert_54 node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_933, UInt<1>(0h1), "") : assert_55 node _T_937 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_937, UInt<1>(0h1), "") : assert_56 node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_941, UInt<1>(0h1), "") : assert_57 node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_945 : node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok_1, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(sink_ok, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_952 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_952, UInt<1>(0h1), "") : assert_60 node _T_956 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_956, UInt<1>(0h1), "") : assert_61 node _T_960 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_960, UInt<1>(0h1), "") : assert_62 node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_964, UInt<1>(0h1), "") : assert_63 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_969, UInt<1>(0h1), "") : assert_64 node _T_973 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(sink_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_980 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_980, UInt<1>(0h1), "") : assert_67 node _T_984 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_984, UInt<1>(0h1), "") : assert_68 node _T_988 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_988, UInt<1>(0h1), "") : assert_69 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(_T_992, io.in.d.bits.corrupt) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_993, UInt<1>(0h1), "") : assert_70 node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_998 = or(UInt<1>(0h0), _T_997) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_998, UInt<1>(0h1), "") : assert_71 node _T_1002 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_73 node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_74 node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1015 = or(UInt<1>(0h0), _T_1014) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_75 node _T_1019 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1019 : node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(source_ok_1, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1023 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_77 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = or(_T_1027, io.in.d.bits.corrupt) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_78 node _T_1032 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1033 = or(UInt<1>(0h0), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_79 node _T_1037 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1037 : node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(source_ok_1, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_81 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_82 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1054 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1058 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1062 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1066 = eq(a_first, UInt<1>(0h0)) node _T_1067 = and(io.in.a.valid, _T_1066) when _T_1067 : node _T_1068 = eq(io.in.a.bits.opcode, opcode) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_87 node _T_1072 = eq(io.in.a.bits.param, param) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_88 node _T_1076 = eq(io.in.a.bits.size, size) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_89 node _T_1080 = eq(io.in.a.bits.source, source) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_90 node _T_1084 = eq(io.in.a.bits.address, address) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_91 node _T_1088 = and(io.in.a.ready, io.in.a.valid) node _T_1089 = and(_T_1088, a_first) when _T_1089 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1090 = eq(d_first, UInt<1>(0h0)) node _T_1091 = and(io.in.d.valid, _T_1090) when _T_1091 : node _T_1092 = eq(io.in.d.bits.opcode, opcode_1) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_92 node _T_1096 = eq(io.in.d.bits.param, param_1) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_93 node _T_1100 = eq(io.in.d.bits.size, size_1) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_94 node _T_1104 = eq(io.in.d.bits.source, source_1) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_95 node _T_1108 = eq(io.in.d.bits.sink, sink) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_96 node _T_1112 = eq(io.in.d.bits.denied, denied) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_97 node _T_1116 = and(io.in.d.ready, io.in.d.valid) node _T_1117 = and(_T_1116, d_first) when _T_1117 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1118 = and(io.in.a.valid, a_first_1) node _T_1119 = and(_T_1118, UInt<1>(0h1)) when _T_1119 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1120 = and(io.in.a.ready, io.in.a.valid) node _T_1121 = and(_T_1120, a_first_1) node _T_1122 = and(_T_1121, UInt<1>(0h1)) when _T_1122 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1123 = dshr(inflight, io.in.a.bits.source) node _T_1124 = bits(_T_1123, 0, 0) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1129 = and(io.in.d.valid, d_first_1) node _T_1130 = and(_T_1129, UInt<1>(0h1)) node _T_1131 = eq(d_release_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1133 = and(io.in.d.ready, io.in.d.valid) node _T_1134 = and(_T_1133, d_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) node _T_1136 = eq(d_release_ack, UInt<1>(0h0)) node _T_1137 = and(_T_1135, _T_1136) when _T_1137 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1138 = and(io.in.d.valid, d_first_1) node _T_1139 = and(_T_1138, UInt<1>(0h1)) node _T_1140 = eq(d_release_ack, UInt<1>(0h0)) node _T_1141 = and(_T_1139, _T_1140) when _T_1141 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1142 = dshr(inflight, io.in.d.bits.source) node _T_1143 = bits(_T_1142, 0, 0) node _T_1144 = or(_T_1143, same_cycle_resp) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1148 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1149 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1150 = or(_T_1148, _T_1149) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_100 node _T_1154 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_101 else : node _T_1158 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1159 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1160 = or(_T_1158, _T_1159) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_102 node _T_1164 = eq(io.in.d.bits.size, a_size_lookup) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_103 node _T_1168 = and(io.in.d.valid, d_first_1) node _T_1169 = and(_T_1168, a_first_1) node _T_1170 = and(_T_1169, io.in.a.valid) node _T_1171 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1172 = and(_T_1170, _T_1171) node _T_1173 = eq(d_release_ack, UInt<1>(0h0)) node _T_1174 = and(_T_1172, _T_1173) when _T_1174 : node _T_1175 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1176 = or(_T_1175, io.in.a.ready) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_52 node _T_1180 = orr(inflight) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) node _T_1182 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1183 = or(_T_1181, _T_1182) node _T_1184 = lt(watchdog, plusarg_reader.out) node _T_1185 = or(_T_1183, _T_1184) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1189 = and(io.in.a.ready, io.in.a.valid) node _T_1190 = and(io.in.d.ready, io.in.d.valid) node _T_1191 = or(_T_1189, _T_1190) when _T_1191 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1192 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1193 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1194 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = and(_T_1192, _T_1195) when _T_1196 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1197 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1198 = and(_T_1197, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1199 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1200 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = and(_T_1198, _T_1201) when _T_1202 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1203 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1209 = and(io.in.d.valid, d_first_2) node _T_1210 = and(_T_1209, UInt<1>(0h1)) node _T_1211 = and(_T_1210, d_release_ack_1) when _T_1211 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1212 = and(io.in.d.ready, io.in.d.valid) node _T_1213 = and(_T_1212, d_first_2) node _T_1214 = and(_T_1213, UInt<1>(0h1)) node _T_1215 = and(_T_1214, d_release_ack_1) when _T_1215 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1216 = and(io.in.d.valid, d_first_2) node _T_1217 = and(_T_1216, UInt<1>(0h1)) node _T_1218 = and(_T_1217, d_release_ack_1) when _T_1218 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1219 = dshr(inflight_1, io.in.d.bits.source) node _T_1220 = bits(_T_1219, 0, 0) node _T_1221 = or(_T_1220, same_cycle_resp_1) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1225 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_108 else : node _T_1229 = eq(io.in.d.bits.size, c_size_lookup) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_109 node _T_1233 = and(io.in.d.valid, d_first_2) node _T_1234 = and(_T_1233, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1235 = and(_T_1234, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1236 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1237 = and(_T_1235, _T_1236) node _T_1238 = and(_T_1237, d_release_ack_1) node _T_1239 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1240 = and(_T_1238, _T_1239) when _T_1240 : node _T_1241 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1242 = or(_T_1241, _WIRE_27.ready) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_53 node _T_1246 = orr(inflight_1) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) node _T_1248 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1249 = or(_T_1247, _T_1248) node _T_1250 = lt(watchdog_1, plusarg_reader_1.out) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1255 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1256 = and(io.in.d.ready, io.in.d.valid) node _T_1257 = or(_T_1255, _T_1256) when _T_1257 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_26( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_41 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_61 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_44 = _source_ok_T_43 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire _source_ok_T_67 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire _source_ok_T_68 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire _source_ok_T_69 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_82 = _source_ok_T_81 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_83 = _source_ok_T_82 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_83 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _T_1189 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1189; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1189; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1257 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1257; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1122 = _T_1189 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1122 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1122 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1122 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1122 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1122 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1168 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1168 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1137 = _T_1257 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1137 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1137 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1137 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1233 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1233 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1215 = _T_1257 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1215 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1215 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1215 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_12 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] connect auto.out, nodeOut connect nodeIn, auto.in inst reg of AsyncResetRegVec_w1_i0_12 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] connect reg.io.en, UInt<1>(0h1) node _T = bits(reg.io.q, 0, 0) connect nodeOut.sync[0], _T	module IntSyncCrossingSource_n1x1_12( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_12 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_205 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_205( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module Router_12 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[4], sa_stall : UInt[4]}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_12 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_1.flit.bits.egress_id invalidate ingressNodesIn_1.flit.bits.payload invalidate ingressNodesIn_1.flit.bits.tail invalidate ingressNodesIn_1.flit.bits.head invalidate ingressNodesIn_1.flit.valid invalidate ingressNodesIn_1.flit.ready wire ingressNodesIn_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_2.flit.bits.egress_id invalidate ingressNodesIn_2.flit.bits.payload invalidate ingressNodesIn_2.flit.bits.tail invalidate ingressNodesIn_2.flit.bits.head invalidate ingressNodesIn_2.flit.valid invalidate ingressNodesIn_2.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut_1.flit.bits.ingress_id invalidate egressNodesOut_1.flit.bits.payload invalidate egressNodesOut_1.flit.bits.tail invalidate egressNodesOut_1.flit.bits.head invalidate egressNodesOut_1.flit.valid invalidate egressNodesOut_1.flit.ready wire debugNodeOut : { va_stall : UInt[4], sa_stall : UInt[4]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.sa_stall[3] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] invalidate debugNodeOut.va_stall[3] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in_0 connect ingressNodesIn_1, auto.ingress_nodes_in_1 connect ingressNodesIn_2, auto.ingress_nodes_in_2 connect auto.egress_nodes_out_0, egressNodesOut connect auto.egress_nodes_out_1, egressNodesOut_1 connect auto.debug_out, debugNodeOut inst input_unit_0_from_29 of InputUnit_12 connect input_unit_0_from_29.clock, clock connect input_unit_0_from_29.reset, reset inst ingress_unit_1_from_21 of IngressUnit_31 connect ingress_unit_1_from_21.clock, clock connect ingress_unit_1_from_21.reset, reset inst ingress_unit_2_from_22 of IngressUnit_32 connect ingress_unit_2_from_22.clock, clock connect ingress_unit_2_from_22.reset, reset inst ingress_unit_3_from_23 of IngressUnit_33 connect ingress_unit_3_from_23.clock, clock connect ingress_unit_3_from_23.reset, reset inst output_unit_0_to_29 of OutputUnit_12 connect output_unit_0_to_29.clock, clock connect output_unit_0_to_29.reset, reset inst egress_unit_1_to_14 of EgressUnit_29 connect egress_unit_1_to_14.clock, clock connect egress_unit_1_to_14.reset, reset inst egress_unit_2_to_15 of EgressUnit_30 connect egress_unit_2_to_15.clock, clock connect egress_unit_2_to_15.reset, reset inst switch of Switch_12 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_12 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_12 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_12 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid) node _fires_count_T_4 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_5 = bits(_fires_count_T_4, 1, 0) node _fires_count_T_6 = add(_fires_count_T_2, _fires_count_T_3) node _fires_count_T_7 = bits(_fires_count_T_6, 1, 0) node _fires_count_T_8 = add(_fires_count_T_5, _fires_count_T_7) node _fires_count_T_9 = bits(_fires_count_T_8, 2, 0) wire fires_count : UInt connect fires_count, _fires_count_T_9 connect input_unit_0_from_29.io.in, destNodesIn connect ingress_unit_1_from_21.io.in, ingressNodesIn.flit connect ingress_unit_2_from_22.io.in, ingressNodesIn_1.flit connect ingress_unit_3_from_23.io.in, ingressNodesIn_2.flit connect output_unit_0_to_29.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_29.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_29.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_14.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_14.io.out.valid connect egress_unit_1_to_14.io.out.ready, egressNodesOut.flit.ready connect egressNodesOut_1.flit.bits, egress_unit_2_to_15.io.out.bits connect egressNodesOut_1.flit.valid, egress_unit_2_to_15.io.out.valid connect egress_unit_2_to_15.io.out.ready, egressNodesOut_1.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_29.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_21.io.router_req connect route_computer.io.req.`2`, ingress_unit_2_from_22.io.router_req connect route_computer.io.req.`3`, ingress_unit_3_from_23.io.router_req connect input_unit_0_from_29.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_21.io.router_resp, route_computer.io.resp.`1` connect ingress_unit_2_from_22.io.router_resp, route_computer.io.resp.`2` connect ingress_unit_3_from_23.io.router_resp, route_computer.io.resp.`3` connect vc_allocator.io.req.`0`, input_unit_0_from_29.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_21.io.vcalloc_req connect vc_allocator.io.req.`2`, ingress_unit_2_from_22.io.vcalloc_req connect vc_allocator.io.req.`3`, ingress_unit_3_from_23.io.vcalloc_req connect input_unit_0_from_29.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_21.io.vcalloc_resp, vc_allocator.io.resp.`1` connect ingress_unit_2_from_22.io.vcalloc_resp, vc_allocator.io.resp.`2` connect ingress_unit_3_from_23.io.vcalloc_resp, vc_allocator.io.resp.`3` connect output_unit_0_to_29.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_14.io.allocs, vc_allocator.io.out_allocs.`1` connect egress_unit_2_to_15.io.allocs, vc_allocator.io.out_allocs.`2` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_29.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_29.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_29.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_29.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_29.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_29.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_29.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_29.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_29.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_29.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_29.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_29.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_29.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_29.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_29.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_29.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_29.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_29.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_29.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_29.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_29.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_29.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_29.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_29.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_29.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_29.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_29.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_29.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_29.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_29.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_29.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_29.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_29.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_29.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_29.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_29.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_29.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_29.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_29.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_29.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_14.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_14.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_14.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_14.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_14.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_14.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_15.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_15.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_15.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_15.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_15.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_15.io.channel_status[0].occupied connect input_unit_0_from_29.io.out_credit_available.`0`[0], output_unit_0_to_29.io.credit_available[0] connect input_unit_0_from_29.io.out_credit_available.`0`[1], output_unit_0_to_29.io.credit_available[1] connect input_unit_0_from_29.io.out_credit_available.`0`[2], output_unit_0_to_29.io.credit_available[2] connect input_unit_0_from_29.io.out_credit_available.`0`[3], output_unit_0_to_29.io.credit_available[3] connect input_unit_0_from_29.io.out_credit_available.`0`[4], output_unit_0_to_29.io.credit_available[4] connect input_unit_0_from_29.io.out_credit_available.`0`[5], output_unit_0_to_29.io.credit_available[5] connect input_unit_0_from_29.io.out_credit_available.`0`[6], output_unit_0_to_29.io.credit_available[6] connect input_unit_0_from_29.io.out_credit_available.`0`[7], output_unit_0_to_29.io.credit_available[7] connect input_unit_0_from_29.io.out_credit_available.`1`[0], egress_unit_1_to_14.io.credit_available[0] connect input_unit_0_from_29.io.out_credit_available.`2`[0], egress_unit_2_to_15.io.credit_available[0] connect ingress_unit_1_from_21.io.out_credit_available.`0`[0], output_unit_0_to_29.io.credit_available[0] connect ingress_unit_1_from_21.io.out_credit_available.`0`[1], output_unit_0_to_29.io.credit_available[1] connect ingress_unit_1_from_21.io.out_credit_available.`0`[2], output_unit_0_to_29.io.credit_available[2] connect ingress_unit_1_from_21.io.out_credit_available.`0`[3], output_unit_0_to_29.io.credit_available[3] connect ingress_unit_1_from_21.io.out_credit_available.`0`[4], output_unit_0_to_29.io.credit_available[4] connect ingress_unit_1_from_21.io.out_credit_available.`0`[5], output_unit_0_to_29.io.credit_available[5] connect ingress_unit_1_from_21.io.out_credit_available.`0`[6], output_unit_0_to_29.io.credit_available[6] connect ingress_unit_1_from_21.io.out_credit_available.`0`[7], output_unit_0_to_29.io.credit_available[7] connect ingress_unit_1_from_21.io.out_credit_available.`1`[0], egress_unit_1_to_14.io.credit_available[0] connect ingress_unit_1_from_21.io.out_credit_available.`2`[0], egress_unit_2_to_15.io.credit_available[0] connect ingress_unit_2_from_22.io.out_credit_available.`0`[0], output_unit_0_to_29.io.credit_available[0] connect ingress_unit_2_from_22.io.out_credit_available.`0`[1], output_unit_0_to_29.io.credit_available[1] connect ingress_unit_2_from_22.io.out_credit_available.`0`[2], output_unit_0_to_29.io.credit_available[2] connect ingress_unit_2_from_22.io.out_credit_available.`0`[3], output_unit_0_to_29.io.credit_available[3] connect ingress_unit_2_from_22.io.out_credit_available.`0`[4], output_unit_0_to_29.io.credit_available[4] connect ingress_unit_2_from_22.io.out_credit_available.`0`[5], output_unit_0_to_29.io.credit_available[5] connect ingress_unit_2_from_22.io.out_credit_available.`0`[6], output_unit_0_to_29.io.credit_available[6] connect ingress_unit_2_from_22.io.out_credit_available.`0`[7], output_unit_0_to_29.io.credit_available[7] connect ingress_unit_2_from_22.io.out_credit_available.`1`[0], egress_unit_1_to_14.io.credit_available[0] connect ingress_unit_2_from_22.io.out_credit_available.`2`[0], egress_unit_2_to_15.io.credit_available[0] connect ingress_unit_3_from_23.io.out_credit_available.`0`[0], output_unit_0_to_29.io.credit_available[0] connect ingress_unit_3_from_23.io.out_credit_available.`0`[1], output_unit_0_to_29.io.credit_available[1] connect ingress_unit_3_from_23.io.out_credit_available.`0`[2], output_unit_0_to_29.io.credit_available[2] connect ingress_unit_3_from_23.io.out_credit_available.`0`[3], output_unit_0_to_29.io.credit_available[3] connect ingress_unit_3_from_23.io.out_credit_available.`0`[4], output_unit_0_to_29.io.credit_available[4] connect ingress_unit_3_from_23.io.out_credit_available.`0`[5], output_unit_0_to_29.io.credit_available[5] connect ingress_unit_3_from_23.io.out_credit_available.`0`[6], output_unit_0_to_29.io.credit_available[6] connect ingress_unit_3_from_23.io.out_credit_available.`0`[7], output_unit_0_to_29.io.credit_available[7] connect ingress_unit_3_from_23.io.out_credit_available.`1`[0], egress_unit_1_to_14.io.credit_available[0] connect ingress_unit_3_from_23.io.out_credit_available.`2`[0], egress_unit_2_to_15.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_29.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_21.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_22.io.salloc_req[0] connect switch_allocator.io.req.`3`[0], ingress_unit_3_from_23.io.salloc_req[0] connect output_unit_0_to_29.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_29.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_29.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_29.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_29.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_29.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_29.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_29.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_29.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_29.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_0_to_29.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail connect output_unit_0_to_29.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc connect output_unit_0_to_29.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail connect output_unit_0_to_29.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc connect output_unit_0_to_29.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail connect output_unit_0_to_29.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc connect egress_unit_1_to_14.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_14.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect egress_unit_2_to_15.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect egress_unit_2_to_15.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_29.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_21.io.out[0] connect switch.io.in.`2`[0], ingress_unit_2_from_22.io.out[0] connect switch.io.in.`3`[0], ingress_unit_3_from_23.io.out[0] connect output_unit_0_to_29.io.in, switch.io.out.`0` connect egress_unit_1_to_14.io.in, switch.io.out.`1` connect egress_unit_2_to_15.io.in, switch.io.out.`2` reg REG : { `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`0`[0].`3`[0], REG.`0`[0].`3`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`1`[0].`3`[0], REG.`1`[0].`3`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect switch.io.sel.`2`[0].`3`[0], REG.`2`[0].`3`[0] connect input_unit_0_from_29.io.block, UInt<1>(0h0) connect ingress_unit_1_from_21.io.block, UInt<1>(0h0) connect ingress_unit_2_from_22.io.block, UInt<1>(0h0) connect ingress_unit_3_from_23.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_29.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_21.io.debug.va_stall connect debugNodeOut.va_stall[2], ingress_unit_2_from_22.io.debug.va_stall connect debugNodeOut.va_stall[3], ingress_unit_3_from_23.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_29.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_21.io.debug.sa_stall connect debugNodeOut.sa_stall[2], ingress_unit_2_from_22.io.debug.sa_stall connect debugNodeOut.sa_stall[3], ingress_unit_3_from_23.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_30 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 29 13 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i21 13 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d i22 13 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20 node _T_29 = and(ingressNodesIn_2.flit.ready, ingressNodesIn_2.flit.valid) regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, _T_29) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, _T_29) connect fired_3, _fired_T_3 node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_32 = tail(_T_31, 1) node _T_33 = eq(debug_sample, _T_32) node _T_34 = and(_T_30, _T_33) node _T_35 = and(_T_34, fired_3) when _T_35 : node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "nocsample %d i23 13 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, _T_29 node _T_38 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, _T_38) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, _T_38) connect fired_4, _fired_T_4 node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_41 = tail(_T_40, 1) node _T_42 = eq(debug_sample, _T_41) node _T_43 = and(_T_39, _T_42) node _T_44 = and(_T_43, fired_4) when _T_44 : node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : printf(clock, UInt<1>(0h1), "nocsample %d 13 e14 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, _T_38 node _T_47 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid) regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_10 = add(util_ctr_5, _T_47) node _util_ctr_T_11 = tail(_util_ctr_T_10, 1) connect util_ctr_5, _util_ctr_T_11 node _fired_T_5 = or(fired_5, _T_47) connect fired_5, _fired_T_5 node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_50 = tail(_T_49, 1) node _T_51 = eq(debug_sample, _T_50) node _T_52 = and(_T_48, _T_51) node _T_53 = and(_T_52, fired_5) when _T_53 : node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "nocsample %d 13 e15 %d\n", debug_tsc, util_ctr_5) : printf_5 connect fired_5, _T_47	module Router_12( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [5:0] auto_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_2_to_15_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_2_to_15_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_2_to_15_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_1_to_14_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_14_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_14_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_29_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _ingress_unit_3_from_23_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_3_from_23_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_23_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_23_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_23_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_23_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_23_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_23_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_2_from_22_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_22_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_1_from_21_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_21_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_in_ready; // @[Router.scala:116:13] wire _input_unit_0_from_29_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_29_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_29_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_29_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_29_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_29_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_29_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_29_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_21_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_22_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_23_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg REG_2_0_3_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_3_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_3_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_63 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_129 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_130 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_20 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_20( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter : input clock : Clock input reset : Reset output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlNodeIn.d.bits.corrupt invalidate tlNodeIn.d.bits.data invalidate tlNodeIn.d.bits.denied invalidate tlNodeIn.d.bits.sink invalidate tlNodeIn.d.bits.source invalidate tlNodeIn.d.bits.size invalidate tlNodeIn.d.bits.param invalidate tlNodeIn.d.bits.opcode invalidate tlNodeIn.d.valid invalidate tlNodeIn.d.ready invalidate tlNodeIn.a.bits.corrupt invalidate tlNodeIn.a.bits.data invalidate tlNodeIn.a.bits.mask invalidate tlNodeIn.a.bits.address invalidate tlNodeIn.a.bits.source invalidate tlNodeIn.a.bits.size invalidate tlNodeIn.a.bits.param invalidate tlNodeIn.a.bits.opcode invalidate tlNodeIn.a.valid invalidate tlNodeIn.a.ready inst monitor of TLMonitor_67 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, tlNodeIn.d.valid connect monitor.io.in.d.ready, tlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, tlNodeIn.a.valid connect monitor.io.in.a.ready, tlNodeIn.a.ready wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeOut.member.allClocks_uncore.reset invalidate clockNodeOut.member.allClocks_uncore.clock wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeIn.member.allClocks_uncore.reset invalidate clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut, clockNodeIn connect tlNodeIn, auto.tl_in connect auto.clock_out, clockNodeOut connect clockNodeIn, auto.clock_in wire tile_async_resets : Reset[1] node _tile_async_resets_0_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[0], _tile_async_resets_0_T inst r_tile_resets_0 of AsyncResetRegVec_w1_i0_6 connect r_tile_resets_0.clock, clock connect r_tile_resets_0.reset, tile_async_resets[0] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(tlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, tlNodeIn.a.bits.data connect in.bits.mask, tlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect r_tile_resets_0.io.en, out_f_woready connect r_tile_resets_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(r_tile_resets_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, tlNodeIn.a.valid connect tlNodeIn.a.ready, in.ready connect tlNodeIn.d.valid, out.valid connect out.ready, tlNodeIn.d.ready wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect tlNodeIn_d_bits_d.param, UInt<1>(0h0) connect tlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect tlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate tlNodeIn_d_bits_d.data connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode connect tlNodeIn.d.bits.data, out.bits.data node _tlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset extmodule plusarg_reader_140 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_141 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] wire [11:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33] wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_WIRE_1_0 = 1'h0; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_T_3 = 1'h0; // @[MuxLiteral.scala:49:10] wire _out_out_bits_data_T_4 = 1'h0; // @[RegisterRouter.scala:87:24] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25] wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [11:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] wire [11:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_67 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i0_6 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15] .clock (clock), .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileResetSetter.scala:33:15] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_41 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_41( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLDFromNoC_10 : input clock : Clock input reset : Reset output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, ingress_id : UInt}}} wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1) reg const_reg : UInt<16>, clock node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg) node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0)) node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T) node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready) connect io.flit.ready, _io_flit_ready_T_2 node _protocol_valid_T = eq(is_const, UInt<1>(0h0)) node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail) node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid) connect protocol.valid, _protocol_valid_T_2 wire _protocol_bits_denied_WIRE : UInt<1> connect _protocol_bits_denied_WIRE, const connect protocol.bits.denied, _protocol_bits_denied_WIRE node _T = shr(const, 1) wire _protocol_bits_sink_WIRE : UInt<1> connect _protocol_bits_sink_WIRE, _T connect protocol.bits.sink, _protocol_bits_sink_WIRE node _T_1 = shr(_T, 1) wire _protocol_bits_echo_WIRE : { } wire _protocol_bits_echo_WIRE_1 : UInt<0> connect _protocol_bits_echo_WIRE_1, _T_1 connect protocol.bits.echo, _protocol_bits_echo_WIRE node _T_2 = shr(_T_1, 0) wire _protocol_bits_user_WIRE : { } wire _protocol_bits_user_WIRE_1 : UInt<0> connect _protocol_bits_user_WIRE_1, _T_2 connect protocol.bits.user, _protocol_bits_user_WIRE node _T_3 = shr(_T_2, 0) wire _protocol_bits_source_WIRE : UInt<6> connect _protocol_bits_source_WIRE, _T_3 connect protocol.bits.source, _protocol_bits_source_WIRE node _T_4 = shr(_T_3, 6) wire _protocol_bits_size_WIRE : UInt<3> connect _protocol_bits_size_WIRE, _T_4 connect protocol.bits.size, _protocol_bits_size_WIRE node _T_5 = shr(_T_4, 3) wire _protocol_bits_param_WIRE : UInt<2> connect _protocol_bits_param_WIRE, _T_5 connect protocol.bits.param, _protocol_bits_param_WIRE node _T_6 = shr(_T_5, 2) wire _protocol_bits_opcode_WIRE : UInt<3> connect _protocol_bits_opcode_WIRE, _T_6 connect protocol.bits.opcode, _protocol_bits_opcode_WIRE node _T_7 = shr(_T_6, 3) wire _protocol_bits_corrupt_WIRE : UInt<1> connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE node _T_8 = shr(io.flit.bits.payload, 1) wire _protocol_bits_data_WIRE : UInt<64> connect _protocol_bits_data_WIRE, _T_8 connect protocol.bits.data, _protocol_bits_data_WIRE node _T_9 = shr(_T_8, 64) node _T_10 = and(io.flit.ready, io.flit.valid) node _T_11 = and(_T_10, io.flit.bits.head) when _T_11 : connect is_const, UInt<1>(0h0) connect const_reg, io.flit.bits.payload node _T_12 = and(io.flit.ready, io.flit.valid) node _T_13 = and(_T_12, io.flit.bits.tail) when _T_13 : connect is_const, UInt<1>(0h1) connect io.protocol, protocol node _io_protocol_bits_source_T = bits(protocol.bits.source, 3, 0) connect io.protocol.bits.source, _io_protocol_bits_source_T	module TLDFromNoC_10( // @[TilelinkAdapters.scala:185:7] input clock, // @[TilelinkAdapters.scala:185:7] input reset, // @[TilelinkAdapters.scala:185:7] input io_protocol_ready, // @[TilelinkAdapters.scala:56:14] output io_protocol_valid, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14] output [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14] output [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_sink, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_denied, // @[TilelinkAdapters.scala:56:14] output [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14] output io_flit_ready, // @[TilelinkAdapters.scala:56:14] input io_flit_valid, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14] input [64:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14] ); reg is_const; // @[TilelinkAdapters.scala:68:25] reg [15:0] const_reg; // @[TilelinkAdapters.scala:69:22] wire [15:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[15:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18] wire io_flit_ready_0 = is_const & ~io_flit_bits_tail \| io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}] wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35] wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:185:7] if (reset) // @[TilelinkAdapters.scala:185:7] is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :185:7] else // @[TilelinkAdapters.scala:185:7] is_const <= _GEN & io_flit_bits_tail \| ~_GEN_0 & is_const; // @[Decoupled.scala:51:35] if (_GEN_0) // @[TilelinkAdapters.scala:84:22] const_reg <= io_flit_bits_payload[15:0]; // @[TilelinkAdapters.scala:56:14, :69:22] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_95 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_95( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ZstdCompressorLitRotBuf_2 : input clock : Clock input reset : Reset output io : { flip memwrites_in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>}}, consumer : { flip user_consumed_bytes : UInt<6>, available_output_bytes : UInt<6>, output_valid : UInt<1>, flip output_ready : UInt<1>, output_data : UInt<256>, output_last_chunk : UInt<1>}} inst incoming_writes_Q of Queue4_WriterBundle_12 connect incoming_writes_Q.clock, clock connect incoming_writes_Q.reset, reset connect incoming_writes_Q.io.enq, io.memwrites_in node _T = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid) when _T : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "[lit-rot-buf] dat: 0x%x, bytes: 0x%x, EOM: %d\n", incoming_writes_Q.io.deq.bits.data, incoming_writes_Q.io.deq.bits.validbytes, incoming_writes_Q.io.deq.bits.end_of_message) : printf_1 regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0) inst Queue10_UInt8 of Queue10_UInt8_96 connect Queue10_UInt8.clock, clock connect Queue10_UInt8.reset, reset inst Queue10_UInt8_1 of Queue10_UInt8_97 connect Queue10_UInt8_1.clock, clock connect Queue10_UInt8_1.reset, reset inst Queue10_UInt8_2 of Queue10_UInt8_98 connect Queue10_UInt8_2.clock, clock connect Queue10_UInt8_2.reset, reset inst Queue10_UInt8_3 of Queue10_UInt8_99 connect Queue10_UInt8_3.clock, clock connect Queue10_UInt8_3.reset, reset inst Queue10_UInt8_4 of Queue10_UInt8_100 connect Queue10_UInt8_4.clock, clock connect Queue10_UInt8_4.reset, reset inst Queue10_UInt8_5 of Queue10_UInt8_101 connect Queue10_UInt8_5.clock, clock connect Queue10_UInt8_5.reset, reset inst Queue10_UInt8_6 of Queue10_UInt8_102 connect Queue10_UInt8_6.clock, clock connect Queue10_UInt8_6.reset, reset inst Queue10_UInt8_7 of Queue10_UInt8_103 connect Queue10_UInt8_7.clock, clock connect Queue10_UInt8_7.reset, reset inst Queue10_UInt8_8 of Queue10_UInt8_104 connect Queue10_UInt8_8.clock, clock connect Queue10_UInt8_8.reset, reset inst Queue10_UInt8_9 of Queue10_UInt8_105 connect Queue10_UInt8_9.clock, clock connect Queue10_UInt8_9.reset, reset inst Queue10_UInt8_10 of Queue10_UInt8_106 connect Queue10_UInt8_10.clock, clock connect Queue10_UInt8_10.reset, reset inst Queue10_UInt8_11 of Queue10_UInt8_107 connect Queue10_UInt8_11.clock, clock connect Queue10_UInt8_11.reset, reset inst Queue10_UInt8_12 of Queue10_UInt8_108 connect Queue10_UInt8_12.clock, clock connect Queue10_UInt8_12.reset, reset inst Queue10_UInt8_13 of Queue10_UInt8_109 connect Queue10_UInt8_13.clock, clock connect Queue10_UInt8_13.reset, reset inst Queue10_UInt8_14 of Queue10_UInt8_110 connect Queue10_UInt8_14.clock, clock connect Queue10_UInt8_14.reset, reset inst Queue10_UInt8_15 of Queue10_UInt8_111 connect Queue10_UInt8_15.clock, clock connect Queue10_UInt8_15.reset, reset inst Queue10_UInt8_16 of Queue10_UInt8_112 connect Queue10_UInt8_16.clock, clock connect Queue10_UInt8_16.reset, reset inst Queue10_UInt8_17 of Queue10_UInt8_113 connect Queue10_UInt8_17.clock, clock connect Queue10_UInt8_17.reset, reset inst Queue10_UInt8_18 of Queue10_UInt8_114 connect Queue10_UInt8_18.clock, clock connect Queue10_UInt8_18.reset, reset inst Queue10_UInt8_19 of Queue10_UInt8_115 connect Queue10_UInt8_19.clock, clock connect Queue10_UInt8_19.reset, reset inst Queue10_UInt8_20 of Queue10_UInt8_116 connect Queue10_UInt8_20.clock, clock connect Queue10_UInt8_20.reset, reset inst Queue10_UInt8_21 of Queue10_UInt8_117 connect Queue10_UInt8_21.clock, clock connect Queue10_UInt8_21.reset, reset inst Queue10_UInt8_22 of Queue10_UInt8_118 connect Queue10_UInt8_22.clock, clock connect Queue10_UInt8_22.reset, reset inst Queue10_UInt8_23 of Queue10_UInt8_119 connect Queue10_UInt8_23.clock, clock connect Queue10_UInt8_23.reset, reset inst Queue10_UInt8_24 of Queue10_UInt8_120 connect Queue10_UInt8_24.clock, clock connect Queue10_UInt8_24.reset, reset inst Queue10_UInt8_25 of Queue10_UInt8_121 connect Queue10_UInt8_25.clock, clock connect Queue10_UInt8_25.reset, reset inst Queue10_UInt8_26 of Queue10_UInt8_122 connect Queue10_UInt8_26.clock, clock connect Queue10_UInt8_26.reset, reset inst Queue10_UInt8_27 of Queue10_UInt8_123 connect Queue10_UInt8_27.clock, clock connect Queue10_UInt8_27.reset, reset inst Queue10_UInt8_28 of Queue10_UInt8_124 connect Queue10_UInt8_28.clock, clock connect Queue10_UInt8_28.reset, reset inst Queue10_UInt8_29 of Queue10_UInt8_125 connect Queue10_UInt8_29.clock, clock connect Queue10_UInt8_29.reset, reset inst Queue10_UInt8_30 of Queue10_UInt8_126 connect Queue10_UInt8_30.clock, clock connect Queue10_UInt8_30.reset, reset inst Queue10_UInt8_31 of Queue10_UInt8_127 connect Queue10_UInt8_31.clock, clock connect Queue10_UInt8_31.reset, reset connect Queue10_UInt8.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_1.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_2.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_3.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_4.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_5.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_6.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_7.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_8.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_9.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_10.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_11.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_12.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_13.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_14.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_15.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_16.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_17.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_18.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_19.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_20.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_21.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_22.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_23.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_24.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_25.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_26.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_27.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_28.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_29.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_30.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_31.io.enq.bits, UInt<1>(0h0) node _idx_T = add(write_start_index, UInt<1>(0h0)) node idx = rem(_idx_T, UInt<6>(0h20)) node _T_5 = eq(UInt<1>(0h0), idx) when _T_5 : node _T_6 = shl(UInt<1>(0h0), 3) node _T_7 = dshr(incoming_writes_Q.io.deq.bits.data, _T_6) connect Queue10_UInt8.io.enq.bits, _T_7 node _T_8 = eq(UInt<1>(0h1), idx) when _T_8 : node _T_9 = shl(UInt<1>(0h0), 3) node _T_10 = dshr(incoming_writes_Q.io.deq.bits.data, _T_9) connect Queue10_UInt8_1.io.enq.bits, _T_10 node _T_11 = eq(UInt<2>(0h2), idx) when _T_11 : node _T_12 = shl(UInt<1>(0h0), 3) node _T_13 = dshr(incoming_writes_Q.io.deq.bits.data, _T_12) connect Queue10_UInt8_2.io.enq.bits, _T_13 node _T_14 = eq(UInt<2>(0h3), idx) when _T_14 : node _T_15 = shl(UInt<1>(0h0), 3) node _T_16 = dshr(incoming_writes_Q.io.deq.bits.data, _T_15) connect Queue10_UInt8_3.io.enq.bits, _T_16 node _T_17 = eq(UInt<3>(0h4), idx) when _T_17 : node _T_18 = shl(UInt<1>(0h0), 3) node _T_19 = dshr(incoming_writes_Q.io.deq.bits.data, _T_18) connect Queue10_UInt8_4.io.enq.bits, _T_19 node _T_20 = eq(UInt<3>(0h5), idx) when _T_20 : node _T_21 = shl(UInt<1>(0h0), 3) node _T_22 = dshr(incoming_writes_Q.io.deq.bits.data, _T_21) connect Queue10_UInt8_5.io.enq.bits, _T_22 node _T_23 = eq(UInt<3>(0h6), idx) when _T_23 : node _T_24 = shl(UInt<1>(0h0), 3) node _T_25 = dshr(incoming_writes_Q.io.deq.bits.data, _T_24) connect Queue10_UInt8_6.io.enq.bits, _T_25 node _T_26 = eq(UInt<3>(0h7), idx) when _T_26 : node _T_27 = shl(UInt<1>(0h0), 3) node _T_28 = dshr(incoming_writes_Q.io.deq.bits.data, _T_27) connect Queue10_UInt8_7.io.enq.bits, _T_28 node _T_29 = eq(UInt<4>(0h8), idx) when _T_29 : node _T_30 = shl(UInt<1>(0h0), 3) node _T_31 = dshr(incoming_writes_Q.io.deq.bits.data, _T_30) connect Queue10_UInt8_8.io.enq.bits, _T_31 node _T_32 = eq(UInt<4>(0h9), idx) when _T_32 : node _T_33 = shl(UInt<1>(0h0), 3) node _T_34 = dshr(incoming_writes_Q.io.deq.bits.data, _T_33) connect Queue10_UInt8_9.io.enq.bits, _T_34 node _T_35 = eq(UInt<4>(0ha), idx) when _T_35 : node _T_36 = shl(UInt<1>(0h0), 3) node _T_37 = dshr(incoming_writes_Q.io.deq.bits.data, _T_36) connect Queue10_UInt8_10.io.enq.bits, _T_37 node _T_38 = eq(UInt<4>(0hb), idx) when _T_38 : node _T_39 = shl(UInt<1>(0h0), 3) node _T_40 = dshr(incoming_writes_Q.io.deq.bits.data, _T_39) connect Queue10_UInt8_11.io.enq.bits, _T_40 node _T_41 = eq(UInt<4>(0hc), idx) when _T_41 : node _T_42 = shl(UInt<1>(0h0), 3) node _T_43 = dshr(incoming_writes_Q.io.deq.bits.data, _T_42) connect Queue10_UInt8_12.io.enq.bits, _T_43 node _T_44 = eq(UInt<4>(0hd), idx) when _T_44 : node _T_45 = shl(UInt<1>(0h0), 3) node _T_46 = dshr(incoming_writes_Q.io.deq.bits.data, _T_45) connect Queue10_UInt8_13.io.enq.bits, _T_46 node _T_47 = eq(UInt<4>(0he), idx) when _T_47 : node _T_48 = shl(UInt<1>(0h0), 3) node _T_49 = dshr(incoming_writes_Q.io.deq.bits.data, _T_48) connect Queue10_UInt8_14.io.enq.bits, _T_49 node _T_50 = eq(UInt<4>(0hf), idx) when _T_50 : node _T_51 = shl(UInt<1>(0h0), 3) node _T_52 = dshr(incoming_writes_Q.io.deq.bits.data, _T_51) connect Queue10_UInt8_15.io.enq.bits, _T_52 node _T_53 = eq(UInt<5>(0h10), idx) when _T_53 : node _T_54 = shl(UInt<1>(0h0), 3) node _T_55 = dshr(incoming_writes_Q.io.deq.bits.data, _T_54) connect Queue10_UInt8_16.io.enq.bits, _T_55 node _T_56 = eq(UInt<5>(0h11), idx) when _T_56 : node _T_57 = shl(UInt<1>(0h0), 3) node _T_58 = dshr(incoming_writes_Q.io.deq.bits.data, _T_57) connect Queue10_UInt8_17.io.enq.bits, _T_58 node _T_59 = eq(UInt<5>(0h12), idx) when _T_59 : node _T_60 = shl(UInt<1>(0h0), 3) node _T_61 = dshr(incoming_writes_Q.io.deq.bits.data, _T_60) connect Queue10_UInt8_18.io.enq.bits, _T_61 node _T_62 = eq(UInt<5>(0h13), idx) when _T_62 : node _T_63 = shl(UInt<1>(0h0), 3) node _T_64 = dshr(incoming_writes_Q.io.deq.bits.data, _T_63) connect Queue10_UInt8_19.io.enq.bits, _T_64 node _T_65 = eq(UInt<5>(0h14), idx) when _T_65 : node _T_66 = shl(UInt<1>(0h0), 3) node _T_67 = dshr(incoming_writes_Q.io.deq.bits.data, _T_66) connect Queue10_UInt8_20.io.enq.bits, _T_67 node _T_68 = eq(UInt<5>(0h15), idx) when _T_68 : node _T_69 = shl(UInt<1>(0h0), 3) node _T_70 = dshr(incoming_writes_Q.io.deq.bits.data, _T_69) connect Queue10_UInt8_21.io.enq.bits, _T_70 node _T_71 = eq(UInt<5>(0h16), idx) when _T_71 : node _T_72 = shl(UInt<1>(0h0), 3) node _T_73 = dshr(incoming_writes_Q.io.deq.bits.data, _T_72) connect Queue10_UInt8_22.io.enq.bits, _T_73 node _T_74 = eq(UInt<5>(0h17), idx) when _T_74 : node _T_75 = shl(UInt<1>(0h0), 3) node _T_76 = dshr(incoming_writes_Q.io.deq.bits.data, _T_75) connect Queue10_UInt8_23.io.enq.bits, _T_76 node _T_77 = eq(UInt<5>(0h18), idx) when _T_77 : node _T_78 = shl(UInt<1>(0h0), 3) node _T_79 = dshr(incoming_writes_Q.io.deq.bits.data, _T_78) connect Queue10_UInt8_24.io.enq.bits, _T_79 node _T_80 = eq(UInt<5>(0h19), idx) when _T_80 : node _T_81 = shl(UInt<1>(0h0), 3) node _T_82 = dshr(incoming_writes_Q.io.deq.bits.data, _T_81) connect Queue10_UInt8_25.io.enq.bits, _T_82 node _T_83 = eq(UInt<5>(0h1a), idx) when _T_83 : node _T_84 = shl(UInt<1>(0h0), 3) node _T_85 = dshr(incoming_writes_Q.io.deq.bits.data, _T_84) connect Queue10_UInt8_26.io.enq.bits, _T_85 node _T_86 = eq(UInt<5>(0h1b), idx) when _T_86 : node _T_87 = shl(UInt<1>(0h0), 3) node _T_88 = dshr(incoming_writes_Q.io.deq.bits.data, _T_87) connect Queue10_UInt8_27.io.enq.bits, _T_88 node _T_89 = eq(UInt<5>(0h1c), idx) when _T_89 : node _T_90 = shl(UInt<1>(0h0), 3) node _T_91 = dshr(incoming_writes_Q.io.deq.bits.data, _T_90) connect Queue10_UInt8_28.io.enq.bits, _T_91 node _T_92 = eq(UInt<5>(0h1d), idx) when _T_92 : node _T_93 = shl(UInt<1>(0h0), 3) node _T_94 = dshr(incoming_writes_Q.io.deq.bits.data, _T_93) connect Queue10_UInt8_29.io.enq.bits, _T_94 node _T_95 = eq(UInt<5>(0h1e), idx) when _T_95 : node _T_96 = shl(UInt<1>(0h0), 3) node _T_97 = dshr(incoming_writes_Q.io.deq.bits.data, _T_96) connect Queue10_UInt8_30.io.enq.bits, _T_97 node _T_98 = eq(UInt<5>(0h1f), idx) when _T_98 : node _T_99 = shl(UInt<1>(0h0), 3) node _T_100 = dshr(incoming_writes_Q.io.deq.bits.data, _T_99) connect Queue10_UInt8_31.io.enq.bits, _T_100 node _idx_T_1 = add(write_start_index, UInt<1>(0h1)) node idx_1 = rem(_idx_T_1, UInt<6>(0h20)) node _T_101 = eq(UInt<1>(0h0), idx_1) when _T_101 : node _T_102 = shl(UInt<1>(0h1), 3) node _T_103 = dshr(incoming_writes_Q.io.deq.bits.data, _T_102) connect Queue10_UInt8.io.enq.bits, _T_103 node _T_104 = eq(UInt<1>(0h1), idx_1) when _T_104 : node _T_105 = shl(UInt<1>(0h1), 3) node _T_106 = dshr(incoming_writes_Q.io.deq.bits.data, _T_105) connect Queue10_UInt8_1.io.enq.bits, _T_106 node _T_107 = eq(UInt<2>(0h2), idx_1) when _T_107 : node _T_108 = shl(UInt<1>(0h1), 3) node _T_109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_108) connect Queue10_UInt8_2.io.enq.bits, _T_109 node _T_110 = eq(UInt<2>(0h3), idx_1) when _T_110 : node _T_111 = shl(UInt<1>(0h1), 3) node _T_112 = dshr(incoming_writes_Q.io.deq.bits.data, _T_111) connect Queue10_UInt8_3.io.enq.bits, _T_112 node _T_113 = eq(UInt<3>(0h4), idx_1) when _T_113 : node _T_114 = shl(UInt<1>(0h1), 3) node _T_115 = dshr(incoming_writes_Q.io.deq.bits.data, _T_114) connect Queue10_UInt8_4.io.enq.bits, _T_115 node _T_116 = eq(UInt<3>(0h5), idx_1) when _T_116 : node _T_117 = shl(UInt<1>(0h1), 3) node _T_118 = dshr(incoming_writes_Q.io.deq.bits.data, _T_117) connect Queue10_UInt8_5.io.enq.bits, _T_118 node _T_119 = eq(UInt<3>(0h6), idx_1) when _T_119 : node _T_120 = shl(UInt<1>(0h1), 3) node _T_121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_120) connect Queue10_UInt8_6.io.enq.bits, _T_121 node _T_122 = eq(UInt<3>(0h7), idx_1) when _T_122 : node _T_123 = shl(UInt<1>(0h1), 3) node _T_124 = dshr(incoming_writes_Q.io.deq.bits.data, _T_123) connect Queue10_UInt8_7.io.enq.bits, _T_124 node _T_125 = eq(UInt<4>(0h8), idx_1) when _T_125 : node _T_126 = shl(UInt<1>(0h1), 3) node _T_127 = dshr(incoming_writes_Q.io.deq.bits.data, _T_126) connect Queue10_UInt8_8.io.enq.bits, _T_127 node _T_128 = eq(UInt<4>(0h9), idx_1) when _T_128 : node _T_129 = shl(UInt<1>(0h1), 3) node _T_130 = dshr(incoming_writes_Q.io.deq.bits.data, _T_129) connect Queue10_UInt8_9.io.enq.bits, _T_130 node _T_131 = eq(UInt<4>(0ha), idx_1) when _T_131 : node _T_132 = shl(UInt<1>(0h1), 3) node _T_133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_132) connect Queue10_UInt8_10.io.enq.bits, _T_133 node _T_134 = eq(UInt<4>(0hb), idx_1) when _T_134 : node _T_135 = shl(UInt<1>(0h1), 3) node _T_136 = dshr(incoming_writes_Q.io.deq.bits.data, _T_135) connect Queue10_UInt8_11.io.enq.bits, _T_136 node _T_137 = eq(UInt<4>(0hc), idx_1) when _T_137 : node _T_138 = shl(UInt<1>(0h1), 3) node _T_139 = dshr(incoming_writes_Q.io.deq.bits.data, _T_138) connect Queue10_UInt8_12.io.enq.bits, _T_139 node _T_140 = eq(UInt<4>(0hd), idx_1) when _T_140 : node _T_141 = shl(UInt<1>(0h1), 3) node _T_142 = dshr(incoming_writes_Q.io.deq.bits.data, _T_141) connect Queue10_UInt8_13.io.enq.bits, _T_142 node _T_143 = eq(UInt<4>(0he), idx_1) when _T_143 : node _T_144 = shl(UInt<1>(0h1), 3) node _T_145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_144) connect Queue10_UInt8_14.io.enq.bits, _T_145 node _T_146 = eq(UInt<4>(0hf), idx_1) when _T_146 : node _T_147 = shl(UInt<1>(0h1), 3) node _T_148 = dshr(incoming_writes_Q.io.deq.bits.data, _T_147) connect Queue10_UInt8_15.io.enq.bits, _T_148 node _T_149 = eq(UInt<5>(0h10), idx_1) when _T_149 : node _T_150 = shl(UInt<1>(0h1), 3) node _T_151 = dshr(incoming_writes_Q.io.deq.bits.data, _T_150) connect Queue10_UInt8_16.io.enq.bits, _T_151 node _T_152 = eq(UInt<5>(0h11), idx_1) when _T_152 : node _T_153 = shl(UInt<1>(0h1), 3) node _T_154 = dshr(incoming_writes_Q.io.deq.bits.data, _T_153) connect Queue10_UInt8_17.io.enq.bits, _T_154 node _T_155 = eq(UInt<5>(0h12), idx_1) when _T_155 : node _T_156 = shl(UInt<1>(0h1), 3) node _T_157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_156) connect Queue10_UInt8_18.io.enq.bits, _T_157 node _T_158 = eq(UInt<5>(0h13), idx_1) when _T_158 : node _T_159 = shl(UInt<1>(0h1), 3) node _T_160 = dshr(incoming_writes_Q.io.deq.bits.data, _T_159) connect Queue10_UInt8_19.io.enq.bits, _T_160 node _T_161 = eq(UInt<5>(0h14), idx_1) when _T_161 : node _T_162 = shl(UInt<1>(0h1), 3) node _T_163 = dshr(incoming_writes_Q.io.deq.bits.data, _T_162) connect Queue10_UInt8_20.io.enq.bits, _T_163 node _T_164 = eq(UInt<5>(0h15), idx_1) when _T_164 : node _T_165 = shl(UInt<1>(0h1), 3) node _T_166 = dshr(incoming_writes_Q.io.deq.bits.data, _T_165) connect Queue10_UInt8_21.io.enq.bits, _T_166 node _T_167 = eq(UInt<5>(0h16), idx_1) when _T_167 : node _T_168 = shl(UInt<1>(0h1), 3) node _T_169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_168) connect Queue10_UInt8_22.io.enq.bits, _T_169 node _T_170 = eq(UInt<5>(0h17), idx_1) when _T_170 : node _T_171 = shl(UInt<1>(0h1), 3) node _T_172 = dshr(incoming_writes_Q.io.deq.bits.data, _T_171) connect Queue10_UInt8_23.io.enq.bits, _T_172 node _T_173 = eq(UInt<5>(0h18), idx_1) when _T_173 : node _T_174 = shl(UInt<1>(0h1), 3) node _T_175 = dshr(incoming_writes_Q.io.deq.bits.data, _T_174) connect Queue10_UInt8_24.io.enq.bits, _T_175 node _T_176 = eq(UInt<5>(0h19), idx_1) when _T_176 : node _T_177 = shl(UInt<1>(0h1), 3) node _T_178 = dshr(incoming_writes_Q.io.deq.bits.data, _T_177) connect Queue10_UInt8_25.io.enq.bits, _T_178 node _T_179 = eq(UInt<5>(0h1a), idx_1) when _T_179 : node _T_180 = shl(UInt<1>(0h1), 3) node _T_181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_180) connect Queue10_UInt8_26.io.enq.bits, _T_181 node _T_182 = eq(UInt<5>(0h1b), idx_1) when _T_182 : node _T_183 = shl(UInt<1>(0h1), 3) node _T_184 = dshr(incoming_writes_Q.io.deq.bits.data, _T_183) connect Queue10_UInt8_27.io.enq.bits, _T_184 node _T_185 = eq(UInt<5>(0h1c), idx_1) when _T_185 : node _T_186 = shl(UInt<1>(0h1), 3) node _T_187 = dshr(incoming_writes_Q.io.deq.bits.data, _T_186) connect Queue10_UInt8_28.io.enq.bits, _T_187 node _T_188 = eq(UInt<5>(0h1d), idx_1) when _T_188 : node _T_189 = shl(UInt<1>(0h1), 3) node _T_190 = dshr(incoming_writes_Q.io.deq.bits.data, _T_189) connect Queue10_UInt8_29.io.enq.bits, _T_190 node _T_191 = eq(UInt<5>(0h1e), idx_1) when _T_191 : node _T_192 = shl(UInt<1>(0h1), 3) node _T_193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_192) connect Queue10_UInt8_30.io.enq.bits, _T_193 node _T_194 = eq(UInt<5>(0h1f), idx_1) when _T_194 : node _T_195 = shl(UInt<1>(0h1), 3) node _T_196 = dshr(incoming_writes_Q.io.deq.bits.data, _T_195) connect Queue10_UInt8_31.io.enq.bits, _T_196 node _idx_T_2 = add(write_start_index, UInt<2>(0h2)) node idx_2 = rem(_idx_T_2, UInt<6>(0h20)) node _T_197 = eq(UInt<1>(0h0), idx_2) when _T_197 : node _T_198 = shl(UInt<2>(0h2), 3) node _T_199 = dshr(incoming_writes_Q.io.deq.bits.data, _T_198) connect Queue10_UInt8.io.enq.bits, _T_199 node _T_200 = eq(UInt<1>(0h1), idx_2) when _T_200 : node _T_201 = shl(UInt<2>(0h2), 3) node _T_202 = dshr(incoming_writes_Q.io.deq.bits.data, _T_201) connect Queue10_UInt8_1.io.enq.bits, _T_202 node _T_203 = eq(UInt<2>(0h2), idx_2) when _T_203 : node _T_204 = shl(UInt<2>(0h2), 3) node _T_205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_204) connect Queue10_UInt8_2.io.enq.bits, _T_205 node _T_206 = eq(UInt<2>(0h3), idx_2) when _T_206 : node _T_207 = shl(UInt<2>(0h2), 3) node _T_208 = dshr(incoming_writes_Q.io.deq.bits.data, _T_207) connect Queue10_UInt8_3.io.enq.bits, _T_208 node _T_209 = eq(UInt<3>(0h4), idx_2) when _T_209 : node _T_210 = shl(UInt<2>(0h2), 3) node _T_211 = dshr(incoming_writes_Q.io.deq.bits.data, _T_210) connect Queue10_UInt8_4.io.enq.bits, _T_211 node _T_212 = eq(UInt<3>(0h5), idx_2) when _T_212 : node _T_213 = shl(UInt<2>(0h2), 3) node _T_214 = dshr(incoming_writes_Q.io.deq.bits.data, _T_213) connect Queue10_UInt8_5.io.enq.bits, _T_214 node _T_215 = eq(UInt<3>(0h6), idx_2) when _T_215 : node _T_216 = shl(UInt<2>(0h2), 3) node _T_217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_216) connect Queue10_UInt8_6.io.enq.bits, _T_217 node _T_218 = eq(UInt<3>(0h7), idx_2) when _T_218 : node _T_219 = shl(UInt<2>(0h2), 3) node _T_220 = dshr(incoming_writes_Q.io.deq.bits.data, _T_219) connect Queue10_UInt8_7.io.enq.bits, _T_220 node _T_221 = eq(UInt<4>(0h8), idx_2) when _T_221 : node _T_222 = shl(UInt<2>(0h2), 3) node _T_223 = dshr(incoming_writes_Q.io.deq.bits.data, _T_222) connect Queue10_UInt8_8.io.enq.bits, _T_223 node _T_224 = eq(UInt<4>(0h9), idx_2) when _T_224 : node _T_225 = shl(UInt<2>(0h2), 3) node _T_226 = dshr(incoming_writes_Q.io.deq.bits.data, _T_225) connect Queue10_UInt8_9.io.enq.bits, _T_226 node _T_227 = eq(UInt<4>(0ha), idx_2) when _T_227 : node _T_228 = shl(UInt<2>(0h2), 3) node _T_229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_228) connect Queue10_UInt8_10.io.enq.bits, _T_229 node _T_230 = eq(UInt<4>(0hb), idx_2) when _T_230 : node _T_231 = shl(UInt<2>(0h2), 3) node _T_232 = dshr(incoming_writes_Q.io.deq.bits.data, _T_231) connect Queue10_UInt8_11.io.enq.bits, _T_232 node _T_233 = eq(UInt<4>(0hc), idx_2) when _T_233 : node _T_234 = shl(UInt<2>(0h2), 3) node _T_235 = dshr(incoming_writes_Q.io.deq.bits.data, _T_234) connect Queue10_UInt8_12.io.enq.bits, _T_235 node _T_236 = eq(UInt<4>(0hd), idx_2) when _T_236 : node _T_237 = shl(UInt<2>(0h2), 3) node _T_238 = dshr(incoming_writes_Q.io.deq.bits.data, _T_237) connect Queue10_UInt8_13.io.enq.bits, _T_238 node _T_239 = eq(UInt<4>(0he), idx_2) when _T_239 : node _T_240 = shl(UInt<2>(0h2), 3) node _T_241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_240) connect Queue10_UInt8_14.io.enq.bits, _T_241 node _T_242 = eq(UInt<4>(0hf), idx_2) when _T_242 : node _T_243 = shl(UInt<2>(0h2), 3) node _T_244 = dshr(incoming_writes_Q.io.deq.bits.data, _T_243) connect Queue10_UInt8_15.io.enq.bits, _T_244 node _T_245 = eq(UInt<5>(0h10), idx_2) when _T_245 : node _T_246 = shl(UInt<2>(0h2), 3) node _T_247 = dshr(incoming_writes_Q.io.deq.bits.data, _T_246) connect Queue10_UInt8_16.io.enq.bits, _T_247 node _T_248 = eq(UInt<5>(0h11), idx_2) when _T_248 : node _T_249 = shl(UInt<2>(0h2), 3) node _T_250 = dshr(incoming_writes_Q.io.deq.bits.data, _T_249) connect Queue10_UInt8_17.io.enq.bits, _T_250 node _T_251 = eq(UInt<5>(0h12), idx_2) when _T_251 : node _T_252 = shl(UInt<2>(0h2), 3) node _T_253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_252) connect Queue10_UInt8_18.io.enq.bits, _T_253 node _T_254 = eq(UInt<5>(0h13), idx_2) when _T_254 : node _T_255 = shl(UInt<2>(0h2), 3) node _T_256 = dshr(incoming_writes_Q.io.deq.bits.data, _T_255) connect Queue10_UInt8_19.io.enq.bits, _T_256 node _T_257 = eq(UInt<5>(0h14), idx_2) when _T_257 : node _T_258 = shl(UInt<2>(0h2), 3) node _T_259 = dshr(incoming_writes_Q.io.deq.bits.data, _T_258) connect Queue10_UInt8_20.io.enq.bits, _T_259 node _T_260 = eq(UInt<5>(0h15), idx_2) when _T_260 : node _T_261 = shl(UInt<2>(0h2), 3) node _T_262 = dshr(incoming_writes_Q.io.deq.bits.data, _T_261) connect Queue10_UInt8_21.io.enq.bits, _T_262 node _T_263 = eq(UInt<5>(0h16), idx_2) when _T_263 : node _T_264 = shl(UInt<2>(0h2), 3) node _T_265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_264) connect Queue10_UInt8_22.io.enq.bits, _T_265 node _T_266 = eq(UInt<5>(0h17), idx_2) when _T_266 : node _T_267 = shl(UInt<2>(0h2), 3) node _T_268 = dshr(incoming_writes_Q.io.deq.bits.data, _T_267) connect Queue10_UInt8_23.io.enq.bits, _T_268 node _T_269 = eq(UInt<5>(0h18), idx_2) when _T_269 : node _T_270 = shl(UInt<2>(0h2), 3) node _T_271 = dshr(incoming_writes_Q.io.deq.bits.data, _T_270) connect Queue10_UInt8_24.io.enq.bits, _T_271 node _T_272 = eq(UInt<5>(0h19), idx_2) when _T_272 : node _T_273 = shl(UInt<2>(0h2), 3) node _T_274 = dshr(incoming_writes_Q.io.deq.bits.data, _T_273) connect Queue10_UInt8_25.io.enq.bits, _T_274 node _T_275 = eq(UInt<5>(0h1a), idx_2) when _T_275 : node _T_276 = shl(UInt<2>(0h2), 3) node _T_277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_276) connect Queue10_UInt8_26.io.enq.bits, _T_277 node _T_278 = eq(UInt<5>(0h1b), idx_2) when _T_278 : node _T_279 = shl(UInt<2>(0h2), 3) node _T_280 = dshr(incoming_writes_Q.io.deq.bits.data, _T_279) connect Queue10_UInt8_27.io.enq.bits, _T_280 node _T_281 = eq(UInt<5>(0h1c), idx_2) when _T_281 : node _T_282 = shl(UInt<2>(0h2), 3) node _T_283 = dshr(incoming_writes_Q.io.deq.bits.data, _T_282) connect Queue10_UInt8_28.io.enq.bits, _T_283 node _T_284 = eq(UInt<5>(0h1d), idx_2) when _T_284 : node _T_285 = shl(UInt<2>(0h2), 3) node _T_286 = dshr(incoming_writes_Q.io.deq.bits.data, _T_285) connect Queue10_UInt8_29.io.enq.bits, _T_286 node _T_287 = eq(UInt<5>(0h1e), idx_2) when _T_287 : node _T_288 = shl(UInt<2>(0h2), 3) node _T_289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_288) connect Queue10_UInt8_30.io.enq.bits, _T_289 node _T_290 = eq(UInt<5>(0h1f), idx_2) when _T_290 : node _T_291 = shl(UInt<2>(0h2), 3) node _T_292 = dshr(incoming_writes_Q.io.deq.bits.data, _T_291) connect Queue10_UInt8_31.io.enq.bits, _T_292 node _idx_T_3 = add(write_start_index, UInt<2>(0h3)) node idx_3 = rem(_idx_T_3, UInt<6>(0h20)) node _T_293 = eq(UInt<1>(0h0), idx_3) when _T_293 : node _T_294 = shl(UInt<2>(0h3), 3) node _T_295 = dshr(incoming_writes_Q.io.deq.bits.data, _T_294) connect Queue10_UInt8.io.enq.bits, _T_295 node _T_296 = eq(UInt<1>(0h1), idx_3) when _T_296 : node _T_297 = shl(UInt<2>(0h3), 3) node _T_298 = dshr(incoming_writes_Q.io.deq.bits.data, _T_297) connect Queue10_UInt8_1.io.enq.bits, _T_298 node _T_299 = eq(UInt<2>(0h2), idx_3) when _T_299 : node _T_300 = shl(UInt<2>(0h3), 3) node _T_301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_300) connect Queue10_UInt8_2.io.enq.bits, _T_301 node _T_302 = eq(UInt<2>(0h3), idx_3) when _T_302 : node _T_303 = shl(UInt<2>(0h3), 3) node _T_304 = dshr(incoming_writes_Q.io.deq.bits.data, _T_303) connect Queue10_UInt8_3.io.enq.bits, _T_304 node _T_305 = eq(UInt<3>(0h4), idx_3) when _T_305 : node _T_306 = shl(UInt<2>(0h3), 3) node _T_307 = dshr(incoming_writes_Q.io.deq.bits.data, _T_306) connect Queue10_UInt8_4.io.enq.bits, _T_307 node _T_308 = eq(UInt<3>(0h5), idx_3) when _T_308 : node _T_309 = shl(UInt<2>(0h3), 3) node _T_310 = dshr(incoming_writes_Q.io.deq.bits.data, _T_309) connect Queue10_UInt8_5.io.enq.bits, _T_310 node _T_311 = eq(UInt<3>(0h6), idx_3) when _T_311 : node _T_312 = shl(UInt<2>(0h3), 3) node _T_313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_312) connect Queue10_UInt8_6.io.enq.bits, _T_313 node _T_314 = eq(UInt<3>(0h7), idx_3) when _T_314 : node _T_315 = shl(UInt<2>(0h3), 3) node _T_316 = dshr(incoming_writes_Q.io.deq.bits.data, _T_315) connect Queue10_UInt8_7.io.enq.bits, _T_316 node _T_317 = eq(UInt<4>(0h8), idx_3) when _T_317 : node _T_318 = shl(UInt<2>(0h3), 3) node _T_319 = dshr(incoming_writes_Q.io.deq.bits.data, _T_318) connect Queue10_UInt8_8.io.enq.bits, _T_319 node _T_320 = eq(UInt<4>(0h9), idx_3) when _T_320 : node _T_321 = shl(UInt<2>(0h3), 3) node _T_322 = dshr(incoming_writes_Q.io.deq.bits.data, _T_321) connect Queue10_UInt8_9.io.enq.bits, _T_322 node _T_323 = eq(UInt<4>(0ha), idx_3) when _T_323 : node _T_324 = shl(UInt<2>(0h3), 3) node _T_325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_324) connect Queue10_UInt8_10.io.enq.bits, _T_325 node _T_326 = eq(UInt<4>(0hb), idx_3) when _T_326 : node _T_327 = shl(UInt<2>(0h3), 3) node _T_328 = dshr(incoming_writes_Q.io.deq.bits.data, _T_327) connect Queue10_UInt8_11.io.enq.bits, _T_328 node _T_329 = eq(UInt<4>(0hc), idx_3) when _T_329 : node _T_330 = shl(UInt<2>(0h3), 3) node _T_331 = dshr(incoming_writes_Q.io.deq.bits.data, _T_330) connect Queue10_UInt8_12.io.enq.bits, _T_331 node _T_332 = eq(UInt<4>(0hd), idx_3) when _T_332 : node _T_333 = shl(UInt<2>(0h3), 3) node _T_334 = dshr(incoming_writes_Q.io.deq.bits.data, _T_333) connect Queue10_UInt8_13.io.enq.bits, _T_334 node _T_335 = eq(UInt<4>(0he), idx_3) when _T_335 : node _T_336 = shl(UInt<2>(0h3), 3) node _T_337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_336) connect Queue10_UInt8_14.io.enq.bits, _T_337 node _T_338 = eq(UInt<4>(0hf), idx_3) when _T_338 : node _T_339 = shl(UInt<2>(0h3), 3) node _T_340 = dshr(incoming_writes_Q.io.deq.bits.data, _T_339) connect Queue10_UInt8_15.io.enq.bits, _T_340 node _T_341 = eq(UInt<5>(0h10), idx_3) when _T_341 : node _T_342 = shl(UInt<2>(0h3), 3) node _T_343 = dshr(incoming_writes_Q.io.deq.bits.data, _T_342) connect Queue10_UInt8_16.io.enq.bits, _T_343 node _T_344 = eq(UInt<5>(0h11), idx_3) when _T_344 : node _T_345 = shl(UInt<2>(0h3), 3) node _T_346 = dshr(incoming_writes_Q.io.deq.bits.data, _T_345) connect Queue10_UInt8_17.io.enq.bits, _T_346 node _T_347 = eq(UInt<5>(0h12), idx_3) when _T_347 : node _T_348 = shl(UInt<2>(0h3), 3) node _T_349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_348) connect Queue10_UInt8_18.io.enq.bits, _T_349 node _T_350 = eq(UInt<5>(0h13), idx_3) when _T_350 : node _T_351 = shl(UInt<2>(0h3), 3) node _T_352 = dshr(incoming_writes_Q.io.deq.bits.data, _T_351) connect Queue10_UInt8_19.io.enq.bits, _T_352 node _T_353 = eq(UInt<5>(0h14), idx_3) when _T_353 : node _T_354 = shl(UInt<2>(0h3), 3) node _T_355 = dshr(incoming_writes_Q.io.deq.bits.data, _T_354) connect Queue10_UInt8_20.io.enq.bits, _T_355 node _T_356 = eq(UInt<5>(0h15), idx_3) when _T_356 : node _T_357 = shl(UInt<2>(0h3), 3) node _T_358 = dshr(incoming_writes_Q.io.deq.bits.data, _T_357) connect Queue10_UInt8_21.io.enq.bits, _T_358 node _T_359 = eq(UInt<5>(0h16), idx_3) when _T_359 : node _T_360 = shl(UInt<2>(0h3), 3) node _T_361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_360) connect Queue10_UInt8_22.io.enq.bits, _T_361 node _T_362 = eq(UInt<5>(0h17), idx_3) when _T_362 : node _T_363 = shl(UInt<2>(0h3), 3) node _T_364 = dshr(incoming_writes_Q.io.deq.bits.data, _T_363) connect Queue10_UInt8_23.io.enq.bits, _T_364 node _T_365 = eq(UInt<5>(0h18), idx_3) when _T_365 : node _T_366 = shl(UInt<2>(0h3), 3) node _T_367 = dshr(incoming_writes_Q.io.deq.bits.data, _T_366) connect Queue10_UInt8_24.io.enq.bits, _T_367 node _T_368 = eq(UInt<5>(0h19), idx_3) when _T_368 : node _T_369 = shl(UInt<2>(0h3), 3) node _T_370 = dshr(incoming_writes_Q.io.deq.bits.data, _T_369) connect Queue10_UInt8_25.io.enq.bits, _T_370 node _T_371 = eq(UInt<5>(0h1a), idx_3) when _T_371 : node _T_372 = shl(UInt<2>(0h3), 3) node _T_373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_372) connect Queue10_UInt8_26.io.enq.bits, _T_373 node _T_374 = eq(UInt<5>(0h1b), idx_3) when _T_374 : node _T_375 = shl(UInt<2>(0h3), 3) node _T_376 = dshr(incoming_writes_Q.io.deq.bits.data, _T_375) connect Queue10_UInt8_27.io.enq.bits, _T_376 node _T_377 = eq(UInt<5>(0h1c), idx_3) when _T_377 : node _T_378 = shl(UInt<2>(0h3), 3) node _T_379 = dshr(incoming_writes_Q.io.deq.bits.data, _T_378) connect Queue10_UInt8_28.io.enq.bits, _T_379 node _T_380 = eq(UInt<5>(0h1d), idx_3) when _T_380 : node _T_381 = shl(UInt<2>(0h3), 3) node _T_382 = dshr(incoming_writes_Q.io.deq.bits.data, _T_381) connect Queue10_UInt8_29.io.enq.bits, _T_382 node _T_383 = eq(UInt<5>(0h1e), idx_3) when _T_383 : node _T_384 = shl(UInt<2>(0h3), 3) node _T_385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_384) connect Queue10_UInt8_30.io.enq.bits, _T_385 node _T_386 = eq(UInt<5>(0h1f), idx_3) when _T_386 : node _T_387 = shl(UInt<2>(0h3), 3) node _T_388 = dshr(incoming_writes_Q.io.deq.bits.data, _T_387) connect Queue10_UInt8_31.io.enq.bits, _T_388 node _idx_T_4 = add(write_start_index, UInt<3>(0h4)) node idx_4 = rem(_idx_T_4, UInt<6>(0h20)) node _T_389 = eq(UInt<1>(0h0), idx_4) when _T_389 : node _T_390 = shl(UInt<3>(0h4), 3) node _T_391 = dshr(incoming_writes_Q.io.deq.bits.data, _T_390) connect Queue10_UInt8.io.enq.bits, _T_391 node _T_392 = eq(UInt<1>(0h1), idx_4) when _T_392 : node _T_393 = shl(UInt<3>(0h4), 3) node _T_394 = dshr(incoming_writes_Q.io.deq.bits.data, _T_393) connect Queue10_UInt8_1.io.enq.bits, _T_394 node _T_395 = eq(UInt<2>(0h2), idx_4) when _T_395 : node _T_396 = shl(UInt<3>(0h4), 3) node _T_397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_396) connect Queue10_UInt8_2.io.enq.bits, _T_397 node _T_398 = eq(UInt<2>(0h3), idx_4) when _T_398 : node _T_399 = shl(UInt<3>(0h4), 3) node _T_400 = dshr(incoming_writes_Q.io.deq.bits.data, _T_399) connect Queue10_UInt8_3.io.enq.bits, _T_400 node _T_401 = eq(UInt<3>(0h4), idx_4) when _T_401 : node _T_402 = shl(UInt<3>(0h4), 3) node _T_403 = dshr(incoming_writes_Q.io.deq.bits.data, _T_402) connect Queue10_UInt8_4.io.enq.bits, _T_403 node _T_404 = eq(UInt<3>(0h5), idx_4) when _T_404 : node _T_405 = shl(UInt<3>(0h4), 3) node _T_406 = dshr(incoming_writes_Q.io.deq.bits.data, _T_405) connect Queue10_UInt8_5.io.enq.bits, _T_406 node _T_407 = eq(UInt<3>(0h6), idx_4) when _T_407 : node _T_408 = shl(UInt<3>(0h4), 3) node _T_409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_408) connect Queue10_UInt8_6.io.enq.bits, _T_409 node _T_410 = eq(UInt<3>(0h7), idx_4) when _T_410 : node _T_411 = shl(UInt<3>(0h4), 3) node _T_412 = dshr(incoming_writes_Q.io.deq.bits.data, _T_411) connect Queue10_UInt8_7.io.enq.bits, _T_412 node _T_413 = eq(UInt<4>(0h8), idx_4) when _T_413 : node _T_414 = shl(UInt<3>(0h4), 3) node _T_415 = dshr(incoming_writes_Q.io.deq.bits.data, _T_414) connect Queue10_UInt8_8.io.enq.bits, _T_415 node _T_416 = eq(UInt<4>(0h9), idx_4) when _T_416 : node _T_417 = shl(UInt<3>(0h4), 3) node _T_418 = dshr(incoming_writes_Q.io.deq.bits.data, _T_417) connect Queue10_UInt8_9.io.enq.bits, _T_418 node _T_419 = eq(UInt<4>(0ha), idx_4) when _T_419 : node _T_420 = shl(UInt<3>(0h4), 3) node _T_421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_420) connect Queue10_UInt8_10.io.enq.bits, _T_421 node _T_422 = eq(UInt<4>(0hb), idx_4) when _T_422 : node _T_423 = shl(UInt<3>(0h4), 3) node _T_424 = dshr(incoming_writes_Q.io.deq.bits.data, _T_423) connect Queue10_UInt8_11.io.enq.bits, _T_424 node _T_425 = eq(UInt<4>(0hc), idx_4) when _T_425 : node _T_426 = shl(UInt<3>(0h4), 3) node _T_427 = dshr(incoming_writes_Q.io.deq.bits.data, _T_426) connect Queue10_UInt8_12.io.enq.bits, _T_427 node _T_428 = eq(UInt<4>(0hd), idx_4) when _T_428 : node _T_429 = shl(UInt<3>(0h4), 3) node _T_430 = dshr(incoming_writes_Q.io.deq.bits.data, _T_429) connect Queue10_UInt8_13.io.enq.bits, _T_430 node _T_431 = eq(UInt<4>(0he), idx_4) when _T_431 : node _T_432 = shl(UInt<3>(0h4), 3) node _T_433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_432) connect Queue10_UInt8_14.io.enq.bits, _T_433 node _T_434 = eq(UInt<4>(0hf), idx_4) when _T_434 : node _T_435 = shl(UInt<3>(0h4), 3) node _T_436 = dshr(incoming_writes_Q.io.deq.bits.data, _T_435) connect Queue10_UInt8_15.io.enq.bits, _T_436 node _T_437 = eq(UInt<5>(0h10), idx_4) when _T_437 : node _T_438 = shl(UInt<3>(0h4), 3) node _T_439 = dshr(incoming_writes_Q.io.deq.bits.data, _T_438) connect Queue10_UInt8_16.io.enq.bits, _T_439 node _T_440 = eq(UInt<5>(0h11), idx_4) when _T_440 : node _T_441 = shl(UInt<3>(0h4), 3) node _T_442 = dshr(incoming_writes_Q.io.deq.bits.data, _T_441) connect Queue10_UInt8_17.io.enq.bits, _T_442 node _T_443 = eq(UInt<5>(0h12), idx_4) when _T_443 : node _T_444 = shl(UInt<3>(0h4), 3) node _T_445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_444) connect Queue10_UInt8_18.io.enq.bits, _T_445 node _T_446 = eq(UInt<5>(0h13), idx_4) when _T_446 : node _T_447 = shl(UInt<3>(0h4), 3) node _T_448 = dshr(incoming_writes_Q.io.deq.bits.data, _T_447) connect Queue10_UInt8_19.io.enq.bits, _T_448 node _T_449 = eq(UInt<5>(0h14), idx_4) when _T_449 : node _T_450 = shl(UInt<3>(0h4), 3) node _T_451 = dshr(incoming_writes_Q.io.deq.bits.data, _T_450) connect Queue10_UInt8_20.io.enq.bits, _T_451 node _T_452 = eq(UInt<5>(0h15), idx_4) when _T_452 : node _T_453 = shl(UInt<3>(0h4), 3) node _T_454 = dshr(incoming_writes_Q.io.deq.bits.data, _T_453) connect Queue10_UInt8_21.io.enq.bits, _T_454 node _T_455 = eq(UInt<5>(0h16), idx_4) when _T_455 : node _T_456 = shl(UInt<3>(0h4), 3) node _T_457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_456) connect Queue10_UInt8_22.io.enq.bits, _T_457 node _T_458 = eq(UInt<5>(0h17), idx_4) when _T_458 : node _T_459 = shl(UInt<3>(0h4), 3) node _T_460 = dshr(incoming_writes_Q.io.deq.bits.data, _T_459) connect Queue10_UInt8_23.io.enq.bits, _T_460 node _T_461 = eq(UInt<5>(0h18), idx_4) when _T_461 : node _T_462 = shl(UInt<3>(0h4), 3) node _T_463 = dshr(incoming_writes_Q.io.deq.bits.data, _T_462) connect Queue10_UInt8_24.io.enq.bits, _T_463 node _T_464 = eq(UInt<5>(0h19), idx_4) when _T_464 : node _T_465 = shl(UInt<3>(0h4), 3) node _T_466 = dshr(incoming_writes_Q.io.deq.bits.data, _T_465) connect Queue10_UInt8_25.io.enq.bits, _T_466 node _T_467 = eq(UInt<5>(0h1a), idx_4) when _T_467 : node _T_468 = shl(UInt<3>(0h4), 3) node _T_469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_468) connect Queue10_UInt8_26.io.enq.bits, _T_469 node _T_470 = eq(UInt<5>(0h1b), idx_4) when _T_470 : node _T_471 = shl(UInt<3>(0h4), 3) node _T_472 = dshr(incoming_writes_Q.io.deq.bits.data, _T_471) connect Queue10_UInt8_27.io.enq.bits, _T_472 node _T_473 = eq(UInt<5>(0h1c), idx_4) when _T_473 : node _T_474 = shl(UInt<3>(0h4), 3) node _T_475 = dshr(incoming_writes_Q.io.deq.bits.data, _T_474) connect Queue10_UInt8_28.io.enq.bits, _T_475 node _T_476 = eq(UInt<5>(0h1d), idx_4) when _T_476 : node _T_477 = shl(UInt<3>(0h4), 3) node _T_478 = dshr(incoming_writes_Q.io.deq.bits.data, _T_477) connect Queue10_UInt8_29.io.enq.bits, _T_478 node _T_479 = eq(UInt<5>(0h1e), idx_4) when _T_479 : node _T_480 = shl(UInt<3>(0h4), 3) node _T_481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_480) connect Queue10_UInt8_30.io.enq.bits, _T_481 node _T_482 = eq(UInt<5>(0h1f), idx_4) when _T_482 : node _T_483 = shl(UInt<3>(0h4), 3) node _T_484 = dshr(incoming_writes_Q.io.deq.bits.data, _T_483) connect Queue10_UInt8_31.io.enq.bits, _T_484 node _idx_T_5 = add(write_start_index, UInt<3>(0h5)) node idx_5 = rem(_idx_T_5, UInt<6>(0h20)) node _T_485 = eq(UInt<1>(0h0), idx_5) when _T_485 : node _T_486 = shl(UInt<3>(0h5), 3) node _T_487 = dshr(incoming_writes_Q.io.deq.bits.data, _T_486) connect Queue10_UInt8.io.enq.bits, _T_487 node _T_488 = eq(UInt<1>(0h1), idx_5) when _T_488 : node _T_489 = shl(UInt<3>(0h5), 3) node _T_490 = dshr(incoming_writes_Q.io.deq.bits.data, _T_489) connect Queue10_UInt8_1.io.enq.bits, _T_490 node _T_491 = eq(UInt<2>(0h2), idx_5) when _T_491 : node _T_492 = shl(UInt<3>(0h5), 3) node _T_493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_492) connect Queue10_UInt8_2.io.enq.bits, _T_493 node _T_494 = eq(UInt<2>(0h3), idx_5) when _T_494 : node _T_495 = shl(UInt<3>(0h5), 3) node _T_496 = dshr(incoming_writes_Q.io.deq.bits.data, _T_495) connect Queue10_UInt8_3.io.enq.bits, _T_496 node _T_497 = eq(UInt<3>(0h4), idx_5) when _T_497 : node _T_498 = shl(UInt<3>(0h5), 3) node _T_499 = dshr(incoming_writes_Q.io.deq.bits.data, _T_498) connect Queue10_UInt8_4.io.enq.bits, _T_499 node _T_500 = eq(UInt<3>(0h5), idx_5) when _T_500 : node _T_501 = shl(UInt<3>(0h5), 3) node _T_502 = dshr(incoming_writes_Q.io.deq.bits.data, _T_501) connect Queue10_UInt8_5.io.enq.bits, _T_502 node _T_503 = eq(UInt<3>(0h6), idx_5) when _T_503 : node _T_504 = shl(UInt<3>(0h5), 3) node _T_505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_504) connect Queue10_UInt8_6.io.enq.bits, _T_505 node _T_506 = eq(UInt<3>(0h7), idx_5) when _T_506 : node _T_507 = shl(UInt<3>(0h5), 3) node _T_508 = dshr(incoming_writes_Q.io.deq.bits.data, _T_507) connect Queue10_UInt8_7.io.enq.bits, _T_508 node _T_509 = eq(UInt<4>(0h8), idx_5) when _T_509 : node _T_510 = shl(UInt<3>(0h5), 3) node _T_511 = dshr(incoming_writes_Q.io.deq.bits.data, _T_510) connect Queue10_UInt8_8.io.enq.bits, _T_511 node _T_512 = eq(UInt<4>(0h9), idx_5) when _T_512 : node _T_513 = shl(UInt<3>(0h5), 3) node _T_514 = dshr(incoming_writes_Q.io.deq.bits.data, _T_513) connect Queue10_UInt8_9.io.enq.bits, _T_514 node _T_515 = eq(UInt<4>(0ha), idx_5) when _T_515 : node _T_516 = shl(UInt<3>(0h5), 3) node _T_517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_516) connect Queue10_UInt8_10.io.enq.bits, _T_517 node _T_518 = eq(UInt<4>(0hb), idx_5) when _T_518 : node _T_519 = shl(UInt<3>(0h5), 3) node _T_520 = dshr(incoming_writes_Q.io.deq.bits.data, _T_519) connect Queue10_UInt8_11.io.enq.bits, _T_520 node _T_521 = eq(UInt<4>(0hc), idx_5) when _T_521 : node _T_522 = shl(UInt<3>(0h5), 3) node _T_523 = dshr(incoming_writes_Q.io.deq.bits.data, _T_522) connect Queue10_UInt8_12.io.enq.bits, _T_523 node _T_524 = eq(UInt<4>(0hd), idx_5) when _T_524 : node _T_525 = shl(UInt<3>(0h5), 3) node _T_526 = dshr(incoming_writes_Q.io.deq.bits.data, _T_525) connect Queue10_UInt8_13.io.enq.bits, _T_526 node _T_527 = eq(UInt<4>(0he), idx_5) when _T_527 : node _T_528 = shl(UInt<3>(0h5), 3) node _T_529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_528) connect Queue10_UInt8_14.io.enq.bits, _T_529 node _T_530 = eq(UInt<4>(0hf), idx_5) when _T_530 : node _T_531 = shl(UInt<3>(0h5), 3) node _T_532 = dshr(incoming_writes_Q.io.deq.bits.data, _T_531) connect Queue10_UInt8_15.io.enq.bits, _T_532 node _T_533 = eq(UInt<5>(0h10), idx_5) when _T_533 : node _T_534 = shl(UInt<3>(0h5), 3) node _T_535 = dshr(incoming_writes_Q.io.deq.bits.data, _T_534) connect Queue10_UInt8_16.io.enq.bits, _T_535 node _T_536 = eq(UInt<5>(0h11), idx_5) when _T_536 : node _T_537 = shl(UInt<3>(0h5), 3) node _T_538 = dshr(incoming_writes_Q.io.deq.bits.data, _T_537) connect Queue10_UInt8_17.io.enq.bits, _T_538 node _T_539 = eq(UInt<5>(0h12), idx_5) when _T_539 : node _T_540 = shl(UInt<3>(0h5), 3) node _T_541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_540) connect Queue10_UInt8_18.io.enq.bits, _T_541 node _T_542 = eq(UInt<5>(0h13), idx_5) when _T_542 : node _T_543 = shl(UInt<3>(0h5), 3) node _T_544 = dshr(incoming_writes_Q.io.deq.bits.data, _T_543) connect Queue10_UInt8_19.io.enq.bits, _T_544 node _T_545 = eq(UInt<5>(0h14), idx_5) when _T_545 : node _T_546 = shl(UInt<3>(0h5), 3) node _T_547 = dshr(incoming_writes_Q.io.deq.bits.data, _T_546) connect Queue10_UInt8_20.io.enq.bits, _T_547 node _T_548 = eq(UInt<5>(0h15), idx_5) when _T_548 : node _T_549 = shl(UInt<3>(0h5), 3) node _T_550 = dshr(incoming_writes_Q.io.deq.bits.data, _T_549) connect Queue10_UInt8_21.io.enq.bits, _T_550 node _T_551 = eq(UInt<5>(0h16), idx_5) when _T_551 : node _T_552 = shl(UInt<3>(0h5), 3) node _T_553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_552) connect Queue10_UInt8_22.io.enq.bits, _T_553 node _T_554 = eq(UInt<5>(0h17), idx_5) when _T_554 : node _T_555 = shl(UInt<3>(0h5), 3) node _T_556 = dshr(incoming_writes_Q.io.deq.bits.data, _T_555) connect Queue10_UInt8_23.io.enq.bits, _T_556 node _T_557 = eq(UInt<5>(0h18), idx_5) when _T_557 : node _T_558 = shl(UInt<3>(0h5), 3) node _T_559 = dshr(incoming_writes_Q.io.deq.bits.data, _T_558) connect Queue10_UInt8_24.io.enq.bits, _T_559 node _T_560 = eq(UInt<5>(0h19), idx_5) when _T_560 : node _T_561 = shl(UInt<3>(0h5), 3) node _T_562 = dshr(incoming_writes_Q.io.deq.bits.data, _T_561) connect Queue10_UInt8_25.io.enq.bits, _T_562 node _T_563 = eq(UInt<5>(0h1a), idx_5) when _T_563 : node _T_564 = shl(UInt<3>(0h5), 3) node _T_565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_564) connect Queue10_UInt8_26.io.enq.bits, _T_565 node _T_566 = eq(UInt<5>(0h1b), idx_5) when _T_566 : node _T_567 = shl(UInt<3>(0h5), 3) node _T_568 = dshr(incoming_writes_Q.io.deq.bits.data, _T_567) connect Queue10_UInt8_27.io.enq.bits, _T_568 node _T_569 = eq(UInt<5>(0h1c), idx_5) when _T_569 : node _T_570 = shl(UInt<3>(0h5), 3) node _T_571 = dshr(incoming_writes_Q.io.deq.bits.data, _T_570) connect Queue10_UInt8_28.io.enq.bits, _T_571 node _T_572 = eq(UInt<5>(0h1d), idx_5) when _T_572 : node _T_573 = shl(UInt<3>(0h5), 3) node _T_574 = dshr(incoming_writes_Q.io.deq.bits.data, _T_573) connect Queue10_UInt8_29.io.enq.bits, _T_574 node _T_575 = eq(UInt<5>(0h1e), idx_5) when _T_575 : node _T_576 = shl(UInt<3>(0h5), 3) node _T_577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_576) connect Queue10_UInt8_30.io.enq.bits, _T_577 node _T_578 = eq(UInt<5>(0h1f), idx_5) when _T_578 : node _T_579 = shl(UInt<3>(0h5), 3) node _T_580 = dshr(incoming_writes_Q.io.deq.bits.data, _T_579) connect Queue10_UInt8_31.io.enq.bits, _T_580 node _idx_T_6 = add(write_start_index, UInt<3>(0h6)) node idx_6 = rem(_idx_T_6, UInt<6>(0h20)) node _T_581 = eq(UInt<1>(0h0), idx_6) when _T_581 : node _T_582 = shl(UInt<3>(0h6), 3) node _T_583 = dshr(incoming_writes_Q.io.deq.bits.data, _T_582) connect Queue10_UInt8.io.enq.bits, _T_583 node _T_584 = eq(UInt<1>(0h1), idx_6) when _T_584 : node _T_585 = shl(UInt<3>(0h6), 3) node _T_586 = dshr(incoming_writes_Q.io.deq.bits.data, _T_585) connect Queue10_UInt8_1.io.enq.bits, _T_586 node _T_587 = eq(UInt<2>(0h2), idx_6) when _T_587 : node _T_588 = shl(UInt<3>(0h6), 3) node _T_589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_588) connect Queue10_UInt8_2.io.enq.bits, _T_589 node _T_590 = eq(UInt<2>(0h3), idx_6) when _T_590 : node _T_591 = shl(UInt<3>(0h6), 3) node _T_592 = dshr(incoming_writes_Q.io.deq.bits.data, _T_591) connect Queue10_UInt8_3.io.enq.bits, _T_592 node _T_593 = eq(UInt<3>(0h4), idx_6) when _T_593 : node _T_594 = shl(UInt<3>(0h6), 3) node _T_595 = dshr(incoming_writes_Q.io.deq.bits.data, _T_594) connect Queue10_UInt8_4.io.enq.bits, _T_595 node _T_596 = eq(UInt<3>(0h5), idx_6) when _T_596 : node _T_597 = shl(UInt<3>(0h6), 3) node _T_598 = dshr(incoming_writes_Q.io.deq.bits.data, _T_597) connect Queue10_UInt8_5.io.enq.bits, _T_598 node _T_599 = eq(UInt<3>(0h6), idx_6) when _T_599 : node _T_600 = shl(UInt<3>(0h6), 3) node _T_601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_600) connect Queue10_UInt8_6.io.enq.bits, _T_601 node _T_602 = eq(UInt<3>(0h7), idx_6) when _T_602 : node _T_603 = shl(UInt<3>(0h6), 3) node _T_604 = dshr(incoming_writes_Q.io.deq.bits.data, _T_603) connect Queue10_UInt8_7.io.enq.bits, _T_604 node _T_605 = eq(UInt<4>(0h8), idx_6) when _T_605 : node _T_606 = shl(UInt<3>(0h6), 3) node _T_607 = dshr(incoming_writes_Q.io.deq.bits.data, _T_606) connect Queue10_UInt8_8.io.enq.bits, _T_607 node _T_608 = eq(UInt<4>(0h9), idx_6) when _T_608 : node _T_609 = shl(UInt<3>(0h6), 3) node _T_610 = dshr(incoming_writes_Q.io.deq.bits.data, _T_609) connect Queue10_UInt8_9.io.enq.bits, _T_610 node _T_611 = eq(UInt<4>(0ha), idx_6) when _T_611 : node _T_612 = shl(UInt<3>(0h6), 3) node _T_613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_612) connect Queue10_UInt8_10.io.enq.bits, _T_613 node _T_614 = eq(UInt<4>(0hb), idx_6) when _T_614 : node _T_615 = shl(UInt<3>(0h6), 3) node _T_616 = dshr(incoming_writes_Q.io.deq.bits.data, _T_615) connect Queue10_UInt8_11.io.enq.bits, _T_616 node _T_617 = eq(UInt<4>(0hc), idx_6) when _T_617 : node _T_618 = shl(UInt<3>(0h6), 3) node _T_619 = dshr(incoming_writes_Q.io.deq.bits.data, _T_618) connect Queue10_UInt8_12.io.enq.bits, _T_619 node _T_620 = eq(UInt<4>(0hd), idx_6) when _T_620 : node _T_621 = shl(UInt<3>(0h6), 3) node _T_622 = dshr(incoming_writes_Q.io.deq.bits.data, _T_621) connect Queue10_UInt8_13.io.enq.bits, _T_622 node _T_623 = eq(UInt<4>(0he), idx_6) when _T_623 : node _T_624 = shl(UInt<3>(0h6), 3) node _T_625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_624) connect Queue10_UInt8_14.io.enq.bits, _T_625 node _T_626 = eq(UInt<4>(0hf), idx_6) when _T_626 : node _T_627 = shl(UInt<3>(0h6), 3) node _T_628 = dshr(incoming_writes_Q.io.deq.bits.data, _T_627) connect Queue10_UInt8_15.io.enq.bits, _T_628 node _T_629 = eq(UInt<5>(0h10), idx_6) when _T_629 : node _T_630 = shl(UInt<3>(0h6), 3) node _T_631 = dshr(incoming_writes_Q.io.deq.bits.data, _T_630) connect Queue10_UInt8_16.io.enq.bits, _T_631 node _T_632 = eq(UInt<5>(0h11), idx_6) when _T_632 : node _T_633 = shl(UInt<3>(0h6), 3) node _T_634 = dshr(incoming_writes_Q.io.deq.bits.data, _T_633) connect Queue10_UInt8_17.io.enq.bits, _T_634 node _T_635 = eq(UInt<5>(0h12), idx_6) when _T_635 : node _T_636 = shl(UInt<3>(0h6), 3) node _T_637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_636) connect Queue10_UInt8_18.io.enq.bits, _T_637 node _T_638 = eq(UInt<5>(0h13), idx_6) when _T_638 : node _T_639 = shl(UInt<3>(0h6), 3) node _T_640 = dshr(incoming_writes_Q.io.deq.bits.data, _T_639) connect Queue10_UInt8_19.io.enq.bits, _T_640 node _T_641 = eq(UInt<5>(0h14), idx_6) when _T_641 : node _T_642 = shl(UInt<3>(0h6), 3) node _T_643 = dshr(incoming_writes_Q.io.deq.bits.data, _T_642) connect Queue10_UInt8_20.io.enq.bits, _T_643 node _T_644 = eq(UInt<5>(0h15), idx_6) when _T_644 : node _T_645 = shl(UInt<3>(0h6), 3) node _T_646 = dshr(incoming_writes_Q.io.deq.bits.data, _T_645) connect Queue10_UInt8_21.io.enq.bits, _T_646 node _T_647 = eq(UInt<5>(0h16), idx_6) when _T_647 : node _T_648 = shl(UInt<3>(0h6), 3) node _T_649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_648) connect Queue10_UInt8_22.io.enq.bits, _T_649 node _T_650 = eq(UInt<5>(0h17), idx_6) when _T_650 : node _T_651 = shl(UInt<3>(0h6), 3) node _T_652 = dshr(incoming_writes_Q.io.deq.bits.data, _T_651) connect Queue10_UInt8_23.io.enq.bits, _T_652 node _T_653 = eq(UInt<5>(0h18), idx_6) when _T_653 : node _T_654 = shl(UInt<3>(0h6), 3) node _T_655 = dshr(incoming_writes_Q.io.deq.bits.data, _T_654) connect Queue10_UInt8_24.io.enq.bits, _T_655 node _T_656 = eq(UInt<5>(0h19), idx_6) when _T_656 : node _T_657 = shl(UInt<3>(0h6), 3) node _T_658 = dshr(incoming_writes_Q.io.deq.bits.data, _T_657) connect Queue10_UInt8_25.io.enq.bits, _T_658 node _T_659 = eq(UInt<5>(0h1a), idx_6) when _T_659 : node _T_660 = shl(UInt<3>(0h6), 3) node _T_661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_660) connect Queue10_UInt8_26.io.enq.bits, _T_661 node _T_662 = eq(UInt<5>(0h1b), idx_6) when _T_662 : node _T_663 = shl(UInt<3>(0h6), 3) node _T_664 = dshr(incoming_writes_Q.io.deq.bits.data, _T_663) connect Queue10_UInt8_27.io.enq.bits, _T_664 node _T_665 = eq(UInt<5>(0h1c), idx_6) when _T_665 : node _T_666 = shl(UInt<3>(0h6), 3) node _T_667 = dshr(incoming_writes_Q.io.deq.bits.data, _T_666) connect Queue10_UInt8_28.io.enq.bits, _T_667 node _T_668 = eq(UInt<5>(0h1d), idx_6) when _T_668 : node _T_669 = shl(UInt<3>(0h6), 3) node _T_670 = dshr(incoming_writes_Q.io.deq.bits.data, _T_669) connect Queue10_UInt8_29.io.enq.bits, _T_670 node _T_671 = eq(UInt<5>(0h1e), idx_6) when _T_671 : node _T_672 = shl(UInt<3>(0h6), 3) node _T_673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_672) connect Queue10_UInt8_30.io.enq.bits, _T_673 node _T_674 = eq(UInt<5>(0h1f), idx_6) when _T_674 : node _T_675 = shl(UInt<3>(0h6), 3) node _T_676 = dshr(incoming_writes_Q.io.deq.bits.data, _T_675) connect Queue10_UInt8_31.io.enq.bits, _T_676 node _idx_T_7 = add(write_start_index, UInt<3>(0h7)) node idx_7 = rem(_idx_T_7, UInt<6>(0h20)) node _T_677 = eq(UInt<1>(0h0), idx_7) when _T_677 : node _T_678 = shl(UInt<3>(0h7), 3) node _T_679 = dshr(incoming_writes_Q.io.deq.bits.data, _T_678) connect Queue10_UInt8.io.enq.bits, _T_679 node _T_680 = eq(UInt<1>(0h1), idx_7) when _T_680 : node _T_681 = shl(UInt<3>(0h7), 3) node _T_682 = dshr(incoming_writes_Q.io.deq.bits.data, _T_681) connect Queue10_UInt8_1.io.enq.bits, _T_682 node _T_683 = eq(UInt<2>(0h2), idx_7) when _T_683 : node _T_684 = shl(UInt<3>(0h7), 3) node _T_685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_684) connect Queue10_UInt8_2.io.enq.bits, _T_685 node _T_686 = eq(UInt<2>(0h3), idx_7) when _T_686 : node _T_687 = shl(UInt<3>(0h7), 3) node _T_688 = dshr(incoming_writes_Q.io.deq.bits.data, _T_687) connect Queue10_UInt8_3.io.enq.bits, _T_688 node _T_689 = eq(UInt<3>(0h4), idx_7) when _T_689 : node _T_690 = shl(UInt<3>(0h7), 3) node _T_691 = dshr(incoming_writes_Q.io.deq.bits.data, _T_690) connect Queue10_UInt8_4.io.enq.bits, _T_691 node _T_692 = eq(UInt<3>(0h5), idx_7) when _T_692 : node _T_693 = shl(UInt<3>(0h7), 3) node _T_694 = dshr(incoming_writes_Q.io.deq.bits.data, _T_693) connect Queue10_UInt8_5.io.enq.bits, _T_694 node _T_695 = eq(UInt<3>(0h6), idx_7) when _T_695 : node _T_696 = shl(UInt<3>(0h7), 3) node _T_697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_696) connect Queue10_UInt8_6.io.enq.bits, _T_697 node _T_698 = eq(UInt<3>(0h7), idx_7) when _T_698 : node _T_699 = shl(UInt<3>(0h7), 3) node _T_700 = dshr(incoming_writes_Q.io.deq.bits.data, _T_699) connect Queue10_UInt8_7.io.enq.bits, _T_700 node _T_701 = eq(UInt<4>(0h8), idx_7) when _T_701 : node _T_702 = shl(UInt<3>(0h7), 3) node _T_703 = dshr(incoming_writes_Q.io.deq.bits.data, _T_702) connect Queue10_UInt8_8.io.enq.bits, _T_703 node _T_704 = eq(UInt<4>(0h9), idx_7) when _T_704 : node _T_705 = shl(UInt<3>(0h7), 3) node _T_706 = dshr(incoming_writes_Q.io.deq.bits.data, _T_705) connect Queue10_UInt8_9.io.enq.bits, _T_706 node _T_707 = eq(UInt<4>(0ha), idx_7) when _T_707 : node _T_708 = shl(UInt<3>(0h7), 3) node _T_709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_708) connect Queue10_UInt8_10.io.enq.bits, _T_709 node _T_710 = eq(UInt<4>(0hb), idx_7) when _T_710 : node _T_711 = shl(UInt<3>(0h7), 3) node _T_712 = dshr(incoming_writes_Q.io.deq.bits.data, _T_711) connect Queue10_UInt8_11.io.enq.bits, _T_712 node _T_713 = eq(UInt<4>(0hc), idx_7) when _T_713 : node _T_714 = shl(UInt<3>(0h7), 3) node _T_715 = dshr(incoming_writes_Q.io.deq.bits.data, _T_714) connect Queue10_UInt8_12.io.enq.bits, _T_715 node _T_716 = eq(UInt<4>(0hd), idx_7) when _T_716 : node _T_717 = shl(UInt<3>(0h7), 3) node _T_718 = dshr(incoming_writes_Q.io.deq.bits.data, _T_717) connect Queue10_UInt8_13.io.enq.bits, _T_718 node _T_719 = eq(UInt<4>(0he), idx_7) when _T_719 : node _T_720 = shl(UInt<3>(0h7), 3) node _T_721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_720) connect Queue10_UInt8_14.io.enq.bits, _T_721 node _T_722 = eq(UInt<4>(0hf), idx_7) when _T_722 : node _T_723 = shl(UInt<3>(0h7), 3) node _T_724 = dshr(incoming_writes_Q.io.deq.bits.data, _T_723) connect Queue10_UInt8_15.io.enq.bits, _T_724 node _T_725 = eq(UInt<5>(0h10), idx_7) when _T_725 : node _T_726 = shl(UInt<3>(0h7), 3) node _T_727 = dshr(incoming_writes_Q.io.deq.bits.data, _T_726) connect Queue10_UInt8_16.io.enq.bits, _T_727 node _T_728 = eq(UInt<5>(0h11), idx_7) when _T_728 : node _T_729 = shl(UInt<3>(0h7), 3) node _T_730 = dshr(incoming_writes_Q.io.deq.bits.data, _T_729) connect Queue10_UInt8_17.io.enq.bits, _T_730 node _T_731 = eq(UInt<5>(0h12), idx_7) when _T_731 : node _T_732 = shl(UInt<3>(0h7), 3) node _T_733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_732) connect Queue10_UInt8_18.io.enq.bits, _T_733 node _T_734 = eq(UInt<5>(0h13), idx_7) when _T_734 : node _T_735 = shl(UInt<3>(0h7), 3) node _T_736 = dshr(incoming_writes_Q.io.deq.bits.data, _T_735) connect Queue10_UInt8_19.io.enq.bits, _T_736 node _T_737 = eq(UInt<5>(0h14), idx_7) when _T_737 : node _T_738 = shl(UInt<3>(0h7), 3) node _T_739 = dshr(incoming_writes_Q.io.deq.bits.data, _T_738) connect Queue10_UInt8_20.io.enq.bits, _T_739 node _T_740 = eq(UInt<5>(0h15), idx_7) when _T_740 : node _T_741 = shl(UInt<3>(0h7), 3) node _T_742 = dshr(incoming_writes_Q.io.deq.bits.data, _T_741) connect Queue10_UInt8_21.io.enq.bits, _T_742 node _T_743 = eq(UInt<5>(0h16), idx_7) when _T_743 : node _T_744 = shl(UInt<3>(0h7), 3) node _T_745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_744) connect Queue10_UInt8_22.io.enq.bits, _T_745 node _T_746 = eq(UInt<5>(0h17), idx_7) when _T_746 : node _T_747 = shl(UInt<3>(0h7), 3) node _T_748 = dshr(incoming_writes_Q.io.deq.bits.data, _T_747) connect Queue10_UInt8_23.io.enq.bits, _T_748 node _T_749 = eq(UInt<5>(0h18), idx_7) when _T_749 : node _T_750 = shl(UInt<3>(0h7), 3) node _T_751 = dshr(incoming_writes_Q.io.deq.bits.data, _T_750) connect Queue10_UInt8_24.io.enq.bits, _T_751 node _T_752 = eq(UInt<5>(0h19), idx_7) when _T_752 : node _T_753 = shl(UInt<3>(0h7), 3) node _T_754 = dshr(incoming_writes_Q.io.deq.bits.data, _T_753) connect Queue10_UInt8_25.io.enq.bits, _T_754 node _T_755 = eq(UInt<5>(0h1a), idx_7) when _T_755 : node _T_756 = shl(UInt<3>(0h7), 3) node _T_757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_756) connect Queue10_UInt8_26.io.enq.bits, _T_757 node _T_758 = eq(UInt<5>(0h1b), idx_7) when _T_758 : node _T_759 = shl(UInt<3>(0h7), 3) node _T_760 = dshr(incoming_writes_Q.io.deq.bits.data, _T_759) connect Queue10_UInt8_27.io.enq.bits, _T_760 node _T_761 = eq(UInt<5>(0h1c), idx_7) when _T_761 : node _T_762 = shl(UInt<3>(0h7), 3) node _T_763 = dshr(incoming_writes_Q.io.deq.bits.data, _T_762) connect Queue10_UInt8_28.io.enq.bits, _T_763 node _T_764 = eq(UInt<5>(0h1d), idx_7) when _T_764 : node _T_765 = shl(UInt<3>(0h7), 3) node _T_766 = dshr(incoming_writes_Q.io.deq.bits.data, _T_765) connect Queue10_UInt8_29.io.enq.bits, _T_766 node _T_767 = eq(UInt<5>(0h1e), idx_7) when _T_767 : node _T_768 = shl(UInt<3>(0h7), 3) node _T_769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_768) connect Queue10_UInt8_30.io.enq.bits, _T_769 node _T_770 = eq(UInt<5>(0h1f), idx_7) when _T_770 : node _T_771 = shl(UInt<3>(0h7), 3) node _T_772 = dshr(incoming_writes_Q.io.deq.bits.data, _T_771) connect Queue10_UInt8_31.io.enq.bits, _T_772 node _idx_T_8 = add(write_start_index, UInt<4>(0h8)) node idx_8 = rem(_idx_T_8, UInt<6>(0h20)) node _T_773 = eq(UInt<1>(0h0), idx_8) when _T_773 : node _T_774 = shl(UInt<4>(0h8), 3) node _T_775 = dshr(incoming_writes_Q.io.deq.bits.data, _T_774) connect Queue10_UInt8.io.enq.bits, _T_775 node _T_776 = eq(UInt<1>(0h1), idx_8) when _T_776 : node _T_777 = shl(UInt<4>(0h8), 3) node _T_778 = dshr(incoming_writes_Q.io.deq.bits.data, _T_777) connect Queue10_UInt8_1.io.enq.bits, _T_778 node _T_779 = eq(UInt<2>(0h2), idx_8) when _T_779 : node _T_780 = shl(UInt<4>(0h8), 3) node _T_781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_780) connect Queue10_UInt8_2.io.enq.bits, _T_781 node _T_782 = eq(UInt<2>(0h3), idx_8) when _T_782 : node _T_783 = shl(UInt<4>(0h8), 3) node _T_784 = dshr(incoming_writes_Q.io.deq.bits.data, _T_783) connect Queue10_UInt8_3.io.enq.bits, _T_784 node _T_785 = eq(UInt<3>(0h4), idx_8) when _T_785 : node _T_786 = shl(UInt<4>(0h8), 3) node _T_787 = dshr(incoming_writes_Q.io.deq.bits.data, _T_786) connect Queue10_UInt8_4.io.enq.bits, _T_787 node _T_788 = eq(UInt<3>(0h5), idx_8) when _T_788 : node _T_789 = shl(UInt<4>(0h8), 3) node _T_790 = dshr(incoming_writes_Q.io.deq.bits.data, _T_789) connect Queue10_UInt8_5.io.enq.bits, _T_790 node _T_791 = eq(UInt<3>(0h6), idx_8) when _T_791 : node _T_792 = shl(UInt<4>(0h8), 3) node _T_793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_792) connect Queue10_UInt8_6.io.enq.bits, _T_793 node _T_794 = eq(UInt<3>(0h7), idx_8) when _T_794 : node _T_795 = shl(UInt<4>(0h8), 3) node _T_796 = dshr(incoming_writes_Q.io.deq.bits.data, _T_795) connect Queue10_UInt8_7.io.enq.bits, _T_796 node _T_797 = eq(UInt<4>(0h8), idx_8) when _T_797 : node _T_798 = shl(UInt<4>(0h8), 3) node _T_799 = dshr(incoming_writes_Q.io.deq.bits.data, _T_798) connect Queue10_UInt8_8.io.enq.bits, _T_799 node _T_800 = eq(UInt<4>(0h9), idx_8) when _T_800 : node _T_801 = shl(UInt<4>(0h8), 3) node _T_802 = dshr(incoming_writes_Q.io.deq.bits.data, _T_801) connect Queue10_UInt8_9.io.enq.bits, _T_802 node _T_803 = eq(UInt<4>(0ha), idx_8) when _T_803 : node _T_804 = shl(UInt<4>(0h8), 3) node _T_805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_804) connect Queue10_UInt8_10.io.enq.bits, _T_805 node _T_806 = eq(UInt<4>(0hb), idx_8) when _T_806 : node _T_807 = shl(UInt<4>(0h8), 3) node _T_808 = dshr(incoming_writes_Q.io.deq.bits.data, _T_807) connect Queue10_UInt8_11.io.enq.bits, _T_808 node _T_809 = eq(UInt<4>(0hc), idx_8) when _T_809 : node _T_810 = shl(UInt<4>(0h8), 3) node _T_811 = dshr(incoming_writes_Q.io.deq.bits.data, _T_810) connect Queue10_UInt8_12.io.enq.bits, _T_811 node _T_812 = eq(UInt<4>(0hd), idx_8) when _T_812 : node _T_813 = shl(UInt<4>(0h8), 3) node _T_814 = dshr(incoming_writes_Q.io.deq.bits.data, _T_813) connect Queue10_UInt8_13.io.enq.bits, _T_814 node _T_815 = eq(UInt<4>(0he), idx_8) when _T_815 : node _T_816 = shl(UInt<4>(0h8), 3) node _T_817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_816) connect Queue10_UInt8_14.io.enq.bits, _T_817 node _T_818 = eq(UInt<4>(0hf), idx_8) when _T_818 : node _T_819 = shl(UInt<4>(0h8), 3) node _T_820 = dshr(incoming_writes_Q.io.deq.bits.data, _T_819) connect Queue10_UInt8_15.io.enq.bits, _T_820 node _T_821 = eq(UInt<5>(0h10), idx_8) when _T_821 : node _T_822 = shl(UInt<4>(0h8), 3) node _T_823 = dshr(incoming_writes_Q.io.deq.bits.data, _T_822) connect Queue10_UInt8_16.io.enq.bits, _T_823 node _T_824 = eq(UInt<5>(0h11), idx_8) when _T_824 : node _T_825 = shl(UInt<4>(0h8), 3) node _T_826 = dshr(incoming_writes_Q.io.deq.bits.data, _T_825) connect Queue10_UInt8_17.io.enq.bits, _T_826 node _T_827 = eq(UInt<5>(0h12), idx_8) when _T_827 : node _T_828 = shl(UInt<4>(0h8), 3) node _T_829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_828) connect Queue10_UInt8_18.io.enq.bits, _T_829 node _T_830 = eq(UInt<5>(0h13), idx_8) when _T_830 : node _T_831 = shl(UInt<4>(0h8), 3) node _T_832 = dshr(incoming_writes_Q.io.deq.bits.data, _T_831) connect Queue10_UInt8_19.io.enq.bits, _T_832 node _T_833 = eq(UInt<5>(0h14), idx_8) when _T_833 : node _T_834 = shl(UInt<4>(0h8), 3) node _T_835 = dshr(incoming_writes_Q.io.deq.bits.data, _T_834) connect Queue10_UInt8_20.io.enq.bits, _T_835 node _T_836 = eq(UInt<5>(0h15), idx_8) when _T_836 : node _T_837 = shl(UInt<4>(0h8), 3) node _T_838 = dshr(incoming_writes_Q.io.deq.bits.data, _T_837) connect Queue10_UInt8_21.io.enq.bits, _T_838 node _T_839 = eq(UInt<5>(0h16), idx_8) when _T_839 : node _T_840 = shl(UInt<4>(0h8), 3) node _T_841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_840) connect Queue10_UInt8_22.io.enq.bits, _T_841 node _T_842 = eq(UInt<5>(0h17), idx_8) when _T_842 : node _T_843 = shl(UInt<4>(0h8), 3) node _T_844 = dshr(incoming_writes_Q.io.deq.bits.data, _T_843) connect Queue10_UInt8_23.io.enq.bits, _T_844 node _T_845 = eq(UInt<5>(0h18), idx_8) when _T_845 : node _T_846 = shl(UInt<4>(0h8), 3) node _T_847 = dshr(incoming_writes_Q.io.deq.bits.data, _T_846) connect Queue10_UInt8_24.io.enq.bits, _T_847 node _T_848 = eq(UInt<5>(0h19), idx_8) when _T_848 : node _T_849 = shl(UInt<4>(0h8), 3) node _T_850 = dshr(incoming_writes_Q.io.deq.bits.data, _T_849) connect Queue10_UInt8_25.io.enq.bits, _T_850 node _T_851 = eq(UInt<5>(0h1a), idx_8) when _T_851 : node _T_852 = shl(UInt<4>(0h8), 3) node _T_853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_852) connect Queue10_UInt8_26.io.enq.bits, _T_853 node _T_854 = eq(UInt<5>(0h1b), idx_8) when _T_854 : node _T_855 = shl(UInt<4>(0h8), 3) node _T_856 = dshr(incoming_writes_Q.io.deq.bits.data, _T_855) connect Queue10_UInt8_27.io.enq.bits, _T_856 node _T_857 = eq(UInt<5>(0h1c), idx_8) when _T_857 : node _T_858 = shl(UInt<4>(0h8), 3) node _T_859 = dshr(incoming_writes_Q.io.deq.bits.data, _T_858) connect Queue10_UInt8_28.io.enq.bits, _T_859 node _T_860 = eq(UInt<5>(0h1d), idx_8) when _T_860 : node _T_861 = shl(UInt<4>(0h8), 3) node _T_862 = dshr(incoming_writes_Q.io.deq.bits.data, _T_861) connect Queue10_UInt8_29.io.enq.bits, _T_862 node _T_863 = eq(UInt<5>(0h1e), idx_8) when _T_863 : node _T_864 = shl(UInt<4>(0h8), 3) node _T_865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_864) connect Queue10_UInt8_30.io.enq.bits, _T_865 node _T_866 = eq(UInt<5>(0h1f), idx_8) when _T_866 : node _T_867 = shl(UInt<4>(0h8), 3) node _T_868 = dshr(incoming_writes_Q.io.deq.bits.data, _T_867) connect Queue10_UInt8_31.io.enq.bits, _T_868 node _idx_T_9 = add(write_start_index, UInt<4>(0h9)) node idx_9 = rem(_idx_T_9, UInt<6>(0h20)) node _T_869 = eq(UInt<1>(0h0), idx_9) when _T_869 : node _T_870 = shl(UInt<4>(0h9), 3) node _T_871 = dshr(incoming_writes_Q.io.deq.bits.data, _T_870) connect Queue10_UInt8.io.enq.bits, _T_871 node _T_872 = eq(UInt<1>(0h1), idx_9) when _T_872 : node _T_873 = shl(UInt<4>(0h9), 3) node _T_874 = dshr(incoming_writes_Q.io.deq.bits.data, _T_873) connect Queue10_UInt8_1.io.enq.bits, _T_874 node _T_875 = eq(UInt<2>(0h2), idx_9) when _T_875 : node _T_876 = shl(UInt<4>(0h9), 3) node _T_877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_876) connect Queue10_UInt8_2.io.enq.bits, _T_877 node _T_878 = eq(UInt<2>(0h3), idx_9) when _T_878 : node _T_879 = shl(UInt<4>(0h9), 3) node _T_880 = dshr(incoming_writes_Q.io.deq.bits.data, _T_879) connect Queue10_UInt8_3.io.enq.bits, _T_880 node _T_881 = eq(UInt<3>(0h4), idx_9) when _T_881 : node _T_882 = shl(UInt<4>(0h9), 3) node _T_883 = dshr(incoming_writes_Q.io.deq.bits.data, _T_882) connect Queue10_UInt8_4.io.enq.bits, _T_883 node _T_884 = eq(UInt<3>(0h5), idx_9) when _T_884 : node _T_885 = shl(UInt<4>(0h9), 3) node _T_886 = dshr(incoming_writes_Q.io.deq.bits.data, _T_885) connect Queue10_UInt8_5.io.enq.bits, _T_886 node _T_887 = eq(UInt<3>(0h6), idx_9) when _T_887 : node _T_888 = shl(UInt<4>(0h9), 3) node _T_889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_888) connect Queue10_UInt8_6.io.enq.bits, _T_889 node _T_890 = eq(UInt<3>(0h7), idx_9) when _T_890 : node _T_891 = shl(UInt<4>(0h9), 3) node _T_892 = dshr(incoming_writes_Q.io.deq.bits.data, _T_891) connect Queue10_UInt8_7.io.enq.bits, _T_892 node _T_893 = eq(UInt<4>(0h8), idx_9) when _T_893 : node _T_894 = shl(UInt<4>(0h9), 3) node _T_895 = dshr(incoming_writes_Q.io.deq.bits.data, _T_894) connect Queue10_UInt8_8.io.enq.bits, _T_895 node _T_896 = eq(UInt<4>(0h9), idx_9) when _T_896 : node _T_897 = shl(UInt<4>(0h9), 3) node _T_898 = dshr(incoming_writes_Q.io.deq.bits.data, _T_897) connect Queue10_UInt8_9.io.enq.bits, _T_898 node _T_899 = eq(UInt<4>(0ha), idx_9) when _T_899 : node _T_900 = shl(UInt<4>(0h9), 3) node _T_901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_900) connect Queue10_UInt8_10.io.enq.bits, _T_901 node _T_902 = eq(UInt<4>(0hb), idx_9) when _T_902 : node _T_903 = shl(UInt<4>(0h9), 3) node _T_904 = dshr(incoming_writes_Q.io.deq.bits.data, _T_903) connect Queue10_UInt8_11.io.enq.bits, _T_904 node _T_905 = eq(UInt<4>(0hc), idx_9) when _T_905 : node _T_906 = shl(UInt<4>(0h9), 3) node _T_907 = dshr(incoming_writes_Q.io.deq.bits.data, _T_906) connect Queue10_UInt8_12.io.enq.bits, _T_907 node _T_908 = eq(UInt<4>(0hd), idx_9) when _T_908 : node _T_909 = shl(UInt<4>(0h9), 3) node _T_910 = dshr(incoming_writes_Q.io.deq.bits.data, _T_909) connect Queue10_UInt8_13.io.enq.bits, _T_910 node _T_911 = eq(UInt<4>(0he), idx_9) when _T_911 : node _T_912 = shl(UInt<4>(0h9), 3) node _T_913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_912) connect Queue10_UInt8_14.io.enq.bits, _T_913 node _T_914 = eq(UInt<4>(0hf), idx_9) when _T_914 : node _T_915 = shl(UInt<4>(0h9), 3) node _T_916 = dshr(incoming_writes_Q.io.deq.bits.data, _T_915) connect Queue10_UInt8_15.io.enq.bits, _T_916 node _T_917 = eq(UInt<5>(0h10), idx_9) when _T_917 : node _T_918 = shl(UInt<4>(0h9), 3) node _T_919 = dshr(incoming_writes_Q.io.deq.bits.data, _T_918) connect Queue10_UInt8_16.io.enq.bits, _T_919 node _T_920 = eq(UInt<5>(0h11), idx_9) when _T_920 : node _T_921 = shl(UInt<4>(0h9), 3) node _T_922 = dshr(incoming_writes_Q.io.deq.bits.data, _T_921) connect Queue10_UInt8_17.io.enq.bits, _T_922 node _T_923 = eq(UInt<5>(0h12), idx_9) when _T_923 : node _T_924 = shl(UInt<4>(0h9), 3) node _T_925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_924) connect Queue10_UInt8_18.io.enq.bits, _T_925 node _T_926 = eq(UInt<5>(0h13), idx_9) when _T_926 : node _T_927 = shl(UInt<4>(0h9), 3) node _T_928 = dshr(incoming_writes_Q.io.deq.bits.data, _T_927) connect Queue10_UInt8_19.io.enq.bits, _T_928 node _T_929 = eq(UInt<5>(0h14), idx_9) when _T_929 : node _T_930 = shl(UInt<4>(0h9), 3) node _T_931 = dshr(incoming_writes_Q.io.deq.bits.data, _T_930) connect Queue10_UInt8_20.io.enq.bits, _T_931 node _T_932 = eq(UInt<5>(0h15), idx_9) when _T_932 : node _T_933 = shl(UInt<4>(0h9), 3) node _T_934 = dshr(incoming_writes_Q.io.deq.bits.data, _T_933) connect Queue10_UInt8_21.io.enq.bits, _T_934 node _T_935 = eq(UInt<5>(0h16), idx_9) when _T_935 : node _T_936 = shl(UInt<4>(0h9), 3) node _T_937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_936) connect Queue10_UInt8_22.io.enq.bits, _T_937 node _T_938 = eq(UInt<5>(0h17), idx_9) when _T_938 : node _T_939 = shl(UInt<4>(0h9), 3) node _T_940 = dshr(incoming_writes_Q.io.deq.bits.data, _T_939) connect Queue10_UInt8_23.io.enq.bits, _T_940 node _T_941 = eq(UInt<5>(0h18), idx_9) when _T_941 : node _T_942 = shl(UInt<4>(0h9), 3) node _T_943 = dshr(incoming_writes_Q.io.deq.bits.data, _T_942) connect Queue10_UInt8_24.io.enq.bits, _T_943 node _T_944 = eq(UInt<5>(0h19), idx_9) when _T_944 : node _T_945 = shl(UInt<4>(0h9), 3) node _T_946 = dshr(incoming_writes_Q.io.deq.bits.data, _T_945) connect Queue10_UInt8_25.io.enq.bits, _T_946 node _T_947 = eq(UInt<5>(0h1a), idx_9) when _T_947 : node _T_948 = shl(UInt<4>(0h9), 3) node _T_949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_948) connect Queue10_UInt8_26.io.enq.bits, _T_949 node _T_950 = eq(UInt<5>(0h1b), idx_9) when _T_950 : node _T_951 = shl(UInt<4>(0h9), 3) node _T_952 = dshr(incoming_writes_Q.io.deq.bits.data, _T_951) connect Queue10_UInt8_27.io.enq.bits, _T_952 node _T_953 = eq(UInt<5>(0h1c), idx_9) when _T_953 : node _T_954 = shl(UInt<4>(0h9), 3) node _T_955 = dshr(incoming_writes_Q.io.deq.bits.data, _T_954) connect Queue10_UInt8_28.io.enq.bits, _T_955 node _T_956 = eq(UInt<5>(0h1d), idx_9) when _T_956 : node _T_957 = shl(UInt<4>(0h9), 3) node _T_958 = dshr(incoming_writes_Q.io.deq.bits.data, _T_957) connect Queue10_UInt8_29.io.enq.bits, _T_958 node _T_959 = eq(UInt<5>(0h1e), idx_9) when _T_959 : node _T_960 = shl(UInt<4>(0h9), 3) node _T_961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_960) connect Queue10_UInt8_30.io.enq.bits, _T_961 node _T_962 = eq(UInt<5>(0h1f), idx_9) when _T_962 : node _T_963 = shl(UInt<4>(0h9), 3) node _T_964 = dshr(incoming_writes_Q.io.deq.bits.data, _T_963) connect Queue10_UInt8_31.io.enq.bits, _T_964 node _idx_T_10 = add(write_start_index, UInt<4>(0ha)) node idx_10 = rem(_idx_T_10, UInt<6>(0h20)) node _T_965 = eq(UInt<1>(0h0), idx_10) when _T_965 : node _T_966 = shl(UInt<4>(0ha), 3) node _T_967 = dshr(incoming_writes_Q.io.deq.bits.data, _T_966) connect Queue10_UInt8.io.enq.bits, _T_967 node _T_968 = eq(UInt<1>(0h1), idx_10) when _T_968 : node _T_969 = shl(UInt<4>(0ha), 3) node _T_970 = dshr(incoming_writes_Q.io.deq.bits.data, _T_969) connect Queue10_UInt8_1.io.enq.bits, _T_970 node _T_971 = eq(UInt<2>(0h2), idx_10) when _T_971 : node _T_972 = shl(UInt<4>(0ha), 3) node _T_973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_972) connect Queue10_UInt8_2.io.enq.bits, _T_973 node _T_974 = eq(UInt<2>(0h3), idx_10) when _T_974 : node _T_975 = shl(UInt<4>(0ha), 3) node _T_976 = dshr(incoming_writes_Q.io.deq.bits.data, _T_975) connect Queue10_UInt8_3.io.enq.bits, _T_976 node _T_977 = eq(UInt<3>(0h4), idx_10) when _T_977 : node _T_978 = shl(UInt<4>(0ha), 3) node _T_979 = dshr(incoming_writes_Q.io.deq.bits.data, _T_978) connect Queue10_UInt8_4.io.enq.bits, _T_979 node _T_980 = eq(UInt<3>(0h5), idx_10) when _T_980 : node _T_981 = shl(UInt<4>(0ha), 3) node _T_982 = dshr(incoming_writes_Q.io.deq.bits.data, _T_981) connect Queue10_UInt8_5.io.enq.bits, _T_982 node _T_983 = eq(UInt<3>(0h6), idx_10) when _T_983 : node _T_984 = shl(UInt<4>(0ha), 3) node _T_985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_984) connect Queue10_UInt8_6.io.enq.bits, _T_985 node _T_986 = eq(UInt<3>(0h7), idx_10) when _T_986 : node _T_987 = shl(UInt<4>(0ha), 3) node _T_988 = dshr(incoming_writes_Q.io.deq.bits.data, _T_987) connect Queue10_UInt8_7.io.enq.bits, _T_988 node _T_989 = eq(UInt<4>(0h8), idx_10) when _T_989 : node _T_990 = shl(UInt<4>(0ha), 3) node _T_991 = dshr(incoming_writes_Q.io.deq.bits.data, _T_990) connect Queue10_UInt8_8.io.enq.bits, _T_991 node _T_992 = eq(UInt<4>(0h9), idx_10) when _T_992 : node _T_993 = shl(UInt<4>(0ha), 3) node _T_994 = dshr(incoming_writes_Q.io.deq.bits.data, _T_993) connect Queue10_UInt8_9.io.enq.bits, _T_994 node _T_995 = eq(UInt<4>(0ha), idx_10) when _T_995 : node _T_996 = shl(UInt<4>(0ha), 3) node _T_997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_996) connect Queue10_UInt8_10.io.enq.bits, _T_997 node _T_998 = eq(UInt<4>(0hb), idx_10) when _T_998 : node _T_999 = shl(UInt<4>(0ha), 3) node _T_1000 = dshr(incoming_writes_Q.io.deq.bits.data, _T_999) connect Queue10_UInt8_11.io.enq.bits, _T_1000 node _T_1001 = eq(UInt<4>(0hc), idx_10) when _T_1001 : node _T_1002 = shl(UInt<4>(0ha), 3) node _T_1003 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1002) connect Queue10_UInt8_12.io.enq.bits, _T_1003 node _T_1004 = eq(UInt<4>(0hd), idx_10) when _T_1004 : node _T_1005 = shl(UInt<4>(0ha), 3) node _T_1006 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1005) connect Queue10_UInt8_13.io.enq.bits, _T_1006 node _T_1007 = eq(UInt<4>(0he), idx_10) when _T_1007 : node _T_1008 = shl(UInt<4>(0ha), 3) node _T_1009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1008) connect Queue10_UInt8_14.io.enq.bits, _T_1009 node _T_1010 = eq(UInt<4>(0hf), idx_10) when _T_1010 : node _T_1011 = shl(UInt<4>(0ha), 3) node _T_1012 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1011) connect Queue10_UInt8_15.io.enq.bits, _T_1012 node _T_1013 = eq(UInt<5>(0h10), idx_10) when _T_1013 : node _T_1014 = shl(UInt<4>(0ha), 3) node _T_1015 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1014) connect Queue10_UInt8_16.io.enq.bits, _T_1015 node _T_1016 = eq(UInt<5>(0h11), idx_10) when _T_1016 : node _T_1017 = shl(UInt<4>(0ha), 3) node _T_1018 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1017) connect Queue10_UInt8_17.io.enq.bits, _T_1018 node _T_1019 = eq(UInt<5>(0h12), idx_10) when _T_1019 : node _T_1020 = shl(UInt<4>(0ha), 3) node _T_1021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1020) connect Queue10_UInt8_18.io.enq.bits, _T_1021 node _T_1022 = eq(UInt<5>(0h13), idx_10) when _T_1022 : node _T_1023 = shl(UInt<4>(0ha), 3) node _T_1024 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1023) connect Queue10_UInt8_19.io.enq.bits, _T_1024 node _T_1025 = eq(UInt<5>(0h14), idx_10) when _T_1025 : node _T_1026 = shl(UInt<4>(0ha), 3) node _T_1027 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1026) connect Queue10_UInt8_20.io.enq.bits, _T_1027 node _T_1028 = eq(UInt<5>(0h15), idx_10) when _T_1028 : node _T_1029 = shl(UInt<4>(0ha), 3) node _T_1030 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1029) connect Queue10_UInt8_21.io.enq.bits, _T_1030 node _T_1031 = eq(UInt<5>(0h16), idx_10) when _T_1031 : node _T_1032 = shl(UInt<4>(0ha), 3) node _T_1033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1032) connect Queue10_UInt8_22.io.enq.bits, _T_1033 node _T_1034 = eq(UInt<5>(0h17), idx_10) when _T_1034 : node _T_1035 = shl(UInt<4>(0ha), 3) node _T_1036 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1035) connect Queue10_UInt8_23.io.enq.bits, _T_1036 node _T_1037 = eq(UInt<5>(0h18), idx_10) when _T_1037 : node _T_1038 = shl(UInt<4>(0ha), 3) node _T_1039 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1038) connect Queue10_UInt8_24.io.enq.bits, _T_1039 node _T_1040 = eq(UInt<5>(0h19), idx_10) when _T_1040 : node _T_1041 = shl(UInt<4>(0ha), 3) node _T_1042 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1041) connect Queue10_UInt8_25.io.enq.bits, _T_1042 node _T_1043 = eq(UInt<5>(0h1a), idx_10) when _T_1043 : node _T_1044 = shl(UInt<4>(0ha), 3) node _T_1045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1044) connect Queue10_UInt8_26.io.enq.bits, _T_1045 node _T_1046 = eq(UInt<5>(0h1b), idx_10) when _T_1046 : node _T_1047 = shl(UInt<4>(0ha), 3) node _T_1048 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1047) connect Queue10_UInt8_27.io.enq.bits, _T_1048 node _T_1049 = eq(UInt<5>(0h1c), idx_10) when _T_1049 : node _T_1050 = shl(UInt<4>(0ha), 3) node _T_1051 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1050) connect Queue10_UInt8_28.io.enq.bits, _T_1051 node _T_1052 = eq(UInt<5>(0h1d), idx_10) when _T_1052 : node _T_1053 = shl(UInt<4>(0ha), 3) node _T_1054 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1053) connect Queue10_UInt8_29.io.enq.bits, _T_1054 node _T_1055 = eq(UInt<5>(0h1e), idx_10) when _T_1055 : node _T_1056 = shl(UInt<4>(0ha), 3) node _T_1057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1056) connect Queue10_UInt8_30.io.enq.bits, _T_1057 node _T_1058 = eq(UInt<5>(0h1f), idx_10) when _T_1058 : node _T_1059 = shl(UInt<4>(0ha), 3) node _T_1060 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1059) connect Queue10_UInt8_31.io.enq.bits, _T_1060 node _idx_T_11 = add(write_start_index, UInt<4>(0hb)) node idx_11 = rem(_idx_T_11, UInt<6>(0h20)) node _T_1061 = eq(UInt<1>(0h0), idx_11) when _T_1061 : node _T_1062 = shl(UInt<4>(0hb), 3) node _T_1063 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1062) connect Queue10_UInt8.io.enq.bits, _T_1063 node _T_1064 = eq(UInt<1>(0h1), idx_11) when _T_1064 : node _T_1065 = shl(UInt<4>(0hb), 3) node _T_1066 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1065) connect Queue10_UInt8_1.io.enq.bits, _T_1066 node _T_1067 = eq(UInt<2>(0h2), idx_11) when _T_1067 : node _T_1068 = shl(UInt<4>(0hb), 3) node _T_1069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1068) connect Queue10_UInt8_2.io.enq.bits, _T_1069 node _T_1070 = eq(UInt<2>(0h3), idx_11) when _T_1070 : node _T_1071 = shl(UInt<4>(0hb), 3) node _T_1072 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1071) connect Queue10_UInt8_3.io.enq.bits, _T_1072 node _T_1073 = eq(UInt<3>(0h4), idx_11) when _T_1073 : node _T_1074 = shl(UInt<4>(0hb), 3) node _T_1075 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1074) connect Queue10_UInt8_4.io.enq.bits, _T_1075 node _T_1076 = eq(UInt<3>(0h5), idx_11) when _T_1076 : node _T_1077 = shl(UInt<4>(0hb), 3) node _T_1078 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1077) connect Queue10_UInt8_5.io.enq.bits, _T_1078 node _T_1079 = eq(UInt<3>(0h6), idx_11) when _T_1079 : node _T_1080 = shl(UInt<4>(0hb), 3) node _T_1081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1080) connect Queue10_UInt8_6.io.enq.bits, _T_1081 node _T_1082 = eq(UInt<3>(0h7), idx_11) when _T_1082 : node _T_1083 = shl(UInt<4>(0hb), 3) node _T_1084 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1083) connect Queue10_UInt8_7.io.enq.bits, _T_1084 node _T_1085 = eq(UInt<4>(0h8), idx_11) when _T_1085 : node _T_1086 = shl(UInt<4>(0hb), 3) node _T_1087 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1086) connect Queue10_UInt8_8.io.enq.bits, _T_1087 node _T_1088 = eq(UInt<4>(0h9), idx_11) when _T_1088 : node _T_1089 = shl(UInt<4>(0hb), 3) node _T_1090 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1089) connect Queue10_UInt8_9.io.enq.bits, _T_1090 node _T_1091 = eq(UInt<4>(0ha), idx_11) when _T_1091 : node _T_1092 = shl(UInt<4>(0hb), 3) node _T_1093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1092) connect Queue10_UInt8_10.io.enq.bits, _T_1093 node _T_1094 = eq(UInt<4>(0hb), idx_11) when _T_1094 : node _T_1095 = shl(UInt<4>(0hb), 3) node _T_1096 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1095) connect Queue10_UInt8_11.io.enq.bits, _T_1096 node _T_1097 = eq(UInt<4>(0hc), idx_11) when _T_1097 : node _T_1098 = shl(UInt<4>(0hb), 3) node _T_1099 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1098) connect Queue10_UInt8_12.io.enq.bits, _T_1099 node _T_1100 = eq(UInt<4>(0hd), idx_11) when _T_1100 : node _T_1101 = shl(UInt<4>(0hb), 3) node _T_1102 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1101) connect Queue10_UInt8_13.io.enq.bits, _T_1102 node _T_1103 = eq(UInt<4>(0he), idx_11) when _T_1103 : node _T_1104 = shl(UInt<4>(0hb), 3) node _T_1105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1104) connect Queue10_UInt8_14.io.enq.bits, _T_1105 node _T_1106 = eq(UInt<4>(0hf), idx_11) when _T_1106 : node _T_1107 = shl(UInt<4>(0hb), 3) node _T_1108 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1107) connect Queue10_UInt8_15.io.enq.bits, _T_1108 node _T_1109 = eq(UInt<5>(0h10), idx_11) when _T_1109 : node _T_1110 = shl(UInt<4>(0hb), 3) node _T_1111 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1110) connect Queue10_UInt8_16.io.enq.bits, _T_1111 node _T_1112 = eq(UInt<5>(0h11), idx_11) when _T_1112 : node _T_1113 = shl(UInt<4>(0hb), 3) node _T_1114 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1113) connect Queue10_UInt8_17.io.enq.bits, _T_1114 node _T_1115 = eq(UInt<5>(0h12), idx_11) when _T_1115 : node _T_1116 = shl(UInt<4>(0hb), 3) node _T_1117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1116) connect Queue10_UInt8_18.io.enq.bits, _T_1117 node _T_1118 = eq(UInt<5>(0h13), idx_11) when _T_1118 : node _T_1119 = shl(UInt<4>(0hb), 3) node _T_1120 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1119) connect Queue10_UInt8_19.io.enq.bits, _T_1120 node _T_1121 = eq(UInt<5>(0h14), idx_11) when _T_1121 : node _T_1122 = shl(UInt<4>(0hb), 3) node _T_1123 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1122) connect Queue10_UInt8_20.io.enq.bits, _T_1123 node _T_1124 = eq(UInt<5>(0h15), idx_11) when _T_1124 : node _T_1125 = shl(UInt<4>(0hb), 3) node _T_1126 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1125) connect Queue10_UInt8_21.io.enq.bits, _T_1126 node _T_1127 = eq(UInt<5>(0h16), idx_11) when _T_1127 : node _T_1128 = shl(UInt<4>(0hb), 3) node _T_1129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1128) connect Queue10_UInt8_22.io.enq.bits, _T_1129 node _T_1130 = eq(UInt<5>(0h17), idx_11) when _T_1130 : node _T_1131 = shl(UInt<4>(0hb), 3) node _T_1132 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1131) connect Queue10_UInt8_23.io.enq.bits, _T_1132 node _T_1133 = eq(UInt<5>(0h18), idx_11) when _T_1133 : node _T_1134 = shl(UInt<4>(0hb), 3) node _T_1135 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1134) connect Queue10_UInt8_24.io.enq.bits, _T_1135 node _T_1136 = eq(UInt<5>(0h19), idx_11) when _T_1136 : node _T_1137 = shl(UInt<4>(0hb), 3) node _T_1138 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1137) connect Queue10_UInt8_25.io.enq.bits, _T_1138 node _T_1139 = eq(UInt<5>(0h1a), idx_11) when _T_1139 : node _T_1140 = shl(UInt<4>(0hb), 3) node _T_1141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1140) connect Queue10_UInt8_26.io.enq.bits, _T_1141 node _T_1142 = eq(UInt<5>(0h1b), idx_11) when _T_1142 : node _T_1143 = shl(UInt<4>(0hb), 3) node _T_1144 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1143) connect Queue10_UInt8_27.io.enq.bits, _T_1144 node _T_1145 = eq(UInt<5>(0h1c), idx_11) when _T_1145 : node _T_1146 = shl(UInt<4>(0hb), 3) node _T_1147 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1146) connect Queue10_UInt8_28.io.enq.bits, _T_1147 node _T_1148 = eq(UInt<5>(0h1d), idx_11) when _T_1148 : node _T_1149 = shl(UInt<4>(0hb), 3) node _T_1150 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1149) connect Queue10_UInt8_29.io.enq.bits, _T_1150 node _T_1151 = eq(UInt<5>(0h1e), idx_11) when _T_1151 : node _T_1152 = shl(UInt<4>(0hb), 3) node _T_1153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1152) connect Queue10_UInt8_30.io.enq.bits, _T_1153 node _T_1154 = eq(UInt<5>(0h1f), idx_11) when _T_1154 : node _T_1155 = shl(UInt<4>(0hb), 3) node _T_1156 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1155) connect Queue10_UInt8_31.io.enq.bits, _T_1156 node _idx_T_12 = add(write_start_index, UInt<4>(0hc)) node idx_12 = rem(_idx_T_12, UInt<6>(0h20)) node _T_1157 = eq(UInt<1>(0h0), idx_12) when _T_1157 : node _T_1158 = shl(UInt<4>(0hc), 3) node _T_1159 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1158) connect Queue10_UInt8.io.enq.bits, _T_1159 node _T_1160 = eq(UInt<1>(0h1), idx_12) when _T_1160 : node _T_1161 = shl(UInt<4>(0hc), 3) node _T_1162 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1161) connect Queue10_UInt8_1.io.enq.bits, _T_1162 node _T_1163 = eq(UInt<2>(0h2), idx_12) when _T_1163 : node _T_1164 = shl(UInt<4>(0hc), 3) node _T_1165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1164) connect Queue10_UInt8_2.io.enq.bits, _T_1165 node _T_1166 = eq(UInt<2>(0h3), idx_12) when _T_1166 : node _T_1167 = shl(UInt<4>(0hc), 3) node _T_1168 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1167) connect Queue10_UInt8_3.io.enq.bits, _T_1168 node _T_1169 = eq(UInt<3>(0h4), idx_12) when _T_1169 : node _T_1170 = shl(UInt<4>(0hc), 3) node _T_1171 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1170) connect Queue10_UInt8_4.io.enq.bits, _T_1171 node _T_1172 = eq(UInt<3>(0h5), idx_12) when _T_1172 : node _T_1173 = shl(UInt<4>(0hc), 3) node _T_1174 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1173) connect Queue10_UInt8_5.io.enq.bits, _T_1174 node _T_1175 = eq(UInt<3>(0h6), idx_12) when _T_1175 : node _T_1176 = shl(UInt<4>(0hc), 3) node _T_1177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1176) connect Queue10_UInt8_6.io.enq.bits, _T_1177 node _T_1178 = eq(UInt<3>(0h7), idx_12) when _T_1178 : node _T_1179 = shl(UInt<4>(0hc), 3) node _T_1180 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1179) connect Queue10_UInt8_7.io.enq.bits, _T_1180 node _T_1181 = eq(UInt<4>(0h8), idx_12) when _T_1181 : node _T_1182 = shl(UInt<4>(0hc), 3) node _T_1183 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1182) connect Queue10_UInt8_8.io.enq.bits, _T_1183 node _T_1184 = eq(UInt<4>(0h9), idx_12) when _T_1184 : node _T_1185 = shl(UInt<4>(0hc), 3) node _T_1186 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1185) connect Queue10_UInt8_9.io.enq.bits, _T_1186 node _T_1187 = eq(UInt<4>(0ha), idx_12) when _T_1187 : node _T_1188 = shl(UInt<4>(0hc), 3) node _T_1189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1188) connect Queue10_UInt8_10.io.enq.bits, _T_1189 node _T_1190 = eq(UInt<4>(0hb), idx_12) when _T_1190 : node _T_1191 = shl(UInt<4>(0hc), 3) node _T_1192 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1191) connect Queue10_UInt8_11.io.enq.bits, _T_1192 node _T_1193 = eq(UInt<4>(0hc), idx_12) when _T_1193 : node _T_1194 = shl(UInt<4>(0hc), 3) node _T_1195 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1194) connect Queue10_UInt8_12.io.enq.bits, _T_1195 node _T_1196 = eq(UInt<4>(0hd), idx_12) when _T_1196 : node _T_1197 = shl(UInt<4>(0hc), 3) node _T_1198 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1197) connect Queue10_UInt8_13.io.enq.bits, _T_1198 node _T_1199 = eq(UInt<4>(0he), idx_12) when _T_1199 : node _T_1200 = shl(UInt<4>(0hc), 3) node _T_1201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1200) connect Queue10_UInt8_14.io.enq.bits, _T_1201 node _T_1202 = eq(UInt<4>(0hf), idx_12) when _T_1202 : node _T_1203 = shl(UInt<4>(0hc), 3) node _T_1204 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1203) connect Queue10_UInt8_15.io.enq.bits, _T_1204 node _T_1205 = eq(UInt<5>(0h10), idx_12) when _T_1205 : node _T_1206 = shl(UInt<4>(0hc), 3) node _T_1207 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1206) connect Queue10_UInt8_16.io.enq.bits, _T_1207 node _T_1208 = eq(UInt<5>(0h11), idx_12) when _T_1208 : node _T_1209 = shl(UInt<4>(0hc), 3) node _T_1210 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1209) connect Queue10_UInt8_17.io.enq.bits, _T_1210 node _T_1211 = eq(UInt<5>(0h12), idx_12) when _T_1211 : node _T_1212 = shl(UInt<4>(0hc), 3) node _T_1213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1212) connect Queue10_UInt8_18.io.enq.bits, _T_1213 node _T_1214 = eq(UInt<5>(0h13), idx_12) when _T_1214 : node _T_1215 = shl(UInt<4>(0hc), 3) node _T_1216 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1215) connect Queue10_UInt8_19.io.enq.bits, _T_1216 node _T_1217 = eq(UInt<5>(0h14), idx_12) when _T_1217 : node _T_1218 = shl(UInt<4>(0hc), 3) node _T_1219 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1218) connect Queue10_UInt8_20.io.enq.bits, _T_1219 node _T_1220 = eq(UInt<5>(0h15), idx_12) when _T_1220 : node _T_1221 = shl(UInt<4>(0hc), 3) node _T_1222 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1221) connect Queue10_UInt8_21.io.enq.bits, _T_1222 node _T_1223 = eq(UInt<5>(0h16), idx_12) when _T_1223 : node _T_1224 = shl(UInt<4>(0hc), 3) node _T_1225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1224) connect Queue10_UInt8_22.io.enq.bits, _T_1225 node _T_1226 = eq(UInt<5>(0h17), idx_12) when _T_1226 : node _T_1227 = shl(UInt<4>(0hc), 3) node _T_1228 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1227) connect Queue10_UInt8_23.io.enq.bits, _T_1228 node _T_1229 = eq(UInt<5>(0h18), idx_12) when _T_1229 : node _T_1230 = shl(UInt<4>(0hc), 3) node _T_1231 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1230) connect Queue10_UInt8_24.io.enq.bits, _T_1231 node _T_1232 = eq(UInt<5>(0h19), idx_12) when _T_1232 : node _T_1233 = shl(UInt<4>(0hc), 3) node _T_1234 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1233) connect Queue10_UInt8_25.io.enq.bits, _T_1234 node _T_1235 = eq(UInt<5>(0h1a), idx_12) when _T_1235 : node _T_1236 = shl(UInt<4>(0hc), 3) node _T_1237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1236) connect Queue10_UInt8_26.io.enq.bits, _T_1237 node _T_1238 = eq(UInt<5>(0h1b), idx_12) when _T_1238 : node _T_1239 = shl(UInt<4>(0hc), 3) node _T_1240 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1239) connect Queue10_UInt8_27.io.enq.bits, _T_1240 node _T_1241 = eq(UInt<5>(0h1c), idx_12) when _T_1241 : node _T_1242 = shl(UInt<4>(0hc), 3) node _T_1243 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1242) connect Queue10_UInt8_28.io.enq.bits, _T_1243 node _T_1244 = eq(UInt<5>(0h1d), idx_12) when _T_1244 : node _T_1245 = shl(UInt<4>(0hc), 3) node _T_1246 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1245) connect Queue10_UInt8_29.io.enq.bits, _T_1246 node _T_1247 = eq(UInt<5>(0h1e), idx_12) when _T_1247 : node _T_1248 = shl(UInt<4>(0hc), 3) node _T_1249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1248) connect Queue10_UInt8_30.io.enq.bits, _T_1249 node _T_1250 = eq(UInt<5>(0h1f), idx_12) when _T_1250 : node _T_1251 = shl(UInt<4>(0hc), 3) node _T_1252 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1251) connect Queue10_UInt8_31.io.enq.bits, _T_1252 node _idx_T_13 = add(write_start_index, UInt<4>(0hd)) node idx_13 = rem(_idx_T_13, UInt<6>(0h20)) node _T_1253 = eq(UInt<1>(0h0), idx_13) when _T_1253 : node _T_1254 = shl(UInt<4>(0hd), 3) node _T_1255 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1254) connect Queue10_UInt8.io.enq.bits, _T_1255 node _T_1256 = eq(UInt<1>(0h1), idx_13) when _T_1256 : node _T_1257 = shl(UInt<4>(0hd), 3) node _T_1258 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1257) connect Queue10_UInt8_1.io.enq.bits, _T_1258 node _T_1259 = eq(UInt<2>(0h2), idx_13) when _T_1259 : node _T_1260 = shl(UInt<4>(0hd), 3) node _T_1261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1260) connect Queue10_UInt8_2.io.enq.bits, _T_1261 node _T_1262 = eq(UInt<2>(0h3), idx_13) when _T_1262 : node _T_1263 = shl(UInt<4>(0hd), 3) node _T_1264 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1263) connect Queue10_UInt8_3.io.enq.bits, _T_1264 node _T_1265 = eq(UInt<3>(0h4), idx_13) when _T_1265 : node _T_1266 = shl(UInt<4>(0hd), 3) node _T_1267 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1266) connect Queue10_UInt8_4.io.enq.bits, _T_1267 node _T_1268 = eq(UInt<3>(0h5), idx_13) when _T_1268 : node _T_1269 = shl(UInt<4>(0hd), 3) node _T_1270 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1269) connect Queue10_UInt8_5.io.enq.bits, _T_1270 node _T_1271 = eq(UInt<3>(0h6), idx_13) when _T_1271 : node _T_1272 = shl(UInt<4>(0hd), 3) node _T_1273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1272) connect Queue10_UInt8_6.io.enq.bits, _T_1273 node _T_1274 = eq(UInt<3>(0h7), idx_13) when _T_1274 : node _T_1275 = shl(UInt<4>(0hd), 3) node _T_1276 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1275) connect Queue10_UInt8_7.io.enq.bits, _T_1276 node _T_1277 = eq(UInt<4>(0h8), idx_13) when _T_1277 : node _T_1278 = shl(UInt<4>(0hd), 3) node _T_1279 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1278) connect Queue10_UInt8_8.io.enq.bits, _T_1279 node _T_1280 = eq(UInt<4>(0h9), idx_13) when _T_1280 : node _T_1281 = shl(UInt<4>(0hd), 3) node _T_1282 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1281) connect Queue10_UInt8_9.io.enq.bits, _T_1282 node _T_1283 = eq(UInt<4>(0ha), idx_13) when _T_1283 : node _T_1284 = shl(UInt<4>(0hd), 3) node _T_1285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1284) connect Queue10_UInt8_10.io.enq.bits, _T_1285 node _T_1286 = eq(UInt<4>(0hb), idx_13) when _T_1286 : node _T_1287 = shl(UInt<4>(0hd), 3) node _T_1288 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1287) connect Queue10_UInt8_11.io.enq.bits, _T_1288 node _T_1289 = eq(UInt<4>(0hc), idx_13) when _T_1289 : node _T_1290 = shl(UInt<4>(0hd), 3) node _T_1291 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1290) connect Queue10_UInt8_12.io.enq.bits, _T_1291 node _T_1292 = eq(UInt<4>(0hd), idx_13) when _T_1292 : node _T_1293 = shl(UInt<4>(0hd), 3) node _T_1294 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1293) connect Queue10_UInt8_13.io.enq.bits, _T_1294 node _T_1295 = eq(UInt<4>(0he), idx_13) when _T_1295 : node _T_1296 = shl(UInt<4>(0hd), 3) node _T_1297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1296) connect Queue10_UInt8_14.io.enq.bits, _T_1297 node _T_1298 = eq(UInt<4>(0hf), idx_13) when _T_1298 : node _T_1299 = shl(UInt<4>(0hd), 3) node _T_1300 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1299) connect Queue10_UInt8_15.io.enq.bits, _T_1300 node _T_1301 = eq(UInt<5>(0h10), idx_13) when _T_1301 : node _T_1302 = shl(UInt<4>(0hd), 3) node _T_1303 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1302) connect Queue10_UInt8_16.io.enq.bits, _T_1303 node _T_1304 = eq(UInt<5>(0h11), idx_13) when _T_1304 : node _T_1305 = shl(UInt<4>(0hd), 3) node _T_1306 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1305) connect Queue10_UInt8_17.io.enq.bits, _T_1306 node _T_1307 = eq(UInt<5>(0h12), idx_13) when _T_1307 : node _T_1308 = shl(UInt<4>(0hd), 3) node _T_1309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1308) connect Queue10_UInt8_18.io.enq.bits, _T_1309 node _T_1310 = eq(UInt<5>(0h13), idx_13) when _T_1310 : node _T_1311 = shl(UInt<4>(0hd), 3) node _T_1312 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1311) connect Queue10_UInt8_19.io.enq.bits, _T_1312 node _T_1313 = eq(UInt<5>(0h14), idx_13) when _T_1313 : node _T_1314 = shl(UInt<4>(0hd), 3) node _T_1315 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1314) connect Queue10_UInt8_20.io.enq.bits, _T_1315 node _T_1316 = eq(UInt<5>(0h15), idx_13) when _T_1316 : node _T_1317 = shl(UInt<4>(0hd), 3) node _T_1318 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1317) connect Queue10_UInt8_21.io.enq.bits, _T_1318 node _T_1319 = eq(UInt<5>(0h16), idx_13) when _T_1319 : node _T_1320 = shl(UInt<4>(0hd), 3) node _T_1321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1320) connect Queue10_UInt8_22.io.enq.bits, _T_1321 node _T_1322 = eq(UInt<5>(0h17), idx_13) when _T_1322 : node _T_1323 = shl(UInt<4>(0hd), 3) node _T_1324 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1323) connect Queue10_UInt8_23.io.enq.bits, _T_1324 node _T_1325 = eq(UInt<5>(0h18), idx_13) when _T_1325 : node _T_1326 = shl(UInt<4>(0hd), 3) node _T_1327 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1326) connect Queue10_UInt8_24.io.enq.bits, _T_1327 node _T_1328 = eq(UInt<5>(0h19), idx_13) when _T_1328 : node _T_1329 = shl(UInt<4>(0hd), 3) node _T_1330 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1329) connect Queue10_UInt8_25.io.enq.bits, _T_1330 node _T_1331 = eq(UInt<5>(0h1a), idx_13) when _T_1331 : node _T_1332 = shl(UInt<4>(0hd), 3) node _T_1333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1332) connect Queue10_UInt8_26.io.enq.bits, _T_1333 node _T_1334 = eq(UInt<5>(0h1b), idx_13) when _T_1334 : node _T_1335 = shl(UInt<4>(0hd), 3) node _T_1336 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1335) connect Queue10_UInt8_27.io.enq.bits, _T_1336 node _T_1337 = eq(UInt<5>(0h1c), idx_13) when _T_1337 : node _T_1338 = shl(UInt<4>(0hd), 3) node _T_1339 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1338) connect Queue10_UInt8_28.io.enq.bits, _T_1339 node _T_1340 = eq(UInt<5>(0h1d), idx_13) when _T_1340 : node _T_1341 = shl(UInt<4>(0hd), 3) node _T_1342 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1341) connect Queue10_UInt8_29.io.enq.bits, _T_1342 node _T_1343 = eq(UInt<5>(0h1e), idx_13) when _T_1343 : node _T_1344 = shl(UInt<4>(0hd), 3) node _T_1345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1344) connect Queue10_UInt8_30.io.enq.bits, _T_1345 node _T_1346 = eq(UInt<5>(0h1f), idx_13) when _T_1346 : node _T_1347 = shl(UInt<4>(0hd), 3) node _T_1348 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1347) connect Queue10_UInt8_31.io.enq.bits, _T_1348 node _idx_T_14 = add(write_start_index, UInt<4>(0he)) node idx_14 = rem(_idx_T_14, UInt<6>(0h20)) node _T_1349 = eq(UInt<1>(0h0), idx_14) when _T_1349 : node _T_1350 = shl(UInt<4>(0he), 3) node _T_1351 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1350) connect Queue10_UInt8.io.enq.bits, _T_1351 node _T_1352 = eq(UInt<1>(0h1), idx_14) when _T_1352 : node _T_1353 = shl(UInt<4>(0he), 3) node _T_1354 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1353) connect Queue10_UInt8_1.io.enq.bits, _T_1354 node _T_1355 = eq(UInt<2>(0h2), idx_14) when _T_1355 : node _T_1356 = shl(UInt<4>(0he), 3) node _T_1357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1356) connect Queue10_UInt8_2.io.enq.bits, _T_1357 node _T_1358 = eq(UInt<2>(0h3), idx_14) when _T_1358 : node _T_1359 = shl(UInt<4>(0he), 3) node _T_1360 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1359) connect Queue10_UInt8_3.io.enq.bits, _T_1360 node _T_1361 = eq(UInt<3>(0h4), idx_14) when _T_1361 : node _T_1362 = shl(UInt<4>(0he), 3) node _T_1363 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1362) connect Queue10_UInt8_4.io.enq.bits, _T_1363 node _T_1364 = eq(UInt<3>(0h5), idx_14) when _T_1364 : node _T_1365 = shl(UInt<4>(0he), 3) node _T_1366 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1365) connect Queue10_UInt8_5.io.enq.bits, _T_1366 node _T_1367 = eq(UInt<3>(0h6), idx_14) when _T_1367 : node _T_1368 = shl(UInt<4>(0he), 3) node _T_1369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1368) connect Queue10_UInt8_6.io.enq.bits, _T_1369 node _T_1370 = eq(UInt<3>(0h7), idx_14) when _T_1370 : node _T_1371 = shl(UInt<4>(0he), 3) node _T_1372 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1371) connect Queue10_UInt8_7.io.enq.bits, _T_1372 node _T_1373 = eq(UInt<4>(0h8), idx_14) when _T_1373 : node _T_1374 = shl(UInt<4>(0he), 3) node _T_1375 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1374) connect Queue10_UInt8_8.io.enq.bits, _T_1375 node _T_1376 = eq(UInt<4>(0h9), idx_14) when _T_1376 : node _T_1377 = shl(UInt<4>(0he), 3) node _T_1378 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1377) connect Queue10_UInt8_9.io.enq.bits, _T_1378 node _T_1379 = eq(UInt<4>(0ha), idx_14) when _T_1379 : node _T_1380 = shl(UInt<4>(0he), 3) node _T_1381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1380) connect Queue10_UInt8_10.io.enq.bits, _T_1381 node _T_1382 = eq(UInt<4>(0hb), idx_14) when _T_1382 : node _T_1383 = shl(UInt<4>(0he), 3) node _T_1384 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1383) connect Queue10_UInt8_11.io.enq.bits, _T_1384 node _T_1385 = eq(UInt<4>(0hc), idx_14) when _T_1385 : node _T_1386 = shl(UInt<4>(0he), 3) node _T_1387 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1386) connect Queue10_UInt8_12.io.enq.bits, _T_1387 node _T_1388 = eq(UInt<4>(0hd), idx_14) when _T_1388 : node _T_1389 = shl(UInt<4>(0he), 3) node _T_1390 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1389) connect Queue10_UInt8_13.io.enq.bits, _T_1390 node _T_1391 = eq(UInt<4>(0he), idx_14) when _T_1391 : node _T_1392 = shl(UInt<4>(0he), 3) node _T_1393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1392) connect Queue10_UInt8_14.io.enq.bits, _T_1393 node _T_1394 = eq(UInt<4>(0hf), idx_14) when _T_1394 : node _T_1395 = shl(UInt<4>(0he), 3) node _T_1396 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1395) connect Queue10_UInt8_15.io.enq.bits, _T_1396 node _T_1397 = eq(UInt<5>(0h10), idx_14) when _T_1397 : node _T_1398 = shl(UInt<4>(0he), 3) node _T_1399 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1398) connect Queue10_UInt8_16.io.enq.bits, _T_1399 node _T_1400 = eq(UInt<5>(0h11), idx_14) when _T_1400 : node _T_1401 = shl(UInt<4>(0he), 3) node _T_1402 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1401) connect Queue10_UInt8_17.io.enq.bits, _T_1402 node _T_1403 = eq(UInt<5>(0h12), idx_14) when _T_1403 : node _T_1404 = shl(UInt<4>(0he), 3) node _T_1405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1404) connect Queue10_UInt8_18.io.enq.bits, _T_1405 node _T_1406 = eq(UInt<5>(0h13), idx_14) when _T_1406 : node _T_1407 = shl(UInt<4>(0he), 3) node _T_1408 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1407) connect Queue10_UInt8_19.io.enq.bits, _T_1408 node _T_1409 = eq(UInt<5>(0h14), idx_14) when _T_1409 : node _T_1410 = shl(UInt<4>(0he), 3) node _T_1411 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1410) connect Queue10_UInt8_20.io.enq.bits, _T_1411 node _T_1412 = eq(UInt<5>(0h15), idx_14) when _T_1412 : node _T_1413 = shl(UInt<4>(0he), 3) node _T_1414 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1413) connect Queue10_UInt8_21.io.enq.bits, _T_1414 node _T_1415 = eq(UInt<5>(0h16), idx_14) when _T_1415 : node _T_1416 = shl(UInt<4>(0he), 3) node _T_1417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1416) connect Queue10_UInt8_22.io.enq.bits, _T_1417 node _T_1418 = eq(UInt<5>(0h17), idx_14) when _T_1418 : node _T_1419 = shl(UInt<4>(0he), 3) node _T_1420 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1419) connect Queue10_UInt8_23.io.enq.bits, _T_1420 node _T_1421 = eq(UInt<5>(0h18), idx_14) when _T_1421 : node _T_1422 = shl(UInt<4>(0he), 3) node _T_1423 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1422) connect Queue10_UInt8_24.io.enq.bits, _T_1423 node _T_1424 = eq(UInt<5>(0h19), idx_14) when _T_1424 : node _T_1425 = shl(UInt<4>(0he), 3) node _T_1426 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1425) connect Queue10_UInt8_25.io.enq.bits, _T_1426 node _T_1427 = eq(UInt<5>(0h1a), idx_14) when _T_1427 : node _T_1428 = shl(UInt<4>(0he), 3) node _T_1429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1428) connect Queue10_UInt8_26.io.enq.bits, _T_1429 node _T_1430 = eq(UInt<5>(0h1b), idx_14) when _T_1430 : node _T_1431 = shl(UInt<4>(0he), 3) node _T_1432 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1431) connect Queue10_UInt8_27.io.enq.bits, _T_1432 node _T_1433 = eq(UInt<5>(0h1c), idx_14) when _T_1433 : node _T_1434 = shl(UInt<4>(0he), 3) node _T_1435 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1434) connect Queue10_UInt8_28.io.enq.bits, _T_1435 node _T_1436 = eq(UInt<5>(0h1d), idx_14) when _T_1436 : node _T_1437 = shl(UInt<4>(0he), 3) node _T_1438 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1437) connect Queue10_UInt8_29.io.enq.bits, _T_1438 node _T_1439 = eq(UInt<5>(0h1e), idx_14) when _T_1439 : node _T_1440 = shl(UInt<4>(0he), 3) node _T_1441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1440) connect Queue10_UInt8_30.io.enq.bits, _T_1441 node _T_1442 = eq(UInt<5>(0h1f), idx_14) when _T_1442 : node _T_1443 = shl(UInt<4>(0he), 3) node _T_1444 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1443) connect Queue10_UInt8_31.io.enq.bits, _T_1444 node _idx_T_15 = add(write_start_index, UInt<4>(0hf)) node idx_15 = rem(_idx_T_15, UInt<6>(0h20)) node _T_1445 = eq(UInt<1>(0h0), idx_15) when _T_1445 : node _T_1446 = shl(UInt<4>(0hf), 3) node _T_1447 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1446) connect Queue10_UInt8.io.enq.bits, _T_1447 node _T_1448 = eq(UInt<1>(0h1), idx_15) when _T_1448 : node _T_1449 = shl(UInt<4>(0hf), 3) node _T_1450 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1449) connect Queue10_UInt8_1.io.enq.bits, _T_1450 node _T_1451 = eq(UInt<2>(0h2), idx_15) when _T_1451 : node _T_1452 = shl(UInt<4>(0hf), 3) node _T_1453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1452) connect Queue10_UInt8_2.io.enq.bits, _T_1453 node _T_1454 = eq(UInt<2>(0h3), idx_15) when _T_1454 : node _T_1455 = shl(UInt<4>(0hf), 3) node _T_1456 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1455) connect Queue10_UInt8_3.io.enq.bits, _T_1456 node _T_1457 = eq(UInt<3>(0h4), idx_15) when _T_1457 : node _T_1458 = shl(UInt<4>(0hf), 3) node _T_1459 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1458) connect Queue10_UInt8_4.io.enq.bits, _T_1459 node _T_1460 = eq(UInt<3>(0h5), idx_15) when _T_1460 : node _T_1461 = shl(UInt<4>(0hf), 3) node _T_1462 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1461) connect Queue10_UInt8_5.io.enq.bits, _T_1462 node _T_1463 = eq(UInt<3>(0h6), idx_15) when _T_1463 : node _T_1464 = shl(UInt<4>(0hf), 3) node _T_1465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1464) connect Queue10_UInt8_6.io.enq.bits, _T_1465 node _T_1466 = eq(UInt<3>(0h7), idx_15) when _T_1466 : node _T_1467 = shl(UInt<4>(0hf), 3) node _T_1468 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1467) connect Queue10_UInt8_7.io.enq.bits, _T_1468 node _T_1469 = eq(UInt<4>(0h8), idx_15) when _T_1469 : node _T_1470 = shl(UInt<4>(0hf), 3) node _T_1471 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1470) connect Queue10_UInt8_8.io.enq.bits, _T_1471 node _T_1472 = eq(UInt<4>(0h9), idx_15) when _T_1472 : node _T_1473 = shl(UInt<4>(0hf), 3) node _T_1474 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1473) connect Queue10_UInt8_9.io.enq.bits, _T_1474 node _T_1475 = eq(UInt<4>(0ha), idx_15) when _T_1475 : node _T_1476 = shl(UInt<4>(0hf), 3) node _T_1477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1476) connect Queue10_UInt8_10.io.enq.bits, _T_1477 node _T_1478 = eq(UInt<4>(0hb), idx_15) when _T_1478 : node _T_1479 = shl(UInt<4>(0hf), 3) node _T_1480 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1479) connect Queue10_UInt8_11.io.enq.bits, _T_1480 node _T_1481 = eq(UInt<4>(0hc), idx_15) when _T_1481 : node _T_1482 = shl(UInt<4>(0hf), 3) node _T_1483 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1482) connect Queue10_UInt8_12.io.enq.bits, _T_1483 node _T_1484 = eq(UInt<4>(0hd), idx_15) when _T_1484 : node _T_1485 = shl(UInt<4>(0hf), 3) node _T_1486 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1485) connect Queue10_UInt8_13.io.enq.bits, _T_1486 node _T_1487 = eq(UInt<4>(0he), idx_15) when _T_1487 : node _T_1488 = shl(UInt<4>(0hf), 3) node _T_1489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1488) connect Queue10_UInt8_14.io.enq.bits, _T_1489 node _T_1490 = eq(UInt<4>(0hf), idx_15) when _T_1490 : node _T_1491 = shl(UInt<4>(0hf), 3) node _T_1492 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1491) connect Queue10_UInt8_15.io.enq.bits, _T_1492 node _T_1493 = eq(UInt<5>(0h10), idx_15) when _T_1493 : node _T_1494 = shl(UInt<4>(0hf), 3) node _T_1495 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1494) connect Queue10_UInt8_16.io.enq.bits, _T_1495 node _T_1496 = eq(UInt<5>(0h11), idx_15) when _T_1496 : node _T_1497 = shl(UInt<4>(0hf), 3) node _T_1498 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1497) connect Queue10_UInt8_17.io.enq.bits, _T_1498 node _T_1499 = eq(UInt<5>(0h12), idx_15) when _T_1499 : node _T_1500 = shl(UInt<4>(0hf), 3) node _T_1501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1500) connect Queue10_UInt8_18.io.enq.bits, _T_1501 node _T_1502 = eq(UInt<5>(0h13), idx_15) when _T_1502 : node _T_1503 = shl(UInt<4>(0hf), 3) node _T_1504 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1503) connect Queue10_UInt8_19.io.enq.bits, _T_1504 node _T_1505 = eq(UInt<5>(0h14), idx_15) when _T_1505 : node _T_1506 = shl(UInt<4>(0hf), 3) node _T_1507 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1506) connect Queue10_UInt8_20.io.enq.bits, _T_1507 node _T_1508 = eq(UInt<5>(0h15), idx_15) when _T_1508 : node _T_1509 = shl(UInt<4>(0hf), 3) node _T_1510 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1509) connect Queue10_UInt8_21.io.enq.bits, _T_1510 node _T_1511 = eq(UInt<5>(0h16), idx_15) when _T_1511 : node _T_1512 = shl(UInt<4>(0hf), 3) node _T_1513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1512) connect Queue10_UInt8_22.io.enq.bits, _T_1513 node _T_1514 = eq(UInt<5>(0h17), idx_15) when _T_1514 : node _T_1515 = shl(UInt<4>(0hf), 3) node _T_1516 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1515) connect Queue10_UInt8_23.io.enq.bits, _T_1516 node _T_1517 = eq(UInt<5>(0h18), idx_15) when _T_1517 : node _T_1518 = shl(UInt<4>(0hf), 3) node _T_1519 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1518) connect Queue10_UInt8_24.io.enq.bits, _T_1519 node _T_1520 = eq(UInt<5>(0h19), idx_15) when _T_1520 : node _T_1521 = shl(UInt<4>(0hf), 3) node _T_1522 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1521) connect Queue10_UInt8_25.io.enq.bits, _T_1522 node _T_1523 = eq(UInt<5>(0h1a), idx_15) when _T_1523 : node _T_1524 = shl(UInt<4>(0hf), 3) node _T_1525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1524) connect Queue10_UInt8_26.io.enq.bits, _T_1525 node _T_1526 = eq(UInt<5>(0h1b), idx_15) when _T_1526 : node _T_1527 = shl(UInt<4>(0hf), 3) node _T_1528 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1527) connect Queue10_UInt8_27.io.enq.bits, _T_1528 node _T_1529 = eq(UInt<5>(0h1c), idx_15) when _T_1529 : node _T_1530 = shl(UInt<4>(0hf), 3) node _T_1531 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1530) connect Queue10_UInt8_28.io.enq.bits, _T_1531 node _T_1532 = eq(UInt<5>(0h1d), idx_15) when _T_1532 : node _T_1533 = shl(UInt<4>(0hf), 3) node _T_1534 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1533) connect Queue10_UInt8_29.io.enq.bits, _T_1534 node _T_1535 = eq(UInt<5>(0h1e), idx_15) when _T_1535 : node _T_1536 = shl(UInt<4>(0hf), 3) node _T_1537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1536) connect Queue10_UInt8_30.io.enq.bits, _T_1537 node _T_1538 = eq(UInt<5>(0h1f), idx_15) when _T_1538 : node _T_1539 = shl(UInt<4>(0hf), 3) node _T_1540 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1539) connect Queue10_UInt8_31.io.enq.bits, _T_1540 node _idx_T_16 = add(write_start_index, UInt<5>(0h10)) node idx_16 = rem(_idx_T_16, UInt<6>(0h20)) node _T_1541 = eq(UInt<1>(0h0), idx_16) when _T_1541 : node _T_1542 = shl(UInt<5>(0h10), 3) node _T_1543 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1542) connect Queue10_UInt8.io.enq.bits, _T_1543 node _T_1544 = eq(UInt<1>(0h1), idx_16) when _T_1544 : node _T_1545 = shl(UInt<5>(0h10), 3) node _T_1546 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1545) connect Queue10_UInt8_1.io.enq.bits, _T_1546 node _T_1547 = eq(UInt<2>(0h2), idx_16) when _T_1547 : node _T_1548 = shl(UInt<5>(0h10), 3) node _T_1549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1548) connect Queue10_UInt8_2.io.enq.bits, _T_1549 node _T_1550 = eq(UInt<2>(0h3), idx_16) when _T_1550 : node _T_1551 = shl(UInt<5>(0h10), 3) node _T_1552 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1551) connect Queue10_UInt8_3.io.enq.bits, _T_1552 node _T_1553 = eq(UInt<3>(0h4), idx_16) when _T_1553 : node _T_1554 = shl(UInt<5>(0h10), 3) node _T_1555 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1554) connect Queue10_UInt8_4.io.enq.bits, _T_1555 node _T_1556 = eq(UInt<3>(0h5), idx_16) when _T_1556 : node _T_1557 = shl(UInt<5>(0h10), 3) node _T_1558 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1557) connect Queue10_UInt8_5.io.enq.bits, _T_1558 node _T_1559 = eq(UInt<3>(0h6), idx_16) when _T_1559 : node _T_1560 = shl(UInt<5>(0h10), 3) node _T_1561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1560) connect Queue10_UInt8_6.io.enq.bits, _T_1561 node _T_1562 = eq(UInt<3>(0h7), idx_16) when _T_1562 : node _T_1563 = shl(UInt<5>(0h10), 3) node _T_1564 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1563) connect Queue10_UInt8_7.io.enq.bits, _T_1564 node _T_1565 = eq(UInt<4>(0h8), idx_16) when _T_1565 : node _T_1566 = shl(UInt<5>(0h10), 3) node _T_1567 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1566) connect Queue10_UInt8_8.io.enq.bits, _T_1567 node _T_1568 = eq(UInt<4>(0h9), idx_16) when _T_1568 : node _T_1569 = shl(UInt<5>(0h10), 3) node _T_1570 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1569) connect Queue10_UInt8_9.io.enq.bits, _T_1570 node _T_1571 = eq(UInt<4>(0ha), idx_16) when _T_1571 : node _T_1572 = shl(UInt<5>(0h10), 3) node _T_1573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1572) connect Queue10_UInt8_10.io.enq.bits, _T_1573 node _T_1574 = eq(UInt<4>(0hb), idx_16) when _T_1574 : node _T_1575 = shl(UInt<5>(0h10), 3) node _T_1576 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1575) connect Queue10_UInt8_11.io.enq.bits, _T_1576 node _T_1577 = eq(UInt<4>(0hc), idx_16) when _T_1577 : node _T_1578 = shl(UInt<5>(0h10), 3) node _T_1579 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1578) connect Queue10_UInt8_12.io.enq.bits, _T_1579 node _T_1580 = eq(UInt<4>(0hd), idx_16) when _T_1580 : node _T_1581 = shl(UInt<5>(0h10), 3) node _T_1582 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1581) connect Queue10_UInt8_13.io.enq.bits, _T_1582 node _T_1583 = eq(UInt<4>(0he), idx_16) when _T_1583 : node _T_1584 = shl(UInt<5>(0h10), 3) node _T_1585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1584) connect Queue10_UInt8_14.io.enq.bits, _T_1585 node _T_1586 = eq(UInt<4>(0hf), idx_16) when _T_1586 : node _T_1587 = shl(UInt<5>(0h10), 3) node _T_1588 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1587) connect Queue10_UInt8_15.io.enq.bits, _T_1588 node _T_1589 = eq(UInt<5>(0h10), idx_16) when _T_1589 : node _T_1590 = shl(UInt<5>(0h10), 3) node _T_1591 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1590) connect Queue10_UInt8_16.io.enq.bits, _T_1591 node _T_1592 = eq(UInt<5>(0h11), idx_16) when _T_1592 : node _T_1593 = shl(UInt<5>(0h10), 3) node _T_1594 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1593) connect Queue10_UInt8_17.io.enq.bits, _T_1594 node _T_1595 = eq(UInt<5>(0h12), idx_16) when _T_1595 : node _T_1596 = shl(UInt<5>(0h10), 3) node _T_1597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1596) connect Queue10_UInt8_18.io.enq.bits, _T_1597 node _T_1598 = eq(UInt<5>(0h13), idx_16) when _T_1598 : node _T_1599 = shl(UInt<5>(0h10), 3) node _T_1600 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1599) connect Queue10_UInt8_19.io.enq.bits, _T_1600 node _T_1601 = eq(UInt<5>(0h14), idx_16) when _T_1601 : node _T_1602 = shl(UInt<5>(0h10), 3) node _T_1603 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1602) connect Queue10_UInt8_20.io.enq.bits, _T_1603 node _T_1604 = eq(UInt<5>(0h15), idx_16) when _T_1604 : node _T_1605 = shl(UInt<5>(0h10), 3) node _T_1606 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1605) connect Queue10_UInt8_21.io.enq.bits, _T_1606 node _T_1607 = eq(UInt<5>(0h16), idx_16) when _T_1607 : node _T_1608 = shl(UInt<5>(0h10), 3) node _T_1609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1608) connect Queue10_UInt8_22.io.enq.bits, _T_1609 node _T_1610 = eq(UInt<5>(0h17), idx_16) when _T_1610 : node _T_1611 = shl(UInt<5>(0h10), 3) node _T_1612 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1611) connect Queue10_UInt8_23.io.enq.bits, _T_1612 node _T_1613 = eq(UInt<5>(0h18), idx_16) when _T_1613 : node _T_1614 = shl(UInt<5>(0h10), 3) node _T_1615 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1614) connect Queue10_UInt8_24.io.enq.bits, _T_1615 node _T_1616 = eq(UInt<5>(0h19), idx_16) when _T_1616 : node _T_1617 = shl(UInt<5>(0h10), 3) node _T_1618 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1617) connect Queue10_UInt8_25.io.enq.bits, _T_1618 node _T_1619 = eq(UInt<5>(0h1a), idx_16) when _T_1619 : node _T_1620 = shl(UInt<5>(0h10), 3) node _T_1621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1620) connect Queue10_UInt8_26.io.enq.bits, _T_1621 node _T_1622 = eq(UInt<5>(0h1b), idx_16) when _T_1622 : node _T_1623 = shl(UInt<5>(0h10), 3) node _T_1624 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1623) connect Queue10_UInt8_27.io.enq.bits, _T_1624 node _T_1625 = eq(UInt<5>(0h1c), idx_16) when _T_1625 : node _T_1626 = shl(UInt<5>(0h10), 3) node _T_1627 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1626) connect Queue10_UInt8_28.io.enq.bits, _T_1627 node _T_1628 = eq(UInt<5>(0h1d), idx_16) when _T_1628 : node _T_1629 = shl(UInt<5>(0h10), 3) node _T_1630 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1629) connect Queue10_UInt8_29.io.enq.bits, _T_1630 node _T_1631 = eq(UInt<5>(0h1e), idx_16) when _T_1631 : node _T_1632 = shl(UInt<5>(0h10), 3) node _T_1633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1632) connect Queue10_UInt8_30.io.enq.bits, _T_1633 node _T_1634 = eq(UInt<5>(0h1f), idx_16) when _T_1634 : node _T_1635 = shl(UInt<5>(0h10), 3) node _T_1636 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1635) connect Queue10_UInt8_31.io.enq.bits, _T_1636 node _idx_T_17 = add(write_start_index, UInt<5>(0h11)) node idx_17 = rem(_idx_T_17, UInt<6>(0h20)) node _T_1637 = eq(UInt<1>(0h0), idx_17) when _T_1637 : node _T_1638 = shl(UInt<5>(0h11), 3) node _T_1639 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1638) connect Queue10_UInt8.io.enq.bits, _T_1639 node _T_1640 = eq(UInt<1>(0h1), idx_17) when _T_1640 : node _T_1641 = shl(UInt<5>(0h11), 3) node _T_1642 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1641) connect Queue10_UInt8_1.io.enq.bits, _T_1642 node _T_1643 = eq(UInt<2>(0h2), idx_17) when _T_1643 : node _T_1644 = shl(UInt<5>(0h11), 3) node _T_1645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1644) connect Queue10_UInt8_2.io.enq.bits, _T_1645 node _T_1646 = eq(UInt<2>(0h3), idx_17) when _T_1646 : node _T_1647 = shl(UInt<5>(0h11), 3) node _T_1648 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1647) connect Queue10_UInt8_3.io.enq.bits, _T_1648 node _T_1649 = eq(UInt<3>(0h4), idx_17) when _T_1649 : node _T_1650 = shl(UInt<5>(0h11), 3) node _T_1651 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1650) connect Queue10_UInt8_4.io.enq.bits, _T_1651 node _T_1652 = eq(UInt<3>(0h5), idx_17) when _T_1652 : node _T_1653 = shl(UInt<5>(0h11), 3) node _T_1654 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1653) connect Queue10_UInt8_5.io.enq.bits, _T_1654 node _T_1655 = eq(UInt<3>(0h6), idx_17) when _T_1655 : node _T_1656 = shl(UInt<5>(0h11), 3) node _T_1657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1656) connect Queue10_UInt8_6.io.enq.bits, _T_1657 node _T_1658 = eq(UInt<3>(0h7), idx_17) when _T_1658 : node _T_1659 = shl(UInt<5>(0h11), 3) node _T_1660 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1659) connect Queue10_UInt8_7.io.enq.bits, _T_1660 node _T_1661 = eq(UInt<4>(0h8), idx_17) when _T_1661 : node _T_1662 = shl(UInt<5>(0h11), 3) node _T_1663 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1662) connect Queue10_UInt8_8.io.enq.bits, _T_1663 node _T_1664 = eq(UInt<4>(0h9), idx_17) when _T_1664 : node _T_1665 = shl(UInt<5>(0h11), 3) node _T_1666 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1665) connect Queue10_UInt8_9.io.enq.bits, _T_1666 node _T_1667 = eq(UInt<4>(0ha), idx_17) when _T_1667 : node _T_1668 = shl(UInt<5>(0h11), 3) node _T_1669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1668) connect Queue10_UInt8_10.io.enq.bits, _T_1669 node _T_1670 = eq(UInt<4>(0hb), idx_17) when _T_1670 : node _T_1671 = shl(UInt<5>(0h11), 3) node _T_1672 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1671) connect Queue10_UInt8_11.io.enq.bits, _T_1672 node _T_1673 = eq(UInt<4>(0hc), idx_17) when _T_1673 : node _T_1674 = shl(UInt<5>(0h11), 3) node _T_1675 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1674) connect Queue10_UInt8_12.io.enq.bits, _T_1675 node _T_1676 = eq(UInt<4>(0hd), idx_17) when _T_1676 : node _T_1677 = shl(UInt<5>(0h11), 3) node _T_1678 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1677) connect Queue10_UInt8_13.io.enq.bits, _T_1678 node _T_1679 = eq(UInt<4>(0he), idx_17) when _T_1679 : node _T_1680 = shl(UInt<5>(0h11), 3) node _T_1681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1680) connect Queue10_UInt8_14.io.enq.bits, _T_1681 node _T_1682 = eq(UInt<4>(0hf), idx_17) when _T_1682 : node _T_1683 = shl(UInt<5>(0h11), 3) node _T_1684 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1683) connect Queue10_UInt8_15.io.enq.bits, _T_1684 node _T_1685 = eq(UInt<5>(0h10), idx_17) when _T_1685 : node _T_1686 = shl(UInt<5>(0h11), 3) node _T_1687 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1686) connect Queue10_UInt8_16.io.enq.bits, _T_1687 node _T_1688 = eq(UInt<5>(0h11), idx_17) when _T_1688 : node _T_1689 = shl(UInt<5>(0h11), 3) node _T_1690 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1689) connect Queue10_UInt8_17.io.enq.bits, _T_1690 node _T_1691 = eq(UInt<5>(0h12), idx_17) when _T_1691 : node _T_1692 = shl(UInt<5>(0h11), 3) node _T_1693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1692) connect Queue10_UInt8_18.io.enq.bits, _T_1693 node _T_1694 = eq(UInt<5>(0h13), idx_17) when _T_1694 : node _T_1695 = shl(UInt<5>(0h11), 3) node _T_1696 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1695) connect Queue10_UInt8_19.io.enq.bits, _T_1696 node _T_1697 = eq(UInt<5>(0h14), idx_17) when _T_1697 : node _T_1698 = shl(UInt<5>(0h11), 3) node _T_1699 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1698) connect Queue10_UInt8_20.io.enq.bits, _T_1699 node _T_1700 = eq(UInt<5>(0h15), idx_17) when _T_1700 : node _T_1701 = shl(UInt<5>(0h11), 3) node _T_1702 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1701) connect Queue10_UInt8_21.io.enq.bits, _T_1702 node _T_1703 = eq(UInt<5>(0h16), idx_17) when _T_1703 : node _T_1704 = shl(UInt<5>(0h11), 3) node _T_1705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1704) connect Queue10_UInt8_22.io.enq.bits, _T_1705 node _T_1706 = eq(UInt<5>(0h17), idx_17) when _T_1706 : node _T_1707 = shl(UInt<5>(0h11), 3) node _T_1708 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1707) connect Queue10_UInt8_23.io.enq.bits, _T_1708 node _T_1709 = eq(UInt<5>(0h18), idx_17) when _T_1709 : node _T_1710 = shl(UInt<5>(0h11), 3) node _T_1711 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1710) connect Queue10_UInt8_24.io.enq.bits, _T_1711 node _T_1712 = eq(UInt<5>(0h19), idx_17) when _T_1712 : node _T_1713 = shl(UInt<5>(0h11), 3) node _T_1714 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1713) connect Queue10_UInt8_25.io.enq.bits, _T_1714 node _T_1715 = eq(UInt<5>(0h1a), idx_17) when _T_1715 : node _T_1716 = shl(UInt<5>(0h11), 3) node _T_1717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1716) connect Queue10_UInt8_26.io.enq.bits, _T_1717 node _T_1718 = eq(UInt<5>(0h1b), idx_17) when _T_1718 : node _T_1719 = shl(UInt<5>(0h11), 3) node _T_1720 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1719) connect Queue10_UInt8_27.io.enq.bits, _T_1720 node _T_1721 = eq(UInt<5>(0h1c), idx_17) when _T_1721 : node _T_1722 = shl(UInt<5>(0h11), 3) node _T_1723 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1722) connect Queue10_UInt8_28.io.enq.bits, _T_1723 node _T_1724 = eq(UInt<5>(0h1d), idx_17) when _T_1724 : node _T_1725 = shl(UInt<5>(0h11), 3) node _T_1726 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1725) connect Queue10_UInt8_29.io.enq.bits, _T_1726 node _T_1727 = eq(UInt<5>(0h1e), idx_17) when _T_1727 : node _T_1728 = shl(UInt<5>(0h11), 3) node _T_1729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1728) connect Queue10_UInt8_30.io.enq.bits, _T_1729 node _T_1730 = eq(UInt<5>(0h1f), idx_17) when _T_1730 : node _T_1731 = shl(UInt<5>(0h11), 3) node _T_1732 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1731) connect Queue10_UInt8_31.io.enq.bits, _T_1732 node _idx_T_18 = add(write_start_index, UInt<5>(0h12)) node idx_18 = rem(_idx_T_18, UInt<6>(0h20)) node _T_1733 = eq(UInt<1>(0h0), idx_18) when _T_1733 : node _T_1734 = shl(UInt<5>(0h12), 3) node _T_1735 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1734) connect Queue10_UInt8.io.enq.bits, _T_1735 node _T_1736 = eq(UInt<1>(0h1), idx_18) when _T_1736 : node _T_1737 = shl(UInt<5>(0h12), 3) node _T_1738 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1737) connect Queue10_UInt8_1.io.enq.bits, _T_1738 node _T_1739 = eq(UInt<2>(0h2), idx_18) when _T_1739 : node _T_1740 = shl(UInt<5>(0h12), 3) node _T_1741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1740) connect Queue10_UInt8_2.io.enq.bits, _T_1741 node _T_1742 = eq(UInt<2>(0h3), idx_18) when _T_1742 : node _T_1743 = shl(UInt<5>(0h12), 3) node _T_1744 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1743) connect Queue10_UInt8_3.io.enq.bits, _T_1744 node _T_1745 = eq(UInt<3>(0h4), idx_18) when _T_1745 : node _T_1746 = shl(UInt<5>(0h12), 3) node _T_1747 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1746) connect Queue10_UInt8_4.io.enq.bits, _T_1747 node _T_1748 = eq(UInt<3>(0h5), idx_18) when _T_1748 : node _T_1749 = shl(UInt<5>(0h12), 3) node _T_1750 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1749) connect Queue10_UInt8_5.io.enq.bits, _T_1750 node _T_1751 = eq(UInt<3>(0h6), idx_18) when _T_1751 : node _T_1752 = shl(UInt<5>(0h12), 3) node _T_1753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1752) connect Queue10_UInt8_6.io.enq.bits, _T_1753 node _T_1754 = eq(UInt<3>(0h7), idx_18) when _T_1754 : node _T_1755 = shl(UInt<5>(0h12), 3) node _T_1756 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1755) connect Queue10_UInt8_7.io.enq.bits, _T_1756 node _T_1757 = eq(UInt<4>(0h8), idx_18) when _T_1757 : node _T_1758 = shl(UInt<5>(0h12), 3) node _T_1759 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1758) connect Queue10_UInt8_8.io.enq.bits, _T_1759 node _T_1760 = eq(UInt<4>(0h9), idx_18) when _T_1760 : node _T_1761 = shl(UInt<5>(0h12), 3) node _T_1762 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1761) connect Queue10_UInt8_9.io.enq.bits, _T_1762 node _T_1763 = eq(UInt<4>(0ha), idx_18) when _T_1763 : node _T_1764 = shl(UInt<5>(0h12), 3) node _T_1765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1764) connect Queue10_UInt8_10.io.enq.bits, _T_1765 node _T_1766 = eq(UInt<4>(0hb), idx_18) when _T_1766 : node _T_1767 = shl(UInt<5>(0h12), 3) node _T_1768 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1767) connect Queue10_UInt8_11.io.enq.bits, _T_1768 node _T_1769 = eq(UInt<4>(0hc), idx_18) when _T_1769 : node _T_1770 = shl(UInt<5>(0h12), 3) node _T_1771 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1770) connect Queue10_UInt8_12.io.enq.bits, _T_1771 node _T_1772 = eq(UInt<4>(0hd), idx_18) when _T_1772 : node _T_1773 = shl(UInt<5>(0h12), 3) node _T_1774 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1773) connect Queue10_UInt8_13.io.enq.bits, _T_1774 node _T_1775 = eq(UInt<4>(0he), idx_18) when _T_1775 : node _T_1776 = shl(UInt<5>(0h12), 3) node _T_1777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1776) connect Queue10_UInt8_14.io.enq.bits, _T_1777 node _T_1778 = eq(UInt<4>(0hf), idx_18) when _T_1778 : node _T_1779 = shl(UInt<5>(0h12), 3) node _T_1780 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1779) connect Queue10_UInt8_15.io.enq.bits, _T_1780 node _T_1781 = eq(UInt<5>(0h10), idx_18) when _T_1781 : node _T_1782 = shl(UInt<5>(0h12), 3) node _T_1783 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1782) connect Queue10_UInt8_16.io.enq.bits, _T_1783 node _T_1784 = eq(UInt<5>(0h11), idx_18) when _T_1784 : node _T_1785 = shl(UInt<5>(0h12), 3) node _T_1786 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1785) connect Queue10_UInt8_17.io.enq.bits, _T_1786 node _T_1787 = eq(UInt<5>(0h12), idx_18) when _T_1787 : node _T_1788 = shl(UInt<5>(0h12), 3) node _T_1789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1788) connect Queue10_UInt8_18.io.enq.bits, _T_1789 node _T_1790 = eq(UInt<5>(0h13), idx_18) when _T_1790 : node _T_1791 = shl(UInt<5>(0h12), 3) node _T_1792 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1791) connect Queue10_UInt8_19.io.enq.bits, _T_1792 node _T_1793 = eq(UInt<5>(0h14), idx_18) when _T_1793 : node _T_1794 = shl(UInt<5>(0h12), 3) node _T_1795 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1794) connect Queue10_UInt8_20.io.enq.bits, _T_1795 node _T_1796 = eq(UInt<5>(0h15), idx_18) when _T_1796 : node _T_1797 = shl(UInt<5>(0h12), 3) node _T_1798 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1797) connect Queue10_UInt8_21.io.enq.bits, _T_1798 node _T_1799 = eq(UInt<5>(0h16), idx_18) when _T_1799 : node _T_1800 = shl(UInt<5>(0h12), 3) node _T_1801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1800) connect Queue10_UInt8_22.io.enq.bits, _T_1801 node _T_1802 = eq(UInt<5>(0h17), idx_18) when _T_1802 : node _T_1803 = shl(UInt<5>(0h12), 3) node _T_1804 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1803) connect Queue10_UInt8_23.io.enq.bits, _T_1804 node _T_1805 = eq(UInt<5>(0h18), idx_18) when _T_1805 : node _T_1806 = shl(UInt<5>(0h12), 3) node _T_1807 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1806) connect Queue10_UInt8_24.io.enq.bits, _T_1807 node _T_1808 = eq(UInt<5>(0h19), idx_18) when _T_1808 : node _T_1809 = shl(UInt<5>(0h12), 3) node _T_1810 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1809) connect Queue10_UInt8_25.io.enq.bits, _T_1810 node _T_1811 = eq(UInt<5>(0h1a), idx_18) when _T_1811 : node _T_1812 = shl(UInt<5>(0h12), 3) node _T_1813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1812) connect Queue10_UInt8_26.io.enq.bits, _T_1813 node _T_1814 = eq(UInt<5>(0h1b), idx_18) when _T_1814 : node _T_1815 = shl(UInt<5>(0h12), 3) node _T_1816 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1815) connect Queue10_UInt8_27.io.enq.bits, _T_1816 node _T_1817 = eq(UInt<5>(0h1c), idx_18) when _T_1817 : node _T_1818 = shl(UInt<5>(0h12), 3) node _T_1819 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1818) connect Queue10_UInt8_28.io.enq.bits, _T_1819 node _T_1820 = eq(UInt<5>(0h1d), idx_18) when _T_1820 : node _T_1821 = shl(UInt<5>(0h12), 3) node _T_1822 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1821) connect Queue10_UInt8_29.io.enq.bits, _T_1822 node _T_1823 = eq(UInt<5>(0h1e), idx_18) when _T_1823 : node _T_1824 = shl(UInt<5>(0h12), 3) node _T_1825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1824) connect Queue10_UInt8_30.io.enq.bits, _T_1825 node _T_1826 = eq(UInt<5>(0h1f), idx_18) when _T_1826 : node _T_1827 = shl(UInt<5>(0h12), 3) node _T_1828 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1827) connect Queue10_UInt8_31.io.enq.bits, _T_1828 node _idx_T_19 = add(write_start_index, UInt<5>(0h13)) node idx_19 = rem(_idx_T_19, UInt<6>(0h20)) node _T_1829 = eq(UInt<1>(0h0), idx_19) when _T_1829 : node _T_1830 = shl(UInt<5>(0h13), 3) node _T_1831 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1830) connect Queue10_UInt8.io.enq.bits, _T_1831 node _T_1832 = eq(UInt<1>(0h1), idx_19) when _T_1832 : node _T_1833 = shl(UInt<5>(0h13), 3) node _T_1834 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1833) connect Queue10_UInt8_1.io.enq.bits, _T_1834 node _T_1835 = eq(UInt<2>(0h2), idx_19) when _T_1835 : node _T_1836 = shl(UInt<5>(0h13), 3) node _T_1837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1836) connect Queue10_UInt8_2.io.enq.bits, _T_1837 node _T_1838 = eq(UInt<2>(0h3), idx_19) when _T_1838 : node _T_1839 = shl(UInt<5>(0h13), 3) node _T_1840 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1839) connect Queue10_UInt8_3.io.enq.bits, _T_1840 node _T_1841 = eq(UInt<3>(0h4), idx_19) when _T_1841 : node _T_1842 = shl(UInt<5>(0h13), 3) node _T_1843 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1842) connect Queue10_UInt8_4.io.enq.bits, _T_1843 node _T_1844 = eq(UInt<3>(0h5), idx_19) when _T_1844 : node _T_1845 = shl(UInt<5>(0h13), 3) node _T_1846 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1845) connect Queue10_UInt8_5.io.enq.bits, _T_1846 node _T_1847 = eq(UInt<3>(0h6), idx_19) when _T_1847 : node _T_1848 = shl(UInt<5>(0h13), 3) node _T_1849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1848) connect Queue10_UInt8_6.io.enq.bits, _T_1849 node _T_1850 = eq(UInt<3>(0h7), idx_19) when _T_1850 : node _T_1851 = shl(UInt<5>(0h13), 3) node _T_1852 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1851) connect Queue10_UInt8_7.io.enq.bits, _T_1852 node _T_1853 = eq(UInt<4>(0h8), idx_19) when _T_1853 : node _T_1854 = shl(UInt<5>(0h13), 3) node _T_1855 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1854) connect Queue10_UInt8_8.io.enq.bits, _T_1855 node _T_1856 = eq(UInt<4>(0h9), idx_19) when _T_1856 : node _T_1857 = shl(UInt<5>(0h13), 3) node _T_1858 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1857) connect Queue10_UInt8_9.io.enq.bits, _T_1858 node _T_1859 = eq(UInt<4>(0ha), idx_19) when _T_1859 : node _T_1860 = shl(UInt<5>(0h13), 3) node _T_1861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1860) connect Queue10_UInt8_10.io.enq.bits, _T_1861 node _T_1862 = eq(UInt<4>(0hb), idx_19) when _T_1862 : node _T_1863 = shl(UInt<5>(0h13), 3) node _T_1864 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1863) connect Queue10_UInt8_11.io.enq.bits, _T_1864 node _T_1865 = eq(UInt<4>(0hc), idx_19) when _T_1865 : node _T_1866 = shl(UInt<5>(0h13), 3) node _T_1867 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1866) connect Queue10_UInt8_12.io.enq.bits, _T_1867 node _T_1868 = eq(UInt<4>(0hd), idx_19) when _T_1868 : node _T_1869 = shl(UInt<5>(0h13), 3) node _T_1870 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1869) connect Queue10_UInt8_13.io.enq.bits, _T_1870 node _T_1871 = eq(UInt<4>(0he), idx_19) when _T_1871 : node _T_1872 = shl(UInt<5>(0h13), 3) node _T_1873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1872) connect Queue10_UInt8_14.io.enq.bits, _T_1873 node _T_1874 = eq(UInt<4>(0hf), idx_19) when _T_1874 : node _T_1875 = shl(UInt<5>(0h13), 3) node _T_1876 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1875) connect Queue10_UInt8_15.io.enq.bits, _T_1876 node _T_1877 = eq(UInt<5>(0h10), idx_19) when _T_1877 : node _T_1878 = shl(UInt<5>(0h13), 3) node _T_1879 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1878) connect Queue10_UInt8_16.io.enq.bits, _T_1879 node _T_1880 = eq(UInt<5>(0h11), idx_19) when _T_1880 : node _T_1881 = shl(UInt<5>(0h13), 3) node _T_1882 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1881) connect Queue10_UInt8_17.io.enq.bits, _T_1882 node _T_1883 = eq(UInt<5>(0h12), idx_19) when _T_1883 : node _T_1884 = shl(UInt<5>(0h13), 3) node _T_1885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1884) connect Queue10_UInt8_18.io.enq.bits, _T_1885 node _T_1886 = eq(UInt<5>(0h13), idx_19) when _T_1886 : node _T_1887 = shl(UInt<5>(0h13), 3) node _T_1888 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1887) connect Queue10_UInt8_19.io.enq.bits, _T_1888 node _T_1889 = eq(UInt<5>(0h14), idx_19) when _T_1889 : node _T_1890 = shl(UInt<5>(0h13), 3) node _T_1891 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1890) connect Queue10_UInt8_20.io.enq.bits, _T_1891 node _T_1892 = eq(UInt<5>(0h15), idx_19) when _T_1892 : node _T_1893 = shl(UInt<5>(0h13), 3) node _T_1894 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1893) connect Queue10_UInt8_21.io.enq.bits, _T_1894 node _T_1895 = eq(UInt<5>(0h16), idx_19) when _T_1895 : node _T_1896 = shl(UInt<5>(0h13), 3) node _T_1897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1896) connect Queue10_UInt8_22.io.enq.bits, _T_1897 node _T_1898 = eq(UInt<5>(0h17), idx_19) when _T_1898 : node _T_1899 = shl(UInt<5>(0h13), 3) node _T_1900 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1899) connect Queue10_UInt8_23.io.enq.bits, _T_1900 node _T_1901 = eq(UInt<5>(0h18), idx_19) when _T_1901 : node _T_1902 = shl(UInt<5>(0h13), 3) node _T_1903 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1902) connect Queue10_UInt8_24.io.enq.bits, _T_1903 node _T_1904 = eq(UInt<5>(0h19), idx_19) when _T_1904 : node _T_1905 = shl(UInt<5>(0h13), 3) node _T_1906 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1905) connect Queue10_UInt8_25.io.enq.bits, _T_1906 node _T_1907 = eq(UInt<5>(0h1a), idx_19) when _T_1907 : node _T_1908 = shl(UInt<5>(0h13), 3) node _T_1909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1908) connect Queue10_UInt8_26.io.enq.bits, _T_1909 node _T_1910 = eq(UInt<5>(0h1b), idx_19) when _T_1910 : node _T_1911 = shl(UInt<5>(0h13), 3) node _T_1912 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1911) connect Queue10_UInt8_27.io.enq.bits, _T_1912 node _T_1913 = eq(UInt<5>(0h1c), idx_19) when _T_1913 : node _T_1914 = shl(UInt<5>(0h13), 3) node _T_1915 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1914) connect Queue10_UInt8_28.io.enq.bits, _T_1915 node _T_1916 = eq(UInt<5>(0h1d), idx_19) when _T_1916 : node _T_1917 = shl(UInt<5>(0h13), 3) node _T_1918 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1917) connect Queue10_UInt8_29.io.enq.bits, _T_1918 node _T_1919 = eq(UInt<5>(0h1e), idx_19) when _T_1919 : node _T_1920 = shl(UInt<5>(0h13), 3) node _T_1921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1920) connect Queue10_UInt8_30.io.enq.bits, _T_1921 node _T_1922 = eq(UInt<5>(0h1f), idx_19) when _T_1922 : node _T_1923 = shl(UInt<5>(0h13), 3) node _T_1924 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1923) connect Queue10_UInt8_31.io.enq.bits, _T_1924 node _idx_T_20 = add(write_start_index, UInt<5>(0h14)) node idx_20 = rem(_idx_T_20, UInt<6>(0h20)) node _T_1925 = eq(UInt<1>(0h0), idx_20) when _T_1925 : node _T_1926 = shl(UInt<5>(0h14), 3) node _T_1927 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1926) connect Queue10_UInt8.io.enq.bits, _T_1927 node _T_1928 = eq(UInt<1>(0h1), idx_20) when _T_1928 : node _T_1929 = shl(UInt<5>(0h14), 3) node _T_1930 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1929) connect Queue10_UInt8_1.io.enq.bits, _T_1930 node _T_1931 = eq(UInt<2>(0h2), idx_20) when _T_1931 : node _T_1932 = shl(UInt<5>(0h14), 3) node _T_1933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1932) connect Queue10_UInt8_2.io.enq.bits, _T_1933 node _T_1934 = eq(UInt<2>(0h3), idx_20) when _T_1934 : node _T_1935 = shl(UInt<5>(0h14), 3) node _T_1936 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1935) connect Queue10_UInt8_3.io.enq.bits, _T_1936 node _T_1937 = eq(UInt<3>(0h4), idx_20) when _T_1937 : node _T_1938 = shl(UInt<5>(0h14), 3) node _T_1939 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1938) connect Queue10_UInt8_4.io.enq.bits, _T_1939 node _T_1940 = eq(UInt<3>(0h5), idx_20) when _T_1940 : node _T_1941 = shl(UInt<5>(0h14), 3) node _T_1942 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1941) connect Queue10_UInt8_5.io.enq.bits, _T_1942 node _T_1943 = eq(UInt<3>(0h6), idx_20) when _T_1943 : node _T_1944 = shl(UInt<5>(0h14), 3) node _T_1945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1944) connect Queue10_UInt8_6.io.enq.bits, _T_1945 node _T_1946 = eq(UInt<3>(0h7), idx_20) when _T_1946 : node _T_1947 = shl(UInt<5>(0h14), 3) node _T_1948 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1947) connect Queue10_UInt8_7.io.enq.bits, _T_1948 node _T_1949 = eq(UInt<4>(0h8), idx_20) when _T_1949 : node _T_1950 = shl(UInt<5>(0h14), 3) node _T_1951 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1950) connect Queue10_UInt8_8.io.enq.bits, _T_1951 node _T_1952 = eq(UInt<4>(0h9), idx_20) when _T_1952 : node _T_1953 = shl(UInt<5>(0h14), 3) node _T_1954 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1953) connect Queue10_UInt8_9.io.enq.bits, _T_1954 node _T_1955 = eq(UInt<4>(0ha), idx_20) when _T_1955 : node _T_1956 = shl(UInt<5>(0h14), 3) node _T_1957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1956) connect Queue10_UInt8_10.io.enq.bits, _T_1957 node _T_1958 = eq(UInt<4>(0hb), idx_20) when _T_1958 : node _T_1959 = shl(UInt<5>(0h14), 3) node _T_1960 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1959) connect Queue10_UInt8_11.io.enq.bits, _T_1960 node _T_1961 = eq(UInt<4>(0hc), idx_20) when _T_1961 : node _T_1962 = shl(UInt<5>(0h14), 3) node _T_1963 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1962) connect Queue10_UInt8_12.io.enq.bits, _T_1963 node _T_1964 = eq(UInt<4>(0hd), idx_20) when _T_1964 : node _T_1965 = shl(UInt<5>(0h14), 3) node _T_1966 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1965) connect Queue10_UInt8_13.io.enq.bits, _T_1966 node _T_1967 = eq(UInt<4>(0he), idx_20) when _T_1967 : node _T_1968 = shl(UInt<5>(0h14), 3) node _T_1969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1968) connect Queue10_UInt8_14.io.enq.bits, _T_1969 node _T_1970 = eq(UInt<4>(0hf), idx_20) when _T_1970 : node _T_1971 = shl(UInt<5>(0h14), 3) node _T_1972 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1971) connect Queue10_UInt8_15.io.enq.bits, _T_1972 node _T_1973 = eq(UInt<5>(0h10), idx_20) when _T_1973 : node _T_1974 = shl(UInt<5>(0h14), 3) node _T_1975 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1974) connect Queue10_UInt8_16.io.enq.bits, _T_1975 node _T_1976 = eq(UInt<5>(0h11), idx_20) when _T_1976 : node _T_1977 = shl(UInt<5>(0h14), 3) node _T_1978 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1977) connect Queue10_UInt8_17.io.enq.bits, _T_1978 node _T_1979 = eq(UInt<5>(0h12), idx_20) when _T_1979 : node _T_1980 = shl(UInt<5>(0h14), 3) node _T_1981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1980) connect Queue10_UInt8_18.io.enq.bits, _T_1981 node _T_1982 = eq(UInt<5>(0h13), idx_20) when _T_1982 : node _T_1983 = shl(UInt<5>(0h14), 3) node _T_1984 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1983) connect Queue10_UInt8_19.io.enq.bits, _T_1984 node _T_1985 = eq(UInt<5>(0h14), idx_20) when _T_1985 : node _T_1986 = shl(UInt<5>(0h14), 3) node _T_1987 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1986) connect Queue10_UInt8_20.io.enq.bits, _T_1987 node _T_1988 = eq(UInt<5>(0h15), idx_20) when _T_1988 : node _T_1989 = shl(UInt<5>(0h14), 3) node _T_1990 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1989) connect Queue10_UInt8_21.io.enq.bits, _T_1990 node _T_1991 = eq(UInt<5>(0h16), idx_20) when _T_1991 : node _T_1992 = shl(UInt<5>(0h14), 3) node _T_1993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1992) connect Queue10_UInt8_22.io.enq.bits, _T_1993 node _T_1994 = eq(UInt<5>(0h17), idx_20) when _T_1994 : node _T_1995 = shl(UInt<5>(0h14), 3) node _T_1996 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1995) connect Queue10_UInt8_23.io.enq.bits, _T_1996 node _T_1997 = eq(UInt<5>(0h18), idx_20) when _T_1997 : node _T_1998 = shl(UInt<5>(0h14), 3) node _T_1999 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1998) connect Queue10_UInt8_24.io.enq.bits, _T_1999 node _T_2000 = eq(UInt<5>(0h19), idx_20) when _T_2000 : node _T_2001 = shl(UInt<5>(0h14), 3) node _T_2002 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2001) connect Queue10_UInt8_25.io.enq.bits, _T_2002 node _T_2003 = eq(UInt<5>(0h1a), idx_20) when _T_2003 : node _T_2004 = shl(UInt<5>(0h14), 3) node _T_2005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2004) connect Queue10_UInt8_26.io.enq.bits, _T_2005 node _T_2006 = eq(UInt<5>(0h1b), idx_20) when _T_2006 : node _T_2007 = shl(UInt<5>(0h14), 3) node _T_2008 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2007) connect Queue10_UInt8_27.io.enq.bits, _T_2008 node _T_2009 = eq(UInt<5>(0h1c), idx_20) when _T_2009 : node _T_2010 = shl(UInt<5>(0h14), 3) node _T_2011 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2010) connect Queue10_UInt8_28.io.enq.bits, _T_2011 node _T_2012 = eq(UInt<5>(0h1d), idx_20) when _T_2012 : node _T_2013 = shl(UInt<5>(0h14), 3) node _T_2014 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2013) connect Queue10_UInt8_29.io.enq.bits, _T_2014 node _T_2015 = eq(UInt<5>(0h1e), idx_20) when _T_2015 : node _T_2016 = shl(UInt<5>(0h14), 3) node _T_2017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2016) connect Queue10_UInt8_30.io.enq.bits, _T_2017 node _T_2018 = eq(UInt<5>(0h1f), idx_20) when _T_2018 : node _T_2019 = shl(UInt<5>(0h14), 3) node _T_2020 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2019) connect Queue10_UInt8_31.io.enq.bits, _T_2020 node _idx_T_21 = add(write_start_index, UInt<5>(0h15)) node idx_21 = rem(_idx_T_21, UInt<6>(0h20)) node _T_2021 = eq(UInt<1>(0h0), idx_21) when _T_2021 : node _T_2022 = shl(UInt<5>(0h15), 3) node _T_2023 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2022) connect Queue10_UInt8.io.enq.bits, _T_2023 node _T_2024 = eq(UInt<1>(0h1), idx_21) when _T_2024 : node _T_2025 = shl(UInt<5>(0h15), 3) node _T_2026 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2025) connect Queue10_UInt8_1.io.enq.bits, _T_2026 node _T_2027 = eq(UInt<2>(0h2), idx_21) when _T_2027 : node _T_2028 = shl(UInt<5>(0h15), 3) node _T_2029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2028) connect Queue10_UInt8_2.io.enq.bits, _T_2029 node _T_2030 = eq(UInt<2>(0h3), idx_21) when _T_2030 : node _T_2031 = shl(UInt<5>(0h15), 3) node _T_2032 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2031) connect Queue10_UInt8_3.io.enq.bits, _T_2032 node _T_2033 = eq(UInt<3>(0h4), idx_21) when _T_2033 : node _T_2034 = shl(UInt<5>(0h15), 3) node _T_2035 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2034) connect Queue10_UInt8_4.io.enq.bits, _T_2035 node _T_2036 = eq(UInt<3>(0h5), idx_21) when _T_2036 : node _T_2037 = shl(UInt<5>(0h15), 3) node _T_2038 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2037) connect Queue10_UInt8_5.io.enq.bits, _T_2038 node _T_2039 = eq(UInt<3>(0h6), idx_21) when _T_2039 : node _T_2040 = shl(UInt<5>(0h15), 3) node _T_2041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2040) connect Queue10_UInt8_6.io.enq.bits, _T_2041 node _T_2042 = eq(UInt<3>(0h7), idx_21) when _T_2042 : node _T_2043 = shl(UInt<5>(0h15), 3) node _T_2044 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2043) connect Queue10_UInt8_7.io.enq.bits, _T_2044 node _T_2045 = eq(UInt<4>(0h8), idx_21) when _T_2045 : node _T_2046 = shl(UInt<5>(0h15), 3) node _T_2047 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2046) connect Queue10_UInt8_8.io.enq.bits, _T_2047 node _T_2048 = eq(UInt<4>(0h9), idx_21) when _T_2048 : node _T_2049 = shl(UInt<5>(0h15), 3) node _T_2050 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2049) connect Queue10_UInt8_9.io.enq.bits, _T_2050 node _T_2051 = eq(UInt<4>(0ha), idx_21) when _T_2051 : node _T_2052 = shl(UInt<5>(0h15), 3) node _T_2053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2052) connect Queue10_UInt8_10.io.enq.bits, _T_2053 node _T_2054 = eq(UInt<4>(0hb), idx_21) when _T_2054 : node _T_2055 = shl(UInt<5>(0h15), 3) node _T_2056 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2055) connect Queue10_UInt8_11.io.enq.bits, _T_2056 node _T_2057 = eq(UInt<4>(0hc), idx_21) when _T_2057 : node _T_2058 = shl(UInt<5>(0h15), 3) node _T_2059 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2058) connect Queue10_UInt8_12.io.enq.bits, _T_2059 node _T_2060 = eq(UInt<4>(0hd), idx_21) when _T_2060 : node _T_2061 = shl(UInt<5>(0h15), 3) node _T_2062 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2061) connect Queue10_UInt8_13.io.enq.bits, _T_2062 node _T_2063 = eq(UInt<4>(0he), idx_21) when _T_2063 : node _T_2064 = shl(UInt<5>(0h15), 3) node _T_2065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2064) connect Queue10_UInt8_14.io.enq.bits, _T_2065 node _T_2066 = eq(UInt<4>(0hf), idx_21) when _T_2066 : node _T_2067 = shl(UInt<5>(0h15), 3) node _T_2068 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2067) connect Queue10_UInt8_15.io.enq.bits, _T_2068 node _T_2069 = eq(UInt<5>(0h10), idx_21) when _T_2069 : node _T_2070 = shl(UInt<5>(0h15), 3) node _T_2071 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2070) connect Queue10_UInt8_16.io.enq.bits, _T_2071 node _T_2072 = eq(UInt<5>(0h11), idx_21) when _T_2072 : node _T_2073 = shl(UInt<5>(0h15), 3) node _T_2074 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2073) connect Queue10_UInt8_17.io.enq.bits, _T_2074 node _T_2075 = eq(UInt<5>(0h12), idx_21) when _T_2075 : node _T_2076 = shl(UInt<5>(0h15), 3) node _T_2077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2076) connect Queue10_UInt8_18.io.enq.bits, _T_2077 node _T_2078 = eq(UInt<5>(0h13), idx_21) when _T_2078 : node _T_2079 = shl(UInt<5>(0h15), 3) node _T_2080 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2079) connect Queue10_UInt8_19.io.enq.bits, _T_2080 node _T_2081 = eq(UInt<5>(0h14), idx_21) when _T_2081 : node _T_2082 = shl(UInt<5>(0h15), 3) node _T_2083 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2082) connect Queue10_UInt8_20.io.enq.bits, _T_2083 node _T_2084 = eq(UInt<5>(0h15), idx_21) when _T_2084 : node _T_2085 = shl(UInt<5>(0h15), 3) node _T_2086 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2085) connect Queue10_UInt8_21.io.enq.bits, _T_2086 node _T_2087 = eq(UInt<5>(0h16), idx_21) when _T_2087 : node _T_2088 = shl(UInt<5>(0h15), 3) node _T_2089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2088) connect Queue10_UInt8_22.io.enq.bits, _T_2089 node _T_2090 = eq(UInt<5>(0h17), idx_21) when _T_2090 : node _T_2091 = shl(UInt<5>(0h15), 3) node _T_2092 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2091) connect Queue10_UInt8_23.io.enq.bits, _T_2092 node _T_2093 = eq(UInt<5>(0h18), idx_21) when _T_2093 : node _T_2094 = shl(UInt<5>(0h15), 3) node _T_2095 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2094) connect Queue10_UInt8_24.io.enq.bits, _T_2095 node _T_2096 = eq(UInt<5>(0h19), idx_21) when _T_2096 : node _T_2097 = shl(UInt<5>(0h15), 3) node _T_2098 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2097) connect Queue10_UInt8_25.io.enq.bits, _T_2098 node _T_2099 = eq(UInt<5>(0h1a), idx_21) when _T_2099 : node _T_2100 = shl(UInt<5>(0h15), 3) node _T_2101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2100) connect Queue10_UInt8_26.io.enq.bits, _T_2101 node _T_2102 = eq(UInt<5>(0h1b), idx_21) when _T_2102 : node _T_2103 = shl(UInt<5>(0h15), 3) node _T_2104 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2103) connect Queue10_UInt8_27.io.enq.bits, _T_2104 node _T_2105 = eq(UInt<5>(0h1c), idx_21) when _T_2105 : node _T_2106 = shl(UInt<5>(0h15), 3) node _T_2107 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2106) connect Queue10_UInt8_28.io.enq.bits, _T_2107 node _T_2108 = eq(UInt<5>(0h1d), idx_21) when _T_2108 : node _T_2109 = shl(UInt<5>(0h15), 3) node _T_2110 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2109) connect Queue10_UInt8_29.io.enq.bits, _T_2110 node _T_2111 = eq(UInt<5>(0h1e), idx_21) when _T_2111 : node _T_2112 = shl(UInt<5>(0h15), 3) node _T_2113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2112) connect Queue10_UInt8_30.io.enq.bits, _T_2113 node _T_2114 = eq(UInt<5>(0h1f), idx_21) when _T_2114 : node _T_2115 = shl(UInt<5>(0h15), 3) node _T_2116 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2115) connect Queue10_UInt8_31.io.enq.bits, _T_2116 node _idx_T_22 = add(write_start_index, UInt<5>(0h16)) node idx_22 = rem(_idx_T_22, UInt<6>(0h20)) node _T_2117 = eq(UInt<1>(0h0), idx_22) when _T_2117 : node _T_2118 = shl(UInt<5>(0h16), 3) node _T_2119 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2118) connect Queue10_UInt8.io.enq.bits, _T_2119 node _T_2120 = eq(UInt<1>(0h1), idx_22) when _T_2120 : node _T_2121 = shl(UInt<5>(0h16), 3) node _T_2122 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2121) connect Queue10_UInt8_1.io.enq.bits, _T_2122 node _T_2123 = eq(UInt<2>(0h2), idx_22) when _T_2123 : node _T_2124 = shl(UInt<5>(0h16), 3) node _T_2125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2124) connect Queue10_UInt8_2.io.enq.bits, _T_2125 node _T_2126 = eq(UInt<2>(0h3), idx_22) when _T_2126 : node _T_2127 = shl(UInt<5>(0h16), 3) node _T_2128 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2127) connect Queue10_UInt8_3.io.enq.bits, _T_2128 node _T_2129 = eq(UInt<3>(0h4), idx_22) when _T_2129 : node _T_2130 = shl(UInt<5>(0h16), 3) node _T_2131 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2130) connect Queue10_UInt8_4.io.enq.bits, _T_2131 node _T_2132 = eq(UInt<3>(0h5), idx_22) when _T_2132 : node _T_2133 = shl(UInt<5>(0h16), 3) node _T_2134 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2133) connect Queue10_UInt8_5.io.enq.bits, _T_2134 node _T_2135 = eq(UInt<3>(0h6), idx_22) when _T_2135 : node _T_2136 = shl(UInt<5>(0h16), 3) node _T_2137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2136) connect Queue10_UInt8_6.io.enq.bits, _T_2137 node _T_2138 = eq(UInt<3>(0h7), idx_22) when _T_2138 : node _T_2139 = shl(UInt<5>(0h16), 3) node _T_2140 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2139) connect Queue10_UInt8_7.io.enq.bits, _T_2140 node _T_2141 = eq(UInt<4>(0h8), idx_22) when _T_2141 : node _T_2142 = shl(UInt<5>(0h16), 3) node _T_2143 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2142) connect Queue10_UInt8_8.io.enq.bits, _T_2143 node _T_2144 = eq(UInt<4>(0h9), idx_22) when _T_2144 : node _T_2145 = shl(UInt<5>(0h16), 3) node _T_2146 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2145) connect Queue10_UInt8_9.io.enq.bits, _T_2146 node _T_2147 = eq(UInt<4>(0ha), idx_22) when _T_2147 : node _T_2148 = shl(UInt<5>(0h16), 3) node _T_2149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2148) connect Queue10_UInt8_10.io.enq.bits, _T_2149 node _T_2150 = eq(UInt<4>(0hb), idx_22) when _T_2150 : node _T_2151 = shl(UInt<5>(0h16), 3) node _T_2152 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2151) connect Queue10_UInt8_11.io.enq.bits, _T_2152 node _T_2153 = eq(UInt<4>(0hc), idx_22) when _T_2153 : node _T_2154 = shl(UInt<5>(0h16), 3) node _T_2155 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2154) connect Queue10_UInt8_12.io.enq.bits, _T_2155 node _T_2156 = eq(UInt<4>(0hd), idx_22) when _T_2156 : node _T_2157 = shl(UInt<5>(0h16), 3) node _T_2158 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2157) connect Queue10_UInt8_13.io.enq.bits, _T_2158 node _T_2159 = eq(UInt<4>(0he), idx_22) when _T_2159 : node _T_2160 = shl(UInt<5>(0h16), 3) node _T_2161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2160) connect Queue10_UInt8_14.io.enq.bits, _T_2161 node _T_2162 = eq(UInt<4>(0hf), idx_22) when _T_2162 : node _T_2163 = shl(UInt<5>(0h16), 3) node _T_2164 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2163) connect Queue10_UInt8_15.io.enq.bits, _T_2164 node _T_2165 = eq(UInt<5>(0h10), idx_22) when _T_2165 : node _T_2166 = shl(UInt<5>(0h16), 3) node _T_2167 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2166) connect Queue10_UInt8_16.io.enq.bits, _T_2167 node _T_2168 = eq(UInt<5>(0h11), idx_22) when _T_2168 : node _T_2169 = shl(UInt<5>(0h16), 3) node _T_2170 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2169) connect Queue10_UInt8_17.io.enq.bits, _T_2170 node _T_2171 = eq(UInt<5>(0h12), idx_22) when _T_2171 : node _T_2172 = shl(UInt<5>(0h16), 3) node _T_2173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2172) connect Queue10_UInt8_18.io.enq.bits, _T_2173 node _T_2174 = eq(UInt<5>(0h13), idx_22) when _T_2174 : node _T_2175 = shl(UInt<5>(0h16), 3) node _T_2176 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2175) connect Queue10_UInt8_19.io.enq.bits, _T_2176 node _T_2177 = eq(UInt<5>(0h14), idx_22) when _T_2177 : node _T_2178 = shl(UInt<5>(0h16), 3) node _T_2179 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2178) connect Queue10_UInt8_20.io.enq.bits, _T_2179 node _T_2180 = eq(UInt<5>(0h15), idx_22) when _T_2180 : node _T_2181 = shl(UInt<5>(0h16), 3) node _T_2182 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2181) connect Queue10_UInt8_21.io.enq.bits, _T_2182 node _T_2183 = eq(UInt<5>(0h16), idx_22) when _T_2183 : node _T_2184 = shl(UInt<5>(0h16), 3) node _T_2185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2184) connect Queue10_UInt8_22.io.enq.bits, _T_2185 node _T_2186 = eq(UInt<5>(0h17), idx_22) when _T_2186 : node _T_2187 = shl(UInt<5>(0h16), 3) node _T_2188 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2187) connect Queue10_UInt8_23.io.enq.bits, _T_2188 node _T_2189 = eq(UInt<5>(0h18), idx_22) when _T_2189 : node _T_2190 = shl(UInt<5>(0h16), 3) node _T_2191 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2190) connect Queue10_UInt8_24.io.enq.bits, _T_2191 node _T_2192 = eq(UInt<5>(0h19), idx_22) when _T_2192 : node _T_2193 = shl(UInt<5>(0h16), 3) node _T_2194 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2193) connect Queue10_UInt8_25.io.enq.bits, _T_2194 node _T_2195 = eq(UInt<5>(0h1a), idx_22) when _T_2195 : node _T_2196 = shl(UInt<5>(0h16), 3) node _T_2197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2196) connect Queue10_UInt8_26.io.enq.bits, _T_2197 node _T_2198 = eq(UInt<5>(0h1b), idx_22) when _T_2198 : node _T_2199 = shl(UInt<5>(0h16), 3) node _T_2200 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2199) connect Queue10_UInt8_27.io.enq.bits, _T_2200 node _T_2201 = eq(UInt<5>(0h1c), idx_22) when _T_2201 : node _T_2202 = shl(UInt<5>(0h16), 3) node _T_2203 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2202) connect Queue10_UInt8_28.io.enq.bits, _T_2203 node _T_2204 = eq(UInt<5>(0h1d), idx_22) when _T_2204 : node _T_2205 = shl(UInt<5>(0h16), 3) node _T_2206 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2205) connect Queue10_UInt8_29.io.enq.bits, _T_2206 node _T_2207 = eq(UInt<5>(0h1e), idx_22) when _T_2207 : node _T_2208 = shl(UInt<5>(0h16), 3) node _T_2209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2208) connect Queue10_UInt8_30.io.enq.bits, _T_2209 node _T_2210 = eq(UInt<5>(0h1f), idx_22) when _T_2210 : node _T_2211 = shl(UInt<5>(0h16), 3) node _T_2212 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2211) connect Queue10_UInt8_31.io.enq.bits, _T_2212 node _idx_T_23 = add(write_start_index, UInt<5>(0h17)) node idx_23 = rem(_idx_T_23, UInt<6>(0h20)) node _T_2213 = eq(UInt<1>(0h0), idx_23) when _T_2213 : node _T_2214 = shl(UInt<5>(0h17), 3) node _T_2215 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2214) connect Queue10_UInt8.io.enq.bits, _T_2215 node _T_2216 = eq(UInt<1>(0h1), idx_23) when _T_2216 : node _T_2217 = shl(UInt<5>(0h17), 3) node _T_2218 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2217) connect Queue10_UInt8_1.io.enq.bits, _T_2218 node _T_2219 = eq(UInt<2>(0h2), idx_23) when _T_2219 : node _T_2220 = shl(UInt<5>(0h17), 3) node _T_2221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2220) connect Queue10_UInt8_2.io.enq.bits, _T_2221 node _T_2222 = eq(UInt<2>(0h3), idx_23) when _T_2222 : node _T_2223 = shl(UInt<5>(0h17), 3) node _T_2224 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2223) connect Queue10_UInt8_3.io.enq.bits, _T_2224 node _T_2225 = eq(UInt<3>(0h4), idx_23) when _T_2225 : node _T_2226 = shl(UInt<5>(0h17), 3) node _T_2227 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2226) connect Queue10_UInt8_4.io.enq.bits, _T_2227 node _T_2228 = eq(UInt<3>(0h5), idx_23) when _T_2228 : node _T_2229 = shl(UInt<5>(0h17), 3) node _T_2230 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2229) connect Queue10_UInt8_5.io.enq.bits, _T_2230 node _T_2231 = eq(UInt<3>(0h6), idx_23) when _T_2231 : node _T_2232 = shl(UInt<5>(0h17), 3) node _T_2233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2232) connect Queue10_UInt8_6.io.enq.bits, _T_2233 node _T_2234 = eq(UInt<3>(0h7), idx_23) when _T_2234 : node _T_2235 = shl(UInt<5>(0h17), 3) node _T_2236 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2235) connect Queue10_UInt8_7.io.enq.bits, _T_2236 node _T_2237 = eq(UInt<4>(0h8), idx_23) when _T_2237 : node _T_2238 = shl(UInt<5>(0h17), 3) node _T_2239 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2238) connect Queue10_UInt8_8.io.enq.bits, _T_2239 node _T_2240 = eq(UInt<4>(0h9), idx_23) when _T_2240 : node _T_2241 = shl(UInt<5>(0h17), 3) node _T_2242 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2241) connect Queue10_UInt8_9.io.enq.bits, _T_2242 node _T_2243 = eq(UInt<4>(0ha), idx_23) when _T_2243 : node _T_2244 = shl(UInt<5>(0h17), 3) node _T_2245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2244) connect Queue10_UInt8_10.io.enq.bits, _T_2245 node _T_2246 = eq(UInt<4>(0hb), idx_23) when _T_2246 : node _T_2247 = shl(UInt<5>(0h17), 3) node _T_2248 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2247) connect Queue10_UInt8_11.io.enq.bits, _T_2248 node _T_2249 = eq(UInt<4>(0hc), idx_23) when _T_2249 : node _T_2250 = shl(UInt<5>(0h17), 3) node _T_2251 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2250) connect Queue10_UInt8_12.io.enq.bits, _T_2251 node _T_2252 = eq(UInt<4>(0hd), idx_23) when _T_2252 : node _T_2253 = shl(UInt<5>(0h17), 3) node _T_2254 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2253) connect Queue10_UInt8_13.io.enq.bits, _T_2254 node _T_2255 = eq(UInt<4>(0he), idx_23) when _T_2255 : node _T_2256 = shl(UInt<5>(0h17), 3) node _T_2257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2256) connect Queue10_UInt8_14.io.enq.bits, _T_2257 node _T_2258 = eq(UInt<4>(0hf), idx_23) when _T_2258 : node _T_2259 = shl(UInt<5>(0h17), 3) node _T_2260 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2259) connect Queue10_UInt8_15.io.enq.bits, _T_2260 node _T_2261 = eq(UInt<5>(0h10), idx_23) when _T_2261 : node _T_2262 = shl(UInt<5>(0h17), 3) node _T_2263 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2262) connect Queue10_UInt8_16.io.enq.bits, _T_2263 node _T_2264 = eq(UInt<5>(0h11), idx_23) when _T_2264 : node _T_2265 = shl(UInt<5>(0h17), 3) node _T_2266 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2265) connect Queue10_UInt8_17.io.enq.bits, _T_2266 node _T_2267 = eq(UInt<5>(0h12), idx_23) when _T_2267 : node _T_2268 = shl(UInt<5>(0h17), 3) node _T_2269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2268) connect Queue10_UInt8_18.io.enq.bits, _T_2269 node _T_2270 = eq(UInt<5>(0h13), idx_23) when _T_2270 : node _T_2271 = shl(UInt<5>(0h17), 3) node _T_2272 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2271) connect Queue10_UInt8_19.io.enq.bits, _T_2272 node _T_2273 = eq(UInt<5>(0h14), idx_23) when _T_2273 : node _T_2274 = shl(UInt<5>(0h17), 3) node _T_2275 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2274) connect Queue10_UInt8_20.io.enq.bits, _T_2275 node _T_2276 = eq(UInt<5>(0h15), idx_23) when _T_2276 : node _T_2277 = shl(UInt<5>(0h17), 3) node _T_2278 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2277) connect Queue10_UInt8_21.io.enq.bits, _T_2278 node _T_2279 = eq(UInt<5>(0h16), idx_23) when _T_2279 : node _T_2280 = shl(UInt<5>(0h17), 3) node _T_2281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2280) connect Queue10_UInt8_22.io.enq.bits, _T_2281 node _T_2282 = eq(UInt<5>(0h17), idx_23) when _T_2282 : node _T_2283 = shl(UInt<5>(0h17), 3) node _T_2284 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2283) connect Queue10_UInt8_23.io.enq.bits, _T_2284 node _T_2285 = eq(UInt<5>(0h18), idx_23) when _T_2285 : node _T_2286 = shl(UInt<5>(0h17), 3) node _T_2287 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2286) connect Queue10_UInt8_24.io.enq.bits, _T_2287 node _T_2288 = eq(UInt<5>(0h19), idx_23) when _T_2288 : node _T_2289 = shl(UInt<5>(0h17), 3) node _T_2290 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2289) connect Queue10_UInt8_25.io.enq.bits, _T_2290 node _T_2291 = eq(UInt<5>(0h1a), idx_23) when _T_2291 : node _T_2292 = shl(UInt<5>(0h17), 3) node _T_2293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2292) connect Queue10_UInt8_26.io.enq.bits, _T_2293 node _T_2294 = eq(UInt<5>(0h1b), idx_23) when _T_2294 : node _T_2295 = shl(UInt<5>(0h17), 3) node _T_2296 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2295) connect Queue10_UInt8_27.io.enq.bits, _T_2296 node _T_2297 = eq(UInt<5>(0h1c), idx_23) when _T_2297 : node _T_2298 = shl(UInt<5>(0h17), 3) node _T_2299 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2298) connect Queue10_UInt8_28.io.enq.bits, _T_2299 node _T_2300 = eq(UInt<5>(0h1d), idx_23) when _T_2300 : node _T_2301 = shl(UInt<5>(0h17), 3) node _T_2302 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2301) connect Queue10_UInt8_29.io.enq.bits, _T_2302 node _T_2303 = eq(UInt<5>(0h1e), idx_23) when _T_2303 : node _T_2304 = shl(UInt<5>(0h17), 3) node _T_2305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2304) connect Queue10_UInt8_30.io.enq.bits, _T_2305 node _T_2306 = eq(UInt<5>(0h1f), idx_23) when _T_2306 : node _T_2307 = shl(UInt<5>(0h17), 3) node _T_2308 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2307) connect Queue10_UInt8_31.io.enq.bits, _T_2308 node _idx_T_24 = add(write_start_index, UInt<5>(0h18)) node idx_24 = rem(_idx_T_24, UInt<6>(0h20)) node _T_2309 = eq(UInt<1>(0h0), idx_24) when _T_2309 : node _T_2310 = shl(UInt<5>(0h18), 3) node _T_2311 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2310) connect Queue10_UInt8.io.enq.bits, _T_2311 node _T_2312 = eq(UInt<1>(0h1), idx_24) when _T_2312 : node _T_2313 = shl(UInt<5>(0h18), 3) node _T_2314 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2313) connect Queue10_UInt8_1.io.enq.bits, _T_2314 node _T_2315 = eq(UInt<2>(0h2), idx_24) when _T_2315 : node _T_2316 = shl(UInt<5>(0h18), 3) node _T_2317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2316) connect Queue10_UInt8_2.io.enq.bits, _T_2317 node _T_2318 = eq(UInt<2>(0h3), idx_24) when _T_2318 : node _T_2319 = shl(UInt<5>(0h18), 3) node _T_2320 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2319) connect Queue10_UInt8_3.io.enq.bits, _T_2320 node _T_2321 = eq(UInt<3>(0h4), idx_24) when _T_2321 : node _T_2322 = shl(UInt<5>(0h18), 3) node _T_2323 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2322) connect Queue10_UInt8_4.io.enq.bits, _T_2323 node _T_2324 = eq(UInt<3>(0h5), idx_24) when _T_2324 : node _T_2325 = shl(UInt<5>(0h18), 3) node _T_2326 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2325) connect Queue10_UInt8_5.io.enq.bits, _T_2326 node _T_2327 = eq(UInt<3>(0h6), idx_24) when _T_2327 : node _T_2328 = shl(UInt<5>(0h18), 3) node _T_2329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2328) connect Queue10_UInt8_6.io.enq.bits, _T_2329 node _T_2330 = eq(UInt<3>(0h7), idx_24) when _T_2330 : node _T_2331 = shl(UInt<5>(0h18), 3) node _T_2332 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2331) connect Queue10_UInt8_7.io.enq.bits, _T_2332 node _T_2333 = eq(UInt<4>(0h8), idx_24) when _T_2333 : node _T_2334 = shl(UInt<5>(0h18), 3) node _T_2335 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2334) connect Queue10_UInt8_8.io.enq.bits, _T_2335 node _T_2336 = eq(UInt<4>(0h9), idx_24) when _T_2336 : node _T_2337 = shl(UInt<5>(0h18), 3) node _T_2338 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2337) connect Queue10_UInt8_9.io.enq.bits, _T_2338 node _T_2339 = eq(UInt<4>(0ha), idx_24) when _T_2339 : node _T_2340 = shl(UInt<5>(0h18), 3) node _T_2341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2340) connect Queue10_UInt8_10.io.enq.bits, _T_2341 node _T_2342 = eq(UInt<4>(0hb), idx_24) when _T_2342 : node _T_2343 = shl(UInt<5>(0h18), 3) node _T_2344 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2343) connect Queue10_UInt8_11.io.enq.bits, _T_2344 node _T_2345 = eq(UInt<4>(0hc), idx_24) when _T_2345 : node _T_2346 = shl(UInt<5>(0h18), 3) node _T_2347 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2346) connect Queue10_UInt8_12.io.enq.bits, _T_2347 node _T_2348 = eq(UInt<4>(0hd), idx_24) when _T_2348 : node _T_2349 = shl(UInt<5>(0h18), 3) node _T_2350 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2349) connect Queue10_UInt8_13.io.enq.bits, _T_2350 node _T_2351 = eq(UInt<4>(0he), idx_24) when _T_2351 : node _T_2352 = shl(UInt<5>(0h18), 3) node _T_2353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2352) connect Queue10_UInt8_14.io.enq.bits, _T_2353 node _T_2354 = eq(UInt<4>(0hf), idx_24) when _T_2354 : node _T_2355 = shl(UInt<5>(0h18), 3) node _T_2356 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2355) connect Queue10_UInt8_15.io.enq.bits, _T_2356 node _T_2357 = eq(UInt<5>(0h10), idx_24) when _T_2357 : node _T_2358 = shl(UInt<5>(0h18), 3) node _T_2359 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2358) connect Queue10_UInt8_16.io.enq.bits, _T_2359 node _T_2360 = eq(UInt<5>(0h11), idx_24) when _T_2360 : node _T_2361 = shl(UInt<5>(0h18), 3) node _T_2362 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2361) connect Queue10_UInt8_17.io.enq.bits, _T_2362 node _T_2363 = eq(UInt<5>(0h12), idx_24) when _T_2363 : node _T_2364 = shl(UInt<5>(0h18), 3) node _T_2365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2364) connect Queue10_UInt8_18.io.enq.bits, _T_2365 node _T_2366 = eq(UInt<5>(0h13), idx_24) when _T_2366 : node _T_2367 = shl(UInt<5>(0h18), 3) node _T_2368 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2367) connect Queue10_UInt8_19.io.enq.bits, _T_2368 node _T_2369 = eq(UInt<5>(0h14), idx_24) when _T_2369 : node _T_2370 = shl(UInt<5>(0h18), 3) node _T_2371 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2370) connect Queue10_UInt8_20.io.enq.bits, _T_2371 node _T_2372 = eq(UInt<5>(0h15), idx_24) when _T_2372 : node _T_2373 = shl(UInt<5>(0h18), 3) node _T_2374 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2373) connect Queue10_UInt8_21.io.enq.bits, _T_2374 node _T_2375 = eq(UInt<5>(0h16), idx_24) when _T_2375 : node _T_2376 = shl(UInt<5>(0h18), 3) node _T_2377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2376) connect Queue10_UInt8_22.io.enq.bits, _T_2377 node _T_2378 = eq(UInt<5>(0h17), idx_24) when _T_2378 : node _T_2379 = shl(UInt<5>(0h18), 3) node _T_2380 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2379) connect Queue10_UInt8_23.io.enq.bits, _T_2380 node _T_2381 = eq(UInt<5>(0h18), idx_24) when _T_2381 : node _T_2382 = shl(UInt<5>(0h18), 3) node _T_2383 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2382) connect Queue10_UInt8_24.io.enq.bits, _T_2383 node _T_2384 = eq(UInt<5>(0h19), idx_24) when _T_2384 : node _T_2385 = shl(UInt<5>(0h18), 3) node _T_2386 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2385) connect Queue10_UInt8_25.io.enq.bits, _T_2386 node _T_2387 = eq(UInt<5>(0h1a), idx_24) when _T_2387 : node _T_2388 = shl(UInt<5>(0h18), 3) node _T_2389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2388) connect Queue10_UInt8_26.io.enq.bits, _T_2389 node _T_2390 = eq(UInt<5>(0h1b), idx_24) when _T_2390 : node _T_2391 = shl(UInt<5>(0h18), 3) node _T_2392 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2391) connect Queue10_UInt8_27.io.enq.bits, _T_2392 node _T_2393 = eq(UInt<5>(0h1c), idx_24) when _T_2393 : node _T_2394 = shl(UInt<5>(0h18), 3) node _T_2395 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2394) connect Queue10_UInt8_28.io.enq.bits, _T_2395 node _T_2396 = eq(UInt<5>(0h1d), idx_24) when _T_2396 : node _T_2397 = shl(UInt<5>(0h18), 3) node _T_2398 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2397) connect Queue10_UInt8_29.io.enq.bits, _T_2398 node _T_2399 = eq(UInt<5>(0h1e), idx_24) when _T_2399 : node _T_2400 = shl(UInt<5>(0h18), 3) node _T_2401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2400) connect Queue10_UInt8_30.io.enq.bits, _T_2401 node _T_2402 = eq(UInt<5>(0h1f), idx_24) when _T_2402 : node _T_2403 = shl(UInt<5>(0h18), 3) node _T_2404 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2403) connect Queue10_UInt8_31.io.enq.bits, _T_2404 node _idx_T_25 = add(write_start_index, UInt<5>(0h19)) node idx_25 = rem(_idx_T_25, UInt<6>(0h20)) node _T_2405 = eq(UInt<1>(0h0), idx_25) when _T_2405 : node _T_2406 = shl(UInt<5>(0h19), 3) node _T_2407 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2406) connect Queue10_UInt8.io.enq.bits, _T_2407 node _T_2408 = eq(UInt<1>(0h1), idx_25) when _T_2408 : node _T_2409 = shl(UInt<5>(0h19), 3) node _T_2410 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2409) connect Queue10_UInt8_1.io.enq.bits, _T_2410 node _T_2411 = eq(UInt<2>(0h2), idx_25) when _T_2411 : node _T_2412 = shl(UInt<5>(0h19), 3) node _T_2413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2412) connect Queue10_UInt8_2.io.enq.bits, _T_2413 node _T_2414 = eq(UInt<2>(0h3), idx_25) when _T_2414 : node _T_2415 = shl(UInt<5>(0h19), 3) node _T_2416 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2415) connect Queue10_UInt8_3.io.enq.bits, _T_2416 node _T_2417 = eq(UInt<3>(0h4), idx_25) when _T_2417 : node _T_2418 = shl(UInt<5>(0h19), 3) node _T_2419 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2418) connect Queue10_UInt8_4.io.enq.bits, _T_2419 node _T_2420 = eq(UInt<3>(0h5), idx_25) when _T_2420 : node _T_2421 = shl(UInt<5>(0h19), 3) node _T_2422 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2421) connect Queue10_UInt8_5.io.enq.bits, _T_2422 node _T_2423 = eq(UInt<3>(0h6), idx_25) when _T_2423 : node _T_2424 = shl(UInt<5>(0h19), 3) node _T_2425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2424) connect Queue10_UInt8_6.io.enq.bits, _T_2425 node _T_2426 = eq(UInt<3>(0h7), idx_25) when _T_2426 : node _T_2427 = shl(UInt<5>(0h19), 3) node _T_2428 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2427) connect Queue10_UInt8_7.io.enq.bits, _T_2428 node _T_2429 = eq(UInt<4>(0h8), idx_25) when _T_2429 : node _T_2430 = shl(UInt<5>(0h19), 3) node _T_2431 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2430) connect Queue10_UInt8_8.io.enq.bits, _T_2431 node _T_2432 = eq(UInt<4>(0h9), idx_25) when _T_2432 : node _T_2433 = shl(UInt<5>(0h19), 3) node _T_2434 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2433) connect Queue10_UInt8_9.io.enq.bits, _T_2434 node _T_2435 = eq(UInt<4>(0ha), idx_25) when _T_2435 : node _T_2436 = shl(UInt<5>(0h19), 3) node _T_2437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2436) connect Queue10_UInt8_10.io.enq.bits, _T_2437 node _T_2438 = eq(UInt<4>(0hb), idx_25) when _T_2438 : node _T_2439 = shl(UInt<5>(0h19), 3) node _T_2440 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2439) connect Queue10_UInt8_11.io.enq.bits, _T_2440 node _T_2441 = eq(UInt<4>(0hc), idx_25) when _T_2441 : node _T_2442 = shl(UInt<5>(0h19), 3) node _T_2443 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2442) connect Queue10_UInt8_12.io.enq.bits, _T_2443 node _T_2444 = eq(UInt<4>(0hd), idx_25) when _T_2444 : node _T_2445 = shl(UInt<5>(0h19), 3) node _T_2446 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2445) connect Queue10_UInt8_13.io.enq.bits, _T_2446 node _T_2447 = eq(UInt<4>(0he), idx_25) when _T_2447 : node _T_2448 = shl(UInt<5>(0h19), 3) node _T_2449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2448) connect Queue10_UInt8_14.io.enq.bits, _T_2449 node _T_2450 = eq(UInt<4>(0hf), idx_25) when _T_2450 : node _T_2451 = shl(UInt<5>(0h19), 3) node _T_2452 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2451) connect Queue10_UInt8_15.io.enq.bits, _T_2452 node _T_2453 = eq(UInt<5>(0h10), idx_25) when _T_2453 : node _T_2454 = shl(UInt<5>(0h19), 3) node _T_2455 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2454) connect Queue10_UInt8_16.io.enq.bits, _T_2455 node _T_2456 = eq(UInt<5>(0h11), idx_25) when _T_2456 : node _T_2457 = shl(UInt<5>(0h19), 3) node _T_2458 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2457) connect Queue10_UInt8_17.io.enq.bits, _T_2458 node _T_2459 = eq(UInt<5>(0h12), idx_25) when _T_2459 : node _T_2460 = shl(UInt<5>(0h19), 3) node _T_2461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2460) connect Queue10_UInt8_18.io.enq.bits, _T_2461 node _T_2462 = eq(UInt<5>(0h13), idx_25) when _T_2462 : node _T_2463 = shl(UInt<5>(0h19), 3) node _T_2464 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2463) connect Queue10_UInt8_19.io.enq.bits, _T_2464 node _T_2465 = eq(UInt<5>(0h14), idx_25) when _T_2465 : node _T_2466 = shl(UInt<5>(0h19), 3) node _T_2467 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2466) connect Queue10_UInt8_20.io.enq.bits, _T_2467 node _T_2468 = eq(UInt<5>(0h15), idx_25) when _T_2468 : node _T_2469 = shl(UInt<5>(0h19), 3) node _T_2470 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2469) connect Queue10_UInt8_21.io.enq.bits, _T_2470 node _T_2471 = eq(UInt<5>(0h16), idx_25) when _T_2471 : node _T_2472 = shl(UInt<5>(0h19), 3) node _T_2473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2472) connect Queue10_UInt8_22.io.enq.bits, _T_2473 node _T_2474 = eq(UInt<5>(0h17), idx_25) when _T_2474 : node _T_2475 = shl(UInt<5>(0h19), 3) node _T_2476 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2475) connect Queue10_UInt8_23.io.enq.bits, _T_2476 node _T_2477 = eq(UInt<5>(0h18), idx_25) when _T_2477 : node _T_2478 = shl(UInt<5>(0h19), 3) node _T_2479 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2478) connect Queue10_UInt8_24.io.enq.bits, _T_2479 node _T_2480 = eq(UInt<5>(0h19), idx_25) when _T_2480 : node _T_2481 = shl(UInt<5>(0h19), 3) node _T_2482 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2481) connect Queue10_UInt8_25.io.enq.bits, _T_2482 node _T_2483 = eq(UInt<5>(0h1a), idx_25) when _T_2483 : node _T_2484 = shl(UInt<5>(0h19), 3) node _T_2485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2484) connect Queue10_UInt8_26.io.enq.bits, _T_2485 node _T_2486 = eq(UInt<5>(0h1b), idx_25) when _T_2486 : node _T_2487 = shl(UInt<5>(0h19), 3) node _T_2488 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2487) connect Queue10_UInt8_27.io.enq.bits, _T_2488 node _T_2489 = eq(UInt<5>(0h1c), idx_25) when _T_2489 : node _T_2490 = shl(UInt<5>(0h19), 3) node _T_2491 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2490) connect Queue10_UInt8_28.io.enq.bits, _T_2491 node _T_2492 = eq(UInt<5>(0h1d), idx_25) when _T_2492 : node _T_2493 = shl(UInt<5>(0h19), 3) node _T_2494 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2493) connect Queue10_UInt8_29.io.enq.bits, _T_2494 node _T_2495 = eq(UInt<5>(0h1e), idx_25) when _T_2495 : node _T_2496 = shl(UInt<5>(0h19), 3) node _T_2497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2496) connect Queue10_UInt8_30.io.enq.bits, _T_2497 node _T_2498 = eq(UInt<5>(0h1f), idx_25) when _T_2498 : node _T_2499 = shl(UInt<5>(0h19), 3) node _T_2500 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2499) connect Queue10_UInt8_31.io.enq.bits, _T_2500 node _idx_T_26 = add(write_start_index, UInt<5>(0h1a)) node idx_26 = rem(_idx_T_26, UInt<6>(0h20)) node _T_2501 = eq(UInt<1>(0h0), idx_26) when _T_2501 : node _T_2502 = shl(UInt<5>(0h1a), 3) node _T_2503 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2502) connect Queue10_UInt8.io.enq.bits, _T_2503 node _T_2504 = eq(UInt<1>(0h1), idx_26) when _T_2504 : node _T_2505 = shl(UInt<5>(0h1a), 3) node _T_2506 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2505) connect Queue10_UInt8_1.io.enq.bits, _T_2506 node _T_2507 = eq(UInt<2>(0h2), idx_26) when _T_2507 : node _T_2508 = shl(UInt<5>(0h1a), 3) node _T_2509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2508) connect Queue10_UInt8_2.io.enq.bits, _T_2509 node _T_2510 = eq(UInt<2>(0h3), idx_26) when _T_2510 : node _T_2511 = shl(UInt<5>(0h1a), 3) node _T_2512 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2511) connect Queue10_UInt8_3.io.enq.bits, _T_2512 node _T_2513 = eq(UInt<3>(0h4), idx_26) when _T_2513 : node _T_2514 = shl(UInt<5>(0h1a), 3) node _T_2515 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2514) connect Queue10_UInt8_4.io.enq.bits, _T_2515 node _T_2516 = eq(UInt<3>(0h5), idx_26) when _T_2516 : node _T_2517 = shl(UInt<5>(0h1a), 3) node _T_2518 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2517) connect Queue10_UInt8_5.io.enq.bits, _T_2518 node _T_2519 = eq(UInt<3>(0h6), idx_26) when _T_2519 : node _T_2520 = shl(UInt<5>(0h1a), 3) node _T_2521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2520) connect Queue10_UInt8_6.io.enq.bits, _T_2521 node _T_2522 = eq(UInt<3>(0h7), idx_26) when _T_2522 : node _T_2523 = shl(UInt<5>(0h1a), 3) node _T_2524 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2523) connect Queue10_UInt8_7.io.enq.bits, _T_2524 node _T_2525 = eq(UInt<4>(0h8), idx_26) when _T_2525 : node _T_2526 = shl(UInt<5>(0h1a), 3) node _T_2527 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2526) connect Queue10_UInt8_8.io.enq.bits, _T_2527 node _T_2528 = eq(UInt<4>(0h9), idx_26) when _T_2528 : node _T_2529 = shl(UInt<5>(0h1a), 3) node _T_2530 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2529) connect Queue10_UInt8_9.io.enq.bits, _T_2530 node _T_2531 = eq(UInt<4>(0ha), idx_26) when _T_2531 : node _T_2532 = shl(UInt<5>(0h1a), 3) node _T_2533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2532) connect Queue10_UInt8_10.io.enq.bits, _T_2533 node _T_2534 = eq(UInt<4>(0hb), idx_26) when _T_2534 : node _T_2535 = shl(UInt<5>(0h1a), 3) node _T_2536 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2535) connect Queue10_UInt8_11.io.enq.bits, _T_2536 node _T_2537 = eq(UInt<4>(0hc), idx_26) when _T_2537 : node _T_2538 = shl(UInt<5>(0h1a), 3) node _T_2539 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2538) connect Queue10_UInt8_12.io.enq.bits, _T_2539 node _T_2540 = eq(UInt<4>(0hd), idx_26) when _T_2540 : node _T_2541 = shl(UInt<5>(0h1a), 3) node _T_2542 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2541) connect Queue10_UInt8_13.io.enq.bits, _T_2542 node _T_2543 = eq(UInt<4>(0he), idx_26) when _T_2543 : node _T_2544 = shl(UInt<5>(0h1a), 3) node _T_2545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2544) connect Queue10_UInt8_14.io.enq.bits, _T_2545 node _T_2546 = eq(UInt<4>(0hf), idx_26) when _T_2546 : node _T_2547 = shl(UInt<5>(0h1a), 3) node _T_2548 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2547) connect Queue10_UInt8_15.io.enq.bits, _T_2548 node _T_2549 = eq(UInt<5>(0h10), idx_26) when _T_2549 : node _T_2550 = shl(UInt<5>(0h1a), 3) node _T_2551 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2550) connect Queue10_UInt8_16.io.enq.bits, _T_2551 node _T_2552 = eq(UInt<5>(0h11), idx_26) when _T_2552 : node _T_2553 = shl(UInt<5>(0h1a), 3) node _T_2554 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2553) connect Queue10_UInt8_17.io.enq.bits, _T_2554 node _T_2555 = eq(UInt<5>(0h12), idx_26) when _T_2555 : node _T_2556 = shl(UInt<5>(0h1a), 3) node _T_2557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2556) connect Queue10_UInt8_18.io.enq.bits, _T_2557 node _T_2558 = eq(UInt<5>(0h13), idx_26) when _T_2558 : node _T_2559 = shl(UInt<5>(0h1a), 3) node _T_2560 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2559) connect Queue10_UInt8_19.io.enq.bits, _T_2560 node _T_2561 = eq(UInt<5>(0h14), idx_26) when _T_2561 : node _T_2562 = shl(UInt<5>(0h1a), 3) node _T_2563 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2562) connect Queue10_UInt8_20.io.enq.bits, _T_2563 node _T_2564 = eq(UInt<5>(0h15), idx_26) when _T_2564 : node _T_2565 = shl(UInt<5>(0h1a), 3) node _T_2566 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2565) connect Queue10_UInt8_21.io.enq.bits, _T_2566 node _T_2567 = eq(UInt<5>(0h16), idx_26) when _T_2567 : node _T_2568 = shl(UInt<5>(0h1a), 3) node _T_2569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2568) connect Queue10_UInt8_22.io.enq.bits, _T_2569 node _T_2570 = eq(UInt<5>(0h17), idx_26) when _T_2570 : node _T_2571 = shl(UInt<5>(0h1a), 3) node _T_2572 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2571) connect Queue10_UInt8_23.io.enq.bits, _T_2572 node _T_2573 = eq(UInt<5>(0h18), idx_26) when _T_2573 : node _T_2574 = shl(UInt<5>(0h1a), 3) node _T_2575 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2574) connect Queue10_UInt8_24.io.enq.bits, _T_2575 node _T_2576 = eq(UInt<5>(0h19), idx_26) when _T_2576 : node _T_2577 = shl(UInt<5>(0h1a), 3) node _T_2578 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2577) connect Queue10_UInt8_25.io.enq.bits, _T_2578 node _T_2579 = eq(UInt<5>(0h1a), idx_26) when _T_2579 : node _T_2580 = shl(UInt<5>(0h1a), 3) node _T_2581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2580) connect Queue10_UInt8_26.io.enq.bits, _T_2581 node _T_2582 = eq(UInt<5>(0h1b), idx_26) when _T_2582 : node _T_2583 = shl(UInt<5>(0h1a), 3) node _T_2584 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2583) connect Queue10_UInt8_27.io.enq.bits, _T_2584 node _T_2585 = eq(UInt<5>(0h1c), idx_26) when _T_2585 : node _T_2586 = shl(UInt<5>(0h1a), 3) node _T_2587 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2586) connect Queue10_UInt8_28.io.enq.bits, _T_2587 node _T_2588 = eq(UInt<5>(0h1d), idx_26) when _T_2588 : node _T_2589 = shl(UInt<5>(0h1a), 3) node _T_2590 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2589) connect Queue10_UInt8_29.io.enq.bits, _T_2590 node _T_2591 = eq(UInt<5>(0h1e), idx_26) when _T_2591 : node _T_2592 = shl(UInt<5>(0h1a), 3) node _T_2593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2592) connect Queue10_UInt8_30.io.enq.bits, _T_2593 node _T_2594 = eq(UInt<5>(0h1f), idx_26) when _T_2594 : node _T_2595 = shl(UInt<5>(0h1a), 3) node _T_2596 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2595) connect Queue10_UInt8_31.io.enq.bits, _T_2596 node _idx_T_27 = add(write_start_index, UInt<5>(0h1b)) node idx_27 = rem(_idx_T_27, UInt<6>(0h20)) node _T_2597 = eq(UInt<1>(0h0), idx_27) when _T_2597 : node _T_2598 = shl(UInt<5>(0h1b), 3) node _T_2599 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2598) connect Queue10_UInt8.io.enq.bits, _T_2599 node _T_2600 = eq(UInt<1>(0h1), idx_27) when _T_2600 : node _T_2601 = shl(UInt<5>(0h1b), 3) node _T_2602 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2601) connect Queue10_UInt8_1.io.enq.bits, _T_2602 node _T_2603 = eq(UInt<2>(0h2), idx_27) when _T_2603 : node _T_2604 = shl(UInt<5>(0h1b), 3) node _T_2605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2604) connect Queue10_UInt8_2.io.enq.bits, _T_2605 node _T_2606 = eq(UInt<2>(0h3), idx_27) when _T_2606 : node _T_2607 = shl(UInt<5>(0h1b), 3) node _T_2608 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2607) connect Queue10_UInt8_3.io.enq.bits, _T_2608 node _T_2609 = eq(UInt<3>(0h4), idx_27) when _T_2609 : node _T_2610 = shl(UInt<5>(0h1b), 3) node _T_2611 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2610) connect Queue10_UInt8_4.io.enq.bits, _T_2611 node _T_2612 = eq(UInt<3>(0h5), idx_27) when _T_2612 : node _T_2613 = shl(UInt<5>(0h1b), 3) node _T_2614 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2613) connect Queue10_UInt8_5.io.enq.bits, _T_2614 node _T_2615 = eq(UInt<3>(0h6), idx_27) when _T_2615 : node _T_2616 = shl(UInt<5>(0h1b), 3) node _T_2617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2616) connect Queue10_UInt8_6.io.enq.bits, _T_2617 node _T_2618 = eq(UInt<3>(0h7), idx_27) when _T_2618 : node _T_2619 = shl(UInt<5>(0h1b), 3) node _T_2620 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2619) connect Queue10_UInt8_7.io.enq.bits, _T_2620 node _T_2621 = eq(UInt<4>(0h8), idx_27) when _T_2621 : node _T_2622 = shl(UInt<5>(0h1b), 3) node _T_2623 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2622) connect Queue10_UInt8_8.io.enq.bits, _T_2623 node _T_2624 = eq(UInt<4>(0h9), idx_27) when _T_2624 : node _T_2625 = shl(UInt<5>(0h1b), 3) node _T_2626 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2625) connect Queue10_UInt8_9.io.enq.bits, _T_2626 node _T_2627 = eq(UInt<4>(0ha), idx_27) when _T_2627 : node _T_2628 = shl(UInt<5>(0h1b), 3) node _T_2629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2628) connect Queue10_UInt8_10.io.enq.bits, _T_2629 node _T_2630 = eq(UInt<4>(0hb), idx_27) when _T_2630 : node _T_2631 = shl(UInt<5>(0h1b), 3) node _T_2632 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2631) connect Queue10_UInt8_11.io.enq.bits, _T_2632 node _T_2633 = eq(UInt<4>(0hc), idx_27) when _T_2633 : node _T_2634 = shl(UInt<5>(0h1b), 3) node _T_2635 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2634) connect Queue10_UInt8_12.io.enq.bits, _T_2635 node _T_2636 = eq(UInt<4>(0hd), idx_27) when _T_2636 : node _T_2637 = shl(UInt<5>(0h1b), 3) node _T_2638 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2637) connect Queue10_UInt8_13.io.enq.bits, _T_2638 node _T_2639 = eq(UInt<4>(0he), idx_27) when _T_2639 : node _T_2640 = shl(UInt<5>(0h1b), 3) node _T_2641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2640) connect Queue10_UInt8_14.io.enq.bits, _T_2641 node _T_2642 = eq(UInt<4>(0hf), idx_27) when _T_2642 : node _T_2643 = shl(UInt<5>(0h1b), 3) node _T_2644 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2643) connect Queue10_UInt8_15.io.enq.bits, _T_2644 node _T_2645 = eq(UInt<5>(0h10), idx_27) when _T_2645 : node _T_2646 = shl(UInt<5>(0h1b), 3) node _T_2647 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2646) connect Queue10_UInt8_16.io.enq.bits, _T_2647 node _T_2648 = eq(UInt<5>(0h11), idx_27) when _T_2648 : node _T_2649 = shl(UInt<5>(0h1b), 3) node _T_2650 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2649) connect Queue10_UInt8_17.io.enq.bits, _T_2650 node _T_2651 = eq(UInt<5>(0h12), idx_27) when _T_2651 : node _T_2652 = shl(UInt<5>(0h1b), 3) node _T_2653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2652) connect Queue10_UInt8_18.io.enq.bits, _T_2653 node _T_2654 = eq(UInt<5>(0h13), idx_27) when _T_2654 : node _T_2655 = shl(UInt<5>(0h1b), 3) node _T_2656 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2655) connect Queue10_UInt8_19.io.enq.bits, _T_2656 node _T_2657 = eq(UInt<5>(0h14), idx_27) when _T_2657 : node _T_2658 = shl(UInt<5>(0h1b), 3) node _T_2659 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2658) connect Queue10_UInt8_20.io.enq.bits, _T_2659 node _T_2660 = eq(UInt<5>(0h15), idx_27) when _T_2660 : node _T_2661 = shl(UInt<5>(0h1b), 3) node _T_2662 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2661) connect Queue10_UInt8_21.io.enq.bits, _T_2662 node _T_2663 = eq(UInt<5>(0h16), idx_27) when _T_2663 : node _T_2664 = shl(UInt<5>(0h1b), 3) node _T_2665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2664) connect Queue10_UInt8_22.io.enq.bits, _T_2665 node _T_2666 = eq(UInt<5>(0h17), idx_27) when _T_2666 : node _T_2667 = shl(UInt<5>(0h1b), 3) node _T_2668 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2667) connect Queue10_UInt8_23.io.enq.bits, _T_2668 node _T_2669 = eq(UInt<5>(0h18), idx_27) when _T_2669 : node _T_2670 = shl(UInt<5>(0h1b), 3) node _T_2671 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2670) connect Queue10_UInt8_24.io.enq.bits, _T_2671 node _T_2672 = eq(UInt<5>(0h19), idx_27) when _T_2672 : node _T_2673 = shl(UInt<5>(0h1b), 3) node _T_2674 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2673) connect Queue10_UInt8_25.io.enq.bits, _T_2674 node _T_2675 = eq(UInt<5>(0h1a), idx_27) when _T_2675 : node _T_2676 = shl(UInt<5>(0h1b), 3) node _T_2677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2676) connect Queue10_UInt8_26.io.enq.bits, _T_2677 node _T_2678 = eq(UInt<5>(0h1b), idx_27) when _T_2678 : node _T_2679 = shl(UInt<5>(0h1b), 3) node _T_2680 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2679) connect Queue10_UInt8_27.io.enq.bits, _T_2680 node _T_2681 = eq(UInt<5>(0h1c), idx_27) when _T_2681 : node _T_2682 = shl(UInt<5>(0h1b), 3) node _T_2683 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2682) connect Queue10_UInt8_28.io.enq.bits, _T_2683 node _T_2684 = eq(UInt<5>(0h1d), idx_27) when _T_2684 : node _T_2685 = shl(UInt<5>(0h1b), 3) node _T_2686 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2685) connect Queue10_UInt8_29.io.enq.bits, _T_2686 node _T_2687 = eq(UInt<5>(0h1e), idx_27) when _T_2687 : node _T_2688 = shl(UInt<5>(0h1b), 3) node _T_2689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2688) connect Queue10_UInt8_30.io.enq.bits, _T_2689 node _T_2690 = eq(UInt<5>(0h1f), idx_27) when _T_2690 : node _T_2691 = shl(UInt<5>(0h1b), 3) node _T_2692 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2691) connect Queue10_UInt8_31.io.enq.bits, _T_2692 node _idx_T_28 = add(write_start_index, UInt<5>(0h1c)) node idx_28 = rem(_idx_T_28, UInt<6>(0h20)) node _T_2693 = eq(UInt<1>(0h0), idx_28) when _T_2693 : node _T_2694 = shl(UInt<5>(0h1c), 3) node _T_2695 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2694) connect Queue10_UInt8.io.enq.bits, _T_2695 node _T_2696 = eq(UInt<1>(0h1), idx_28) when _T_2696 : node _T_2697 = shl(UInt<5>(0h1c), 3) node _T_2698 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2697) connect Queue10_UInt8_1.io.enq.bits, _T_2698 node _T_2699 = eq(UInt<2>(0h2), idx_28) when _T_2699 : node _T_2700 = shl(UInt<5>(0h1c), 3) node _T_2701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2700) connect Queue10_UInt8_2.io.enq.bits, _T_2701 node _T_2702 = eq(UInt<2>(0h3), idx_28) when _T_2702 : node _T_2703 = shl(UInt<5>(0h1c), 3) node _T_2704 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2703) connect Queue10_UInt8_3.io.enq.bits, _T_2704 node _T_2705 = eq(UInt<3>(0h4), idx_28) when _T_2705 : node _T_2706 = shl(UInt<5>(0h1c), 3) node _T_2707 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2706) connect Queue10_UInt8_4.io.enq.bits, _T_2707 node _T_2708 = eq(UInt<3>(0h5), idx_28) when _T_2708 : node _T_2709 = shl(UInt<5>(0h1c), 3) node _T_2710 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2709) connect Queue10_UInt8_5.io.enq.bits, _T_2710 node _T_2711 = eq(UInt<3>(0h6), idx_28) when _T_2711 : node _T_2712 = shl(UInt<5>(0h1c), 3) node _T_2713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2712) connect Queue10_UInt8_6.io.enq.bits, _T_2713 node _T_2714 = eq(UInt<3>(0h7), idx_28) when _T_2714 : node _T_2715 = shl(UInt<5>(0h1c), 3) node _T_2716 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2715) connect Queue10_UInt8_7.io.enq.bits, _T_2716 node _T_2717 = eq(UInt<4>(0h8), idx_28) when _T_2717 : node _T_2718 = shl(UInt<5>(0h1c), 3) node _T_2719 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2718) connect Queue10_UInt8_8.io.enq.bits, _T_2719 node _T_2720 = eq(UInt<4>(0h9), idx_28) when _T_2720 : node _T_2721 = shl(UInt<5>(0h1c), 3) node _T_2722 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2721) connect Queue10_UInt8_9.io.enq.bits, _T_2722 node _T_2723 = eq(UInt<4>(0ha), idx_28) when _T_2723 : node _T_2724 = shl(UInt<5>(0h1c), 3) node _T_2725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2724) connect Queue10_UInt8_10.io.enq.bits, _T_2725 node _T_2726 = eq(UInt<4>(0hb), idx_28) when _T_2726 : node _T_2727 = shl(UInt<5>(0h1c), 3) node _T_2728 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2727) connect Queue10_UInt8_11.io.enq.bits, _T_2728 node _T_2729 = eq(UInt<4>(0hc), idx_28) when _T_2729 : node _T_2730 = shl(UInt<5>(0h1c), 3) node _T_2731 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2730) connect Queue10_UInt8_12.io.enq.bits, _T_2731 node _T_2732 = eq(UInt<4>(0hd), idx_28) when _T_2732 : node _T_2733 = shl(UInt<5>(0h1c), 3) node _T_2734 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2733) connect Queue10_UInt8_13.io.enq.bits, _T_2734 node _T_2735 = eq(UInt<4>(0he), idx_28) when _T_2735 : node _T_2736 = shl(UInt<5>(0h1c), 3) node _T_2737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2736) connect Queue10_UInt8_14.io.enq.bits, _T_2737 node _T_2738 = eq(UInt<4>(0hf), idx_28) when _T_2738 : node _T_2739 = shl(UInt<5>(0h1c), 3) node _T_2740 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2739) connect Queue10_UInt8_15.io.enq.bits, _T_2740 node _T_2741 = eq(UInt<5>(0h10), idx_28) when _T_2741 : node _T_2742 = shl(UInt<5>(0h1c), 3) node _T_2743 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2742) connect Queue10_UInt8_16.io.enq.bits, _T_2743 node _T_2744 = eq(UInt<5>(0h11), idx_28) when _T_2744 : node _T_2745 = shl(UInt<5>(0h1c), 3) node _T_2746 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2745) connect Queue10_UInt8_17.io.enq.bits, _T_2746 node _T_2747 = eq(UInt<5>(0h12), idx_28) when _T_2747 : node _T_2748 = shl(UInt<5>(0h1c), 3) node _T_2749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2748) connect Queue10_UInt8_18.io.enq.bits, _T_2749 node _T_2750 = eq(UInt<5>(0h13), idx_28) when _T_2750 : node _T_2751 = shl(UInt<5>(0h1c), 3) node _T_2752 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2751) connect Queue10_UInt8_19.io.enq.bits, _T_2752 node _T_2753 = eq(UInt<5>(0h14), idx_28) when _T_2753 : node _T_2754 = shl(UInt<5>(0h1c), 3) node _T_2755 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2754) connect Queue10_UInt8_20.io.enq.bits, _T_2755 node _T_2756 = eq(UInt<5>(0h15), idx_28) when _T_2756 : node _T_2757 = shl(UInt<5>(0h1c), 3) node _T_2758 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2757) connect Queue10_UInt8_21.io.enq.bits, _T_2758 node _T_2759 = eq(UInt<5>(0h16), idx_28) when _T_2759 : node _T_2760 = shl(UInt<5>(0h1c), 3) node _T_2761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2760) connect Queue10_UInt8_22.io.enq.bits, _T_2761 node _T_2762 = eq(UInt<5>(0h17), idx_28) when _T_2762 : node _T_2763 = shl(UInt<5>(0h1c), 3) node _T_2764 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2763) connect Queue10_UInt8_23.io.enq.bits, _T_2764 node _T_2765 = eq(UInt<5>(0h18), idx_28) when _T_2765 : node _T_2766 = shl(UInt<5>(0h1c), 3) node _T_2767 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2766) connect Queue10_UInt8_24.io.enq.bits, _T_2767 node _T_2768 = eq(UInt<5>(0h19), idx_28) when _T_2768 : node _T_2769 = shl(UInt<5>(0h1c), 3) node _T_2770 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2769) connect Queue10_UInt8_25.io.enq.bits, _T_2770 node _T_2771 = eq(UInt<5>(0h1a), idx_28) when _T_2771 : node _T_2772 = shl(UInt<5>(0h1c), 3) node _T_2773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2772) connect Queue10_UInt8_26.io.enq.bits, _T_2773 node _T_2774 = eq(UInt<5>(0h1b), idx_28) when _T_2774 : node _T_2775 = shl(UInt<5>(0h1c), 3) node _T_2776 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2775) connect Queue10_UInt8_27.io.enq.bits, _T_2776 node _T_2777 = eq(UInt<5>(0h1c), idx_28) when _T_2777 : node _T_2778 = shl(UInt<5>(0h1c), 3) node _T_2779 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2778) connect Queue10_UInt8_28.io.enq.bits, _T_2779 node _T_2780 = eq(UInt<5>(0h1d), idx_28) when _T_2780 : node _T_2781 = shl(UInt<5>(0h1c), 3) node _T_2782 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2781) connect Queue10_UInt8_29.io.enq.bits, _T_2782 node _T_2783 = eq(UInt<5>(0h1e), idx_28) when _T_2783 : node _T_2784 = shl(UInt<5>(0h1c), 3) node _T_2785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2784) connect Queue10_UInt8_30.io.enq.bits, _T_2785 node _T_2786 = eq(UInt<5>(0h1f), idx_28) when _T_2786 : node _T_2787 = shl(UInt<5>(0h1c), 3) node _T_2788 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2787) connect Queue10_UInt8_31.io.enq.bits, _T_2788 node _idx_T_29 = add(write_start_index, UInt<5>(0h1d)) node idx_29 = rem(_idx_T_29, UInt<6>(0h20)) node _T_2789 = eq(UInt<1>(0h0), idx_29) when _T_2789 : node _T_2790 = shl(UInt<5>(0h1d), 3) node _T_2791 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2790) connect Queue10_UInt8.io.enq.bits, _T_2791 node _T_2792 = eq(UInt<1>(0h1), idx_29) when _T_2792 : node _T_2793 = shl(UInt<5>(0h1d), 3) node _T_2794 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2793) connect Queue10_UInt8_1.io.enq.bits, _T_2794 node _T_2795 = eq(UInt<2>(0h2), idx_29) when _T_2795 : node _T_2796 = shl(UInt<5>(0h1d), 3) node _T_2797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2796) connect Queue10_UInt8_2.io.enq.bits, _T_2797 node _T_2798 = eq(UInt<2>(0h3), idx_29) when _T_2798 : node _T_2799 = shl(UInt<5>(0h1d), 3) node _T_2800 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2799) connect Queue10_UInt8_3.io.enq.bits, _T_2800 node _T_2801 = eq(UInt<3>(0h4), idx_29) when _T_2801 : node _T_2802 = shl(UInt<5>(0h1d), 3) node _T_2803 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2802) connect Queue10_UInt8_4.io.enq.bits, _T_2803 node _T_2804 = eq(UInt<3>(0h5), idx_29) when _T_2804 : node _T_2805 = shl(UInt<5>(0h1d), 3) node _T_2806 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2805) connect Queue10_UInt8_5.io.enq.bits, _T_2806 node _T_2807 = eq(UInt<3>(0h6), idx_29) when _T_2807 : node _T_2808 = shl(UInt<5>(0h1d), 3) node _T_2809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2808) connect Queue10_UInt8_6.io.enq.bits, _T_2809 node _T_2810 = eq(UInt<3>(0h7), idx_29) when _T_2810 : node _T_2811 = shl(UInt<5>(0h1d), 3) node _T_2812 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2811) connect Queue10_UInt8_7.io.enq.bits, _T_2812 node _T_2813 = eq(UInt<4>(0h8), idx_29) when _T_2813 : node _T_2814 = shl(UInt<5>(0h1d), 3) node _T_2815 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2814) connect Queue10_UInt8_8.io.enq.bits, _T_2815 node _T_2816 = eq(UInt<4>(0h9), idx_29) when _T_2816 : node _T_2817 = shl(UInt<5>(0h1d), 3) node _T_2818 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2817) connect Queue10_UInt8_9.io.enq.bits, _T_2818 node _T_2819 = eq(UInt<4>(0ha), idx_29) when _T_2819 : node _T_2820 = shl(UInt<5>(0h1d), 3) node _T_2821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2820) connect Queue10_UInt8_10.io.enq.bits, _T_2821 node _T_2822 = eq(UInt<4>(0hb), idx_29) when _T_2822 : node _T_2823 = shl(UInt<5>(0h1d), 3) node _T_2824 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2823) connect Queue10_UInt8_11.io.enq.bits, _T_2824 node _T_2825 = eq(UInt<4>(0hc), idx_29) when _T_2825 : node _T_2826 = shl(UInt<5>(0h1d), 3) node _T_2827 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2826) connect Queue10_UInt8_12.io.enq.bits, _T_2827 node _T_2828 = eq(UInt<4>(0hd), idx_29) when _T_2828 : node _T_2829 = shl(UInt<5>(0h1d), 3) node _T_2830 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2829) connect Queue10_UInt8_13.io.enq.bits, _T_2830 node _T_2831 = eq(UInt<4>(0he), idx_29) when _T_2831 : node _T_2832 = shl(UInt<5>(0h1d), 3) node _T_2833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2832) connect Queue10_UInt8_14.io.enq.bits, _T_2833 node _T_2834 = eq(UInt<4>(0hf), idx_29) when _T_2834 : node _T_2835 = shl(UInt<5>(0h1d), 3) node _T_2836 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2835) connect Queue10_UInt8_15.io.enq.bits, _T_2836 node _T_2837 = eq(UInt<5>(0h10), idx_29) when _T_2837 : node _T_2838 = shl(UInt<5>(0h1d), 3) node _T_2839 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2838) connect Queue10_UInt8_16.io.enq.bits, _T_2839 node _T_2840 = eq(UInt<5>(0h11), idx_29) when _T_2840 : node _T_2841 = shl(UInt<5>(0h1d), 3) node _T_2842 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2841) connect Queue10_UInt8_17.io.enq.bits, _T_2842 node _T_2843 = eq(UInt<5>(0h12), idx_29) when _T_2843 : node _T_2844 = shl(UInt<5>(0h1d), 3) node _T_2845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2844) connect Queue10_UInt8_18.io.enq.bits, _T_2845 node _T_2846 = eq(UInt<5>(0h13), idx_29) when _T_2846 : node _T_2847 = shl(UInt<5>(0h1d), 3) node _T_2848 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2847) connect Queue10_UInt8_19.io.enq.bits, _T_2848 node _T_2849 = eq(UInt<5>(0h14), idx_29) when _T_2849 : node _T_2850 = shl(UInt<5>(0h1d), 3) node _T_2851 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2850) connect Queue10_UInt8_20.io.enq.bits, _T_2851 node _T_2852 = eq(UInt<5>(0h15), idx_29) when _T_2852 : node _T_2853 = shl(UInt<5>(0h1d), 3) node _T_2854 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2853) connect Queue10_UInt8_21.io.enq.bits, _T_2854 node _T_2855 = eq(UInt<5>(0h16), idx_29) when _T_2855 : node _T_2856 = shl(UInt<5>(0h1d), 3) node _T_2857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2856) connect Queue10_UInt8_22.io.enq.bits, _T_2857 node _T_2858 = eq(UInt<5>(0h17), idx_29) when _T_2858 : node _T_2859 = shl(UInt<5>(0h1d), 3) node _T_2860 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2859) connect Queue10_UInt8_23.io.enq.bits, _T_2860 node _T_2861 = eq(UInt<5>(0h18), idx_29) when _T_2861 : node _T_2862 = shl(UInt<5>(0h1d), 3) node _T_2863 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2862) connect Queue10_UInt8_24.io.enq.bits, _T_2863 node _T_2864 = eq(UInt<5>(0h19), idx_29) when _T_2864 : node _T_2865 = shl(UInt<5>(0h1d), 3) node _T_2866 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2865) connect Queue10_UInt8_25.io.enq.bits, _T_2866 node _T_2867 = eq(UInt<5>(0h1a), idx_29) when _T_2867 : node _T_2868 = shl(UInt<5>(0h1d), 3) node _T_2869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2868) connect Queue10_UInt8_26.io.enq.bits, _T_2869 node _T_2870 = eq(UInt<5>(0h1b), idx_29) when _T_2870 : node _T_2871 = shl(UInt<5>(0h1d), 3) node _T_2872 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2871) connect Queue10_UInt8_27.io.enq.bits, _T_2872 node _T_2873 = eq(UInt<5>(0h1c), idx_29) when _T_2873 : node _T_2874 = shl(UInt<5>(0h1d), 3) node _T_2875 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2874) connect Queue10_UInt8_28.io.enq.bits, _T_2875 node _T_2876 = eq(UInt<5>(0h1d), idx_29) when _T_2876 : node _T_2877 = shl(UInt<5>(0h1d), 3) node _T_2878 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2877) connect Queue10_UInt8_29.io.enq.bits, _T_2878 node _T_2879 = eq(UInt<5>(0h1e), idx_29) when _T_2879 : node _T_2880 = shl(UInt<5>(0h1d), 3) node _T_2881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2880) connect Queue10_UInt8_30.io.enq.bits, _T_2881 node _T_2882 = eq(UInt<5>(0h1f), idx_29) when _T_2882 : node _T_2883 = shl(UInt<5>(0h1d), 3) node _T_2884 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2883) connect Queue10_UInt8_31.io.enq.bits, _T_2884 node _idx_T_30 = add(write_start_index, UInt<5>(0h1e)) node idx_30 = rem(_idx_T_30, UInt<6>(0h20)) node _T_2885 = eq(UInt<1>(0h0), idx_30) when _T_2885 : node _T_2886 = shl(UInt<5>(0h1e), 3) node _T_2887 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2886) connect Queue10_UInt8.io.enq.bits, _T_2887 node _T_2888 = eq(UInt<1>(0h1), idx_30) when _T_2888 : node _T_2889 = shl(UInt<5>(0h1e), 3) node _T_2890 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2889) connect Queue10_UInt8_1.io.enq.bits, _T_2890 node _T_2891 = eq(UInt<2>(0h2), idx_30) when _T_2891 : node _T_2892 = shl(UInt<5>(0h1e), 3) node _T_2893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2892) connect Queue10_UInt8_2.io.enq.bits, _T_2893 node _T_2894 = eq(UInt<2>(0h3), idx_30) when _T_2894 : node _T_2895 = shl(UInt<5>(0h1e), 3) node _T_2896 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2895) connect Queue10_UInt8_3.io.enq.bits, _T_2896 node _T_2897 = eq(UInt<3>(0h4), idx_30) when _T_2897 : node _T_2898 = shl(UInt<5>(0h1e), 3) node _T_2899 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2898) connect Queue10_UInt8_4.io.enq.bits, _T_2899 node _T_2900 = eq(UInt<3>(0h5), idx_30) when _T_2900 : node _T_2901 = shl(UInt<5>(0h1e), 3) node _T_2902 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2901) connect Queue10_UInt8_5.io.enq.bits, _T_2902 node _T_2903 = eq(UInt<3>(0h6), idx_30) when _T_2903 : node _T_2904 = shl(UInt<5>(0h1e), 3) node _T_2905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2904) connect Queue10_UInt8_6.io.enq.bits, _T_2905 node _T_2906 = eq(UInt<3>(0h7), idx_30) when _T_2906 : node _T_2907 = shl(UInt<5>(0h1e), 3) node _T_2908 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2907) connect Queue10_UInt8_7.io.enq.bits, _T_2908 node _T_2909 = eq(UInt<4>(0h8), idx_30) when _T_2909 : node _T_2910 = shl(UInt<5>(0h1e), 3) node _T_2911 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2910) connect Queue10_UInt8_8.io.enq.bits, _T_2911 node _T_2912 = eq(UInt<4>(0h9), idx_30) when _T_2912 : node _T_2913 = shl(UInt<5>(0h1e), 3) node _T_2914 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2913) connect Queue10_UInt8_9.io.enq.bits, _T_2914 node _T_2915 = eq(UInt<4>(0ha), idx_30) when _T_2915 : node _T_2916 = shl(UInt<5>(0h1e), 3) node _T_2917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2916) connect Queue10_UInt8_10.io.enq.bits, _T_2917 node _T_2918 = eq(UInt<4>(0hb), idx_30) when _T_2918 : node _T_2919 = shl(UInt<5>(0h1e), 3) node _T_2920 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2919) connect Queue10_UInt8_11.io.enq.bits, _T_2920 node _T_2921 = eq(UInt<4>(0hc), idx_30) when _T_2921 : node _T_2922 = shl(UInt<5>(0h1e), 3) node _T_2923 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2922) connect Queue10_UInt8_12.io.enq.bits, _T_2923 node _T_2924 = eq(UInt<4>(0hd), idx_30) when _T_2924 : node _T_2925 = shl(UInt<5>(0h1e), 3) node _T_2926 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2925) connect Queue10_UInt8_13.io.enq.bits, _T_2926 node _T_2927 = eq(UInt<4>(0he), idx_30) when _T_2927 : node _T_2928 = shl(UInt<5>(0h1e), 3) node _T_2929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2928) connect Queue10_UInt8_14.io.enq.bits, _T_2929 node _T_2930 = eq(UInt<4>(0hf), idx_30) when _T_2930 : node _T_2931 = shl(UInt<5>(0h1e), 3) node _T_2932 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2931) connect Queue10_UInt8_15.io.enq.bits, _T_2932 node _T_2933 = eq(UInt<5>(0h10), idx_30) when _T_2933 : node _T_2934 = shl(UInt<5>(0h1e), 3) node _T_2935 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2934) connect Queue10_UInt8_16.io.enq.bits, _T_2935 node _T_2936 = eq(UInt<5>(0h11), idx_30) when _T_2936 : node _T_2937 = shl(UInt<5>(0h1e), 3) node _T_2938 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2937) connect Queue10_UInt8_17.io.enq.bits, _T_2938 node _T_2939 = eq(UInt<5>(0h12), idx_30) when _T_2939 : node _T_2940 = shl(UInt<5>(0h1e), 3) node _T_2941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2940) connect Queue10_UInt8_18.io.enq.bits, _T_2941 node _T_2942 = eq(UInt<5>(0h13), idx_30) when _T_2942 : node _T_2943 = shl(UInt<5>(0h1e), 3) node _T_2944 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2943) connect Queue10_UInt8_19.io.enq.bits, _T_2944 node _T_2945 = eq(UInt<5>(0h14), idx_30) when _T_2945 : node _T_2946 = shl(UInt<5>(0h1e), 3) node _T_2947 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2946) connect Queue10_UInt8_20.io.enq.bits, _T_2947 node _T_2948 = eq(UInt<5>(0h15), idx_30) when _T_2948 : node _T_2949 = shl(UInt<5>(0h1e), 3) node _T_2950 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2949) connect Queue10_UInt8_21.io.enq.bits, _T_2950 node _T_2951 = eq(UInt<5>(0h16), idx_30) when _T_2951 : node _T_2952 = shl(UInt<5>(0h1e), 3) node _T_2953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2952) connect Queue10_UInt8_22.io.enq.bits, _T_2953 node _T_2954 = eq(UInt<5>(0h17), idx_30) when _T_2954 : node _T_2955 = shl(UInt<5>(0h1e), 3) node _T_2956 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2955) connect Queue10_UInt8_23.io.enq.bits, _T_2956 node _T_2957 = eq(UInt<5>(0h18), idx_30) when _T_2957 : node _T_2958 = shl(UInt<5>(0h1e), 3) node _T_2959 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2958) connect Queue10_UInt8_24.io.enq.bits, _T_2959 node _T_2960 = eq(UInt<5>(0h19), idx_30) when _T_2960 : node _T_2961 = shl(UInt<5>(0h1e), 3) node _T_2962 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2961) connect Queue10_UInt8_25.io.enq.bits, _T_2962 node _T_2963 = eq(UInt<5>(0h1a), idx_30) when _T_2963 : node _T_2964 = shl(UInt<5>(0h1e), 3) node _T_2965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2964) connect Queue10_UInt8_26.io.enq.bits, _T_2965 node _T_2966 = eq(UInt<5>(0h1b), idx_30) when _T_2966 : node _T_2967 = shl(UInt<5>(0h1e), 3) node _T_2968 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2967) connect Queue10_UInt8_27.io.enq.bits, _T_2968 node _T_2969 = eq(UInt<5>(0h1c), idx_30) when _T_2969 : node _T_2970 = shl(UInt<5>(0h1e), 3) node _T_2971 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2970) connect Queue10_UInt8_28.io.enq.bits, _T_2971 node _T_2972 = eq(UInt<5>(0h1d), idx_30) when _T_2972 : node _T_2973 = shl(UInt<5>(0h1e), 3) node _T_2974 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2973) connect Queue10_UInt8_29.io.enq.bits, _T_2974 node _T_2975 = eq(UInt<5>(0h1e), idx_30) when _T_2975 : node _T_2976 = shl(UInt<5>(0h1e), 3) node _T_2977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2976) connect Queue10_UInt8_30.io.enq.bits, _T_2977 node _T_2978 = eq(UInt<5>(0h1f), idx_30) when _T_2978 : node _T_2979 = shl(UInt<5>(0h1e), 3) node _T_2980 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2979) connect Queue10_UInt8_31.io.enq.bits, _T_2980 node _idx_T_31 = add(write_start_index, UInt<5>(0h1f)) node idx_31 = rem(_idx_T_31, UInt<6>(0h20)) node _T_2981 = eq(UInt<1>(0h0), idx_31) when _T_2981 : node _T_2982 = shl(UInt<5>(0h1f), 3) node _T_2983 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2982) connect Queue10_UInt8.io.enq.bits, _T_2983 node _T_2984 = eq(UInt<1>(0h1), idx_31) when _T_2984 : node _T_2985 = shl(UInt<5>(0h1f), 3) node _T_2986 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2985) connect Queue10_UInt8_1.io.enq.bits, _T_2986 node _T_2987 = eq(UInt<2>(0h2), idx_31) when _T_2987 : node _T_2988 = shl(UInt<5>(0h1f), 3) node _T_2989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2988) connect Queue10_UInt8_2.io.enq.bits, _T_2989 node _T_2990 = eq(UInt<2>(0h3), idx_31) when _T_2990 : node _T_2991 = shl(UInt<5>(0h1f), 3) node _T_2992 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2991) connect Queue10_UInt8_3.io.enq.bits, _T_2992 node _T_2993 = eq(UInt<3>(0h4), idx_31) when _T_2993 : node _T_2994 = shl(UInt<5>(0h1f), 3) node _T_2995 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2994) connect Queue10_UInt8_4.io.enq.bits, _T_2995 node _T_2996 = eq(UInt<3>(0h5), idx_31) when _T_2996 : node _T_2997 = shl(UInt<5>(0h1f), 3) node _T_2998 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2997) connect Queue10_UInt8_5.io.enq.bits, _T_2998 node _T_2999 = eq(UInt<3>(0h6), idx_31) when _T_2999 : node _T_3000 = shl(UInt<5>(0h1f), 3) node _T_3001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3000) connect Queue10_UInt8_6.io.enq.bits, _T_3001 node _T_3002 = eq(UInt<3>(0h7), idx_31) when _T_3002 : node _T_3003 = shl(UInt<5>(0h1f), 3) node _T_3004 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3003) connect Queue10_UInt8_7.io.enq.bits, _T_3004 node _T_3005 = eq(UInt<4>(0h8), idx_31) when _T_3005 : node _T_3006 = shl(UInt<5>(0h1f), 3) node _T_3007 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3006) connect Queue10_UInt8_8.io.enq.bits, _T_3007 node _T_3008 = eq(UInt<4>(0h9), idx_31) when _T_3008 : node _T_3009 = shl(UInt<5>(0h1f), 3) node _T_3010 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3009) connect Queue10_UInt8_9.io.enq.bits, _T_3010 node _T_3011 = eq(UInt<4>(0ha), idx_31) when _T_3011 : node _T_3012 = shl(UInt<5>(0h1f), 3) node _T_3013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3012) connect Queue10_UInt8_10.io.enq.bits, _T_3013 node _T_3014 = eq(UInt<4>(0hb), idx_31) when _T_3014 : node _T_3015 = shl(UInt<5>(0h1f), 3) node _T_3016 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3015) connect Queue10_UInt8_11.io.enq.bits, _T_3016 node _T_3017 = eq(UInt<4>(0hc), idx_31) when _T_3017 : node _T_3018 = shl(UInt<5>(0h1f), 3) node _T_3019 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3018) connect Queue10_UInt8_12.io.enq.bits, _T_3019 node _T_3020 = eq(UInt<4>(0hd), idx_31) when _T_3020 : node _T_3021 = shl(UInt<5>(0h1f), 3) node _T_3022 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3021) connect Queue10_UInt8_13.io.enq.bits, _T_3022 node _T_3023 = eq(UInt<4>(0he), idx_31) when _T_3023 : node _T_3024 = shl(UInt<5>(0h1f), 3) node _T_3025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3024) connect Queue10_UInt8_14.io.enq.bits, _T_3025 node _T_3026 = eq(UInt<4>(0hf), idx_31) when _T_3026 : node _T_3027 = shl(UInt<5>(0h1f), 3) node _T_3028 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3027) connect Queue10_UInt8_15.io.enq.bits, _T_3028 node _T_3029 = eq(UInt<5>(0h10), idx_31) when _T_3029 : node _T_3030 = shl(UInt<5>(0h1f), 3) node _T_3031 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3030) connect Queue10_UInt8_16.io.enq.bits, _T_3031 node _T_3032 = eq(UInt<5>(0h11), idx_31) when _T_3032 : node _T_3033 = shl(UInt<5>(0h1f), 3) node _T_3034 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3033) connect Queue10_UInt8_17.io.enq.bits, _T_3034 node _T_3035 = eq(UInt<5>(0h12), idx_31) when _T_3035 : node _T_3036 = shl(UInt<5>(0h1f), 3) node _T_3037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3036) connect Queue10_UInt8_18.io.enq.bits, _T_3037 node _T_3038 = eq(UInt<5>(0h13), idx_31) when _T_3038 : node _T_3039 = shl(UInt<5>(0h1f), 3) node _T_3040 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3039) connect Queue10_UInt8_19.io.enq.bits, _T_3040 node _T_3041 = eq(UInt<5>(0h14), idx_31) when _T_3041 : node _T_3042 = shl(UInt<5>(0h1f), 3) node _T_3043 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3042) connect Queue10_UInt8_20.io.enq.bits, _T_3043 node _T_3044 = eq(UInt<5>(0h15), idx_31) when _T_3044 : node _T_3045 = shl(UInt<5>(0h1f), 3) node _T_3046 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3045) connect Queue10_UInt8_21.io.enq.bits, _T_3046 node _T_3047 = eq(UInt<5>(0h16), idx_31) when _T_3047 : node _T_3048 = shl(UInt<5>(0h1f), 3) node _T_3049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3048) connect Queue10_UInt8_22.io.enq.bits, _T_3049 node _T_3050 = eq(UInt<5>(0h17), idx_31) when _T_3050 : node _T_3051 = shl(UInt<5>(0h1f), 3) node _T_3052 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3051) connect Queue10_UInt8_23.io.enq.bits, _T_3052 node _T_3053 = eq(UInt<5>(0h18), idx_31) when _T_3053 : node _T_3054 = shl(UInt<5>(0h1f), 3) node _T_3055 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3054) connect Queue10_UInt8_24.io.enq.bits, _T_3055 node _T_3056 = eq(UInt<5>(0h19), idx_31) when _T_3056 : node _T_3057 = shl(UInt<5>(0h1f), 3) node _T_3058 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3057) connect Queue10_UInt8_25.io.enq.bits, _T_3058 node _T_3059 = eq(UInt<5>(0h1a), idx_31) when _T_3059 : node _T_3060 = shl(UInt<5>(0h1f), 3) node _T_3061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3060) connect Queue10_UInt8_26.io.enq.bits, _T_3061 node _T_3062 = eq(UInt<5>(0h1b), idx_31) when _T_3062 : node _T_3063 = shl(UInt<5>(0h1f), 3) node _T_3064 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3063) connect Queue10_UInt8_27.io.enq.bits, _T_3064 node _T_3065 = eq(UInt<5>(0h1c), idx_31) when _T_3065 : node _T_3066 = shl(UInt<5>(0h1f), 3) node _T_3067 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3066) connect Queue10_UInt8_28.io.enq.bits, _T_3067 node _T_3068 = eq(UInt<5>(0h1d), idx_31) when _T_3068 : node _T_3069 = shl(UInt<5>(0h1f), 3) node _T_3070 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3069) connect Queue10_UInt8_29.io.enq.bits, _T_3070 node _T_3071 = eq(UInt<5>(0h1e), idx_31) when _T_3071 : node _T_3072 = shl(UInt<5>(0h1f), 3) node _T_3073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3072) connect Queue10_UInt8_30.io.enq.bits, _T_3073 node _T_3074 = eq(UInt<5>(0h1f), idx_31) when _T_3074 : node _T_3075 = shl(UInt<5>(0h1f), 3) node _T_3076 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3075) connect Queue10_UInt8_31.io.enq.bits, _T_3076 node wrap_len_index_wide = add(write_start_index, incoming_writes_Q.io.deq.bits.validbytes) node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20)) node wrapped = geq(wrap_len_index_wide, UInt<6>(0h20)) node _all_queues_ready_T = and(Queue10_UInt8.io.enq.ready, Queue10_UInt8_1.io.enq.ready) node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue10_UInt8_2.io.enq.ready) node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue10_UInt8_3.io.enq.ready) node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue10_UInt8_4.io.enq.ready) node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue10_UInt8_5.io.enq.ready) node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue10_UInt8_6.io.enq.ready) node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue10_UInt8_7.io.enq.ready) node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue10_UInt8_8.io.enq.ready) node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue10_UInt8_9.io.enq.ready) node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue10_UInt8_10.io.enq.ready) node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue10_UInt8_11.io.enq.ready) node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue10_UInt8_12.io.enq.ready) node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue10_UInt8_13.io.enq.ready) node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue10_UInt8_14.io.enq.ready) node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue10_UInt8_15.io.enq.ready) node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue10_UInt8_16.io.enq.ready) node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue10_UInt8_17.io.enq.ready) node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue10_UInt8_18.io.enq.ready) node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue10_UInt8_19.io.enq.ready) node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue10_UInt8_20.io.enq.ready) node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue10_UInt8_21.io.enq.ready) node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue10_UInt8_22.io.enq.ready) node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue10_UInt8_23.io.enq.ready) node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue10_UInt8_24.io.enq.ready) node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue10_UInt8_25.io.enq.ready) node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue10_UInt8_26.io.enq.ready) node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue10_UInt8_27.io.enq.ready) node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue10_UInt8_28.io.enq.ready) node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue10_UInt8_29.io.enq.ready) node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue10_UInt8_30.io.enq.ready) node all_queues_ready = and(_all_queues_ready_T_29, Queue10_UInt8_31.io.enq.ready) connect incoming_writes_Q.io.deq.ready, all_queues_ready node _T_3077 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) when _T_3077 : connect write_start_index, wrap_len_index_end node _use_this_queue_T = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_1 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_2 = or(_use_this_queue_T, _use_this_queue_T_1) node _use_this_queue_T_3 = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_4 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_5 = and(_use_this_queue_T_3, _use_this_queue_T_4) node use_this_queue = mux(wrapped, _use_this_queue_T_2, _use_this_queue_T_5) node _T_3078 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3079 = and(_T_3078, use_this_queue) connect Queue10_UInt8.io.enq.valid, _T_3079 node _use_this_queue_T_6 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_7 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_8 = or(_use_this_queue_T_6, _use_this_queue_T_7) node _use_this_queue_T_9 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_10 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_11 = and(_use_this_queue_T_9, _use_this_queue_T_10) node use_this_queue_1 = mux(wrapped, _use_this_queue_T_8, _use_this_queue_T_11) node _T_3080 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3081 = and(_T_3080, use_this_queue_1) connect Queue10_UInt8_1.io.enq.valid, _T_3081 node _use_this_queue_T_12 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_13 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_14 = or(_use_this_queue_T_12, _use_this_queue_T_13) node _use_this_queue_T_15 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_16 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_17 = and(_use_this_queue_T_15, _use_this_queue_T_16) node use_this_queue_2 = mux(wrapped, _use_this_queue_T_14, _use_this_queue_T_17) node _T_3082 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3083 = and(_T_3082, use_this_queue_2) connect Queue10_UInt8_2.io.enq.valid, _T_3083 node _use_this_queue_T_18 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_19 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_20 = or(_use_this_queue_T_18, _use_this_queue_T_19) node _use_this_queue_T_21 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_22 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_23 = and(_use_this_queue_T_21, _use_this_queue_T_22) node use_this_queue_3 = mux(wrapped, _use_this_queue_T_20, _use_this_queue_T_23) node _T_3084 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3085 = and(_T_3084, use_this_queue_3) connect Queue10_UInt8_3.io.enq.valid, _T_3085 node _use_this_queue_T_24 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_25 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_26 = or(_use_this_queue_T_24, _use_this_queue_T_25) node _use_this_queue_T_27 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_28 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_29 = and(_use_this_queue_T_27, _use_this_queue_T_28) node use_this_queue_4 = mux(wrapped, _use_this_queue_T_26, _use_this_queue_T_29) node _T_3086 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3087 = and(_T_3086, use_this_queue_4) connect Queue10_UInt8_4.io.enq.valid, _T_3087 node _use_this_queue_T_30 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_31 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31) node _use_this_queue_T_33 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_34 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_35 = and(_use_this_queue_T_33, _use_this_queue_T_34) node use_this_queue_5 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_35) node _T_3088 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3089 = and(_T_3088, use_this_queue_5) connect Queue10_UInt8_5.io.enq.valid, _T_3089 node _use_this_queue_T_36 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_37 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_38 = or(_use_this_queue_T_36, _use_this_queue_T_37) node _use_this_queue_T_39 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_40 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_41 = and(_use_this_queue_T_39, _use_this_queue_T_40) node use_this_queue_6 = mux(wrapped, _use_this_queue_T_38, _use_this_queue_T_41) node _T_3090 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3091 = and(_T_3090, use_this_queue_6) connect Queue10_UInt8_6.io.enq.valid, _T_3091 node _use_this_queue_T_42 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_43 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_44 = or(_use_this_queue_T_42, _use_this_queue_T_43) node _use_this_queue_T_45 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_46 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_47 = and(_use_this_queue_T_45, _use_this_queue_T_46) node use_this_queue_7 = mux(wrapped, _use_this_queue_T_44, _use_this_queue_T_47) node _T_3092 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3093 = and(_T_3092, use_this_queue_7) connect Queue10_UInt8_7.io.enq.valid, _T_3093 node _use_this_queue_T_48 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_49 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_50 = or(_use_this_queue_T_48, _use_this_queue_T_49) node _use_this_queue_T_51 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_52 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_53 = and(_use_this_queue_T_51, _use_this_queue_T_52) node use_this_queue_8 = mux(wrapped, _use_this_queue_T_50, _use_this_queue_T_53) node _T_3094 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3095 = and(_T_3094, use_this_queue_8) connect Queue10_UInt8_8.io.enq.valid, _T_3095 node _use_this_queue_T_54 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_55 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_56 = or(_use_this_queue_T_54, _use_this_queue_T_55) node _use_this_queue_T_57 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_58 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_59 = and(_use_this_queue_T_57, _use_this_queue_T_58) node use_this_queue_9 = mux(wrapped, _use_this_queue_T_56, _use_this_queue_T_59) node _T_3096 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3097 = and(_T_3096, use_this_queue_9) connect Queue10_UInt8_9.io.enq.valid, _T_3097 node _use_this_queue_T_60 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_61 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_62 = or(_use_this_queue_T_60, _use_this_queue_T_61) node _use_this_queue_T_63 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_64 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_65 = and(_use_this_queue_T_63, _use_this_queue_T_64) node use_this_queue_10 = mux(wrapped, _use_this_queue_T_62, _use_this_queue_T_65) node _T_3098 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3099 = and(_T_3098, use_this_queue_10) connect Queue10_UInt8_10.io.enq.valid, _T_3099 node _use_this_queue_T_66 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_67 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_68 = or(_use_this_queue_T_66, _use_this_queue_T_67) node _use_this_queue_T_69 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_70 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_71 = and(_use_this_queue_T_69, _use_this_queue_T_70) node use_this_queue_11 = mux(wrapped, _use_this_queue_T_68, _use_this_queue_T_71) node _T_3100 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3101 = and(_T_3100, use_this_queue_11) connect Queue10_UInt8_11.io.enq.valid, _T_3101 node _use_this_queue_T_72 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_73 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73) node _use_this_queue_T_75 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_76 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_77 = and(_use_this_queue_T_75, _use_this_queue_T_76) node use_this_queue_12 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_77) node _T_3102 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3103 = and(_T_3102, use_this_queue_12) connect Queue10_UInt8_12.io.enq.valid, _T_3103 node _use_this_queue_T_78 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_79 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_80 = or(_use_this_queue_T_78, _use_this_queue_T_79) node _use_this_queue_T_81 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_82 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_83 = and(_use_this_queue_T_81, _use_this_queue_T_82) node use_this_queue_13 = mux(wrapped, _use_this_queue_T_80, _use_this_queue_T_83) node _T_3104 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3105 = and(_T_3104, use_this_queue_13) connect Queue10_UInt8_13.io.enq.valid, _T_3105 node _use_this_queue_T_84 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_85 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_86 = or(_use_this_queue_T_84, _use_this_queue_T_85) node _use_this_queue_T_87 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_88 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_89 = and(_use_this_queue_T_87, _use_this_queue_T_88) node use_this_queue_14 = mux(wrapped, _use_this_queue_T_86, _use_this_queue_T_89) node _T_3106 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3107 = and(_T_3106, use_this_queue_14) connect Queue10_UInt8_14.io.enq.valid, _T_3107 node _use_this_queue_T_90 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_91 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_92 = or(_use_this_queue_T_90, _use_this_queue_T_91) node _use_this_queue_T_93 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_94 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_95 = and(_use_this_queue_T_93, _use_this_queue_T_94) node use_this_queue_15 = mux(wrapped, _use_this_queue_T_92, _use_this_queue_T_95) node _T_3108 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3109 = and(_T_3108, use_this_queue_15) connect Queue10_UInt8_15.io.enq.valid, _T_3109 node _use_this_queue_T_96 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_97 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_98 = or(_use_this_queue_T_96, _use_this_queue_T_97) node _use_this_queue_T_99 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_100 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_101 = and(_use_this_queue_T_99, _use_this_queue_T_100) node use_this_queue_16 = mux(wrapped, _use_this_queue_T_98, _use_this_queue_T_101) node _T_3110 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3111 = and(_T_3110, use_this_queue_16) connect Queue10_UInt8_16.io.enq.valid, _T_3111 node _use_this_queue_T_102 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_103 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_104 = or(_use_this_queue_T_102, _use_this_queue_T_103) node _use_this_queue_T_105 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_106 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_107 = and(_use_this_queue_T_105, _use_this_queue_T_106) node use_this_queue_17 = mux(wrapped, _use_this_queue_T_104, _use_this_queue_T_107) node _T_3112 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3113 = and(_T_3112, use_this_queue_17) connect Queue10_UInt8_17.io.enq.valid, _T_3113 node _use_this_queue_T_108 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_109 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_110 = or(_use_this_queue_T_108, _use_this_queue_T_109) node _use_this_queue_T_111 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_112 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_113 = and(_use_this_queue_T_111, _use_this_queue_T_112) node use_this_queue_18 = mux(wrapped, _use_this_queue_T_110, _use_this_queue_T_113) node _T_3114 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3115 = and(_T_3114, use_this_queue_18) connect Queue10_UInt8_18.io.enq.valid, _T_3115 node _use_this_queue_T_114 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_115 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115) node _use_this_queue_T_117 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_118 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_119 = and(_use_this_queue_T_117, _use_this_queue_T_118) node use_this_queue_19 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_119) node _T_3116 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3117 = and(_T_3116, use_this_queue_19) connect Queue10_UInt8_19.io.enq.valid, _T_3117 node _use_this_queue_T_120 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_121 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_122 = or(_use_this_queue_T_120, _use_this_queue_T_121) node _use_this_queue_T_123 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_124 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_125 = and(_use_this_queue_T_123, _use_this_queue_T_124) node use_this_queue_20 = mux(wrapped, _use_this_queue_T_122, _use_this_queue_T_125) node _T_3118 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3119 = and(_T_3118, use_this_queue_20) connect Queue10_UInt8_20.io.enq.valid, _T_3119 node _use_this_queue_T_126 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_127 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_128 = or(_use_this_queue_T_126, _use_this_queue_T_127) node _use_this_queue_T_129 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_130 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_131 = and(_use_this_queue_T_129, _use_this_queue_T_130) node use_this_queue_21 = mux(wrapped, _use_this_queue_T_128, _use_this_queue_T_131) node _T_3120 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3121 = and(_T_3120, use_this_queue_21) connect Queue10_UInt8_21.io.enq.valid, _T_3121 node _use_this_queue_T_132 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_133 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_134 = or(_use_this_queue_T_132, _use_this_queue_T_133) node _use_this_queue_T_135 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_136 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_137 = and(_use_this_queue_T_135, _use_this_queue_T_136) node use_this_queue_22 = mux(wrapped, _use_this_queue_T_134, _use_this_queue_T_137) node _T_3122 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3123 = and(_T_3122, use_this_queue_22) connect Queue10_UInt8_22.io.enq.valid, _T_3123 node _use_this_queue_T_138 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_139 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_140 = or(_use_this_queue_T_138, _use_this_queue_T_139) node _use_this_queue_T_141 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_142 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_143 = and(_use_this_queue_T_141, _use_this_queue_T_142) node use_this_queue_23 = mux(wrapped, _use_this_queue_T_140, _use_this_queue_T_143) node _T_3124 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3125 = and(_T_3124, use_this_queue_23) connect Queue10_UInt8_23.io.enq.valid, _T_3125 node _use_this_queue_T_144 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_145 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_146 = or(_use_this_queue_T_144, _use_this_queue_T_145) node _use_this_queue_T_147 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_148 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_149 = and(_use_this_queue_T_147, _use_this_queue_T_148) node use_this_queue_24 = mux(wrapped, _use_this_queue_T_146, _use_this_queue_T_149) node _T_3126 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3127 = and(_T_3126, use_this_queue_24) connect Queue10_UInt8_24.io.enq.valid, _T_3127 node _use_this_queue_T_150 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_151 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_152 = or(_use_this_queue_T_150, _use_this_queue_T_151) node _use_this_queue_T_153 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_154 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_155 = and(_use_this_queue_T_153, _use_this_queue_T_154) node use_this_queue_25 = mux(wrapped, _use_this_queue_T_152, _use_this_queue_T_155) node _T_3128 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3129 = and(_T_3128, use_this_queue_25) connect Queue10_UInt8_25.io.enq.valid, _T_3129 node _use_this_queue_T_156 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_157 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157) node _use_this_queue_T_159 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_160 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_161 = and(_use_this_queue_T_159, _use_this_queue_T_160) node use_this_queue_26 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_161) node _T_3130 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3131 = and(_T_3130, use_this_queue_26) connect Queue10_UInt8_26.io.enq.valid, _T_3131 node _use_this_queue_T_162 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_163 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_164 = or(_use_this_queue_T_162, _use_this_queue_T_163) node _use_this_queue_T_165 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_166 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_167 = and(_use_this_queue_T_165, _use_this_queue_T_166) node use_this_queue_27 = mux(wrapped, _use_this_queue_T_164, _use_this_queue_T_167) node _T_3132 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3133 = and(_T_3132, use_this_queue_27) connect Queue10_UInt8_27.io.enq.valid, _T_3133 node _use_this_queue_T_168 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_169 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_170 = or(_use_this_queue_T_168, _use_this_queue_T_169) node _use_this_queue_T_171 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_172 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_173 = and(_use_this_queue_T_171, _use_this_queue_T_172) node use_this_queue_28 = mux(wrapped, _use_this_queue_T_170, _use_this_queue_T_173) node _T_3134 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3135 = and(_T_3134, use_this_queue_28) connect Queue10_UInt8_28.io.enq.valid, _T_3135 node _use_this_queue_T_174 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_175 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_176 = or(_use_this_queue_T_174, _use_this_queue_T_175) node _use_this_queue_T_177 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_178 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_179 = and(_use_this_queue_T_177, _use_this_queue_T_178) node use_this_queue_29 = mux(wrapped, _use_this_queue_T_176, _use_this_queue_T_179) node _T_3136 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3137 = and(_T_3136, use_this_queue_29) connect Queue10_UInt8_29.io.enq.valid, _T_3137 node _use_this_queue_T_180 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_181 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_182 = or(_use_this_queue_T_180, _use_this_queue_T_181) node _use_this_queue_T_183 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_184 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_185 = and(_use_this_queue_T_183, _use_this_queue_T_184) node use_this_queue_30 = mux(wrapped, _use_this_queue_T_182, _use_this_queue_T_185) node _T_3138 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3139 = and(_T_3138, use_this_queue_30) connect Queue10_UInt8_30.io.enq.valid, _T_3139 node _use_this_queue_T_186 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_187 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_188 = or(_use_this_queue_T_186, _use_this_queue_T_187) node _use_this_queue_T_189 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_190 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_191 = and(_use_this_queue_T_189, _use_this_queue_T_190) node use_this_queue_31 = mux(wrapped, _use_this_queue_T_188, _use_this_queue_T_191) node _T_3140 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3141 = and(_T_3140, use_this_queue_31) connect Queue10_UInt8_31.io.enq.valid, _T_3141 when Queue10_UInt8.io.deq.valid : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_3142 = asUInt(reset) node _T_3143 = eq(_T_3142, UInt<1>(0h0)) when _T_3143 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_3144 = asUInt(reset) node _T_3145 = eq(_T_3144, UInt<1>(0h0)) when _T_3145 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<1>(0h0), Queue10_UInt8.io.deq.bits) : printf_3 when Queue10_UInt8_1.io.deq.valid : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_3146 = asUInt(reset) node _T_3147 = eq(_T_3146, UInt<1>(0h0)) when _T_3147 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_3148 = asUInt(reset) node _T_3149 = eq(_T_3148, UInt<1>(0h0)) when _T_3149 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<1>(0h1), Queue10_UInt8_1.io.deq.bits) : printf_5 when Queue10_UInt8_2.io.deq.valid : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_3150 = asUInt(reset) node _T_3151 = eq(_T_3150, UInt<1>(0h0)) when _T_3151 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6 node _T_3152 = asUInt(reset) node _T_3153 = eq(_T_3152, UInt<1>(0h0)) when _T_3153 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<2>(0h2), Queue10_UInt8_2.io.deq.bits) : printf_7 when Queue10_UInt8_3.io.deq.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_3154 = asUInt(reset) node _T_3155 = eq(_T_3154, UInt<1>(0h0)) when _T_3155 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8 node _T_3156 = asUInt(reset) node _T_3157 = eq(_T_3156, UInt<1>(0h0)) when _T_3157 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<2>(0h3), Queue10_UInt8_3.io.deq.bits) : printf_9 when Queue10_UInt8_4.io.deq.valid : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_3158 = asUInt(reset) node _T_3159 = eq(_T_3158, UInt<1>(0h0)) when _T_3159 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10 node _T_3160 = asUInt(reset) node _T_3161 = eq(_T_3160, UInt<1>(0h0)) when _T_3161 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<3>(0h4), Queue10_UInt8_4.io.deq.bits) : printf_11 when Queue10_UInt8_5.io.deq.valid : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _T_3162 = asUInt(reset) node _T_3163 = eq(_T_3162, UInt<1>(0h0)) when _T_3163 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12 node _T_3164 = asUInt(reset) node _T_3165 = eq(_T_3164, UInt<1>(0h0)) when _T_3165 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<3>(0h5), Queue10_UInt8_5.io.deq.bits) : printf_13 when Queue10_UInt8_6.io.deq.valid : regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_3166 = asUInt(reset) node _T_3167 = eq(_T_3166, UInt<1>(0h0)) when _T_3167 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14 node _T_3168 = asUInt(reset) node _T_3169 = eq(_T_3168, UInt<1>(0h0)) when _T_3169 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<3>(0h6), Queue10_UInt8_6.io.deq.bits) : printf_15 when Queue10_UInt8_7.io.deq.valid : regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_3170 = asUInt(reset) node _T_3171 = eq(_T_3170, UInt<1>(0h0)) when _T_3171 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16 node _T_3172 = asUInt(reset) node _T_3173 = eq(_T_3172, UInt<1>(0h0)) when _T_3173 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<3>(0h7), Queue10_UInt8_7.io.deq.bits) : printf_17 when Queue10_UInt8_8.io.deq.valid : regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_3174 = asUInt(reset) node _T_3175 = eq(_T_3174, UInt<1>(0h0)) when _T_3175 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18 node _T_3176 = asUInt(reset) node _T_3177 = eq(_T_3176, UInt<1>(0h0)) when _T_3177 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0h8), Queue10_UInt8_8.io.deq.bits) : printf_19 when Queue10_UInt8_9.io.deq.valid : regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_3178 = asUInt(reset) node _T_3179 = eq(_T_3178, UInt<1>(0h0)) when _T_3179 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20 node _T_3180 = asUInt(reset) node _T_3181 = eq(_T_3180, UInt<1>(0h0)) when _T_3181 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0h9), Queue10_UInt8_9.io.deq.bits) : printf_21 when Queue10_UInt8_10.io.deq.valid : regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_3182 = asUInt(reset) node _T_3183 = eq(_T_3182, UInt<1>(0h0)) when _T_3183 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22 node _T_3184 = asUInt(reset) node _T_3185 = eq(_T_3184, UInt<1>(0h0)) when _T_3185 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0ha), Queue10_UInt8_10.io.deq.bits) : printf_23 when Queue10_UInt8_11.io.deq.valid : regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_3186 = asUInt(reset) node _T_3187 = eq(_T_3186, UInt<1>(0h0)) when _T_3187 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24 node _T_3188 = asUInt(reset) node _T_3189 = eq(_T_3188, UInt<1>(0h0)) when _T_3189 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0hb), Queue10_UInt8_11.io.deq.bits) : printf_25 when Queue10_UInt8_12.io.deq.valid : regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_3190 = asUInt(reset) node _T_3191 = eq(_T_3190, UInt<1>(0h0)) when _T_3191 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26 node _T_3192 = asUInt(reset) node _T_3193 = eq(_T_3192, UInt<1>(0h0)) when _T_3193 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0hc), Queue10_UInt8_12.io.deq.bits) : printf_27 when Queue10_UInt8_13.io.deq.valid : regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_3194 = asUInt(reset) node _T_3195 = eq(_T_3194, UInt<1>(0h0)) when _T_3195 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28 node _T_3196 = asUInt(reset) node _T_3197 = eq(_T_3196, UInt<1>(0h0)) when _T_3197 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0hd), Queue10_UInt8_13.io.deq.bits) : printf_29 when Queue10_UInt8_14.io.deq.valid : regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_3198 = asUInt(reset) node _T_3199 = eq(_T_3198, UInt<1>(0h0)) when _T_3199 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30 node _T_3200 = asUInt(reset) node _T_3201 = eq(_T_3200, UInt<1>(0h0)) when _T_3201 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0he), Queue10_UInt8_14.io.deq.bits) : printf_31 when Queue10_UInt8_15.io.deq.valid : regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_3202 = asUInt(reset) node _T_3203 = eq(_T_3202, UInt<1>(0h0)) when _T_3203 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32 node _T_3204 = asUInt(reset) node _T_3205 = eq(_T_3204, UInt<1>(0h0)) when _T_3205 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0hf), Queue10_UInt8_15.io.deq.bits) : printf_33 when Queue10_UInt8_16.io.deq.valid : regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_3206 = asUInt(reset) node _T_3207 = eq(_T_3206, UInt<1>(0h0)) when _T_3207 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34 node _T_3208 = asUInt(reset) node _T_3209 = eq(_T_3208, UInt<1>(0h0)) when _T_3209 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h10), Queue10_UInt8_16.io.deq.bits) : printf_35 when Queue10_UInt8_17.io.deq.valid : regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_3210 = asUInt(reset) node _T_3211 = eq(_T_3210, UInt<1>(0h0)) when _T_3211 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36 node _T_3212 = asUInt(reset) node _T_3213 = eq(_T_3212, UInt<1>(0h0)) when _T_3213 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h11), Queue10_UInt8_17.io.deq.bits) : printf_37 when Queue10_UInt8_18.io.deq.valid : regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_3214 = asUInt(reset) node _T_3215 = eq(_T_3214, UInt<1>(0h0)) when _T_3215 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38 node _T_3216 = asUInt(reset) node _T_3217 = eq(_T_3216, UInt<1>(0h0)) when _T_3217 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h12), Queue10_UInt8_18.io.deq.bits) : printf_39 when Queue10_UInt8_19.io.deq.valid : regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_3218 = asUInt(reset) node _T_3219 = eq(_T_3218, UInt<1>(0h0)) when _T_3219 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_40 node _T_3220 = asUInt(reset) node _T_3221 = eq(_T_3220, UInt<1>(0h0)) when _T_3221 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h13), Queue10_UInt8_19.io.deq.bits) : printf_41 when Queue10_UInt8_20.io.deq.valid : regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_3222 = asUInt(reset) node _T_3223 = eq(_T_3222, UInt<1>(0h0)) when _T_3223 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_42 node _T_3224 = asUInt(reset) node _T_3225 = eq(_T_3224, UInt<1>(0h0)) when _T_3225 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h14), Queue10_UInt8_20.io.deq.bits) : printf_43 when Queue10_UInt8_21.io.deq.valid : regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_3226 = asUInt(reset) node _T_3227 = eq(_T_3226, UInt<1>(0h0)) when _T_3227 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_44 node _T_3228 = asUInt(reset) node _T_3229 = eq(_T_3228, UInt<1>(0h0)) when _T_3229 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h15), Queue10_UInt8_21.io.deq.bits) : printf_45 when Queue10_UInt8_22.io.deq.valid : regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_3230 = asUInt(reset) node _T_3231 = eq(_T_3230, UInt<1>(0h0)) when _T_3231 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_46 node _T_3232 = asUInt(reset) node _T_3233 = eq(_T_3232, UInt<1>(0h0)) when _T_3233 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h16), Queue10_UInt8_22.io.deq.bits) : printf_47 when Queue10_UInt8_23.io.deq.valid : regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_3234 = asUInt(reset) node _T_3235 = eq(_T_3234, UInt<1>(0h0)) when _T_3235 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_48 node _T_3236 = asUInt(reset) node _T_3237 = eq(_T_3236, UInt<1>(0h0)) when _T_3237 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h17), Queue10_UInt8_23.io.deq.bits) : printf_49 when Queue10_UInt8_24.io.deq.valid : regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_3238 = asUInt(reset) node _T_3239 = eq(_T_3238, UInt<1>(0h0)) when _T_3239 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_50 node _T_3240 = asUInt(reset) node _T_3241 = eq(_T_3240, UInt<1>(0h0)) when _T_3241 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h18), Queue10_UInt8_24.io.deq.bits) : printf_51 when Queue10_UInt8_25.io.deq.valid : regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_3242 = asUInt(reset) node _T_3243 = eq(_T_3242, UInt<1>(0h0)) when _T_3243 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_52 node _T_3244 = asUInt(reset) node _T_3245 = eq(_T_3244, UInt<1>(0h0)) when _T_3245 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h19), Queue10_UInt8_25.io.deq.bits) : printf_53 when Queue10_UInt8_26.io.deq.valid : regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_3246 = asUInt(reset) node _T_3247 = eq(_T_3246, UInt<1>(0h0)) when _T_3247 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_54 node _T_3248 = asUInt(reset) node _T_3249 = eq(_T_3248, UInt<1>(0h0)) when _T_3249 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1a), Queue10_UInt8_26.io.deq.bits) : printf_55 when Queue10_UInt8_27.io.deq.valid : regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_3250 = asUInt(reset) node _T_3251 = eq(_T_3250, UInt<1>(0h0)) when _T_3251 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_56 node _T_3252 = asUInt(reset) node _T_3253 = eq(_T_3252, UInt<1>(0h0)) when _T_3253 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1b), Queue10_UInt8_27.io.deq.bits) : printf_57 when Queue10_UInt8_28.io.deq.valid : regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_3254 = asUInt(reset) node _T_3255 = eq(_T_3254, UInt<1>(0h0)) when _T_3255 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_58 node _T_3256 = asUInt(reset) node _T_3257 = eq(_T_3256, UInt<1>(0h0)) when _T_3257 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1c), Queue10_UInt8_28.io.deq.bits) : printf_59 when Queue10_UInt8_29.io.deq.valid : regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_3258 = asUInt(reset) node _T_3259 = eq(_T_3258, UInt<1>(0h0)) when _T_3259 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_60 node _T_3260 = asUInt(reset) node _T_3261 = eq(_T_3260, UInt<1>(0h0)) when _T_3261 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1d), Queue10_UInt8_29.io.deq.bits) : printf_61 when Queue10_UInt8_30.io.deq.valid : regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_3262 = asUInt(reset) node _T_3263 = eq(_T_3262, UInt<1>(0h0)) when _T_3263 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_62 node _T_3264 = asUInt(reset) node _T_3265 = eq(_T_3264, UInt<1>(0h0)) when _T_3265 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1e), Queue10_UInt8_30.io.deq.bits) : printf_63 when Queue10_UInt8_31.io.deq.valid : regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_3266 = asUInt(reset) node _T_3267 = eq(_T_3266, UInt<1>(0h0)) when _T_3267 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_64 node _T_3268 = asUInt(reset) node _T_3269 = eq(_T_3268, UInt<1>(0h0)) when _T_3269 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1f), Queue10_UInt8_31.io.deq.bits) : printf_65 regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0) wire remapVecData : UInt<8>[32] wire remapVecValids : UInt<1>[32] wire remapVecReadys : UInt<1>[32] connect remapVecData[0], UInt<1>(0h0) connect remapVecValids[0], UInt<1>(0h0) connect Queue10_UInt8.io.deq.ready, UInt<1>(0h0) connect remapVecData[1], UInt<1>(0h0) connect remapVecValids[1], UInt<1>(0h0) connect Queue10_UInt8_1.io.deq.ready, UInt<1>(0h0) connect remapVecData[2], UInt<1>(0h0) connect remapVecValids[2], UInt<1>(0h0) connect Queue10_UInt8_2.io.deq.ready, UInt<1>(0h0) connect remapVecData[3], UInt<1>(0h0) connect remapVecValids[3], UInt<1>(0h0) connect Queue10_UInt8_3.io.deq.ready, UInt<1>(0h0) connect remapVecData[4], UInt<1>(0h0) connect remapVecValids[4], UInt<1>(0h0) connect Queue10_UInt8_4.io.deq.ready, UInt<1>(0h0) connect remapVecData[5], UInt<1>(0h0) connect remapVecValids[5], UInt<1>(0h0) connect Queue10_UInt8_5.io.deq.ready, UInt<1>(0h0) connect remapVecData[6], UInt<1>(0h0) connect remapVecValids[6], UInt<1>(0h0) connect Queue10_UInt8_6.io.deq.ready, UInt<1>(0h0) connect remapVecData[7], UInt<1>(0h0) connect remapVecValids[7], UInt<1>(0h0) connect Queue10_UInt8_7.io.deq.ready, UInt<1>(0h0) connect remapVecData[8], UInt<1>(0h0) connect remapVecValids[8], UInt<1>(0h0) connect Queue10_UInt8_8.io.deq.ready, UInt<1>(0h0) connect remapVecData[9], UInt<1>(0h0) connect remapVecValids[9], UInt<1>(0h0) connect Queue10_UInt8_9.io.deq.ready, UInt<1>(0h0) connect remapVecData[10], UInt<1>(0h0) connect remapVecValids[10], UInt<1>(0h0) connect Queue10_UInt8_10.io.deq.ready, UInt<1>(0h0) connect remapVecData[11], UInt<1>(0h0) connect remapVecValids[11], UInt<1>(0h0) connect Queue10_UInt8_11.io.deq.ready, UInt<1>(0h0) connect remapVecData[12], UInt<1>(0h0) connect remapVecValids[12], UInt<1>(0h0) connect Queue10_UInt8_12.io.deq.ready, UInt<1>(0h0) connect remapVecData[13], UInt<1>(0h0) connect remapVecValids[13], UInt<1>(0h0) connect Queue10_UInt8_13.io.deq.ready, UInt<1>(0h0) connect remapVecData[14], UInt<1>(0h0) connect remapVecValids[14], UInt<1>(0h0) connect Queue10_UInt8_14.io.deq.ready, UInt<1>(0h0) connect remapVecData[15], UInt<1>(0h0) connect remapVecValids[15], UInt<1>(0h0) connect Queue10_UInt8_15.io.deq.ready, UInt<1>(0h0) connect remapVecData[16], UInt<1>(0h0) connect remapVecValids[16], UInt<1>(0h0) connect Queue10_UInt8_16.io.deq.ready, UInt<1>(0h0) connect remapVecData[17], UInt<1>(0h0) connect remapVecValids[17], UInt<1>(0h0) connect Queue10_UInt8_17.io.deq.ready, UInt<1>(0h0) connect remapVecData[18], UInt<1>(0h0) connect remapVecValids[18], UInt<1>(0h0) connect Queue10_UInt8_18.io.deq.ready, UInt<1>(0h0) connect remapVecData[19], UInt<1>(0h0) connect remapVecValids[19], UInt<1>(0h0) connect Queue10_UInt8_19.io.deq.ready, UInt<1>(0h0) connect remapVecData[20], UInt<1>(0h0) connect remapVecValids[20], UInt<1>(0h0) connect Queue10_UInt8_20.io.deq.ready, UInt<1>(0h0) connect remapVecData[21], UInt<1>(0h0) connect remapVecValids[21], UInt<1>(0h0) connect Queue10_UInt8_21.io.deq.ready, UInt<1>(0h0) connect remapVecData[22], UInt<1>(0h0) connect remapVecValids[22], UInt<1>(0h0) connect Queue10_UInt8_22.io.deq.ready, UInt<1>(0h0) connect remapVecData[23], UInt<1>(0h0) connect remapVecValids[23], UInt<1>(0h0) connect Queue10_UInt8_23.io.deq.ready, UInt<1>(0h0) connect remapVecData[24], UInt<1>(0h0) connect remapVecValids[24], UInt<1>(0h0) connect Queue10_UInt8_24.io.deq.ready, UInt<1>(0h0) connect remapVecData[25], UInt<1>(0h0) connect remapVecValids[25], UInt<1>(0h0) connect Queue10_UInt8_25.io.deq.ready, UInt<1>(0h0) connect remapVecData[26], UInt<1>(0h0) connect remapVecValids[26], UInt<1>(0h0) connect Queue10_UInt8_26.io.deq.ready, UInt<1>(0h0) connect remapVecData[27], UInt<1>(0h0) connect remapVecValids[27], UInt<1>(0h0) connect Queue10_UInt8_27.io.deq.ready, UInt<1>(0h0) connect remapVecData[28], UInt<1>(0h0) connect remapVecValids[28], UInt<1>(0h0) connect Queue10_UInt8_28.io.deq.ready, UInt<1>(0h0) connect remapVecData[29], UInt<1>(0h0) connect remapVecValids[29], UInt<1>(0h0) connect Queue10_UInt8_29.io.deq.ready, UInt<1>(0h0) connect remapVecData[30], UInt<1>(0h0) connect remapVecValids[30], UInt<1>(0h0) connect Queue10_UInt8_30.io.deq.ready, UInt<1>(0h0) connect remapVecData[31], UInt<1>(0h0) connect remapVecValids[31], UInt<1>(0h0) connect Queue10_UInt8_31.io.deq.ready, UInt<1>(0h0) node _remapindex_T = add(UInt<1>(0h0), read_start_index) node remapindex = rem(_remapindex_T, UInt<6>(0h20)) node _T_3270 = eq(UInt<1>(0h0), remapindex) when _T_3270 : connect remapVecData[0], Queue10_UInt8.io.deq.bits connect remapVecValids[0], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[0] node _T_3271 = eq(UInt<1>(0h1), remapindex) when _T_3271 : connect remapVecData[0], Queue10_UInt8_1.io.deq.bits connect remapVecValids[0], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[0] node _T_3272 = eq(UInt<2>(0h2), remapindex) when _T_3272 : connect remapVecData[0], Queue10_UInt8_2.io.deq.bits connect remapVecValids[0], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[0] node _T_3273 = eq(UInt<2>(0h3), remapindex) when _T_3273 : connect remapVecData[0], Queue10_UInt8_3.io.deq.bits connect remapVecValids[0], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[0] node _T_3274 = eq(UInt<3>(0h4), remapindex) when _T_3274 : connect remapVecData[0], Queue10_UInt8_4.io.deq.bits connect remapVecValids[0], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[0] node _T_3275 = eq(UInt<3>(0h5), remapindex) when _T_3275 : connect remapVecData[0], Queue10_UInt8_5.io.deq.bits connect remapVecValids[0], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[0] node _T_3276 = eq(UInt<3>(0h6), remapindex) when _T_3276 : connect remapVecData[0], Queue10_UInt8_6.io.deq.bits connect remapVecValids[0], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[0] node _T_3277 = eq(UInt<3>(0h7), remapindex) when _T_3277 : connect remapVecData[0], Queue10_UInt8_7.io.deq.bits connect remapVecValids[0], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[0] node _T_3278 = eq(UInt<4>(0h8), remapindex) when _T_3278 : connect remapVecData[0], Queue10_UInt8_8.io.deq.bits connect remapVecValids[0], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[0] node _T_3279 = eq(UInt<4>(0h9), remapindex) when _T_3279 : connect remapVecData[0], Queue10_UInt8_9.io.deq.bits connect remapVecValids[0], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[0] node _T_3280 = eq(UInt<4>(0ha), remapindex) when _T_3280 : connect remapVecData[0], Queue10_UInt8_10.io.deq.bits connect remapVecValids[0], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[0] node _T_3281 = eq(UInt<4>(0hb), remapindex) when _T_3281 : connect remapVecData[0], Queue10_UInt8_11.io.deq.bits connect remapVecValids[0], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[0] node _T_3282 = eq(UInt<4>(0hc), remapindex) when _T_3282 : connect remapVecData[0], Queue10_UInt8_12.io.deq.bits connect remapVecValids[0], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[0] node _T_3283 = eq(UInt<4>(0hd), remapindex) when _T_3283 : connect remapVecData[0], Queue10_UInt8_13.io.deq.bits connect remapVecValids[0], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[0] node _T_3284 = eq(UInt<4>(0he), remapindex) when _T_3284 : connect remapVecData[0], Queue10_UInt8_14.io.deq.bits connect remapVecValids[0], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[0] node _T_3285 = eq(UInt<4>(0hf), remapindex) when _T_3285 : connect remapVecData[0], Queue10_UInt8_15.io.deq.bits connect remapVecValids[0], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[0] node _T_3286 = eq(UInt<5>(0h10), remapindex) when _T_3286 : connect remapVecData[0], Queue10_UInt8_16.io.deq.bits connect remapVecValids[0], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[0] node _T_3287 = eq(UInt<5>(0h11), remapindex) when _T_3287 : connect remapVecData[0], Queue10_UInt8_17.io.deq.bits connect remapVecValids[0], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[0] node _T_3288 = eq(UInt<5>(0h12), remapindex) when _T_3288 : connect remapVecData[0], Queue10_UInt8_18.io.deq.bits connect remapVecValids[0], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[0] node _T_3289 = eq(UInt<5>(0h13), remapindex) when _T_3289 : connect remapVecData[0], Queue10_UInt8_19.io.deq.bits connect remapVecValids[0], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[0] node _T_3290 = eq(UInt<5>(0h14), remapindex) when _T_3290 : connect remapVecData[0], Queue10_UInt8_20.io.deq.bits connect remapVecValids[0], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[0] node _T_3291 = eq(UInt<5>(0h15), remapindex) when _T_3291 : connect remapVecData[0], Queue10_UInt8_21.io.deq.bits connect remapVecValids[0], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[0] node _T_3292 = eq(UInt<5>(0h16), remapindex) when _T_3292 : connect remapVecData[0], Queue10_UInt8_22.io.deq.bits connect remapVecValids[0], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[0] node _T_3293 = eq(UInt<5>(0h17), remapindex) when _T_3293 : connect remapVecData[0], Queue10_UInt8_23.io.deq.bits connect remapVecValids[0], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[0] node _T_3294 = eq(UInt<5>(0h18), remapindex) when _T_3294 : connect remapVecData[0], Queue10_UInt8_24.io.deq.bits connect remapVecValids[0], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[0] node _T_3295 = eq(UInt<5>(0h19), remapindex) when _T_3295 : connect remapVecData[0], Queue10_UInt8_25.io.deq.bits connect remapVecValids[0], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[0] node _T_3296 = eq(UInt<5>(0h1a), remapindex) when _T_3296 : connect remapVecData[0], Queue10_UInt8_26.io.deq.bits connect remapVecValids[0], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[0] node _T_3297 = eq(UInt<5>(0h1b), remapindex) when _T_3297 : connect remapVecData[0], Queue10_UInt8_27.io.deq.bits connect remapVecValids[0], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[0] node _T_3298 = eq(UInt<5>(0h1c), remapindex) when _T_3298 : connect remapVecData[0], Queue10_UInt8_28.io.deq.bits connect remapVecValids[0], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[0] node _T_3299 = eq(UInt<5>(0h1d), remapindex) when _T_3299 : connect remapVecData[0], Queue10_UInt8_29.io.deq.bits connect remapVecValids[0], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[0] node _T_3300 = eq(UInt<5>(0h1e), remapindex) when _T_3300 : connect remapVecData[0], Queue10_UInt8_30.io.deq.bits connect remapVecValids[0], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[0] node _T_3301 = eq(UInt<5>(0h1f), remapindex) when _T_3301 : connect remapVecData[0], Queue10_UInt8_31.io.deq.bits connect remapVecValids[0], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[0] node _remapindex_T_1 = add(UInt<1>(0h1), read_start_index) node remapindex_1 = rem(_remapindex_T_1, UInt<6>(0h20)) node _T_3302 = eq(UInt<1>(0h0), remapindex_1) when _T_3302 : connect remapVecData[1], Queue10_UInt8.io.deq.bits connect remapVecValids[1], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[1] node _T_3303 = eq(UInt<1>(0h1), remapindex_1) when _T_3303 : connect remapVecData[1], Queue10_UInt8_1.io.deq.bits connect remapVecValids[1], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[1] node _T_3304 = eq(UInt<2>(0h2), remapindex_1) when _T_3304 : connect remapVecData[1], Queue10_UInt8_2.io.deq.bits connect remapVecValids[1], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[1] node _T_3305 = eq(UInt<2>(0h3), remapindex_1) when _T_3305 : connect remapVecData[1], Queue10_UInt8_3.io.deq.bits connect remapVecValids[1], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[1] node _T_3306 = eq(UInt<3>(0h4), remapindex_1) when _T_3306 : connect remapVecData[1], Queue10_UInt8_4.io.deq.bits connect remapVecValids[1], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[1] node _T_3307 = eq(UInt<3>(0h5), remapindex_1) when _T_3307 : connect remapVecData[1], Queue10_UInt8_5.io.deq.bits connect remapVecValids[1], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[1] node _T_3308 = eq(UInt<3>(0h6), remapindex_1) when _T_3308 : connect remapVecData[1], Queue10_UInt8_6.io.deq.bits connect remapVecValids[1], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[1] node _T_3309 = eq(UInt<3>(0h7), remapindex_1) when _T_3309 : connect remapVecData[1], Queue10_UInt8_7.io.deq.bits connect remapVecValids[1], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[1] node _T_3310 = eq(UInt<4>(0h8), remapindex_1) when _T_3310 : connect remapVecData[1], Queue10_UInt8_8.io.deq.bits connect remapVecValids[1], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[1] node _T_3311 = eq(UInt<4>(0h9), remapindex_1) when _T_3311 : connect remapVecData[1], Queue10_UInt8_9.io.deq.bits connect remapVecValids[1], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[1] node _T_3312 = eq(UInt<4>(0ha), remapindex_1) when _T_3312 : connect remapVecData[1], Queue10_UInt8_10.io.deq.bits connect remapVecValids[1], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[1] node _T_3313 = eq(UInt<4>(0hb), remapindex_1) when _T_3313 : connect remapVecData[1], Queue10_UInt8_11.io.deq.bits connect remapVecValids[1], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[1] node _T_3314 = eq(UInt<4>(0hc), remapindex_1) when _T_3314 : connect remapVecData[1], Queue10_UInt8_12.io.deq.bits connect remapVecValids[1], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[1] node _T_3315 = eq(UInt<4>(0hd), remapindex_1) when _T_3315 : connect remapVecData[1], Queue10_UInt8_13.io.deq.bits connect remapVecValids[1], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[1] node _T_3316 = eq(UInt<4>(0he), remapindex_1) when _T_3316 : connect remapVecData[1], Queue10_UInt8_14.io.deq.bits connect remapVecValids[1], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[1] node _T_3317 = eq(UInt<4>(0hf), remapindex_1) when _T_3317 : connect remapVecData[1], Queue10_UInt8_15.io.deq.bits connect remapVecValids[1], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[1] node _T_3318 = eq(UInt<5>(0h10), remapindex_1) when _T_3318 : connect remapVecData[1], Queue10_UInt8_16.io.deq.bits connect remapVecValids[1], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[1] node _T_3319 = eq(UInt<5>(0h11), remapindex_1) when _T_3319 : connect remapVecData[1], Queue10_UInt8_17.io.deq.bits connect remapVecValids[1], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[1] node _T_3320 = eq(UInt<5>(0h12), remapindex_1) when _T_3320 : connect remapVecData[1], Queue10_UInt8_18.io.deq.bits connect remapVecValids[1], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[1] node _T_3321 = eq(UInt<5>(0h13), remapindex_1) when _T_3321 : connect remapVecData[1], Queue10_UInt8_19.io.deq.bits connect remapVecValids[1], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[1] node _T_3322 = eq(UInt<5>(0h14), remapindex_1) when _T_3322 : connect remapVecData[1], Queue10_UInt8_20.io.deq.bits connect remapVecValids[1], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[1] node _T_3323 = eq(UInt<5>(0h15), remapindex_1) when _T_3323 : connect remapVecData[1], Queue10_UInt8_21.io.deq.bits connect remapVecValids[1], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[1] node _T_3324 = eq(UInt<5>(0h16), remapindex_1) when _T_3324 : connect remapVecData[1], Queue10_UInt8_22.io.deq.bits connect remapVecValids[1], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[1] node _T_3325 = eq(UInt<5>(0h17), remapindex_1) when _T_3325 : connect remapVecData[1], Queue10_UInt8_23.io.deq.bits connect remapVecValids[1], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[1] node _T_3326 = eq(UInt<5>(0h18), remapindex_1) when _T_3326 : connect remapVecData[1], Queue10_UInt8_24.io.deq.bits connect remapVecValids[1], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[1] node _T_3327 = eq(UInt<5>(0h19), remapindex_1) when _T_3327 : connect remapVecData[1], Queue10_UInt8_25.io.deq.bits connect remapVecValids[1], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[1] node _T_3328 = eq(UInt<5>(0h1a), remapindex_1) when _T_3328 : connect remapVecData[1], Queue10_UInt8_26.io.deq.bits connect remapVecValids[1], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[1] node _T_3329 = eq(UInt<5>(0h1b), remapindex_1) when _T_3329 : connect remapVecData[1], Queue10_UInt8_27.io.deq.bits connect remapVecValids[1], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[1] node _T_3330 = eq(UInt<5>(0h1c), remapindex_1) when _T_3330 : connect remapVecData[1], Queue10_UInt8_28.io.deq.bits connect remapVecValids[1], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[1] node _T_3331 = eq(UInt<5>(0h1d), remapindex_1) when _T_3331 : connect remapVecData[1], Queue10_UInt8_29.io.deq.bits connect remapVecValids[1], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[1] node _T_3332 = eq(UInt<5>(0h1e), remapindex_1) when _T_3332 : connect remapVecData[1], Queue10_UInt8_30.io.deq.bits connect remapVecValids[1], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[1] node _T_3333 = eq(UInt<5>(0h1f), remapindex_1) when _T_3333 : connect remapVecData[1], Queue10_UInt8_31.io.deq.bits connect remapVecValids[1], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[1] node _remapindex_T_2 = add(UInt<2>(0h2), read_start_index) node remapindex_2 = rem(_remapindex_T_2, UInt<6>(0h20)) node _T_3334 = eq(UInt<1>(0h0), remapindex_2) when _T_3334 : connect remapVecData[2], Queue10_UInt8.io.deq.bits connect remapVecValids[2], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[2] node _T_3335 = eq(UInt<1>(0h1), remapindex_2) when _T_3335 : connect remapVecData[2], Queue10_UInt8_1.io.deq.bits connect remapVecValids[2], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[2] node _T_3336 = eq(UInt<2>(0h2), remapindex_2) when _T_3336 : connect remapVecData[2], Queue10_UInt8_2.io.deq.bits connect remapVecValids[2], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[2] node _T_3337 = eq(UInt<2>(0h3), remapindex_2) when _T_3337 : connect remapVecData[2], Queue10_UInt8_3.io.deq.bits connect remapVecValids[2], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[2] node _T_3338 = eq(UInt<3>(0h4), remapindex_2) when _T_3338 : connect remapVecData[2], Queue10_UInt8_4.io.deq.bits connect remapVecValids[2], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[2] node _T_3339 = eq(UInt<3>(0h5), remapindex_2) when _T_3339 : connect remapVecData[2], Queue10_UInt8_5.io.deq.bits connect remapVecValids[2], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[2] node _T_3340 = eq(UInt<3>(0h6), remapindex_2) when _T_3340 : connect remapVecData[2], Queue10_UInt8_6.io.deq.bits connect remapVecValids[2], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[2] node _T_3341 = eq(UInt<3>(0h7), remapindex_2) when _T_3341 : connect remapVecData[2], Queue10_UInt8_7.io.deq.bits connect remapVecValids[2], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[2] node _T_3342 = eq(UInt<4>(0h8), remapindex_2) when _T_3342 : connect remapVecData[2], Queue10_UInt8_8.io.deq.bits connect remapVecValids[2], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[2] node _T_3343 = eq(UInt<4>(0h9), remapindex_2) when _T_3343 : connect remapVecData[2], Queue10_UInt8_9.io.deq.bits connect remapVecValids[2], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[2] node _T_3344 = eq(UInt<4>(0ha), remapindex_2) when _T_3344 : connect remapVecData[2], Queue10_UInt8_10.io.deq.bits connect remapVecValids[2], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[2] node _T_3345 = eq(UInt<4>(0hb), remapindex_2) when _T_3345 : connect remapVecData[2], Queue10_UInt8_11.io.deq.bits connect remapVecValids[2], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[2] node _T_3346 = eq(UInt<4>(0hc), remapindex_2) when _T_3346 : connect remapVecData[2], Queue10_UInt8_12.io.deq.bits connect remapVecValids[2], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[2] node _T_3347 = eq(UInt<4>(0hd), remapindex_2) when _T_3347 : connect remapVecData[2], Queue10_UInt8_13.io.deq.bits connect remapVecValids[2], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[2] node _T_3348 = eq(UInt<4>(0he), remapindex_2) when _T_3348 : connect remapVecData[2], Queue10_UInt8_14.io.deq.bits connect remapVecValids[2], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[2] node _T_3349 = eq(UInt<4>(0hf), remapindex_2) when _T_3349 : connect remapVecData[2], Queue10_UInt8_15.io.deq.bits connect remapVecValids[2], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[2] node _T_3350 = eq(UInt<5>(0h10), remapindex_2) when _T_3350 : connect remapVecData[2], Queue10_UInt8_16.io.deq.bits connect remapVecValids[2], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[2] node _T_3351 = eq(UInt<5>(0h11), remapindex_2) when _T_3351 : connect remapVecData[2], Queue10_UInt8_17.io.deq.bits connect remapVecValids[2], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[2] node _T_3352 = eq(UInt<5>(0h12), remapindex_2) when _T_3352 : connect remapVecData[2], Queue10_UInt8_18.io.deq.bits connect remapVecValids[2], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[2] node _T_3353 = eq(UInt<5>(0h13), remapindex_2) when _T_3353 : connect remapVecData[2], Queue10_UInt8_19.io.deq.bits connect remapVecValids[2], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[2] node _T_3354 = eq(UInt<5>(0h14), remapindex_2) when _T_3354 : connect remapVecData[2], Queue10_UInt8_20.io.deq.bits connect remapVecValids[2], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[2] node _T_3355 = eq(UInt<5>(0h15), remapindex_2) when _T_3355 : connect remapVecData[2], Queue10_UInt8_21.io.deq.bits connect remapVecValids[2], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[2] node _T_3356 = eq(UInt<5>(0h16), remapindex_2) when _T_3356 : connect remapVecData[2], Queue10_UInt8_22.io.deq.bits connect remapVecValids[2], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[2] node _T_3357 = eq(UInt<5>(0h17), remapindex_2) when _T_3357 : connect remapVecData[2], Queue10_UInt8_23.io.deq.bits connect remapVecValids[2], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[2] node _T_3358 = eq(UInt<5>(0h18), remapindex_2) when _T_3358 : connect remapVecData[2], Queue10_UInt8_24.io.deq.bits connect remapVecValids[2], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[2] node _T_3359 = eq(UInt<5>(0h19), remapindex_2) when _T_3359 : connect remapVecData[2], Queue10_UInt8_25.io.deq.bits connect remapVecValids[2], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[2] node _T_3360 = eq(UInt<5>(0h1a), remapindex_2) when _T_3360 : connect remapVecData[2], Queue10_UInt8_26.io.deq.bits connect remapVecValids[2], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[2] node _T_3361 = eq(UInt<5>(0h1b), remapindex_2) when _T_3361 : connect remapVecData[2], Queue10_UInt8_27.io.deq.bits connect remapVecValids[2], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[2] node _T_3362 = eq(UInt<5>(0h1c), remapindex_2) when _T_3362 : connect remapVecData[2], Queue10_UInt8_28.io.deq.bits connect remapVecValids[2], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[2] node _T_3363 = eq(UInt<5>(0h1d), remapindex_2) when _T_3363 : connect remapVecData[2], Queue10_UInt8_29.io.deq.bits connect remapVecValids[2], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[2] node _T_3364 = eq(UInt<5>(0h1e), remapindex_2) when _T_3364 : connect remapVecData[2], Queue10_UInt8_30.io.deq.bits connect remapVecValids[2], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[2] node _T_3365 = eq(UInt<5>(0h1f), remapindex_2) when _T_3365 : connect remapVecData[2], Queue10_UInt8_31.io.deq.bits connect remapVecValids[2], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[2] node _remapindex_T_3 = add(UInt<2>(0h3), read_start_index) node remapindex_3 = rem(_remapindex_T_3, UInt<6>(0h20)) node _T_3366 = eq(UInt<1>(0h0), remapindex_3) when _T_3366 : connect remapVecData[3], Queue10_UInt8.io.deq.bits connect remapVecValids[3], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[3] node _T_3367 = eq(UInt<1>(0h1), remapindex_3) when _T_3367 : connect remapVecData[3], Queue10_UInt8_1.io.deq.bits connect remapVecValids[3], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[3] node _T_3368 = eq(UInt<2>(0h2), remapindex_3) when _T_3368 : connect remapVecData[3], Queue10_UInt8_2.io.deq.bits connect remapVecValids[3], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[3] node _T_3369 = eq(UInt<2>(0h3), remapindex_3) when _T_3369 : connect remapVecData[3], Queue10_UInt8_3.io.deq.bits connect remapVecValids[3], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[3] node _T_3370 = eq(UInt<3>(0h4), remapindex_3) when _T_3370 : connect remapVecData[3], Queue10_UInt8_4.io.deq.bits connect remapVecValids[3], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[3] node _T_3371 = eq(UInt<3>(0h5), remapindex_3) when _T_3371 : connect remapVecData[3], Queue10_UInt8_5.io.deq.bits connect remapVecValids[3], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[3] node _T_3372 = eq(UInt<3>(0h6), remapindex_3) when _T_3372 : connect remapVecData[3], Queue10_UInt8_6.io.deq.bits connect remapVecValids[3], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[3] node _T_3373 = eq(UInt<3>(0h7), remapindex_3) when _T_3373 : connect remapVecData[3], Queue10_UInt8_7.io.deq.bits connect remapVecValids[3], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[3] node _T_3374 = eq(UInt<4>(0h8), remapindex_3) when _T_3374 : connect remapVecData[3], Queue10_UInt8_8.io.deq.bits connect remapVecValids[3], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[3] node _T_3375 = eq(UInt<4>(0h9), remapindex_3) when _T_3375 : connect remapVecData[3], Queue10_UInt8_9.io.deq.bits connect remapVecValids[3], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[3] node _T_3376 = eq(UInt<4>(0ha), remapindex_3) when _T_3376 : connect remapVecData[3], Queue10_UInt8_10.io.deq.bits connect remapVecValids[3], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[3] node _T_3377 = eq(UInt<4>(0hb), remapindex_3) when _T_3377 : connect remapVecData[3], Queue10_UInt8_11.io.deq.bits connect remapVecValids[3], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[3] node _T_3378 = eq(UInt<4>(0hc), remapindex_3) when _T_3378 : connect remapVecData[3], Queue10_UInt8_12.io.deq.bits connect remapVecValids[3], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[3] node _T_3379 = eq(UInt<4>(0hd), remapindex_3) when _T_3379 : connect remapVecData[3], Queue10_UInt8_13.io.deq.bits connect remapVecValids[3], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[3] node _T_3380 = eq(UInt<4>(0he), remapindex_3) when _T_3380 : connect remapVecData[3], Queue10_UInt8_14.io.deq.bits connect remapVecValids[3], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[3] node _T_3381 = eq(UInt<4>(0hf), remapindex_3) when _T_3381 : connect remapVecData[3], Queue10_UInt8_15.io.deq.bits connect remapVecValids[3], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[3] node _T_3382 = eq(UInt<5>(0h10), remapindex_3) when _T_3382 : connect remapVecData[3], Queue10_UInt8_16.io.deq.bits connect remapVecValids[3], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[3] node _T_3383 = eq(UInt<5>(0h11), remapindex_3) when _T_3383 : connect remapVecData[3], Queue10_UInt8_17.io.deq.bits connect remapVecValids[3], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[3] node _T_3384 = eq(UInt<5>(0h12), remapindex_3) when _T_3384 : connect remapVecData[3], Queue10_UInt8_18.io.deq.bits connect remapVecValids[3], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[3] node _T_3385 = eq(UInt<5>(0h13), remapindex_3) when _T_3385 : connect remapVecData[3], Queue10_UInt8_19.io.deq.bits connect remapVecValids[3], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[3] node _T_3386 = eq(UInt<5>(0h14), remapindex_3) when _T_3386 : connect remapVecData[3], Queue10_UInt8_20.io.deq.bits connect remapVecValids[3], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[3] node _T_3387 = eq(UInt<5>(0h15), remapindex_3) when _T_3387 : connect remapVecData[3], Queue10_UInt8_21.io.deq.bits connect remapVecValids[3], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[3] node _T_3388 = eq(UInt<5>(0h16), remapindex_3) when _T_3388 : connect remapVecData[3], Queue10_UInt8_22.io.deq.bits connect remapVecValids[3], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[3] node _T_3389 = eq(UInt<5>(0h17), remapindex_3) when _T_3389 : connect remapVecData[3], Queue10_UInt8_23.io.deq.bits connect remapVecValids[3], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[3] node _T_3390 = eq(UInt<5>(0h18), remapindex_3) when _T_3390 : connect remapVecData[3], Queue10_UInt8_24.io.deq.bits connect remapVecValids[3], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[3] node _T_3391 = eq(UInt<5>(0h19), remapindex_3) when _T_3391 : connect remapVecData[3], Queue10_UInt8_25.io.deq.bits connect remapVecValids[3], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[3] node _T_3392 = eq(UInt<5>(0h1a), remapindex_3) when _T_3392 : connect remapVecData[3], Queue10_UInt8_26.io.deq.bits connect remapVecValids[3], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[3] node _T_3393 = eq(UInt<5>(0h1b), remapindex_3) when _T_3393 : connect remapVecData[3], Queue10_UInt8_27.io.deq.bits connect remapVecValids[3], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[3] node _T_3394 = eq(UInt<5>(0h1c), remapindex_3) when _T_3394 : connect remapVecData[3], Queue10_UInt8_28.io.deq.bits connect remapVecValids[3], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[3] node _T_3395 = eq(UInt<5>(0h1d), remapindex_3) when _T_3395 : connect remapVecData[3], Queue10_UInt8_29.io.deq.bits connect remapVecValids[3], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[3] node _T_3396 = eq(UInt<5>(0h1e), remapindex_3) when _T_3396 : connect remapVecData[3], Queue10_UInt8_30.io.deq.bits connect remapVecValids[3], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[3] node _T_3397 = eq(UInt<5>(0h1f), remapindex_3) when _T_3397 : connect remapVecData[3], Queue10_UInt8_31.io.deq.bits connect remapVecValids[3], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[3] node _remapindex_T_4 = add(UInt<3>(0h4), read_start_index) node remapindex_4 = rem(_remapindex_T_4, UInt<6>(0h20)) node _T_3398 = eq(UInt<1>(0h0), remapindex_4) when _T_3398 : connect remapVecData[4], Queue10_UInt8.io.deq.bits connect remapVecValids[4], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[4] node _T_3399 = eq(UInt<1>(0h1), remapindex_4) when _T_3399 : connect remapVecData[4], Queue10_UInt8_1.io.deq.bits connect remapVecValids[4], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[4] node _T_3400 = eq(UInt<2>(0h2), remapindex_4) when _T_3400 : connect remapVecData[4], Queue10_UInt8_2.io.deq.bits connect remapVecValids[4], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[4] node _T_3401 = eq(UInt<2>(0h3), remapindex_4) when _T_3401 : connect remapVecData[4], Queue10_UInt8_3.io.deq.bits connect remapVecValids[4], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[4] node _T_3402 = eq(UInt<3>(0h4), remapindex_4) when _T_3402 : connect remapVecData[4], Queue10_UInt8_4.io.deq.bits connect remapVecValids[4], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[4] node _T_3403 = eq(UInt<3>(0h5), remapindex_4) when _T_3403 : connect remapVecData[4], Queue10_UInt8_5.io.deq.bits connect remapVecValids[4], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[4] node _T_3404 = eq(UInt<3>(0h6), remapindex_4) when _T_3404 : connect remapVecData[4], Queue10_UInt8_6.io.deq.bits connect remapVecValids[4], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[4] node _T_3405 = eq(UInt<3>(0h7), remapindex_4) when _T_3405 : connect remapVecData[4], Queue10_UInt8_7.io.deq.bits connect remapVecValids[4], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[4] node _T_3406 = eq(UInt<4>(0h8), remapindex_4) when _T_3406 : connect remapVecData[4], Queue10_UInt8_8.io.deq.bits connect remapVecValids[4], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[4] node _T_3407 = eq(UInt<4>(0h9), remapindex_4) when _T_3407 : connect remapVecData[4], Queue10_UInt8_9.io.deq.bits connect remapVecValids[4], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[4] node _T_3408 = eq(UInt<4>(0ha), remapindex_4) when _T_3408 : connect remapVecData[4], Queue10_UInt8_10.io.deq.bits connect remapVecValids[4], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[4] node _T_3409 = eq(UInt<4>(0hb), remapindex_4) when _T_3409 : connect remapVecData[4], Queue10_UInt8_11.io.deq.bits connect remapVecValids[4], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[4] node _T_3410 = eq(UInt<4>(0hc), remapindex_4) when _T_3410 : connect remapVecData[4], Queue10_UInt8_12.io.deq.bits connect remapVecValids[4], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[4] node _T_3411 = eq(UInt<4>(0hd), remapindex_4) when _T_3411 : connect remapVecData[4], Queue10_UInt8_13.io.deq.bits connect remapVecValids[4], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[4] node _T_3412 = eq(UInt<4>(0he), remapindex_4) when _T_3412 : connect remapVecData[4], Queue10_UInt8_14.io.deq.bits connect remapVecValids[4], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[4] node _T_3413 = eq(UInt<4>(0hf), remapindex_4) when _T_3413 : connect remapVecData[4], Queue10_UInt8_15.io.deq.bits connect remapVecValids[4], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[4] node _T_3414 = eq(UInt<5>(0h10), remapindex_4) when _T_3414 : connect remapVecData[4], Queue10_UInt8_16.io.deq.bits connect remapVecValids[4], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[4] node _T_3415 = eq(UInt<5>(0h11), remapindex_4) when _T_3415 : connect remapVecData[4], Queue10_UInt8_17.io.deq.bits connect remapVecValids[4], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[4] node _T_3416 = eq(UInt<5>(0h12), remapindex_4) when _T_3416 : connect remapVecData[4], Queue10_UInt8_18.io.deq.bits connect remapVecValids[4], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[4] node _T_3417 = eq(UInt<5>(0h13), remapindex_4) when _T_3417 : connect remapVecData[4], Queue10_UInt8_19.io.deq.bits connect remapVecValids[4], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[4] node _T_3418 = eq(UInt<5>(0h14), remapindex_4) when _T_3418 : connect remapVecData[4], Queue10_UInt8_20.io.deq.bits connect remapVecValids[4], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[4] node _T_3419 = eq(UInt<5>(0h15), remapindex_4) when _T_3419 : connect remapVecData[4], Queue10_UInt8_21.io.deq.bits connect remapVecValids[4], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[4] node _T_3420 = eq(UInt<5>(0h16), remapindex_4) when _T_3420 : connect remapVecData[4], Queue10_UInt8_22.io.deq.bits connect remapVecValids[4], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[4] node _T_3421 = eq(UInt<5>(0h17), remapindex_4) when _T_3421 : connect remapVecData[4], Queue10_UInt8_23.io.deq.bits connect remapVecValids[4], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[4] node _T_3422 = eq(UInt<5>(0h18), remapindex_4) when _T_3422 : connect remapVecData[4], Queue10_UInt8_24.io.deq.bits connect remapVecValids[4], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[4] node _T_3423 = eq(UInt<5>(0h19), remapindex_4) when _T_3423 : connect remapVecData[4], Queue10_UInt8_25.io.deq.bits connect remapVecValids[4], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[4] node _T_3424 = eq(UInt<5>(0h1a), remapindex_4) when _T_3424 : connect remapVecData[4], Queue10_UInt8_26.io.deq.bits connect remapVecValids[4], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[4] node _T_3425 = eq(UInt<5>(0h1b), remapindex_4) when _T_3425 : connect remapVecData[4], Queue10_UInt8_27.io.deq.bits connect remapVecValids[4], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[4] node _T_3426 = eq(UInt<5>(0h1c), remapindex_4) when _T_3426 : connect remapVecData[4], Queue10_UInt8_28.io.deq.bits connect remapVecValids[4], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[4] node _T_3427 = eq(UInt<5>(0h1d), remapindex_4) when _T_3427 : connect remapVecData[4], Queue10_UInt8_29.io.deq.bits connect remapVecValids[4], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[4] node _T_3428 = eq(UInt<5>(0h1e), remapindex_4) when _T_3428 : connect remapVecData[4], Queue10_UInt8_30.io.deq.bits connect remapVecValids[4], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[4] node _T_3429 = eq(UInt<5>(0h1f), remapindex_4) when _T_3429 : connect remapVecData[4], Queue10_UInt8_31.io.deq.bits connect remapVecValids[4], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[4] node _remapindex_T_5 = add(UInt<3>(0h5), read_start_index) node remapindex_5 = rem(_remapindex_T_5, UInt<6>(0h20)) node _T_3430 = eq(UInt<1>(0h0), remapindex_5) when _T_3430 : connect remapVecData[5], Queue10_UInt8.io.deq.bits connect remapVecValids[5], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[5] node _T_3431 = eq(UInt<1>(0h1), remapindex_5) when _T_3431 : connect remapVecData[5], Queue10_UInt8_1.io.deq.bits connect remapVecValids[5], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[5] node _T_3432 = eq(UInt<2>(0h2), remapindex_5) when _T_3432 : connect remapVecData[5], Queue10_UInt8_2.io.deq.bits connect remapVecValids[5], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[5] node _T_3433 = eq(UInt<2>(0h3), remapindex_5) when _T_3433 : connect remapVecData[5], Queue10_UInt8_3.io.deq.bits connect remapVecValids[5], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[5] node _T_3434 = eq(UInt<3>(0h4), remapindex_5) when _T_3434 : connect remapVecData[5], Queue10_UInt8_4.io.deq.bits connect remapVecValids[5], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[5] node _T_3435 = eq(UInt<3>(0h5), remapindex_5) when _T_3435 : connect remapVecData[5], Queue10_UInt8_5.io.deq.bits connect remapVecValids[5], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[5] node _T_3436 = eq(UInt<3>(0h6), remapindex_5) when _T_3436 : connect remapVecData[5], Queue10_UInt8_6.io.deq.bits connect remapVecValids[5], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[5] node _T_3437 = eq(UInt<3>(0h7), remapindex_5) when _T_3437 : connect remapVecData[5], Queue10_UInt8_7.io.deq.bits connect remapVecValids[5], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[5] node _T_3438 = eq(UInt<4>(0h8), remapindex_5) when _T_3438 : connect remapVecData[5], Queue10_UInt8_8.io.deq.bits connect remapVecValids[5], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[5] node _T_3439 = eq(UInt<4>(0h9), remapindex_5) when _T_3439 : connect remapVecData[5], Queue10_UInt8_9.io.deq.bits connect remapVecValids[5], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[5] node _T_3440 = eq(UInt<4>(0ha), remapindex_5) when _T_3440 : connect remapVecData[5], Queue10_UInt8_10.io.deq.bits connect remapVecValids[5], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[5] node _T_3441 = eq(UInt<4>(0hb), remapindex_5) when _T_3441 : connect remapVecData[5], Queue10_UInt8_11.io.deq.bits connect remapVecValids[5], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[5] node _T_3442 = eq(UInt<4>(0hc), remapindex_5) when _T_3442 : connect remapVecData[5], Queue10_UInt8_12.io.deq.bits connect remapVecValids[5], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[5] node _T_3443 = eq(UInt<4>(0hd), remapindex_5) when _T_3443 : connect remapVecData[5], Queue10_UInt8_13.io.deq.bits connect remapVecValids[5], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[5] node _T_3444 = eq(UInt<4>(0he), remapindex_5) when _T_3444 : connect remapVecData[5], Queue10_UInt8_14.io.deq.bits connect remapVecValids[5], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[5] node _T_3445 = eq(UInt<4>(0hf), remapindex_5) when _T_3445 : connect remapVecData[5], Queue10_UInt8_15.io.deq.bits connect remapVecValids[5], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[5] node _T_3446 = eq(UInt<5>(0h10), remapindex_5) when _T_3446 : connect remapVecData[5], Queue10_UInt8_16.io.deq.bits connect remapVecValids[5], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[5] node _T_3447 = eq(UInt<5>(0h11), remapindex_5) when _T_3447 : connect remapVecData[5], Queue10_UInt8_17.io.deq.bits connect remapVecValids[5], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[5] node _T_3448 = eq(UInt<5>(0h12), remapindex_5) when _T_3448 : connect remapVecData[5], Queue10_UInt8_18.io.deq.bits connect remapVecValids[5], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[5] node _T_3449 = eq(UInt<5>(0h13), remapindex_5) when _T_3449 : connect remapVecData[5], Queue10_UInt8_19.io.deq.bits connect remapVecValids[5], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[5] node _T_3450 = eq(UInt<5>(0h14), remapindex_5) when _T_3450 : connect remapVecData[5], Queue10_UInt8_20.io.deq.bits connect remapVecValids[5], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[5] node _T_3451 = eq(UInt<5>(0h15), remapindex_5) when _T_3451 : connect remapVecData[5], Queue10_UInt8_21.io.deq.bits connect remapVecValids[5], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[5] node _T_3452 = eq(UInt<5>(0h16), remapindex_5) when _T_3452 : connect remapVecData[5], Queue10_UInt8_22.io.deq.bits connect remapVecValids[5], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[5] node _T_3453 = eq(UInt<5>(0h17), remapindex_5) when _T_3453 : connect remapVecData[5], Queue10_UInt8_23.io.deq.bits connect remapVecValids[5], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[5] node _T_3454 = eq(UInt<5>(0h18), remapindex_5) when _T_3454 : connect remapVecData[5], Queue10_UInt8_24.io.deq.bits connect remapVecValids[5], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[5] node _T_3455 = eq(UInt<5>(0h19), remapindex_5) when _T_3455 : connect remapVecData[5], Queue10_UInt8_25.io.deq.bits connect remapVecValids[5], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[5] node _T_3456 = eq(UInt<5>(0h1a), remapindex_5) when _T_3456 : connect remapVecData[5], Queue10_UInt8_26.io.deq.bits connect remapVecValids[5], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[5] node _T_3457 = eq(UInt<5>(0h1b), remapindex_5) when _T_3457 : connect remapVecData[5], Queue10_UInt8_27.io.deq.bits connect remapVecValids[5], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[5] node _T_3458 = eq(UInt<5>(0h1c), remapindex_5) when _T_3458 : connect remapVecData[5], Queue10_UInt8_28.io.deq.bits connect remapVecValids[5], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[5] node _T_3459 = eq(UInt<5>(0h1d), remapindex_5) when _T_3459 : connect remapVecData[5], Queue10_UInt8_29.io.deq.bits connect remapVecValids[5], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[5] node _T_3460 = eq(UInt<5>(0h1e), remapindex_5) when _T_3460 : connect remapVecData[5], Queue10_UInt8_30.io.deq.bits connect remapVecValids[5], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[5] node _T_3461 = eq(UInt<5>(0h1f), remapindex_5) when _T_3461 : connect remapVecData[5], Queue10_UInt8_31.io.deq.bits connect remapVecValids[5], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[5] node _remapindex_T_6 = add(UInt<3>(0h6), read_start_index) node remapindex_6 = rem(_remapindex_T_6, UInt<6>(0h20)) node _T_3462 = eq(UInt<1>(0h0), remapindex_6) when _T_3462 : connect remapVecData[6], Queue10_UInt8.io.deq.bits connect remapVecValids[6], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[6] node _T_3463 = eq(UInt<1>(0h1), remapindex_6) when _T_3463 : connect remapVecData[6], Queue10_UInt8_1.io.deq.bits connect remapVecValids[6], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[6] node _T_3464 = eq(UInt<2>(0h2), remapindex_6) when _T_3464 : connect remapVecData[6], Queue10_UInt8_2.io.deq.bits connect remapVecValids[6], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[6] node _T_3465 = eq(UInt<2>(0h3), remapindex_6) when _T_3465 : connect remapVecData[6], Queue10_UInt8_3.io.deq.bits connect remapVecValids[6], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[6] node _T_3466 = eq(UInt<3>(0h4), remapindex_6) when _T_3466 : connect remapVecData[6], Queue10_UInt8_4.io.deq.bits connect remapVecValids[6], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[6] node _T_3467 = eq(UInt<3>(0h5), remapindex_6) when _T_3467 : connect remapVecData[6], Queue10_UInt8_5.io.deq.bits connect remapVecValids[6], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[6] node _T_3468 = eq(UInt<3>(0h6), remapindex_6) when _T_3468 : connect remapVecData[6], Queue10_UInt8_6.io.deq.bits connect remapVecValids[6], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[6] node _T_3469 = eq(UInt<3>(0h7), remapindex_6) when _T_3469 : connect remapVecData[6], Queue10_UInt8_7.io.deq.bits connect remapVecValids[6], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[6] node _T_3470 = eq(UInt<4>(0h8), remapindex_6) when _T_3470 : connect remapVecData[6], Queue10_UInt8_8.io.deq.bits connect remapVecValids[6], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[6] node _T_3471 = eq(UInt<4>(0h9), remapindex_6) when _T_3471 : connect remapVecData[6], Queue10_UInt8_9.io.deq.bits connect remapVecValids[6], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[6] node _T_3472 = eq(UInt<4>(0ha), remapindex_6) when _T_3472 : connect remapVecData[6], Queue10_UInt8_10.io.deq.bits connect remapVecValids[6], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[6] node _T_3473 = eq(UInt<4>(0hb), remapindex_6) when _T_3473 : connect remapVecData[6], Queue10_UInt8_11.io.deq.bits connect remapVecValids[6], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[6] node _T_3474 = eq(UInt<4>(0hc), remapindex_6) when _T_3474 : connect remapVecData[6], Queue10_UInt8_12.io.deq.bits connect remapVecValids[6], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[6] node _T_3475 = eq(UInt<4>(0hd), remapindex_6) when _T_3475 : connect remapVecData[6], Queue10_UInt8_13.io.deq.bits connect remapVecValids[6], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[6] node _T_3476 = eq(UInt<4>(0he), remapindex_6) when _T_3476 : connect remapVecData[6], Queue10_UInt8_14.io.deq.bits connect remapVecValids[6], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[6] node _T_3477 = eq(UInt<4>(0hf), remapindex_6) when _T_3477 : connect remapVecData[6], Queue10_UInt8_15.io.deq.bits connect remapVecValids[6], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[6] node _T_3478 = eq(UInt<5>(0h10), remapindex_6) when _T_3478 : connect remapVecData[6], Queue10_UInt8_16.io.deq.bits connect remapVecValids[6], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[6] node _T_3479 = eq(UInt<5>(0h11), remapindex_6) when _T_3479 : connect remapVecData[6], Queue10_UInt8_17.io.deq.bits connect remapVecValids[6], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[6] node _T_3480 = eq(UInt<5>(0h12), remapindex_6) when _T_3480 : connect remapVecData[6], Queue10_UInt8_18.io.deq.bits connect remapVecValids[6], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[6] node _T_3481 = eq(UInt<5>(0h13), remapindex_6) when _T_3481 : connect remapVecData[6], Queue10_UInt8_19.io.deq.bits connect remapVecValids[6], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[6] node _T_3482 = eq(UInt<5>(0h14), remapindex_6) when _T_3482 : connect remapVecData[6], Queue10_UInt8_20.io.deq.bits connect remapVecValids[6], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[6] node _T_3483 = eq(UInt<5>(0h15), remapindex_6) when _T_3483 : connect remapVecData[6], Queue10_UInt8_21.io.deq.bits connect remapVecValids[6], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[6] node _T_3484 = eq(UInt<5>(0h16), remapindex_6) when _T_3484 : connect remapVecData[6], Queue10_UInt8_22.io.deq.bits connect remapVecValids[6], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[6] node _T_3485 = eq(UInt<5>(0h17), remapindex_6) when _T_3485 : connect remapVecData[6], Queue10_UInt8_23.io.deq.bits connect remapVecValids[6], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[6] node _T_3486 = eq(UInt<5>(0h18), remapindex_6) when _T_3486 : connect remapVecData[6], Queue10_UInt8_24.io.deq.bits connect remapVecValids[6], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[6] node _T_3487 = eq(UInt<5>(0h19), remapindex_6) when _T_3487 : connect remapVecData[6], Queue10_UInt8_25.io.deq.bits connect remapVecValids[6], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[6] node _T_3488 = eq(UInt<5>(0h1a), remapindex_6) when _T_3488 : connect remapVecData[6], Queue10_UInt8_26.io.deq.bits connect remapVecValids[6], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[6] node _T_3489 = eq(UInt<5>(0h1b), remapindex_6) when _T_3489 : connect remapVecData[6], Queue10_UInt8_27.io.deq.bits connect remapVecValids[6], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[6] node _T_3490 = eq(UInt<5>(0h1c), remapindex_6) when _T_3490 : connect remapVecData[6], Queue10_UInt8_28.io.deq.bits connect remapVecValids[6], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[6] node _T_3491 = eq(UInt<5>(0h1d), remapindex_6) when _T_3491 : connect remapVecData[6], Queue10_UInt8_29.io.deq.bits connect remapVecValids[6], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[6] node _T_3492 = eq(UInt<5>(0h1e), remapindex_6) when _T_3492 : connect remapVecData[6], Queue10_UInt8_30.io.deq.bits connect remapVecValids[6], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[6] node _T_3493 = eq(UInt<5>(0h1f), remapindex_6) when _T_3493 : connect remapVecData[6], Queue10_UInt8_31.io.deq.bits connect remapVecValids[6], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[6] node _remapindex_T_7 = add(UInt<3>(0h7), read_start_index) node remapindex_7 = rem(_remapindex_T_7, UInt<6>(0h20)) node _T_3494 = eq(UInt<1>(0h0), remapindex_7) when _T_3494 : connect remapVecData[7], Queue10_UInt8.io.deq.bits connect remapVecValids[7], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[7] node _T_3495 = eq(UInt<1>(0h1), remapindex_7) when _T_3495 : connect remapVecData[7], Queue10_UInt8_1.io.deq.bits connect remapVecValids[7], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[7] node _T_3496 = eq(UInt<2>(0h2), remapindex_7) when _T_3496 : connect remapVecData[7], Queue10_UInt8_2.io.deq.bits connect remapVecValids[7], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[7] node _T_3497 = eq(UInt<2>(0h3), remapindex_7) when _T_3497 : connect remapVecData[7], Queue10_UInt8_3.io.deq.bits connect remapVecValids[7], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[7] node _T_3498 = eq(UInt<3>(0h4), remapindex_7) when _T_3498 : connect remapVecData[7], Queue10_UInt8_4.io.deq.bits connect remapVecValids[7], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[7] node _T_3499 = eq(UInt<3>(0h5), remapindex_7) when _T_3499 : connect remapVecData[7], Queue10_UInt8_5.io.deq.bits connect remapVecValids[7], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[7] node _T_3500 = eq(UInt<3>(0h6), remapindex_7) when _T_3500 : connect remapVecData[7], Queue10_UInt8_6.io.deq.bits connect remapVecValids[7], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[7] node _T_3501 = eq(UInt<3>(0h7), remapindex_7) when _T_3501 : connect remapVecData[7], Queue10_UInt8_7.io.deq.bits connect remapVecValids[7], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[7] node _T_3502 = eq(UInt<4>(0h8), remapindex_7) when _T_3502 : connect remapVecData[7], Queue10_UInt8_8.io.deq.bits connect remapVecValids[7], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[7] node _T_3503 = eq(UInt<4>(0h9), remapindex_7) when _T_3503 : connect remapVecData[7], Queue10_UInt8_9.io.deq.bits connect remapVecValids[7], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[7] node _T_3504 = eq(UInt<4>(0ha), remapindex_7) when _T_3504 : connect remapVecData[7], Queue10_UInt8_10.io.deq.bits connect remapVecValids[7], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[7] node _T_3505 = eq(UInt<4>(0hb), remapindex_7) when _T_3505 : connect remapVecData[7], Queue10_UInt8_11.io.deq.bits connect remapVecValids[7], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[7] node _T_3506 = eq(UInt<4>(0hc), remapindex_7) when _T_3506 : connect remapVecData[7], Queue10_UInt8_12.io.deq.bits connect remapVecValids[7], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[7] node _T_3507 = eq(UInt<4>(0hd), remapindex_7) when _T_3507 : connect remapVecData[7], Queue10_UInt8_13.io.deq.bits connect remapVecValids[7], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[7] node _T_3508 = eq(UInt<4>(0he), remapindex_7) when _T_3508 : connect remapVecData[7], Queue10_UInt8_14.io.deq.bits connect remapVecValids[7], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[7] node _T_3509 = eq(UInt<4>(0hf), remapindex_7) when _T_3509 : connect remapVecData[7], Queue10_UInt8_15.io.deq.bits connect remapVecValids[7], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[7] node _T_3510 = eq(UInt<5>(0h10), remapindex_7) when _T_3510 : connect remapVecData[7], Queue10_UInt8_16.io.deq.bits connect remapVecValids[7], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[7] node _T_3511 = eq(UInt<5>(0h11), remapindex_7) when _T_3511 : connect remapVecData[7], Queue10_UInt8_17.io.deq.bits connect remapVecValids[7], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[7] node _T_3512 = eq(UInt<5>(0h12), remapindex_7) when _T_3512 : connect remapVecData[7], Queue10_UInt8_18.io.deq.bits connect remapVecValids[7], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[7] node _T_3513 = eq(UInt<5>(0h13), remapindex_7) when _T_3513 : connect remapVecData[7], Queue10_UInt8_19.io.deq.bits connect remapVecValids[7], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[7] node _T_3514 = eq(UInt<5>(0h14), remapindex_7) when _T_3514 : connect remapVecData[7], Queue10_UInt8_20.io.deq.bits connect remapVecValids[7], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[7] node _T_3515 = eq(UInt<5>(0h15), remapindex_7) when _T_3515 : connect remapVecData[7], Queue10_UInt8_21.io.deq.bits connect remapVecValids[7], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[7] node _T_3516 = eq(UInt<5>(0h16), remapindex_7) when _T_3516 : connect remapVecData[7], Queue10_UInt8_22.io.deq.bits connect remapVecValids[7], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[7] node _T_3517 = eq(UInt<5>(0h17), remapindex_7) when _T_3517 : connect remapVecData[7], Queue10_UInt8_23.io.deq.bits connect remapVecValids[7], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[7] node _T_3518 = eq(UInt<5>(0h18), remapindex_7) when _T_3518 : connect remapVecData[7], Queue10_UInt8_24.io.deq.bits connect remapVecValids[7], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[7] node _T_3519 = eq(UInt<5>(0h19), remapindex_7) when _T_3519 : connect remapVecData[7], Queue10_UInt8_25.io.deq.bits connect remapVecValids[7], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[7] node _T_3520 = eq(UInt<5>(0h1a), remapindex_7) when _T_3520 : connect remapVecData[7], Queue10_UInt8_26.io.deq.bits connect remapVecValids[7], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[7] node _T_3521 = eq(UInt<5>(0h1b), remapindex_7) when _T_3521 : connect remapVecData[7], Queue10_UInt8_27.io.deq.bits connect remapVecValids[7], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[7] node _T_3522 = eq(UInt<5>(0h1c), remapindex_7) when _T_3522 : connect remapVecData[7], Queue10_UInt8_28.io.deq.bits connect remapVecValids[7], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[7] node _T_3523 = eq(UInt<5>(0h1d), remapindex_7) when _T_3523 : connect remapVecData[7], Queue10_UInt8_29.io.deq.bits connect remapVecValids[7], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[7] node _T_3524 = eq(UInt<5>(0h1e), remapindex_7) when _T_3524 : connect remapVecData[7], Queue10_UInt8_30.io.deq.bits connect remapVecValids[7], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[7] node _T_3525 = eq(UInt<5>(0h1f), remapindex_7) when _T_3525 : connect remapVecData[7], Queue10_UInt8_31.io.deq.bits connect remapVecValids[7], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[7] node _remapindex_T_8 = add(UInt<4>(0h8), read_start_index) node remapindex_8 = rem(_remapindex_T_8, UInt<6>(0h20)) node _T_3526 = eq(UInt<1>(0h0), remapindex_8) when _T_3526 : connect remapVecData[8], Queue10_UInt8.io.deq.bits connect remapVecValids[8], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[8] node _T_3527 = eq(UInt<1>(0h1), remapindex_8) when _T_3527 : connect remapVecData[8], Queue10_UInt8_1.io.deq.bits connect remapVecValids[8], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[8] node _T_3528 = eq(UInt<2>(0h2), remapindex_8) when _T_3528 : connect remapVecData[8], Queue10_UInt8_2.io.deq.bits connect remapVecValids[8], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[8] node _T_3529 = eq(UInt<2>(0h3), remapindex_8) when _T_3529 : connect remapVecData[8], Queue10_UInt8_3.io.deq.bits connect remapVecValids[8], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[8] node _T_3530 = eq(UInt<3>(0h4), remapindex_8) when _T_3530 : connect remapVecData[8], Queue10_UInt8_4.io.deq.bits connect remapVecValids[8], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[8] node _T_3531 = eq(UInt<3>(0h5), remapindex_8) when _T_3531 : connect remapVecData[8], Queue10_UInt8_5.io.deq.bits connect remapVecValids[8], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[8] node _T_3532 = eq(UInt<3>(0h6), remapindex_8) when _T_3532 : connect remapVecData[8], Queue10_UInt8_6.io.deq.bits connect remapVecValids[8], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[8] node _T_3533 = eq(UInt<3>(0h7), remapindex_8) when _T_3533 : connect remapVecData[8], Queue10_UInt8_7.io.deq.bits connect remapVecValids[8], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[8] node _T_3534 = eq(UInt<4>(0h8), remapindex_8) when _T_3534 : connect remapVecData[8], Queue10_UInt8_8.io.deq.bits connect remapVecValids[8], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[8] node _T_3535 = eq(UInt<4>(0h9), remapindex_8) when _T_3535 : connect remapVecData[8], Queue10_UInt8_9.io.deq.bits connect remapVecValids[8], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[8] node _T_3536 = eq(UInt<4>(0ha), remapindex_8) when _T_3536 : connect remapVecData[8], Queue10_UInt8_10.io.deq.bits connect remapVecValids[8], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[8] node _T_3537 = eq(UInt<4>(0hb), remapindex_8) when _T_3537 : connect remapVecData[8], Queue10_UInt8_11.io.deq.bits connect remapVecValids[8], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[8] node _T_3538 = eq(UInt<4>(0hc), remapindex_8) when _T_3538 : connect remapVecData[8], Queue10_UInt8_12.io.deq.bits connect remapVecValids[8], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[8] node _T_3539 = eq(UInt<4>(0hd), remapindex_8) when _T_3539 : connect remapVecData[8], Queue10_UInt8_13.io.deq.bits connect remapVecValids[8], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[8] node _T_3540 = eq(UInt<4>(0he), remapindex_8) when _T_3540 : connect remapVecData[8], Queue10_UInt8_14.io.deq.bits connect remapVecValids[8], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[8] node _T_3541 = eq(UInt<4>(0hf), remapindex_8) when _T_3541 : connect remapVecData[8], Queue10_UInt8_15.io.deq.bits connect remapVecValids[8], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[8] node _T_3542 = eq(UInt<5>(0h10), remapindex_8) when _T_3542 : connect remapVecData[8], Queue10_UInt8_16.io.deq.bits connect remapVecValids[8], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[8] node _T_3543 = eq(UInt<5>(0h11), remapindex_8) when _T_3543 : connect remapVecData[8], Queue10_UInt8_17.io.deq.bits connect remapVecValids[8], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[8] node _T_3544 = eq(UInt<5>(0h12), remapindex_8) when _T_3544 : connect remapVecData[8], Queue10_UInt8_18.io.deq.bits connect remapVecValids[8], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[8] node _T_3545 = eq(UInt<5>(0h13), remapindex_8) when _T_3545 : connect remapVecData[8], Queue10_UInt8_19.io.deq.bits connect remapVecValids[8], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[8] node _T_3546 = eq(UInt<5>(0h14), remapindex_8) when _T_3546 : connect remapVecData[8], Queue10_UInt8_20.io.deq.bits connect remapVecValids[8], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[8] node _T_3547 = eq(UInt<5>(0h15), remapindex_8) when _T_3547 : connect remapVecData[8], Queue10_UInt8_21.io.deq.bits connect remapVecValids[8], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[8] node _T_3548 = eq(UInt<5>(0h16), remapindex_8) when _T_3548 : connect remapVecData[8], Queue10_UInt8_22.io.deq.bits connect remapVecValids[8], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[8] node _T_3549 = eq(UInt<5>(0h17), remapindex_8) when _T_3549 : connect remapVecData[8], Queue10_UInt8_23.io.deq.bits connect remapVecValids[8], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[8] node _T_3550 = eq(UInt<5>(0h18), remapindex_8) when _T_3550 : connect remapVecData[8], Queue10_UInt8_24.io.deq.bits connect remapVecValids[8], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[8] node _T_3551 = eq(UInt<5>(0h19), remapindex_8) when _T_3551 : connect remapVecData[8], Queue10_UInt8_25.io.deq.bits connect remapVecValids[8], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[8] node _T_3552 = eq(UInt<5>(0h1a), remapindex_8) when _T_3552 : connect remapVecData[8], Queue10_UInt8_26.io.deq.bits connect remapVecValids[8], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[8] node _T_3553 = eq(UInt<5>(0h1b), remapindex_8) when _T_3553 : connect remapVecData[8], Queue10_UInt8_27.io.deq.bits connect remapVecValids[8], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[8] node _T_3554 = eq(UInt<5>(0h1c), remapindex_8) when _T_3554 : connect remapVecData[8], Queue10_UInt8_28.io.deq.bits connect remapVecValids[8], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[8] node _T_3555 = eq(UInt<5>(0h1d), remapindex_8) when _T_3555 : connect remapVecData[8], Queue10_UInt8_29.io.deq.bits connect remapVecValids[8], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[8] node _T_3556 = eq(UInt<5>(0h1e), remapindex_8) when _T_3556 : connect remapVecData[8], Queue10_UInt8_30.io.deq.bits connect remapVecValids[8], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[8] node _T_3557 = eq(UInt<5>(0h1f), remapindex_8) when _T_3557 : connect remapVecData[8], Queue10_UInt8_31.io.deq.bits connect remapVecValids[8], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[8] node _remapindex_T_9 = add(UInt<4>(0h9), read_start_index) node remapindex_9 = rem(_remapindex_T_9, UInt<6>(0h20)) node _T_3558 = eq(UInt<1>(0h0), remapindex_9) when _T_3558 : connect remapVecData[9], Queue10_UInt8.io.deq.bits connect remapVecValids[9], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[9] node _T_3559 = eq(UInt<1>(0h1), remapindex_9) when _T_3559 : connect remapVecData[9], Queue10_UInt8_1.io.deq.bits connect remapVecValids[9], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[9] node _T_3560 = eq(UInt<2>(0h2), remapindex_9) when _T_3560 : connect remapVecData[9], Queue10_UInt8_2.io.deq.bits connect remapVecValids[9], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[9] node _T_3561 = eq(UInt<2>(0h3), remapindex_9) when _T_3561 : connect remapVecData[9], Queue10_UInt8_3.io.deq.bits connect remapVecValids[9], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[9] node _T_3562 = eq(UInt<3>(0h4), remapindex_9) when _T_3562 : connect remapVecData[9], Queue10_UInt8_4.io.deq.bits connect remapVecValids[9], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[9] node _T_3563 = eq(UInt<3>(0h5), remapindex_9) when _T_3563 : connect remapVecData[9], Queue10_UInt8_5.io.deq.bits connect remapVecValids[9], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[9] node _T_3564 = eq(UInt<3>(0h6), remapindex_9) when _T_3564 : connect remapVecData[9], Queue10_UInt8_6.io.deq.bits connect remapVecValids[9], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[9] node _T_3565 = eq(UInt<3>(0h7), remapindex_9) when _T_3565 : connect remapVecData[9], Queue10_UInt8_7.io.deq.bits connect remapVecValids[9], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[9] node _T_3566 = eq(UInt<4>(0h8), remapindex_9) when _T_3566 : connect remapVecData[9], Queue10_UInt8_8.io.deq.bits connect remapVecValids[9], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[9] node _T_3567 = eq(UInt<4>(0h9), remapindex_9) when _T_3567 : connect remapVecData[9], Queue10_UInt8_9.io.deq.bits connect remapVecValids[9], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[9] node _T_3568 = eq(UInt<4>(0ha), remapindex_9) when _T_3568 : connect remapVecData[9], Queue10_UInt8_10.io.deq.bits connect remapVecValids[9], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[9] node _T_3569 = eq(UInt<4>(0hb), remapindex_9) when _T_3569 : connect remapVecData[9], Queue10_UInt8_11.io.deq.bits connect remapVecValids[9], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[9] node _T_3570 = eq(UInt<4>(0hc), remapindex_9) when _T_3570 : connect remapVecData[9], Queue10_UInt8_12.io.deq.bits connect remapVecValids[9], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[9] node _T_3571 = eq(UInt<4>(0hd), remapindex_9) when _T_3571 : connect remapVecData[9], Queue10_UInt8_13.io.deq.bits connect remapVecValids[9], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[9] node _T_3572 = eq(UInt<4>(0he), remapindex_9) when _T_3572 : connect remapVecData[9], Queue10_UInt8_14.io.deq.bits connect remapVecValids[9], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[9] node _T_3573 = eq(UInt<4>(0hf), remapindex_9) when _T_3573 : connect remapVecData[9], Queue10_UInt8_15.io.deq.bits connect remapVecValids[9], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[9] node _T_3574 = eq(UInt<5>(0h10), remapindex_9) when _T_3574 : connect remapVecData[9], Queue10_UInt8_16.io.deq.bits connect remapVecValids[9], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[9] node _T_3575 = eq(UInt<5>(0h11), remapindex_9) when _T_3575 : connect remapVecData[9], Queue10_UInt8_17.io.deq.bits connect remapVecValids[9], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[9] node _T_3576 = eq(UInt<5>(0h12), remapindex_9) when _T_3576 : connect remapVecData[9], Queue10_UInt8_18.io.deq.bits connect remapVecValids[9], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[9] node _T_3577 = eq(UInt<5>(0h13), remapindex_9) when _T_3577 : connect remapVecData[9], Queue10_UInt8_19.io.deq.bits connect remapVecValids[9], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[9] node _T_3578 = eq(UInt<5>(0h14), remapindex_9) when _T_3578 : connect remapVecData[9], Queue10_UInt8_20.io.deq.bits connect remapVecValids[9], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[9] node _T_3579 = eq(UInt<5>(0h15), remapindex_9) when _T_3579 : connect remapVecData[9], Queue10_UInt8_21.io.deq.bits connect remapVecValids[9], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[9] node _T_3580 = eq(UInt<5>(0h16), remapindex_9) when _T_3580 : connect remapVecData[9], Queue10_UInt8_22.io.deq.bits connect remapVecValids[9], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[9] node _T_3581 = eq(UInt<5>(0h17), remapindex_9) when _T_3581 : connect remapVecData[9], Queue10_UInt8_23.io.deq.bits connect remapVecValids[9], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[9] node _T_3582 = eq(UInt<5>(0h18), remapindex_9) when _T_3582 : connect remapVecData[9], Queue10_UInt8_24.io.deq.bits connect remapVecValids[9], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[9] node _T_3583 = eq(UInt<5>(0h19), remapindex_9) when _T_3583 : connect remapVecData[9], Queue10_UInt8_25.io.deq.bits connect remapVecValids[9], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[9] node _T_3584 = eq(UInt<5>(0h1a), remapindex_9) when _T_3584 : connect remapVecData[9], Queue10_UInt8_26.io.deq.bits connect remapVecValids[9], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[9] node _T_3585 = eq(UInt<5>(0h1b), remapindex_9) when _T_3585 : connect remapVecData[9], Queue10_UInt8_27.io.deq.bits connect remapVecValids[9], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[9] node _T_3586 = eq(UInt<5>(0h1c), remapindex_9) when _T_3586 : connect remapVecData[9], Queue10_UInt8_28.io.deq.bits connect remapVecValids[9], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[9] node _T_3587 = eq(UInt<5>(0h1d), remapindex_9) when _T_3587 : connect remapVecData[9], Queue10_UInt8_29.io.deq.bits connect remapVecValids[9], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[9] node _T_3588 = eq(UInt<5>(0h1e), remapindex_9) when _T_3588 : connect remapVecData[9], Queue10_UInt8_30.io.deq.bits connect remapVecValids[9], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[9] node _T_3589 = eq(UInt<5>(0h1f), remapindex_9) when _T_3589 : connect remapVecData[9], Queue10_UInt8_31.io.deq.bits connect remapVecValids[9], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[9] node _remapindex_T_10 = add(UInt<4>(0ha), read_start_index) node remapindex_10 = rem(_remapindex_T_10, UInt<6>(0h20)) node _T_3590 = eq(UInt<1>(0h0), remapindex_10) when _T_3590 : connect remapVecData[10], Queue10_UInt8.io.deq.bits connect remapVecValids[10], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[10] node _T_3591 = eq(UInt<1>(0h1), remapindex_10) when _T_3591 : connect remapVecData[10], Queue10_UInt8_1.io.deq.bits connect remapVecValids[10], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[10] node _T_3592 = eq(UInt<2>(0h2), remapindex_10) when _T_3592 : connect remapVecData[10], Queue10_UInt8_2.io.deq.bits connect remapVecValids[10], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[10] node _T_3593 = eq(UInt<2>(0h3), remapindex_10) when _T_3593 : connect remapVecData[10], Queue10_UInt8_3.io.deq.bits connect remapVecValids[10], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[10] node _T_3594 = eq(UInt<3>(0h4), remapindex_10) when _T_3594 : connect remapVecData[10], Queue10_UInt8_4.io.deq.bits connect remapVecValids[10], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[10] node _T_3595 = eq(UInt<3>(0h5), remapindex_10) when _T_3595 : connect remapVecData[10], Queue10_UInt8_5.io.deq.bits connect remapVecValids[10], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[10] node _T_3596 = eq(UInt<3>(0h6), remapindex_10) when _T_3596 : connect remapVecData[10], Queue10_UInt8_6.io.deq.bits connect remapVecValids[10], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[10] node _T_3597 = eq(UInt<3>(0h7), remapindex_10) when _T_3597 : connect remapVecData[10], Queue10_UInt8_7.io.deq.bits connect remapVecValids[10], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[10] node _T_3598 = eq(UInt<4>(0h8), remapindex_10) when _T_3598 : connect remapVecData[10], Queue10_UInt8_8.io.deq.bits connect remapVecValids[10], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[10] node _T_3599 = eq(UInt<4>(0h9), remapindex_10) when _T_3599 : connect remapVecData[10], Queue10_UInt8_9.io.deq.bits connect remapVecValids[10], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[10] node _T_3600 = eq(UInt<4>(0ha), remapindex_10) when _T_3600 : connect remapVecData[10], Queue10_UInt8_10.io.deq.bits connect remapVecValids[10], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[10] node _T_3601 = eq(UInt<4>(0hb), remapindex_10) when _T_3601 : connect remapVecData[10], Queue10_UInt8_11.io.deq.bits connect remapVecValids[10], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[10] node _T_3602 = eq(UInt<4>(0hc), remapindex_10) when _T_3602 : connect remapVecData[10], Queue10_UInt8_12.io.deq.bits connect remapVecValids[10], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[10] node _T_3603 = eq(UInt<4>(0hd), remapindex_10) when _T_3603 : connect remapVecData[10], Queue10_UInt8_13.io.deq.bits connect remapVecValids[10], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[10] node _T_3604 = eq(UInt<4>(0he), remapindex_10) when _T_3604 : connect remapVecData[10], Queue10_UInt8_14.io.deq.bits connect remapVecValids[10], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[10] node _T_3605 = eq(UInt<4>(0hf), remapindex_10) when _T_3605 : connect remapVecData[10], Queue10_UInt8_15.io.deq.bits connect remapVecValids[10], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[10] node _T_3606 = eq(UInt<5>(0h10), remapindex_10) when _T_3606 : connect remapVecData[10], Queue10_UInt8_16.io.deq.bits connect remapVecValids[10], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[10] node _T_3607 = eq(UInt<5>(0h11), remapindex_10) when _T_3607 : connect remapVecData[10], Queue10_UInt8_17.io.deq.bits connect remapVecValids[10], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[10] node _T_3608 = eq(UInt<5>(0h12), remapindex_10) when _T_3608 : connect remapVecData[10], Queue10_UInt8_18.io.deq.bits connect remapVecValids[10], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[10] node _T_3609 = eq(UInt<5>(0h13), remapindex_10) when _T_3609 : connect remapVecData[10], Queue10_UInt8_19.io.deq.bits connect remapVecValids[10], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[10] node _T_3610 = eq(UInt<5>(0h14), remapindex_10) when _T_3610 : connect remapVecData[10], Queue10_UInt8_20.io.deq.bits connect remapVecValids[10], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[10] node _T_3611 = eq(UInt<5>(0h15), remapindex_10) when _T_3611 : connect remapVecData[10], Queue10_UInt8_21.io.deq.bits connect remapVecValids[10], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[10] node _T_3612 = eq(UInt<5>(0h16), remapindex_10) when _T_3612 : connect remapVecData[10], Queue10_UInt8_22.io.deq.bits connect remapVecValids[10], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[10] node _T_3613 = eq(UInt<5>(0h17), remapindex_10) when _T_3613 : connect remapVecData[10], Queue10_UInt8_23.io.deq.bits connect remapVecValids[10], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[10] node _T_3614 = eq(UInt<5>(0h18), remapindex_10) when _T_3614 : connect remapVecData[10], Queue10_UInt8_24.io.deq.bits connect remapVecValids[10], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[10] node _T_3615 = eq(UInt<5>(0h19), remapindex_10) when _T_3615 : connect remapVecData[10], Queue10_UInt8_25.io.deq.bits connect remapVecValids[10], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[10] node _T_3616 = eq(UInt<5>(0h1a), remapindex_10) when _T_3616 : connect remapVecData[10], Queue10_UInt8_26.io.deq.bits connect remapVecValids[10], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[10] node _T_3617 = eq(UInt<5>(0h1b), remapindex_10) when _T_3617 : connect remapVecData[10], Queue10_UInt8_27.io.deq.bits connect remapVecValids[10], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[10] node _T_3618 = eq(UInt<5>(0h1c), remapindex_10) when _T_3618 : connect remapVecData[10], Queue10_UInt8_28.io.deq.bits connect remapVecValids[10], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[10] node _T_3619 = eq(UInt<5>(0h1d), remapindex_10) when _T_3619 : connect remapVecData[10], Queue10_UInt8_29.io.deq.bits connect remapVecValids[10], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[10] node _T_3620 = eq(UInt<5>(0h1e), remapindex_10) when _T_3620 : connect remapVecData[10], Queue10_UInt8_30.io.deq.bits connect remapVecValids[10], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[10] node _T_3621 = eq(UInt<5>(0h1f), remapindex_10) when _T_3621 : connect remapVecData[10], Queue10_UInt8_31.io.deq.bits connect remapVecValids[10], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[10] node _remapindex_T_11 = add(UInt<4>(0hb), read_start_index) node remapindex_11 = rem(_remapindex_T_11, UInt<6>(0h20)) node _T_3622 = eq(UInt<1>(0h0), remapindex_11) when _T_3622 : connect remapVecData[11], Queue10_UInt8.io.deq.bits connect remapVecValids[11], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[11] node _T_3623 = eq(UInt<1>(0h1), remapindex_11) when _T_3623 : connect remapVecData[11], Queue10_UInt8_1.io.deq.bits connect remapVecValids[11], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[11] node _T_3624 = eq(UInt<2>(0h2), remapindex_11) when _T_3624 : connect remapVecData[11], Queue10_UInt8_2.io.deq.bits connect remapVecValids[11], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[11] node _T_3625 = eq(UInt<2>(0h3), remapindex_11) when _T_3625 : connect remapVecData[11], Queue10_UInt8_3.io.deq.bits connect remapVecValids[11], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[11] node _T_3626 = eq(UInt<3>(0h4), remapindex_11) when _T_3626 : connect remapVecData[11], Queue10_UInt8_4.io.deq.bits connect remapVecValids[11], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[11] node _T_3627 = eq(UInt<3>(0h5), remapindex_11) when _T_3627 : connect remapVecData[11], Queue10_UInt8_5.io.deq.bits connect remapVecValids[11], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[11] node _T_3628 = eq(UInt<3>(0h6), remapindex_11) when _T_3628 : connect remapVecData[11], Queue10_UInt8_6.io.deq.bits connect remapVecValids[11], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[11] node _T_3629 = eq(UInt<3>(0h7), remapindex_11) when _T_3629 : connect remapVecData[11], Queue10_UInt8_7.io.deq.bits connect remapVecValids[11], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[11] node _T_3630 = eq(UInt<4>(0h8), remapindex_11) when _T_3630 : connect remapVecData[11], Queue10_UInt8_8.io.deq.bits connect remapVecValids[11], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[11] node _T_3631 = eq(UInt<4>(0h9), remapindex_11) when _T_3631 : connect remapVecData[11], Queue10_UInt8_9.io.deq.bits connect remapVecValids[11], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[11] node _T_3632 = eq(UInt<4>(0ha), remapindex_11) when _T_3632 : connect remapVecData[11], Queue10_UInt8_10.io.deq.bits connect remapVecValids[11], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[11] node _T_3633 = eq(UInt<4>(0hb), remapindex_11) when _T_3633 : connect remapVecData[11], Queue10_UInt8_11.io.deq.bits connect remapVecValids[11], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[11] node _T_3634 = eq(UInt<4>(0hc), remapindex_11) when _T_3634 : connect remapVecData[11], Queue10_UInt8_12.io.deq.bits connect remapVecValids[11], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[11] node _T_3635 = eq(UInt<4>(0hd), remapindex_11) when _T_3635 : connect remapVecData[11], Queue10_UInt8_13.io.deq.bits connect remapVecValids[11], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[11] node _T_3636 = eq(UInt<4>(0he), remapindex_11) when _T_3636 : connect remapVecData[11], Queue10_UInt8_14.io.deq.bits connect remapVecValids[11], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[11] node _T_3637 = eq(UInt<4>(0hf), remapindex_11) when _T_3637 : connect remapVecData[11], Queue10_UInt8_15.io.deq.bits connect remapVecValids[11], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[11] node _T_3638 = eq(UInt<5>(0h10), remapindex_11) when _T_3638 : connect remapVecData[11], Queue10_UInt8_16.io.deq.bits connect remapVecValids[11], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[11] node _T_3639 = eq(UInt<5>(0h11), remapindex_11) when _T_3639 : connect remapVecData[11], Queue10_UInt8_17.io.deq.bits connect remapVecValids[11], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[11] node _T_3640 = eq(UInt<5>(0h12), remapindex_11) when _T_3640 : connect remapVecData[11], Queue10_UInt8_18.io.deq.bits connect remapVecValids[11], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[11] node _T_3641 = eq(UInt<5>(0h13), remapindex_11) when _T_3641 : connect remapVecData[11], Queue10_UInt8_19.io.deq.bits connect remapVecValids[11], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[11] node _T_3642 = eq(UInt<5>(0h14), remapindex_11) when _T_3642 : connect remapVecData[11], Queue10_UInt8_20.io.deq.bits connect remapVecValids[11], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[11] node _T_3643 = eq(UInt<5>(0h15), remapindex_11) when _T_3643 : connect remapVecData[11], Queue10_UInt8_21.io.deq.bits connect remapVecValids[11], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[11] node _T_3644 = eq(UInt<5>(0h16), remapindex_11) when _T_3644 : connect remapVecData[11], Queue10_UInt8_22.io.deq.bits connect remapVecValids[11], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[11] node _T_3645 = eq(UInt<5>(0h17), remapindex_11) when _T_3645 : connect remapVecData[11], Queue10_UInt8_23.io.deq.bits connect remapVecValids[11], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[11] node _T_3646 = eq(UInt<5>(0h18), remapindex_11) when _T_3646 : connect remapVecData[11], Queue10_UInt8_24.io.deq.bits connect remapVecValids[11], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[11] node _T_3647 = eq(UInt<5>(0h19), remapindex_11) when _T_3647 : connect remapVecData[11], Queue10_UInt8_25.io.deq.bits connect remapVecValids[11], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[11] node _T_3648 = eq(UInt<5>(0h1a), remapindex_11) when _T_3648 : connect remapVecData[11], Queue10_UInt8_26.io.deq.bits connect remapVecValids[11], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[11] node _T_3649 = eq(UInt<5>(0h1b), remapindex_11) when _T_3649 : connect remapVecData[11], Queue10_UInt8_27.io.deq.bits connect remapVecValids[11], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[11] node _T_3650 = eq(UInt<5>(0h1c), remapindex_11) when _T_3650 : connect remapVecData[11], Queue10_UInt8_28.io.deq.bits connect remapVecValids[11], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[11] node _T_3651 = eq(UInt<5>(0h1d), remapindex_11) when _T_3651 : connect remapVecData[11], Queue10_UInt8_29.io.deq.bits connect remapVecValids[11], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[11] node _T_3652 = eq(UInt<5>(0h1e), remapindex_11) when _T_3652 : connect remapVecData[11], Queue10_UInt8_30.io.deq.bits connect remapVecValids[11], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[11] node _T_3653 = eq(UInt<5>(0h1f), remapindex_11) when _T_3653 : connect remapVecData[11], Queue10_UInt8_31.io.deq.bits connect remapVecValids[11], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[11] node _remapindex_T_12 = add(UInt<4>(0hc), read_start_index) node remapindex_12 = rem(_remapindex_T_12, UInt<6>(0h20)) node _T_3654 = eq(UInt<1>(0h0), remapindex_12) when _T_3654 : connect remapVecData[12], Queue10_UInt8.io.deq.bits connect remapVecValids[12], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[12] node _T_3655 = eq(UInt<1>(0h1), remapindex_12) when _T_3655 : connect remapVecData[12], Queue10_UInt8_1.io.deq.bits connect remapVecValids[12], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[12] node _T_3656 = eq(UInt<2>(0h2), remapindex_12) when _T_3656 : connect remapVecData[12], Queue10_UInt8_2.io.deq.bits connect remapVecValids[12], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[12] node _T_3657 = eq(UInt<2>(0h3), remapindex_12) when _T_3657 : connect remapVecData[12], Queue10_UInt8_3.io.deq.bits connect remapVecValids[12], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[12] node _T_3658 = eq(UInt<3>(0h4), remapindex_12) when _T_3658 : connect remapVecData[12], Queue10_UInt8_4.io.deq.bits connect remapVecValids[12], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[12] node _T_3659 = eq(UInt<3>(0h5), remapindex_12) when _T_3659 : connect remapVecData[12], Queue10_UInt8_5.io.deq.bits connect remapVecValids[12], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[12] node _T_3660 = eq(UInt<3>(0h6), remapindex_12) when _T_3660 : connect remapVecData[12], Queue10_UInt8_6.io.deq.bits connect remapVecValids[12], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[12] node _T_3661 = eq(UInt<3>(0h7), remapindex_12) when _T_3661 : connect remapVecData[12], Queue10_UInt8_7.io.deq.bits connect remapVecValids[12], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[12] node _T_3662 = eq(UInt<4>(0h8), remapindex_12) when _T_3662 : connect remapVecData[12], Queue10_UInt8_8.io.deq.bits connect remapVecValids[12], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[12] node _T_3663 = eq(UInt<4>(0h9), remapindex_12) when _T_3663 : connect remapVecData[12], Queue10_UInt8_9.io.deq.bits connect remapVecValids[12], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[12] node _T_3664 = eq(UInt<4>(0ha), remapindex_12) when _T_3664 : connect remapVecData[12], Queue10_UInt8_10.io.deq.bits connect remapVecValids[12], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[12] node _T_3665 = eq(UInt<4>(0hb), remapindex_12) when _T_3665 : connect remapVecData[12], Queue10_UInt8_11.io.deq.bits connect remapVecValids[12], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[12] node _T_3666 = eq(UInt<4>(0hc), remapindex_12) when _T_3666 : connect remapVecData[12], Queue10_UInt8_12.io.deq.bits connect remapVecValids[12], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[12] node _T_3667 = eq(UInt<4>(0hd), remapindex_12) when _T_3667 : connect remapVecData[12], Queue10_UInt8_13.io.deq.bits connect remapVecValids[12], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[12] node _T_3668 = eq(UInt<4>(0he), remapindex_12) when _T_3668 : connect remapVecData[12], Queue10_UInt8_14.io.deq.bits connect remapVecValids[12], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[12] node _T_3669 = eq(UInt<4>(0hf), remapindex_12) when _T_3669 : connect remapVecData[12], Queue10_UInt8_15.io.deq.bits connect remapVecValids[12], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[12] node _T_3670 = eq(UInt<5>(0h10), remapindex_12) when _T_3670 : connect remapVecData[12], Queue10_UInt8_16.io.deq.bits connect remapVecValids[12], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[12] node _T_3671 = eq(UInt<5>(0h11), remapindex_12) when _T_3671 : connect remapVecData[12], Queue10_UInt8_17.io.deq.bits connect remapVecValids[12], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[12] node _T_3672 = eq(UInt<5>(0h12), remapindex_12) when _T_3672 : connect remapVecData[12], Queue10_UInt8_18.io.deq.bits connect remapVecValids[12], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[12] node _T_3673 = eq(UInt<5>(0h13), remapindex_12) when _T_3673 : connect remapVecData[12], Queue10_UInt8_19.io.deq.bits connect remapVecValids[12], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[12] node _T_3674 = eq(UInt<5>(0h14), remapindex_12) when _T_3674 : connect remapVecData[12], Queue10_UInt8_20.io.deq.bits connect remapVecValids[12], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[12] node _T_3675 = eq(UInt<5>(0h15), remapindex_12) when _T_3675 : connect remapVecData[12], Queue10_UInt8_21.io.deq.bits connect remapVecValids[12], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[12] node _T_3676 = eq(UInt<5>(0h16), remapindex_12) when _T_3676 : connect remapVecData[12], Queue10_UInt8_22.io.deq.bits connect remapVecValids[12], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[12] node _T_3677 = eq(UInt<5>(0h17), remapindex_12) when _T_3677 : connect remapVecData[12], Queue10_UInt8_23.io.deq.bits connect remapVecValids[12], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[12] node _T_3678 = eq(UInt<5>(0h18), remapindex_12) when _T_3678 : connect remapVecData[12], Queue10_UInt8_24.io.deq.bits connect remapVecValids[12], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[12] node _T_3679 = eq(UInt<5>(0h19), remapindex_12) when _T_3679 : connect remapVecData[12], Queue10_UInt8_25.io.deq.bits connect remapVecValids[12], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[12] node _T_3680 = eq(UInt<5>(0h1a), remapindex_12) when _T_3680 : connect remapVecData[12], Queue10_UInt8_26.io.deq.bits connect remapVecValids[12], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[12] node _T_3681 = eq(UInt<5>(0h1b), remapindex_12) when _T_3681 : connect remapVecData[12], Queue10_UInt8_27.io.deq.bits connect remapVecValids[12], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[12] node _T_3682 = eq(UInt<5>(0h1c), remapindex_12) when _T_3682 : connect remapVecData[12], Queue10_UInt8_28.io.deq.bits connect remapVecValids[12], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[12] node _T_3683 = eq(UInt<5>(0h1d), remapindex_12) when _T_3683 : connect remapVecData[12], Queue10_UInt8_29.io.deq.bits connect remapVecValids[12], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[12] node _T_3684 = eq(UInt<5>(0h1e), remapindex_12) when _T_3684 : connect remapVecData[12], Queue10_UInt8_30.io.deq.bits connect remapVecValids[12], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[12] node _T_3685 = eq(UInt<5>(0h1f), remapindex_12) when _T_3685 : connect remapVecData[12], Queue10_UInt8_31.io.deq.bits connect remapVecValids[12], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[12] node _remapindex_T_13 = add(UInt<4>(0hd), read_start_index) node remapindex_13 = rem(_remapindex_T_13, UInt<6>(0h20)) node _T_3686 = eq(UInt<1>(0h0), remapindex_13) when _T_3686 : connect remapVecData[13], Queue10_UInt8.io.deq.bits connect remapVecValids[13], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[13] node _T_3687 = eq(UInt<1>(0h1), remapindex_13) when _T_3687 : connect remapVecData[13], Queue10_UInt8_1.io.deq.bits connect remapVecValids[13], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[13] node _T_3688 = eq(UInt<2>(0h2), remapindex_13) when _T_3688 : connect remapVecData[13], Queue10_UInt8_2.io.deq.bits connect remapVecValids[13], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[13] node _T_3689 = eq(UInt<2>(0h3), remapindex_13) when _T_3689 : connect remapVecData[13], Queue10_UInt8_3.io.deq.bits connect remapVecValids[13], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[13] node _T_3690 = eq(UInt<3>(0h4), remapindex_13) when _T_3690 : connect remapVecData[13], Queue10_UInt8_4.io.deq.bits connect remapVecValids[13], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[13] node _T_3691 = eq(UInt<3>(0h5), remapindex_13) when _T_3691 : connect remapVecData[13], Queue10_UInt8_5.io.deq.bits connect remapVecValids[13], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[13] node _T_3692 = eq(UInt<3>(0h6), remapindex_13) when _T_3692 : connect remapVecData[13], Queue10_UInt8_6.io.deq.bits connect remapVecValids[13], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[13] node _T_3693 = eq(UInt<3>(0h7), remapindex_13) when _T_3693 : connect remapVecData[13], Queue10_UInt8_7.io.deq.bits connect remapVecValids[13], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[13] node _T_3694 = eq(UInt<4>(0h8), remapindex_13) when _T_3694 : connect remapVecData[13], Queue10_UInt8_8.io.deq.bits connect remapVecValids[13], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[13] node _T_3695 = eq(UInt<4>(0h9), remapindex_13) when _T_3695 : connect remapVecData[13], Queue10_UInt8_9.io.deq.bits connect remapVecValids[13], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[13] node _T_3696 = eq(UInt<4>(0ha), remapindex_13) when _T_3696 : connect remapVecData[13], Queue10_UInt8_10.io.deq.bits connect remapVecValids[13], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[13] node _T_3697 = eq(UInt<4>(0hb), remapindex_13) when _T_3697 : connect remapVecData[13], Queue10_UInt8_11.io.deq.bits connect remapVecValids[13], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[13] node _T_3698 = eq(UInt<4>(0hc), remapindex_13) when _T_3698 : connect remapVecData[13], Queue10_UInt8_12.io.deq.bits connect remapVecValids[13], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[13] node _T_3699 = eq(UInt<4>(0hd), remapindex_13) when _T_3699 : connect remapVecData[13], Queue10_UInt8_13.io.deq.bits connect remapVecValids[13], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[13] node _T_3700 = eq(UInt<4>(0he), remapindex_13) when _T_3700 : connect remapVecData[13], Queue10_UInt8_14.io.deq.bits connect remapVecValids[13], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[13] node _T_3701 = eq(UInt<4>(0hf), remapindex_13) when _T_3701 : connect remapVecData[13], Queue10_UInt8_15.io.deq.bits connect remapVecValids[13], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[13] node _T_3702 = eq(UInt<5>(0h10), remapindex_13) when _T_3702 : connect remapVecData[13], Queue10_UInt8_16.io.deq.bits connect remapVecValids[13], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[13] node _T_3703 = eq(UInt<5>(0h11), remapindex_13) when _T_3703 : connect remapVecData[13], Queue10_UInt8_17.io.deq.bits connect remapVecValids[13], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[13] node _T_3704 = eq(UInt<5>(0h12), remapindex_13) when _T_3704 : connect remapVecData[13], Queue10_UInt8_18.io.deq.bits connect remapVecValids[13], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[13] node _T_3705 = eq(UInt<5>(0h13), remapindex_13) when _T_3705 : connect remapVecData[13], Queue10_UInt8_19.io.deq.bits connect remapVecValids[13], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[13] node _T_3706 = eq(UInt<5>(0h14), remapindex_13) when _T_3706 : connect remapVecData[13], Queue10_UInt8_20.io.deq.bits connect remapVecValids[13], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[13] node _T_3707 = eq(UInt<5>(0h15), remapindex_13) when _T_3707 : connect remapVecData[13], Queue10_UInt8_21.io.deq.bits connect remapVecValids[13], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[13] node _T_3708 = eq(UInt<5>(0h16), remapindex_13) when _T_3708 : connect remapVecData[13], Queue10_UInt8_22.io.deq.bits connect remapVecValids[13], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[13] node _T_3709 = eq(UInt<5>(0h17), remapindex_13) when _T_3709 : connect remapVecData[13], Queue10_UInt8_23.io.deq.bits connect remapVecValids[13], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[13] node _T_3710 = eq(UInt<5>(0h18), remapindex_13) when _T_3710 : connect remapVecData[13], Queue10_UInt8_24.io.deq.bits connect remapVecValids[13], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[13] node _T_3711 = eq(UInt<5>(0h19), remapindex_13) when _T_3711 : connect remapVecData[13], Queue10_UInt8_25.io.deq.bits connect remapVecValids[13], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[13] node _T_3712 = eq(UInt<5>(0h1a), remapindex_13) when _T_3712 : connect remapVecData[13], Queue10_UInt8_26.io.deq.bits connect remapVecValids[13], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[13] node _T_3713 = eq(UInt<5>(0h1b), remapindex_13) when _T_3713 : connect remapVecData[13], Queue10_UInt8_27.io.deq.bits connect remapVecValids[13], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[13] node _T_3714 = eq(UInt<5>(0h1c), remapindex_13) when _T_3714 : connect remapVecData[13], Queue10_UInt8_28.io.deq.bits connect remapVecValids[13], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[13] node _T_3715 = eq(UInt<5>(0h1d), remapindex_13) when _T_3715 : connect remapVecData[13], Queue10_UInt8_29.io.deq.bits connect remapVecValids[13], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[13] node _T_3716 = eq(UInt<5>(0h1e), remapindex_13) when _T_3716 : connect remapVecData[13], Queue10_UInt8_30.io.deq.bits connect remapVecValids[13], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[13] node _T_3717 = eq(UInt<5>(0h1f), remapindex_13) when _T_3717 : connect remapVecData[13], Queue10_UInt8_31.io.deq.bits connect remapVecValids[13], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[13] node _remapindex_T_14 = add(UInt<4>(0he), read_start_index) node remapindex_14 = rem(_remapindex_T_14, UInt<6>(0h20)) node _T_3718 = eq(UInt<1>(0h0), remapindex_14) when _T_3718 : connect remapVecData[14], Queue10_UInt8.io.deq.bits connect remapVecValids[14], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[14] node _T_3719 = eq(UInt<1>(0h1), remapindex_14) when _T_3719 : connect remapVecData[14], Queue10_UInt8_1.io.deq.bits connect remapVecValids[14], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[14] node _T_3720 = eq(UInt<2>(0h2), remapindex_14) when _T_3720 : connect remapVecData[14], Queue10_UInt8_2.io.deq.bits connect remapVecValids[14], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[14] node _T_3721 = eq(UInt<2>(0h3), remapindex_14) when _T_3721 : connect remapVecData[14], Queue10_UInt8_3.io.deq.bits connect remapVecValids[14], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[14] node _T_3722 = eq(UInt<3>(0h4), remapindex_14) when _T_3722 : connect remapVecData[14], Queue10_UInt8_4.io.deq.bits connect remapVecValids[14], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[14] node _T_3723 = eq(UInt<3>(0h5), remapindex_14) when _T_3723 : connect remapVecData[14], Queue10_UInt8_5.io.deq.bits connect remapVecValids[14], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[14] node _T_3724 = eq(UInt<3>(0h6), remapindex_14) when _T_3724 : connect remapVecData[14], Queue10_UInt8_6.io.deq.bits connect remapVecValids[14], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[14] node _T_3725 = eq(UInt<3>(0h7), remapindex_14) when _T_3725 : connect remapVecData[14], Queue10_UInt8_7.io.deq.bits connect remapVecValids[14], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[14] node _T_3726 = eq(UInt<4>(0h8), remapindex_14) when _T_3726 : connect remapVecData[14], Queue10_UInt8_8.io.deq.bits connect remapVecValids[14], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[14] node _T_3727 = eq(UInt<4>(0h9), remapindex_14) when _T_3727 : connect remapVecData[14], Queue10_UInt8_9.io.deq.bits connect remapVecValids[14], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[14] node _T_3728 = eq(UInt<4>(0ha), remapindex_14) when _T_3728 : connect remapVecData[14], Queue10_UInt8_10.io.deq.bits connect remapVecValids[14], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[14] node _T_3729 = eq(UInt<4>(0hb), remapindex_14) when _T_3729 : connect remapVecData[14], Queue10_UInt8_11.io.deq.bits connect remapVecValids[14], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[14] node _T_3730 = eq(UInt<4>(0hc), remapindex_14) when _T_3730 : connect remapVecData[14], Queue10_UInt8_12.io.deq.bits connect remapVecValids[14], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[14] node _T_3731 = eq(UInt<4>(0hd), remapindex_14) when _T_3731 : connect remapVecData[14], Queue10_UInt8_13.io.deq.bits connect remapVecValids[14], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[14] node _T_3732 = eq(UInt<4>(0he), remapindex_14) when _T_3732 : connect remapVecData[14], Queue10_UInt8_14.io.deq.bits connect remapVecValids[14], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[14] node _T_3733 = eq(UInt<4>(0hf), remapindex_14) when _T_3733 : connect remapVecData[14], Queue10_UInt8_15.io.deq.bits connect remapVecValids[14], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[14] node _T_3734 = eq(UInt<5>(0h10), remapindex_14) when _T_3734 : connect remapVecData[14], Queue10_UInt8_16.io.deq.bits connect remapVecValids[14], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[14] node _T_3735 = eq(UInt<5>(0h11), remapindex_14) when _T_3735 : connect remapVecData[14], Queue10_UInt8_17.io.deq.bits connect remapVecValids[14], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[14] node _T_3736 = eq(UInt<5>(0h12), remapindex_14) when _T_3736 : connect remapVecData[14], Queue10_UInt8_18.io.deq.bits connect remapVecValids[14], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[14] node _T_3737 = eq(UInt<5>(0h13), remapindex_14) when _T_3737 : connect remapVecData[14], Queue10_UInt8_19.io.deq.bits connect remapVecValids[14], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[14] node _T_3738 = eq(UInt<5>(0h14), remapindex_14) when _T_3738 : connect remapVecData[14], Queue10_UInt8_20.io.deq.bits connect remapVecValids[14], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[14] node _T_3739 = eq(UInt<5>(0h15), remapindex_14) when _T_3739 : connect remapVecData[14], Queue10_UInt8_21.io.deq.bits connect remapVecValids[14], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[14] node _T_3740 = eq(UInt<5>(0h16), remapindex_14) when _T_3740 : connect remapVecData[14], Queue10_UInt8_22.io.deq.bits connect remapVecValids[14], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[14] node _T_3741 = eq(UInt<5>(0h17), remapindex_14) when _T_3741 : connect remapVecData[14], Queue10_UInt8_23.io.deq.bits connect remapVecValids[14], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[14] node _T_3742 = eq(UInt<5>(0h18), remapindex_14) when _T_3742 : connect remapVecData[14], Queue10_UInt8_24.io.deq.bits connect remapVecValids[14], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[14] node _T_3743 = eq(UInt<5>(0h19), remapindex_14) when _T_3743 : connect remapVecData[14], Queue10_UInt8_25.io.deq.bits connect remapVecValids[14], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[14] node _T_3744 = eq(UInt<5>(0h1a), remapindex_14) when _T_3744 : connect remapVecData[14], Queue10_UInt8_26.io.deq.bits connect remapVecValids[14], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[14] node _T_3745 = eq(UInt<5>(0h1b), remapindex_14) when _T_3745 : connect remapVecData[14], Queue10_UInt8_27.io.deq.bits connect remapVecValids[14], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[14] node _T_3746 = eq(UInt<5>(0h1c), remapindex_14) when _T_3746 : connect remapVecData[14], Queue10_UInt8_28.io.deq.bits connect remapVecValids[14], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[14] node _T_3747 = eq(UInt<5>(0h1d), remapindex_14) when _T_3747 : connect remapVecData[14], Queue10_UInt8_29.io.deq.bits connect remapVecValids[14], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[14] node _T_3748 = eq(UInt<5>(0h1e), remapindex_14) when _T_3748 : connect remapVecData[14], Queue10_UInt8_30.io.deq.bits connect remapVecValids[14], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[14] node _T_3749 = eq(UInt<5>(0h1f), remapindex_14) when _T_3749 : connect remapVecData[14], Queue10_UInt8_31.io.deq.bits connect remapVecValids[14], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[14] node _remapindex_T_15 = add(UInt<4>(0hf), read_start_index) node remapindex_15 = rem(_remapindex_T_15, UInt<6>(0h20)) node _T_3750 = eq(UInt<1>(0h0), remapindex_15) when _T_3750 : connect remapVecData[15], Queue10_UInt8.io.deq.bits connect remapVecValids[15], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[15] node _T_3751 = eq(UInt<1>(0h1), remapindex_15) when _T_3751 : connect remapVecData[15], Queue10_UInt8_1.io.deq.bits connect remapVecValids[15], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[15] node _T_3752 = eq(UInt<2>(0h2), remapindex_15) when _T_3752 : connect remapVecData[15], Queue10_UInt8_2.io.deq.bits connect remapVecValids[15], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[15] node _T_3753 = eq(UInt<2>(0h3), remapindex_15) when _T_3753 : connect remapVecData[15], Queue10_UInt8_3.io.deq.bits connect remapVecValids[15], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[15] node _T_3754 = eq(UInt<3>(0h4), remapindex_15) when _T_3754 : connect remapVecData[15], Queue10_UInt8_4.io.deq.bits connect remapVecValids[15], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[15] node _T_3755 = eq(UInt<3>(0h5), remapindex_15) when _T_3755 : connect remapVecData[15], Queue10_UInt8_5.io.deq.bits connect remapVecValids[15], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[15] node _T_3756 = eq(UInt<3>(0h6), remapindex_15) when _T_3756 : connect remapVecData[15], Queue10_UInt8_6.io.deq.bits connect remapVecValids[15], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[15] node _T_3757 = eq(UInt<3>(0h7), remapindex_15) when _T_3757 : connect remapVecData[15], Queue10_UInt8_7.io.deq.bits connect remapVecValids[15], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[15] node _T_3758 = eq(UInt<4>(0h8), remapindex_15) when _T_3758 : connect remapVecData[15], Queue10_UInt8_8.io.deq.bits connect remapVecValids[15], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[15] node _T_3759 = eq(UInt<4>(0h9), remapindex_15) when _T_3759 : connect remapVecData[15], Queue10_UInt8_9.io.deq.bits connect remapVecValids[15], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[15] node _T_3760 = eq(UInt<4>(0ha), remapindex_15) when _T_3760 : connect remapVecData[15], Queue10_UInt8_10.io.deq.bits connect remapVecValids[15], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[15] node _T_3761 = eq(UInt<4>(0hb), remapindex_15) when _T_3761 : connect remapVecData[15], Queue10_UInt8_11.io.deq.bits connect remapVecValids[15], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[15] node _T_3762 = eq(UInt<4>(0hc), remapindex_15) when _T_3762 : connect remapVecData[15], Queue10_UInt8_12.io.deq.bits connect remapVecValids[15], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[15] node _T_3763 = eq(UInt<4>(0hd), remapindex_15) when _T_3763 : connect remapVecData[15], Queue10_UInt8_13.io.deq.bits connect remapVecValids[15], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[15] node _T_3764 = eq(UInt<4>(0he), remapindex_15) when _T_3764 : connect remapVecData[15], Queue10_UInt8_14.io.deq.bits connect remapVecValids[15], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[15] node _T_3765 = eq(UInt<4>(0hf), remapindex_15) when _T_3765 : connect remapVecData[15], Queue10_UInt8_15.io.deq.bits connect remapVecValids[15], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[15] node _T_3766 = eq(UInt<5>(0h10), remapindex_15) when _T_3766 : connect remapVecData[15], Queue10_UInt8_16.io.deq.bits connect remapVecValids[15], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[15] node _T_3767 = eq(UInt<5>(0h11), remapindex_15) when _T_3767 : connect remapVecData[15], Queue10_UInt8_17.io.deq.bits connect remapVecValids[15], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[15] node _T_3768 = eq(UInt<5>(0h12), remapindex_15) when _T_3768 : connect remapVecData[15], Queue10_UInt8_18.io.deq.bits connect remapVecValids[15], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[15] node _T_3769 = eq(UInt<5>(0h13), remapindex_15) when _T_3769 : connect remapVecData[15], Queue10_UInt8_19.io.deq.bits connect remapVecValids[15], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[15] node _T_3770 = eq(UInt<5>(0h14), remapindex_15) when _T_3770 : connect remapVecData[15], Queue10_UInt8_20.io.deq.bits connect remapVecValids[15], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[15] node _T_3771 = eq(UInt<5>(0h15), remapindex_15) when _T_3771 : connect remapVecData[15], Queue10_UInt8_21.io.deq.bits connect remapVecValids[15], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[15] node _T_3772 = eq(UInt<5>(0h16), remapindex_15) when _T_3772 : connect remapVecData[15], Queue10_UInt8_22.io.deq.bits connect remapVecValids[15], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[15] node _T_3773 = eq(UInt<5>(0h17), remapindex_15) when _T_3773 : connect remapVecData[15], Queue10_UInt8_23.io.deq.bits connect remapVecValids[15], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[15] node _T_3774 = eq(UInt<5>(0h18), remapindex_15) when _T_3774 : connect remapVecData[15], Queue10_UInt8_24.io.deq.bits connect remapVecValids[15], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[15] node _T_3775 = eq(UInt<5>(0h19), remapindex_15) when _T_3775 : connect remapVecData[15], Queue10_UInt8_25.io.deq.bits connect remapVecValids[15], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[15] node _T_3776 = eq(UInt<5>(0h1a), remapindex_15) when _T_3776 : connect remapVecData[15], Queue10_UInt8_26.io.deq.bits connect remapVecValids[15], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[15] node _T_3777 = eq(UInt<5>(0h1b), remapindex_15) when _T_3777 : connect remapVecData[15], Queue10_UInt8_27.io.deq.bits connect remapVecValids[15], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[15] node _T_3778 = eq(UInt<5>(0h1c), remapindex_15) when _T_3778 : connect remapVecData[15], Queue10_UInt8_28.io.deq.bits connect remapVecValids[15], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[15] node _T_3779 = eq(UInt<5>(0h1d), remapindex_15) when _T_3779 : connect remapVecData[15], Queue10_UInt8_29.io.deq.bits connect remapVecValids[15], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[15] node _T_3780 = eq(UInt<5>(0h1e), remapindex_15) when _T_3780 : connect remapVecData[15], Queue10_UInt8_30.io.deq.bits connect remapVecValids[15], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[15] node _T_3781 = eq(UInt<5>(0h1f), remapindex_15) when _T_3781 : connect remapVecData[15], Queue10_UInt8_31.io.deq.bits connect remapVecValids[15], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[15] node _remapindex_T_16 = add(UInt<5>(0h10), read_start_index) node remapindex_16 = rem(_remapindex_T_16, UInt<6>(0h20)) node _T_3782 = eq(UInt<1>(0h0), remapindex_16) when _T_3782 : connect remapVecData[16], Queue10_UInt8.io.deq.bits connect remapVecValids[16], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[16] node _T_3783 = eq(UInt<1>(0h1), remapindex_16) when _T_3783 : connect remapVecData[16], Queue10_UInt8_1.io.deq.bits connect remapVecValids[16], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[16] node _T_3784 = eq(UInt<2>(0h2), remapindex_16) when _T_3784 : connect remapVecData[16], Queue10_UInt8_2.io.deq.bits connect remapVecValids[16], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[16] node _T_3785 = eq(UInt<2>(0h3), remapindex_16) when _T_3785 : connect remapVecData[16], Queue10_UInt8_3.io.deq.bits connect remapVecValids[16], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[16] node _T_3786 = eq(UInt<3>(0h4), remapindex_16) when _T_3786 : connect remapVecData[16], Queue10_UInt8_4.io.deq.bits connect remapVecValids[16], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[16] node _T_3787 = eq(UInt<3>(0h5), remapindex_16) when _T_3787 : connect remapVecData[16], Queue10_UInt8_5.io.deq.bits connect remapVecValids[16], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[16] node _T_3788 = eq(UInt<3>(0h6), remapindex_16) when _T_3788 : connect remapVecData[16], Queue10_UInt8_6.io.deq.bits connect remapVecValids[16], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[16] node _T_3789 = eq(UInt<3>(0h7), remapindex_16) when _T_3789 : connect remapVecData[16], Queue10_UInt8_7.io.deq.bits connect remapVecValids[16], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[16] node _T_3790 = eq(UInt<4>(0h8), remapindex_16) when _T_3790 : connect remapVecData[16], Queue10_UInt8_8.io.deq.bits connect remapVecValids[16], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[16] node _T_3791 = eq(UInt<4>(0h9), remapindex_16) when _T_3791 : connect remapVecData[16], Queue10_UInt8_9.io.deq.bits connect remapVecValids[16], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[16] node _T_3792 = eq(UInt<4>(0ha), remapindex_16) when _T_3792 : connect remapVecData[16], Queue10_UInt8_10.io.deq.bits connect remapVecValids[16], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[16] node _T_3793 = eq(UInt<4>(0hb), remapindex_16) when _T_3793 : connect remapVecData[16], Queue10_UInt8_11.io.deq.bits connect remapVecValids[16], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[16] node _T_3794 = eq(UInt<4>(0hc), remapindex_16) when _T_3794 : connect remapVecData[16], Queue10_UInt8_12.io.deq.bits connect remapVecValids[16], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[16] node _T_3795 = eq(UInt<4>(0hd), remapindex_16) when _T_3795 : connect remapVecData[16], Queue10_UInt8_13.io.deq.bits connect remapVecValids[16], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[16] node _T_3796 = eq(UInt<4>(0he), remapindex_16) when _T_3796 : connect remapVecData[16], Queue10_UInt8_14.io.deq.bits connect remapVecValids[16], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[16] node _T_3797 = eq(UInt<4>(0hf), remapindex_16) when _T_3797 : connect remapVecData[16], Queue10_UInt8_15.io.deq.bits connect remapVecValids[16], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[16] node _T_3798 = eq(UInt<5>(0h10), remapindex_16) when _T_3798 : connect remapVecData[16], Queue10_UInt8_16.io.deq.bits connect remapVecValids[16], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[16] node _T_3799 = eq(UInt<5>(0h11), remapindex_16) when _T_3799 : connect remapVecData[16], Queue10_UInt8_17.io.deq.bits connect remapVecValids[16], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[16] node _T_3800 = eq(UInt<5>(0h12), remapindex_16) when _T_3800 : connect remapVecData[16], Queue10_UInt8_18.io.deq.bits connect remapVecValids[16], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[16] node _T_3801 = eq(UInt<5>(0h13), remapindex_16) when _T_3801 : connect remapVecData[16], Queue10_UInt8_19.io.deq.bits connect remapVecValids[16], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[16] node _T_3802 = eq(UInt<5>(0h14), remapindex_16) when _T_3802 : connect remapVecData[16], Queue10_UInt8_20.io.deq.bits connect remapVecValids[16], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[16] node _T_3803 = eq(UInt<5>(0h15), remapindex_16) when _T_3803 : connect remapVecData[16], Queue10_UInt8_21.io.deq.bits connect remapVecValids[16], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[16] node _T_3804 = eq(UInt<5>(0h16), remapindex_16) when _T_3804 : connect remapVecData[16], Queue10_UInt8_22.io.deq.bits connect remapVecValids[16], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[16] node _T_3805 = eq(UInt<5>(0h17), remapindex_16) when _T_3805 : connect remapVecData[16], Queue10_UInt8_23.io.deq.bits connect remapVecValids[16], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[16] node _T_3806 = eq(UInt<5>(0h18), remapindex_16) when _T_3806 : connect remapVecData[16], Queue10_UInt8_24.io.deq.bits connect remapVecValids[16], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[16] node _T_3807 = eq(UInt<5>(0h19), remapindex_16) when _T_3807 : connect remapVecData[16], Queue10_UInt8_25.io.deq.bits connect remapVecValids[16], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[16] node _T_3808 = eq(UInt<5>(0h1a), remapindex_16) when _T_3808 : connect remapVecData[16], Queue10_UInt8_26.io.deq.bits connect remapVecValids[16], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[16] node _T_3809 = eq(UInt<5>(0h1b), remapindex_16) when _T_3809 : connect remapVecData[16], Queue10_UInt8_27.io.deq.bits connect remapVecValids[16], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[16] node _T_3810 = eq(UInt<5>(0h1c), remapindex_16) when _T_3810 : connect remapVecData[16], Queue10_UInt8_28.io.deq.bits connect remapVecValids[16], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[16] node _T_3811 = eq(UInt<5>(0h1d), remapindex_16) when _T_3811 : connect remapVecData[16], Queue10_UInt8_29.io.deq.bits connect remapVecValids[16], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[16] node _T_3812 = eq(UInt<5>(0h1e), remapindex_16) when _T_3812 : connect remapVecData[16], Queue10_UInt8_30.io.deq.bits connect remapVecValids[16], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[16] node _T_3813 = eq(UInt<5>(0h1f), remapindex_16) when _T_3813 : connect remapVecData[16], Queue10_UInt8_31.io.deq.bits connect remapVecValids[16], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[16] node _remapindex_T_17 = add(UInt<5>(0h11), read_start_index) node remapindex_17 = rem(_remapindex_T_17, UInt<6>(0h20)) node _T_3814 = eq(UInt<1>(0h0), remapindex_17) when _T_3814 : connect remapVecData[17], Queue10_UInt8.io.deq.bits connect remapVecValids[17], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[17] node _T_3815 = eq(UInt<1>(0h1), remapindex_17) when _T_3815 : connect remapVecData[17], Queue10_UInt8_1.io.deq.bits connect remapVecValids[17], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[17] node _T_3816 = eq(UInt<2>(0h2), remapindex_17) when _T_3816 : connect remapVecData[17], Queue10_UInt8_2.io.deq.bits connect remapVecValids[17], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[17] node _T_3817 = eq(UInt<2>(0h3), remapindex_17) when _T_3817 : connect remapVecData[17], Queue10_UInt8_3.io.deq.bits connect remapVecValids[17], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[17] node _T_3818 = eq(UInt<3>(0h4), remapindex_17) when _T_3818 : connect remapVecData[17], Queue10_UInt8_4.io.deq.bits connect remapVecValids[17], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[17] node _T_3819 = eq(UInt<3>(0h5), remapindex_17) when _T_3819 : connect remapVecData[17], Queue10_UInt8_5.io.deq.bits connect remapVecValids[17], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[17] node _T_3820 = eq(UInt<3>(0h6), remapindex_17) when _T_3820 : connect remapVecData[17], Queue10_UInt8_6.io.deq.bits connect remapVecValids[17], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[17] node _T_3821 = eq(UInt<3>(0h7), remapindex_17) when _T_3821 : connect remapVecData[17], Queue10_UInt8_7.io.deq.bits connect remapVecValids[17], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[17] node _T_3822 = eq(UInt<4>(0h8), remapindex_17) when _T_3822 : connect remapVecData[17], Queue10_UInt8_8.io.deq.bits connect remapVecValids[17], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[17] node _T_3823 = eq(UInt<4>(0h9), remapindex_17) when _T_3823 : connect remapVecData[17], Queue10_UInt8_9.io.deq.bits connect remapVecValids[17], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[17] node _T_3824 = eq(UInt<4>(0ha), remapindex_17) when _T_3824 : connect remapVecData[17], Queue10_UInt8_10.io.deq.bits connect remapVecValids[17], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[17] node _T_3825 = eq(UInt<4>(0hb), remapindex_17) when _T_3825 : connect remapVecData[17], Queue10_UInt8_11.io.deq.bits connect remapVecValids[17], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[17] node _T_3826 = eq(UInt<4>(0hc), remapindex_17) when _T_3826 : connect remapVecData[17], Queue10_UInt8_12.io.deq.bits connect remapVecValids[17], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[17] node _T_3827 = eq(UInt<4>(0hd), remapindex_17) when _T_3827 : connect remapVecData[17], Queue10_UInt8_13.io.deq.bits connect remapVecValids[17], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[17] node _T_3828 = eq(UInt<4>(0he), remapindex_17) when _T_3828 : connect remapVecData[17], Queue10_UInt8_14.io.deq.bits connect remapVecValids[17], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[17] node _T_3829 = eq(UInt<4>(0hf), remapindex_17) when _T_3829 : connect remapVecData[17], Queue10_UInt8_15.io.deq.bits connect remapVecValids[17], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[17] node _T_3830 = eq(UInt<5>(0h10), remapindex_17) when _T_3830 : connect remapVecData[17], Queue10_UInt8_16.io.deq.bits connect remapVecValids[17], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[17] node _T_3831 = eq(UInt<5>(0h11), remapindex_17) when _T_3831 : connect remapVecData[17], Queue10_UInt8_17.io.deq.bits connect remapVecValids[17], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[17] node _T_3832 = eq(UInt<5>(0h12), remapindex_17) when _T_3832 : connect remapVecData[17], Queue10_UInt8_18.io.deq.bits connect remapVecValids[17], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[17] node _T_3833 = eq(UInt<5>(0h13), remapindex_17) when _T_3833 : connect remapVecData[17], Queue10_UInt8_19.io.deq.bits connect remapVecValids[17], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[17] node _T_3834 = eq(UInt<5>(0h14), remapindex_17) when _T_3834 : connect remapVecData[17], Queue10_UInt8_20.io.deq.bits connect remapVecValids[17], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[17] node _T_3835 = eq(UInt<5>(0h15), remapindex_17) when _T_3835 : connect remapVecData[17], Queue10_UInt8_21.io.deq.bits connect remapVecValids[17], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[17] node _T_3836 = eq(UInt<5>(0h16), remapindex_17) when _T_3836 : connect remapVecData[17], Queue10_UInt8_22.io.deq.bits connect remapVecValids[17], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[17] node _T_3837 = eq(UInt<5>(0h17), remapindex_17) when _T_3837 : connect remapVecData[17], Queue10_UInt8_23.io.deq.bits connect remapVecValids[17], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[17] node _T_3838 = eq(UInt<5>(0h18), remapindex_17) when _T_3838 : connect remapVecData[17], Queue10_UInt8_24.io.deq.bits connect remapVecValids[17], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[17] node _T_3839 = eq(UInt<5>(0h19), remapindex_17) when _T_3839 : connect remapVecData[17], Queue10_UInt8_25.io.deq.bits connect remapVecValids[17], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[17] node _T_3840 = eq(UInt<5>(0h1a), remapindex_17) when _T_3840 : connect remapVecData[17], Queue10_UInt8_26.io.deq.bits connect remapVecValids[17], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[17] node _T_3841 = eq(UInt<5>(0h1b), remapindex_17) when _T_3841 : connect remapVecData[17], Queue10_UInt8_27.io.deq.bits connect remapVecValids[17], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[17] node _T_3842 = eq(UInt<5>(0h1c), remapindex_17) when _T_3842 : connect remapVecData[17], Queue10_UInt8_28.io.deq.bits connect remapVecValids[17], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[17] node _T_3843 = eq(UInt<5>(0h1d), remapindex_17) when _T_3843 : connect remapVecData[17], Queue10_UInt8_29.io.deq.bits connect remapVecValids[17], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[17] node _T_3844 = eq(UInt<5>(0h1e), remapindex_17) when _T_3844 : connect remapVecData[17], Queue10_UInt8_30.io.deq.bits connect remapVecValids[17], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[17] node _T_3845 = eq(UInt<5>(0h1f), remapindex_17) when _T_3845 : connect remapVecData[17], Queue10_UInt8_31.io.deq.bits connect remapVecValids[17], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[17] node _remapindex_T_18 = add(UInt<5>(0h12), read_start_index) node remapindex_18 = rem(_remapindex_T_18, UInt<6>(0h20)) node _T_3846 = eq(UInt<1>(0h0), remapindex_18) when _T_3846 : connect remapVecData[18], Queue10_UInt8.io.deq.bits connect remapVecValids[18], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[18] node _T_3847 = eq(UInt<1>(0h1), remapindex_18) when _T_3847 : connect remapVecData[18], Queue10_UInt8_1.io.deq.bits connect remapVecValids[18], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[18] node _T_3848 = eq(UInt<2>(0h2), remapindex_18) when _T_3848 : connect remapVecData[18], Queue10_UInt8_2.io.deq.bits connect remapVecValids[18], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[18] node _T_3849 = eq(UInt<2>(0h3), remapindex_18) when _T_3849 : connect remapVecData[18], Queue10_UInt8_3.io.deq.bits connect remapVecValids[18], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[18] node _T_3850 = eq(UInt<3>(0h4), remapindex_18) when _T_3850 : connect remapVecData[18], Queue10_UInt8_4.io.deq.bits connect remapVecValids[18], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[18] node _T_3851 = eq(UInt<3>(0h5), remapindex_18) when _T_3851 : connect remapVecData[18], Queue10_UInt8_5.io.deq.bits connect remapVecValids[18], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[18] node _T_3852 = eq(UInt<3>(0h6), remapindex_18) when _T_3852 : connect remapVecData[18], Queue10_UInt8_6.io.deq.bits connect remapVecValids[18], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[18] node _T_3853 = eq(UInt<3>(0h7), remapindex_18) when _T_3853 : connect remapVecData[18], Queue10_UInt8_7.io.deq.bits connect remapVecValids[18], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[18] node _T_3854 = eq(UInt<4>(0h8), remapindex_18) when _T_3854 : connect remapVecData[18], Queue10_UInt8_8.io.deq.bits connect remapVecValids[18], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[18] node _T_3855 = eq(UInt<4>(0h9), remapindex_18) when _T_3855 : connect remapVecData[18], Queue10_UInt8_9.io.deq.bits connect remapVecValids[18], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[18] node _T_3856 = eq(UInt<4>(0ha), remapindex_18) when _T_3856 : connect remapVecData[18], Queue10_UInt8_10.io.deq.bits connect remapVecValids[18], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[18] node _T_3857 = eq(UInt<4>(0hb), remapindex_18) when _T_3857 : connect remapVecData[18], Queue10_UInt8_11.io.deq.bits connect remapVecValids[18], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[18] node _T_3858 = eq(UInt<4>(0hc), remapindex_18) when _T_3858 : connect remapVecData[18], Queue10_UInt8_12.io.deq.bits connect remapVecValids[18], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[18] node _T_3859 = eq(UInt<4>(0hd), remapindex_18) when _T_3859 : connect remapVecData[18], Queue10_UInt8_13.io.deq.bits connect remapVecValids[18], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[18] node _T_3860 = eq(UInt<4>(0he), remapindex_18) when _T_3860 : connect remapVecData[18], Queue10_UInt8_14.io.deq.bits connect remapVecValids[18], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[18] node _T_3861 = eq(UInt<4>(0hf), remapindex_18) when _T_3861 : connect remapVecData[18], Queue10_UInt8_15.io.deq.bits connect remapVecValids[18], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[18] node _T_3862 = eq(UInt<5>(0h10), remapindex_18) when _T_3862 : connect remapVecData[18], Queue10_UInt8_16.io.deq.bits connect remapVecValids[18], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[18] node _T_3863 = eq(UInt<5>(0h11), remapindex_18) when _T_3863 : connect remapVecData[18], Queue10_UInt8_17.io.deq.bits connect remapVecValids[18], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[18] node _T_3864 = eq(UInt<5>(0h12), remapindex_18) when _T_3864 : connect remapVecData[18], Queue10_UInt8_18.io.deq.bits connect remapVecValids[18], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[18] node _T_3865 = eq(UInt<5>(0h13), remapindex_18) when _T_3865 : connect remapVecData[18], Queue10_UInt8_19.io.deq.bits connect remapVecValids[18], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[18] node _T_3866 = eq(UInt<5>(0h14), remapindex_18) when _T_3866 : connect remapVecData[18], Queue10_UInt8_20.io.deq.bits connect remapVecValids[18], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[18] node _T_3867 = eq(UInt<5>(0h15), remapindex_18) when _T_3867 : connect remapVecData[18], Queue10_UInt8_21.io.deq.bits connect remapVecValids[18], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[18] node _T_3868 = eq(UInt<5>(0h16), remapindex_18) when _T_3868 : connect remapVecData[18], Queue10_UInt8_22.io.deq.bits connect remapVecValids[18], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[18] node _T_3869 = eq(UInt<5>(0h17), remapindex_18) when _T_3869 : connect remapVecData[18], Queue10_UInt8_23.io.deq.bits connect remapVecValids[18], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[18] node _T_3870 = eq(UInt<5>(0h18), remapindex_18) when _T_3870 : connect remapVecData[18], Queue10_UInt8_24.io.deq.bits connect remapVecValids[18], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[18] node _T_3871 = eq(UInt<5>(0h19), remapindex_18) when _T_3871 : connect remapVecData[18], Queue10_UInt8_25.io.deq.bits connect remapVecValids[18], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[18] node _T_3872 = eq(UInt<5>(0h1a), remapindex_18) when _T_3872 : connect remapVecData[18], Queue10_UInt8_26.io.deq.bits connect remapVecValids[18], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[18] node _T_3873 = eq(UInt<5>(0h1b), remapindex_18) when _T_3873 : connect remapVecData[18], Queue10_UInt8_27.io.deq.bits connect remapVecValids[18], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[18] node _T_3874 = eq(UInt<5>(0h1c), remapindex_18) when _T_3874 : connect remapVecData[18], Queue10_UInt8_28.io.deq.bits connect remapVecValids[18], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[18] node _T_3875 = eq(UInt<5>(0h1d), remapindex_18) when _T_3875 : connect remapVecData[18], Queue10_UInt8_29.io.deq.bits connect remapVecValids[18], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[18] node _T_3876 = eq(UInt<5>(0h1e), remapindex_18) when _T_3876 : connect remapVecData[18], Queue10_UInt8_30.io.deq.bits connect remapVecValids[18], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[18] node _T_3877 = eq(UInt<5>(0h1f), remapindex_18) when _T_3877 : connect remapVecData[18], Queue10_UInt8_31.io.deq.bits connect remapVecValids[18], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[18] node _remapindex_T_19 = add(UInt<5>(0h13), read_start_index) node remapindex_19 = rem(_remapindex_T_19, UInt<6>(0h20)) node _T_3878 = eq(UInt<1>(0h0), remapindex_19) when _T_3878 : connect remapVecData[19], Queue10_UInt8.io.deq.bits connect remapVecValids[19], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[19] node _T_3879 = eq(UInt<1>(0h1), remapindex_19) when _T_3879 : connect remapVecData[19], Queue10_UInt8_1.io.deq.bits connect remapVecValids[19], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[19] node _T_3880 = eq(UInt<2>(0h2), remapindex_19) when _T_3880 : connect remapVecData[19], Queue10_UInt8_2.io.deq.bits connect remapVecValids[19], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[19] node _T_3881 = eq(UInt<2>(0h3), remapindex_19) when _T_3881 : connect remapVecData[19], Queue10_UInt8_3.io.deq.bits connect remapVecValids[19], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[19] node _T_3882 = eq(UInt<3>(0h4), remapindex_19) when _T_3882 : connect remapVecData[19], Queue10_UInt8_4.io.deq.bits connect remapVecValids[19], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[19] node _T_3883 = eq(UInt<3>(0h5), remapindex_19) when _T_3883 : connect remapVecData[19], Queue10_UInt8_5.io.deq.bits connect remapVecValids[19], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[19] node _T_3884 = eq(UInt<3>(0h6), remapindex_19) when _T_3884 : connect remapVecData[19], Queue10_UInt8_6.io.deq.bits connect remapVecValids[19], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[19] node _T_3885 = eq(UInt<3>(0h7), remapindex_19) when _T_3885 : connect remapVecData[19], Queue10_UInt8_7.io.deq.bits connect remapVecValids[19], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[19] node _T_3886 = eq(UInt<4>(0h8), remapindex_19) when _T_3886 : connect remapVecData[19], Queue10_UInt8_8.io.deq.bits connect remapVecValids[19], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[19] node _T_3887 = eq(UInt<4>(0h9), remapindex_19) when _T_3887 : connect remapVecData[19], Queue10_UInt8_9.io.deq.bits connect remapVecValids[19], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[19] node _T_3888 = eq(UInt<4>(0ha), remapindex_19) when _T_3888 : connect remapVecData[19], Queue10_UInt8_10.io.deq.bits connect remapVecValids[19], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[19] node _T_3889 = eq(UInt<4>(0hb), remapindex_19) when _T_3889 : connect remapVecData[19], Queue10_UInt8_11.io.deq.bits connect remapVecValids[19], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[19] node _T_3890 = eq(UInt<4>(0hc), remapindex_19) when _T_3890 : connect remapVecData[19], Queue10_UInt8_12.io.deq.bits connect remapVecValids[19], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[19] node _T_3891 = eq(UInt<4>(0hd), remapindex_19) when _T_3891 : connect remapVecData[19], Queue10_UInt8_13.io.deq.bits connect remapVecValids[19], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[19] node _T_3892 = eq(UInt<4>(0he), remapindex_19) when _T_3892 : connect remapVecData[19], Queue10_UInt8_14.io.deq.bits connect remapVecValids[19], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[19] node _T_3893 = eq(UInt<4>(0hf), remapindex_19) when _T_3893 : connect remapVecData[19], Queue10_UInt8_15.io.deq.bits connect remapVecValids[19], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[19] node _T_3894 = eq(UInt<5>(0h10), remapindex_19) when _T_3894 : connect remapVecData[19], Queue10_UInt8_16.io.deq.bits connect remapVecValids[19], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[19] node _T_3895 = eq(UInt<5>(0h11), remapindex_19) when _T_3895 : connect remapVecData[19], Queue10_UInt8_17.io.deq.bits connect remapVecValids[19], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[19] node _T_3896 = eq(UInt<5>(0h12), remapindex_19) when _T_3896 : connect remapVecData[19], Queue10_UInt8_18.io.deq.bits connect remapVecValids[19], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[19] node _T_3897 = eq(UInt<5>(0h13), remapindex_19) when _T_3897 : connect remapVecData[19], Queue10_UInt8_19.io.deq.bits connect remapVecValids[19], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[19] node _T_3898 = eq(UInt<5>(0h14), remapindex_19) when _T_3898 : connect remapVecData[19], Queue10_UInt8_20.io.deq.bits connect remapVecValids[19], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[19] node _T_3899 = eq(UInt<5>(0h15), remapindex_19) when _T_3899 : connect remapVecData[19], Queue10_UInt8_21.io.deq.bits connect remapVecValids[19], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[19] node _T_3900 = eq(UInt<5>(0h16), remapindex_19) when _T_3900 : connect remapVecData[19], Queue10_UInt8_22.io.deq.bits connect remapVecValids[19], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[19] node _T_3901 = eq(UInt<5>(0h17), remapindex_19) when _T_3901 : connect remapVecData[19], Queue10_UInt8_23.io.deq.bits connect remapVecValids[19], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[19] node _T_3902 = eq(UInt<5>(0h18), remapindex_19) when _T_3902 : connect remapVecData[19], Queue10_UInt8_24.io.deq.bits connect remapVecValids[19], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[19] node _T_3903 = eq(UInt<5>(0h19), remapindex_19) when _T_3903 : connect remapVecData[19], Queue10_UInt8_25.io.deq.bits connect remapVecValids[19], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[19] node _T_3904 = eq(UInt<5>(0h1a), remapindex_19) when _T_3904 : connect remapVecData[19], Queue10_UInt8_26.io.deq.bits connect remapVecValids[19], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[19] node _T_3905 = eq(UInt<5>(0h1b), remapindex_19) when _T_3905 : connect remapVecData[19], Queue10_UInt8_27.io.deq.bits connect remapVecValids[19], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[19] node _T_3906 = eq(UInt<5>(0h1c), remapindex_19) when _T_3906 : connect remapVecData[19], Queue10_UInt8_28.io.deq.bits connect remapVecValids[19], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[19] node _T_3907 = eq(UInt<5>(0h1d), remapindex_19) when _T_3907 : connect remapVecData[19], Queue10_UInt8_29.io.deq.bits connect remapVecValids[19], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[19] node _T_3908 = eq(UInt<5>(0h1e), remapindex_19) when _T_3908 : connect remapVecData[19], Queue10_UInt8_30.io.deq.bits connect remapVecValids[19], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[19] node _T_3909 = eq(UInt<5>(0h1f), remapindex_19) when _T_3909 : connect remapVecData[19], Queue10_UInt8_31.io.deq.bits connect remapVecValids[19], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[19] node _remapindex_T_20 = add(UInt<5>(0h14), read_start_index) node remapindex_20 = rem(_remapindex_T_20, UInt<6>(0h20)) node _T_3910 = eq(UInt<1>(0h0), remapindex_20) when _T_3910 : connect remapVecData[20], Queue10_UInt8.io.deq.bits connect remapVecValids[20], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[20] node _T_3911 = eq(UInt<1>(0h1), remapindex_20) when _T_3911 : connect remapVecData[20], Queue10_UInt8_1.io.deq.bits connect remapVecValids[20], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[20] node _T_3912 = eq(UInt<2>(0h2), remapindex_20) when _T_3912 : connect remapVecData[20], Queue10_UInt8_2.io.deq.bits connect remapVecValids[20], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[20] node _T_3913 = eq(UInt<2>(0h3), remapindex_20) when _T_3913 : connect remapVecData[20], Queue10_UInt8_3.io.deq.bits connect remapVecValids[20], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[20] node _T_3914 = eq(UInt<3>(0h4), remapindex_20) when _T_3914 : connect remapVecData[20], Queue10_UInt8_4.io.deq.bits connect remapVecValids[20], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[20] node _T_3915 = eq(UInt<3>(0h5), remapindex_20) when _T_3915 : connect remapVecData[20], Queue10_UInt8_5.io.deq.bits connect remapVecValids[20], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[20] node _T_3916 = eq(UInt<3>(0h6), remapindex_20) when _T_3916 : connect remapVecData[20], Queue10_UInt8_6.io.deq.bits connect remapVecValids[20], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[20] node _T_3917 = eq(UInt<3>(0h7), remapindex_20) when _T_3917 : connect remapVecData[20], Queue10_UInt8_7.io.deq.bits connect remapVecValids[20], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[20] node _T_3918 = eq(UInt<4>(0h8), remapindex_20) when _T_3918 : connect remapVecData[20], Queue10_UInt8_8.io.deq.bits connect remapVecValids[20], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[20] node _T_3919 = eq(UInt<4>(0h9), remapindex_20) when _T_3919 : connect remapVecData[20], Queue10_UInt8_9.io.deq.bits connect remapVecValids[20], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[20] node _T_3920 = eq(UInt<4>(0ha), remapindex_20) when _T_3920 : connect remapVecData[20], Queue10_UInt8_10.io.deq.bits connect remapVecValids[20], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[20] node _T_3921 = eq(UInt<4>(0hb), remapindex_20) when _T_3921 : connect remapVecData[20], Queue10_UInt8_11.io.deq.bits connect remapVecValids[20], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[20] node _T_3922 = eq(UInt<4>(0hc), remapindex_20) when _T_3922 : connect remapVecData[20], Queue10_UInt8_12.io.deq.bits connect remapVecValids[20], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[20] node _T_3923 = eq(UInt<4>(0hd), remapindex_20) when _T_3923 : connect remapVecData[20], Queue10_UInt8_13.io.deq.bits connect remapVecValids[20], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[20] node _T_3924 = eq(UInt<4>(0he), remapindex_20) when _T_3924 : connect remapVecData[20], Queue10_UInt8_14.io.deq.bits connect remapVecValids[20], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[20] node _T_3925 = eq(UInt<4>(0hf), remapindex_20) when _T_3925 : connect remapVecData[20], Queue10_UInt8_15.io.deq.bits connect remapVecValids[20], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[20] node _T_3926 = eq(UInt<5>(0h10), remapindex_20) when _T_3926 : connect remapVecData[20], Queue10_UInt8_16.io.deq.bits connect remapVecValids[20], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[20] node _T_3927 = eq(UInt<5>(0h11), remapindex_20) when _T_3927 : connect remapVecData[20], Queue10_UInt8_17.io.deq.bits connect remapVecValids[20], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[20] node _T_3928 = eq(UInt<5>(0h12), remapindex_20) when _T_3928 : connect remapVecData[20], Queue10_UInt8_18.io.deq.bits connect remapVecValids[20], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[20] node _T_3929 = eq(UInt<5>(0h13), remapindex_20) when _T_3929 : connect remapVecData[20], Queue10_UInt8_19.io.deq.bits connect remapVecValids[20], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[20] node _T_3930 = eq(UInt<5>(0h14), remapindex_20) when _T_3930 : connect remapVecData[20], Queue10_UInt8_20.io.deq.bits connect remapVecValids[20], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[20] node _T_3931 = eq(UInt<5>(0h15), remapindex_20) when _T_3931 : connect remapVecData[20], Queue10_UInt8_21.io.deq.bits connect remapVecValids[20], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[20] node _T_3932 = eq(UInt<5>(0h16), remapindex_20) when _T_3932 : connect remapVecData[20], Queue10_UInt8_22.io.deq.bits connect remapVecValids[20], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[20] node _T_3933 = eq(UInt<5>(0h17), remapindex_20) when _T_3933 : connect remapVecData[20], Queue10_UInt8_23.io.deq.bits connect remapVecValids[20], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[20] node _T_3934 = eq(UInt<5>(0h18), remapindex_20) when _T_3934 : connect remapVecData[20], Queue10_UInt8_24.io.deq.bits connect remapVecValids[20], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[20] node _T_3935 = eq(UInt<5>(0h19), remapindex_20) when _T_3935 : connect remapVecData[20], Queue10_UInt8_25.io.deq.bits connect remapVecValids[20], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[20] node _T_3936 = eq(UInt<5>(0h1a), remapindex_20) when _T_3936 : connect remapVecData[20], Queue10_UInt8_26.io.deq.bits connect remapVecValids[20], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[20] node _T_3937 = eq(UInt<5>(0h1b), remapindex_20) when _T_3937 : connect remapVecData[20], Queue10_UInt8_27.io.deq.bits connect remapVecValids[20], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[20] node _T_3938 = eq(UInt<5>(0h1c), remapindex_20) when _T_3938 : connect remapVecData[20], Queue10_UInt8_28.io.deq.bits connect remapVecValids[20], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[20] node _T_3939 = eq(UInt<5>(0h1d), remapindex_20) when _T_3939 : connect remapVecData[20], Queue10_UInt8_29.io.deq.bits connect remapVecValids[20], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[20] node _T_3940 = eq(UInt<5>(0h1e), remapindex_20) when _T_3940 : connect remapVecData[20], Queue10_UInt8_30.io.deq.bits connect remapVecValids[20], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[20] node _T_3941 = eq(UInt<5>(0h1f), remapindex_20) when _T_3941 : connect remapVecData[20], Queue10_UInt8_31.io.deq.bits connect remapVecValids[20], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[20] node _remapindex_T_21 = add(UInt<5>(0h15), read_start_index) node remapindex_21 = rem(_remapindex_T_21, UInt<6>(0h20)) node _T_3942 = eq(UInt<1>(0h0), remapindex_21) when _T_3942 : connect remapVecData[21], Queue10_UInt8.io.deq.bits connect remapVecValids[21], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[21] node _T_3943 = eq(UInt<1>(0h1), remapindex_21) when _T_3943 : connect remapVecData[21], Queue10_UInt8_1.io.deq.bits connect remapVecValids[21], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[21] node _T_3944 = eq(UInt<2>(0h2), remapindex_21) when _T_3944 : connect remapVecData[21], Queue10_UInt8_2.io.deq.bits connect remapVecValids[21], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[21] node _T_3945 = eq(UInt<2>(0h3), remapindex_21) when _T_3945 : connect remapVecData[21], Queue10_UInt8_3.io.deq.bits connect remapVecValids[21], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[21] node _T_3946 = eq(UInt<3>(0h4), remapindex_21) when _T_3946 : connect remapVecData[21], Queue10_UInt8_4.io.deq.bits connect remapVecValids[21], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[21] node _T_3947 = eq(UInt<3>(0h5), remapindex_21) when _T_3947 : connect remapVecData[21], Queue10_UInt8_5.io.deq.bits connect remapVecValids[21], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[21] node _T_3948 = eq(UInt<3>(0h6), remapindex_21) when _T_3948 : connect remapVecData[21], Queue10_UInt8_6.io.deq.bits connect remapVecValids[21], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[21] node _T_3949 = eq(UInt<3>(0h7), remapindex_21) when _T_3949 : connect remapVecData[21], Queue10_UInt8_7.io.deq.bits connect remapVecValids[21], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[21] node _T_3950 = eq(UInt<4>(0h8), remapindex_21) when _T_3950 : connect remapVecData[21], Queue10_UInt8_8.io.deq.bits connect remapVecValids[21], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[21] node _T_3951 = eq(UInt<4>(0h9), remapindex_21) when _T_3951 : connect remapVecData[21], Queue10_UInt8_9.io.deq.bits connect remapVecValids[21], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[21] node _T_3952 = eq(UInt<4>(0ha), remapindex_21) when _T_3952 : connect remapVecData[21], Queue10_UInt8_10.io.deq.bits connect remapVecValids[21], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[21] node _T_3953 = eq(UInt<4>(0hb), remapindex_21) when _T_3953 : connect remapVecData[21], Queue10_UInt8_11.io.deq.bits connect remapVecValids[21], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[21] node _T_3954 = eq(UInt<4>(0hc), remapindex_21) when _T_3954 : connect remapVecData[21], Queue10_UInt8_12.io.deq.bits connect remapVecValids[21], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[21] node _T_3955 = eq(UInt<4>(0hd), remapindex_21) when _T_3955 : connect remapVecData[21], Queue10_UInt8_13.io.deq.bits connect remapVecValids[21], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[21] node _T_3956 = eq(UInt<4>(0he), remapindex_21) when _T_3956 : connect remapVecData[21], Queue10_UInt8_14.io.deq.bits connect remapVecValids[21], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[21] node _T_3957 = eq(UInt<4>(0hf), remapindex_21) when _T_3957 : connect remapVecData[21], Queue10_UInt8_15.io.deq.bits connect remapVecValids[21], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[21] node _T_3958 = eq(UInt<5>(0h10), remapindex_21) when _T_3958 : connect remapVecData[21], Queue10_UInt8_16.io.deq.bits connect remapVecValids[21], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[21] node _T_3959 = eq(UInt<5>(0h11), remapindex_21) when _T_3959 : connect remapVecData[21], Queue10_UInt8_17.io.deq.bits connect remapVecValids[21], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[21] node _T_3960 = eq(UInt<5>(0h12), remapindex_21) when _T_3960 : connect remapVecData[21], Queue10_UInt8_18.io.deq.bits connect remapVecValids[21], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[21] node _T_3961 = eq(UInt<5>(0h13), remapindex_21) when _T_3961 : connect remapVecData[21], Queue10_UInt8_19.io.deq.bits connect remapVecValids[21], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[21] node _T_3962 = eq(UInt<5>(0h14), remapindex_21) when _T_3962 : connect remapVecData[21], Queue10_UInt8_20.io.deq.bits connect remapVecValids[21], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[21] node _T_3963 = eq(UInt<5>(0h15), remapindex_21) when _T_3963 : connect remapVecData[21], Queue10_UInt8_21.io.deq.bits connect remapVecValids[21], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[21] node _T_3964 = eq(UInt<5>(0h16), remapindex_21) when _T_3964 : connect remapVecData[21], Queue10_UInt8_22.io.deq.bits connect remapVecValids[21], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[21] node _T_3965 = eq(UInt<5>(0h17), remapindex_21) when _T_3965 : connect remapVecData[21], Queue10_UInt8_23.io.deq.bits connect remapVecValids[21], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[21] node _T_3966 = eq(UInt<5>(0h18), remapindex_21) when _T_3966 : connect remapVecData[21], Queue10_UInt8_24.io.deq.bits connect remapVecValids[21], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[21] node _T_3967 = eq(UInt<5>(0h19), remapindex_21) when _T_3967 : connect remapVecData[21], Queue10_UInt8_25.io.deq.bits connect remapVecValids[21], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[21] node _T_3968 = eq(UInt<5>(0h1a), remapindex_21) when _T_3968 : connect remapVecData[21], Queue10_UInt8_26.io.deq.bits connect remapVecValids[21], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[21] node _T_3969 = eq(UInt<5>(0h1b), remapindex_21) when _T_3969 : connect remapVecData[21], Queue10_UInt8_27.io.deq.bits connect remapVecValids[21], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[21] node _T_3970 = eq(UInt<5>(0h1c), remapindex_21) when _T_3970 : connect remapVecData[21], Queue10_UInt8_28.io.deq.bits connect remapVecValids[21], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[21] node _T_3971 = eq(UInt<5>(0h1d), remapindex_21) when _T_3971 : connect remapVecData[21], Queue10_UInt8_29.io.deq.bits connect remapVecValids[21], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[21] node _T_3972 = eq(UInt<5>(0h1e), remapindex_21) when _T_3972 : connect remapVecData[21], Queue10_UInt8_30.io.deq.bits connect remapVecValids[21], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[21] node _T_3973 = eq(UInt<5>(0h1f), remapindex_21) when _T_3973 : connect remapVecData[21], Queue10_UInt8_31.io.deq.bits connect remapVecValids[21], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[21] node _remapindex_T_22 = add(UInt<5>(0h16), read_start_index) node remapindex_22 = rem(_remapindex_T_22, UInt<6>(0h20)) node _T_3974 = eq(UInt<1>(0h0), remapindex_22) when _T_3974 : connect remapVecData[22], Queue10_UInt8.io.deq.bits connect remapVecValids[22], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[22] node _T_3975 = eq(UInt<1>(0h1), remapindex_22) when _T_3975 : connect remapVecData[22], Queue10_UInt8_1.io.deq.bits connect remapVecValids[22], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[22] node _T_3976 = eq(UInt<2>(0h2), remapindex_22) when _T_3976 : connect remapVecData[22], Queue10_UInt8_2.io.deq.bits connect remapVecValids[22], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[22] node _T_3977 = eq(UInt<2>(0h3), remapindex_22) when _T_3977 : connect remapVecData[22], Queue10_UInt8_3.io.deq.bits connect remapVecValids[22], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[22] node _T_3978 = eq(UInt<3>(0h4), remapindex_22) when _T_3978 : connect remapVecData[22], Queue10_UInt8_4.io.deq.bits connect remapVecValids[22], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[22] node _T_3979 = eq(UInt<3>(0h5), remapindex_22) when _T_3979 : connect remapVecData[22], Queue10_UInt8_5.io.deq.bits connect remapVecValids[22], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[22] node _T_3980 = eq(UInt<3>(0h6), remapindex_22) when _T_3980 : connect remapVecData[22], Queue10_UInt8_6.io.deq.bits connect remapVecValids[22], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[22] node _T_3981 = eq(UInt<3>(0h7), remapindex_22) when _T_3981 : connect remapVecData[22], Queue10_UInt8_7.io.deq.bits connect remapVecValids[22], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[22] node _T_3982 = eq(UInt<4>(0h8), remapindex_22) when _T_3982 : connect remapVecData[22], Queue10_UInt8_8.io.deq.bits connect remapVecValids[22], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[22] node _T_3983 = eq(UInt<4>(0h9), remapindex_22) when _T_3983 : connect remapVecData[22], Queue10_UInt8_9.io.deq.bits connect remapVecValids[22], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[22] node _T_3984 = eq(UInt<4>(0ha), remapindex_22) when _T_3984 : connect remapVecData[22], Queue10_UInt8_10.io.deq.bits connect remapVecValids[22], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[22] node _T_3985 = eq(UInt<4>(0hb), remapindex_22) when _T_3985 : connect remapVecData[22], Queue10_UInt8_11.io.deq.bits connect remapVecValids[22], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[22] node _T_3986 = eq(UInt<4>(0hc), remapindex_22) when _T_3986 : connect remapVecData[22], Queue10_UInt8_12.io.deq.bits connect remapVecValids[22], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[22] node _T_3987 = eq(UInt<4>(0hd), remapindex_22) when _T_3987 : connect remapVecData[22], Queue10_UInt8_13.io.deq.bits connect remapVecValids[22], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[22] node _T_3988 = eq(UInt<4>(0he), remapindex_22) when _T_3988 : connect remapVecData[22], Queue10_UInt8_14.io.deq.bits connect remapVecValids[22], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[22] node _T_3989 = eq(UInt<4>(0hf), remapindex_22) when _T_3989 : connect remapVecData[22], Queue10_UInt8_15.io.deq.bits connect remapVecValids[22], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[22] node _T_3990 = eq(UInt<5>(0h10), remapindex_22) when _T_3990 : connect remapVecData[22], Queue10_UInt8_16.io.deq.bits connect remapVecValids[22], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[22] node _T_3991 = eq(UInt<5>(0h11), remapindex_22) when _T_3991 : connect remapVecData[22], Queue10_UInt8_17.io.deq.bits connect remapVecValids[22], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[22] node _T_3992 = eq(UInt<5>(0h12), remapindex_22) when _T_3992 : connect remapVecData[22], Queue10_UInt8_18.io.deq.bits connect remapVecValids[22], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[22] node _T_3993 = eq(UInt<5>(0h13), remapindex_22) when _T_3993 : connect remapVecData[22], Queue10_UInt8_19.io.deq.bits connect remapVecValids[22], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[22] node _T_3994 = eq(UInt<5>(0h14), remapindex_22) when _T_3994 : connect remapVecData[22], Queue10_UInt8_20.io.deq.bits connect remapVecValids[22], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[22] node _T_3995 = eq(UInt<5>(0h15), remapindex_22) when _T_3995 : connect remapVecData[22], Queue10_UInt8_21.io.deq.bits connect remapVecValids[22], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[22] node _T_3996 = eq(UInt<5>(0h16), remapindex_22) when _T_3996 : connect remapVecData[22], Queue10_UInt8_22.io.deq.bits connect remapVecValids[22], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[22] node _T_3997 = eq(UInt<5>(0h17), remapindex_22) when _T_3997 : connect remapVecData[22], Queue10_UInt8_23.io.deq.bits connect remapVecValids[22], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[22] node _T_3998 = eq(UInt<5>(0h18), remapindex_22) when _T_3998 : connect remapVecData[22], Queue10_UInt8_24.io.deq.bits connect remapVecValids[22], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[22] node _T_3999 = eq(UInt<5>(0h19), remapindex_22) when _T_3999 : connect remapVecData[22], Queue10_UInt8_25.io.deq.bits connect remapVecValids[22], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[22] node _T_4000 = eq(UInt<5>(0h1a), remapindex_22) when _T_4000 : connect remapVecData[22], Queue10_UInt8_26.io.deq.bits connect remapVecValids[22], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[22] node _T_4001 = eq(UInt<5>(0h1b), remapindex_22) when _T_4001 : connect remapVecData[22], Queue10_UInt8_27.io.deq.bits connect remapVecValids[22], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[22] node _T_4002 = eq(UInt<5>(0h1c), remapindex_22) when _T_4002 : connect remapVecData[22], Queue10_UInt8_28.io.deq.bits connect remapVecValids[22], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[22] node _T_4003 = eq(UInt<5>(0h1d), remapindex_22) when _T_4003 : connect remapVecData[22], Queue10_UInt8_29.io.deq.bits connect remapVecValids[22], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[22] node _T_4004 = eq(UInt<5>(0h1e), remapindex_22) when _T_4004 : connect remapVecData[22], Queue10_UInt8_30.io.deq.bits connect remapVecValids[22], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[22] node _T_4005 = eq(UInt<5>(0h1f), remapindex_22) when _T_4005 : connect remapVecData[22], Queue10_UInt8_31.io.deq.bits connect remapVecValids[22], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[22] node _remapindex_T_23 = add(UInt<5>(0h17), read_start_index) node remapindex_23 = rem(_remapindex_T_23, UInt<6>(0h20)) node _T_4006 = eq(UInt<1>(0h0), remapindex_23) when _T_4006 : connect remapVecData[23], Queue10_UInt8.io.deq.bits connect remapVecValids[23], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[23] node _T_4007 = eq(UInt<1>(0h1), remapindex_23) when _T_4007 : connect remapVecData[23], Queue10_UInt8_1.io.deq.bits connect remapVecValids[23], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[23] node _T_4008 = eq(UInt<2>(0h2), remapindex_23) when _T_4008 : connect remapVecData[23], Queue10_UInt8_2.io.deq.bits connect remapVecValids[23], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[23] node _T_4009 = eq(UInt<2>(0h3), remapindex_23) when _T_4009 : connect remapVecData[23], Queue10_UInt8_3.io.deq.bits connect remapVecValids[23], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[23] node _T_4010 = eq(UInt<3>(0h4), remapindex_23) when _T_4010 : connect remapVecData[23], Queue10_UInt8_4.io.deq.bits connect remapVecValids[23], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[23] node _T_4011 = eq(UInt<3>(0h5), remapindex_23) when _T_4011 : connect remapVecData[23], Queue10_UInt8_5.io.deq.bits connect remapVecValids[23], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[23] node _T_4012 = eq(UInt<3>(0h6), remapindex_23) when _T_4012 : connect remapVecData[23], Queue10_UInt8_6.io.deq.bits connect remapVecValids[23], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[23] node _T_4013 = eq(UInt<3>(0h7), remapindex_23) when _T_4013 : connect remapVecData[23], Queue10_UInt8_7.io.deq.bits connect remapVecValids[23], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[23] node _T_4014 = eq(UInt<4>(0h8), remapindex_23) when _T_4014 : connect remapVecData[23], Queue10_UInt8_8.io.deq.bits connect remapVecValids[23], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[23] node _T_4015 = eq(UInt<4>(0h9), remapindex_23) when _T_4015 : connect remapVecData[23], Queue10_UInt8_9.io.deq.bits connect remapVecValids[23], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[23] node _T_4016 = eq(UInt<4>(0ha), remapindex_23) when _T_4016 : connect remapVecData[23], Queue10_UInt8_10.io.deq.bits connect remapVecValids[23], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[23] node _T_4017 = eq(UInt<4>(0hb), remapindex_23) when _T_4017 : connect remapVecData[23], Queue10_UInt8_11.io.deq.bits connect remapVecValids[23], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[23] node _T_4018 = eq(UInt<4>(0hc), remapindex_23) when _T_4018 : connect remapVecData[23], Queue10_UInt8_12.io.deq.bits connect remapVecValids[23], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[23] node _T_4019 = eq(UInt<4>(0hd), remapindex_23) when _T_4019 : connect remapVecData[23], Queue10_UInt8_13.io.deq.bits connect remapVecValids[23], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[23] node _T_4020 = eq(UInt<4>(0he), remapindex_23) when _T_4020 : connect remapVecData[23], Queue10_UInt8_14.io.deq.bits connect remapVecValids[23], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[23] node _T_4021 = eq(UInt<4>(0hf), remapindex_23) when _T_4021 : connect remapVecData[23], Queue10_UInt8_15.io.deq.bits connect remapVecValids[23], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[23] node _T_4022 = eq(UInt<5>(0h10), remapindex_23) when _T_4022 : connect remapVecData[23], Queue10_UInt8_16.io.deq.bits connect remapVecValids[23], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[23] node _T_4023 = eq(UInt<5>(0h11), remapindex_23) when _T_4023 : connect remapVecData[23], Queue10_UInt8_17.io.deq.bits connect remapVecValids[23], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[23] node _T_4024 = eq(UInt<5>(0h12), remapindex_23) when _T_4024 : connect remapVecData[23], Queue10_UInt8_18.io.deq.bits connect remapVecValids[23], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[23] node _T_4025 = eq(UInt<5>(0h13), remapindex_23) when _T_4025 : connect remapVecData[23], Queue10_UInt8_19.io.deq.bits connect remapVecValids[23], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[23] node _T_4026 = eq(UInt<5>(0h14), remapindex_23) when _T_4026 : connect remapVecData[23], Queue10_UInt8_20.io.deq.bits connect remapVecValids[23], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[23] node _T_4027 = eq(UInt<5>(0h15), remapindex_23) when _T_4027 : connect remapVecData[23], Queue10_UInt8_21.io.deq.bits connect remapVecValids[23], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[23] node _T_4028 = eq(UInt<5>(0h16), remapindex_23) when _T_4028 : connect remapVecData[23], Queue10_UInt8_22.io.deq.bits connect remapVecValids[23], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[23] node _T_4029 = eq(UInt<5>(0h17), remapindex_23) when _T_4029 : connect remapVecData[23], Queue10_UInt8_23.io.deq.bits connect remapVecValids[23], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[23] node _T_4030 = eq(UInt<5>(0h18), remapindex_23) when _T_4030 : connect remapVecData[23], Queue10_UInt8_24.io.deq.bits connect remapVecValids[23], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[23] node _T_4031 = eq(UInt<5>(0h19), remapindex_23) when _T_4031 : connect remapVecData[23], Queue10_UInt8_25.io.deq.bits connect remapVecValids[23], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[23] node _T_4032 = eq(UInt<5>(0h1a), remapindex_23) when _T_4032 : connect remapVecData[23], Queue10_UInt8_26.io.deq.bits connect remapVecValids[23], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[23] node _T_4033 = eq(UInt<5>(0h1b), remapindex_23) when _T_4033 : connect remapVecData[23], Queue10_UInt8_27.io.deq.bits connect remapVecValids[23], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[23] node _T_4034 = eq(UInt<5>(0h1c), remapindex_23) when _T_4034 : connect remapVecData[23], Queue10_UInt8_28.io.deq.bits connect remapVecValids[23], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[23] node _T_4035 = eq(UInt<5>(0h1d), remapindex_23) when _T_4035 : connect remapVecData[23], Queue10_UInt8_29.io.deq.bits connect remapVecValids[23], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[23] node _T_4036 = eq(UInt<5>(0h1e), remapindex_23) when _T_4036 : connect remapVecData[23], Queue10_UInt8_30.io.deq.bits connect remapVecValids[23], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[23] node _T_4037 = eq(UInt<5>(0h1f), remapindex_23) when _T_4037 : connect remapVecData[23], Queue10_UInt8_31.io.deq.bits connect remapVecValids[23], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[23] node _remapindex_T_24 = add(UInt<5>(0h18), read_start_index) node remapindex_24 = rem(_remapindex_T_24, UInt<6>(0h20)) node _T_4038 = eq(UInt<1>(0h0), remapindex_24) when _T_4038 : connect remapVecData[24], Queue10_UInt8.io.deq.bits connect remapVecValids[24], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[24] node _T_4039 = eq(UInt<1>(0h1), remapindex_24) when _T_4039 : connect remapVecData[24], Queue10_UInt8_1.io.deq.bits connect remapVecValids[24], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[24] node _T_4040 = eq(UInt<2>(0h2), remapindex_24) when _T_4040 : connect remapVecData[24], Queue10_UInt8_2.io.deq.bits connect remapVecValids[24], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[24] node _T_4041 = eq(UInt<2>(0h3), remapindex_24) when _T_4041 : connect remapVecData[24], Queue10_UInt8_3.io.deq.bits connect remapVecValids[24], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[24] node _T_4042 = eq(UInt<3>(0h4), remapindex_24) when _T_4042 : connect remapVecData[24], Queue10_UInt8_4.io.deq.bits connect remapVecValids[24], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[24] node _T_4043 = eq(UInt<3>(0h5), remapindex_24) when _T_4043 : connect remapVecData[24], Queue10_UInt8_5.io.deq.bits connect remapVecValids[24], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[24] node _T_4044 = eq(UInt<3>(0h6), remapindex_24) when _T_4044 : connect remapVecData[24], Queue10_UInt8_6.io.deq.bits connect remapVecValids[24], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[24] node _T_4045 = eq(UInt<3>(0h7), remapindex_24) when _T_4045 : connect remapVecData[24], Queue10_UInt8_7.io.deq.bits connect remapVecValids[24], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[24] node _T_4046 = eq(UInt<4>(0h8), remapindex_24) when _T_4046 : connect remapVecData[24], Queue10_UInt8_8.io.deq.bits connect remapVecValids[24], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[24] node _T_4047 = eq(UInt<4>(0h9), remapindex_24) when _T_4047 : connect remapVecData[24], Queue10_UInt8_9.io.deq.bits connect remapVecValids[24], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[24] node _T_4048 = eq(UInt<4>(0ha), remapindex_24) when _T_4048 : connect remapVecData[24], Queue10_UInt8_10.io.deq.bits connect remapVecValids[24], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[24] node _T_4049 = eq(UInt<4>(0hb), remapindex_24) when _T_4049 : connect remapVecData[24], Queue10_UInt8_11.io.deq.bits connect remapVecValids[24], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[24] node _T_4050 = eq(UInt<4>(0hc), remapindex_24) when _T_4050 : connect remapVecData[24], Queue10_UInt8_12.io.deq.bits connect remapVecValids[24], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[24] node _T_4051 = eq(UInt<4>(0hd), remapindex_24) when _T_4051 : connect remapVecData[24], Queue10_UInt8_13.io.deq.bits connect remapVecValids[24], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[24] node _T_4052 = eq(UInt<4>(0he), remapindex_24) when _T_4052 : connect remapVecData[24], Queue10_UInt8_14.io.deq.bits connect remapVecValids[24], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[24] node _T_4053 = eq(UInt<4>(0hf), remapindex_24) when _T_4053 : connect remapVecData[24], Queue10_UInt8_15.io.deq.bits connect remapVecValids[24], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[24] node _T_4054 = eq(UInt<5>(0h10), remapindex_24) when _T_4054 : connect remapVecData[24], Queue10_UInt8_16.io.deq.bits connect remapVecValids[24], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[24] node _T_4055 = eq(UInt<5>(0h11), remapindex_24) when _T_4055 : connect remapVecData[24], Queue10_UInt8_17.io.deq.bits connect remapVecValids[24], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[24] node _T_4056 = eq(UInt<5>(0h12), remapindex_24) when _T_4056 : connect remapVecData[24], Queue10_UInt8_18.io.deq.bits connect remapVecValids[24], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[24] node _T_4057 = eq(UInt<5>(0h13), remapindex_24) when _T_4057 : connect remapVecData[24], Queue10_UInt8_19.io.deq.bits connect remapVecValids[24], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[24] node _T_4058 = eq(UInt<5>(0h14), remapindex_24) when _T_4058 : connect remapVecData[24], Queue10_UInt8_20.io.deq.bits connect remapVecValids[24], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[24] node _T_4059 = eq(UInt<5>(0h15), remapindex_24) when _T_4059 : connect remapVecData[24], Queue10_UInt8_21.io.deq.bits connect remapVecValids[24], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[24] node _T_4060 = eq(UInt<5>(0h16), remapindex_24) when _T_4060 : connect remapVecData[24], Queue10_UInt8_22.io.deq.bits connect remapVecValids[24], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[24] node _T_4061 = eq(UInt<5>(0h17), remapindex_24) when _T_4061 : connect remapVecData[24], Queue10_UInt8_23.io.deq.bits connect remapVecValids[24], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[24] node _T_4062 = eq(UInt<5>(0h18), remapindex_24) when _T_4062 : connect remapVecData[24], Queue10_UInt8_24.io.deq.bits connect remapVecValids[24], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[24] node _T_4063 = eq(UInt<5>(0h19), remapindex_24) when _T_4063 : connect remapVecData[24], Queue10_UInt8_25.io.deq.bits connect remapVecValids[24], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[24] node _T_4064 = eq(UInt<5>(0h1a), remapindex_24) when _T_4064 : connect remapVecData[24], Queue10_UInt8_26.io.deq.bits connect remapVecValids[24], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[24] node _T_4065 = eq(UInt<5>(0h1b), remapindex_24) when _T_4065 : connect remapVecData[24], Queue10_UInt8_27.io.deq.bits connect remapVecValids[24], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[24] node _T_4066 = eq(UInt<5>(0h1c), remapindex_24) when _T_4066 : connect remapVecData[24], Queue10_UInt8_28.io.deq.bits connect remapVecValids[24], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[24] node _T_4067 = eq(UInt<5>(0h1d), remapindex_24) when _T_4067 : connect remapVecData[24], Queue10_UInt8_29.io.deq.bits connect remapVecValids[24], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[24] node _T_4068 = eq(UInt<5>(0h1e), remapindex_24) when _T_4068 : connect remapVecData[24], Queue10_UInt8_30.io.deq.bits connect remapVecValids[24], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[24] node _T_4069 = eq(UInt<5>(0h1f), remapindex_24) when _T_4069 : connect remapVecData[24], Queue10_UInt8_31.io.deq.bits connect remapVecValids[24], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[24] node _remapindex_T_25 = add(UInt<5>(0h19), read_start_index) node remapindex_25 = rem(_remapindex_T_25, UInt<6>(0h20)) node _T_4070 = eq(UInt<1>(0h0), remapindex_25) when _T_4070 : connect remapVecData[25], Queue10_UInt8.io.deq.bits connect remapVecValids[25], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[25] node _T_4071 = eq(UInt<1>(0h1), remapindex_25) when _T_4071 : connect remapVecData[25], Queue10_UInt8_1.io.deq.bits connect remapVecValids[25], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[25] node _T_4072 = eq(UInt<2>(0h2), remapindex_25) when _T_4072 : connect remapVecData[25], Queue10_UInt8_2.io.deq.bits connect remapVecValids[25], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[25] node _T_4073 = eq(UInt<2>(0h3), remapindex_25) when _T_4073 : connect remapVecData[25], Queue10_UInt8_3.io.deq.bits connect remapVecValids[25], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[25] node _T_4074 = eq(UInt<3>(0h4), remapindex_25) when _T_4074 : connect remapVecData[25], Queue10_UInt8_4.io.deq.bits connect remapVecValids[25], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[25] node _T_4075 = eq(UInt<3>(0h5), remapindex_25) when _T_4075 : connect remapVecData[25], Queue10_UInt8_5.io.deq.bits connect remapVecValids[25], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[25] node _T_4076 = eq(UInt<3>(0h6), remapindex_25) when _T_4076 : connect remapVecData[25], Queue10_UInt8_6.io.deq.bits connect remapVecValids[25], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[25] node _T_4077 = eq(UInt<3>(0h7), remapindex_25) when _T_4077 : connect remapVecData[25], Queue10_UInt8_7.io.deq.bits connect remapVecValids[25], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[25] node _T_4078 = eq(UInt<4>(0h8), remapindex_25) when _T_4078 : connect remapVecData[25], Queue10_UInt8_8.io.deq.bits connect remapVecValids[25], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[25] node _T_4079 = eq(UInt<4>(0h9), remapindex_25) when _T_4079 : connect remapVecData[25], Queue10_UInt8_9.io.deq.bits connect remapVecValids[25], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[25] node _T_4080 = eq(UInt<4>(0ha), remapindex_25) when _T_4080 : connect remapVecData[25], Queue10_UInt8_10.io.deq.bits connect remapVecValids[25], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[25] node _T_4081 = eq(UInt<4>(0hb), remapindex_25) when _T_4081 : connect remapVecData[25], Queue10_UInt8_11.io.deq.bits connect remapVecValids[25], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[25] node _T_4082 = eq(UInt<4>(0hc), remapindex_25) when _T_4082 : connect remapVecData[25], Queue10_UInt8_12.io.deq.bits connect remapVecValids[25], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[25] node _T_4083 = eq(UInt<4>(0hd), remapindex_25) when _T_4083 : connect remapVecData[25], Queue10_UInt8_13.io.deq.bits connect remapVecValids[25], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[25] node _T_4084 = eq(UInt<4>(0he), remapindex_25) when _T_4084 : connect remapVecData[25], Queue10_UInt8_14.io.deq.bits connect remapVecValids[25], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[25] node _T_4085 = eq(UInt<4>(0hf), remapindex_25) when _T_4085 : connect remapVecData[25], Queue10_UInt8_15.io.deq.bits connect remapVecValids[25], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[25] node _T_4086 = eq(UInt<5>(0h10), remapindex_25) when _T_4086 : connect remapVecData[25], Queue10_UInt8_16.io.deq.bits connect remapVecValids[25], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[25] node _T_4087 = eq(UInt<5>(0h11), remapindex_25) when _T_4087 : connect remapVecData[25], Queue10_UInt8_17.io.deq.bits connect remapVecValids[25], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[25] node _T_4088 = eq(UInt<5>(0h12), remapindex_25) when _T_4088 : connect remapVecData[25], Queue10_UInt8_18.io.deq.bits connect remapVecValids[25], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[25] node _T_4089 = eq(UInt<5>(0h13), remapindex_25) when _T_4089 : connect remapVecData[25], Queue10_UInt8_19.io.deq.bits connect remapVecValids[25], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[25] node _T_4090 = eq(UInt<5>(0h14), remapindex_25) when _T_4090 : connect remapVecData[25], Queue10_UInt8_20.io.deq.bits connect remapVecValids[25], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[25] node _T_4091 = eq(UInt<5>(0h15), remapindex_25) when _T_4091 : connect remapVecData[25], Queue10_UInt8_21.io.deq.bits connect remapVecValids[25], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[25] node _T_4092 = eq(UInt<5>(0h16), remapindex_25) when _T_4092 : connect remapVecData[25], Queue10_UInt8_22.io.deq.bits connect remapVecValids[25], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[25] node _T_4093 = eq(UInt<5>(0h17), remapindex_25) when _T_4093 : connect remapVecData[25], Queue10_UInt8_23.io.deq.bits connect remapVecValids[25], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[25] node _T_4094 = eq(UInt<5>(0h18), remapindex_25) when _T_4094 : connect remapVecData[25], Queue10_UInt8_24.io.deq.bits connect remapVecValids[25], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[25] node _T_4095 = eq(UInt<5>(0h19), remapindex_25) when _T_4095 : connect remapVecData[25], Queue10_UInt8_25.io.deq.bits connect remapVecValids[25], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[25] node _T_4096 = eq(UInt<5>(0h1a), remapindex_25) when _T_4096 : connect remapVecData[25], Queue10_UInt8_26.io.deq.bits connect remapVecValids[25], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[25] node _T_4097 = eq(UInt<5>(0h1b), remapindex_25) when _T_4097 : connect remapVecData[25], Queue10_UInt8_27.io.deq.bits connect remapVecValids[25], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[25] node _T_4098 = eq(UInt<5>(0h1c), remapindex_25) when _T_4098 : connect remapVecData[25], Queue10_UInt8_28.io.deq.bits connect remapVecValids[25], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[25] node _T_4099 = eq(UInt<5>(0h1d), remapindex_25) when _T_4099 : connect remapVecData[25], Queue10_UInt8_29.io.deq.bits connect remapVecValids[25], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[25] node _T_4100 = eq(UInt<5>(0h1e), remapindex_25) when _T_4100 : connect remapVecData[25], Queue10_UInt8_30.io.deq.bits connect remapVecValids[25], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[25] node _T_4101 = eq(UInt<5>(0h1f), remapindex_25) when _T_4101 : connect remapVecData[25], Queue10_UInt8_31.io.deq.bits connect remapVecValids[25], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[25] node _remapindex_T_26 = add(UInt<5>(0h1a), read_start_index) node remapindex_26 = rem(_remapindex_T_26, UInt<6>(0h20)) node _T_4102 = eq(UInt<1>(0h0), remapindex_26) when _T_4102 : connect remapVecData[26], Queue10_UInt8.io.deq.bits connect remapVecValids[26], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[26] node _T_4103 = eq(UInt<1>(0h1), remapindex_26) when _T_4103 : connect remapVecData[26], Queue10_UInt8_1.io.deq.bits connect remapVecValids[26], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[26] node _T_4104 = eq(UInt<2>(0h2), remapindex_26) when _T_4104 : connect remapVecData[26], Queue10_UInt8_2.io.deq.bits connect remapVecValids[26], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[26] node _T_4105 = eq(UInt<2>(0h3), remapindex_26) when _T_4105 : connect remapVecData[26], Queue10_UInt8_3.io.deq.bits connect remapVecValids[26], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[26] node _T_4106 = eq(UInt<3>(0h4), remapindex_26) when _T_4106 : connect remapVecData[26], Queue10_UInt8_4.io.deq.bits connect remapVecValids[26], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[26] node _T_4107 = eq(UInt<3>(0h5), remapindex_26) when _T_4107 : connect remapVecData[26], Queue10_UInt8_5.io.deq.bits connect remapVecValids[26], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[26] node _T_4108 = eq(UInt<3>(0h6), remapindex_26) when _T_4108 : connect remapVecData[26], Queue10_UInt8_6.io.deq.bits connect remapVecValids[26], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[26] node _T_4109 = eq(UInt<3>(0h7), remapindex_26) when _T_4109 : connect remapVecData[26], Queue10_UInt8_7.io.deq.bits connect remapVecValids[26], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[26] node _T_4110 = eq(UInt<4>(0h8), remapindex_26) when _T_4110 : connect remapVecData[26], Queue10_UInt8_8.io.deq.bits connect remapVecValids[26], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[26] node _T_4111 = eq(UInt<4>(0h9), remapindex_26) when _T_4111 : connect remapVecData[26], Queue10_UInt8_9.io.deq.bits connect remapVecValids[26], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[26] node _T_4112 = eq(UInt<4>(0ha), remapindex_26) when _T_4112 : connect remapVecData[26], Queue10_UInt8_10.io.deq.bits connect remapVecValids[26], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[26] node _T_4113 = eq(UInt<4>(0hb), remapindex_26) when _T_4113 : connect remapVecData[26], Queue10_UInt8_11.io.deq.bits connect remapVecValids[26], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[26] node _T_4114 = eq(UInt<4>(0hc), remapindex_26) when _T_4114 : connect remapVecData[26], Queue10_UInt8_12.io.deq.bits connect remapVecValids[26], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[26] node _T_4115 = eq(UInt<4>(0hd), remapindex_26) when _T_4115 : connect remapVecData[26], Queue10_UInt8_13.io.deq.bits connect remapVecValids[26], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[26] node _T_4116 = eq(UInt<4>(0he), remapindex_26) when _T_4116 : connect remapVecData[26], Queue10_UInt8_14.io.deq.bits connect remapVecValids[26], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[26] node _T_4117 = eq(UInt<4>(0hf), remapindex_26) when _T_4117 : connect remapVecData[26], Queue10_UInt8_15.io.deq.bits connect remapVecValids[26], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[26] node _T_4118 = eq(UInt<5>(0h10), remapindex_26) when _T_4118 : connect remapVecData[26], Queue10_UInt8_16.io.deq.bits connect remapVecValids[26], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[26] node _T_4119 = eq(UInt<5>(0h11), remapindex_26) when _T_4119 : connect remapVecData[26], Queue10_UInt8_17.io.deq.bits connect remapVecValids[26], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[26] node _T_4120 = eq(UInt<5>(0h12), remapindex_26) when _T_4120 : connect remapVecData[26], Queue10_UInt8_18.io.deq.bits connect remapVecValids[26], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[26] node _T_4121 = eq(UInt<5>(0h13), remapindex_26) when _T_4121 : connect remapVecData[26], Queue10_UInt8_19.io.deq.bits connect remapVecValids[26], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[26] node _T_4122 = eq(UInt<5>(0h14), remapindex_26) when _T_4122 : connect remapVecData[26], Queue10_UInt8_20.io.deq.bits connect remapVecValids[26], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[26] node _T_4123 = eq(UInt<5>(0h15), remapindex_26) when _T_4123 : connect remapVecData[26], Queue10_UInt8_21.io.deq.bits connect remapVecValids[26], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[26] node _T_4124 = eq(UInt<5>(0h16), remapindex_26) when _T_4124 : connect remapVecData[26], Queue10_UInt8_22.io.deq.bits connect remapVecValids[26], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[26] node _T_4125 = eq(UInt<5>(0h17), remapindex_26) when _T_4125 : connect remapVecData[26], Queue10_UInt8_23.io.deq.bits connect remapVecValids[26], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[26] node _T_4126 = eq(UInt<5>(0h18), remapindex_26) when _T_4126 : connect remapVecData[26], Queue10_UInt8_24.io.deq.bits connect remapVecValids[26], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[26] node _T_4127 = eq(UInt<5>(0h19), remapindex_26) when _T_4127 : connect remapVecData[26], Queue10_UInt8_25.io.deq.bits connect remapVecValids[26], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[26] node _T_4128 = eq(UInt<5>(0h1a), remapindex_26) when _T_4128 : connect remapVecData[26], Queue10_UInt8_26.io.deq.bits connect remapVecValids[26], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[26] node _T_4129 = eq(UInt<5>(0h1b), remapindex_26) when _T_4129 : connect remapVecData[26], Queue10_UInt8_27.io.deq.bits connect remapVecValids[26], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[26] node _T_4130 = eq(UInt<5>(0h1c), remapindex_26) when _T_4130 : connect remapVecData[26], Queue10_UInt8_28.io.deq.bits connect remapVecValids[26], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[26] node _T_4131 = eq(UInt<5>(0h1d), remapindex_26) when _T_4131 : connect remapVecData[26], Queue10_UInt8_29.io.deq.bits connect remapVecValids[26], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[26] node _T_4132 = eq(UInt<5>(0h1e), remapindex_26) when _T_4132 : connect remapVecData[26], Queue10_UInt8_30.io.deq.bits connect remapVecValids[26], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[26] node _T_4133 = eq(UInt<5>(0h1f), remapindex_26) when _T_4133 : connect remapVecData[26], Queue10_UInt8_31.io.deq.bits connect remapVecValids[26], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[26] node _remapindex_T_27 = add(UInt<5>(0h1b), read_start_index) node remapindex_27 = rem(_remapindex_T_27, UInt<6>(0h20)) node _T_4134 = eq(UInt<1>(0h0), remapindex_27) when _T_4134 : connect remapVecData[27], Queue10_UInt8.io.deq.bits connect remapVecValids[27], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[27] node _T_4135 = eq(UInt<1>(0h1), remapindex_27) when _T_4135 : connect remapVecData[27], Queue10_UInt8_1.io.deq.bits connect remapVecValids[27], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[27] node _T_4136 = eq(UInt<2>(0h2), remapindex_27) when _T_4136 : connect remapVecData[27], Queue10_UInt8_2.io.deq.bits connect remapVecValids[27], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[27] node _T_4137 = eq(UInt<2>(0h3), remapindex_27) when _T_4137 : connect remapVecData[27], Queue10_UInt8_3.io.deq.bits connect remapVecValids[27], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[27] node _T_4138 = eq(UInt<3>(0h4), remapindex_27) when _T_4138 : connect remapVecData[27], Queue10_UInt8_4.io.deq.bits connect remapVecValids[27], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[27] node _T_4139 = eq(UInt<3>(0h5), remapindex_27) when _T_4139 : connect remapVecData[27], Queue10_UInt8_5.io.deq.bits connect remapVecValids[27], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[27] node _T_4140 = eq(UInt<3>(0h6), remapindex_27) when _T_4140 : connect remapVecData[27], Queue10_UInt8_6.io.deq.bits connect remapVecValids[27], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[27] node _T_4141 = eq(UInt<3>(0h7), remapindex_27) when _T_4141 : connect remapVecData[27], Queue10_UInt8_7.io.deq.bits connect remapVecValids[27], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[27] node _T_4142 = eq(UInt<4>(0h8), remapindex_27) when _T_4142 : connect remapVecData[27], Queue10_UInt8_8.io.deq.bits connect remapVecValids[27], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[27] node _T_4143 = eq(UInt<4>(0h9), remapindex_27) when _T_4143 : connect remapVecData[27], Queue10_UInt8_9.io.deq.bits connect remapVecValids[27], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[27] node _T_4144 = eq(UInt<4>(0ha), remapindex_27) when _T_4144 : connect remapVecData[27], Queue10_UInt8_10.io.deq.bits connect remapVecValids[27], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[27] node _T_4145 = eq(UInt<4>(0hb), remapindex_27) when _T_4145 : connect remapVecData[27], Queue10_UInt8_11.io.deq.bits connect remapVecValids[27], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[27] node _T_4146 = eq(UInt<4>(0hc), remapindex_27) when _T_4146 : connect remapVecData[27], Queue10_UInt8_12.io.deq.bits connect remapVecValids[27], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[27] node _T_4147 = eq(UInt<4>(0hd), remapindex_27) when _T_4147 : connect remapVecData[27], Queue10_UInt8_13.io.deq.bits connect remapVecValids[27], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[27] node _T_4148 = eq(UInt<4>(0he), remapindex_27) when _T_4148 : connect remapVecData[27], Queue10_UInt8_14.io.deq.bits connect remapVecValids[27], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[27] node _T_4149 = eq(UInt<4>(0hf), remapindex_27) when _T_4149 : connect remapVecData[27], Queue10_UInt8_15.io.deq.bits connect remapVecValids[27], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[27] node _T_4150 = eq(UInt<5>(0h10), remapindex_27) when _T_4150 : connect remapVecData[27], Queue10_UInt8_16.io.deq.bits connect remapVecValids[27], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[27] node _T_4151 = eq(UInt<5>(0h11), remapindex_27) when _T_4151 : connect remapVecData[27], Queue10_UInt8_17.io.deq.bits connect remapVecValids[27], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[27] node _T_4152 = eq(UInt<5>(0h12), remapindex_27) when _T_4152 : connect remapVecData[27], Queue10_UInt8_18.io.deq.bits connect remapVecValids[27], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[27] node _T_4153 = eq(UInt<5>(0h13), remapindex_27) when _T_4153 : connect remapVecData[27], Queue10_UInt8_19.io.deq.bits connect remapVecValids[27], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[27] node _T_4154 = eq(UInt<5>(0h14), remapindex_27) when _T_4154 : connect remapVecData[27], Queue10_UInt8_20.io.deq.bits connect remapVecValids[27], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[27] node _T_4155 = eq(UInt<5>(0h15), remapindex_27) when _T_4155 : connect remapVecData[27], Queue10_UInt8_21.io.deq.bits connect remapVecValids[27], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[27] node _T_4156 = eq(UInt<5>(0h16), remapindex_27) when _T_4156 : connect remapVecData[27], Queue10_UInt8_22.io.deq.bits connect remapVecValids[27], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[27] node _T_4157 = eq(UInt<5>(0h17), remapindex_27) when _T_4157 : connect remapVecData[27], Queue10_UInt8_23.io.deq.bits connect remapVecValids[27], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[27] node _T_4158 = eq(UInt<5>(0h18), remapindex_27) when _T_4158 : connect remapVecData[27], Queue10_UInt8_24.io.deq.bits connect remapVecValids[27], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[27] node _T_4159 = eq(UInt<5>(0h19), remapindex_27) when _T_4159 : connect remapVecData[27], Queue10_UInt8_25.io.deq.bits connect remapVecValids[27], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[27] node _T_4160 = eq(UInt<5>(0h1a), remapindex_27) when _T_4160 : connect remapVecData[27], Queue10_UInt8_26.io.deq.bits connect remapVecValids[27], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[27] node _T_4161 = eq(UInt<5>(0h1b), remapindex_27) when _T_4161 : connect remapVecData[27], Queue10_UInt8_27.io.deq.bits connect remapVecValids[27], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[27] node _T_4162 = eq(UInt<5>(0h1c), remapindex_27) when _T_4162 : connect remapVecData[27], Queue10_UInt8_28.io.deq.bits connect remapVecValids[27], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[27] node _T_4163 = eq(UInt<5>(0h1d), remapindex_27) when _T_4163 : connect remapVecData[27], Queue10_UInt8_29.io.deq.bits connect remapVecValids[27], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[27] node _T_4164 = eq(UInt<5>(0h1e), remapindex_27) when _T_4164 : connect remapVecData[27], Queue10_UInt8_30.io.deq.bits connect remapVecValids[27], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[27] node _T_4165 = eq(UInt<5>(0h1f), remapindex_27) when _T_4165 : connect remapVecData[27], Queue10_UInt8_31.io.deq.bits connect remapVecValids[27], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[27] node _remapindex_T_28 = add(UInt<5>(0h1c), read_start_index) node remapindex_28 = rem(_remapindex_T_28, UInt<6>(0h20)) node _T_4166 = eq(UInt<1>(0h0), remapindex_28) when _T_4166 : connect remapVecData[28], Queue10_UInt8.io.deq.bits connect remapVecValids[28], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[28] node _T_4167 = eq(UInt<1>(0h1), remapindex_28) when _T_4167 : connect remapVecData[28], Queue10_UInt8_1.io.deq.bits connect remapVecValids[28], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[28] node _T_4168 = eq(UInt<2>(0h2), remapindex_28) when _T_4168 : connect remapVecData[28], Queue10_UInt8_2.io.deq.bits connect remapVecValids[28], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[28] node _T_4169 = eq(UInt<2>(0h3), remapindex_28) when _T_4169 : connect remapVecData[28], Queue10_UInt8_3.io.deq.bits connect remapVecValids[28], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[28] node _T_4170 = eq(UInt<3>(0h4), remapindex_28) when _T_4170 : connect remapVecData[28], Queue10_UInt8_4.io.deq.bits connect remapVecValids[28], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[28] node _T_4171 = eq(UInt<3>(0h5), remapindex_28) when _T_4171 : connect remapVecData[28], Queue10_UInt8_5.io.deq.bits connect remapVecValids[28], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[28] node _T_4172 = eq(UInt<3>(0h6), remapindex_28) when _T_4172 : connect remapVecData[28], Queue10_UInt8_6.io.deq.bits connect remapVecValids[28], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[28] node _T_4173 = eq(UInt<3>(0h7), remapindex_28) when _T_4173 : connect remapVecData[28], Queue10_UInt8_7.io.deq.bits connect remapVecValids[28], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[28] node _T_4174 = eq(UInt<4>(0h8), remapindex_28) when _T_4174 : connect remapVecData[28], Queue10_UInt8_8.io.deq.bits connect remapVecValids[28], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[28] node _T_4175 = eq(UInt<4>(0h9), remapindex_28) when _T_4175 : connect remapVecData[28], Queue10_UInt8_9.io.deq.bits connect remapVecValids[28], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[28] node _T_4176 = eq(UInt<4>(0ha), remapindex_28) when _T_4176 : connect remapVecData[28], Queue10_UInt8_10.io.deq.bits connect remapVecValids[28], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[28] node _T_4177 = eq(UInt<4>(0hb), remapindex_28) when _T_4177 : connect remapVecData[28], Queue10_UInt8_11.io.deq.bits connect remapVecValids[28], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[28] node _T_4178 = eq(UInt<4>(0hc), remapindex_28) when _T_4178 : connect remapVecData[28], Queue10_UInt8_12.io.deq.bits connect remapVecValids[28], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[28] node _T_4179 = eq(UInt<4>(0hd), remapindex_28) when _T_4179 : connect remapVecData[28], Queue10_UInt8_13.io.deq.bits connect remapVecValids[28], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[28] node _T_4180 = eq(UInt<4>(0he), remapindex_28) when _T_4180 : connect remapVecData[28], Queue10_UInt8_14.io.deq.bits connect remapVecValids[28], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[28] node _T_4181 = eq(UInt<4>(0hf), remapindex_28) when _T_4181 : connect remapVecData[28], Queue10_UInt8_15.io.deq.bits connect remapVecValids[28], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[28] node _T_4182 = eq(UInt<5>(0h10), remapindex_28) when _T_4182 : connect remapVecData[28], Queue10_UInt8_16.io.deq.bits connect remapVecValids[28], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[28] node _T_4183 = eq(UInt<5>(0h11), remapindex_28) when _T_4183 : connect remapVecData[28], Queue10_UInt8_17.io.deq.bits connect remapVecValids[28], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[28] node _T_4184 = eq(UInt<5>(0h12), remapindex_28) when _T_4184 : connect remapVecData[28], Queue10_UInt8_18.io.deq.bits connect remapVecValids[28], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[28] node _T_4185 = eq(UInt<5>(0h13), remapindex_28) when _T_4185 : connect remapVecData[28], Queue10_UInt8_19.io.deq.bits connect remapVecValids[28], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[28] node _T_4186 = eq(UInt<5>(0h14), remapindex_28) when _T_4186 : connect remapVecData[28], Queue10_UInt8_20.io.deq.bits connect remapVecValids[28], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[28] node _T_4187 = eq(UInt<5>(0h15), remapindex_28) when _T_4187 : connect remapVecData[28], Queue10_UInt8_21.io.deq.bits connect remapVecValids[28], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[28] node _T_4188 = eq(UInt<5>(0h16), remapindex_28) when _T_4188 : connect remapVecData[28], Queue10_UInt8_22.io.deq.bits connect remapVecValids[28], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[28] node _T_4189 = eq(UInt<5>(0h17), remapindex_28) when _T_4189 : connect remapVecData[28], Queue10_UInt8_23.io.deq.bits connect remapVecValids[28], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[28] node _T_4190 = eq(UInt<5>(0h18), remapindex_28) when _T_4190 : connect remapVecData[28], Queue10_UInt8_24.io.deq.bits connect remapVecValids[28], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[28] node _T_4191 = eq(UInt<5>(0h19), remapindex_28) when _T_4191 : connect remapVecData[28], Queue10_UInt8_25.io.deq.bits connect remapVecValids[28], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[28] node _T_4192 = eq(UInt<5>(0h1a), remapindex_28) when _T_4192 : connect remapVecData[28], Queue10_UInt8_26.io.deq.bits connect remapVecValids[28], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[28] node _T_4193 = eq(UInt<5>(0h1b), remapindex_28) when _T_4193 : connect remapVecData[28], Queue10_UInt8_27.io.deq.bits connect remapVecValids[28], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[28] node _T_4194 = eq(UInt<5>(0h1c), remapindex_28) when _T_4194 : connect remapVecData[28], Queue10_UInt8_28.io.deq.bits connect remapVecValids[28], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[28] node _T_4195 = eq(UInt<5>(0h1d), remapindex_28) when _T_4195 : connect remapVecData[28], Queue10_UInt8_29.io.deq.bits connect remapVecValids[28], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[28] node _T_4196 = eq(UInt<5>(0h1e), remapindex_28) when _T_4196 : connect remapVecData[28], Queue10_UInt8_30.io.deq.bits connect remapVecValids[28], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[28] node _T_4197 = eq(UInt<5>(0h1f), remapindex_28) when _T_4197 : connect remapVecData[28], Queue10_UInt8_31.io.deq.bits connect remapVecValids[28], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[28] node _remapindex_T_29 = add(UInt<5>(0h1d), read_start_index) node remapindex_29 = rem(_remapindex_T_29, UInt<6>(0h20)) node _T_4198 = eq(UInt<1>(0h0), remapindex_29) when _T_4198 : connect remapVecData[29], Queue10_UInt8.io.deq.bits connect remapVecValids[29], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[29] node _T_4199 = eq(UInt<1>(0h1), remapindex_29) when _T_4199 : connect remapVecData[29], Queue10_UInt8_1.io.deq.bits connect remapVecValids[29], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[29] node _T_4200 = eq(UInt<2>(0h2), remapindex_29) when _T_4200 : connect remapVecData[29], Queue10_UInt8_2.io.deq.bits connect remapVecValids[29], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[29] node _T_4201 = eq(UInt<2>(0h3), remapindex_29) when _T_4201 : connect remapVecData[29], Queue10_UInt8_3.io.deq.bits connect remapVecValids[29], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[29] node _T_4202 = eq(UInt<3>(0h4), remapindex_29) when _T_4202 : connect remapVecData[29], Queue10_UInt8_4.io.deq.bits connect remapVecValids[29], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[29] node _T_4203 = eq(UInt<3>(0h5), remapindex_29) when _T_4203 : connect remapVecData[29], Queue10_UInt8_5.io.deq.bits connect remapVecValids[29], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[29] node _T_4204 = eq(UInt<3>(0h6), remapindex_29) when _T_4204 : connect remapVecData[29], Queue10_UInt8_6.io.deq.bits connect remapVecValids[29], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[29] node _T_4205 = eq(UInt<3>(0h7), remapindex_29) when _T_4205 : connect remapVecData[29], Queue10_UInt8_7.io.deq.bits connect remapVecValids[29], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[29] node _T_4206 = eq(UInt<4>(0h8), remapindex_29) when _T_4206 : connect remapVecData[29], Queue10_UInt8_8.io.deq.bits connect remapVecValids[29], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[29] node _T_4207 = eq(UInt<4>(0h9), remapindex_29) when _T_4207 : connect remapVecData[29], Queue10_UInt8_9.io.deq.bits connect remapVecValids[29], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[29] node _T_4208 = eq(UInt<4>(0ha), remapindex_29) when _T_4208 : connect remapVecData[29], Queue10_UInt8_10.io.deq.bits connect remapVecValids[29], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[29] node _T_4209 = eq(UInt<4>(0hb), remapindex_29) when _T_4209 : connect remapVecData[29], Queue10_UInt8_11.io.deq.bits connect remapVecValids[29], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[29] node _T_4210 = eq(UInt<4>(0hc), remapindex_29) when _T_4210 : connect remapVecData[29], Queue10_UInt8_12.io.deq.bits connect remapVecValids[29], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[29] node _T_4211 = eq(UInt<4>(0hd), remapindex_29) when _T_4211 : connect remapVecData[29], Queue10_UInt8_13.io.deq.bits connect remapVecValids[29], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[29] node _T_4212 = eq(UInt<4>(0he), remapindex_29) when _T_4212 : connect remapVecData[29], Queue10_UInt8_14.io.deq.bits connect remapVecValids[29], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[29] node _T_4213 = eq(UInt<4>(0hf), remapindex_29) when _T_4213 : connect remapVecData[29], Queue10_UInt8_15.io.deq.bits connect remapVecValids[29], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[29] node _T_4214 = eq(UInt<5>(0h10), remapindex_29) when _T_4214 : connect remapVecData[29], Queue10_UInt8_16.io.deq.bits connect remapVecValids[29], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[29] node _T_4215 = eq(UInt<5>(0h11), remapindex_29) when _T_4215 : connect remapVecData[29], Queue10_UInt8_17.io.deq.bits connect remapVecValids[29], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[29] node _T_4216 = eq(UInt<5>(0h12), remapindex_29) when _T_4216 : connect remapVecData[29], Queue10_UInt8_18.io.deq.bits connect remapVecValids[29], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[29] node _T_4217 = eq(UInt<5>(0h13), remapindex_29) when _T_4217 : connect remapVecData[29], Queue10_UInt8_19.io.deq.bits connect remapVecValids[29], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[29] node _T_4218 = eq(UInt<5>(0h14), remapindex_29) when _T_4218 : connect remapVecData[29], Queue10_UInt8_20.io.deq.bits connect remapVecValids[29], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[29] node _T_4219 = eq(UInt<5>(0h15), remapindex_29) when _T_4219 : connect remapVecData[29], Queue10_UInt8_21.io.deq.bits connect remapVecValids[29], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[29] node _T_4220 = eq(UInt<5>(0h16), remapindex_29) when _T_4220 : connect remapVecData[29], Queue10_UInt8_22.io.deq.bits connect remapVecValids[29], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[29] node _T_4221 = eq(UInt<5>(0h17), remapindex_29) when _T_4221 : connect remapVecData[29], Queue10_UInt8_23.io.deq.bits connect remapVecValids[29], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[29] node _T_4222 = eq(UInt<5>(0h18), remapindex_29) when _T_4222 : connect remapVecData[29], Queue10_UInt8_24.io.deq.bits connect remapVecValids[29], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[29] node _T_4223 = eq(UInt<5>(0h19), remapindex_29) when _T_4223 : connect remapVecData[29], Queue10_UInt8_25.io.deq.bits connect remapVecValids[29], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[29] node _T_4224 = eq(UInt<5>(0h1a), remapindex_29) when _T_4224 : connect remapVecData[29], Queue10_UInt8_26.io.deq.bits connect remapVecValids[29], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[29] node _T_4225 = eq(UInt<5>(0h1b), remapindex_29) when _T_4225 : connect remapVecData[29], Queue10_UInt8_27.io.deq.bits connect remapVecValids[29], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[29] node _T_4226 = eq(UInt<5>(0h1c), remapindex_29) when _T_4226 : connect remapVecData[29], Queue10_UInt8_28.io.deq.bits connect remapVecValids[29], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[29] node _T_4227 = eq(UInt<5>(0h1d), remapindex_29) when _T_4227 : connect remapVecData[29], Queue10_UInt8_29.io.deq.bits connect remapVecValids[29], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[29] node _T_4228 = eq(UInt<5>(0h1e), remapindex_29) when _T_4228 : connect remapVecData[29], Queue10_UInt8_30.io.deq.bits connect remapVecValids[29], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[29] node _T_4229 = eq(UInt<5>(0h1f), remapindex_29) when _T_4229 : connect remapVecData[29], Queue10_UInt8_31.io.deq.bits connect remapVecValids[29], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[29] node _remapindex_T_30 = add(UInt<5>(0h1e), read_start_index) node remapindex_30 = rem(_remapindex_T_30, UInt<6>(0h20)) node _T_4230 = eq(UInt<1>(0h0), remapindex_30) when _T_4230 : connect remapVecData[30], Queue10_UInt8.io.deq.bits connect remapVecValids[30], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[30] node _T_4231 = eq(UInt<1>(0h1), remapindex_30) when _T_4231 : connect remapVecData[30], Queue10_UInt8_1.io.deq.bits connect remapVecValids[30], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[30] node _T_4232 = eq(UInt<2>(0h2), remapindex_30) when _T_4232 : connect remapVecData[30], Queue10_UInt8_2.io.deq.bits connect remapVecValids[30], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[30] node _T_4233 = eq(UInt<2>(0h3), remapindex_30) when _T_4233 : connect remapVecData[30], Queue10_UInt8_3.io.deq.bits connect remapVecValids[30], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[30] node _T_4234 = eq(UInt<3>(0h4), remapindex_30) when _T_4234 : connect remapVecData[30], Queue10_UInt8_4.io.deq.bits connect remapVecValids[30], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[30] node _T_4235 = eq(UInt<3>(0h5), remapindex_30) when _T_4235 : connect remapVecData[30], Queue10_UInt8_5.io.deq.bits connect remapVecValids[30], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[30] node _T_4236 = eq(UInt<3>(0h6), remapindex_30) when _T_4236 : connect remapVecData[30], Queue10_UInt8_6.io.deq.bits connect remapVecValids[30], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[30] node _T_4237 = eq(UInt<3>(0h7), remapindex_30) when _T_4237 : connect remapVecData[30], Queue10_UInt8_7.io.deq.bits connect remapVecValids[30], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[30] node _T_4238 = eq(UInt<4>(0h8), remapindex_30) when _T_4238 : connect remapVecData[30], Queue10_UInt8_8.io.deq.bits connect remapVecValids[30], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[30] node _T_4239 = eq(UInt<4>(0h9), remapindex_30) when _T_4239 : connect remapVecData[30], Queue10_UInt8_9.io.deq.bits connect remapVecValids[30], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[30] node _T_4240 = eq(UInt<4>(0ha), remapindex_30) when _T_4240 : connect remapVecData[30], Queue10_UInt8_10.io.deq.bits connect remapVecValids[30], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[30] node _T_4241 = eq(UInt<4>(0hb), remapindex_30) when _T_4241 : connect remapVecData[30], Queue10_UInt8_11.io.deq.bits connect remapVecValids[30], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[30] node _T_4242 = eq(UInt<4>(0hc), remapindex_30) when _T_4242 : connect remapVecData[30], Queue10_UInt8_12.io.deq.bits connect remapVecValids[30], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[30] node _T_4243 = eq(UInt<4>(0hd), remapindex_30) when _T_4243 : connect remapVecData[30], Queue10_UInt8_13.io.deq.bits connect remapVecValids[30], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[30] node _T_4244 = eq(UInt<4>(0he), remapindex_30) when _T_4244 : connect remapVecData[30], Queue10_UInt8_14.io.deq.bits connect remapVecValids[30], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[30] node _T_4245 = eq(UInt<4>(0hf), remapindex_30) when _T_4245 : connect remapVecData[30], Queue10_UInt8_15.io.deq.bits connect remapVecValids[30], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[30] node _T_4246 = eq(UInt<5>(0h10), remapindex_30) when _T_4246 : connect remapVecData[30], Queue10_UInt8_16.io.deq.bits connect remapVecValids[30], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[30] node _T_4247 = eq(UInt<5>(0h11), remapindex_30) when _T_4247 : connect remapVecData[30], Queue10_UInt8_17.io.deq.bits connect remapVecValids[30], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[30] node _T_4248 = eq(UInt<5>(0h12), remapindex_30) when _T_4248 : connect remapVecData[30], Queue10_UInt8_18.io.deq.bits connect remapVecValids[30], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[30] node _T_4249 = eq(UInt<5>(0h13), remapindex_30) when _T_4249 : connect remapVecData[30], Queue10_UInt8_19.io.deq.bits connect remapVecValids[30], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[30] node _T_4250 = eq(UInt<5>(0h14), remapindex_30) when _T_4250 : connect remapVecData[30], Queue10_UInt8_20.io.deq.bits connect remapVecValids[30], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[30] node _T_4251 = eq(UInt<5>(0h15), remapindex_30) when _T_4251 : connect remapVecData[30], Queue10_UInt8_21.io.deq.bits connect remapVecValids[30], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[30] node _T_4252 = eq(UInt<5>(0h16), remapindex_30) when _T_4252 : connect remapVecData[30], Queue10_UInt8_22.io.deq.bits connect remapVecValids[30], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[30] node _T_4253 = eq(UInt<5>(0h17), remapindex_30) when _T_4253 : connect remapVecData[30], Queue10_UInt8_23.io.deq.bits connect remapVecValids[30], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[30] node _T_4254 = eq(UInt<5>(0h18), remapindex_30) when _T_4254 : connect remapVecData[30], Queue10_UInt8_24.io.deq.bits connect remapVecValids[30], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[30] node _T_4255 = eq(UInt<5>(0h19), remapindex_30) when _T_4255 : connect remapVecData[30], Queue10_UInt8_25.io.deq.bits connect remapVecValids[30], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[30] node _T_4256 = eq(UInt<5>(0h1a), remapindex_30) when _T_4256 : connect remapVecData[30], Queue10_UInt8_26.io.deq.bits connect remapVecValids[30], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[30] node _T_4257 = eq(UInt<5>(0h1b), remapindex_30) when _T_4257 : connect remapVecData[30], Queue10_UInt8_27.io.deq.bits connect remapVecValids[30], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[30] node _T_4258 = eq(UInt<5>(0h1c), remapindex_30) when _T_4258 : connect remapVecData[30], Queue10_UInt8_28.io.deq.bits connect remapVecValids[30], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[30] node _T_4259 = eq(UInt<5>(0h1d), remapindex_30) when _T_4259 : connect remapVecData[30], Queue10_UInt8_29.io.deq.bits connect remapVecValids[30], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[30] node _T_4260 = eq(UInt<5>(0h1e), remapindex_30) when _T_4260 : connect remapVecData[30], Queue10_UInt8_30.io.deq.bits connect remapVecValids[30], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[30] node _T_4261 = eq(UInt<5>(0h1f), remapindex_30) when _T_4261 : connect remapVecData[30], Queue10_UInt8_31.io.deq.bits connect remapVecValids[30], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[30] node _remapindex_T_31 = add(UInt<5>(0h1f), read_start_index) node remapindex_31 = rem(_remapindex_T_31, UInt<6>(0h20)) node _T_4262 = eq(UInt<1>(0h0), remapindex_31) when _T_4262 : connect remapVecData[31], Queue10_UInt8.io.deq.bits connect remapVecValids[31], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[31] node _T_4263 = eq(UInt<1>(0h1), remapindex_31) when _T_4263 : connect remapVecData[31], Queue10_UInt8_1.io.deq.bits connect remapVecValids[31], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[31] node _T_4264 = eq(UInt<2>(0h2), remapindex_31) when _T_4264 : connect remapVecData[31], Queue10_UInt8_2.io.deq.bits connect remapVecValids[31], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[31] node _T_4265 = eq(UInt<2>(0h3), remapindex_31) when _T_4265 : connect remapVecData[31], Queue10_UInt8_3.io.deq.bits connect remapVecValids[31], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[31] node _T_4266 = eq(UInt<3>(0h4), remapindex_31) when _T_4266 : connect remapVecData[31], Queue10_UInt8_4.io.deq.bits connect remapVecValids[31], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[31] node _T_4267 = eq(UInt<3>(0h5), remapindex_31) when _T_4267 : connect remapVecData[31], Queue10_UInt8_5.io.deq.bits connect remapVecValids[31], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[31] node _T_4268 = eq(UInt<3>(0h6), remapindex_31) when _T_4268 : connect remapVecData[31], Queue10_UInt8_6.io.deq.bits connect remapVecValids[31], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[31] node _T_4269 = eq(UInt<3>(0h7), remapindex_31) when _T_4269 : connect remapVecData[31], Queue10_UInt8_7.io.deq.bits connect remapVecValids[31], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[31] node _T_4270 = eq(UInt<4>(0h8), remapindex_31) when _T_4270 : connect remapVecData[31], Queue10_UInt8_8.io.deq.bits connect remapVecValids[31], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[31] node _T_4271 = eq(UInt<4>(0h9), remapindex_31) when _T_4271 : connect remapVecData[31], Queue10_UInt8_9.io.deq.bits connect remapVecValids[31], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[31] node _T_4272 = eq(UInt<4>(0ha), remapindex_31) when _T_4272 : connect remapVecData[31], Queue10_UInt8_10.io.deq.bits connect remapVecValids[31], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[31] node _T_4273 = eq(UInt<4>(0hb), remapindex_31) when _T_4273 : connect remapVecData[31], Queue10_UInt8_11.io.deq.bits connect remapVecValids[31], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[31] node _T_4274 = eq(UInt<4>(0hc), remapindex_31) when _T_4274 : connect remapVecData[31], Queue10_UInt8_12.io.deq.bits connect remapVecValids[31], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[31] node _T_4275 = eq(UInt<4>(0hd), remapindex_31) when _T_4275 : connect remapVecData[31], Queue10_UInt8_13.io.deq.bits connect remapVecValids[31], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[31] node _T_4276 = eq(UInt<4>(0he), remapindex_31) when _T_4276 : connect remapVecData[31], Queue10_UInt8_14.io.deq.bits connect remapVecValids[31], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[31] node _T_4277 = eq(UInt<4>(0hf), remapindex_31) when _T_4277 : connect remapVecData[31], Queue10_UInt8_15.io.deq.bits connect remapVecValids[31], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[31] node _T_4278 = eq(UInt<5>(0h10), remapindex_31) when _T_4278 : connect remapVecData[31], Queue10_UInt8_16.io.deq.bits connect remapVecValids[31], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[31] node _T_4279 = eq(UInt<5>(0h11), remapindex_31) when _T_4279 : connect remapVecData[31], Queue10_UInt8_17.io.deq.bits connect remapVecValids[31], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[31] node _T_4280 = eq(UInt<5>(0h12), remapindex_31) when _T_4280 : connect remapVecData[31], Queue10_UInt8_18.io.deq.bits connect remapVecValids[31], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[31] node _T_4281 = eq(UInt<5>(0h13), remapindex_31) when _T_4281 : connect remapVecData[31], Queue10_UInt8_19.io.deq.bits connect remapVecValids[31], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[31] node _T_4282 = eq(UInt<5>(0h14), remapindex_31) when _T_4282 : connect remapVecData[31], Queue10_UInt8_20.io.deq.bits connect remapVecValids[31], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[31] node _T_4283 = eq(UInt<5>(0h15), remapindex_31) when _T_4283 : connect remapVecData[31], Queue10_UInt8_21.io.deq.bits connect remapVecValids[31], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[31] node _T_4284 = eq(UInt<5>(0h16), remapindex_31) when _T_4284 : connect remapVecData[31], Queue10_UInt8_22.io.deq.bits connect remapVecValids[31], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[31] node _T_4285 = eq(UInt<5>(0h17), remapindex_31) when _T_4285 : connect remapVecData[31], Queue10_UInt8_23.io.deq.bits connect remapVecValids[31], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[31] node _T_4286 = eq(UInt<5>(0h18), remapindex_31) when _T_4286 : connect remapVecData[31], Queue10_UInt8_24.io.deq.bits connect remapVecValids[31], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[31] node _T_4287 = eq(UInt<5>(0h19), remapindex_31) when _T_4287 : connect remapVecData[31], Queue10_UInt8_25.io.deq.bits connect remapVecValids[31], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[31] node _T_4288 = eq(UInt<5>(0h1a), remapindex_31) when _T_4288 : connect remapVecData[31], Queue10_UInt8_26.io.deq.bits connect remapVecValids[31], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[31] node _T_4289 = eq(UInt<5>(0h1b), remapindex_31) when _T_4289 : connect remapVecData[31], Queue10_UInt8_27.io.deq.bits connect remapVecValids[31], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[31] node _T_4290 = eq(UInt<5>(0h1c), remapindex_31) when _T_4290 : connect remapVecData[31], Queue10_UInt8_28.io.deq.bits connect remapVecValids[31], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[31] node _T_4291 = eq(UInt<5>(0h1d), remapindex_31) when _T_4291 : connect remapVecData[31], Queue10_UInt8_29.io.deq.bits connect remapVecValids[31], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[31] node _T_4292 = eq(UInt<5>(0h1e), remapindex_31) when _T_4292 : connect remapVecData[31], Queue10_UInt8_30.io.deq.bits connect remapVecValids[31], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[31] node _T_4293 = eq(UInt<5>(0h1f), remapindex_31) when _T_4293 : connect remapVecData[31], Queue10_UInt8_31.io.deq.bits connect remapVecValids[31], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[31] node io_consumer_output_data_lo_lo_lo_lo = cat(remapVecData[1], remapVecData[0]) node io_consumer_output_data_lo_lo_lo_hi = cat(remapVecData[3], remapVecData[2]) node io_consumer_output_data_lo_lo_lo = cat(io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo) node io_consumer_output_data_lo_lo_hi_lo = cat(remapVecData[5], remapVecData[4]) node io_consumer_output_data_lo_lo_hi_hi = cat(remapVecData[7], remapVecData[6]) node io_consumer_output_data_lo_lo_hi = cat(io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo) node io_consumer_output_data_lo_lo = cat(io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo) node io_consumer_output_data_lo_hi_lo_lo = cat(remapVecData[9], remapVecData[8]) node io_consumer_output_data_lo_hi_lo_hi = cat(remapVecData[11], remapVecData[10]) node io_consumer_output_data_lo_hi_lo = cat(io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo) node io_consumer_output_data_lo_hi_hi_lo = cat(remapVecData[13], remapVecData[12]) node io_consumer_output_data_lo_hi_hi_hi = cat(remapVecData[15], remapVecData[14]) node io_consumer_output_data_lo_hi_hi = cat(io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo) node io_consumer_output_data_lo_hi = cat(io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo) node io_consumer_output_data_lo = cat(io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo) node io_consumer_output_data_hi_lo_lo_lo = cat(remapVecData[17], remapVecData[16]) node io_consumer_output_data_hi_lo_lo_hi = cat(remapVecData[19], remapVecData[18]) node io_consumer_output_data_hi_lo_lo = cat(io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo) node io_consumer_output_data_hi_lo_hi_lo = cat(remapVecData[21], remapVecData[20]) node io_consumer_output_data_hi_lo_hi_hi = cat(remapVecData[23], remapVecData[22]) node io_consumer_output_data_hi_lo_hi = cat(io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo) node io_consumer_output_data_hi_lo = cat(io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo) node io_consumer_output_data_hi_hi_lo_lo = cat(remapVecData[25], remapVecData[24]) node io_consumer_output_data_hi_hi_lo_hi = cat(remapVecData[27], remapVecData[26]) node io_consumer_output_data_hi_hi_lo = cat(io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo) node io_consumer_output_data_hi_hi_hi_lo = cat(remapVecData[29], remapVecData[28]) node io_consumer_output_data_hi_hi_hi_hi = cat(remapVecData[31], remapVecData[30]) node io_consumer_output_data_hi_hi_hi = cat(io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo) node io_consumer_output_data_hi_hi = cat(io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo) node io_consumer_output_data_hi = cat(io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo) node _io_consumer_output_data_T = cat(io_consumer_output_data_hi, io_consumer_output_data_lo) connect io.consumer.output_data, _io_consumer_output_data_T node _count_valids_T = add(remapVecValids[0], remapVecValids[1]) node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2]) node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3]) node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4]) node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5]) node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6]) node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7]) node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8]) node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9]) node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10]) node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11]) node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12]) node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13]) node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14]) node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15]) node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16]) node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17]) node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18]) node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19]) node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20]) node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21]) node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22]) node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23]) node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24]) node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25]) node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26]) node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27]) node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28]) node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29]) node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30]) node count_valids = add(_count_valids_T_29, remapVecValids[31]) node enough_data = neq(count_valids, UInt<1>(0h0)) connect io.consumer.available_output_bytes, count_valids connect io.consumer.output_last_chunk, UInt<1>(0h0) node _T_4294 = and(io.consumer.output_ready, enough_data) when _T_4294 : regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_4295 = asUInt(reset) node _T_4296 = eq(_T_4295, UInt<1>(0h0)) when _T_4296 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_66 node _T_4297 = asUInt(reset) node _T_4298 = eq(_T_4297, UInt<1>(0h0)) when _T_4298 : printf(clock, UInt<1>(0h1), "lrb READ: bytesread %d\n", io.consumer.user_consumed_bytes) : printf_67 regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_4299 = asUInt(reset) node _T_4300 = eq(_T_4299, UInt<1>(0h0)) when _T_4300 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_68 node _T_4301 = asUInt(reset) node _T_4302 = eq(_T_4301, UInt<1>(0h0)) when _T_4302 : printf(clock, UInt<1>(0h1), "lrb read data: 0x%x\n", io.consumer.output_data) : printf_69 connect io.consumer.output_valid, enough_data node _remapVecReadys_0_T = lt(UInt<1>(0h0), io.consumer.user_consumed_bytes) node _remapVecReadys_0_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_1) connect remapVecReadys[0], _remapVecReadys_0_T_2 node _remapVecReadys_1_T = lt(UInt<1>(0h1), io.consumer.user_consumed_bytes) node _remapVecReadys_1_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_1) connect remapVecReadys[1], _remapVecReadys_1_T_2 node _remapVecReadys_2_T = lt(UInt<2>(0h2), io.consumer.user_consumed_bytes) node _remapVecReadys_2_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_1) connect remapVecReadys[2], _remapVecReadys_2_T_2 node _remapVecReadys_3_T = lt(UInt<2>(0h3), io.consumer.user_consumed_bytes) node _remapVecReadys_3_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_1) connect remapVecReadys[3], _remapVecReadys_3_T_2 node _remapVecReadys_4_T = lt(UInt<3>(0h4), io.consumer.user_consumed_bytes) node _remapVecReadys_4_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_1) connect remapVecReadys[4], _remapVecReadys_4_T_2 node _remapVecReadys_5_T = lt(UInt<3>(0h5), io.consumer.user_consumed_bytes) node _remapVecReadys_5_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_1) connect remapVecReadys[5], _remapVecReadys_5_T_2 node _remapVecReadys_6_T = lt(UInt<3>(0h6), io.consumer.user_consumed_bytes) node _remapVecReadys_6_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_1) connect remapVecReadys[6], _remapVecReadys_6_T_2 node _remapVecReadys_7_T = lt(UInt<3>(0h7), io.consumer.user_consumed_bytes) node _remapVecReadys_7_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_1) connect remapVecReadys[7], _remapVecReadys_7_T_2 node _remapVecReadys_8_T = lt(UInt<4>(0h8), io.consumer.user_consumed_bytes) node _remapVecReadys_8_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_1) connect remapVecReadys[8], _remapVecReadys_8_T_2 node _remapVecReadys_9_T = lt(UInt<4>(0h9), io.consumer.user_consumed_bytes) node _remapVecReadys_9_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_1) connect remapVecReadys[9], _remapVecReadys_9_T_2 node _remapVecReadys_10_T = lt(UInt<4>(0ha), io.consumer.user_consumed_bytes) node _remapVecReadys_10_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_1) connect remapVecReadys[10], _remapVecReadys_10_T_2 node _remapVecReadys_11_T = lt(UInt<4>(0hb), io.consumer.user_consumed_bytes) node _remapVecReadys_11_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_1) connect remapVecReadys[11], _remapVecReadys_11_T_2 node _remapVecReadys_12_T = lt(UInt<4>(0hc), io.consumer.user_consumed_bytes) node _remapVecReadys_12_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_1) connect remapVecReadys[12], _remapVecReadys_12_T_2 node _remapVecReadys_13_T = lt(UInt<4>(0hd), io.consumer.user_consumed_bytes) node _remapVecReadys_13_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_1) connect remapVecReadys[13], _remapVecReadys_13_T_2 node _remapVecReadys_14_T = lt(UInt<4>(0he), io.consumer.user_consumed_bytes) node _remapVecReadys_14_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_1) connect remapVecReadys[14], _remapVecReadys_14_T_2 node _remapVecReadys_15_T = lt(UInt<4>(0hf), io.consumer.user_consumed_bytes) node _remapVecReadys_15_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_1) connect remapVecReadys[15], _remapVecReadys_15_T_2 node _remapVecReadys_16_T = lt(UInt<5>(0h10), io.consumer.user_consumed_bytes) node _remapVecReadys_16_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_1) connect remapVecReadys[16], _remapVecReadys_16_T_2 node _remapVecReadys_17_T = lt(UInt<5>(0h11), io.consumer.user_consumed_bytes) node _remapVecReadys_17_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_1) connect remapVecReadys[17], _remapVecReadys_17_T_2 node _remapVecReadys_18_T = lt(UInt<5>(0h12), io.consumer.user_consumed_bytes) node _remapVecReadys_18_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_1) connect remapVecReadys[18], _remapVecReadys_18_T_2 node _remapVecReadys_19_T = lt(UInt<5>(0h13), io.consumer.user_consumed_bytes) node _remapVecReadys_19_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_1) connect remapVecReadys[19], _remapVecReadys_19_T_2 node _remapVecReadys_20_T = lt(UInt<5>(0h14), io.consumer.user_consumed_bytes) node _remapVecReadys_20_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_1) connect remapVecReadys[20], _remapVecReadys_20_T_2 node _remapVecReadys_21_T = lt(UInt<5>(0h15), io.consumer.user_consumed_bytes) node _remapVecReadys_21_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_1) connect remapVecReadys[21], _remapVecReadys_21_T_2 node _remapVecReadys_22_T = lt(UInt<5>(0h16), io.consumer.user_consumed_bytes) node _remapVecReadys_22_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_1) connect remapVecReadys[22], _remapVecReadys_22_T_2 node _remapVecReadys_23_T = lt(UInt<5>(0h17), io.consumer.user_consumed_bytes) node _remapVecReadys_23_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_1) connect remapVecReadys[23], _remapVecReadys_23_T_2 node _remapVecReadys_24_T = lt(UInt<5>(0h18), io.consumer.user_consumed_bytes) node _remapVecReadys_24_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_1) connect remapVecReadys[24], _remapVecReadys_24_T_2 node _remapVecReadys_25_T = lt(UInt<5>(0h19), io.consumer.user_consumed_bytes) node _remapVecReadys_25_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_1) connect remapVecReadys[25], _remapVecReadys_25_T_2 node _remapVecReadys_26_T = lt(UInt<5>(0h1a), io.consumer.user_consumed_bytes) node _remapVecReadys_26_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_1) connect remapVecReadys[26], _remapVecReadys_26_T_2 node _remapVecReadys_27_T = lt(UInt<5>(0h1b), io.consumer.user_consumed_bytes) node _remapVecReadys_27_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_1) connect remapVecReadys[27], _remapVecReadys_27_T_2 node _remapVecReadys_28_T = lt(UInt<5>(0h1c), io.consumer.user_consumed_bytes) node _remapVecReadys_28_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_1) connect remapVecReadys[28], _remapVecReadys_28_T_2 node _remapVecReadys_29_T = lt(UInt<5>(0h1d), io.consumer.user_consumed_bytes) node _remapVecReadys_29_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_1) connect remapVecReadys[29], _remapVecReadys_29_T_2 node _remapVecReadys_30_T = lt(UInt<5>(0h1e), io.consumer.user_consumed_bytes) node _remapVecReadys_30_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_1) connect remapVecReadys[30], _remapVecReadys_30_T_2 node _remapVecReadys_31_T = lt(UInt<5>(0h1f), io.consumer.user_consumed_bytes) node _remapVecReadys_31_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_1) connect remapVecReadys[31], _remapVecReadys_31_T_2 node _T_4303 = and(io.consumer.output_ready, enough_data) when _T_4303 : node _read_start_index_T = add(read_start_index, io.consumer.user_consumed_bytes) node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20)) connect read_start_index, _read_start_index_T_1	module ZstdCompressorLitRotBuf_2( // @[ZstdLitRotBuf.scala:152:7] input clock, // @[ZstdLitRotBuf.scala:152:7] input reset, // @[ZstdLitRotBuf.scala:152:7] output io_memwrites_in_ready, // @[ZstdLitRotBuf.scala:153:14] input io_memwrites_in_valid, // @[ZstdLitRotBuf.scala:153:14] input [255:0] io_memwrites_in_bits_data, // @[ZstdLitRotBuf.scala:153:14] input io_memwrites_in_bits_end_of_message, // @[ZstdLitRotBuf.scala:153:14] input [5:0] io_consumer_user_consumed_bytes, // @[ZstdLitRotBuf.scala:153:14] output [5:0] io_consumer_available_output_bytes, // @[ZstdLitRotBuf.scala:153:14] output io_consumer_output_valid, // @[ZstdLitRotBuf.scala:153:14] input io_consumer_output_ready, // @[ZstdLitRotBuf.scala:153:14] output [255:0] io_consumer_output_data // @[ZstdLitRotBuf.scala:153:14] ); wire _Queue10_UInt8_31_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_31_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_31_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_30_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_30_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_30_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_29_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_29_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_29_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_28_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_28_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_28_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_27_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_27_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_27_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_26_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_26_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_26_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_25_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_25_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_25_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_24_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_24_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_24_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_23_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_23_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_23_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_22_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_22_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_22_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_21_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_21_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_21_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_20_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_20_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_20_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_19_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_19_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_19_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_18_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_18_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_18_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_17_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_17_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_17_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_16_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_16_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_16_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_15_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_15_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_15_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_14_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_14_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_14_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_13_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_13_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_13_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_12_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_12_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_12_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_11_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_11_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_11_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_10_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_10_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_10_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_9_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_9_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_9_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_8_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_8_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_7_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_7_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_7_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_6_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_6_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_6_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_5_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_5_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_5_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_4_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_4_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_4_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_3_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_3_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_3_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_2_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_2_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_2_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_1_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_1_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_1_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _incoming_writes_Q_io_deq_valid; // @[ZstdLitRotBuf.scala:158:33] wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[ZstdLitRotBuf.scala:158:33] wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[ZstdLitRotBuf.scala:158:33] wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdLitRotBuf.scala:158:33] wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[ZstdLitRotBuf.scala:152:7] wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[ZstdLitRotBuf.scala:152:7] wire io_memwrites_in_bits_end_of_message_0 = io_memwrites_in_bits_end_of_message; // @[ZstdLitRotBuf.scala:152:7] wire [5:0] io_consumer_user_consumed_bytes_0 = io_consumer_user_consumed_bytes; // @[ZstdLitRotBuf.scala:152:7] wire io_consumer_output_ready_0 = io_consumer_output_ready; // @[ZstdLitRotBuf.scala:152:7] wire [5:0] io_memwrites_in_bits_validbytes = 6'h1; // @[ZstdLitRotBuf.scala:152:7] wire io_consumer_output_last_chunk = 1'h0; // @[ZstdLitRotBuf.scala:152:7] wire enough_data; // @[ZstdLitRotBuf.scala:251:34] wire [255:0] _io_consumer_output_data_T; // @[ZstdLitRotBuf.scala:246:33] wire io_memwrites_in_ready_0; // @[ZstdLitRotBuf.scala:152:7] wire [5:0] io_consumer_available_output_bytes_0; // @[ZstdLitRotBuf.scala:152:7] wire io_consumer_output_valid_0; // @[ZstdLitRotBuf.scala:152:7] wire [255:0] io_consumer_output_data_0; // @[ZstdLitRotBuf.scala:152:7] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [5:0] write_start_index; // @[ZstdLitRotBuf.scala:172:34] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[ZstdLitRotBuf.scala:172:34, :182:34] wire [6:0] _GEN = _idx_T % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx = _GEN[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_0 = _idx_T_1 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_1 = _GEN_0[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_1 = _idx_T_2 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_2 = _GEN_1[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_2 = _idx_T_3 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_3 = _GEN_2[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_3 = _idx_T_4 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_4 = _GEN_3[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_4 = _idx_T_5 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_5 = _GEN_4[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_5 = _idx_T_6 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_6 = _GEN_5[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_6 = _idx_T_7 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_7 = _GEN_6[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_7 = _idx_T_8 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_8 = _GEN_7[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_8 = _idx_T_9 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_9 = _GEN_8[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_9 = _idx_T_10 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_10 = _GEN_9[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_10 = _idx_T_11 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_11 = _GEN_10[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_11 = _idx_T_12 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_12 = _GEN_11[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_12 = _idx_T_13 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_13 = _GEN_12[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_13 = _idx_T_14 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_14 = _GEN_13[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_14 = _idx_T_15 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_15 = _GEN_14[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_15 = _idx_T_16 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_16 = _GEN_15[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_16 = _idx_T_17 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_17 = _GEN_16[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_17 = _idx_T_18 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_18 = _GEN_17[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_18 = _idx_T_19 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_19 = _GEN_18[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_19 = _idx_T_20 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_20 = _GEN_19[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_20 = _idx_T_21 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_21 = _GEN_20[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_21 = _idx_T_22 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_22 = _GEN_21[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_22 = _idx_T_23 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_23 = _GEN_22[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_23 = _idx_T_24 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_24 = _GEN_23[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_24 = _idx_T_25 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_25 = _GEN_24[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_25 = _idx_T_26 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_26 = _GEN_25[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_26 = _idx_T_27 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_27 = _GEN_26[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_27 = _idx_T_28 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_28 = _GEN_27[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_28 = _idx_T_29 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_29 = _GEN_28[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_29 = _idx_T_30 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_30 = _GEN_29[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_30 = _idx_T_31 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_31 = _GEN_30[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdLitRotBuf.scala:158:33, :182:34, :190:47] wire [6:0] _GEN_31 = wrap_len_index_wide % 7'h20; // @[ZstdLitRotBuf.scala:190:47, :191:48] wire [5:0] wrap_len_index_end = _GEN_31[5:0]; // @[ZstdLitRotBuf.scala:191:48] wire wrapped = \|(wrap_len_index_wide[6:5]); // @[ZstdLitRotBuf.scala:190:47, :192:37] wire _all_queues_ready_T = _Queue10_UInt8_io_enq_ready & _Queue10_UInt8_1_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue10_UInt8_2_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue10_UInt8_3_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue10_UInt8_4_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue10_UInt8_5_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue10_UInt8_6_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue10_UInt8_7_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue10_UInt8_8_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue10_UInt8_9_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue10_UInt8_10_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue10_UInt8_11_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue10_UInt8_12_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue10_UInt8_13_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue10_UInt8_14_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue10_UInt8_15_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue10_UInt8_16_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue10_UInt8_17_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue10_UInt8_18_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue10_UInt8_19_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue10_UInt8_20_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue10_UInt8_21_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue10_UInt8_22_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue10_UInt8_23_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue10_UInt8_24_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue10_UInt8_25_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue10_UInt8_26_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue10_UInt8_27_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue10_UInt8_28_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue10_UInt8_29_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue10_UInt8_30_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue10_UInt8_31_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _T_3140 = _incoming_writes_Q_io_deq_valid & all_queues_ready; // @[Misc.scala:29:18] wire _GEN_32 = write_start_index == 6'h0; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T = _GEN_32; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_3; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_3 = _GEN_32; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_1 = \|wrap_len_index_end; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_2 = _use_this_queue_T \| _use_this_queue_T_1; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_4 = \|wrap_len_index_end; // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_33 = write_start_index < 6'h2; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_6; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_6 = _GEN_33; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_9; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_9 = _GEN_33; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_7 = \|(wrap_len_index_end[5:1]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 \| _use_this_queue_T_7; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_10 = \|(wrap_len_index_end[5:1]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_34 = write_start_index < 6'h3; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_12; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_12 = _GEN_34; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_15; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_15 = _GEN_34; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_35 = wrap_len_index_end > 6'h2; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_13; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_13 = _GEN_35; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_16; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_16 = _GEN_35; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 \| _use_this_queue_T_13; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_36 = write_start_index < 6'h4; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_18; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_18 = _GEN_36; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_21; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_21 = _GEN_36; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_19 = \|(wrap_len_index_end[5:2]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 \| _use_this_queue_T_19; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_22 = \|(wrap_len_index_end[5:2]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_37 = write_start_index < 6'h5; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_24; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_24 = _GEN_37; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_27; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_27 = _GEN_37; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_38 = wrap_len_index_end > 6'h4; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_25; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_25 = _GEN_38; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_28; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_28 = _GEN_38; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 \| _use_this_queue_T_25; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_39 = write_start_index < 6'h6; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_30; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_30 = _GEN_39; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_33; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_33 = _GEN_39; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_40 = wrap_len_index_end > 6'h5; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_31; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_31 = _GEN_40; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_34; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_34 = _GEN_40; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 \| _use_this_queue_T_31; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_41 = write_start_index < 6'h7; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_36; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_36 = _GEN_41; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_39; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_39 = _GEN_41; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_42 = wrap_len_index_end > 6'h6; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_37; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_37 = _GEN_42; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_40; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_40 = _GEN_42; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 \| _use_this_queue_T_37; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_43 = write_start_index < 6'h8; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_42; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_42 = _GEN_43; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_45; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_45 = _GEN_43; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_43 = \|(wrap_len_index_end[5:3]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 \| _use_this_queue_T_43; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_46 = \|(wrap_len_index_end[5:3]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_44 = write_start_index < 6'h9; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_48; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_48 = _GEN_44; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_51; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_51 = _GEN_44; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_45 = wrap_len_index_end > 6'h8; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_49; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_49 = _GEN_45; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_52; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_52 = _GEN_45; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 \| _use_this_queue_T_49; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_46 = write_start_index < 6'hA; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_54; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_54 = _GEN_46; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_57; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_57 = _GEN_46; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_47 = wrap_len_index_end > 6'h9; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_55; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_55 = _GEN_47; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_58; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_58 = _GEN_47; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 \| _use_this_queue_T_55; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_48 = write_start_index < 6'hB; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_60; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_60 = _GEN_48; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_63; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_63 = _GEN_48; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_49 = wrap_len_index_end > 6'hA; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_61; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_61 = _GEN_49; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_64; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_64 = _GEN_49; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 \| _use_this_queue_T_61; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_50 = write_start_index < 6'hC; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_66; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_66 = _GEN_50; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_69; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_69 = _GEN_50; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_51 = wrap_len_index_end > 6'hB; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_67; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_67 = _GEN_51; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_70; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_70 = _GEN_51; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 \| _use_this_queue_T_67; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_52 = write_start_index < 6'hD; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_72; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_72 = _GEN_52; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_75; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_75 = _GEN_52; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_53 = wrap_len_index_end > 6'hC; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_73; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_73 = _GEN_53; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_76; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_76 = _GEN_53; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 \| _use_this_queue_T_73; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_54 = write_start_index < 6'hE; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_78; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_78 = _GEN_54; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_81; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_81 = _GEN_54; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_55 = wrap_len_index_end > 6'hD; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_79; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_79 = _GEN_55; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_82; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_82 = _GEN_55; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 \| _use_this_queue_T_79; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_56 = write_start_index < 6'hF; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_84; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_84 = _GEN_56; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_87; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_87 = _GEN_56; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_57 = wrap_len_index_end > 6'hE; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_85; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_85 = _GEN_57; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_88; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_88 = _GEN_57; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 \| _use_this_queue_T_85; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_58 = write_start_index < 6'h10; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_90; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_90 = _GEN_58; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_93; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_93 = _GEN_58; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_91 = \|(wrap_len_index_end[5:4]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 \| _use_this_queue_T_91; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_94 = \|(wrap_len_index_end[5:4]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_59 = write_start_index < 6'h11; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_96; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_96 = _GEN_59; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_99; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_99 = _GEN_59; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_60 = wrap_len_index_end > 6'h10; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_97; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_97 = _GEN_60; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_100; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_100 = _GEN_60; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 \| _use_this_queue_T_97; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_61 = write_start_index < 6'h12; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_102; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_102 = _GEN_61; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_105; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_105 = _GEN_61; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_62 = wrap_len_index_end > 6'h11; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_103; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_103 = _GEN_62; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_106; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_106 = _GEN_62; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 \| _use_this_queue_T_103; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_63 = write_start_index < 6'h13; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_108; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_108 = _GEN_63; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_111; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_111 = _GEN_63; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_64 = wrap_len_index_end > 6'h12; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_109; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_109 = _GEN_64; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_112; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_112 = _GEN_64; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 \| _use_this_queue_T_109; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_65 = write_start_index < 6'h14; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_114; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_114 = _GEN_65; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_117; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_117 = _GEN_65; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_66 = wrap_len_index_end > 6'h13; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_115; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_115 = _GEN_66; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_118; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_118 = _GEN_66; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 \| _use_this_queue_T_115; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_67 = write_start_index < 6'h15; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_120; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_120 = _GEN_67; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_123; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_123 = _GEN_67; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_68 = wrap_len_index_end > 6'h14; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_121; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_121 = _GEN_68; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_124; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_124 = _GEN_68; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 \| _use_this_queue_T_121; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_69 = write_start_index < 6'h16; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_126; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_126 = _GEN_69; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_129; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_129 = _GEN_69; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_70 = wrap_len_index_end > 6'h15; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_127; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_127 = _GEN_70; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_130; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_130 = _GEN_70; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 \| _use_this_queue_T_127; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_71 = write_start_index < 6'h17; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_132; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_132 = _GEN_71; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_135; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_135 = _GEN_71; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_72 = wrap_len_index_end > 6'h16; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_133; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_133 = _GEN_72; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_136; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_136 = _GEN_72; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 \| _use_this_queue_T_133; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_73 = write_start_index < 6'h18; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_138; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_138 = _GEN_73; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_141; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_141 = _GEN_73; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_74 = wrap_len_index_end > 6'h17; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_139; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_139 = _GEN_74; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_142; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_142 = _GEN_74; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 \| _use_this_queue_T_139; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_75 = write_start_index < 6'h19; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_144; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_144 = _GEN_75; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_147; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_147 = _GEN_75; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_76 = wrap_len_index_end > 6'h18; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_145; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_145 = _GEN_76; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_148; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_148 = _GEN_76; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 \| _use_this_queue_T_145; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_77 = write_start_index < 6'h1A; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_150; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_150 = _GEN_77; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_153; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_153 = _GEN_77; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_78 = wrap_len_index_end > 6'h19; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_151; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_151 = _GEN_78; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_154; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_154 = _GEN_78; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 \| _use_this_queue_T_151; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_79 = write_start_index < 6'h1B; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_156; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_156 = _GEN_79; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_159; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_159 = _GEN_79; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_80 = wrap_len_index_end > 6'h1A; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_157; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_157 = _GEN_80; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_160; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_160 = _GEN_80; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 \| _use_this_queue_T_157; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_81 = write_start_index < 6'h1C; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_162; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_162 = _GEN_81; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_165; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_165 = _GEN_81; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_82 = wrap_len_index_end > 6'h1B; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_163; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_163 = _GEN_82; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_166; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_166 = _GEN_82; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 \| _use_this_queue_T_163; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_83 = write_start_index < 6'h1D; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_168; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_168 = _GEN_83; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_171; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_171 = _GEN_83; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_84 = wrap_len_index_end > 6'h1C; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_169; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_169 = _GEN_84; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_172; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_172 = _GEN_84; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 \| _use_this_queue_T_169; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_85 = write_start_index < 6'h1E; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_174; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_174 = _GEN_85; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_177; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_177 = _GEN_85; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_86 = wrap_len_index_end > 6'h1D; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_175; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_175 = _GEN_86; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_178; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_178 = _GEN_86; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 \| _use_this_queue_T_175; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_87 = write_start_index < 6'h1F; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_180; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_180 = _GEN_87; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_183; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_183 = _GEN_87; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_88 = wrap_len_index_end > 6'h1E; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_181; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_181 = _GEN_88; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_184; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_184 = _GEN_88; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 \| _use_this_queue_T_181; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 \| _use_this_queue_T_187; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[ZstdLitRotBuf.scala:172:34, :210:41, :211:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[ZstdLitRotBuf.scala:222:33] wire [7:0] remapVecData_0; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_1; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_2; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_3; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_4; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_5; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_6; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_7; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_8; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_9; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_10; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_11; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_12; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_13; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_14; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_15; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_16; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_17; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_18; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_19; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_20; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_21; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_22; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_23; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_24; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_25; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_26; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_27; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_28; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_29; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_30; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_31; // @[ZstdLitRotBuf.scala:225:26] wire remapVecValids_0; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_1; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_2; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_3; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_4; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_5; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_6; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_7; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_8; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_9; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_10; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_11; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_12; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_13; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_14; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_15; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_16; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_17; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_18; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_19; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_20; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_21; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_22; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_23; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_24; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_25; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_26; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_27; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_28; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_29; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_30; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_31; // @[ZstdLitRotBuf.scala:226:28] wire _remapVecReadys_0_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_1_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_2_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_3_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_4_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_5_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_6_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_7_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_8_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_9_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_10_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_11_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_12_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_13_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_14_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_15_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_16_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_17_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_18_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_19_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_20_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_21_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_22_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_23_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_24_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_25_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_26_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_27_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_28_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_29_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_30_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_31_T_2; // @[ZstdLitRotBuf.scala:270:78] wire remapVecReadys_0; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_1; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_2; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_3; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_4; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_5; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_6; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_7; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_8; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_9; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_10; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_11; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_12; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_13; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_14; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_15; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_16; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_17; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_18; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_19; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_20; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_21; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_22; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_23; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_24; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_25; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_26; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_27; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_28; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_29; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_30; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_31; // @[ZstdLitRotBuf.scala:227:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[ZstdLitRotBuf.scala:222:33, :237:33] wire [6:0] _GEN_89 = _remapindex_T % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex = _GEN_89[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3270 = remapindex == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3271 = remapindex == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3272 = remapindex == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3273 = remapindex == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3274 = remapindex == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3275 = remapindex == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3276 = remapindex == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3277 = remapindex == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3278 = remapindex == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3279 = remapindex == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3280 = remapindex == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3281 = remapindex == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3282 = remapindex == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3283 = remapindex == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3284 = remapindex == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3285 = remapindex == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3286 = remapindex == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3287 = remapindex == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3288 = remapindex == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3289 = remapindex == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3290 = remapindex == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3291 = remapindex == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3292 = remapindex == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3293 = remapindex == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3294 = remapindex == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3295 = remapindex == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3296 = remapindex == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3297 = remapindex == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3298 = remapindex == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3299 = remapindex == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3300 = remapindex == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3301 = remapindex == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_0 = _T_3301 ? _Queue10_UInt8_31_io_deq_bits : _T_3300 ? _Queue10_UInt8_30_io_deq_bits : _T_3299 ? _Queue10_UInt8_29_io_deq_bits : _T_3298 ? _Queue10_UInt8_28_io_deq_bits : _T_3297 ? _Queue10_UInt8_27_io_deq_bits : _T_3296 ? _Queue10_UInt8_26_io_deq_bits : _T_3295 ? _Queue10_UInt8_25_io_deq_bits : _T_3294 ? _Queue10_UInt8_24_io_deq_bits : _T_3293 ? _Queue10_UInt8_23_io_deq_bits : _T_3292 ? _Queue10_UInt8_22_io_deq_bits : _T_3291 ? _Queue10_UInt8_21_io_deq_bits : _T_3290 ? _Queue10_UInt8_20_io_deq_bits : _T_3289 ? _Queue10_UInt8_19_io_deq_bits : _T_3288 ? _Queue10_UInt8_18_io_deq_bits : _T_3287 ? _Queue10_UInt8_17_io_deq_bits : _T_3286 ? _Queue10_UInt8_16_io_deq_bits : _T_3285 ? _Queue10_UInt8_15_io_deq_bits : _T_3284 ? _Queue10_UInt8_14_io_deq_bits : _T_3283 ? _Queue10_UInt8_13_io_deq_bits : _T_3282 ? _Queue10_UInt8_12_io_deq_bits : _T_3281 ? _Queue10_UInt8_11_io_deq_bits : _T_3280 ? _Queue10_UInt8_10_io_deq_bits : _T_3279 ? _Queue10_UInt8_9_io_deq_bits : _T_3278 ? _Queue10_UInt8_8_io_deq_bits : _T_3277 ? _Queue10_UInt8_7_io_deq_bits : _T_3276 ? _Queue10_UInt8_6_io_deq_bits : _T_3275 ? _Queue10_UInt8_5_io_deq_bits : _T_3274 ? _Queue10_UInt8_4_io_deq_bits : _T_3273 ? _Queue10_UInt8_3_io_deq_bits : _T_3272 ? _Queue10_UInt8_2_io_deq_bits : _T_3271 ? _Queue10_UInt8_1_io_deq_bits : _T_3270 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_0 = _T_3301 ? _Queue10_UInt8_31_io_deq_valid : _T_3300 ? _Queue10_UInt8_30_io_deq_valid : _T_3299 ? _Queue10_UInt8_29_io_deq_valid : _T_3298 ? _Queue10_UInt8_28_io_deq_valid : _T_3297 ? _Queue10_UInt8_27_io_deq_valid : _T_3296 ? _Queue10_UInt8_26_io_deq_valid : _T_3295 ? _Queue10_UInt8_25_io_deq_valid : _T_3294 ? _Queue10_UInt8_24_io_deq_valid : _T_3293 ? _Queue10_UInt8_23_io_deq_valid : _T_3292 ? _Queue10_UInt8_22_io_deq_valid : _T_3291 ? _Queue10_UInt8_21_io_deq_valid : _T_3290 ? _Queue10_UInt8_20_io_deq_valid : _T_3289 ? _Queue10_UInt8_19_io_deq_valid : _T_3288 ? _Queue10_UInt8_18_io_deq_valid : _T_3287 ? _Queue10_UInt8_17_io_deq_valid : _T_3286 ? _Queue10_UInt8_16_io_deq_valid : _T_3285 ? _Queue10_UInt8_15_io_deq_valid : _T_3284 ? _Queue10_UInt8_14_io_deq_valid : _T_3283 ? _Queue10_UInt8_13_io_deq_valid : _T_3282 ? _Queue10_UInt8_12_io_deq_valid : _T_3281 ? _Queue10_UInt8_11_io_deq_valid : _T_3280 ? _Queue10_UInt8_10_io_deq_valid : _T_3279 ? _Queue10_UInt8_9_io_deq_valid : _T_3278 ? _Queue10_UInt8_8_io_deq_valid : _T_3277 ? _Queue10_UInt8_7_io_deq_valid : _T_3276 ? _Queue10_UInt8_6_io_deq_valid : _T_3275 ? _Queue10_UInt8_5_io_deq_valid : _T_3274 ? _Queue10_UInt8_4_io_deq_valid : _T_3273 ? _Queue10_UInt8_3_io_deq_valid : _T_3272 ? _Queue10_UInt8_2_io_deq_valid : _T_3271 ? _Queue10_UInt8_1_io_deq_valid : _T_3270 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_90 = _remapindex_T_1 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_1 = _GEN_90[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3302 = remapindex_1 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3303 = remapindex_1 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3304 = remapindex_1 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3305 = remapindex_1 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3306 = remapindex_1 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3307 = remapindex_1 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3308 = remapindex_1 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3309 = remapindex_1 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3310 = remapindex_1 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3311 = remapindex_1 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3312 = remapindex_1 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3313 = remapindex_1 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3314 = remapindex_1 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3315 = remapindex_1 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3316 = remapindex_1 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3317 = remapindex_1 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3318 = remapindex_1 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3319 = remapindex_1 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3320 = remapindex_1 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3321 = remapindex_1 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3322 = remapindex_1 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3323 = remapindex_1 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3324 = remapindex_1 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3325 = remapindex_1 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3326 = remapindex_1 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3327 = remapindex_1 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3328 = remapindex_1 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3329 = remapindex_1 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3330 = remapindex_1 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3331 = remapindex_1 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3332 = remapindex_1 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3333 = remapindex_1 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_1 = _T_3333 ? _Queue10_UInt8_31_io_deq_bits : _T_3332 ? _Queue10_UInt8_30_io_deq_bits : _T_3331 ? _Queue10_UInt8_29_io_deq_bits : _T_3330 ? _Queue10_UInt8_28_io_deq_bits : _T_3329 ? _Queue10_UInt8_27_io_deq_bits : _T_3328 ? _Queue10_UInt8_26_io_deq_bits : _T_3327 ? _Queue10_UInt8_25_io_deq_bits : _T_3326 ? _Queue10_UInt8_24_io_deq_bits : _T_3325 ? _Queue10_UInt8_23_io_deq_bits : _T_3324 ? _Queue10_UInt8_22_io_deq_bits : _T_3323 ? _Queue10_UInt8_21_io_deq_bits : _T_3322 ? _Queue10_UInt8_20_io_deq_bits : _T_3321 ? _Queue10_UInt8_19_io_deq_bits : _T_3320 ? _Queue10_UInt8_18_io_deq_bits : _T_3319 ? _Queue10_UInt8_17_io_deq_bits : _T_3318 ? _Queue10_UInt8_16_io_deq_bits : _T_3317 ? _Queue10_UInt8_15_io_deq_bits : _T_3316 ? _Queue10_UInt8_14_io_deq_bits : _T_3315 ? _Queue10_UInt8_13_io_deq_bits : _T_3314 ? _Queue10_UInt8_12_io_deq_bits : _T_3313 ? _Queue10_UInt8_11_io_deq_bits : _T_3312 ? _Queue10_UInt8_10_io_deq_bits : _T_3311 ? _Queue10_UInt8_9_io_deq_bits : _T_3310 ? _Queue10_UInt8_8_io_deq_bits : _T_3309 ? _Queue10_UInt8_7_io_deq_bits : _T_3308 ? _Queue10_UInt8_6_io_deq_bits : _T_3307 ? _Queue10_UInt8_5_io_deq_bits : _T_3306 ? _Queue10_UInt8_4_io_deq_bits : _T_3305 ? _Queue10_UInt8_3_io_deq_bits : _T_3304 ? _Queue10_UInt8_2_io_deq_bits : _T_3303 ? _Queue10_UInt8_1_io_deq_bits : _T_3302 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_1 = _T_3333 ? _Queue10_UInt8_31_io_deq_valid : _T_3332 ? _Queue10_UInt8_30_io_deq_valid : _T_3331 ? _Queue10_UInt8_29_io_deq_valid : _T_3330 ? _Queue10_UInt8_28_io_deq_valid : _T_3329 ? _Queue10_UInt8_27_io_deq_valid : _T_3328 ? _Queue10_UInt8_26_io_deq_valid : _T_3327 ? _Queue10_UInt8_25_io_deq_valid : _T_3326 ? _Queue10_UInt8_24_io_deq_valid : _T_3325 ? _Queue10_UInt8_23_io_deq_valid : _T_3324 ? _Queue10_UInt8_22_io_deq_valid : _T_3323 ? _Queue10_UInt8_21_io_deq_valid : _T_3322 ? _Queue10_UInt8_20_io_deq_valid : _T_3321 ? _Queue10_UInt8_19_io_deq_valid : _T_3320 ? _Queue10_UInt8_18_io_deq_valid : _T_3319 ? _Queue10_UInt8_17_io_deq_valid : _T_3318 ? _Queue10_UInt8_16_io_deq_valid : _T_3317 ? _Queue10_UInt8_15_io_deq_valid : _T_3316 ? _Queue10_UInt8_14_io_deq_valid : _T_3315 ? _Queue10_UInt8_13_io_deq_valid : _T_3314 ? _Queue10_UInt8_12_io_deq_valid : _T_3313 ? _Queue10_UInt8_11_io_deq_valid : _T_3312 ? _Queue10_UInt8_10_io_deq_valid : _T_3311 ? _Queue10_UInt8_9_io_deq_valid : _T_3310 ? _Queue10_UInt8_8_io_deq_valid : _T_3309 ? _Queue10_UInt8_7_io_deq_valid : _T_3308 ? _Queue10_UInt8_6_io_deq_valid : _T_3307 ? _Queue10_UInt8_5_io_deq_valid : _T_3306 ? _Queue10_UInt8_4_io_deq_valid : _T_3305 ? _Queue10_UInt8_3_io_deq_valid : _T_3304 ? _Queue10_UInt8_2_io_deq_valid : _T_3303 ? _Queue10_UInt8_1_io_deq_valid : _T_3302 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_91 = _remapindex_T_2 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_2 = _GEN_91[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3334 = remapindex_2 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3335 = remapindex_2 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3336 = remapindex_2 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3337 = remapindex_2 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3338 = remapindex_2 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3339 = remapindex_2 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3340 = remapindex_2 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3341 = remapindex_2 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3342 = remapindex_2 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3343 = remapindex_2 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3344 = remapindex_2 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3345 = remapindex_2 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3346 = remapindex_2 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3347 = remapindex_2 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3348 = remapindex_2 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3349 = remapindex_2 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3350 = remapindex_2 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3351 = remapindex_2 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3352 = remapindex_2 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3353 = remapindex_2 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3354 = remapindex_2 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3355 = remapindex_2 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3356 = remapindex_2 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3357 = remapindex_2 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3358 = remapindex_2 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3359 = remapindex_2 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3360 = remapindex_2 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3361 = remapindex_2 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3362 = remapindex_2 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3363 = remapindex_2 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3364 = remapindex_2 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3365 = remapindex_2 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_2 = _T_3365 ? _Queue10_UInt8_31_io_deq_bits : _T_3364 ? _Queue10_UInt8_30_io_deq_bits : _T_3363 ? _Queue10_UInt8_29_io_deq_bits : _T_3362 ? _Queue10_UInt8_28_io_deq_bits : _T_3361 ? _Queue10_UInt8_27_io_deq_bits : _T_3360 ? _Queue10_UInt8_26_io_deq_bits : _T_3359 ? _Queue10_UInt8_25_io_deq_bits : _T_3358 ? _Queue10_UInt8_24_io_deq_bits : _T_3357 ? _Queue10_UInt8_23_io_deq_bits : _T_3356 ? _Queue10_UInt8_22_io_deq_bits : _T_3355 ? _Queue10_UInt8_21_io_deq_bits : _T_3354 ? _Queue10_UInt8_20_io_deq_bits : _T_3353 ? _Queue10_UInt8_19_io_deq_bits : _T_3352 ? _Queue10_UInt8_18_io_deq_bits : _T_3351 ? _Queue10_UInt8_17_io_deq_bits : _T_3350 ? _Queue10_UInt8_16_io_deq_bits : _T_3349 ? _Queue10_UInt8_15_io_deq_bits : _T_3348 ? _Queue10_UInt8_14_io_deq_bits : _T_3347 ? _Queue10_UInt8_13_io_deq_bits : _T_3346 ? _Queue10_UInt8_12_io_deq_bits : _T_3345 ? _Queue10_UInt8_11_io_deq_bits : _T_3344 ? _Queue10_UInt8_10_io_deq_bits : _T_3343 ? _Queue10_UInt8_9_io_deq_bits : _T_3342 ? _Queue10_UInt8_8_io_deq_bits : _T_3341 ? _Queue10_UInt8_7_io_deq_bits : _T_3340 ? _Queue10_UInt8_6_io_deq_bits : _T_3339 ? _Queue10_UInt8_5_io_deq_bits : _T_3338 ? _Queue10_UInt8_4_io_deq_bits : _T_3337 ? _Queue10_UInt8_3_io_deq_bits : _T_3336 ? _Queue10_UInt8_2_io_deq_bits : _T_3335 ? _Queue10_UInt8_1_io_deq_bits : _T_3334 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_2 = _T_3365 ? _Queue10_UInt8_31_io_deq_valid : _T_3364 ? _Queue10_UInt8_30_io_deq_valid : _T_3363 ? _Queue10_UInt8_29_io_deq_valid : _T_3362 ? _Queue10_UInt8_28_io_deq_valid : _T_3361 ? _Queue10_UInt8_27_io_deq_valid : _T_3360 ? _Queue10_UInt8_26_io_deq_valid : _T_3359 ? _Queue10_UInt8_25_io_deq_valid : _T_3358 ? _Queue10_UInt8_24_io_deq_valid : _T_3357 ? _Queue10_UInt8_23_io_deq_valid : _T_3356 ? _Queue10_UInt8_22_io_deq_valid : _T_3355 ? _Queue10_UInt8_21_io_deq_valid : _T_3354 ? _Queue10_UInt8_20_io_deq_valid : _T_3353 ? _Queue10_UInt8_19_io_deq_valid : _T_3352 ? _Queue10_UInt8_18_io_deq_valid : _T_3351 ? _Queue10_UInt8_17_io_deq_valid : _T_3350 ? _Queue10_UInt8_16_io_deq_valid : _T_3349 ? _Queue10_UInt8_15_io_deq_valid : _T_3348 ? _Queue10_UInt8_14_io_deq_valid : _T_3347 ? _Queue10_UInt8_13_io_deq_valid : _T_3346 ? _Queue10_UInt8_12_io_deq_valid : _T_3345 ? _Queue10_UInt8_11_io_deq_valid : _T_3344 ? _Queue10_UInt8_10_io_deq_valid : _T_3343 ? _Queue10_UInt8_9_io_deq_valid : _T_3342 ? _Queue10_UInt8_8_io_deq_valid : _T_3341 ? _Queue10_UInt8_7_io_deq_valid : _T_3340 ? _Queue10_UInt8_6_io_deq_valid : _T_3339 ? _Queue10_UInt8_5_io_deq_valid : _T_3338 ? _Queue10_UInt8_4_io_deq_valid : _T_3337 ? _Queue10_UInt8_3_io_deq_valid : _T_3336 ? _Queue10_UInt8_2_io_deq_valid : _T_3335 ? _Queue10_UInt8_1_io_deq_valid : _T_3334 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_92 = _remapindex_T_3 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_3 = _GEN_92[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3366 = remapindex_3 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3367 = remapindex_3 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3368 = remapindex_3 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3369 = remapindex_3 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3370 = remapindex_3 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3371 = remapindex_3 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3372 = remapindex_3 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3373 = remapindex_3 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3374 = remapindex_3 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3375 = remapindex_3 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3376 = remapindex_3 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3377 = remapindex_3 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3378 = remapindex_3 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3379 = remapindex_3 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3380 = remapindex_3 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3381 = remapindex_3 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3382 = remapindex_3 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3383 = remapindex_3 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3384 = remapindex_3 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3385 = remapindex_3 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3386 = remapindex_3 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3387 = remapindex_3 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3388 = remapindex_3 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3389 = remapindex_3 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3390 = remapindex_3 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3391 = remapindex_3 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3392 = remapindex_3 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3393 = remapindex_3 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3394 = remapindex_3 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3395 = remapindex_3 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3396 = remapindex_3 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3397 = remapindex_3 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_3 = _T_3397 ? _Queue10_UInt8_31_io_deq_bits : _T_3396 ? _Queue10_UInt8_30_io_deq_bits : _T_3395 ? _Queue10_UInt8_29_io_deq_bits : _T_3394 ? _Queue10_UInt8_28_io_deq_bits : _T_3393 ? _Queue10_UInt8_27_io_deq_bits : _T_3392 ? _Queue10_UInt8_26_io_deq_bits : _T_3391 ? _Queue10_UInt8_25_io_deq_bits : _T_3390 ? _Queue10_UInt8_24_io_deq_bits : _T_3389 ? _Queue10_UInt8_23_io_deq_bits : _T_3388 ? _Queue10_UInt8_22_io_deq_bits : _T_3387 ? _Queue10_UInt8_21_io_deq_bits : _T_3386 ? _Queue10_UInt8_20_io_deq_bits : _T_3385 ? _Queue10_UInt8_19_io_deq_bits : _T_3384 ? _Queue10_UInt8_18_io_deq_bits : _T_3383 ? _Queue10_UInt8_17_io_deq_bits : _T_3382 ? _Queue10_UInt8_16_io_deq_bits : _T_3381 ? _Queue10_UInt8_15_io_deq_bits : _T_3380 ? _Queue10_UInt8_14_io_deq_bits : _T_3379 ? _Queue10_UInt8_13_io_deq_bits : _T_3378 ? _Queue10_UInt8_12_io_deq_bits : _T_3377 ? _Queue10_UInt8_11_io_deq_bits : _T_3376 ? _Queue10_UInt8_10_io_deq_bits : _T_3375 ? _Queue10_UInt8_9_io_deq_bits : _T_3374 ? _Queue10_UInt8_8_io_deq_bits : _T_3373 ? _Queue10_UInt8_7_io_deq_bits : _T_3372 ? _Queue10_UInt8_6_io_deq_bits : _T_3371 ? _Queue10_UInt8_5_io_deq_bits : _T_3370 ? _Queue10_UInt8_4_io_deq_bits : _T_3369 ? _Queue10_UInt8_3_io_deq_bits : _T_3368 ? _Queue10_UInt8_2_io_deq_bits : _T_3367 ? _Queue10_UInt8_1_io_deq_bits : _T_3366 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_3 = _T_3397 ? _Queue10_UInt8_31_io_deq_valid : _T_3396 ? _Queue10_UInt8_30_io_deq_valid : _T_3395 ? _Queue10_UInt8_29_io_deq_valid : _T_3394 ? _Queue10_UInt8_28_io_deq_valid : _T_3393 ? _Queue10_UInt8_27_io_deq_valid : _T_3392 ? _Queue10_UInt8_26_io_deq_valid : _T_3391 ? _Queue10_UInt8_25_io_deq_valid : _T_3390 ? _Queue10_UInt8_24_io_deq_valid : _T_3389 ? _Queue10_UInt8_23_io_deq_valid : _T_3388 ? _Queue10_UInt8_22_io_deq_valid : _T_3387 ? _Queue10_UInt8_21_io_deq_valid : _T_3386 ? _Queue10_UInt8_20_io_deq_valid : _T_3385 ? _Queue10_UInt8_19_io_deq_valid : _T_3384 ? _Queue10_UInt8_18_io_deq_valid : _T_3383 ? _Queue10_UInt8_17_io_deq_valid : _T_3382 ? _Queue10_UInt8_16_io_deq_valid : _T_3381 ? _Queue10_UInt8_15_io_deq_valid : _T_3380 ? _Queue10_UInt8_14_io_deq_valid : _T_3379 ? _Queue10_UInt8_13_io_deq_valid : _T_3378 ? _Queue10_UInt8_12_io_deq_valid : _T_3377 ? _Queue10_UInt8_11_io_deq_valid : _T_3376 ? _Queue10_UInt8_10_io_deq_valid : _T_3375 ? _Queue10_UInt8_9_io_deq_valid : _T_3374 ? _Queue10_UInt8_8_io_deq_valid : _T_3373 ? _Queue10_UInt8_7_io_deq_valid : _T_3372 ? _Queue10_UInt8_6_io_deq_valid : _T_3371 ? _Queue10_UInt8_5_io_deq_valid : _T_3370 ? _Queue10_UInt8_4_io_deq_valid : _T_3369 ? _Queue10_UInt8_3_io_deq_valid : _T_3368 ? _Queue10_UInt8_2_io_deq_valid : _T_3367 ? _Queue10_UInt8_1_io_deq_valid : _T_3366 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_93 = _remapindex_T_4 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_4 = _GEN_93[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3398 = remapindex_4 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3399 = remapindex_4 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3400 = remapindex_4 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3401 = remapindex_4 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3402 = remapindex_4 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3403 = remapindex_4 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3404 = remapindex_4 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3405 = remapindex_4 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3406 = remapindex_4 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3407 = remapindex_4 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3408 = remapindex_4 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3409 = remapindex_4 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3410 = remapindex_4 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3411 = remapindex_4 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3412 = remapindex_4 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3413 = remapindex_4 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3414 = remapindex_4 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3415 = remapindex_4 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3416 = remapindex_4 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3417 = remapindex_4 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3418 = remapindex_4 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3419 = remapindex_4 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3420 = remapindex_4 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3421 = remapindex_4 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3422 = remapindex_4 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3423 = remapindex_4 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3424 = remapindex_4 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3425 = remapindex_4 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3426 = remapindex_4 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3427 = remapindex_4 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3428 = remapindex_4 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3429 = remapindex_4 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_4 = _T_3429 ? _Queue10_UInt8_31_io_deq_bits : _T_3428 ? _Queue10_UInt8_30_io_deq_bits : _T_3427 ? _Queue10_UInt8_29_io_deq_bits : _T_3426 ? _Queue10_UInt8_28_io_deq_bits : _T_3425 ? _Queue10_UInt8_27_io_deq_bits : _T_3424 ? _Queue10_UInt8_26_io_deq_bits : _T_3423 ? _Queue10_UInt8_25_io_deq_bits : _T_3422 ? _Queue10_UInt8_24_io_deq_bits : _T_3421 ? _Queue10_UInt8_23_io_deq_bits : _T_3420 ? _Queue10_UInt8_22_io_deq_bits : _T_3419 ? _Queue10_UInt8_21_io_deq_bits : _T_3418 ? _Queue10_UInt8_20_io_deq_bits : _T_3417 ? _Queue10_UInt8_19_io_deq_bits : _T_3416 ? _Queue10_UInt8_18_io_deq_bits : _T_3415 ? _Queue10_UInt8_17_io_deq_bits : _T_3414 ? _Queue10_UInt8_16_io_deq_bits : _T_3413 ? _Queue10_UInt8_15_io_deq_bits : _T_3412 ? _Queue10_UInt8_14_io_deq_bits : _T_3411 ? _Queue10_UInt8_13_io_deq_bits : _T_3410 ? _Queue10_UInt8_12_io_deq_bits : _T_3409 ? _Queue10_UInt8_11_io_deq_bits : _T_3408 ? _Queue10_UInt8_10_io_deq_bits : _T_3407 ? _Queue10_UInt8_9_io_deq_bits : _T_3406 ? _Queue10_UInt8_8_io_deq_bits : _T_3405 ? _Queue10_UInt8_7_io_deq_bits : _T_3404 ? _Queue10_UInt8_6_io_deq_bits : _T_3403 ? _Queue10_UInt8_5_io_deq_bits : _T_3402 ? _Queue10_UInt8_4_io_deq_bits : _T_3401 ? _Queue10_UInt8_3_io_deq_bits : _T_3400 ? _Queue10_UInt8_2_io_deq_bits : _T_3399 ? _Queue10_UInt8_1_io_deq_bits : _T_3398 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_4 = _T_3429 ? _Queue10_UInt8_31_io_deq_valid : _T_3428 ? _Queue10_UInt8_30_io_deq_valid : _T_3427 ? _Queue10_UInt8_29_io_deq_valid : _T_3426 ? _Queue10_UInt8_28_io_deq_valid : _T_3425 ? _Queue10_UInt8_27_io_deq_valid : _T_3424 ? _Queue10_UInt8_26_io_deq_valid : _T_3423 ? _Queue10_UInt8_25_io_deq_valid : _T_3422 ? _Queue10_UInt8_24_io_deq_valid : _T_3421 ? _Queue10_UInt8_23_io_deq_valid : _T_3420 ? _Queue10_UInt8_22_io_deq_valid : _T_3419 ? _Queue10_UInt8_21_io_deq_valid : _T_3418 ? _Queue10_UInt8_20_io_deq_valid : _T_3417 ? _Queue10_UInt8_19_io_deq_valid : _T_3416 ? _Queue10_UInt8_18_io_deq_valid : _T_3415 ? _Queue10_UInt8_17_io_deq_valid : _T_3414 ? _Queue10_UInt8_16_io_deq_valid : _T_3413 ? _Queue10_UInt8_15_io_deq_valid : _T_3412 ? _Queue10_UInt8_14_io_deq_valid : _T_3411 ? _Queue10_UInt8_13_io_deq_valid : _T_3410 ? _Queue10_UInt8_12_io_deq_valid : _T_3409 ? _Queue10_UInt8_11_io_deq_valid : _T_3408 ? _Queue10_UInt8_10_io_deq_valid : _T_3407 ? _Queue10_UInt8_9_io_deq_valid : _T_3406 ? _Queue10_UInt8_8_io_deq_valid : _T_3405 ? _Queue10_UInt8_7_io_deq_valid : _T_3404 ? _Queue10_UInt8_6_io_deq_valid : _T_3403 ? _Queue10_UInt8_5_io_deq_valid : _T_3402 ? _Queue10_UInt8_4_io_deq_valid : _T_3401 ? _Queue10_UInt8_3_io_deq_valid : _T_3400 ? _Queue10_UInt8_2_io_deq_valid : _T_3399 ? _Queue10_UInt8_1_io_deq_valid : _T_3398 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_94 = _remapindex_T_5 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_5 = _GEN_94[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3430 = remapindex_5 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3431 = remapindex_5 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3432 = remapindex_5 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3433 = remapindex_5 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3434 = remapindex_5 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3435 = remapindex_5 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3436 = remapindex_5 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3437 = remapindex_5 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3438 = remapindex_5 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3439 = remapindex_5 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3440 = remapindex_5 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3441 = remapindex_5 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3442 = remapindex_5 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3443 = remapindex_5 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3444 = remapindex_5 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3445 = remapindex_5 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3446 = remapindex_5 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3447 = remapindex_5 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3448 = remapindex_5 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3449 = remapindex_5 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3450 = remapindex_5 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3451 = remapindex_5 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3452 = remapindex_5 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3453 = remapindex_5 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3454 = remapindex_5 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3455 = remapindex_5 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3456 = remapindex_5 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3457 = remapindex_5 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3458 = remapindex_5 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3459 = remapindex_5 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3460 = remapindex_5 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3461 = remapindex_5 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_5 = _T_3461 ? _Queue10_UInt8_31_io_deq_bits : _T_3460 ? _Queue10_UInt8_30_io_deq_bits : _T_3459 ? _Queue10_UInt8_29_io_deq_bits : _T_3458 ? _Queue10_UInt8_28_io_deq_bits : _T_3457 ? _Queue10_UInt8_27_io_deq_bits : _T_3456 ? _Queue10_UInt8_26_io_deq_bits : _T_3455 ? _Queue10_UInt8_25_io_deq_bits : _T_3454 ? _Queue10_UInt8_24_io_deq_bits : _T_3453 ? _Queue10_UInt8_23_io_deq_bits : _T_3452 ? _Queue10_UInt8_22_io_deq_bits : _T_3451 ? _Queue10_UInt8_21_io_deq_bits : _T_3450 ? _Queue10_UInt8_20_io_deq_bits : _T_3449 ? _Queue10_UInt8_19_io_deq_bits : _T_3448 ? _Queue10_UInt8_18_io_deq_bits : _T_3447 ? _Queue10_UInt8_17_io_deq_bits : _T_3446 ? _Queue10_UInt8_16_io_deq_bits : _T_3445 ? _Queue10_UInt8_15_io_deq_bits : _T_3444 ? _Queue10_UInt8_14_io_deq_bits : _T_3443 ? _Queue10_UInt8_13_io_deq_bits : _T_3442 ? _Queue10_UInt8_12_io_deq_bits : _T_3441 ? _Queue10_UInt8_11_io_deq_bits : _T_3440 ? _Queue10_UInt8_10_io_deq_bits : _T_3439 ? _Queue10_UInt8_9_io_deq_bits : _T_3438 ? _Queue10_UInt8_8_io_deq_bits : _T_3437 ? _Queue10_UInt8_7_io_deq_bits : _T_3436 ? _Queue10_UInt8_6_io_deq_bits : _T_3435 ? _Queue10_UInt8_5_io_deq_bits : _T_3434 ? _Queue10_UInt8_4_io_deq_bits : _T_3433 ? _Queue10_UInt8_3_io_deq_bits : _T_3432 ? _Queue10_UInt8_2_io_deq_bits : _T_3431 ? _Queue10_UInt8_1_io_deq_bits : _T_3430 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_5 = _T_3461 ? _Queue10_UInt8_31_io_deq_valid : _T_3460 ? _Queue10_UInt8_30_io_deq_valid : _T_3459 ? _Queue10_UInt8_29_io_deq_valid : _T_3458 ? _Queue10_UInt8_28_io_deq_valid : _T_3457 ? _Queue10_UInt8_27_io_deq_valid : _T_3456 ? _Queue10_UInt8_26_io_deq_valid : _T_3455 ? _Queue10_UInt8_25_io_deq_valid : _T_3454 ? _Queue10_UInt8_24_io_deq_valid : _T_3453 ? _Queue10_UInt8_23_io_deq_valid : _T_3452 ? _Queue10_UInt8_22_io_deq_valid : _T_3451 ? _Queue10_UInt8_21_io_deq_valid : _T_3450 ? _Queue10_UInt8_20_io_deq_valid : _T_3449 ? _Queue10_UInt8_19_io_deq_valid : _T_3448 ? _Queue10_UInt8_18_io_deq_valid : _T_3447 ? _Queue10_UInt8_17_io_deq_valid : _T_3446 ? _Queue10_UInt8_16_io_deq_valid : _T_3445 ? _Queue10_UInt8_15_io_deq_valid : _T_3444 ? _Queue10_UInt8_14_io_deq_valid : _T_3443 ? _Queue10_UInt8_13_io_deq_valid : _T_3442 ? _Queue10_UInt8_12_io_deq_valid : _T_3441 ? _Queue10_UInt8_11_io_deq_valid : _T_3440 ? _Queue10_UInt8_10_io_deq_valid : _T_3439 ? _Queue10_UInt8_9_io_deq_valid : _T_3438 ? _Queue10_UInt8_8_io_deq_valid : _T_3437 ? _Queue10_UInt8_7_io_deq_valid : _T_3436 ? _Queue10_UInt8_6_io_deq_valid : _T_3435 ? _Queue10_UInt8_5_io_deq_valid : _T_3434 ? _Queue10_UInt8_4_io_deq_valid : _T_3433 ? _Queue10_UInt8_3_io_deq_valid : _T_3432 ? _Queue10_UInt8_2_io_deq_valid : _T_3431 ? _Queue10_UInt8_1_io_deq_valid : _T_3430 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_95 = _remapindex_T_6 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_6 = _GEN_95[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3462 = remapindex_6 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3463 = remapindex_6 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3464 = remapindex_6 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3465 = remapindex_6 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3466 = remapindex_6 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3467 = remapindex_6 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3468 = remapindex_6 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3469 = remapindex_6 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3470 = remapindex_6 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3471 = remapindex_6 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3472 = remapindex_6 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3473 = remapindex_6 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3474 = remapindex_6 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3475 = remapindex_6 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3476 = remapindex_6 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3477 = remapindex_6 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3478 = remapindex_6 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3479 = remapindex_6 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3480 = remapindex_6 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3481 = remapindex_6 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3482 = remapindex_6 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3483 = remapindex_6 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3484 = remapindex_6 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3485 = remapindex_6 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3486 = remapindex_6 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3487 = remapindex_6 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3488 = remapindex_6 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3489 = remapindex_6 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3490 = remapindex_6 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3491 = remapindex_6 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3492 = remapindex_6 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3493 = remapindex_6 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_6 = _T_3493 ? _Queue10_UInt8_31_io_deq_bits : _T_3492 ? _Queue10_UInt8_30_io_deq_bits : _T_3491 ? _Queue10_UInt8_29_io_deq_bits : _T_3490 ? _Queue10_UInt8_28_io_deq_bits : _T_3489 ? _Queue10_UInt8_27_io_deq_bits : _T_3488 ? _Queue10_UInt8_26_io_deq_bits : _T_3487 ? _Queue10_UInt8_25_io_deq_bits : _T_3486 ? _Queue10_UInt8_24_io_deq_bits : _T_3485 ? _Queue10_UInt8_23_io_deq_bits : _T_3484 ? _Queue10_UInt8_22_io_deq_bits : _T_3483 ? _Queue10_UInt8_21_io_deq_bits : _T_3482 ? _Queue10_UInt8_20_io_deq_bits : _T_3481 ? _Queue10_UInt8_19_io_deq_bits : _T_3480 ? _Queue10_UInt8_18_io_deq_bits : _T_3479 ? _Queue10_UInt8_17_io_deq_bits : _T_3478 ? _Queue10_UInt8_16_io_deq_bits : _T_3477 ? _Queue10_UInt8_15_io_deq_bits : _T_3476 ? _Queue10_UInt8_14_io_deq_bits : _T_3475 ? _Queue10_UInt8_13_io_deq_bits : _T_3474 ? _Queue10_UInt8_12_io_deq_bits : _T_3473 ? _Queue10_UInt8_11_io_deq_bits : _T_3472 ? _Queue10_UInt8_10_io_deq_bits : _T_3471 ? _Queue10_UInt8_9_io_deq_bits : _T_3470 ? _Queue10_UInt8_8_io_deq_bits : _T_3469 ? _Queue10_UInt8_7_io_deq_bits : _T_3468 ? _Queue10_UInt8_6_io_deq_bits : _T_3467 ? _Queue10_UInt8_5_io_deq_bits : _T_3466 ? _Queue10_UInt8_4_io_deq_bits : _T_3465 ? _Queue10_UInt8_3_io_deq_bits : _T_3464 ? _Queue10_UInt8_2_io_deq_bits : _T_3463 ? _Queue10_UInt8_1_io_deq_bits : _T_3462 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_6 = _T_3493 ? _Queue10_UInt8_31_io_deq_valid : _T_3492 ? _Queue10_UInt8_30_io_deq_valid : _T_3491 ? _Queue10_UInt8_29_io_deq_valid : _T_3490 ? _Queue10_UInt8_28_io_deq_valid : _T_3489 ? _Queue10_UInt8_27_io_deq_valid : _T_3488 ? _Queue10_UInt8_26_io_deq_valid : _T_3487 ? _Queue10_UInt8_25_io_deq_valid : _T_3486 ? _Queue10_UInt8_24_io_deq_valid : _T_3485 ? _Queue10_UInt8_23_io_deq_valid : _T_3484 ? _Queue10_UInt8_22_io_deq_valid : _T_3483 ? _Queue10_UInt8_21_io_deq_valid : _T_3482 ? _Queue10_UInt8_20_io_deq_valid : _T_3481 ? _Queue10_UInt8_19_io_deq_valid : _T_3480 ? _Queue10_UInt8_18_io_deq_valid : _T_3479 ? _Queue10_UInt8_17_io_deq_valid : _T_3478 ? _Queue10_UInt8_16_io_deq_valid : _T_3477 ? _Queue10_UInt8_15_io_deq_valid : _T_3476 ? _Queue10_UInt8_14_io_deq_valid : _T_3475 ? _Queue10_UInt8_13_io_deq_valid : _T_3474 ? _Queue10_UInt8_12_io_deq_valid : _T_3473 ? _Queue10_UInt8_11_io_deq_valid : _T_3472 ? _Queue10_UInt8_10_io_deq_valid : _T_3471 ? _Queue10_UInt8_9_io_deq_valid : _T_3470 ? _Queue10_UInt8_8_io_deq_valid : _T_3469 ? _Queue10_UInt8_7_io_deq_valid : _T_3468 ? _Queue10_UInt8_6_io_deq_valid : _T_3467 ? _Queue10_UInt8_5_io_deq_valid : _T_3466 ? _Queue10_UInt8_4_io_deq_valid : _T_3465 ? _Queue10_UInt8_3_io_deq_valid : _T_3464 ? _Queue10_UInt8_2_io_deq_valid : _T_3463 ? _Queue10_UInt8_1_io_deq_valid : _T_3462 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_96 = _remapindex_T_7 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_7 = _GEN_96[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3494 = remapindex_7 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3495 = remapindex_7 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3496 = remapindex_7 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3497 = remapindex_7 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3498 = remapindex_7 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3499 = remapindex_7 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3500 = remapindex_7 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3501 = remapindex_7 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3502 = remapindex_7 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3503 = remapindex_7 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3504 = remapindex_7 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3505 = remapindex_7 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3506 = remapindex_7 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3507 = remapindex_7 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3508 = remapindex_7 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3509 = remapindex_7 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3510 = remapindex_7 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3511 = remapindex_7 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3512 = remapindex_7 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3513 = remapindex_7 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3514 = remapindex_7 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3515 = remapindex_7 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3516 = remapindex_7 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3517 = remapindex_7 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3518 = remapindex_7 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3519 = remapindex_7 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3520 = remapindex_7 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3521 = remapindex_7 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3522 = remapindex_7 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3523 = remapindex_7 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3524 = remapindex_7 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3525 = remapindex_7 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_7 = _T_3525 ? _Queue10_UInt8_31_io_deq_bits : _T_3524 ? _Queue10_UInt8_30_io_deq_bits : _T_3523 ? _Queue10_UInt8_29_io_deq_bits : _T_3522 ? _Queue10_UInt8_28_io_deq_bits : _T_3521 ? _Queue10_UInt8_27_io_deq_bits : _T_3520 ? _Queue10_UInt8_26_io_deq_bits : _T_3519 ? _Queue10_UInt8_25_io_deq_bits : _T_3518 ? _Queue10_UInt8_24_io_deq_bits : _T_3517 ? _Queue10_UInt8_23_io_deq_bits : _T_3516 ? _Queue10_UInt8_22_io_deq_bits : _T_3515 ? _Queue10_UInt8_21_io_deq_bits : _T_3514 ? _Queue10_UInt8_20_io_deq_bits : _T_3513 ? _Queue10_UInt8_19_io_deq_bits : _T_3512 ? _Queue10_UInt8_18_io_deq_bits : _T_3511 ? _Queue10_UInt8_17_io_deq_bits : _T_3510 ? _Queue10_UInt8_16_io_deq_bits : _T_3509 ? _Queue10_UInt8_15_io_deq_bits : _T_3508 ? _Queue10_UInt8_14_io_deq_bits : _T_3507 ? _Queue10_UInt8_13_io_deq_bits : _T_3506 ? _Queue10_UInt8_12_io_deq_bits : _T_3505 ? _Queue10_UInt8_11_io_deq_bits : _T_3504 ? _Queue10_UInt8_10_io_deq_bits : _T_3503 ? _Queue10_UInt8_9_io_deq_bits : _T_3502 ? _Queue10_UInt8_8_io_deq_bits : _T_3501 ? _Queue10_UInt8_7_io_deq_bits : _T_3500 ? _Queue10_UInt8_6_io_deq_bits : _T_3499 ? _Queue10_UInt8_5_io_deq_bits : _T_3498 ? _Queue10_UInt8_4_io_deq_bits : _T_3497 ? _Queue10_UInt8_3_io_deq_bits : _T_3496 ? _Queue10_UInt8_2_io_deq_bits : _T_3495 ? _Queue10_UInt8_1_io_deq_bits : _T_3494 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_7 = _T_3525 ? _Queue10_UInt8_31_io_deq_valid : _T_3524 ? _Queue10_UInt8_30_io_deq_valid : _T_3523 ? _Queue10_UInt8_29_io_deq_valid : _T_3522 ? _Queue10_UInt8_28_io_deq_valid : _T_3521 ? _Queue10_UInt8_27_io_deq_valid : _T_3520 ? _Queue10_UInt8_26_io_deq_valid : _T_3519 ? _Queue10_UInt8_25_io_deq_valid : _T_3518 ? _Queue10_UInt8_24_io_deq_valid : _T_3517 ? _Queue10_UInt8_23_io_deq_valid : _T_3516 ? _Queue10_UInt8_22_io_deq_valid : _T_3515 ? _Queue10_UInt8_21_io_deq_valid : _T_3514 ? _Queue10_UInt8_20_io_deq_valid : _T_3513 ? _Queue10_UInt8_19_io_deq_valid : _T_3512 ? _Queue10_UInt8_18_io_deq_valid : _T_3511 ? _Queue10_UInt8_17_io_deq_valid : _T_3510 ? _Queue10_UInt8_16_io_deq_valid : _T_3509 ? _Queue10_UInt8_15_io_deq_valid : _T_3508 ? _Queue10_UInt8_14_io_deq_valid : _T_3507 ? _Queue10_UInt8_13_io_deq_valid : _T_3506 ? _Queue10_UInt8_12_io_deq_valid : _T_3505 ? _Queue10_UInt8_11_io_deq_valid : _T_3504 ? _Queue10_UInt8_10_io_deq_valid : _T_3503 ? _Queue10_UInt8_9_io_deq_valid : _T_3502 ? _Queue10_UInt8_8_io_deq_valid : _T_3501 ? _Queue10_UInt8_7_io_deq_valid : _T_3500 ? _Queue10_UInt8_6_io_deq_valid : _T_3499 ? _Queue10_UInt8_5_io_deq_valid : _T_3498 ? _Queue10_UInt8_4_io_deq_valid : _T_3497 ? _Queue10_UInt8_3_io_deq_valid : _T_3496 ? _Queue10_UInt8_2_io_deq_valid : _T_3495 ? _Queue10_UInt8_1_io_deq_valid : _T_3494 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_97 = _remapindex_T_8 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_8 = _GEN_97[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3526 = remapindex_8 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3527 = remapindex_8 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3528 = remapindex_8 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3529 = remapindex_8 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3530 = remapindex_8 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3531 = remapindex_8 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3532 = remapindex_8 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3533 = remapindex_8 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3534 = remapindex_8 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3535 = remapindex_8 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3536 = remapindex_8 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3537 = remapindex_8 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3538 = remapindex_8 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3539 = remapindex_8 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3540 = remapindex_8 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3541 = remapindex_8 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3542 = remapindex_8 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3543 = remapindex_8 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3544 = remapindex_8 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3545 = remapindex_8 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3546 = remapindex_8 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3547 = remapindex_8 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3548 = remapindex_8 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3549 = remapindex_8 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3550 = remapindex_8 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3551 = remapindex_8 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3552 = remapindex_8 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3553 = remapindex_8 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3554 = remapindex_8 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3555 = remapindex_8 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3556 = remapindex_8 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3557 = remapindex_8 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_8 = _T_3557 ? _Queue10_UInt8_31_io_deq_bits : _T_3556 ? _Queue10_UInt8_30_io_deq_bits : _T_3555 ? _Queue10_UInt8_29_io_deq_bits : _T_3554 ? _Queue10_UInt8_28_io_deq_bits : _T_3553 ? _Queue10_UInt8_27_io_deq_bits : _T_3552 ? _Queue10_UInt8_26_io_deq_bits : _T_3551 ? _Queue10_UInt8_25_io_deq_bits : _T_3550 ? _Queue10_UInt8_24_io_deq_bits : _T_3549 ? _Queue10_UInt8_23_io_deq_bits : _T_3548 ? _Queue10_UInt8_22_io_deq_bits : _T_3547 ? _Queue10_UInt8_21_io_deq_bits : _T_3546 ? _Queue10_UInt8_20_io_deq_bits : _T_3545 ? _Queue10_UInt8_19_io_deq_bits : _T_3544 ? _Queue10_UInt8_18_io_deq_bits : _T_3543 ? _Queue10_UInt8_17_io_deq_bits : _T_3542 ? _Queue10_UInt8_16_io_deq_bits : _T_3541 ? _Queue10_UInt8_15_io_deq_bits : _T_3540 ? _Queue10_UInt8_14_io_deq_bits : _T_3539 ? _Queue10_UInt8_13_io_deq_bits : _T_3538 ? _Queue10_UInt8_12_io_deq_bits : _T_3537 ? _Queue10_UInt8_11_io_deq_bits : _T_3536 ? _Queue10_UInt8_10_io_deq_bits : _T_3535 ? _Queue10_UInt8_9_io_deq_bits : _T_3534 ? _Queue10_UInt8_8_io_deq_bits : _T_3533 ? _Queue10_UInt8_7_io_deq_bits : _T_3532 ? _Queue10_UInt8_6_io_deq_bits : _T_3531 ? _Queue10_UInt8_5_io_deq_bits : _T_3530 ? _Queue10_UInt8_4_io_deq_bits : _T_3529 ? _Queue10_UInt8_3_io_deq_bits : _T_3528 ? _Queue10_UInt8_2_io_deq_bits : _T_3527 ? _Queue10_UInt8_1_io_deq_bits : _T_3526 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_8 = _T_3557 ? _Queue10_UInt8_31_io_deq_valid : _T_3556 ? _Queue10_UInt8_30_io_deq_valid : _T_3555 ? _Queue10_UInt8_29_io_deq_valid : _T_3554 ? _Queue10_UInt8_28_io_deq_valid : _T_3553 ? _Queue10_UInt8_27_io_deq_valid : _T_3552 ? _Queue10_UInt8_26_io_deq_valid : _T_3551 ? _Queue10_UInt8_25_io_deq_valid : _T_3550 ? _Queue10_UInt8_24_io_deq_valid : _T_3549 ? _Queue10_UInt8_23_io_deq_valid : _T_3548 ? _Queue10_UInt8_22_io_deq_valid : _T_3547 ? _Queue10_UInt8_21_io_deq_valid : _T_3546 ? _Queue10_UInt8_20_io_deq_valid : _T_3545 ? _Queue10_UInt8_19_io_deq_valid : _T_3544 ? _Queue10_UInt8_18_io_deq_valid : _T_3543 ? _Queue10_UInt8_17_io_deq_valid : _T_3542 ? _Queue10_UInt8_16_io_deq_valid : _T_3541 ? _Queue10_UInt8_15_io_deq_valid : _T_3540 ? _Queue10_UInt8_14_io_deq_valid : _T_3539 ? _Queue10_UInt8_13_io_deq_valid : _T_3538 ? _Queue10_UInt8_12_io_deq_valid : _T_3537 ? _Queue10_UInt8_11_io_deq_valid : _T_3536 ? _Queue10_UInt8_10_io_deq_valid : _T_3535 ? _Queue10_UInt8_9_io_deq_valid : _T_3534 ? _Queue10_UInt8_8_io_deq_valid : _T_3533 ? _Queue10_UInt8_7_io_deq_valid : _T_3532 ? _Queue10_UInt8_6_io_deq_valid : _T_3531 ? _Queue10_UInt8_5_io_deq_valid : _T_3530 ? _Queue10_UInt8_4_io_deq_valid : _T_3529 ? _Queue10_UInt8_3_io_deq_valid : _T_3528 ? _Queue10_UInt8_2_io_deq_valid : _T_3527 ? _Queue10_UInt8_1_io_deq_valid : _T_3526 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_98 = _remapindex_T_9 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_9 = _GEN_98[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3558 = remapindex_9 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3559 = remapindex_9 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3560 = remapindex_9 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3561 = remapindex_9 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3562 = remapindex_9 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3563 = remapindex_9 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3564 = remapindex_9 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3565 = remapindex_9 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3566 = remapindex_9 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3567 = remapindex_9 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3568 = remapindex_9 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3569 = remapindex_9 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3570 = remapindex_9 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3571 = remapindex_9 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3572 = remapindex_9 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3573 = remapindex_9 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3574 = remapindex_9 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3575 = remapindex_9 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3576 = remapindex_9 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3577 = remapindex_9 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3578 = remapindex_9 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3579 = remapindex_9 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3580 = remapindex_9 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3581 = remapindex_9 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3582 = remapindex_9 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3583 = remapindex_9 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3584 = remapindex_9 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3585 = remapindex_9 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3586 = remapindex_9 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3587 = remapindex_9 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3588 = remapindex_9 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3589 = remapindex_9 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_9 = _T_3589 ? _Queue10_UInt8_31_io_deq_bits : _T_3588 ? _Queue10_UInt8_30_io_deq_bits : _T_3587 ? _Queue10_UInt8_29_io_deq_bits : _T_3586 ? _Queue10_UInt8_28_io_deq_bits : _T_3585 ? _Queue10_UInt8_27_io_deq_bits : _T_3584 ? _Queue10_UInt8_26_io_deq_bits : _T_3583 ? _Queue10_UInt8_25_io_deq_bits : _T_3582 ? _Queue10_UInt8_24_io_deq_bits : _T_3581 ? _Queue10_UInt8_23_io_deq_bits : _T_3580 ? _Queue10_UInt8_22_io_deq_bits : _T_3579 ? _Queue10_UInt8_21_io_deq_bits : _T_3578 ? _Queue10_UInt8_20_io_deq_bits : _T_3577 ? _Queue10_UInt8_19_io_deq_bits : _T_3576 ? _Queue10_UInt8_18_io_deq_bits : _T_3575 ? _Queue10_UInt8_17_io_deq_bits : _T_3574 ? _Queue10_UInt8_16_io_deq_bits : _T_3573 ? _Queue10_UInt8_15_io_deq_bits : _T_3572 ? _Queue10_UInt8_14_io_deq_bits : _T_3571 ? _Queue10_UInt8_13_io_deq_bits : _T_3570 ? _Queue10_UInt8_12_io_deq_bits : _T_3569 ? _Queue10_UInt8_11_io_deq_bits : _T_3568 ? _Queue10_UInt8_10_io_deq_bits : _T_3567 ? _Queue10_UInt8_9_io_deq_bits : _T_3566 ? _Queue10_UInt8_8_io_deq_bits : _T_3565 ? _Queue10_UInt8_7_io_deq_bits : _T_3564 ? _Queue10_UInt8_6_io_deq_bits : _T_3563 ? _Queue10_UInt8_5_io_deq_bits : _T_3562 ? _Queue10_UInt8_4_io_deq_bits : _T_3561 ? _Queue10_UInt8_3_io_deq_bits : _T_3560 ? _Queue10_UInt8_2_io_deq_bits : _T_3559 ? _Queue10_UInt8_1_io_deq_bits : _T_3558 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_9 = _T_3589 ? _Queue10_UInt8_31_io_deq_valid : _T_3588 ? _Queue10_UInt8_30_io_deq_valid : _T_3587 ? _Queue10_UInt8_29_io_deq_valid : _T_3586 ? _Queue10_UInt8_28_io_deq_valid : _T_3585 ? _Queue10_UInt8_27_io_deq_valid : _T_3584 ? _Queue10_UInt8_26_io_deq_valid : _T_3583 ? _Queue10_UInt8_25_io_deq_valid : _T_3582 ? _Queue10_UInt8_24_io_deq_valid : _T_3581 ? _Queue10_UInt8_23_io_deq_valid : _T_3580 ? _Queue10_UInt8_22_io_deq_valid : _T_3579 ? _Queue10_UInt8_21_io_deq_valid : _T_3578 ? _Queue10_UInt8_20_io_deq_valid : _T_3577 ? _Queue10_UInt8_19_io_deq_valid : _T_3576 ? _Queue10_UInt8_18_io_deq_valid : _T_3575 ? _Queue10_UInt8_17_io_deq_valid : _T_3574 ? _Queue10_UInt8_16_io_deq_valid : _T_3573 ? _Queue10_UInt8_15_io_deq_valid : _T_3572 ? _Queue10_UInt8_14_io_deq_valid : _T_3571 ? _Queue10_UInt8_13_io_deq_valid : _T_3570 ? _Queue10_UInt8_12_io_deq_valid : _T_3569 ? _Queue10_UInt8_11_io_deq_valid : _T_3568 ? _Queue10_UInt8_10_io_deq_valid : _T_3567 ? _Queue10_UInt8_9_io_deq_valid : _T_3566 ? _Queue10_UInt8_8_io_deq_valid : _T_3565 ? _Queue10_UInt8_7_io_deq_valid : _T_3564 ? _Queue10_UInt8_6_io_deq_valid : _T_3563 ? _Queue10_UInt8_5_io_deq_valid : _T_3562 ? _Queue10_UInt8_4_io_deq_valid : _T_3561 ? _Queue10_UInt8_3_io_deq_valid : _T_3560 ? _Queue10_UInt8_2_io_deq_valid : _T_3559 ? _Queue10_UInt8_1_io_deq_valid : _T_3558 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_99 = _remapindex_T_10 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_10 = _GEN_99[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3590 = remapindex_10 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3591 = remapindex_10 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3592 = remapindex_10 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3593 = remapindex_10 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3594 = remapindex_10 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3595 = remapindex_10 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3596 = remapindex_10 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3597 = remapindex_10 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3598 = remapindex_10 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3599 = remapindex_10 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3600 = remapindex_10 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3601 = remapindex_10 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3602 = remapindex_10 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3603 = remapindex_10 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3604 = remapindex_10 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3605 = remapindex_10 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3606 = remapindex_10 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3607 = remapindex_10 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3608 = remapindex_10 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3609 = remapindex_10 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3610 = remapindex_10 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3611 = remapindex_10 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3612 = remapindex_10 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3613 = remapindex_10 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3614 = remapindex_10 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3615 = remapindex_10 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3616 = remapindex_10 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3617 = remapindex_10 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3618 = remapindex_10 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3619 = remapindex_10 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3620 = remapindex_10 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3621 = remapindex_10 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_10 = _T_3621 ? _Queue10_UInt8_31_io_deq_bits : _T_3620 ? _Queue10_UInt8_30_io_deq_bits : _T_3619 ? _Queue10_UInt8_29_io_deq_bits : _T_3618 ? _Queue10_UInt8_28_io_deq_bits : _T_3617 ? _Queue10_UInt8_27_io_deq_bits : _T_3616 ? _Queue10_UInt8_26_io_deq_bits : _T_3615 ? _Queue10_UInt8_25_io_deq_bits : _T_3614 ? _Queue10_UInt8_24_io_deq_bits : _T_3613 ? _Queue10_UInt8_23_io_deq_bits : _T_3612 ? _Queue10_UInt8_22_io_deq_bits : _T_3611 ? _Queue10_UInt8_21_io_deq_bits : _T_3610 ? _Queue10_UInt8_20_io_deq_bits : _T_3609 ? _Queue10_UInt8_19_io_deq_bits : _T_3608 ? _Queue10_UInt8_18_io_deq_bits : _T_3607 ? _Queue10_UInt8_17_io_deq_bits : _T_3606 ? _Queue10_UInt8_16_io_deq_bits : _T_3605 ? _Queue10_UInt8_15_io_deq_bits : _T_3604 ? _Queue10_UInt8_14_io_deq_bits : _T_3603 ? _Queue10_UInt8_13_io_deq_bits : _T_3602 ? _Queue10_UInt8_12_io_deq_bits : _T_3601 ? _Queue10_UInt8_11_io_deq_bits : _T_3600 ? _Queue10_UInt8_10_io_deq_bits : _T_3599 ? _Queue10_UInt8_9_io_deq_bits : _T_3598 ? _Queue10_UInt8_8_io_deq_bits : _T_3597 ? _Queue10_UInt8_7_io_deq_bits : _T_3596 ? _Queue10_UInt8_6_io_deq_bits : _T_3595 ? _Queue10_UInt8_5_io_deq_bits : _T_3594 ? _Queue10_UInt8_4_io_deq_bits : _T_3593 ? _Queue10_UInt8_3_io_deq_bits : _T_3592 ? _Queue10_UInt8_2_io_deq_bits : _T_3591 ? _Queue10_UInt8_1_io_deq_bits : _T_3590 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_10 = _T_3621 ? _Queue10_UInt8_31_io_deq_valid : _T_3620 ? _Queue10_UInt8_30_io_deq_valid : _T_3619 ? _Queue10_UInt8_29_io_deq_valid : _T_3618 ? _Queue10_UInt8_28_io_deq_valid : _T_3617 ? _Queue10_UInt8_27_io_deq_valid : _T_3616 ? _Queue10_UInt8_26_io_deq_valid : _T_3615 ? _Queue10_UInt8_25_io_deq_valid : _T_3614 ? _Queue10_UInt8_24_io_deq_valid : _T_3613 ? _Queue10_UInt8_23_io_deq_valid : _T_3612 ? _Queue10_UInt8_22_io_deq_valid : _T_3611 ? _Queue10_UInt8_21_io_deq_valid : _T_3610 ? _Queue10_UInt8_20_io_deq_valid : _T_3609 ? _Queue10_UInt8_19_io_deq_valid : _T_3608 ? _Queue10_UInt8_18_io_deq_valid : _T_3607 ? _Queue10_UInt8_17_io_deq_valid : _T_3606 ? _Queue10_UInt8_16_io_deq_valid : _T_3605 ? _Queue10_UInt8_15_io_deq_valid : _T_3604 ? _Queue10_UInt8_14_io_deq_valid : _T_3603 ? _Queue10_UInt8_13_io_deq_valid : _T_3602 ? _Queue10_UInt8_12_io_deq_valid : _T_3601 ? _Queue10_UInt8_11_io_deq_valid : _T_3600 ? _Queue10_UInt8_10_io_deq_valid : _T_3599 ? _Queue10_UInt8_9_io_deq_valid : _T_3598 ? _Queue10_UInt8_8_io_deq_valid : _T_3597 ? _Queue10_UInt8_7_io_deq_valid : _T_3596 ? _Queue10_UInt8_6_io_deq_valid : _T_3595 ? _Queue10_UInt8_5_io_deq_valid : _T_3594 ? _Queue10_UInt8_4_io_deq_valid : _T_3593 ? _Queue10_UInt8_3_io_deq_valid : _T_3592 ? _Queue10_UInt8_2_io_deq_valid : _T_3591 ? _Queue10_UInt8_1_io_deq_valid : _T_3590 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_100 = _remapindex_T_11 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_11 = _GEN_100[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3622 = remapindex_11 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3623 = remapindex_11 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3624 = remapindex_11 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3625 = remapindex_11 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3626 = remapindex_11 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3627 = remapindex_11 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3628 = remapindex_11 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3629 = remapindex_11 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3630 = remapindex_11 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3631 = remapindex_11 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3632 = remapindex_11 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3633 = remapindex_11 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3634 = remapindex_11 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3635 = remapindex_11 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3636 = remapindex_11 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3637 = remapindex_11 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3638 = remapindex_11 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3639 = remapindex_11 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3640 = remapindex_11 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3641 = remapindex_11 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3642 = remapindex_11 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3643 = remapindex_11 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3644 = remapindex_11 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3645 = remapindex_11 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3646 = remapindex_11 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3647 = remapindex_11 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3648 = remapindex_11 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3649 = remapindex_11 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3650 = remapindex_11 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3651 = remapindex_11 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3652 = remapindex_11 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3653 = remapindex_11 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_11 = _T_3653 ? _Queue10_UInt8_31_io_deq_bits : _T_3652 ? _Queue10_UInt8_30_io_deq_bits : _T_3651 ? _Queue10_UInt8_29_io_deq_bits : _T_3650 ? _Queue10_UInt8_28_io_deq_bits : _T_3649 ? _Queue10_UInt8_27_io_deq_bits : _T_3648 ? _Queue10_UInt8_26_io_deq_bits : _T_3647 ? _Queue10_UInt8_25_io_deq_bits : _T_3646 ? _Queue10_UInt8_24_io_deq_bits : _T_3645 ? _Queue10_UInt8_23_io_deq_bits : _T_3644 ? _Queue10_UInt8_22_io_deq_bits : _T_3643 ? _Queue10_UInt8_21_io_deq_bits : _T_3642 ? _Queue10_UInt8_20_io_deq_bits : _T_3641 ? _Queue10_UInt8_19_io_deq_bits : _T_3640 ? _Queue10_UInt8_18_io_deq_bits : _T_3639 ? _Queue10_UInt8_17_io_deq_bits : _T_3638 ? _Queue10_UInt8_16_io_deq_bits : _T_3637 ? _Queue10_UInt8_15_io_deq_bits : _T_3636 ? _Queue10_UInt8_14_io_deq_bits : _T_3635 ? _Queue10_UInt8_13_io_deq_bits : _T_3634 ? _Queue10_UInt8_12_io_deq_bits : _T_3633 ? _Queue10_UInt8_11_io_deq_bits : _T_3632 ? _Queue10_UInt8_10_io_deq_bits : _T_3631 ? _Queue10_UInt8_9_io_deq_bits : _T_3630 ? _Queue10_UInt8_8_io_deq_bits : _T_3629 ? _Queue10_UInt8_7_io_deq_bits : _T_3628 ? _Queue10_UInt8_6_io_deq_bits : _T_3627 ? _Queue10_UInt8_5_io_deq_bits : _T_3626 ? _Queue10_UInt8_4_io_deq_bits : _T_3625 ? _Queue10_UInt8_3_io_deq_bits : _T_3624 ? _Queue10_UInt8_2_io_deq_bits : _T_3623 ? _Queue10_UInt8_1_io_deq_bits : _T_3622 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_11 = _T_3653 ? _Queue10_UInt8_31_io_deq_valid : _T_3652 ? _Queue10_UInt8_30_io_deq_valid : _T_3651 ? _Queue10_UInt8_29_io_deq_valid : _T_3650 ? _Queue10_UInt8_28_io_deq_valid : _T_3649 ? _Queue10_UInt8_27_io_deq_valid : _T_3648 ? _Queue10_UInt8_26_io_deq_valid : _T_3647 ? _Queue10_UInt8_25_io_deq_valid : _T_3646 ? _Queue10_UInt8_24_io_deq_valid : _T_3645 ? _Queue10_UInt8_23_io_deq_valid : _T_3644 ? _Queue10_UInt8_22_io_deq_valid : _T_3643 ? _Queue10_UInt8_21_io_deq_valid : _T_3642 ? _Queue10_UInt8_20_io_deq_valid : _T_3641 ? _Queue10_UInt8_19_io_deq_valid : _T_3640 ? _Queue10_UInt8_18_io_deq_valid : _T_3639 ? _Queue10_UInt8_17_io_deq_valid : _T_3638 ? _Queue10_UInt8_16_io_deq_valid : _T_3637 ? _Queue10_UInt8_15_io_deq_valid : _T_3636 ? _Queue10_UInt8_14_io_deq_valid : _T_3635 ? _Queue10_UInt8_13_io_deq_valid : _T_3634 ? _Queue10_UInt8_12_io_deq_valid : _T_3633 ? _Queue10_UInt8_11_io_deq_valid : _T_3632 ? _Queue10_UInt8_10_io_deq_valid : _T_3631 ? _Queue10_UInt8_9_io_deq_valid : _T_3630 ? _Queue10_UInt8_8_io_deq_valid : _T_3629 ? _Queue10_UInt8_7_io_deq_valid : _T_3628 ? _Queue10_UInt8_6_io_deq_valid : _T_3627 ? _Queue10_UInt8_5_io_deq_valid : _T_3626 ? _Queue10_UInt8_4_io_deq_valid : _T_3625 ? _Queue10_UInt8_3_io_deq_valid : _T_3624 ? _Queue10_UInt8_2_io_deq_valid : _T_3623 ? _Queue10_UInt8_1_io_deq_valid : _T_3622 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_101 = _remapindex_T_12 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_12 = _GEN_101[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3654 = remapindex_12 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3655 = remapindex_12 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3656 = remapindex_12 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3657 = remapindex_12 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3658 = remapindex_12 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3659 = remapindex_12 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3660 = remapindex_12 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3661 = remapindex_12 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3662 = remapindex_12 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3663 = remapindex_12 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3664 = remapindex_12 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3665 = remapindex_12 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3666 = remapindex_12 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3667 = remapindex_12 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3668 = remapindex_12 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3669 = remapindex_12 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3670 = remapindex_12 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3671 = remapindex_12 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3672 = remapindex_12 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3673 = remapindex_12 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3674 = remapindex_12 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3675 = remapindex_12 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3676 = remapindex_12 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3677 = remapindex_12 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3678 = remapindex_12 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3679 = remapindex_12 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3680 = remapindex_12 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3681 = remapindex_12 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3682 = remapindex_12 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3683 = remapindex_12 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3684 = remapindex_12 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3685 = remapindex_12 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_12 = _T_3685 ? _Queue10_UInt8_31_io_deq_bits : _T_3684 ? _Queue10_UInt8_30_io_deq_bits : _T_3683 ? _Queue10_UInt8_29_io_deq_bits : _T_3682 ? _Queue10_UInt8_28_io_deq_bits : _T_3681 ? _Queue10_UInt8_27_io_deq_bits : _T_3680 ? _Queue10_UInt8_26_io_deq_bits : _T_3679 ? _Queue10_UInt8_25_io_deq_bits : _T_3678 ? _Queue10_UInt8_24_io_deq_bits : _T_3677 ? _Queue10_UInt8_23_io_deq_bits : _T_3676 ? _Queue10_UInt8_22_io_deq_bits : _T_3675 ? _Queue10_UInt8_21_io_deq_bits : _T_3674 ? _Queue10_UInt8_20_io_deq_bits : _T_3673 ? _Queue10_UInt8_19_io_deq_bits : _T_3672 ? _Queue10_UInt8_18_io_deq_bits : _T_3671 ? _Queue10_UInt8_17_io_deq_bits : _T_3670 ? _Queue10_UInt8_16_io_deq_bits : _T_3669 ? _Queue10_UInt8_15_io_deq_bits : _T_3668 ? _Queue10_UInt8_14_io_deq_bits : _T_3667 ? _Queue10_UInt8_13_io_deq_bits : _T_3666 ? _Queue10_UInt8_12_io_deq_bits : _T_3665 ? _Queue10_UInt8_11_io_deq_bits : _T_3664 ? _Queue10_UInt8_10_io_deq_bits : _T_3663 ? _Queue10_UInt8_9_io_deq_bits : _T_3662 ? _Queue10_UInt8_8_io_deq_bits : _T_3661 ? _Queue10_UInt8_7_io_deq_bits : _T_3660 ? _Queue10_UInt8_6_io_deq_bits : _T_3659 ? _Queue10_UInt8_5_io_deq_bits : _T_3658 ? _Queue10_UInt8_4_io_deq_bits : _T_3657 ? _Queue10_UInt8_3_io_deq_bits : _T_3656 ? _Queue10_UInt8_2_io_deq_bits : _T_3655 ? _Queue10_UInt8_1_io_deq_bits : _T_3654 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_12 = _T_3685 ? _Queue10_UInt8_31_io_deq_valid : _T_3684 ? _Queue10_UInt8_30_io_deq_valid : _T_3683 ? _Queue10_UInt8_29_io_deq_valid : _T_3682 ? _Queue10_UInt8_28_io_deq_valid : _T_3681 ? _Queue10_UInt8_27_io_deq_valid : _T_3680 ? _Queue10_UInt8_26_io_deq_valid : _T_3679 ? _Queue10_UInt8_25_io_deq_valid : _T_3678 ? _Queue10_UInt8_24_io_deq_valid : _T_3677 ? _Queue10_UInt8_23_io_deq_valid : _T_3676 ? _Queue10_UInt8_22_io_deq_valid : _T_3675 ? _Queue10_UInt8_21_io_deq_valid : _T_3674 ? _Queue10_UInt8_20_io_deq_valid : _T_3673 ? _Queue10_UInt8_19_io_deq_valid : _T_3672 ? _Queue10_UInt8_18_io_deq_valid : _T_3671 ? _Queue10_UInt8_17_io_deq_valid : _T_3670 ? _Queue10_UInt8_16_io_deq_valid : _T_3669 ? _Queue10_UInt8_15_io_deq_valid : _T_3668 ? _Queue10_UInt8_14_io_deq_valid : _T_3667 ? _Queue10_UInt8_13_io_deq_valid : _T_3666 ? _Queue10_UInt8_12_io_deq_valid : _T_3665 ? _Queue10_UInt8_11_io_deq_valid : _T_3664 ? _Queue10_UInt8_10_io_deq_valid : _T_3663 ? _Queue10_UInt8_9_io_deq_valid : _T_3662 ? _Queue10_UInt8_8_io_deq_valid : _T_3661 ? _Queue10_UInt8_7_io_deq_valid : _T_3660 ? _Queue10_UInt8_6_io_deq_valid : _T_3659 ? _Queue10_UInt8_5_io_deq_valid : _T_3658 ? _Queue10_UInt8_4_io_deq_valid : _T_3657 ? _Queue10_UInt8_3_io_deq_valid : _T_3656 ? _Queue10_UInt8_2_io_deq_valid : _T_3655 ? _Queue10_UInt8_1_io_deq_valid : _T_3654 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_102 = _remapindex_T_13 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_13 = _GEN_102[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3686 = remapindex_13 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3687 = remapindex_13 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3688 = remapindex_13 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3689 = remapindex_13 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3690 = remapindex_13 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3691 = remapindex_13 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3692 = remapindex_13 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3693 = remapindex_13 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3694 = remapindex_13 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3695 = remapindex_13 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3696 = remapindex_13 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3697 = remapindex_13 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3698 = remapindex_13 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3699 = remapindex_13 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3700 = remapindex_13 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3701 = remapindex_13 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3702 = remapindex_13 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3703 = remapindex_13 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3704 = remapindex_13 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3705 = remapindex_13 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3706 = remapindex_13 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3707 = remapindex_13 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3708 = remapindex_13 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3709 = remapindex_13 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3710 = remapindex_13 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3711 = remapindex_13 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3712 = remapindex_13 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3713 = remapindex_13 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3714 = remapindex_13 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3715 = remapindex_13 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3716 = remapindex_13 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3717 = remapindex_13 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_13 = _T_3717 ? _Queue10_UInt8_31_io_deq_bits : _T_3716 ? _Queue10_UInt8_30_io_deq_bits : _T_3715 ? _Queue10_UInt8_29_io_deq_bits : _T_3714 ? _Queue10_UInt8_28_io_deq_bits : _T_3713 ? _Queue10_UInt8_27_io_deq_bits : _T_3712 ? _Queue10_UInt8_26_io_deq_bits : _T_3711 ? _Queue10_UInt8_25_io_deq_bits : _T_3710 ? _Queue10_UInt8_24_io_deq_bits : _T_3709 ? _Queue10_UInt8_23_io_deq_bits : _T_3708 ? _Queue10_UInt8_22_io_deq_bits : _T_3707 ? _Queue10_UInt8_21_io_deq_bits : _T_3706 ? _Queue10_UInt8_20_io_deq_bits : _T_3705 ? _Queue10_UInt8_19_io_deq_bits : _T_3704 ? _Queue10_UInt8_18_io_deq_bits : _T_3703 ? _Queue10_UInt8_17_io_deq_bits : _T_3702 ? _Queue10_UInt8_16_io_deq_bits : _T_3701 ? _Queue10_UInt8_15_io_deq_bits : _T_3700 ? _Queue10_UInt8_14_io_deq_bits : _T_3699 ? _Queue10_UInt8_13_io_deq_bits : _T_3698 ? _Queue10_UInt8_12_io_deq_bits : _T_3697 ? _Queue10_UInt8_11_io_deq_bits : _T_3696 ? _Queue10_UInt8_10_io_deq_bits : _T_3695 ? _Queue10_UInt8_9_io_deq_bits : _T_3694 ? _Queue10_UInt8_8_io_deq_bits : _T_3693 ? _Queue10_UInt8_7_io_deq_bits : _T_3692 ? _Queue10_UInt8_6_io_deq_bits : _T_3691 ? _Queue10_UInt8_5_io_deq_bits : _T_3690 ? _Queue10_UInt8_4_io_deq_bits : _T_3689 ? _Queue10_UInt8_3_io_deq_bits : _T_3688 ? _Queue10_UInt8_2_io_deq_bits : _T_3687 ? _Queue10_UInt8_1_io_deq_bits : _T_3686 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_13 = _T_3717 ? _Queue10_UInt8_31_io_deq_valid : _T_3716 ? _Queue10_UInt8_30_io_deq_valid : _T_3715 ? _Queue10_UInt8_29_io_deq_valid : _T_3714 ? _Queue10_UInt8_28_io_deq_valid : _T_3713 ? _Queue10_UInt8_27_io_deq_valid : _T_3712 ? _Queue10_UInt8_26_io_deq_valid : _T_3711 ? _Queue10_UInt8_25_io_deq_valid : _T_3710 ? _Queue10_UInt8_24_io_deq_valid : _T_3709 ? _Queue10_UInt8_23_io_deq_valid : _T_3708 ? _Queue10_UInt8_22_io_deq_valid : _T_3707 ? _Queue10_UInt8_21_io_deq_valid : _T_3706 ? _Queue10_UInt8_20_io_deq_valid : _T_3705 ? _Queue10_UInt8_19_io_deq_valid : _T_3704 ? _Queue10_UInt8_18_io_deq_valid : _T_3703 ? _Queue10_UInt8_17_io_deq_valid : _T_3702 ? _Queue10_UInt8_16_io_deq_valid : _T_3701 ? _Queue10_UInt8_15_io_deq_valid : _T_3700 ? _Queue10_UInt8_14_io_deq_valid : _T_3699 ? _Queue10_UInt8_13_io_deq_valid : _T_3698 ? _Queue10_UInt8_12_io_deq_valid : _T_3697 ? _Queue10_UInt8_11_io_deq_valid : _T_3696 ? _Queue10_UInt8_10_io_deq_valid : _T_3695 ? _Queue10_UInt8_9_io_deq_valid : _T_3694 ? _Queue10_UInt8_8_io_deq_valid : _T_3693 ? _Queue10_UInt8_7_io_deq_valid : _T_3692 ? _Queue10_UInt8_6_io_deq_valid : _T_3691 ? _Queue10_UInt8_5_io_deq_valid : _T_3690 ? _Queue10_UInt8_4_io_deq_valid : _T_3689 ? _Queue10_UInt8_3_io_deq_valid : _T_3688 ? _Queue10_UInt8_2_io_deq_valid : _T_3687 ? _Queue10_UInt8_1_io_deq_valid : _T_3686 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_103 = _remapindex_T_14 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_14 = _GEN_103[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3718 = remapindex_14 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3719 = remapindex_14 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3720 = remapindex_14 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3721 = remapindex_14 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3722 = remapindex_14 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3723 = remapindex_14 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3724 = remapindex_14 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3725 = remapindex_14 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3726 = remapindex_14 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3727 = remapindex_14 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3728 = remapindex_14 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3729 = remapindex_14 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3730 = remapindex_14 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3731 = remapindex_14 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3732 = remapindex_14 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3733 = remapindex_14 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3734 = remapindex_14 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3735 = remapindex_14 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3736 = remapindex_14 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3737 = remapindex_14 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3738 = remapindex_14 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3739 = remapindex_14 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3740 = remapindex_14 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3741 = remapindex_14 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3742 = remapindex_14 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3743 = remapindex_14 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3744 = remapindex_14 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3745 = remapindex_14 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3746 = remapindex_14 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3747 = remapindex_14 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3748 = remapindex_14 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3749 = remapindex_14 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_14 = _T_3749 ? _Queue10_UInt8_31_io_deq_bits : _T_3748 ? _Queue10_UInt8_30_io_deq_bits : _T_3747 ? _Queue10_UInt8_29_io_deq_bits : _T_3746 ? _Queue10_UInt8_28_io_deq_bits : _T_3745 ? _Queue10_UInt8_27_io_deq_bits : _T_3744 ? _Queue10_UInt8_26_io_deq_bits : _T_3743 ? _Queue10_UInt8_25_io_deq_bits : _T_3742 ? _Queue10_UInt8_24_io_deq_bits : _T_3741 ? _Queue10_UInt8_23_io_deq_bits : _T_3740 ? _Queue10_UInt8_22_io_deq_bits : _T_3739 ? _Queue10_UInt8_21_io_deq_bits : _T_3738 ? _Queue10_UInt8_20_io_deq_bits : _T_3737 ? _Queue10_UInt8_19_io_deq_bits : _T_3736 ? _Queue10_UInt8_18_io_deq_bits : _T_3735 ? _Queue10_UInt8_17_io_deq_bits : _T_3734 ? _Queue10_UInt8_16_io_deq_bits : _T_3733 ? _Queue10_UInt8_15_io_deq_bits : _T_3732 ? _Queue10_UInt8_14_io_deq_bits : _T_3731 ? _Queue10_UInt8_13_io_deq_bits : _T_3730 ? _Queue10_UInt8_12_io_deq_bits : _T_3729 ? _Queue10_UInt8_11_io_deq_bits : _T_3728 ? _Queue10_UInt8_10_io_deq_bits : _T_3727 ? _Queue10_UInt8_9_io_deq_bits : _T_3726 ? _Queue10_UInt8_8_io_deq_bits : _T_3725 ? _Queue10_UInt8_7_io_deq_bits : _T_3724 ? _Queue10_UInt8_6_io_deq_bits : _T_3723 ? _Queue10_UInt8_5_io_deq_bits : _T_3722 ? _Queue10_UInt8_4_io_deq_bits : _T_3721 ? _Queue10_UInt8_3_io_deq_bits : _T_3720 ? _Queue10_UInt8_2_io_deq_bits : _T_3719 ? _Queue10_UInt8_1_io_deq_bits : _T_3718 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_14 = _T_3749 ? _Queue10_UInt8_31_io_deq_valid : _T_3748 ? _Queue10_UInt8_30_io_deq_valid : _T_3747 ? _Queue10_UInt8_29_io_deq_valid : _T_3746 ? _Queue10_UInt8_28_io_deq_valid : _T_3745 ? _Queue10_UInt8_27_io_deq_valid : _T_3744 ? _Queue10_UInt8_26_io_deq_valid : _T_3743 ? _Queue10_UInt8_25_io_deq_valid : _T_3742 ? _Queue10_UInt8_24_io_deq_valid : _T_3741 ? _Queue10_UInt8_23_io_deq_valid : _T_3740 ? _Queue10_UInt8_22_io_deq_valid : _T_3739 ? _Queue10_UInt8_21_io_deq_valid : _T_3738 ? _Queue10_UInt8_20_io_deq_valid : _T_3737 ? _Queue10_UInt8_19_io_deq_valid : _T_3736 ? _Queue10_UInt8_18_io_deq_valid : _T_3735 ? _Queue10_UInt8_17_io_deq_valid : _T_3734 ? _Queue10_UInt8_16_io_deq_valid : _T_3733 ? _Queue10_UInt8_15_io_deq_valid : _T_3732 ? _Queue10_UInt8_14_io_deq_valid : _T_3731 ? _Queue10_UInt8_13_io_deq_valid : _T_3730 ? _Queue10_UInt8_12_io_deq_valid : _T_3729 ? _Queue10_UInt8_11_io_deq_valid : _T_3728 ? _Queue10_UInt8_10_io_deq_valid : _T_3727 ? _Queue10_UInt8_9_io_deq_valid : _T_3726 ? _Queue10_UInt8_8_io_deq_valid : _T_3725 ? _Queue10_UInt8_7_io_deq_valid : _T_3724 ? _Queue10_UInt8_6_io_deq_valid : _T_3723 ? _Queue10_UInt8_5_io_deq_valid : _T_3722 ? _Queue10_UInt8_4_io_deq_valid : _T_3721 ? _Queue10_UInt8_3_io_deq_valid : _T_3720 ? _Queue10_UInt8_2_io_deq_valid : _T_3719 ? _Queue10_UInt8_1_io_deq_valid : _T_3718 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_104 = _remapindex_T_15 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_15 = _GEN_104[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3750 = remapindex_15 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3751 = remapindex_15 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3752 = remapindex_15 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3753 = remapindex_15 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3754 = remapindex_15 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3755 = remapindex_15 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3756 = remapindex_15 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3757 = remapindex_15 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3758 = remapindex_15 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3759 = remapindex_15 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3760 = remapindex_15 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3761 = remapindex_15 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3762 = remapindex_15 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3763 = remapindex_15 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3764 = remapindex_15 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3765 = remapindex_15 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3766 = remapindex_15 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3767 = remapindex_15 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3768 = remapindex_15 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3769 = remapindex_15 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3770 = remapindex_15 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3771 = remapindex_15 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3772 = remapindex_15 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3773 = remapindex_15 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3774 = remapindex_15 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3775 = remapindex_15 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3776 = remapindex_15 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3777 = remapindex_15 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3778 = remapindex_15 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3779 = remapindex_15 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3780 = remapindex_15 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3781 = remapindex_15 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_15 = _T_3781 ? _Queue10_UInt8_31_io_deq_bits : _T_3780 ? _Queue10_UInt8_30_io_deq_bits : _T_3779 ? _Queue10_UInt8_29_io_deq_bits : _T_3778 ? _Queue10_UInt8_28_io_deq_bits : _T_3777 ? _Queue10_UInt8_27_io_deq_bits : _T_3776 ? _Queue10_UInt8_26_io_deq_bits : _T_3775 ? _Queue10_UInt8_25_io_deq_bits : _T_3774 ? _Queue10_UInt8_24_io_deq_bits : _T_3773 ? _Queue10_UInt8_23_io_deq_bits : _T_3772 ? _Queue10_UInt8_22_io_deq_bits : _T_3771 ? _Queue10_UInt8_21_io_deq_bits : _T_3770 ? _Queue10_UInt8_20_io_deq_bits : _T_3769 ? _Queue10_UInt8_19_io_deq_bits : _T_3768 ? _Queue10_UInt8_18_io_deq_bits : _T_3767 ? _Queue10_UInt8_17_io_deq_bits : _T_3766 ? _Queue10_UInt8_16_io_deq_bits : _T_3765 ? _Queue10_UInt8_15_io_deq_bits : _T_3764 ? _Queue10_UInt8_14_io_deq_bits : _T_3763 ? _Queue10_UInt8_13_io_deq_bits : _T_3762 ? _Queue10_UInt8_12_io_deq_bits : _T_3761 ? _Queue10_UInt8_11_io_deq_bits : _T_3760 ? _Queue10_UInt8_10_io_deq_bits : _T_3759 ? _Queue10_UInt8_9_io_deq_bits : _T_3758 ? _Queue10_UInt8_8_io_deq_bits : _T_3757 ? _Queue10_UInt8_7_io_deq_bits : _T_3756 ? _Queue10_UInt8_6_io_deq_bits : _T_3755 ? _Queue10_UInt8_5_io_deq_bits : _T_3754 ? _Queue10_UInt8_4_io_deq_bits : _T_3753 ? _Queue10_UInt8_3_io_deq_bits : _T_3752 ? _Queue10_UInt8_2_io_deq_bits : _T_3751 ? _Queue10_UInt8_1_io_deq_bits : _T_3750 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_15 = _T_3781 ? _Queue10_UInt8_31_io_deq_valid : _T_3780 ? _Queue10_UInt8_30_io_deq_valid : _T_3779 ? _Queue10_UInt8_29_io_deq_valid : _T_3778 ? _Queue10_UInt8_28_io_deq_valid : _T_3777 ? _Queue10_UInt8_27_io_deq_valid : _T_3776 ? _Queue10_UInt8_26_io_deq_valid : _T_3775 ? _Queue10_UInt8_25_io_deq_valid : _T_3774 ? _Queue10_UInt8_24_io_deq_valid : _T_3773 ? _Queue10_UInt8_23_io_deq_valid : _T_3772 ? _Queue10_UInt8_22_io_deq_valid : _T_3771 ? _Queue10_UInt8_21_io_deq_valid : _T_3770 ? _Queue10_UInt8_20_io_deq_valid : _T_3769 ? _Queue10_UInt8_19_io_deq_valid : _T_3768 ? _Queue10_UInt8_18_io_deq_valid : _T_3767 ? _Queue10_UInt8_17_io_deq_valid : _T_3766 ? _Queue10_UInt8_16_io_deq_valid : _T_3765 ? _Queue10_UInt8_15_io_deq_valid : _T_3764 ? _Queue10_UInt8_14_io_deq_valid : _T_3763 ? _Queue10_UInt8_13_io_deq_valid : _T_3762 ? _Queue10_UInt8_12_io_deq_valid : _T_3761 ? _Queue10_UInt8_11_io_deq_valid : _T_3760 ? _Queue10_UInt8_10_io_deq_valid : _T_3759 ? _Queue10_UInt8_9_io_deq_valid : _T_3758 ? _Queue10_UInt8_8_io_deq_valid : _T_3757 ? _Queue10_UInt8_7_io_deq_valid : _T_3756 ? _Queue10_UInt8_6_io_deq_valid : _T_3755 ? _Queue10_UInt8_5_io_deq_valid : _T_3754 ? _Queue10_UInt8_4_io_deq_valid : _T_3753 ? _Queue10_UInt8_3_io_deq_valid : _T_3752 ? _Queue10_UInt8_2_io_deq_valid : _T_3751 ? _Queue10_UInt8_1_io_deq_valid : _T_3750 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_105 = _remapindex_T_16 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_16 = _GEN_105[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3782 = remapindex_16 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3783 = remapindex_16 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3784 = remapindex_16 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3785 = remapindex_16 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3786 = remapindex_16 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3787 = remapindex_16 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3788 = remapindex_16 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3789 = remapindex_16 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3790 = remapindex_16 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3791 = remapindex_16 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3792 = remapindex_16 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3793 = remapindex_16 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3794 = remapindex_16 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3795 = remapindex_16 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3796 = remapindex_16 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3797 = remapindex_16 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3798 = remapindex_16 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3799 = remapindex_16 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3800 = remapindex_16 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3801 = remapindex_16 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3802 = remapindex_16 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3803 = remapindex_16 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3804 = remapindex_16 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3805 = remapindex_16 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3806 = remapindex_16 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3807 = remapindex_16 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3808 = remapindex_16 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3809 = remapindex_16 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3810 = remapindex_16 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3811 = remapindex_16 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3812 = remapindex_16 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3813 = remapindex_16 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_16 = _T_3813 ? _Queue10_UInt8_31_io_deq_bits : _T_3812 ? _Queue10_UInt8_30_io_deq_bits : _T_3811 ? _Queue10_UInt8_29_io_deq_bits : _T_3810 ? _Queue10_UInt8_28_io_deq_bits : _T_3809 ? _Queue10_UInt8_27_io_deq_bits : _T_3808 ? _Queue10_UInt8_26_io_deq_bits : _T_3807 ? _Queue10_UInt8_25_io_deq_bits : _T_3806 ? _Queue10_UInt8_24_io_deq_bits : _T_3805 ? _Queue10_UInt8_23_io_deq_bits : _T_3804 ? _Queue10_UInt8_22_io_deq_bits : _T_3803 ? _Queue10_UInt8_21_io_deq_bits : _T_3802 ? _Queue10_UInt8_20_io_deq_bits : _T_3801 ? _Queue10_UInt8_19_io_deq_bits : _T_3800 ? _Queue10_UInt8_18_io_deq_bits : _T_3799 ? _Queue10_UInt8_17_io_deq_bits : _T_3798 ? _Queue10_UInt8_16_io_deq_bits : _T_3797 ? _Queue10_UInt8_15_io_deq_bits : _T_3796 ? _Queue10_UInt8_14_io_deq_bits : _T_3795 ? _Queue10_UInt8_13_io_deq_bits : _T_3794 ? _Queue10_UInt8_12_io_deq_bits : _T_3793 ? _Queue10_UInt8_11_io_deq_bits : _T_3792 ? _Queue10_UInt8_10_io_deq_bits : _T_3791 ? _Queue10_UInt8_9_io_deq_bits : _T_3790 ? _Queue10_UInt8_8_io_deq_bits : _T_3789 ? _Queue10_UInt8_7_io_deq_bits : _T_3788 ? _Queue10_UInt8_6_io_deq_bits : _T_3787 ? _Queue10_UInt8_5_io_deq_bits : _T_3786 ? _Queue10_UInt8_4_io_deq_bits : _T_3785 ? _Queue10_UInt8_3_io_deq_bits : _T_3784 ? _Queue10_UInt8_2_io_deq_bits : _T_3783 ? _Queue10_UInt8_1_io_deq_bits : _T_3782 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_16 = _T_3813 ? _Queue10_UInt8_31_io_deq_valid : _T_3812 ? _Queue10_UInt8_30_io_deq_valid : _T_3811 ? _Queue10_UInt8_29_io_deq_valid : _T_3810 ? _Queue10_UInt8_28_io_deq_valid : _T_3809 ? _Queue10_UInt8_27_io_deq_valid : _T_3808 ? _Queue10_UInt8_26_io_deq_valid : _T_3807 ? _Queue10_UInt8_25_io_deq_valid : _T_3806 ? _Queue10_UInt8_24_io_deq_valid : _T_3805 ? _Queue10_UInt8_23_io_deq_valid : _T_3804 ? _Queue10_UInt8_22_io_deq_valid : _T_3803 ? _Queue10_UInt8_21_io_deq_valid : _T_3802 ? _Queue10_UInt8_20_io_deq_valid : _T_3801 ? _Queue10_UInt8_19_io_deq_valid : _T_3800 ? _Queue10_UInt8_18_io_deq_valid : _T_3799 ? _Queue10_UInt8_17_io_deq_valid : _T_3798 ? _Queue10_UInt8_16_io_deq_valid : _T_3797 ? _Queue10_UInt8_15_io_deq_valid : _T_3796 ? _Queue10_UInt8_14_io_deq_valid : _T_3795 ? _Queue10_UInt8_13_io_deq_valid : _T_3794 ? _Queue10_UInt8_12_io_deq_valid : _T_3793 ? _Queue10_UInt8_11_io_deq_valid : _T_3792 ? _Queue10_UInt8_10_io_deq_valid : _T_3791 ? _Queue10_UInt8_9_io_deq_valid : _T_3790 ? _Queue10_UInt8_8_io_deq_valid : _T_3789 ? _Queue10_UInt8_7_io_deq_valid : _T_3788 ? _Queue10_UInt8_6_io_deq_valid : _T_3787 ? _Queue10_UInt8_5_io_deq_valid : _T_3786 ? _Queue10_UInt8_4_io_deq_valid : _T_3785 ? _Queue10_UInt8_3_io_deq_valid : _T_3784 ? _Queue10_UInt8_2_io_deq_valid : _T_3783 ? _Queue10_UInt8_1_io_deq_valid : _T_3782 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_106 = _remapindex_T_17 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_17 = _GEN_106[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3814 = remapindex_17 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3815 = remapindex_17 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3816 = remapindex_17 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3817 = remapindex_17 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3818 = remapindex_17 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3819 = remapindex_17 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3820 = remapindex_17 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3821 = remapindex_17 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3822 = remapindex_17 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3823 = remapindex_17 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3824 = remapindex_17 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3825 = remapindex_17 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3826 = remapindex_17 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3827 = remapindex_17 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3828 = remapindex_17 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3829 = remapindex_17 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3830 = remapindex_17 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3831 = remapindex_17 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3832 = remapindex_17 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3833 = remapindex_17 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3834 = remapindex_17 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3835 = remapindex_17 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3836 = remapindex_17 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3837 = remapindex_17 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3838 = remapindex_17 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3839 = remapindex_17 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3840 = remapindex_17 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3841 = remapindex_17 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3842 = remapindex_17 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3843 = remapindex_17 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3844 = remapindex_17 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3845 = remapindex_17 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_17 = _T_3845 ? _Queue10_UInt8_31_io_deq_bits : _T_3844 ? _Queue10_UInt8_30_io_deq_bits : _T_3843 ? _Queue10_UInt8_29_io_deq_bits : _T_3842 ? _Queue10_UInt8_28_io_deq_bits : _T_3841 ? _Queue10_UInt8_27_io_deq_bits : _T_3840 ? _Queue10_UInt8_26_io_deq_bits : _T_3839 ? _Queue10_UInt8_25_io_deq_bits : _T_3838 ? _Queue10_UInt8_24_io_deq_bits : _T_3837 ? _Queue10_UInt8_23_io_deq_bits : _T_3836 ? _Queue10_UInt8_22_io_deq_bits : _T_3835 ? _Queue10_UInt8_21_io_deq_bits : _T_3834 ? _Queue10_UInt8_20_io_deq_bits : _T_3833 ? _Queue10_UInt8_19_io_deq_bits : _T_3832 ? _Queue10_UInt8_18_io_deq_bits : _T_3831 ? _Queue10_UInt8_17_io_deq_bits : _T_3830 ? _Queue10_UInt8_16_io_deq_bits : _T_3829 ? _Queue10_UInt8_15_io_deq_bits : _T_3828 ? _Queue10_UInt8_14_io_deq_bits : _T_3827 ? _Queue10_UInt8_13_io_deq_bits : _T_3826 ? _Queue10_UInt8_12_io_deq_bits : _T_3825 ? _Queue10_UInt8_11_io_deq_bits : _T_3824 ? _Queue10_UInt8_10_io_deq_bits : _T_3823 ? _Queue10_UInt8_9_io_deq_bits : _T_3822 ? _Queue10_UInt8_8_io_deq_bits : _T_3821 ? _Queue10_UInt8_7_io_deq_bits : _T_3820 ? _Queue10_UInt8_6_io_deq_bits : _T_3819 ? _Queue10_UInt8_5_io_deq_bits : _T_3818 ? _Queue10_UInt8_4_io_deq_bits : _T_3817 ? _Queue10_UInt8_3_io_deq_bits : _T_3816 ? _Queue10_UInt8_2_io_deq_bits : _T_3815 ? _Queue10_UInt8_1_io_deq_bits : _T_3814 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_17 = _T_3845 ? _Queue10_UInt8_31_io_deq_valid : _T_3844 ? _Queue10_UInt8_30_io_deq_valid : _T_3843 ? _Queue10_UInt8_29_io_deq_valid : _T_3842 ? _Queue10_UInt8_28_io_deq_valid : _T_3841 ? _Queue10_UInt8_27_io_deq_valid : _T_3840 ? _Queue10_UInt8_26_io_deq_valid : _T_3839 ? _Queue10_UInt8_25_io_deq_valid : _T_3838 ? _Queue10_UInt8_24_io_deq_valid : _T_3837 ? _Queue10_UInt8_23_io_deq_valid : _T_3836 ? _Queue10_UInt8_22_io_deq_valid : _T_3835 ? _Queue10_UInt8_21_io_deq_valid : _T_3834 ? _Queue10_UInt8_20_io_deq_valid : _T_3833 ? _Queue10_UInt8_19_io_deq_valid : _T_3832 ? _Queue10_UInt8_18_io_deq_valid : _T_3831 ? _Queue10_UInt8_17_io_deq_valid : _T_3830 ? _Queue10_UInt8_16_io_deq_valid : _T_3829 ? _Queue10_UInt8_15_io_deq_valid : _T_3828 ? _Queue10_UInt8_14_io_deq_valid : _T_3827 ? _Queue10_UInt8_13_io_deq_valid : _T_3826 ? _Queue10_UInt8_12_io_deq_valid : _T_3825 ? _Queue10_UInt8_11_io_deq_valid : _T_3824 ? _Queue10_UInt8_10_io_deq_valid : _T_3823 ? _Queue10_UInt8_9_io_deq_valid : _T_3822 ? _Queue10_UInt8_8_io_deq_valid : _T_3821 ? _Queue10_UInt8_7_io_deq_valid : _T_3820 ? _Queue10_UInt8_6_io_deq_valid : _T_3819 ? _Queue10_UInt8_5_io_deq_valid : _T_3818 ? _Queue10_UInt8_4_io_deq_valid : _T_3817 ? _Queue10_UInt8_3_io_deq_valid : _T_3816 ? _Queue10_UInt8_2_io_deq_valid : _T_3815 ? _Queue10_UInt8_1_io_deq_valid : _T_3814 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_107 = _remapindex_T_18 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_18 = _GEN_107[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3846 = remapindex_18 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3847 = remapindex_18 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3848 = remapindex_18 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3849 = remapindex_18 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3850 = remapindex_18 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3851 = remapindex_18 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3852 = remapindex_18 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3853 = remapindex_18 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3854 = remapindex_18 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3855 = remapindex_18 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3856 = remapindex_18 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3857 = remapindex_18 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3858 = remapindex_18 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3859 = remapindex_18 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3860 = remapindex_18 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3861 = remapindex_18 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3862 = remapindex_18 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3863 = remapindex_18 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3864 = remapindex_18 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3865 = remapindex_18 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3866 = remapindex_18 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3867 = remapindex_18 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3868 = remapindex_18 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3869 = remapindex_18 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3870 = remapindex_18 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3871 = remapindex_18 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3872 = remapindex_18 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3873 = remapindex_18 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3874 = remapindex_18 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3875 = remapindex_18 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3876 = remapindex_18 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3877 = remapindex_18 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_18 = _T_3877 ? _Queue10_UInt8_31_io_deq_bits : _T_3876 ? _Queue10_UInt8_30_io_deq_bits : _T_3875 ? _Queue10_UInt8_29_io_deq_bits : _T_3874 ? _Queue10_UInt8_28_io_deq_bits : _T_3873 ? _Queue10_UInt8_27_io_deq_bits : _T_3872 ? _Queue10_UInt8_26_io_deq_bits : _T_3871 ? _Queue10_UInt8_25_io_deq_bits : _T_3870 ? _Queue10_UInt8_24_io_deq_bits : _T_3869 ? _Queue10_UInt8_23_io_deq_bits : _T_3868 ? _Queue10_UInt8_22_io_deq_bits : _T_3867 ? _Queue10_UInt8_21_io_deq_bits : _T_3866 ? _Queue10_UInt8_20_io_deq_bits : _T_3865 ? _Queue10_UInt8_19_io_deq_bits : _T_3864 ? _Queue10_UInt8_18_io_deq_bits : _T_3863 ? _Queue10_UInt8_17_io_deq_bits : _T_3862 ? _Queue10_UInt8_16_io_deq_bits : _T_3861 ? _Queue10_UInt8_15_io_deq_bits : _T_3860 ? _Queue10_UInt8_14_io_deq_bits : _T_3859 ? _Queue10_UInt8_13_io_deq_bits : _T_3858 ? _Queue10_UInt8_12_io_deq_bits : _T_3857 ? _Queue10_UInt8_11_io_deq_bits : _T_3856 ? _Queue10_UInt8_10_io_deq_bits : _T_3855 ? _Queue10_UInt8_9_io_deq_bits : _T_3854 ? _Queue10_UInt8_8_io_deq_bits : _T_3853 ? _Queue10_UInt8_7_io_deq_bits : _T_3852 ? _Queue10_UInt8_6_io_deq_bits : _T_3851 ? _Queue10_UInt8_5_io_deq_bits : _T_3850 ? _Queue10_UInt8_4_io_deq_bits : _T_3849 ? _Queue10_UInt8_3_io_deq_bits : _T_3848 ? _Queue10_UInt8_2_io_deq_bits : _T_3847 ? _Queue10_UInt8_1_io_deq_bits : _T_3846 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_18 = _T_3877 ? _Queue10_UInt8_31_io_deq_valid : _T_3876 ? _Queue10_UInt8_30_io_deq_valid : _T_3875 ? _Queue10_UInt8_29_io_deq_valid : _T_3874 ? _Queue10_UInt8_28_io_deq_valid : _T_3873 ? _Queue10_UInt8_27_io_deq_valid : _T_3872 ? _Queue10_UInt8_26_io_deq_valid : _T_3871 ? _Queue10_UInt8_25_io_deq_valid : _T_3870 ? _Queue10_UInt8_24_io_deq_valid : _T_3869 ? _Queue10_UInt8_23_io_deq_valid : _T_3868 ? _Queue10_UInt8_22_io_deq_valid : _T_3867 ? _Queue10_UInt8_21_io_deq_valid : _T_3866 ? _Queue10_UInt8_20_io_deq_valid : _T_3865 ? _Queue10_UInt8_19_io_deq_valid : _T_3864 ? _Queue10_UInt8_18_io_deq_valid : _T_3863 ? _Queue10_UInt8_17_io_deq_valid : _T_3862 ? _Queue10_UInt8_16_io_deq_valid : _T_3861 ? _Queue10_UInt8_15_io_deq_valid : _T_3860 ? _Queue10_UInt8_14_io_deq_valid : _T_3859 ? _Queue10_UInt8_13_io_deq_valid : _T_3858 ? _Queue10_UInt8_12_io_deq_valid : _T_3857 ? _Queue10_UInt8_11_io_deq_valid : _T_3856 ? _Queue10_UInt8_10_io_deq_valid : _T_3855 ? _Queue10_UInt8_9_io_deq_valid : _T_3854 ? _Queue10_UInt8_8_io_deq_valid : _T_3853 ? _Queue10_UInt8_7_io_deq_valid : _T_3852 ? _Queue10_UInt8_6_io_deq_valid : _T_3851 ? _Queue10_UInt8_5_io_deq_valid : _T_3850 ? _Queue10_UInt8_4_io_deq_valid : _T_3849 ? _Queue10_UInt8_3_io_deq_valid : _T_3848 ? _Queue10_UInt8_2_io_deq_valid : _T_3847 ? _Queue10_UInt8_1_io_deq_valid : _T_3846 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_108 = _remapindex_T_19 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_19 = _GEN_108[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3878 = remapindex_19 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3879 = remapindex_19 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3880 = remapindex_19 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3881 = remapindex_19 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3882 = remapindex_19 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3883 = remapindex_19 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3884 = remapindex_19 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3885 = remapindex_19 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3886 = remapindex_19 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3887 = remapindex_19 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3888 = remapindex_19 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3889 = remapindex_19 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3890 = remapindex_19 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3891 = remapindex_19 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3892 = remapindex_19 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3893 = remapindex_19 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3894 = remapindex_19 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3895 = remapindex_19 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3896 = remapindex_19 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3897 = remapindex_19 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3898 = remapindex_19 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3899 = remapindex_19 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3900 = remapindex_19 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3901 = remapindex_19 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3902 = remapindex_19 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3903 = remapindex_19 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3904 = remapindex_19 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3905 = remapindex_19 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3906 = remapindex_19 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3907 = remapindex_19 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3908 = remapindex_19 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3909 = remapindex_19 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_19 = _T_3909 ? _Queue10_UInt8_31_io_deq_bits : _T_3908 ? _Queue10_UInt8_30_io_deq_bits : _T_3907 ? _Queue10_UInt8_29_io_deq_bits : _T_3906 ? _Queue10_UInt8_28_io_deq_bits : _T_3905 ? _Queue10_UInt8_27_io_deq_bits : _T_3904 ? _Queue10_UInt8_26_io_deq_bits : _T_3903 ? _Queue10_UInt8_25_io_deq_bits : _T_3902 ? _Queue10_UInt8_24_io_deq_bits : _T_3901 ? _Queue10_UInt8_23_io_deq_bits : _T_3900 ? _Queue10_UInt8_22_io_deq_bits : _T_3899 ? _Queue10_UInt8_21_io_deq_bits : _T_3898 ? _Queue10_UInt8_20_io_deq_bits : _T_3897 ? _Queue10_UInt8_19_io_deq_bits : _T_3896 ? _Queue10_UInt8_18_io_deq_bits : _T_3895 ? _Queue10_UInt8_17_io_deq_bits : _T_3894 ? _Queue10_UInt8_16_io_deq_bits : _T_3893 ? _Queue10_UInt8_15_io_deq_bits : _T_3892 ? _Queue10_UInt8_14_io_deq_bits : _T_3891 ? _Queue10_UInt8_13_io_deq_bits : _T_3890 ? _Queue10_UInt8_12_io_deq_bits : _T_3889 ? _Queue10_UInt8_11_io_deq_bits : _T_3888 ? _Queue10_UInt8_10_io_deq_bits : _T_3887 ? _Queue10_UInt8_9_io_deq_bits : _T_3886 ? _Queue10_UInt8_8_io_deq_bits : _T_3885 ? _Queue10_UInt8_7_io_deq_bits : _T_3884 ? _Queue10_UInt8_6_io_deq_bits : _T_3883 ? _Queue10_UInt8_5_io_deq_bits : _T_3882 ? _Queue10_UInt8_4_io_deq_bits : _T_3881 ? _Queue10_UInt8_3_io_deq_bits : _T_3880 ? _Queue10_UInt8_2_io_deq_bits : _T_3879 ? _Queue10_UInt8_1_io_deq_bits : _T_3878 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_19 = _T_3909 ? _Queue10_UInt8_31_io_deq_valid : _T_3908 ? _Queue10_UInt8_30_io_deq_valid : _T_3907 ? _Queue10_UInt8_29_io_deq_valid : _T_3906 ? _Queue10_UInt8_28_io_deq_valid : _T_3905 ? _Queue10_UInt8_27_io_deq_valid : _T_3904 ? _Queue10_UInt8_26_io_deq_valid : _T_3903 ? _Queue10_UInt8_25_io_deq_valid : _T_3902 ? _Queue10_UInt8_24_io_deq_valid : _T_3901 ? _Queue10_UInt8_23_io_deq_valid : _T_3900 ? _Queue10_UInt8_22_io_deq_valid : _T_3899 ? _Queue10_UInt8_21_io_deq_valid : _T_3898 ? _Queue10_UInt8_20_io_deq_valid : _T_3897 ? _Queue10_UInt8_19_io_deq_valid : _T_3896 ? _Queue10_UInt8_18_io_deq_valid : _T_3895 ? _Queue10_UInt8_17_io_deq_valid : _T_3894 ? _Queue10_UInt8_16_io_deq_valid : _T_3893 ? _Queue10_UInt8_15_io_deq_valid : _T_3892 ? _Queue10_UInt8_14_io_deq_valid : _T_3891 ? _Queue10_UInt8_13_io_deq_valid : _T_3890 ? _Queue10_UInt8_12_io_deq_valid : _T_3889 ? _Queue10_UInt8_11_io_deq_valid : _T_3888 ? _Queue10_UInt8_10_io_deq_valid : _T_3887 ? _Queue10_UInt8_9_io_deq_valid : _T_3886 ? _Queue10_UInt8_8_io_deq_valid : _T_3885 ? _Queue10_UInt8_7_io_deq_valid : _T_3884 ? _Queue10_UInt8_6_io_deq_valid : _T_3883 ? _Queue10_UInt8_5_io_deq_valid : _T_3882 ? _Queue10_UInt8_4_io_deq_valid : _T_3881 ? _Queue10_UInt8_3_io_deq_valid : _T_3880 ? _Queue10_UInt8_2_io_deq_valid : _T_3879 ? _Queue10_UInt8_1_io_deq_valid : _T_3878 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_109 = _remapindex_T_20 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_20 = _GEN_109[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3910 = remapindex_20 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3911 = remapindex_20 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3912 = remapindex_20 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3913 = remapindex_20 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3914 = remapindex_20 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3915 = remapindex_20 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3916 = remapindex_20 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3917 = remapindex_20 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3918 = remapindex_20 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3919 = remapindex_20 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3920 = remapindex_20 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3921 = remapindex_20 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3922 = remapindex_20 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3923 = remapindex_20 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3924 = remapindex_20 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3925 = remapindex_20 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3926 = remapindex_20 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3927 = remapindex_20 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3928 = remapindex_20 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3929 = remapindex_20 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3930 = remapindex_20 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3931 = remapindex_20 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3932 = remapindex_20 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3933 = remapindex_20 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3934 = remapindex_20 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3935 = remapindex_20 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3936 = remapindex_20 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3937 = remapindex_20 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3938 = remapindex_20 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3939 = remapindex_20 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3940 = remapindex_20 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3941 = remapindex_20 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_20 = _T_3941 ? _Queue10_UInt8_31_io_deq_bits : _T_3940 ? _Queue10_UInt8_30_io_deq_bits : _T_3939 ? _Queue10_UInt8_29_io_deq_bits : _T_3938 ? _Queue10_UInt8_28_io_deq_bits : _T_3937 ? _Queue10_UInt8_27_io_deq_bits : _T_3936 ? _Queue10_UInt8_26_io_deq_bits : _T_3935 ? _Queue10_UInt8_25_io_deq_bits : _T_3934 ? _Queue10_UInt8_24_io_deq_bits : _T_3933 ? _Queue10_UInt8_23_io_deq_bits : _T_3932 ? _Queue10_UInt8_22_io_deq_bits : _T_3931 ? _Queue10_UInt8_21_io_deq_bits : _T_3930 ? _Queue10_UInt8_20_io_deq_bits : _T_3929 ? _Queue10_UInt8_19_io_deq_bits : _T_3928 ? _Queue10_UInt8_18_io_deq_bits : _T_3927 ? _Queue10_UInt8_17_io_deq_bits : _T_3926 ? _Queue10_UInt8_16_io_deq_bits : _T_3925 ? _Queue10_UInt8_15_io_deq_bits : _T_3924 ? _Queue10_UInt8_14_io_deq_bits : _T_3923 ? _Queue10_UInt8_13_io_deq_bits : _T_3922 ? _Queue10_UInt8_12_io_deq_bits : _T_3921 ? _Queue10_UInt8_11_io_deq_bits : _T_3920 ? _Queue10_UInt8_10_io_deq_bits : _T_3919 ? _Queue10_UInt8_9_io_deq_bits : _T_3918 ? _Queue10_UInt8_8_io_deq_bits : _T_3917 ? _Queue10_UInt8_7_io_deq_bits : _T_3916 ? _Queue10_UInt8_6_io_deq_bits : _T_3915 ? _Queue10_UInt8_5_io_deq_bits : _T_3914 ? _Queue10_UInt8_4_io_deq_bits : _T_3913 ? _Queue10_UInt8_3_io_deq_bits : _T_3912 ? _Queue10_UInt8_2_io_deq_bits : _T_3911 ? _Queue10_UInt8_1_io_deq_bits : _T_3910 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_20 = _T_3941 ? _Queue10_UInt8_31_io_deq_valid : _T_3940 ? _Queue10_UInt8_30_io_deq_valid : _T_3939 ? _Queue10_UInt8_29_io_deq_valid : _T_3938 ? _Queue10_UInt8_28_io_deq_valid : _T_3937 ? _Queue10_UInt8_27_io_deq_valid : _T_3936 ? _Queue10_UInt8_26_io_deq_valid : _T_3935 ? _Queue10_UInt8_25_io_deq_valid : _T_3934 ? _Queue10_UInt8_24_io_deq_valid : _T_3933 ? _Queue10_UInt8_23_io_deq_valid : _T_3932 ? _Queue10_UInt8_22_io_deq_valid : _T_3931 ? _Queue10_UInt8_21_io_deq_valid : _T_3930 ? _Queue10_UInt8_20_io_deq_valid : _T_3929 ? _Queue10_UInt8_19_io_deq_valid : _T_3928 ? _Queue10_UInt8_18_io_deq_valid : _T_3927 ? _Queue10_UInt8_17_io_deq_valid : _T_3926 ? _Queue10_UInt8_16_io_deq_valid : _T_3925 ? _Queue10_UInt8_15_io_deq_valid : _T_3924 ? _Queue10_UInt8_14_io_deq_valid : _T_3923 ? _Queue10_UInt8_13_io_deq_valid : _T_3922 ? _Queue10_UInt8_12_io_deq_valid : _T_3921 ? _Queue10_UInt8_11_io_deq_valid : _T_3920 ? _Queue10_UInt8_10_io_deq_valid : _T_3919 ? _Queue10_UInt8_9_io_deq_valid : _T_3918 ? _Queue10_UInt8_8_io_deq_valid : _T_3917 ? _Queue10_UInt8_7_io_deq_valid : _T_3916 ? _Queue10_UInt8_6_io_deq_valid : _T_3915 ? _Queue10_UInt8_5_io_deq_valid : _T_3914 ? _Queue10_UInt8_4_io_deq_valid : _T_3913 ? _Queue10_UInt8_3_io_deq_valid : _T_3912 ? _Queue10_UInt8_2_io_deq_valid : _T_3911 ? _Queue10_UInt8_1_io_deq_valid : _T_3910 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_110 = _remapindex_T_21 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_21 = _GEN_110[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3942 = remapindex_21 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3943 = remapindex_21 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3944 = remapindex_21 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3945 = remapindex_21 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3946 = remapindex_21 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3947 = remapindex_21 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3948 = remapindex_21 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3949 = remapindex_21 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3950 = remapindex_21 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3951 = remapindex_21 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3952 = remapindex_21 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3953 = remapindex_21 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3954 = remapindex_21 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3955 = remapindex_21 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3956 = remapindex_21 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3957 = remapindex_21 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3958 = remapindex_21 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3959 = remapindex_21 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3960 = remapindex_21 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3961 = remapindex_21 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3962 = remapindex_21 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3963 = remapindex_21 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3964 = remapindex_21 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3965 = remapindex_21 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3966 = remapindex_21 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3967 = remapindex_21 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3968 = remapindex_21 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3969 = remapindex_21 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3970 = remapindex_21 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3971 = remapindex_21 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3972 = remapindex_21 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3973 = remapindex_21 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_21 = _T_3973 ? _Queue10_UInt8_31_io_deq_bits : _T_3972 ? _Queue10_UInt8_30_io_deq_bits : _T_3971 ? _Queue10_UInt8_29_io_deq_bits : _T_3970 ? _Queue10_UInt8_28_io_deq_bits : _T_3969 ? _Queue10_UInt8_27_io_deq_bits : _T_3968 ? _Queue10_UInt8_26_io_deq_bits : _T_3967 ? _Queue10_UInt8_25_io_deq_bits : _T_3966 ? _Queue10_UInt8_24_io_deq_bits : _T_3965 ? _Queue10_UInt8_23_io_deq_bits : _T_3964 ? _Queue10_UInt8_22_io_deq_bits : _T_3963 ? _Queue10_UInt8_21_io_deq_bits : _T_3962 ? _Queue10_UInt8_20_io_deq_bits : _T_3961 ? _Queue10_UInt8_19_io_deq_bits : _T_3960 ? _Queue10_UInt8_18_io_deq_bits : _T_3959 ? _Queue10_UInt8_17_io_deq_bits : _T_3958 ? _Queue10_UInt8_16_io_deq_bits : _T_3957 ? _Queue10_UInt8_15_io_deq_bits : _T_3956 ? _Queue10_UInt8_14_io_deq_bits : _T_3955 ? _Queue10_UInt8_13_io_deq_bits : _T_3954 ? _Queue10_UInt8_12_io_deq_bits : _T_3953 ? _Queue10_UInt8_11_io_deq_bits : _T_3952 ? _Queue10_UInt8_10_io_deq_bits : _T_3951 ? _Queue10_UInt8_9_io_deq_bits : _T_3950 ? _Queue10_UInt8_8_io_deq_bits : _T_3949 ? _Queue10_UInt8_7_io_deq_bits : _T_3948 ? _Queue10_UInt8_6_io_deq_bits : _T_3947 ? _Queue10_UInt8_5_io_deq_bits : _T_3946 ? _Queue10_UInt8_4_io_deq_bits : _T_3945 ? _Queue10_UInt8_3_io_deq_bits : _T_3944 ? _Queue10_UInt8_2_io_deq_bits : _T_3943 ? _Queue10_UInt8_1_io_deq_bits : _T_3942 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_21 = _T_3973 ? _Queue10_UInt8_31_io_deq_valid : _T_3972 ? _Queue10_UInt8_30_io_deq_valid : _T_3971 ? _Queue10_UInt8_29_io_deq_valid : _T_3970 ? _Queue10_UInt8_28_io_deq_valid : _T_3969 ? _Queue10_UInt8_27_io_deq_valid : _T_3968 ? _Queue10_UInt8_26_io_deq_valid : _T_3967 ? _Queue10_UInt8_25_io_deq_valid : _T_3966 ? _Queue10_UInt8_24_io_deq_valid : _T_3965 ? _Queue10_UInt8_23_io_deq_valid : _T_3964 ? _Queue10_UInt8_22_io_deq_valid : _T_3963 ? _Queue10_UInt8_21_io_deq_valid : _T_3962 ? _Queue10_UInt8_20_io_deq_valid : _T_3961 ? _Queue10_UInt8_19_io_deq_valid : _T_3960 ? _Queue10_UInt8_18_io_deq_valid : _T_3959 ? _Queue10_UInt8_17_io_deq_valid : _T_3958 ? _Queue10_UInt8_16_io_deq_valid : _T_3957 ? _Queue10_UInt8_15_io_deq_valid : _T_3956 ? _Queue10_UInt8_14_io_deq_valid : _T_3955 ? _Queue10_UInt8_13_io_deq_valid : _T_3954 ? _Queue10_UInt8_12_io_deq_valid : _T_3953 ? _Queue10_UInt8_11_io_deq_valid : _T_3952 ? _Queue10_UInt8_10_io_deq_valid : _T_3951 ? _Queue10_UInt8_9_io_deq_valid : _T_3950 ? _Queue10_UInt8_8_io_deq_valid : _T_3949 ? _Queue10_UInt8_7_io_deq_valid : _T_3948 ? _Queue10_UInt8_6_io_deq_valid : _T_3947 ? _Queue10_UInt8_5_io_deq_valid : _T_3946 ? _Queue10_UInt8_4_io_deq_valid : _T_3945 ? _Queue10_UInt8_3_io_deq_valid : _T_3944 ? _Queue10_UInt8_2_io_deq_valid : _T_3943 ? _Queue10_UInt8_1_io_deq_valid : _T_3942 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_111 = _remapindex_T_22 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_22 = _GEN_111[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3974 = remapindex_22 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3975 = remapindex_22 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3976 = remapindex_22 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3977 = remapindex_22 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3978 = remapindex_22 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3979 = remapindex_22 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3980 = remapindex_22 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3981 = remapindex_22 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3982 = remapindex_22 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3983 = remapindex_22 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3984 = remapindex_22 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3985 = remapindex_22 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3986 = remapindex_22 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3987 = remapindex_22 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3988 = remapindex_22 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3989 = remapindex_22 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3990 = remapindex_22 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3991 = remapindex_22 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3992 = remapindex_22 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3993 = remapindex_22 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3994 = remapindex_22 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3995 = remapindex_22 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3996 = remapindex_22 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3997 = remapindex_22 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3998 = remapindex_22 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3999 = remapindex_22 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4000 = remapindex_22 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4001 = remapindex_22 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4002 = remapindex_22 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4003 = remapindex_22 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4004 = remapindex_22 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4005 = remapindex_22 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_22 = _T_4005 ? _Queue10_UInt8_31_io_deq_bits : _T_4004 ? _Queue10_UInt8_30_io_deq_bits : _T_4003 ? _Queue10_UInt8_29_io_deq_bits : _T_4002 ? _Queue10_UInt8_28_io_deq_bits : _T_4001 ? _Queue10_UInt8_27_io_deq_bits : _T_4000 ? _Queue10_UInt8_26_io_deq_bits : _T_3999 ? _Queue10_UInt8_25_io_deq_bits : _T_3998 ? _Queue10_UInt8_24_io_deq_bits : _T_3997 ? _Queue10_UInt8_23_io_deq_bits : _T_3996 ? _Queue10_UInt8_22_io_deq_bits : _T_3995 ? _Queue10_UInt8_21_io_deq_bits : _T_3994 ? _Queue10_UInt8_20_io_deq_bits : _T_3993 ? _Queue10_UInt8_19_io_deq_bits : _T_3992 ? _Queue10_UInt8_18_io_deq_bits : _T_3991 ? _Queue10_UInt8_17_io_deq_bits : _T_3990 ? _Queue10_UInt8_16_io_deq_bits : _T_3989 ? _Queue10_UInt8_15_io_deq_bits : _T_3988 ? _Queue10_UInt8_14_io_deq_bits : _T_3987 ? _Queue10_UInt8_13_io_deq_bits : _T_3986 ? _Queue10_UInt8_12_io_deq_bits : _T_3985 ? _Queue10_UInt8_11_io_deq_bits : _T_3984 ? _Queue10_UInt8_10_io_deq_bits : _T_3983 ? _Queue10_UInt8_9_io_deq_bits : _T_3982 ? _Queue10_UInt8_8_io_deq_bits : _T_3981 ? _Queue10_UInt8_7_io_deq_bits : _T_3980 ? _Queue10_UInt8_6_io_deq_bits : _T_3979 ? _Queue10_UInt8_5_io_deq_bits : _T_3978 ? _Queue10_UInt8_4_io_deq_bits : _T_3977 ? _Queue10_UInt8_3_io_deq_bits : _T_3976 ? _Queue10_UInt8_2_io_deq_bits : _T_3975 ? _Queue10_UInt8_1_io_deq_bits : _T_3974 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_22 = _T_4005 ? _Queue10_UInt8_31_io_deq_valid : _T_4004 ? _Queue10_UInt8_30_io_deq_valid : _T_4003 ? _Queue10_UInt8_29_io_deq_valid : _T_4002 ? _Queue10_UInt8_28_io_deq_valid : _T_4001 ? _Queue10_UInt8_27_io_deq_valid : _T_4000 ? _Queue10_UInt8_26_io_deq_valid : _T_3999 ? _Queue10_UInt8_25_io_deq_valid : _T_3998 ? _Queue10_UInt8_24_io_deq_valid : _T_3997 ? _Queue10_UInt8_23_io_deq_valid : _T_3996 ? _Queue10_UInt8_22_io_deq_valid : _T_3995 ? _Queue10_UInt8_21_io_deq_valid : _T_3994 ? _Queue10_UInt8_20_io_deq_valid : _T_3993 ? _Queue10_UInt8_19_io_deq_valid : _T_3992 ? _Queue10_UInt8_18_io_deq_valid : _T_3991 ? _Queue10_UInt8_17_io_deq_valid : _T_3990 ? _Queue10_UInt8_16_io_deq_valid : _T_3989 ? _Queue10_UInt8_15_io_deq_valid : _T_3988 ? _Queue10_UInt8_14_io_deq_valid : _T_3987 ? _Queue10_UInt8_13_io_deq_valid : _T_3986 ? _Queue10_UInt8_12_io_deq_valid : _T_3985 ? _Queue10_UInt8_11_io_deq_valid : _T_3984 ? _Queue10_UInt8_10_io_deq_valid : _T_3983 ? _Queue10_UInt8_9_io_deq_valid : _T_3982 ? _Queue10_UInt8_8_io_deq_valid : _T_3981 ? _Queue10_UInt8_7_io_deq_valid : _T_3980 ? _Queue10_UInt8_6_io_deq_valid : _T_3979 ? _Queue10_UInt8_5_io_deq_valid : _T_3978 ? _Queue10_UInt8_4_io_deq_valid : _T_3977 ? _Queue10_UInt8_3_io_deq_valid : _T_3976 ? _Queue10_UInt8_2_io_deq_valid : _T_3975 ? _Queue10_UInt8_1_io_deq_valid : _T_3974 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_112 = _remapindex_T_23 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_23 = _GEN_112[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4006 = remapindex_23 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4007 = remapindex_23 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4008 = remapindex_23 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4009 = remapindex_23 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4010 = remapindex_23 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4011 = remapindex_23 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4012 = remapindex_23 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4013 = remapindex_23 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4014 = remapindex_23 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4015 = remapindex_23 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4016 = remapindex_23 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4017 = remapindex_23 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4018 = remapindex_23 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4019 = remapindex_23 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4020 = remapindex_23 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4021 = remapindex_23 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4022 = remapindex_23 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4023 = remapindex_23 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4024 = remapindex_23 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4025 = remapindex_23 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4026 = remapindex_23 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4027 = remapindex_23 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4028 = remapindex_23 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4029 = remapindex_23 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4030 = remapindex_23 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4031 = remapindex_23 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4032 = remapindex_23 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4033 = remapindex_23 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4034 = remapindex_23 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4035 = remapindex_23 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4036 = remapindex_23 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4037 = remapindex_23 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_23 = _T_4037 ? _Queue10_UInt8_31_io_deq_bits : _T_4036 ? _Queue10_UInt8_30_io_deq_bits : _T_4035 ? _Queue10_UInt8_29_io_deq_bits : _T_4034 ? _Queue10_UInt8_28_io_deq_bits : _T_4033 ? _Queue10_UInt8_27_io_deq_bits : _T_4032 ? _Queue10_UInt8_26_io_deq_bits : _T_4031 ? _Queue10_UInt8_25_io_deq_bits : _T_4030 ? _Queue10_UInt8_24_io_deq_bits : _T_4029 ? _Queue10_UInt8_23_io_deq_bits : _T_4028 ? _Queue10_UInt8_22_io_deq_bits : _T_4027 ? _Queue10_UInt8_21_io_deq_bits : _T_4026 ? _Queue10_UInt8_20_io_deq_bits : _T_4025 ? _Queue10_UInt8_19_io_deq_bits : _T_4024 ? _Queue10_UInt8_18_io_deq_bits : _T_4023 ? _Queue10_UInt8_17_io_deq_bits : _T_4022 ? _Queue10_UInt8_16_io_deq_bits : _T_4021 ? _Queue10_UInt8_15_io_deq_bits : _T_4020 ? _Queue10_UInt8_14_io_deq_bits : _T_4019 ? _Queue10_UInt8_13_io_deq_bits : _T_4018 ? _Queue10_UInt8_12_io_deq_bits : _T_4017 ? _Queue10_UInt8_11_io_deq_bits : _T_4016 ? _Queue10_UInt8_10_io_deq_bits : _T_4015 ? _Queue10_UInt8_9_io_deq_bits : _T_4014 ? _Queue10_UInt8_8_io_deq_bits : _T_4013 ? _Queue10_UInt8_7_io_deq_bits : _T_4012 ? _Queue10_UInt8_6_io_deq_bits : _T_4011 ? _Queue10_UInt8_5_io_deq_bits : _T_4010 ? _Queue10_UInt8_4_io_deq_bits : _T_4009 ? _Queue10_UInt8_3_io_deq_bits : _T_4008 ? _Queue10_UInt8_2_io_deq_bits : _T_4007 ? _Queue10_UInt8_1_io_deq_bits : _T_4006 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_23 = _T_4037 ? _Queue10_UInt8_31_io_deq_valid : _T_4036 ? _Queue10_UInt8_30_io_deq_valid : _T_4035 ? _Queue10_UInt8_29_io_deq_valid : _T_4034 ? _Queue10_UInt8_28_io_deq_valid : _T_4033 ? _Queue10_UInt8_27_io_deq_valid : _T_4032 ? _Queue10_UInt8_26_io_deq_valid : _T_4031 ? _Queue10_UInt8_25_io_deq_valid : _T_4030 ? _Queue10_UInt8_24_io_deq_valid : _T_4029 ? _Queue10_UInt8_23_io_deq_valid : _T_4028 ? _Queue10_UInt8_22_io_deq_valid : _T_4027 ? _Queue10_UInt8_21_io_deq_valid : _T_4026 ? _Queue10_UInt8_20_io_deq_valid : _T_4025 ? _Queue10_UInt8_19_io_deq_valid : _T_4024 ? _Queue10_UInt8_18_io_deq_valid : _T_4023 ? _Queue10_UInt8_17_io_deq_valid : _T_4022 ? _Queue10_UInt8_16_io_deq_valid : _T_4021 ? _Queue10_UInt8_15_io_deq_valid : _T_4020 ? _Queue10_UInt8_14_io_deq_valid : _T_4019 ? _Queue10_UInt8_13_io_deq_valid : _T_4018 ? _Queue10_UInt8_12_io_deq_valid : _T_4017 ? _Queue10_UInt8_11_io_deq_valid : _T_4016 ? _Queue10_UInt8_10_io_deq_valid : _T_4015 ? _Queue10_UInt8_9_io_deq_valid : _T_4014 ? _Queue10_UInt8_8_io_deq_valid : _T_4013 ? _Queue10_UInt8_7_io_deq_valid : _T_4012 ? _Queue10_UInt8_6_io_deq_valid : _T_4011 ? _Queue10_UInt8_5_io_deq_valid : _T_4010 ? _Queue10_UInt8_4_io_deq_valid : _T_4009 ? _Queue10_UInt8_3_io_deq_valid : _T_4008 ? _Queue10_UInt8_2_io_deq_valid : _T_4007 ? _Queue10_UInt8_1_io_deq_valid : _T_4006 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_113 = _remapindex_T_24 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_24 = _GEN_113[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4038 = remapindex_24 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4039 = remapindex_24 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4040 = remapindex_24 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4041 = remapindex_24 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4042 = remapindex_24 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4043 = remapindex_24 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4044 = remapindex_24 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4045 = remapindex_24 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4046 = remapindex_24 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4047 = remapindex_24 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4048 = remapindex_24 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4049 = remapindex_24 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4050 = remapindex_24 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4051 = remapindex_24 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4052 = remapindex_24 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4053 = remapindex_24 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4054 = remapindex_24 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4055 = remapindex_24 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4056 = remapindex_24 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4057 = remapindex_24 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4058 = remapindex_24 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4059 = remapindex_24 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4060 = remapindex_24 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4061 = remapindex_24 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4062 = remapindex_24 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4063 = remapindex_24 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4064 = remapindex_24 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4065 = remapindex_24 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4066 = remapindex_24 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4067 = remapindex_24 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4068 = remapindex_24 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4069 = remapindex_24 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_24 = _T_4069 ? _Queue10_UInt8_31_io_deq_bits : _T_4068 ? _Queue10_UInt8_30_io_deq_bits : _T_4067 ? _Queue10_UInt8_29_io_deq_bits : _T_4066 ? _Queue10_UInt8_28_io_deq_bits : _T_4065 ? _Queue10_UInt8_27_io_deq_bits : _T_4064 ? _Queue10_UInt8_26_io_deq_bits : _T_4063 ? _Queue10_UInt8_25_io_deq_bits : _T_4062 ? _Queue10_UInt8_24_io_deq_bits : _T_4061 ? _Queue10_UInt8_23_io_deq_bits : _T_4060 ? _Queue10_UInt8_22_io_deq_bits : _T_4059 ? _Queue10_UInt8_21_io_deq_bits : _T_4058 ? _Queue10_UInt8_20_io_deq_bits : _T_4057 ? _Queue10_UInt8_19_io_deq_bits : _T_4056 ? _Queue10_UInt8_18_io_deq_bits : _T_4055 ? _Queue10_UInt8_17_io_deq_bits : _T_4054 ? _Queue10_UInt8_16_io_deq_bits : _T_4053 ? _Queue10_UInt8_15_io_deq_bits : _T_4052 ? _Queue10_UInt8_14_io_deq_bits : _T_4051 ? _Queue10_UInt8_13_io_deq_bits : _T_4050 ? _Queue10_UInt8_12_io_deq_bits : _T_4049 ? _Queue10_UInt8_11_io_deq_bits : _T_4048 ? _Queue10_UInt8_10_io_deq_bits : _T_4047 ? _Queue10_UInt8_9_io_deq_bits : _T_4046 ? _Queue10_UInt8_8_io_deq_bits : _T_4045 ? _Queue10_UInt8_7_io_deq_bits : _T_4044 ? _Queue10_UInt8_6_io_deq_bits : _T_4043 ? _Queue10_UInt8_5_io_deq_bits : _T_4042 ? _Queue10_UInt8_4_io_deq_bits : _T_4041 ? _Queue10_UInt8_3_io_deq_bits : _T_4040 ? _Queue10_UInt8_2_io_deq_bits : _T_4039 ? _Queue10_UInt8_1_io_deq_bits : _T_4038 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_24 = _T_4069 ? _Queue10_UInt8_31_io_deq_valid : _T_4068 ? _Queue10_UInt8_30_io_deq_valid : _T_4067 ? _Queue10_UInt8_29_io_deq_valid : _T_4066 ? _Queue10_UInt8_28_io_deq_valid : _T_4065 ? _Queue10_UInt8_27_io_deq_valid : _T_4064 ? _Queue10_UInt8_26_io_deq_valid : _T_4063 ? _Queue10_UInt8_25_io_deq_valid : _T_4062 ? _Queue10_UInt8_24_io_deq_valid : _T_4061 ? _Queue10_UInt8_23_io_deq_valid : _T_4060 ? _Queue10_UInt8_22_io_deq_valid : _T_4059 ? _Queue10_UInt8_21_io_deq_valid : _T_4058 ? _Queue10_UInt8_20_io_deq_valid : _T_4057 ? _Queue10_UInt8_19_io_deq_valid : _T_4056 ? _Queue10_UInt8_18_io_deq_valid : _T_4055 ? _Queue10_UInt8_17_io_deq_valid : _T_4054 ? _Queue10_UInt8_16_io_deq_valid : _T_4053 ? _Queue10_UInt8_15_io_deq_valid : _T_4052 ? _Queue10_UInt8_14_io_deq_valid : _T_4051 ? _Queue10_UInt8_13_io_deq_valid : _T_4050 ? _Queue10_UInt8_12_io_deq_valid : _T_4049 ? _Queue10_UInt8_11_io_deq_valid : _T_4048 ? _Queue10_UInt8_10_io_deq_valid : _T_4047 ? _Queue10_UInt8_9_io_deq_valid : _T_4046 ? _Queue10_UInt8_8_io_deq_valid : _T_4045 ? _Queue10_UInt8_7_io_deq_valid : _T_4044 ? _Queue10_UInt8_6_io_deq_valid : _T_4043 ? _Queue10_UInt8_5_io_deq_valid : _T_4042 ? _Queue10_UInt8_4_io_deq_valid : _T_4041 ? _Queue10_UInt8_3_io_deq_valid : _T_4040 ? _Queue10_UInt8_2_io_deq_valid : _T_4039 ? _Queue10_UInt8_1_io_deq_valid : _T_4038 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_114 = _remapindex_T_25 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_25 = _GEN_114[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4070 = remapindex_25 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4071 = remapindex_25 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4072 = remapindex_25 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4073 = remapindex_25 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4074 = remapindex_25 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4075 = remapindex_25 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4076 = remapindex_25 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4077 = remapindex_25 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4078 = remapindex_25 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4079 = remapindex_25 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4080 = remapindex_25 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4081 = remapindex_25 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4082 = remapindex_25 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4083 = remapindex_25 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4084 = remapindex_25 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4085 = remapindex_25 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4086 = remapindex_25 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4087 = remapindex_25 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4088 = remapindex_25 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4089 = remapindex_25 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4090 = remapindex_25 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4091 = remapindex_25 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4092 = remapindex_25 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4093 = remapindex_25 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4094 = remapindex_25 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4095 = remapindex_25 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4096 = remapindex_25 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4097 = remapindex_25 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4098 = remapindex_25 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4099 = remapindex_25 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4100 = remapindex_25 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4101 = remapindex_25 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_25 = _T_4101 ? _Queue10_UInt8_31_io_deq_bits : _T_4100 ? _Queue10_UInt8_30_io_deq_bits : _T_4099 ? _Queue10_UInt8_29_io_deq_bits : _T_4098 ? _Queue10_UInt8_28_io_deq_bits : _T_4097 ? _Queue10_UInt8_27_io_deq_bits : _T_4096 ? _Queue10_UInt8_26_io_deq_bits : _T_4095 ? _Queue10_UInt8_25_io_deq_bits : _T_4094 ? _Queue10_UInt8_24_io_deq_bits : _T_4093 ? _Queue10_UInt8_23_io_deq_bits : _T_4092 ? _Queue10_UInt8_22_io_deq_bits : _T_4091 ? _Queue10_UInt8_21_io_deq_bits : _T_4090 ? _Queue10_UInt8_20_io_deq_bits : _T_4089 ? _Queue10_UInt8_19_io_deq_bits : _T_4088 ? _Queue10_UInt8_18_io_deq_bits : _T_4087 ? _Queue10_UInt8_17_io_deq_bits : _T_4086 ? _Queue10_UInt8_16_io_deq_bits : _T_4085 ? _Queue10_UInt8_15_io_deq_bits : _T_4084 ? _Queue10_UInt8_14_io_deq_bits : _T_4083 ? _Queue10_UInt8_13_io_deq_bits : _T_4082 ? _Queue10_UInt8_12_io_deq_bits : _T_4081 ? _Queue10_UInt8_11_io_deq_bits : _T_4080 ? _Queue10_UInt8_10_io_deq_bits : _T_4079 ? _Queue10_UInt8_9_io_deq_bits : _T_4078 ? _Queue10_UInt8_8_io_deq_bits : _T_4077 ? _Queue10_UInt8_7_io_deq_bits : _T_4076 ? _Queue10_UInt8_6_io_deq_bits : _T_4075 ? _Queue10_UInt8_5_io_deq_bits : _T_4074 ? _Queue10_UInt8_4_io_deq_bits : _T_4073 ? _Queue10_UInt8_3_io_deq_bits : _T_4072 ? _Queue10_UInt8_2_io_deq_bits : _T_4071 ? _Queue10_UInt8_1_io_deq_bits : _T_4070 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_25 = _T_4101 ? _Queue10_UInt8_31_io_deq_valid : _T_4100 ? _Queue10_UInt8_30_io_deq_valid : _T_4099 ? _Queue10_UInt8_29_io_deq_valid : _T_4098 ? _Queue10_UInt8_28_io_deq_valid : _T_4097 ? _Queue10_UInt8_27_io_deq_valid : _T_4096 ? _Queue10_UInt8_26_io_deq_valid : _T_4095 ? _Queue10_UInt8_25_io_deq_valid : _T_4094 ? _Queue10_UInt8_24_io_deq_valid : _T_4093 ? _Queue10_UInt8_23_io_deq_valid : _T_4092 ? _Queue10_UInt8_22_io_deq_valid : _T_4091 ? _Queue10_UInt8_21_io_deq_valid : _T_4090 ? _Queue10_UInt8_20_io_deq_valid : _T_4089 ? _Queue10_UInt8_19_io_deq_valid : _T_4088 ? _Queue10_UInt8_18_io_deq_valid : _T_4087 ? _Queue10_UInt8_17_io_deq_valid : _T_4086 ? _Queue10_UInt8_16_io_deq_valid : _T_4085 ? _Queue10_UInt8_15_io_deq_valid : _T_4084 ? _Queue10_UInt8_14_io_deq_valid : _T_4083 ? _Queue10_UInt8_13_io_deq_valid : _T_4082 ? _Queue10_UInt8_12_io_deq_valid : _T_4081 ? _Queue10_UInt8_11_io_deq_valid : _T_4080 ? _Queue10_UInt8_10_io_deq_valid : _T_4079 ? _Queue10_UInt8_9_io_deq_valid : _T_4078 ? _Queue10_UInt8_8_io_deq_valid : _T_4077 ? _Queue10_UInt8_7_io_deq_valid : _T_4076 ? _Queue10_UInt8_6_io_deq_valid : _T_4075 ? _Queue10_UInt8_5_io_deq_valid : _T_4074 ? _Queue10_UInt8_4_io_deq_valid : _T_4073 ? _Queue10_UInt8_3_io_deq_valid : _T_4072 ? _Queue10_UInt8_2_io_deq_valid : _T_4071 ? _Queue10_UInt8_1_io_deq_valid : _T_4070 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_115 = _remapindex_T_26 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_26 = _GEN_115[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4102 = remapindex_26 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4103 = remapindex_26 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4104 = remapindex_26 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4105 = remapindex_26 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4106 = remapindex_26 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4107 = remapindex_26 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4108 = remapindex_26 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4109 = remapindex_26 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4110 = remapindex_26 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4111 = remapindex_26 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4112 = remapindex_26 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4113 = remapindex_26 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4114 = remapindex_26 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4115 = remapindex_26 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4116 = remapindex_26 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4117 = remapindex_26 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4118 = remapindex_26 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4119 = remapindex_26 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4120 = remapindex_26 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4121 = remapindex_26 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4122 = remapindex_26 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4123 = remapindex_26 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4124 = remapindex_26 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4125 = remapindex_26 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4126 = remapindex_26 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4127 = remapindex_26 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4128 = remapindex_26 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4129 = remapindex_26 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4130 = remapindex_26 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4131 = remapindex_26 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4132 = remapindex_26 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4133 = remapindex_26 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_26 = _T_4133 ? _Queue10_UInt8_31_io_deq_bits : _T_4132 ? _Queue10_UInt8_30_io_deq_bits : _T_4131 ? _Queue10_UInt8_29_io_deq_bits : _T_4130 ? _Queue10_UInt8_28_io_deq_bits : _T_4129 ? _Queue10_UInt8_27_io_deq_bits : _T_4128 ? _Queue10_UInt8_26_io_deq_bits : _T_4127 ? _Queue10_UInt8_25_io_deq_bits : _T_4126 ? _Queue10_UInt8_24_io_deq_bits : _T_4125 ? _Queue10_UInt8_23_io_deq_bits : _T_4124 ? _Queue10_UInt8_22_io_deq_bits : _T_4123 ? _Queue10_UInt8_21_io_deq_bits : _T_4122 ? _Queue10_UInt8_20_io_deq_bits : _T_4121 ? _Queue10_UInt8_19_io_deq_bits : _T_4120 ? _Queue10_UInt8_18_io_deq_bits : _T_4119 ? _Queue10_UInt8_17_io_deq_bits : _T_4118 ? _Queue10_UInt8_16_io_deq_bits : _T_4117 ? _Queue10_UInt8_15_io_deq_bits : _T_4116 ? _Queue10_UInt8_14_io_deq_bits : _T_4115 ? _Queue10_UInt8_13_io_deq_bits : _T_4114 ? _Queue10_UInt8_12_io_deq_bits : _T_4113 ? _Queue10_UInt8_11_io_deq_bits : _T_4112 ? _Queue10_UInt8_10_io_deq_bits : _T_4111 ? _Queue10_UInt8_9_io_deq_bits : _T_4110 ? _Queue10_UInt8_8_io_deq_bits : _T_4109 ? _Queue10_UInt8_7_io_deq_bits : _T_4108 ? _Queue10_UInt8_6_io_deq_bits : _T_4107 ? _Queue10_UInt8_5_io_deq_bits : _T_4106 ? _Queue10_UInt8_4_io_deq_bits : _T_4105 ? _Queue10_UInt8_3_io_deq_bits : _T_4104 ? _Queue10_UInt8_2_io_deq_bits : _T_4103 ? _Queue10_UInt8_1_io_deq_bits : _T_4102 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_26 = _T_4133 ? _Queue10_UInt8_31_io_deq_valid : _T_4132 ? _Queue10_UInt8_30_io_deq_valid : _T_4131 ? _Queue10_UInt8_29_io_deq_valid : _T_4130 ? _Queue10_UInt8_28_io_deq_valid : _T_4129 ? _Queue10_UInt8_27_io_deq_valid : _T_4128 ? _Queue10_UInt8_26_io_deq_valid : _T_4127 ? _Queue10_UInt8_25_io_deq_valid : _T_4126 ? _Queue10_UInt8_24_io_deq_valid : _T_4125 ? _Queue10_UInt8_23_io_deq_valid : _T_4124 ? _Queue10_UInt8_22_io_deq_valid : _T_4123 ? _Queue10_UInt8_21_io_deq_valid : _T_4122 ? _Queue10_UInt8_20_io_deq_valid : _T_4121 ? _Queue10_UInt8_19_io_deq_valid : _T_4120 ? _Queue10_UInt8_18_io_deq_valid : _T_4119 ? _Queue10_UInt8_17_io_deq_valid : _T_4118 ? _Queue10_UInt8_16_io_deq_valid : _T_4117 ? _Queue10_UInt8_15_io_deq_valid : _T_4116 ? _Queue10_UInt8_14_io_deq_valid : _T_4115 ? _Queue10_UInt8_13_io_deq_valid : _T_4114 ? _Queue10_UInt8_12_io_deq_valid : _T_4113 ? _Queue10_UInt8_11_io_deq_valid : _T_4112 ? _Queue10_UInt8_10_io_deq_valid : _T_4111 ? _Queue10_UInt8_9_io_deq_valid : _T_4110 ? _Queue10_UInt8_8_io_deq_valid : _T_4109 ? _Queue10_UInt8_7_io_deq_valid : _T_4108 ? _Queue10_UInt8_6_io_deq_valid : _T_4107 ? _Queue10_UInt8_5_io_deq_valid : _T_4106 ? _Queue10_UInt8_4_io_deq_valid : _T_4105 ? _Queue10_UInt8_3_io_deq_valid : _T_4104 ? _Queue10_UInt8_2_io_deq_valid : _T_4103 ? _Queue10_UInt8_1_io_deq_valid : _T_4102 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_116 = _remapindex_T_27 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_27 = _GEN_116[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4134 = remapindex_27 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4135 = remapindex_27 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4136 = remapindex_27 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4137 = remapindex_27 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4138 = remapindex_27 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4139 = remapindex_27 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4140 = remapindex_27 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4141 = remapindex_27 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4142 = remapindex_27 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4143 = remapindex_27 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4144 = remapindex_27 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4145 = remapindex_27 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4146 = remapindex_27 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4147 = remapindex_27 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4148 = remapindex_27 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4149 = remapindex_27 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4150 = remapindex_27 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4151 = remapindex_27 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4152 = remapindex_27 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4153 = remapindex_27 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4154 = remapindex_27 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4155 = remapindex_27 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4156 = remapindex_27 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4157 = remapindex_27 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4158 = remapindex_27 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4159 = remapindex_27 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4160 = remapindex_27 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4161 = remapindex_27 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4162 = remapindex_27 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4163 = remapindex_27 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4164 = remapindex_27 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4165 = remapindex_27 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_27 = _T_4165 ? _Queue10_UInt8_31_io_deq_bits : _T_4164 ? _Queue10_UInt8_30_io_deq_bits : _T_4163 ? _Queue10_UInt8_29_io_deq_bits : _T_4162 ? _Queue10_UInt8_28_io_deq_bits : _T_4161 ? _Queue10_UInt8_27_io_deq_bits : _T_4160 ? _Queue10_UInt8_26_io_deq_bits : _T_4159 ? _Queue10_UInt8_25_io_deq_bits : _T_4158 ? _Queue10_UInt8_24_io_deq_bits : _T_4157 ? _Queue10_UInt8_23_io_deq_bits : _T_4156 ? _Queue10_UInt8_22_io_deq_bits : _T_4155 ? _Queue10_UInt8_21_io_deq_bits : _T_4154 ? _Queue10_UInt8_20_io_deq_bits : _T_4153 ? _Queue10_UInt8_19_io_deq_bits : _T_4152 ? _Queue10_UInt8_18_io_deq_bits : _T_4151 ? _Queue10_UInt8_17_io_deq_bits : _T_4150 ? _Queue10_UInt8_16_io_deq_bits : _T_4149 ? _Queue10_UInt8_15_io_deq_bits : _T_4148 ? _Queue10_UInt8_14_io_deq_bits : _T_4147 ? _Queue10_UInt8_13_io_deq_bits : _T_4146 ? _Queue10_UInt8_12_io_deq_bits : _T_4145 ? _Queue10_UInt8_11_io_deq_bits : _T_4144 ? _Queue10_UInt8_10_io_deq_bits : _T_4143 ? _Queue10_UInt8_9_io_deq_bits : _T_4142 ? _Queue10_UInt8_8_io_deq_bits : _T_4141 ? _Queue10_UInt8_7_io_deq_bits : _T_4140 ? _Queue10_UInt8_6_io_deq_bits : _T_4139 ? _Queue10_UInt8_5_io_deq_bits : _T_4138 ? _Queue10_UInt8_4_io_deq_bits : _T_4137 ? _Queue10_UInt8_3_io_deq_bits : _T_4136 ? _Queue10_UInt8_2_io_deq_bits : _T_4135 ? _Queue10_UInt8_1_io_deq_bits : _T_4134 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_27 = _T_4165 ? _Queue10_UInt8_31_io_deq_valid : _T_4164 ? _Queue10_UInt8_30_io_deq_valid : _T_4163 ? _Queue10_UInt8_29_io_deq_valid : _T_4162 ? _Queue10_UInt8_28_io_deq_valid : _T_4161 ? _Queue10_UInt8_27_io_deq_valid : _T_4160 ? _Queue10_UInt8_26_io_deq_valid : _T_4159 ? _Queue10_UInt8_25_io_deq_valid : _T_4158 ? _Queue10_UInt8_24_io_deq_valid : _T_4157 ? _Queue10_UInt8_23_io_deq_valid : _T_4156 ? _Queue10_UInt8_22_io_deq_valid : _T_4155 ? _Queue10_UInt8_21_io_deq_valid : _T_4154 ? _Queue10_UInt8_20_io_deq_valid : _T_4153 ? _Queue10_UInt8_19_io_deq_valid : _T_4152 ? _Queue10_UInt8_18_io_deq_valid : _T_4151 ? _Queue10_UInt8_17_io_deq_valid : _T_4150 ? _Queue10_UInt8_16_io_deq_valid : _T_4149 ? _Queue10_UInt8_15_io_deq_valid : _T_4148 ? _Queue10_UInt8_14_io_deq_valid : _T_4147 ? _Queue10_UInt8_13_io_deq_valid : _T_4146 ? _Queue10_UInt8_12_io_deq_valid : _T_4145 ? _Queue10_UInt8_11_io_deq_valid : _T_4144 ? _Queue10_UInt8_10_io_deq_valid : _T_4143 ? _Queue10_UInt8_9_io_deq_valid : _T_4142 ? _Queue10_UInt8_8_io_deq_valid : _T_4141 ? _Queue10_UInt8_7_io_deq_valid : _T_4140 ? _Queue10_UInt8_6_io_deq_valid : _T_4139 ? _Queue10_UInt8_5_io_deq_valid : _T_4138 ? _Queue10_UInt8_4_io_deq_valid : _T_4137 ? _Queue10_UInt8_3_io_deq_valid : _T_4136 ? _Queue10_UInt8_2_io_deq_valid : _T_4135 ? _Queue10_UInt8_1_io_deq_valid : _T_4134 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_117 = _remapindex_T_28 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_28 = _GEN_117[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4166 = remapindex_28 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4167 = remapindex_28 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4168 = remapindex_28 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4169 = remapindex_28 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4170 = remapindex_28 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4171 = remapindex_28 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4172 = remapindex_28 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4173 = remapindex_28 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4174 = remapindex_28 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4175 = remapindex_28 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4176 = remapindex_28 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4177 = remapindex_28 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4178 = remapindex_28 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4179 = remapindex_28 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4180 = remapindex_28 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4181 = remapindex_28 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4182 = remapindex_28 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4183 = remapindex_28 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4184 = remapindex_28 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4185 = remapindex_28 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4186 = remapindex_28 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4187 = remapindex_28 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4188 = remapindex_28 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4189 = remapindex_28 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4190 = remapindex_28 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4191 = remapindex_28 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4192 = remapindex_28 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4193 = remapindex_28 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4194 = remapindex_28 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4195 = remapindex_28 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4196 = remapindex_28 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4197 = remapindex_28 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_28 = _T_4197 ? _Queue10_UInt8_31_io_deq_bits : _T_4196 ? _Queue10_UInt8_30_io_deq_bits : _T_4195 ? _Queue10_UInt8_29_io_deq_bits : _T_4194 ? _Queue10_UInt8_28_io_deq_bits : _T_4193 ? _Queue10_UInt8_27_io_deq_bits : _T_4192 ? _Queue10_UInt8_26_io_deq_bits : _T_4191 ? _Queue10_UInt8_25_io_deq_bits : _T_4190 ? _Queue10_UInt8_24_io_deq_bits : _T_4189 ? _Queue10_UInt8_23_io_deq_bits : _T_4188 ? _Queue10_UInt8_22_io_deq_bits : _T_4187 ? _Queue10_UInt8_21_io_deq_bits : _T_4186 ? _Queue10_UInt8_20_io_deq_bits : _T_4185 ? _Queue10_UInt8_19_io_deq_bits : _T_4184 ? _Queue10_UInt8_18_io_deq_bits : _T_4183 ? _Queue10_UInt8_17_io_deq_bits : _T_4182 ? _Queue10_UInt8_16_io_deq_bits : _T_4181 ? _Queue10_UInt8_15_io_deq_bits : _T_4180 ? _Queue10_UInt8_14_io_deq_bits : _T_4179 ? _Queue10_UInt8_13_io_deq_bits : _T_4178 ? _Queue10_UInt8_12_io_deq_bits : _T_4177 ? _Queue10_UInt8_11_io_deq_bits : _T_4176 ? _Queue10_UInt8_10_io_deq_bits : _T_4175 ? _Queue10_UInt8_9_io_deq_bits : _T_4174 ? _Queue10_UInt8_8_io_deq_bits : _T_4173 ? _Queue10_UInt8_7_io_deq_bits : _T_4172 ? _Queue10_UInt8_6_io_deq_bits : _T_4171 ? _Queue10_UInt8_5_io_deq_bits : _T_4170 ? _Queue10_UInt8_4_io_deq_bits : _T_4169 ? _Queue10_UInt8_3_io_deq_bits : _T_4168 ? _Queue10_UInt8_2_io_deq_bits : _T_4167 ? _Queue10_UInt8_1_io_deq_bits : _T_4166 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_28 = _T_4197 ? _Queue10_UInt8_31_io_deq_valid : _T_4196 ? _Queue10_UInt8_30_io_deq_valid : _T_4195 ? _Queue10_UInt8_29_io_deq_valid : _T_4194 ? _Queue10_UInt8_28_io_deq_valid : _T_4193 ? _Queue10_UInt8_27_io_deq_valid : _T_4192 ? _Queue10_UInt8_26_io_deq_valid : _T_4191 ? _Queue10_UInt8_25_io_deq_valid : _T_4190 ? _Queue10_UInt8_24_io_deq_valid : _T_4189 ? _Queue10_UInt8_23_io_deq_valid : _T_4188 ? _Queue10_UInt8_22_io_deq_valid : _T_4187 ? _Queue10_UInt8_21_io_deq_valid : _T_4186 ? _Queue10_UInt8_20_io_deq_valid : _T_4185 ? _Queue10_UInt8_19_io_deq_valid : _T_4184 ? _Queue10_UInt8_18_io_deq_valid : _T_4183 ? _Queue10_UInt8_17_io_deq_valid : _T_4182 ? _Queue10_UInt8_16_io_deq_valid : _T_4181 ? _Queue10_UInt8_15_io_deq_valid : _T_4180 ? _Queue10_UInt8_14_io_deq_valid : _T_4179 ? _Queue10_UInt8_13_io_deq_valid : _T_4178 ? _Queue10_UInt8_12_io_deq_valid : _T_4177 ? _Queue10_UInt8_11_io_deq_valid : _T_4176 ? _Queue10_UInt8_10_io_deq_valid : _T_4175 ? _Queue10_UInt8_9_io_deq_valid : _T_4174 ? _Queue10_UInt8_8_io_deq_valid : _T_4173 ? _Queue10_UInt8_7_io_deq_valid : _T_4172 ? _Queue10_UInt8_6_io_deq_valid : _T_4171 ? _Queue10_UInt8_5_io_deq_valid : _T_4170 ? _Queue10_UInt8_4_io_deq_valid : _T_4169 ? _Queue10_UInt8_3_io_deq_valid : _T_4168 ? _Queue10_UInt8_2_io_deq_valid : _T_4167 ? _Queue10_UInt8_1_io_deq_valid : _T_4166 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_118 = _remapindex_T_29 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_29 = _GEN_118[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4198 = remapindex_29 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4199 = remapindex_29 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4200 = remapindex_29 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4201 = remapindex_29 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4202 = remapindex_29 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4203 = remapindex_29 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4204 = remapindex_29 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4205 = remapindex_29 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4206 = remapindex_29 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4207 = remapindex_29 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4208 = remapindex_29 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4209 = remapindex_29 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4210 = remapindex_29 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4211 = remapindex_29 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4212 = remapindex_29 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4213 = remapindex_29 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4214 = remapindex_29 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4215 = remapindex_29 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4216 = remapindex_29 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4217 = remapindex_29 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4218 = remapindex_29 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4219 = remapindex_29 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4220 = remapindex_29 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4221 = remapindex_29 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4222 = remapindex_29 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4223 = remapindex_29 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4224 = remapindex_29 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4225 = remapindex_29 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4226 = remapindex_29 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4227 = remapindex_29 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4228 = remapindex_29 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4229 = remapindex_29 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_29 = _T_4229 ? _Queue10_UInt8_31_io_deq_bits : _T_4228 ? _Queue10_UInt8_30_io_deq_bits : _T_4227 ? _Queue10_UInt8_29_io_deq_bits : _T_4226 ? _Queue10_UInt8_28_io_deq_bits : _T_4225 ? _Queue10_UInt8_27_io_deq_bits : _T_4224 ? _Queue10_UInt8_26_io_deq_bits : _T_4223 ? _Queue10_UInt8_25_io_deq_bits : _T_4222 ? _Queue10_UInt8_24_io_deq_bits : _T_4221 ? _Queue10_UInt8_23_io_deq_bits : _T_4220 ? _Queue10_UInt8_22_io_deq_bits : _T_4219 ? _Queue10_UInt8_21_io_deq_bits : _T_4218 ? _Queue10_UInt8_20_io_deq_bits : _T_4217 ? _Queue10_UInt8_19_io_deq_bits : _T_4216 ? _Queue10_UInt8_18_io_deq_bits : _T_4215 ? _Queue10_UInt8_17_io_deq_bits : _T_4214 ? _Queue10_UInt8_16_io_deq_bits : _T_4213 ? _Queue10_UInt8_15_io_deq_bits : _T_4212 ? _Queue10_UInt8_14_io_deq_bits : _T_4211 ? _Queue10_UInt8_13_io_deq_bits : _T_4210 ? _Queue10_UInt8_12_io_deq_bits : _T_4209 ? _Queue10_UInt8_11_io_deq_bits : _T_4208 ? _Queue10_UInt8_10_io_deq_bits : _T_4207 ? _Queue10_UInt8_9_io_deq_bits : _T_4206 ? _Queue10_UInt8_8_io_deq_bits : _T_4205 ? _Queue10_UInt8_7_io_deq_bits : _T_4204 ? _Queue10_UInt8_6_io_deq_bits : _T_4203 ? _Queue10_UInt8_5_io_deq_bits : _T_4202 ? _Queue10_UInt8_4_io_deq_bits : _T_4201 ? _Queue10_UInt8_3_io_deq_bits : _T_4200 ? _Queue10_UInt8_2_io_deq_bits : _T_4199 ? _Queue10_UInt8_1_io_deq_bits : _T_4198 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_29 = _T_4229 ? _Queue10_UInt8_31_io_deq_valid : _T_4228 ? _Queue10_UInt8_30_io_deq_valid : _T_4227 ? _Queue10_UInt8_29_io_deq_valid : _T_4226 ? _Queue10_UInt8_28_io_deq_valid : _T_4225 ? _Queue10_UInt8_27_io_deq_valid : _T_4224 ? _Queue10_UInt8_26_io_deq_valid : _T_4223 ? _Queue10_UInt8_25_io_deq_valid : _T_4222 ? _Queue10_UInt8_24_io_deq_valid : _T_4221 ? _Queue10_UInt8_23_io_deq_valid : _T_4220 ? _Queue10_UInt8_22_io_deq_valid : _T_4219 ? _Queue10_UInt8_21_io_deq_valid : _T_4218 ? _Queue10_UInt8_20_io_deq_valid : _T_4217 ? _Queue10_UInt8_19_io_deq_valid : _T_4216 ? _Queue10_UInt8_18_io_deq_valid : _T_4215 ? _Queue10_UInt8_17_io_deq_valid : _T_4214 ? _Queue10_UInt8_16_io_deq_valid : _T_4213 ? _Queue10_UInt8_15_io_deq_valid : _T_4212 ? _Queue10_UInt8_14_io_deq_valid : _T_4211 ? _Queue10_UInt8_13_io_deq_valid : _T_4210 ? _Queue10_UInt8_12_io_deq_valid : _T_4209 ? _Queue10_UInt8_11_io_deq_valid : _T_4208 ? _Queue10_UInt8_10_io_deq_valid : _T_4207 ? _Queue10_UInt8_9_io_deq_valid : _T_4206 ? _Queue10_UInt8_8_io_deq_valid : _T_4205 ? _Queue10_UInt8_7_io_deq_valid : _T_4204 ? _Queue10_UInt8_6_io_deq_valid : _T_4203 ? _Queue10_UInt8_5_io_deq_valid : _T_4202 ? _Queue10_UInt8_4_io_deq_valid : _T_4201 ? _Queue10_UInt8_3_io_deq_valid : _T_4200 ? _Queue10_UInt8_2_io_deq_valid : _T_4199 ? _Queue10_UInt8_1_io_deq_valid : _T_4198 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_119 = _remapindex_T_30 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_30 = _GEN_119[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4230 = remapindex_30 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4231 = remapindex_30 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4232 = remapindex_30 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4233 = remapindex_30 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4234 = remapindex_30 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4235 = remapindex_30 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4236 = remapindex_30 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4237 = remapindex_30 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4238 = remapindex_30 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4239 = remapindex_30 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4240 = remapindex_30 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4241 = remapindex_30 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4242 = remapindex_30 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4243 = remapindex_30 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4244 = remapindex_30 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4245 = remapindex_30 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4246 = remapindex_30 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4247 = remapindex_30 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4248 = remapindex_30 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4249 = remapindex_30 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4250 = remapindex_30 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4251 = remapindex_30 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4252 = remapindex_30 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4253 = remapindex_30 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4254 = remapindex_30 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4255 = remapindex_30 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4256 = remapindex_30 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4257 = remapindex_30 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4258 = remapindex_30 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4259 = remapindex_30 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4260 = remapindex_30 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4261 = remapindex_30 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_30 = _T_4261 ? _Queue10_UInt8_31_io_deq_bits : _T_4260 ? _Queue10_UInt8_30_io_deq_bits : _T_4259 ? _Queue10_UInt8_29_io_deq_bits : _T_4258 ? _Queue10_UInt8_28_io_deq_bits : _T_4257 ? _Queue10_UInt8_27_io_deq_bits : _T_4256 ? _Queue10_UInt8_26_io_deq_bits : _T_4255 ? _Queue10_UInt8_25_io_deq_bits : _T_4254 ? _Queue10_UInt8_24_io_deq_bits : _T_4253 ? _Queue10_UInt8_23_io_deq_bits : _T_4252 ? _Queue10_UInt8_22_io_deq_bits : _T_4251 ? _Queue10_UInt8_21_io_deq_bits : _T_4250 ? _Queue10_UInt8_20_io_deq_bits : _T_4249 ? _Queue10_UInt8_19_io_deq_bits : _T_4248 ? _Queue10_UInt8_18_io_deq_bits : _T_4247 ? _Queue10_UInt8_17_io_deq_bits : _T_4246 ? _Queue10_UInt8_16_io_deq_bits : _T_4245 ? _Queue10_UInt8_15_io_deq_bits : _T_4244 ? _Queue10_UInt8_14_io_deq_bits : _T_4243 ? _Queue10_UInt8_13_io_deq_bits : _T_4242 ? _Queue10_UInt8_12_io_deq_bits : _T_4241 ? _Queue10_UInt8_11_io_deq_bits : _T_4240 ? _Queue10_UInt8_10_io_deq_bits : _T_4239 ? _Queue10_UInt8_9_io_deq_bits : _T_4238 ? _Queue10_UInt8_8_io_deq_bits : _T_4237 ? _Queue10_UInt8_7_io_deq_bits : _T_4236 ? _Queue10_UInt8_6_io_deq_bits : _T_4235 ? _Queue10_UInt8_5_io_deq_bits : _T_4234 ? _Queue10_UInt8_4_io_deq_bits : _T_4233 ? _Queue10_UInt8_3_io_deq_bits : _T_4232 ? _Queue10_UInt8_2_io_deq_bits : _T_4231 ? _Queue10_UInt8_1_io_deq_bits : _T_4230 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_30 = _T_4261 ? _Queue10_UInt8_31_io_deq_valid : _T_4260 ? _Queue10_UInt8_30_io_deq_valid : _T_4259 ? _Queue10_UInt8_29_io_deq_valid : _T_4258 ? _Queue10_UInt8_28_io_deq_valid : _T_4257 ? _Queue10_UInt8_27_io_deq_valid : _T_4256 ? _Queue10_UInt8_26_io_deq_valid : _T_4255 ? _Queue10_UInt8_25_io_deq_valid : _T_4254 ? _Queue10_UInt8_24_io_deq_valid : _T_4253 ? _Queue10_UInt8_23_io_deq_valid : _T_4252 ? _Queue10_UInt8_22_io_deq_valid : _T_4251 ? _Queue10_UInt8_21_io_deq_valid : _T_4250 ? _Queue10_UInt8_20_io_deq_valid : _T_4249 ? _Queue10_UInt8_19_io_deq_valid : _T_4248 ? _Queue10_UInt8_18_io_deq_valid : _T_4247 ? _Queue10_UInt8_17_io_deq_valid : _T_4246 ? _Queue10_UInt8_16_io_deq_valid : _T_4245 ? _Queue10_UInt8_15_io_deq_valid : _T_4244 ? _Queue10_UInt8_14_io_deq_valid : _T_4243 ? _Queue10_UInt8_13_io_deq_valid : _T_4242 ? _Queue10_UInt8_12_io_deq_valid : _T_4241 ? _Queue10_UInt8_11_io_deq_valid : _T_4240 ? _Queue10_UInt8_10_io_deq_valid : _T_4239 ? _Queue10_UInt8_9_io_deq_valid : _T_4238 ? _Queue10_UInt8_8_io_deq_valid : _T_4237 ? _Queue10_UInt8_7_io_deq_valid : _T_4236 ? _Queue10_UInt8_6_io_deq_valid : _T_4235 ? _Queue10_UInt8_5_io_deq_valid : _T_4234 ? _Queue10_UInt8_4_io_deq_valid : _T_4233 ? _Queue10_UInt8_3_io_deq_valid : _T_4232 ? _Queue10_UInt8_2_io_deq_valid : _T_4231 ? _Queue10_UInt8_1_io_deq_valid : _T_4230 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_120 = _remapindex_T_31 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_31 = _GEN_120[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4262 = remapindex_31 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4263 = remapindex_31 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4264 = remapindex_31 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4265 = remapindex_31 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4266 = remapindex_31 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4267 = remapindex_31 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4268 = remapindex_31 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4269 = remapindex_31 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4270 = remapindex_31 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4271 = remapindex_31 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4272 = remapindex_31 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4273 = remapindex_31 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4274 = remapindex_31 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4275 = remapindex_31 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4276 = remapindex_31 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4277 = remapindex_31 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4278 = remapindex_31 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4279 = remapindex_31 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4280 = remapindex_31 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4281 = remapindex_31 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4282 = remapindex_31 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4283 = remapindex_31 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4284 = remapindex_31 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4285 = remapindex_31 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4286 = remapindex_31 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4287 = remapindex_31 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4288 = remapindex_31 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4289 = remapindex_31 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4290 = remapindex_31 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4291 = remapindex_31 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4292 = remapindex_31 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4293 = remapindex_31 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_31 = _T_4293 ? _Queue10_UInt8_31_io_deq_bits : _T_4292 ? _Queue10_UInt8_30_io_deq_bits : _T_4291 ? _Queue10_UInt8_29_io_deq_bits : _T_4290 ? _Queue10_UInt8_28_io_deq_bits : _T_4289 ? _Queue10_UInt8_27_io_deq_bits : _T_4288 ? _Queue10_UInt8_26_io_deq_bits : _T_4287 ? _Queue10_UInt8_25_io_deq_bits : _T_4286 ? _Queue10_UInt8_24_io_deq_bits : _T_4285 ? _Queue10_UInt8_23_io_deq_bits : _T_4284 ? _Queue10_UInt8_22_io_deq_bits : _T_4283 ? _Queue10_UInt8_21_io_deq_bits : _T_4282 ? _Queue10_UInt8_20_io_deq_bits : _T_4281 ? _Queue10_UInt8_19_io_deq_bits : _T_4280 ? _Queue10_UInt8_18_io_deq_bits : _T_4279 ? _Queue10_UInt8_17_io_deq_bits : _T_4278 ? _Queue10_UInt8_16_io_deq_bits : _T_4277 ? _Queue10_UInt8_15_io_deq_bits : _T_4276 ? _Queue10_UInt8_14_io_deq_bits : _T_4275 ? _Queue10_UInt8_13_io_deq_bits : _T_4274 ? _Queue10_UInt8_12_io_deq_bits : _T_4273 ? _Queue10_UInt8_11_io_deq_bits : _T_4272 ? _Queue10_UInt8_10_io_deq_bits : _T_4271 ? _Queue10_UInt8_9_io_deq_bits : _T_4270 ? _Queue10_UInt8_8_io_deq_bits : _T_4269 ? _Queue10_UInt8_7_io_deq_bits : _T_4268 ? _Queue10_UInt8_6_io_deq_bits : _T_4267 ? _Queue10_UInt8_5_io_deq_bits : _T_4266 ? _Queue10_UInt8_4_io_deq_bits : _T_4265 ? _Queue10_UInt8_3_io_deq_bits : _T_4264 ? _Queue10_UInt8_2_io_deq_bits : _T_4263 ? _Queue10_UInt8_1_io_deq_bits : _T_4262 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_31 = _T_4293 ? _Queue10_UInt8_31_io_deq_valid : _T_4292 ? _Queue10_UInt8_30_io_deq_valid : _T_4291 ? _Queue10_UInt8_29_io_deq_valid : _T_4290 ? _Queue10_UInt8_28_io_deq_valid : _T_4289 ? _Queue10_UInt8_27_io_deq_valid : _T_4288 ? _Queue10_UInt8_26_io_deq_valid : _T_4287 ? _Queue10_UInt8_25_io_deq_valid : _T_4286 ? _Queue10_UInt8_24_io_deq_valid : _T_4285 ? _Queue10_UInt8_23_io_deq_valid : _T_4284 ? _Queue10_UInt8_22_io_deq_valid : _T_4283 ? _Queue10_UInt8_21_io_deq_valid : _T_4282 ? _Queue10_UInt8_20_io_deq_valid : _T_4281 ? _Queue10_UInt8_19_io_deq_valid : _T_4280 ? _Queue10_UInt8_18_io_deq_valid : _T_4279 ? _Queue10_UInt8_17_io_deq_valid : _T_4278 ? _Queue10_UInt8_16_io_deq_valid : _T_4277 ? _Queue10_UInt8_15_io_deq_valid : _T_4276 ? _Queue10_UInt8_14_io_deq_valid : _T_4275 ? _Queue10_UInt8_13_io_deq_valid : _T_4274 ? _Queue10_UInt8_12_io_deq_valid : _T_4273 ? _Queue10_UInt8_11_io_deq_valid : _T_4272 ? _Queue10_UInt8_10_io_deq_valid : _T_4271 ? _Queue10_UInt8_9_io_deq_valid : _T_4270 ? _Queue10_UInt8_8_io_deq_valid : _T_4269 ? _Queue10_UInt8_7_io_deq_valid : _T_4268 ? _Queue10_UInt8_6_io_deq_valid : _T_4267 ? _Queue10_UInt8_5_io_deq_valid : _T_4266 ? _Queue10_UInt8_4_io_deq_valid : _T_4265 ? _Queue10_UInt8_3_io_deq_valid : _T_4264 ? _Queue10_UInt8_2_io_deq_valid : _T_4263 ? _Queue10_UInt8_1_io_deq_valid : _T_4262 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [15:0] io_consumer_output_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_lo_lo = {io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_lo_hi = {io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_lo_lo = {io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_hi_lo = {io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_hi_hi = {io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_lo_hi = {io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [127:0] io_consumer_output_data_lo = {io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_lo_lo = {io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_lo_hi = {io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_hi_lo = {io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_hi_lo = {io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_hi_hi = {io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_hi_hi = {io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [127:0] io_consumer_output_data_hi = {io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] assign _io_consumer_output_data_T = {io_consumer_output_data_hi, io_consumer_output_data_lo}; // @[ZstdLitRotBuf.scala:246:33] assign io_consumer_output_data_0 = _io_consumer_output_data_T; // @[ZstdLitRotBuf.scala:152:7, :246:33] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[ZstdLitRotBuf.scala:185:{75,91}, :226:28, :249:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[ZstdLitRotBuf.scala:185:{75,91}, :226:28, :249:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[ZstdLitRotBuf.scala:226:28, :249:60] assign enough_data = \|count_valids; // @[ZstdLitRotBuf.scala:249:60, :251:34] assign io_consumer_output_valid_0 = enough_data; // @[ZstdLitRotBuf.scala:152:7, :251:34] assign io_consumer_available_output_bytes_0 = count_valids[5:0]; // @[ZstdLitRotBuf.scala:152:7, :249:60, :253:38] wire _T_4303 = io_consumer_output_ready_0 & enough_data; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_4303; // @[Misc.scala:29:18] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module SourceB_2 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}} regreset remain : UInt<1>, clock, reset, UInt<1>(0h0) wire remain_set : UInt<1> connect remain_set, UInt<1>(0h0) wire remain_clr : UInt<1> connect remain_clr, UInt<1>(0h0) node _remain_T = or(remain, remain_set) node _remain_T_1 = not(remain_clr) node _remain_T_2 = and(_remain_T, _remain_T_1) connect remain, _remain_T_2 node busy = orr(remain) node todo = mux(busy, remain, io.req.bits.clients) node _next_T = bits(todo, 0, 0) node _next_T_1 = shl(_next_T, 1) node _next_T_2 = not(_next_T_1) node next = and(_next_T_2, todo) node _T = eq(io.req.valid, UInt<1>(0h0)) node _T_1 = neq(io.req.bits.clients, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceB.scala:59 assert (!io.req.valid \|\| io.req.bits.clients =/= 0.U)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _T_6 = and(io.req.ready, io.req.valid) when _T_6 : connect remain_set, io.req.bits.clients wire b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect io.b, b node _b_valid_T = or(busy, io.req.valid) connect b.valid, _b_valid_T node _T_7 = and(b.ready, b.valid) when _T_7 : connect remain_clr, next node _T_8 = eq(b.ready, UInt<1>(0h0)) node _T_9 = and(b.valid, _T_8) node _tag_T = eq(busy, UInt<1>(0h0)) node _tag_T_1 = and(io.req.ready, io.req.valid) reg tag_r : UInt<9>, clock when _tag_T_1 : connect tag_r, io.req.bits.tag node tag = mux(_tag_T, io.req.bits.tag, tag_r) node _set_T = eq(busy, UInt<1>(0h0)) node _set_T_1 = and(io.req.ready, io.req.valid) reg set_r : UInt<11>, clock when _set_T_1 : connect set_r, io.req.bits.set node set = mux(_set_T, io.req.bits.set, set_r) node _param_T = eq(busy, UInt<1>(0h0)) node _param_T_1 = and(io.req.ready, io.req.valid) reg param_r : UInt<3>, clock when _param_T_1 : connect param_r, io.req.bits.param node param = mux(_param_T, io.req.bits.param, param_r) connect b.bits.opcode, UInt<3>(0h6) connect b.bits.param, param connect b.bits.size, UInt<3>(0h6) node _b_bits_source_T = bits(next, 0, 0) connect b.bits.source, UInt<6>(0h28) node b_bits_address_base_y = or(tag, UInt<9>(0h0)) node _b_bits_address_base_T = shr(b_bits_address_base_y, 9) node _b_bits_address_base_T_1 = eq(_b_bits_address_base_T, UInt<1>(0h0)) node _b_bits_address_base_T_2 = asUInt(reset) node _b_bits_address_base_T_3 = eq(_b_bits_address_base_T_2, UInt<1>(0h0)) when _b_bits_address_base_T_3 : node _b_bits_address_base_T_4 = eq(_b_bits_address_base_T_1, UInt<1>(0h0)) when _b_bits_address_base_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf assert(clock, _b_bits_address_base_T_1, UInt<1>(0h1), "") : b_bits_address_base_assert node _b_bits_address_base_T_5 = bits(b_bits_address_base_y, 8, 0) node b_bits_address_base_y_1 = or(set, UInt<11>(0h0)) node _b_bits_address_base_T_6 = shr(b_bits_address_base_y_1, 11) node _b_bits_address_base_T_7 = eq(_b_bits_address_base_T_6, UInt<1>(0h0)) node _b_bits_address_base_T_8 = asUInt(reset) node _b_bits_address_base_T_9 = eq(_b_bits_address_base_T_8, UInt<1>(0h0)) when _b_bits_address_base_T_9 : node _b_bits_address_base_T_10 = eq(_b_bits_address_base_T_7, UInt<1>(0h0)) when _b_bits_address_base_T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_1 assert(clock, _b_bits_address_base_T_7, UInt<1>(0h1), "") : b_bits_address_base_assert_1 node _b_bits_address_base_T_11 = bits(b_bits_address_base_y_1, 10, 0) node b_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0)) node _b_bits_address_base_T_12 = shr(b_bits_address_base_y_2, 6) node _b_bits_address_base_T_13 = eq(_b_bits_address_base_T_12, UInt<1>(0h0)) node _b_bits_address_base_T_14 = asUInt(reset) node _b_bits_address_base_T_15 = eq(_b_bits_address_base_T_14, UInt<1>(0h0)) when _b_bits_address_base_T_15 : node _b_bits_address_base_T_16 = eq(_b_bits_address_base_T_13, UInt<1>(0h0)) when _b_bits_address_base_T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_2 assert(clock, _b_bits_address_base_T_13, UInt<1>(0h1), "") : b_bits_address_base_assert_2 node _b_bits_address_base_T_17 = bits(b_bits_address_base_y_2, 5, 0) node b_bits_address_base_hi = cat(_b_bits_address_base_T_5, _b_bits_address_base_T_11) node b_bits_address_base = cat(b_bits_address_base_hi, _b_bits_address_base_T_17) node _b_bits_address_T = bits(b_bits_address_base, 0, 0) node _b_bits_address_T_1 = bits(b_bits_address_base, 1, 1) node _b_bits_address_T_2 = bits(b_bits_address_base, 2, 2) node _b_bits_address_T_3 = bits(b_bits_address_base, 3, 3) node _b_bits_address_T_4 = bits(b_bits_address_base, 4, 4) node _b_bits_address_T_5 = bits(b_bits_address_base, 5, 5) node _b_bits_address_T_6 = bits(b_bits_address_base, 6, 6) node _b_bits_address_T_7 = bits(b_bits_address_base, 7, 7) node _b_bits_address_T_8 = bits(b_bits_address_base, 8, 8) node _b_bits_address_T_9 = bits(b_bits_address_base, 9, 9) node _b_bits_address_T_10 = bits(b_bits_address_base, 10, 10) node _b_bits_address_T_11 = bits(b_bits_address_base, 11, 11) node _b_bits_address_T_12 = bits(b_bits_address_base, 12, 12) node _b_bits_address_T_13 = bits(b_bits_address_base, 13, 13) node _b_bits_address_T_14 = bits(b_bits_address_base, 14, 14) node _b_bits_address_T_15 = bits(b_bits_address_base, 15, 15) node _b_bits_address_T_16 = bits(b_bits_address_base, 16, 16) node _b_bits_address_T_17 = bits(b_bits_address_base, 17, 17) node _b_bits_address_T_18 = bits(b_bits_address_base, 18, 18) node _b_bits_address_T_19 = bits(b_bits_address_base, 19, 19) node _b_bits_address_T_20 = bits(b_bits_address_base, 20, 20) node _b_bits_address_T_21 = bits(b_bits_address_base, 21, 21) node _b_bits_address_T_22 = bits(b_bits_address_base, 22, 22) node _b_bits_address_T_23 = bits(b_bits_address_base, 23, 23) node _b_bits_address_T_24 = bits(b_bits_address_base, 24, 24) node _b_bits_address_T_25 = bits(b_bits_address_base, 25, 25) node b_bits_address_lo_lo_lo_lo = cat(_b_bits_address_T_1, _b_bits_address_T) node b_bits_address_lo_lo_lo_hi = cat(_b_bits_address_T_3, _b_bits_address_T_2) node b_bits_address_lo_lo_lo = cat(b_bits_address_lo_lo_lo_hi, b_bits_address_lo_lo_lo_lo) node b_bits_address_lo_lo_hi_lo = cat(_b_bits_address_T_5, _b_bits_address_T_4) node b_bits_address_lo_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node b_bits_address_lo_lo_hi = cat(b_bits_address_lo_lo_hi_hi, b_bits_address_lo_lo_hi_lo) node b_bits_address_lo_lo = cat(b_bits_address_lo_lo_hi, b_bits_address_lo_lo_lo) node b_bits_address_lo_hi_lo_lo = cat(_b_bits_address_T_6, UInt<1>(0h0)) node b_bits_address_lo_hi_lo_hi = cat(_b_bits_address_T_8, _b_bits_address_T_7) node b_bits_address_lo_hi_lo = cat(b_bits_address_lo_hi_lo_hi, b_bits_address_lo_hi_lo_lo) node b_bits_address_lo_hi_hi_lo = cat(_b_bits_address_T_10, _b_bits_address_T_9) node b_bits_address_lo_hi_hi_hi = cat(_b_bits_address_T_12, _b_bits_address_T_11) node b_bits_address_lo_hi_hi = cat(b_bits_address_lo_hi_hi_hi, b_bits_address_lo_hi_hi_lo) node b_bits_address_lo_hi = cat(b_bits_address_lo_hi_hi, b_bits_address_lo_hi_lo) node b_bits_address_lo = cat(b_bits_address_lo_hi, b_bits_address_lo_lo) node b_bits_address_hi_lo_lo_lo = cat(_b_bits_address_T_14, _b_bits_address_T_13) node b_bits_address_hi_lo_lo_hi = cat(_b_bits_address_T_16, _b_bits_address_T_15) node b_bits_address_hi_lo_lo = cat(b_bits_address_hi_lo_lo_hi, b_bits_address_hi_lo_lo_lo) node b_bits_address_hi_lo_hi_lo = cat(_b_bits_address_T_18, _b_bits_address_T_17) node b_bits_address_hi_lo_hi_hi = cat(_b_bits_address_T_20, _b_bits_address_T_19) node b_bits_address_hi_lo_hi = cat(b_bits_address_hi_lo_hi_hi, b_bits_address_hi_lo_hi_lo) node b_bits_address_hi_lo = cat(b_bits_address_hi_lo_hi, b_bits_address_hi_lo_lo) node b_bits_address_hi_hi_lo_lo = cat(_b_bits_address_T_22, _b_bits_address_T_21) node b_bits_address_hi_hi_lo_hi = cat(_b_bits_address_T_24, _b_bits_address_T_23) node b_bits_address_hi_hi_lo = cat(b_bits_address_hi_hi_lo_hi, b_bits_address_hi_hi_lo_lo) node b_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node b_bits_address_hi_hi_hi_hi = cat(_b_bits_address_T_25, UInt<1>(0h0)) node b_bits_address_hi_hi_hi = cat(b_bits_address_hi_hi_hi_hi, b_bits_address_hi_hi_hi_lo) node b_bits_address_hi_hi = cat(b_bits_address_hi_hi_hi, b_bits_address_hi_hi_lo) node b_bits_address_hi = cat(b_bits_address_hi_hi, b_bits_address_hi_lo) node _b_bits_address_T_26 = cat(b_bits_address_hi, b_bits_address_lo) connect b.bits.address, _b_bits_address_T_26 node _b_bits_mask_T = not(UInt<16>(0h0)) connect b.bits.mask, _b_bits_mask_T connect b.bits.data, UInt<1>(0h0) connect b.bits.corrupt, UInt<1>(0h0)	module SourceB_2( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [8:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [10:0] io_req_bits_set, // @[SourceB.scala:35:14] input io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [5:0] io_b_bits_source = 6'h28; // @[SourceB.scala:33:7] wire [5:0] b_bits_source = 6'h28; // @[SourceB.scala:65:17] wire [15:0] io_b_bits_mask = 16'hFFFF; // @[SourceB.scala:33:7] wire [15:0] b_bits_mask = 16'hFFFF; // @[SourceB.scala:65:17] wire [15:0] _b_bits_mask_T = 16'hFFFF; // @[SourceB.scala:81:23] wire [127:0] io_b_bits_data = 128'h0; // @[SourceB.scala:33:7] wire [127:0] b_bits_data = 128'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_lo_lo_hi_hi = 2'h0; // @[Parameters.scala:230:8] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg remain; // @[SourceB.scala:46:25] wire busy = remain; // @[SourceB.scala:46:25, :51:23] wire remain_set; // @[SourceB.scala:47:30] wire remain_clr; // @[SourceB.scala:48:30] wire _remain_T = remain \| remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire _next_T = todo; // @[package.scala:254:17] wire [1:0] _next_T_1 = {_next_T, 1'h0}; // @[package.scala:254:17] wire [1:0] _next_T_2 = ~_next_T_1; // @[SourceB.scala:53:{16,31}] wire [1:0] next = {1'h0, _next_T_2[0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_126 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_126( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_152 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_152( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_5 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_10 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_5 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h15), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h13), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _T_3 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _T_4 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_5 = or(_T, _T_1) node _T_6 = or(_T_5, _T_2) node _T_7 = or(_T_6, _T_3) node _T_8 = or(_T_7, _T_4) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = and(io.in.valid, _T_9) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_11, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h2) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h13), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h13), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<2> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<1>(0h1)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`1`[1], io.router_resp.vc_sel.`1`[1] connect route_q.io.enq.bits.vc_sel.`1`[2], io.router_resp.vc_sel.`1`[2] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`2`[1], io.router_resp.vc_sel.`2`[1] connect route_q.io.enq.bits.vc_sel.`2`[2], io.router_resp.vc_sel.`2`[2] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_15 = and(io.in.ready, io.in.valid) node _T_16 = and(_T_15, io.in.bits.head) node _T_17 = and(_T_16, at_dest) when _T_17 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_18 = eq(UInt<2>(0h2), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_19 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_20 = and(route_q.io.enq.valid, _T_19) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_11 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_5 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`1`[1], io.vcalloc_resp.vc_sel.`1`[1] connect vcalloc_q.io.enq.bits.vc_sel.`1`[2], io.vcalloc_resp.vc_sel.`1`[2] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[1], io.vcalloc_resp.vc_sel.`2`[1] connect vcalloc_q.io.enq.bits.vc_sel.`2`[2], io.vcalloc_resp.vc_sel.`2`[2] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_25 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_26 = and(vcalloc_q.io.enq.valid, _T_25) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _c_T = cat(c_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[2], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node _c_T_1 = cat(c_hi_1, vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node c_hi_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[2], vcalloc_q.io.deq.bits.vc_sel.`2`[1]) node _c_T_2 = cat(c_hi_2, vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node c_lo = cat(_c_T_1, _c_T) node c_hi_3 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], _c_T_2) node _c_T_3 = cat(c_hi_3, c_lo) node c_hi_4 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _c_T_4 = cat(c_hi_4, io.out_credit_available.`0`[0]) node c_hi_5 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _c_T_5 = cat(c_hi_5, io.out_credit_available.`1`[0]) node c_hi_6 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _c_T_6 = cat(c_hi_6, io.out_credit_available.`2`[0]) node c_lo_1 = cat(_c_T_5, _c_T_4) node c_hi_7 = cat(io.out_credit_available.`3`[0], _c_T_6) node _c_T_7 = cat(c_hi_7, c_lo_1) node _c_T_8 = and(_c_T_3, _c_T_7) node c = neq(_c_T_8, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 wire out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}} connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node out_channel_oh_0 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_1 = or(vcalloc_q.io.deq.bits.vc_sel.`1`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node out_channel_oh_1 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`1`[2]) node _out_channel_oh_T_2 = or(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[1]) node out_channel_oh_2 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`2`[2]) node out_bundle_bits_out_virt_channel_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 2, 2) node out_bundle_bits_out_virt_channel_lo = bits(_out_bundle_bits_out_virt_channel_T, 1, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo) node _out_bundle_bits_out_virt_channel_T_3 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 1) node _out_bundle_bits_out_virt_channel_T_4 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_3) node out_bundle_bits_out_virt_channel_hi_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[2], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node _out_bundle_bits_out_virt_channel_T_5 = cat(out_bundle_bits_out_virt_channel_hi_2, vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_5, 2, 2) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T_5, 1, 0) node _out_bundle_bits_out_virt_channel_T_6 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_7 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_1) node _out_bundle_bits_out_virt_channel_T_8 = bits(_out_bundle_bits_out_virt_channel_T_7, 1, 1) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_6, _out_bundle_bits_out_virt_channel_T_8) node out_bundle_bits_out_virt_channel_hi_4 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[2], vcalloc_q.io.deq.bits.vc_sel.`2`[1]) node _out_bundle_bits_out_virt_channel_T_10 = cat(out_bundle_bits_out_virt_channel_hi_4, vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node out_bundle_bits_out_virt_channel_hi_5 = bits(_out_bundle_bits_out_virt_channel_T_10, 2, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_10, 1, 0) node _out_bundle_bits_out_virt_channel_T_11 = orr(out_bundle_bits_out_virt_channel_hi_5) node _out_bundle_bits_out_virt_channel_T_12 = or(out_bundle_bits_out_virt_channel_hi_5, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_13 = bits(_out_bundle_bits_out_virt_channel_T_12, 1, 1) node _out_bundle_bits_out_virt_channel_T_14 = cat(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_13) node _out_bundle_bits_out_virt_channel_T_15 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_4, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_16 = mux(out_channel_oh_1, _out_bundle_bits_out_virt_channel_T_9, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_17 = mux(out_channel_oh_2, _out_bundle_bits_out_virt_channel_T_14, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_18 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_19 = or(_out_bundle_bits_out_virt_channel_T_15, _out_bundle_bits_out_virt_channel_T_16) node _out_bundle_bits_out_virt_channel_T_20 = or(_out_bundle_bits_out_virt_channel_T_19, _out_bundle_bits_out_virt_channel_T_17) node _out_bundle_bits_out_virt_channel_T_21 = or(_out_bundle_bits_out_virt_channel_T_20, _out_bundle_bits_out_virt_channel_T_18) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<2> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_21 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_5( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h13; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 4'hA : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'h9 : 4'h0); // @[Mux.scala:30:73] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_T_10[3], _route_buffer_io_enq_bits_flow_egress_node_T_10[2:0] \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 3'h6 : 3'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0)}; // @[Mux.scala:30:73] wire [1:0] _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_3, 1'h0}; // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'h1; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'h1; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_28 : output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulRawFN of MulRawFN_28 node mulRawFN_io_a_exp = bits(io.a, 31, 23) node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6) node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7) node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T) connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1 node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1) connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2 connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32) connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp) connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0)) node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T) node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0) node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2) connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3 connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN node mulRawFN_io_b_exp = bits(io.b, 31, 23) node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6) node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7) node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T) connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1 node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1) connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2 connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32) connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp) connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0)) node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T) node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0) node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2) connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3 connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_95 connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulRecFN_28( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_28 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_95 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module L2MemHelperLatencyInjection_9 : input clock : Clock input reset : Reset output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} output io : { flip userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip latency_inject_cycles : UInt<64>, flip sfence : UInt<1>, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip status : { valid : UInt<1>, bits : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect auto.master_out, masterNodeOut wire request_input : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}} connect request_input, io.userif.req wire response_output : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}} connect io.userif.resp, response_output reg status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock when io.status.valid : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] setting status.dprv to: %x compare %x\n", io.status.bits.dprv, UInt<2>(0h3)) : printf_1 connect status, io.status.bits inst tlb of DTLB_11 connect tlb.clock, clock connect tlb.reset, reset connect tlb.io.req.valid, request_input.valid connect tlb.io.req.bits.vaddr, request_input.bits.addr connect tlb.io.req.bits.size, request_input.bits.size connect tlb.io.req.bits.cmd, request_input.bits.cmd connect tlb.io.req.bits.passthrough, UInt<1>(0h0) node _tlb_ready_T = eq(tlb.io.resp.miss, UInt<1>(0h0)) node tlb_ready = and(tlb.io.req.ready, _tlb_ready_T) invalidate tlb.io.req.bits.prv invalidate tlb.io.req.bits.v invalidate tlb.io.sfence.bits.hv invalidate tlb.io.sfence.bits.hg connect tlb.io.ptw.customCSRs, io.ptw.customCSRs connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] connect tlb.io.ptw.gstatus, io.ptw.gstatus connect tlb.io.ptw.hstatus, io.ptw.hstatus connect tlb.io.ptw.status, io.ptw.status connect tlb.io.ptw.vsatp, io.ptw.vsatp connect tlb.io.ptw.hgatp, io.ptw.hgatp connect tlb.io.ptw.ptbr, io.ptw.ptbr connect tlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, tlb.io.ptw.req.bits connect io.ptw.req.valid, tlb.io.ptw.req.valid connect tlb.io.ptw.req.ready, io.ptw.req.ready connect tlb.io.ptw.status.uie, status.uie connect tlb.io.ptw.status.sie, status.sie connect tlb.io.ptw.status.hie, status.hie connect tlb.io.ptw.status.mie, status.mie connect tlb.io.ptw.status.upie, status.upie connect tlb.io.ptw.status.spie, status.spie connect tlb.io.ptw.status.ube, status.ube connect tlb.io.ptw.status.mpie, status.mpie connect tlb.io.ptw.status.spp, status.spp connect tlb.io.ptw.status.vs, status.vs connect tlb.io.ptw.status.mpp, status.mpp connect tlb.io.ptw.status.fs, status.fs connect tlb.io.ptw.status.xs, status.xs connect tlb.io.ptw.status.mprv, status.mprv connect tlb.io.ptw.status.sum, status.sum connect tlb.io.ptw.status.mxr, status.mxr connect tlb.io.ptw.status.tvm, status.tvm connect tlb.io.ptw.status.tw, status.tw connect tlb.io.ptw.status.tsr, status.tsr connect tlb.io.ptw.status.zero1, status.zero1 connect tlb.io.ptw.status.sd_rv32, status.sd_rv32 connect tlb.io.ptw.status.uxl, status.uxl connect tlb.io.ptw.status.sxl, status.sxl connect tlb.io.ptw.status.sbe, status.sbe connect tlb.io.ptw.status.mbe, status.mbe connect tlb.io.ptw.status.gva, status.gva connect tlb.io.ptw.status.mpv, status.mpv connect tlb.io.ptw.status.zero2, status.zero2 connect tlb.io.ptw.status.sd, status.sd connect tlb.io.ptw.status.v, status.v connect tlb.io.ptw.status.prv, status.prv connect tlb.io.ptw.status.dv, status.dv connect tlb.io.ptw.status.dprv, status.dprv connect tlb.io.ptw.status.isa, status.isa connect tlb.io.ptw.status.wfi, status.wfi connect tlb.io.ptw.status.cease, status.cease connect tlb.io.ptw.status.debug, status.debug connect tlb.io.sfence.valid, io.sfence connect tlb.io.sfence.bits.rs1, UInt<1>(0h0) connect tlb.io.sfence.bits.rs2, UInt<1>(0h0) connect tlb.io.sfence.bits.addr, UInt<1>(0h0) connect tlb.io.sfence.bits.asid, UInt<1>(0h0) connect tlb.io.kill, UInt<1>(0h0) inst outstanding_req_addr of Queue16_L2InternalTracking_3 connect outstanding_req_addr.clock, clock connect outstanding_req_addr.reset, reset inst tags_for_issue_Q of Queue8_UInt2_3 connect tags_for_issue_Q.clock, clock connect tags_for_issue_Q.reset, reset connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h0) invalidate tags_for_issue_Q.io.enq.bits regreset tags_init_reg : UInt<3>, clock, reset, UInt<3>(0h0) node _T_4 = neq(tags_init_reg, UInt<3>(0h4)) when _T_4 : connect tags_for_issue_Q.io.enq.bits, tags_init_reg connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) when tags_for_issue_Q.io.enq.ready : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] tags_for_issue_Q init with value %d\n", tags_for_issue_Q.io.enq.bits) : printf_3 node _tags_init_reg_T = add(tags_init_reg, UInt<1>(0h1)) node _tags_init_reg_T_1 = tail(_tags_init_reg_T, 1) connect tags_init_reg, _tags_init_reg_T_1 node _addr_mask_check_T = dshl(UInt<64>(0h1), request_input.bits.size) node _addr_mask_check_T_1 = sub(_addr_mask_check_T, UInt<1>(0h1)) node addr_mask_check = tail(_addr_mask_check_T_1, 1) node _assertcheck_T = eq(request_input.valid, UInt<1>(0h0)) node _assertcheck_T_1 = and(request_input.bits.addr, addr_mask_check) node _assertcheck_T_2 = eq(_assertcheck_T_1, UInt<1>(0h0)) node _assertcheck_T_3 = or(_assertcheck_T, _assertcheck_T_2) reg assertcheck : UInt<1>, clock connect assertcheck, _assertcheck_T_3 node _T_9 = eq(assertcheck, UInt<1>(0h0)) when _T_9 : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: access addr must be aligned to write width\n") : printf_5 node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(assertcheck, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed: [huf_jt_writer] L2IF: access addr must be aligned to write width\n\n at L2MemHelperLatencyInjection.scala:114 assert(assertcheck,\n") : printf_6 assert(clock, assertcheck, UInt<1>(0h1), "") : assert regreset global_memop_accepted : UInt<64>, clock, reset, UInt<64>(0h0) node _T_17 = and(io.userif.req.ready, io.userif.req.valid) when _T_17 : node _global_memop_accepted_T = add(global_memop_accepted, UInt<1>(0h1)) node _global_memop_accepted_T_1 = tail(_global_memop_accepted_T, 1) connect global_memop_accepted, _global_memop_accepted_T_1 regreset global_memop_sent : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_ackd : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_resp_to_user : UInt<64>, clock, reset, UInt<64>(0h0) node _io_userif_no_memops_inflight_T = eq(global_memop_accepted, global_memop_ackd) connect io.userif.no_memops_inflight, _io_userif_no_memops_inflight_T node _free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _free_outstanding_op_slots_T_1 = tail(_free_outstanding_op_slots_T, 1) node free_outstanding_op_slots = lt(_free_outstanding_op_slots_T_1, UInt<3>(0h4)) node _assert_free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _assert_free_outstanding_op_slots_T_1 = tail(_assert_free_outstanding_op_slots_T, 1) node assert_free_outstanding_op_slots = leq(_assert_free_outstanding_op_slots_T_1, UInt<3>(0h4)) node _T_18 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_18 : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_7 node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: Too many outstanding requests for tag count.\n") : printf_8 node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed: [huf_jt_writer] L2IF: Too many outstanding requests for tag count.\n\n at L2MemHelperLatencyInjection.scala:136 assert(assert_free_outstanding_op_slots,\n") : printf_9 assert(clock, assert_free_outstanding_op_slots, UInt<1>(0h1), "") : assert_1 node _T_26 = and(request_input.ready, request_input.valid) when _T_26 : node _global_memop_sent_T = add(global_memop_sent, UInt<1>(0h1)) node _global_memop_sent_T_1 = tail(_global_memop_sent_T, 1) connect global_memop_sent, _global_memop_sent_T_1 regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0) node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1)) node _cur_cycle_T_1 = tail(_cur_cycle_T, 1) connect cur_cycle, _cur_cycle_T_1 inst request_latency_injection_q of LatencyInjectionQueue_18 connect request_latency_injection_q.clock, clock connect request_latency_injection_q.reset, reset connect request_latency_injection_q.io.latency_cycles, io.latency_inject_cycles invalidate request_latency_injection_q.io.enq.bits.corrupt invalidate request_latency_injection_q.io.enq.bits.data invalidate request_latency_injection_q.io.enq.bits.mask invalidate request_latency_injection_q.io.enq.bits.address invalidate request_latency_injection_q.io.enq.bits.source invalidate request_latency_injection_q.io.enq.bits.size invalidate request_latency_injection_q.io.enq.bits.param invalidate request_latency_injection_q.io.enq.bits.opcode node _T_27 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_27 : node _legal_T = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_1 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_2 = and(_legal_T, _legal_T_1) node _legal_T_3 = or(UInt<1>(0h0), _legal_T_2) node _legal_T_4 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_5 = cvt(_legal_T_4) node _legal_T_6 = and(_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _legal_T_7 = asSInt(_legal_T_6) node _legal_T_8 = eq(_legal_T_7, asSInt(UInt<1>(0h0))) node _legal_T_9 = and(_legal_T_3, _legal_T_8) node _legal_T_10 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_11 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_12 = and(_legal_T_10, _legal_T_11) node _legal_T_13 = or(UInt<1>(0h0), _legal_T_12) node _legal_T_14 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_15 = cvt(_legal_T_14) node _legal_T_16 = and(_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _legal_T_17 = asSInt(_legal_T_16) node _legal_T_18 = eq(_legal_T_17, asSInt(UInt<1>(0h0))) node _legal_T_19 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_20 = cvt(_legal_T_19) node _legal_T_21 = and(_legal_T_20, asSInt(UInt<33>(0h98013000))) node _legal_T_22 = asSInt(_legal_T_21) node _legal_T_23 = eq(_legal_T_22, asSInt(UInt<1>(0h0))) node _legal_T_24 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_25 = cvt(_legal_T_24) node _legal_T_26 = and(_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _legal_T_27 = asSInt(_legal_T_26) node _legal_T_28 = eq(_legal_T_27, asSInt(UInt<1>(0h0))) node _legal_T_29 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_30 = cvt(_legal_T_29) node _legal_T_31 = and(_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _legal_T_32 = asSInt(_legal_T_31) node _legal_T_33 = eq(_legal_T_32, asSInt(UInt<1>(0h0))) node _legal_T_34 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_35 = cvt(_legal_T_34) node _legal_T_36 = and(_legal_T_35, asSInt(UInt<33>(0h98000000))) node _legal_T_37 = asSInt(_legal_T_36) node _legal_T_38 = eq(_legal_T_37, asSInt(UInt<1>(0h0))) node _legal_T_39 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_40 = cvt(_legal_T_39) node _legal_T_41 = and(_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _legal_T_42 = asSInt(_legal_T_41) node _legal_T_43 = eq(_legal_T_42, asSInt(UInt<1>(0h0))) node _legal_T_44 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_45 = cvt(_legal_T_44) node _legal_T_46 = and(_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _legal_T_47 = asSInt(_legal_T_46) node _legal_T_48 = eq(_legal_T_47, asSInt(UInt<1>(0h0))) node _legal_T_49 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_50 = cvt(_legal_T_49) node _legal_T_51 = and(_legal_T_50, asSInt(UInt<33>(0h90000000))) node _legal_T_52 = asSInt(_legal_T_51) node _legal_T_53 = eq(_legal_T_52, asSInt(UInt<1>(0h0))) node _legal_T_54 = or(_legal_T_18, _legal_T_23) node _legal_T_55 = or(_legal_T_54, _legal_T_28) node _legal_T_56 = or(_legal_T_55, _legal_T_33) node _legal_T_57 = or(_legal_T_56, _legal_T_38) node _legal_T_58 = or(_legal_T_57, _legal_T_43) node _legal_T_59 = or(_legal_T_58, _legal_T_48) node _legal_T_60 = or(_legal_T_59, _legal_T_53) node _legal_T_61 = and(_legal_T_13, _legal_T_60) node _legal_T_62 = or(UInt<1>(0h0), _legal_T_9) node legal = or(_legal_T_62, _legal_T_61) wire bundle : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle.opcode, UInt<3>(0h4) connect bundle.param, UInt<1>(0h0) connect bundle.size, request_input.bits.size connect bundle.source, tags_for_issue_Q.io.deq.bits connect bundle.address, tlb.io.resp.paddr node _a_mask_sizeOH_T = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T = pad(_a_mask_sizeOH_T, 3) node a_mask_sizeOH_shiftAmount = bits(_a_mask_sizeOH_shiftAmount_T, 2, 0) node _a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount) node _a_mask_sizeOH_T_2 = bits(_a_mask_sizeOH_T_1, 4, 0) node a_mask_sizeOH = or(_a_mask_sizeOH_T_2, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size = bits(a_mask_sizeOH, 4, 4) node a_mask_sub_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_0_2) node a_mask_sub_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit) node _a_mask_sub_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_1_2) node a_mask_sub_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_size = bits(a_mask_sizeOH, 3, 3) node a_mask_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_0_2) node a_mask_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_1_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_1_2) node a_mask_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_2_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_2_2) node a_mask_sub_sub_sub_2_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_3_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_3_2) node a_mask_sub_sub_sub_3_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_3) node a_mask_sub_sub_size = bits(a_mask_sizeOH, 2, 2) node a_mask_sub_sub_bit = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit = eq(a_mask_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_0_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T = and(a_mask_sub_sub_size, a_mask_sub_sub_0_2) node a_mask_sub_sub_0_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T) node a_mask_sub_sub_1_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_1 = and(a_mask_sub_sub_size, a_mask_sub_sub_1_2) node a_mask_sub_sub_1_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T_1) node a_mask_sub_sub_2_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_2 = and(a_mask_sub_sub_size, a_mask_sub_sub_2_2) node a_mask_sub_sub_2_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_2) node a_mask_sub_sub_3_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_3 = and(a_mask_sub_sub_size, a_mask_sub_sub_3_2) node a_mask_sub_sub_3_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_3) node a_mask_sub_sub_4_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_4 = and(a_mask_sub_sub_size, a_mask_sub_sub_4_2) node a_mask_sub_sub_4_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_4) node a_mask_sub_sub_5_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_5 = and(a_mask_sub_sub_size, a_mask_sub_sub_5_2) node a_mask_sub_sub_5_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_5) node a_mask_sub_sub_6_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_6 = and(a_mask_sub_sub_size, a_mask_sub_sub_6_2) node a_mask_sub_sub_6_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_6) node a_mask_sub_sub_7_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_7 = and(a_mask_sub_sub_size, a_mask_sub_sub_7_2) node a_mask_sub_sub_7_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_7) node a_mask_sub_size = bits(a_mask_sizeOH, 1, 1) node a_mask_sub_bit = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit = eq(a_mask_sub_bit, UInt<1>(0h0)) node a_mask_sub_0_2 = and(a_mask_sub_sub_0_2, a_mask_sub_nbit) node _a_mask_sub_acc_T = and(a_mask_sub_size, a_mask_sub_0_2) node a_mask_sub_0_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T) node a_mask_sub_1_2 = and(a_mask_sub_sub_0_2, a_mask_sub_bit) node _a_mask_sub_acc_T_1 = and(a_mask_sub_size, a_mask_sub_1_2) node a_mask_sub_1_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T_1) node a_mask_sub_2_2 = and(a_mask_sub_sub_1_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_2 = and(a_mask_sub_size, a_mask_sub_2_2) node a_mask_sub_2_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_2) node a_mask_sub_3_2 = and(a_mask_sub_sub_1_2, a_mask_sub_bit) node _a_mask_sub_acc_T_3 = and(a_mask_sub_size, a_mask_sub_3_2) node a_mask_sub_3_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_3) node a_mask_sub_4_2 = and(a_mask_sub_sub_2_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_4 = and(a_mask_sub_size, a_mask_sub_4_2) node a_mask_sub_4_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_4) node a_mask_sub_5_2 = and(a_mask_sub_sub_2_2, a_mask_sub_bit) node _a_mask_sub_acc_T_5 = and(a_mask_sub_size, a_mask_sub_5_2) node a_mask_sub_5_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_5) node a_mask_sub_6_2 = and(a_mask_sub_sub_3_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_6 = and(a_mask_sub_size, a_mask_sub_6_2) node a_mask_sub_6_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_6) node a_mask_sub_7_2 = and(a_mask_sub_sub_3_2, a_mask_sub_bit) node _a_mask_sub_acc_T_7 = and(a_mask_sub_size, a_mask_sub_7_2) node a_mask_sub_7_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_7) node a_mask_sub_8_2 = and(a_mask_sub_sub_4_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_8 = and(a_mask_sub_size, a_mask_sub_8_2) node a_mask_sub_8_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_8) node a_mask_sub_9_2 = and(a_mask_sub_sub_4_2, a_mask_sub_bit) node _a_mask_sub_acc_T_9 = and(a_mask_sub_size, a_mask_sub_9_2) node a_mask_sub_9_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_9) node a_mask_sub_10_2 = and(a_mask_sub_sub_5_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_10 = and(a_mask_sub_size, a_mask_sub_10_2) node a_mask_sub_10_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_10) node a_mask_sub_11_2 = and(a_mask_sub_sub_5_2, a_mask_sub_bit) node _a_mask_sub_acc_T_11 = and(a_mask_sub_size, a_mask_sub_11_2) node a_mask_sub_11_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_11) node a_mask_sub_12_2 = and(a_mask_sub_sub_6_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_12 = and(a_mask_sub_size, a_mask_sub_12_2) node a_mask_sub_12_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_12) node a_mask_sub_13_2 = and(a_mask_sub_sub_6_2, a_mask_sub_bit) node _a_mask_sub_acc_T_13 = and(a_mask_sub_size, a_mask_sub_13_2) node a_mask_sub_13_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_13) node a_mask_sub_14_2 = and(a_mask_sub_sub_7_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_14 = and(a_mask_sub_size, a_mask_sub_14_2) node a_mask_sub_14_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_14) node a_mask_sub_15_2 = and(a_mask_sub_sub_7_2, a_mask_sub_bit) node _a_mask_sub_acc_T_15 = and(a_mask_sub_size, a_mask_sub_15_2) node a_mask_sub_15_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_15) node a_mask_size = bits(a_mask_sizeOH, 0, 0) node a_mask_bit = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit = eq(a_mask_bit, UInt<1>(0h0)) node a_mask_eq = and(a_mask_sub_0_2, a_mask_nbit) node _a_mask_acc_T = and(a_mask_size, a_mask_eq) node a_mask_acc = or(a_mask_sub_0_1, _a_mask_acc_T) node a_mask_eq_1 = and(a_mask_sub_0_2, a_mask_bit) node _a_mask_acc_T_1 = and(a_mask_size, a_mask_eq_1) node a_mask_acc_1 = or(a_mask_sub_0_1, _a_mask_acc_T_1) node a_mask_eq_2 = and(a_mask_sub_1_2, a_mask_nbit) node _a_mask_acc_T_2 = and(a_mask_size, a_mask_eq_2) node a_mask_acc_2 = or(a_mask_sub_1_1, _a_mask_acc_T_2) node a_mask_eq_3 = and(a_mask_sub_1_2, a_mask_bit) node _a_mask_acc_T_3 = and(a_mask_size, a_mask_eq_3) node a_mask_acc_3 = or(a_mask_sub_1_1, _a_mask_acc_T_3) node a_mask_eq_4 = and(a_mask_sub_2_2, a_mask_nbit) node _a_mask_acc_T_4 = and(a_mask_size, a_mask_eq_4) node a_mask_acc_4 = or(a_mask_sub_2_1, _a_mask_acc_T_4) node a_mask_eq_5 = and(a_mask_sub_2_2, a_mask_bit) node _a_mask_acc_T_5 = and(a_mask_size, a_mask_eq_5) node a_mask_acc_5 = or(a_mask_sub_2_1, _a_mask_acc_T_5) node a_mask_eq_6 = and(a_mask_sub_3_2, a_mask_nbit) node _a_mask_acc_T_6 = and(a_mask_size, a_mask_eq_6) node a_mask_acc_6 = or(a_mask_sub_3_1, _a_mask_acc_T_6) node a_mask_eq_7 = and(a_mask_sub_3_2, a_mask_bit) node _a_mask_acc_T_7 = and(a_mask_size, a_mask_eq_7) node a_mask_acc_7 = or(a_mask_sub_3_1, _a_mask_acc_T_7) node a_mask_eq_8 = and(a_mask_sub_4_2, a_mask_nbit) node _a_mask_acc_T_8 = and(a_mask_size, a_mask_eq_8) node a_mask_acc_8 = or(a_mask_sub_4_1, _a_mask_acc_T_8) node a_mask_eq_9 = and(a_mask_sub_4_2, a_mask_bit) node _a_mask_acc_T_9 = and(a_mask_size, a_mask_eq_9) node a_mask_acc_9 = or(a_mask_sub_4_1, _a_mask_acc_T_9) node a_mask_eq_10 = and(a_mask_sub_5_2, a_mask_nbit) node _a_mask_acc_T_10 = and(a_mask_size, a_mask_eq_10) node a_mask_acc_10 = or(a_mask_sub_5_1, _a_mask_acc_T_10) node a_mask_eq_11 = and(a_mask_sub_5_2, a_mask_bit) node _a_mask_acc_T_11 = and(a_mask_size, a_mask_eq_11) node a_mask_acc_11 = or(a_mask_sub_5_1, _a_mask_acc_T_11) node a_mask_eq_12 = and(a_mask_sub_6_2, a_mask_nbit) node _a_mask_acc_T_12 = and(a_mask_size, a_mask_eq_12) node a_mask_acc_12 = or(a_mask_sub_6_1, _a_mask_acc_T_12) node a_mask_eq_13 = and(a_mask_sub_6_2, a_mask_bit) node _a_mask_acc_T_13 = and(a_mask_size, a_mask_eq_13) node a_mask_acc_13 = or(a_mask_sub_6_1, _a_mask_acc_T_13) node a_mask_eq_14 = and(a_mask_sub_7_2, a_mask_nbit) node _a_mask_acc_T_14 = and(a_mask_size, a_mask_eq_14) node a_mask_acc_14 = or(a_mask_sub_7_1, _a_mask_acc_T_14) node a_mask_eq_15 = and(a_mask_sub_7_2, a_mask_bit) node _a_mask_acc_T_15 = and(a_mask_size, a_mask_eq_15) node a_mask_acc_15 = or(a_mask_sub_7_1, _a_mask_acc_T_15) node a_mask_eq_16 = and(a_mask_sub_8_2, a_mask_nbit) node _a_mask_acc_T_16 = and(a_mask_size, a_mask_eq_16) node a_mask_acc_16 = or(a_mask_sub_8_1, _a_mask_acc_T_16) node a_mask_eq_17 = and(a_mask_sub_8_2, a_mask_bit) node _a_mask_acc_T_17 = and(a_mask_size, a_mask_eq_17) node a_mask_acc_17 = or(a_mask_sub_8_1, _a_mask_acc_T_17) node a_mask_eq_18 = and(a_mask_sub_9_2, a_mask_nbit) node _a_mask_acc_T_18 = and(a_mask_size, a_mask_eq_18) node a_mask_acc_18 = or(a_mask_sub_9_1, _a_mask_acc_T_18) node a_mask_eq_19 = and(a_mask_sub_9_2, a_mask_bit) node _a_mask_acc_T_19 = and(a_mask_size, a_mask_eq_19) node a_mask_acc_19 = or(a_mask_sub_9_1, _a_mask_acc_T_19) node a_mask_eq_20 = and(a_mask_sub_10_2, a_mask_nbit) node _a_mask_acc_T_20 = and(a_mask_size, a_mask_eq_20) node a_mask_acc_20 = or(a_mask_sub_10_1, _a_mask_acc_T_20) node a_mask_eq_21 = and(a_mask_sub_10_2, a_mask_bit) node _a_mask_acc_T_21 = and(a_mask_size, a_mask_eq_21) node a_mask_acc_21 = or(a_mask_sub_10_1, _a_mask_acc_T_21) node a_mask_eq_22 = and(a_mask_sub_11_2, a_mask_nbit) node _a_mask_acc_T_22 = and(a_mask_size, a_mask_eq_22) node a_mask_acc_22 = or(a_mask_sub_11_1, _a_mask_acc_T_22) node a_mask_eq_23 = and(a_mask_sub_11_2, a_mask_bit) node _a_mask_acc_T_23 = and(a_mask_size, a_mask_eq_23) node a_mask_acc_23 = or(a_mask_sub_11_1, _a_mask_acc_T_23) node a_mask_eq_24 = and(a_mask_sub_12_2, a_mask_nbit) node _a_mask_acc_T_24 = and(a_mask_size, a_mask_eq_24) node a_mask_acc_24 = or(a_mask_sub_12_1, _a_mask_acc_T_24) node a_mask_eq_25 = and(a_mask_sub_12_2, a_mask_bit) node _a_mask_acc_T_25 = and(a_mask_size, a_mask_eq_25) node a_mask_acc_25 = or(a_mask_sub_12_1, _a_mask_acc_T_25) node a_mask_eq_26 = and(a_mask_sub_13_2, a_mask_nbit) node _a_mask_acc_T_26 = and(a_mask_size, a_mask_eq_26) node a_mask_acc_26 = or(a_mask_sub_13_1, _a_mask_acc_T_26) node a_mask_eq_27 = and(a_mask_sub_13_2, a_mask_bit) node _a_mask_acc_T_27 = and(a_mask_size, a_mask_eq_27) node a_mask_acc_27 = or(a_mask_sub_13_1, _a_mask_acc_T_27) node a_mask_eq_28 = and(a_mask_sub_14_2, a_mask_nbit) node _a_mask_acc_T_28 = and(a_mask_size, a_mask_eq_28) node a_mask_acc_28 = or(a_mask_sub_14_1, _a_mask_acc_T_28) node a_mask_eq_29 = and(a_mask_sub_14_2, a_mask_bit) node _a_mask_acc_T_29 = and(a_mask_size, a_mask_eq_29) node a_mask_acc_29 = or(a_mask_sub_14_1, _a_mask_acc_T_29) node a_mask_eq_30 = and(a_mask_sub_15_2, a_mask_nbit) node _a_mask_acc_T_30 = and(a_mask_size, a_mask_eq_30) node a_mask_acc_30 = or(a_mask_sub_15_1, _a_mask_acc_T_30) node a_mask_eq_31 = and(a_mask_sub_15_2, a_mask_bit) node _a_mask_acc_T_31 = and(a_mask_size, a_mask_eq_31) node a_mask_acc_31 = or(a_mask_sub_15_1, _a_mask_acc_T_31) node a_mask_lo_lo_lo_lo = cat(a_mask_acc_1, a_mask_acc) node a_mask_lo_lo_lo_hi = cat(a_mask_acc_3, a_mask_acc_2) node a_mask_lo_lo_lo = cat(a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo) node a_mask_lo_lo_hi_lo = cat(a_mask_acc_5, a_mask_acc_4) node a_mask_lo_lo_hi_hi = cat(a_mask_acc_7, a_mask_acc_6) node a_mask_lo_lo_hi = cat(a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo) node a_mask_lo_lo = cat(a_mask_lo_lo_hi, a_mask_lo_lo_lo) node a_mask_lo_hi_lo_lo = cat(a_mask_acc_9, a_mask_acc_8) node a_mask_lo_hi_lo_hi = cat(a_mask_acc_11, a_mask_acc_10) node a_mask_lo_hi_lo = cat(a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo) node a_mask_lo_hi_hi_lo = cat(a_mask_acc_13, a_mask_acc_12) node a_mask_lo_hi_hi_hi = cat(a_mask_acc_15, a_mask_acc_14) node a_mask_lo_hi_hi = cat(a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo) node a_mask_lo_hi = cat(a_mask_lo_hi_hi, a_mask_lo_hi_lo) node a_mask_lo = cat(a_mask_lo_hi, a_mask_lo_lo) node a_mask_hi_lo_lo_lo = cat(a_mask_acc_17, a_mask_acc_16) node a_mask_hi_lo_lo_hi = cat(a_mask_acc_19, a_mask_acc_18) node a_mask_hi_lo_lo = cat(a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo) node a_mask_hi_lo_hi_lo = cat(a_mask_acc_21, a_mask_acc_20) node a_mask_hi_lo_hi_hi = cat(a_mask_acc_23, a_mask_acc_22) node a_mask_hi_lo_hi = cat(a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo) node a_mask_hi_lo = cat(a_mask_hi_lo_hi, a_mask_hi_lo_lo) node a_mask_hi_hi_lo_lo = cat(a_mask_acc_25, a_mask_acc_24) node a_mask_hi_hi_lo_hi = cat(a_mask_acc_27, a_mask_acc_26) node a_mask_hi_hi_lo = cat(a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo) node a_mask_hi_hi_hi_lo = cat(a_mask_acc_29, a_mask_acc_28) node a_mask_hi_hi_hi_hi = cat(a_mask_acc_31, a_mask_acc_30) node a_mask_hi_hi_hi = cat(a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo) node a_mask_hi_hi = cat(a_mask_hi_hi_hi, a_mask_hi_hi_lo) node a_mask_hi = cat(a_mask_hi_hi, a_mask_hi_lo) node _a_mask_T = cat(a_mask_hi, a_mask_lo) connect bundle.mask, _a_mask_T invalidate bundle.data connect bundle.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle.data connect request_latency_injection_q.io.enq.bits.mask, bundle.mask connect request_latency_injection_q.io.enq.bits.address, bundle.address connect request_latency_injection_q.io.enq.bits.source, bundle.source connect request_latency_injection_q.io.enq.bits.size, bundle.size connect request_latency_injection_q.io.enq.bits.param, bundle.param connect request_latency_injection_q.io.enq.bits.opcode, bundle.opcode else : node _T_28 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_28 : node _T_29 = bits(request_input.bits.addr, 4, 0) node _T_30 = shl(_T_29, 3) node _T_31 = dshl(request_input.bits.data, _T_30) node _legal_T_63 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_64 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_65 = and(_legal_T_63, _legal_T_64) node _legal_T_66 = or(UInt<1>(0h0), _legal_T_65) node _legal_T_67 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_68 = cvt(_legal_T_67) node _legal_T_69 = and(_legal_T_68, asSInt(UInt<33>(0h9a113000))) node _legal_T_70 = asSInt(_legal_T_69) node _legal_T_71 = eq(_legal_T_70, asSInt(UInt<1>(0h0))) node _legal_T_72 = and(_legal_T_66, _legal_T_71) node _legal_T_73 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_74 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_75 = and(_legal_T_73, _legal_T_74) node _legal_T_76 = or(UInt<1>(0h0), _legal_T_75) node _legal_T_77 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_78 = cvt(_legal_T_77) node _legal_T_79 = and(_legal_T_78, asSInt(UInt<33>(0h9a112000))) node _legal_T_80 = asSInt(_legal_T_79) node _legal_T_81 = eq(_legal_T_80, asSInt(UInt<1>(0h0))) node _legal_T_82 = xor(tlb.io.resp.paddr, UInt<21>(0h100000)) node _legal_T_83 = cvt(_legal_T_82) node _legal_T_84 = and(_legal_T_83, asSInt(UInt<33>(0h9a103000))) node _legal_T_85 = asSInt(_legal_T_84) node _legal_T_86 = eq(_legal_T_85, asSInt(UInt<1>(0h0))) node _legal_T_87 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_88 = cvt(_legal_T_87) node _legal_T_89 = and(_legal_T_88, asSInt(UInt<33>(0h9a110000))) node _legal_T_90 = asSInt(_legal_T_89) node _legal_T_91 = eq(_legal_T_90, asSInt(UInt<1>(0h0))) node _legal_T_92 = xor(tlb.io.resp.paddr, UInt<26>(0h2010000)) node _legal_T_93 = cvt(_legal_T_92) node _legal_T_94 = and(_legal_T_93, asSInt(UInt<33>(0h9a113000))) node _legal_T_95 = asSInt(_legal_T_94) node _legal_T_96 = eq(_legal_T_95, asSInt(UInt<1>(0h0))) node _legal_T_97 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_98 = cvt(_legal_T_97) node _legal_T_99 = and(_legal_T_98, asSInt(UInt<33>(0h98000000))) node _legal_T_100 = asSInt(_legal_T_99) node _legal_T_101 = eq(_legal_T_100, asSInt(UInt<1>(0h0))) node _legal_T_102 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_103 = cvt(_legal_T_102) node _legal_T_104 = and(_legal_T_103, asSInt(UInt<33>(0h9a110000))) node _legal_T_105 = asSInt(_legal_T_104) node _legal_T_106 = eq(_legal_T_105, asSInt(UInt<1>(0h0))) node _legal_T_107 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_108 = cvt(_legal_T_107) node _legal_T_109 = and(_legal_T_108, asSInt(UInt<33>(0h9a113000))) node _legal_T_110 = asSInt(_legal_T_109) node _legal_T_111 = eq(_legal_T_110, asSInt(UInt<1>(0h0))) node _legal_T_112 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_113 = cvt(_legal_T_112) node _legal_T_114 = and(_legal_T_113, asSInt(UInt<33>(0h90000000))) node _legal_T_115 = asSInt(_legal_T_114) node _legal_T_116 = eq(_legal_T_115, asSInt(UInt<1>(0h0))) node _legal_T_117 = or(_legal_T_81, _legal_T_86) node _legal_T_118 = or(_legal_T_117, _legal_T_91) node _legal_T_119 = or(_legal_T_118, _legal_T_96) node _legal_T_120 = or(_legal_T_119, _legal_T_101) node _legal_T_121 = or(_legal_T_120, _legal_T_106) node _legal_T_122 = or(_legal_T_121, _legal_T_111) node _legal_T_123 = or(_legal_T_122, _legal_T_116) node _legal_T_124 = and(_legal_T_76, _legal_T_123) node _legal_T_125 = or(UInt<1>(0h0), UInt<1>(0h0)) node _legal_T_126 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_127 = cvt(_legal_T_126) node _legal_T_128 = and(_legal_T_127, asSInt(UInt<33>(0h9a110000))) node _legal_T_129 = asSInt(_legal_T_128) node _legal_T_130 = eq(_legal_T_129, asSInt(UInt<1>(0h0))) node _legal_T_131 = and(_legal_T_125, _legal_T_130) node _legal_T_132 = or(UInt<1>(0h0), _legal_T_72) node _legal_T_133 = or(_legal_T_132, _legal_T_124) node legal_1 = or(_legal_T_133, _legal_T_131) wire bundle_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle_1.opcode, UInt<1>(0h0) connect bundle_1.param, UInt<1>(0h0) connect bundle_1.size, request_input.bits.size connect bundle_1.source, tags_for_issue_Q.io.deq.bits connect bundle_1.address, tlb.io.resp.paddr node _a_mask_sizeOH_T_3 = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T_1 = pad(_a_mask_sizeOH_T_3, 3) node a_mask_sizeOH_shiftAmount_1 = bits(_a_mask_sizeOH_shiftAmount_T_1, 2, 0) node _a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount_1) node _a_mask_sizeOH_T_5 = bits(_a_mask_sizeOH_T_4, 4, 0) node a_mask_sizeOH_1 = or(_a_mask_sizeOH_T_5, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 4, 4) node a_mask_sub_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_3) node a_mask_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 3, 3) node a_mask_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_4 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_4) node a_mask_sub_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_5 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_5) node a_mask_sub_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_6 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_2_2_1) node a_mask_sub_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_6) node a_mask_sub_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_7 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_3_2_1) node a_mask_sub_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_7) node a_mask_sub_sub_size_1 = bits(a_mask_sizeOH_1, 2, 2) node a_mask_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit_1 = eq(a_mask_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_8 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_0_2_1) node a_mask_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_8) node a_mask_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_9 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_1_2_1) node a_mask_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_9) node a_mask_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_10 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_2_2_1) node a_mask_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_10) node a_mask_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_11 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_3_2_1) node a_mask_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_11) node a_mask_sub_sub_4_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_12 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_4_2_1) node a_mask_sub_sub_4_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_12) node a_mask_sub_sub_5_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_13 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_5_2_1) node a_mask_sub_sub_5_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_13) node a_mask_sub_sub_6_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_14 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_6_2_1) node a_mask_sub_sub_6_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_14) node a_mask_sub_sub_7_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_15 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_7_2_1) node a_mask_sub_sub_7_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_15) node a_mask_sub_size_1 = bits(a_mask_sizeOH_1, 1, 1) node a_mask_sub_bit_1 = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit_1 = eq(a_mask_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_0_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_16 = and(a_mask_sub_size_1, a_mask_sub_0_2_1) node a_mask_sub_0_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_16) node a_mask_sub_1_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_17 = and(a_mask_sub_size_1, a_mask_sub_1_2_1) node a_mask_sub_1_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_17) node a_mask_sub_2_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_18 = and(a_mask_sub_size_1, a_mask_sub_2_2_1) node a_mask_sub_2_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_18) node a_mask_sub_3_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_19 = and(a_mask_sub_size_1, a_mask_sub_3_2_1) node a_mask_sub_3_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_19) node a_mask_sub_4_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_20 = and(a_mask_sub_size_1, a_mask_sub_4_2_1) node a_mask_sub_4_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_20) node a_mask_sub_5_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_21 = and(a_mask_sub_size_1, a_mask_sub_5_2_1) node a_mask_sub_5_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_21) node a_mask_sub_6_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_22 = and(a_mask_sub_size_1, a_mask_sub_6_2_1) node a_mask_sub_6_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_22) node a_mask_sub_7_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_23 = and(a_mask_sub_size_1, a_mask_sub_7_2_1) node a_mask_sub_7_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_23) node a_mask_sub_8_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_24 = and(a_mask_sub_size_1, a_mask_sub_8_2_1) node a_mask_sub_8_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_24) node a_mask_sub_9_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_25 = and(a_mask_sub_size_1, a_mask_sub_9_2_1) node a_mask_sub_9_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_25) node a_mask_sub_10_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_26 = and(a_mask_sub_size_1, a_mask_sub_10_2_1) node a_mask_sub_10_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_26) node a_mask_sub_11_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_27 = and(a_mask_sub_size_1, a_mask_sub_11_2_1) node a_mask_sub_11_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_27) node a_mask_sub_12_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_28 = and(a_mask_sub_size_1, a_mask_sub_12_2_1) node a_mask_sub_12_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_28) node a_mask_sub_13_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_29 = and(a_mask_sub_size_1, a_mask_sub_13_2_1) node a_mask_sub_13_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_29) node a_mask_sub_14_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_30 = and(a_mask_sub_size_1, a_mask_sub_14_2_1) node a_mask_sub_14_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_30) node a_mask_sub_15_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_31 = and(a_mask_sub_size_1, a_mask_sub_15_2_1) node a_mask_sub_15_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_31) node a_mask_size_1 = bits(a_mask_sizeOH_1, 0, 0) node a_mask_bit_1 = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit_1 = eq(a_mask_bit_1, UInt<1>(0h0)) node a_mask_eq_32 = and(a_mask_sub_0_2_1, a_mask_nbit_1) node _a_mask_acc_T_32 = and(a_mask_size_1, a_mask_eq_32) node a_mask_acc_32 = or(a_mask_sub_0_1_1, _a_mask_acc_T_32) node a_mask_eq_33 = and(a_mask_sub_0_2_1, a_mask_bit_1) node _a_mask_acc_T_33 = and(a_mask_size_1, a_mask_eq_33) node a_mask_acc_33 = or(a_mask_sub_0_1_1, _a_mask_acc_T_33) node a_mask_eq_34 = and(a_mask_sub_1_2_1, a_mask_nbit_1) node _a_mask_acc_T_34 = and(a_mask_size_1, a_mask_eq_34) node a_mask_acc_34 = or(a_mask_sub_1_1_1, _a_mask_acc_T_34) node a_mask_eq_35 = and(a_mask_sub_1_2_1, a_mask_bit_1) node _a_mask_acc_T_35 = and(a_mask_size_1, a_mask_eq_35) node a_mask_acc_35 = or(a_mask_sub_1_1_1, _a_mask_acc_T_35) node a_mask_eq_36 = and(a_mask_sub_2_2_1, a_mask_nbit_1) node _a_mask_acc_T_36 = and(a_mask_size_1, a_mask_eq_36) node a_mask_acc_36 = or(a_mask_sub_2_1_1, _a_mask_acc_T_36) node a_mask_eq_37 = and(a_mask_sub_2_2_1, a_mask_bit_1) node _a_mask_acc_T_37 = and(a_mask_size_1, a_mask_eq_37) node a_mask_acc_37 = or(a_mask_sub_2_1_1, _a_mask_acc_T_37) node a_mask_eq_38 = and(a_mask_sub_3_2_1, a_mask_nbit_1) node _a_mask_acc_T_38 = and(a_mask_size_1, a_mask_eq_38) node a_mask_acc_38 = or(a_mask_sub_3_1_1, _a_mask_acc_T_38) node a_mask_eq_39 = and(a_mask_sub_3_2_1, a_mask_bit_1) node _a_mask_acc_T_39 = and(a_mask_size_1, a_mask_eq_39) node a_mask_acc_39 = or(a_mask_sub_3_1_1, _a_mask_acc_T_39) node a_mask_eq_40 = and(a_mask_sub_4_2_1, a_mask_nbit_1) node _a_mask_acc_T_40 = and(a_mask_size_1, a_mask_eq_40) node a_mask_acc_40 = or(a_mask_sub_4_1_1, _a_mask_acc_T_40) node a_mask_eq_41 = and(a_mask_sub_4_2_1, a_mask_bit_1) node _a_mask_acc_T_41 = and(a_mask_size_1, a_mask_eq_41) node a_mask_acc_41 = or(a_mask_sub_4_1_1, _a_mask_acc_T_41) node a_mask_eq_42 = and(a_mask_sub_5_2_1, a_mask_nbit_1) node _a_mask_acc_T_42 = and(a_mask_size_1, a_mask_eq_42) node a_mask_acc_42 = or(a_mask_sub_5_1_1, _a_mask_acc_T_42) node a_mask_eq_43 = and(a_mask_sub_5_2_1, a_mask_bit_1) node _a_mask_acc_T_43 = and(a_mask_size_1, a_mask_eq_43) node a_mask_acc_43 = or(a_mask_sub_5_1_1, _a_mask_acc_T_43) node a_mask_eq_44 = and(a_mask_sub_6_2_1, a_mask_nbit_1) node _a_mask_acc_T_44 = and(a_mask_size_1, a_mask_eq_44) node a_mask_acc_44 = or(a_mask_sub_6_1_1, _a_mask_acc_T_44) node a_mask_eq_45 = and(a_mask_sub_6_2_1, a_mask_bit_1) node _a_mask_acc_T_45 = and(a_mask_size_1, a_mask_eq_45) node a_mask_acc_45 = or(a_mask_sub_6_1_1, _a_mask_acc_T_45) node a_mask_eq_46 = and(a_mask_sub_7_2_1, a_mask_nbit_1) node _a_mask_acc_T_46 = and(a_mask_size_1, a_mask_eq_46) node a_mask_acc_46 = or(a_mask_sub_7_1_1, _a_mask_acc_T_46) node a_mask_eq_47 = and(a_mask_sub_7_2_1, a_mask_bit_1) node _a_mask_acc_T_47 = and(a_mask_size_1, a_mask_eq_47) node a_mask_acc_47 = or(a_mask_sub_7_1_1, _a_mask_acc_T_47) node a_mask_eq_48 = and(a_mask_sub_8_2_1, a_mask_nbit_1) node _a_mask_acc_T_48 = and(a_mask_size_1, a_mask_eq_48) node a_mask_acc_48 = or(a_mask_sub_8_1_1, _a_mask_acc_T_48) node a_mask_eq_49 = and(a_mask_sub_8_2_1, a_mask_bit_1) node _a_mask_acc_T_49 = and(a_mask_size_1, a_mask_eq_49) node a_mask_acc_49 = or(a_mask_sub_8_1_1, _a_mask_acc_T_49) node a_mask_eq_50 = and(a_mask_sub_9_2_1, a_mask_nbit_1) node _a_mask_acc_T_50 = and(a_mask_size_1, a_mask_eq_50) node a_mask_acc_50 = or(a_mask_sub_9_1_1, _a_mask_acc_T_50) node a_mask_eq_51 = and(a_mask_sub_9_2_1, a_mask_bit_1) node _a_mask_acc_T_51 = and(a_mask_size_1, a_mask_eq_51) node a_mask_acc_51 = or(a_mask_sub_9_1_1, _a_mask_acc_T_51) node a_mask_eq_52 = and(a_mask_sub_10_2_1, a_mask_nbit_1) node _a_mask_acc_T_52 = and(a_mask_size_1, a_mask_eq_52) node a_mask_acc_52 = or(a_mask_sub_10_1_1, _a_mask_acc_T_52) node a_mask_eq_53 = and(a_mask_sub_10_2_1, a_mask_bit_1) node _a_mask_acc_T_53 = and(a_mask_size_1, a_mask_eq_53) node a_mask_acc_53 = or(a_mask_sub_10_1_1, _a_mask_acc_T_53) node a_mask_eq_54 = and(a_mask_sub_11_2_1, a_mask_nbit_1) node _a_mask_acc_T_54 = and(a_mask_size_1, a_mask_eq_54) node a_mask_acc_54 = or(a_mask_sub_11_1_1, _a_mask_acc_T_54) node a_mask_eq_55 = and(a_mask_sub_11_2_1, a_mask_bit_1) node _a_mask_acc_T_55 = and(a_mask_size_1, a_mask_eq_55) node a_mask_acc_55 = or(a_mask_sub_11_1_1, _a_mask_acc_T_55) node a_mask_eq_56 = and(a_mask_sub_12_2_1, a_mask_nbit_1) node _a_mask_acc_T_56 = and(a_mask_size_1, a_mask_eq_56) node a_mask_acc_56 = or(a_mask_sub_12_1_1, _a_mask_acc_T_56) node a_mask_eq_57 = and(a_mask_sub_12_2_1, a_mask_bit_1) node _a_mask_acc_T_57 = and(a_mask_size_1, a_mask_eq_57) node a_mask_acc_57 = or(a_mask_sub_12_1_1, _a_mask_acc_T_57) node a_mask_eq_58 = and(a_mask_sub_13_2_1, a_mask_nbit_1) node _a_mask_acc_T_58 = and(a_mask_size_1, a_mask_eq_58) node a_mask_acc_58 = or(a_mask_sub_13_1_1, _a_mask_acc_T_58) node a_mask_eq_59 = and(a_mask_sub_13_2_1, a_mask_bit_1) node _a_mask_acc_T_59 = and(a_mask_size_1, a_mask_eq_59) node a_mask_acc_59 = or(a_mask_sub_13_1_1, _a_mask_acc_T_59) node a_mask_eq_60 = and(a_mask_sub_14_2_1, a_mask_nbit_1) node _a_mask_acc_T_60 = and(a_mask_size_1, a_mask_eq_60) node a_mask_acc_60 = or(a_mask_sub_14_1_1, _a_mask_acc_T_60) node a_mask_eq_61 = and(a_mask_sub_14_2_1, a_mask_bit_1) node _a_mask_acc_T_61 = and(a_mask_size_1, a_mask_eq_61) node a_mask_acc_61 = or(a_mask_sub_14_1_1, _a_mask_acc_T_61) node a_mask_eq_62 = and(a_mask_sub_15_2_1, a_mask_nbit_1) node _a_mask_acc_T_62 = and(a_mask_size_1, a_mask_eq_62) node a_mask_acc_62 = or(a_mask_sub_15_1_1, _a_mask_acc_T_62) node a_mask_eq_63 = and(a_mask_sub_15_2_1, a_mask_bit_1) node _a_mask_acc_T_63 = and(a_mask_size_1, a_mask_eq_63) node a_mask_acc_63 = or(a_mask_sub_15_1_1, _a_mask_acc_T_63) node a_mask_lo_lo_lo_lo_1 = cat(a_mask_acc_33, a_mask_acc_32) node a_mask_lo_lo_lo_hi_1 = cat(a_mask_acc_35, a_mask_acc_34) node a_mask_lo_lo_lo_1 = cat(a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1) node a_mask_lo_lo_hi_lo_1 = cat(a_mask_acc_37, a_mask_acc_36) node a_mask_lo_lo_hi_hi_1 = cat(a_mask_acc_39, a_mask_acc_38) node a_mask_lo_lo_hi_1 = cat(a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1) node a_mask_lo_lo_1 = cat(a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1) node a_mask_lo_hi_lo_lo_1 = cat(a_mask_acc_41, a_mask_acc_40) node a_mask_lo_hi_lo_hi_1 = cat(a_mask_acc_43, a_mask_acc_42) node a_mask_lo_hi_lo_1 = cat(a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1) node a_mask_lo_hi_hi_lo_1 = cat(a_mask_acc_45, a_mask_acc_44) node a_mask_lo_hi_hi_hi_1 = cat(a_mask_acc_47, a_mask_acc_46) node a_mask_lo_hi_hi_1 = cat(a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1) node a_mask_lo_hi_1 = cat(a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1) node a_mask_lo_1 = cat(a_mask_lo_hi_1, a_mask_lo_lo_1) node a_mask_hi_lo_lo_lo_1 = cat(a_mask_acc_49, a_mask_acc_48) node a_mask_hi_lo_lo_hi_1 = cat(a_mask_acc_51, a_mask_acc_50) node a_mask_hi_lo_lo_1 = cat(a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1) node a_mask_hi_lo_hi_lo_1 = cat(a_mask_acc_53, a_mask_acc_52) node a_mask_hi_lo_hi_hi_1 = cat(a_mask_acc_55, a_mask_acc_54) node a_mask_hi_lo_hi_1 = cat(a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1) node a_mask_hi_lo_1 = cat(a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1) node a_mask_hi_hi_lo_lo_1 = cat(a_mask_acc_57, a_mask_acc_56) node a_mask_hi_hi_lo_hi_1 = cat(a_mask_acc_59, a_mask_acc_58) node a_mask_hi_hi_lo_1 = cat(a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1) node a_mask_hi_hi_hi_lo_1 = cat(a_mask_acc_61, a_mask_acc_60) node a_mask_hi_hi_hi_hi_1 = cat(a_mask_acc_63, a_mask_acc_62) node a_mask_hi_hi_hi_1 = cat(a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1) node a_mask_hi_hi_1 = cat(a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1) node a_mask_hi_1 = cat(a_mask_hi_hi_1, a_mask_hi_lo_1) node _a_mask_T_1 = cat(a_mask_hi_1, a_mask_lo_1) connect bundle_1.mask, _a_mask_T_1 connect bundle_1.data, _T_31 connect bundle_1.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle_1.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle_1.data connect request_latency_injection_q.io.enq.bits.mask, bundle_1.mask connect request_latency_injection_q.io.enq.bits.address, bundle_1.address connect request_latency_injection_q.io.enq.bits.source, bundle_1.source connect request_latency_injection_q.io.enq.bits.size, bundle_1.size connect request_latency_injection_q.io.enq.bits.param, bundle_1.param connect request_latency_injection_q.io.enq.bits.opcode, bundle_1.opcode else : when request_input.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_10 node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] ERR") : printf_11 node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: ERR\n at L2MemHelperLatencyInjection.scala:178 assert(false.B, \"ERR\")\n") : printf_12 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_2 inst Queue4_L2RespInternal of Queue4_L2RespInternal_206 connect Queue4_L2RespInternal.clock, clock connect Queue4_L2RespInternal.reset, reset inst Queue4_L2RespInternal_1 of Queue4_L2RespInternal_207 connect Queue4_L2RespInternal_1.clock, clock connect Queue4_L2RespInternal_1.reset, reset inst Queue4_L2RespInternal_2 of Queue4_L2RespInternal_208 connect Queue4_L2RespInternal_2.clock, clock connect Queue4_L2RespInternal_2.reset, reset inst Queue4_L2RespInternal_3 of Queue4_L2RespInternal_209 connect Queue4_L2RespInternal_3.clock, clock connect Queue4_L2RespInternal_3.reset, reset node _current_request_tag_has_response_space_T = eq(UInt<1>(0h0), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _current_request_tag_has_response_space_T) node _current_request_tag_has_response_space_T_2 = eq(UInt<1>(0h1), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _current_request_tag_has_response_space_T_2) node _current_request_tag_has_response_space_T_4 = eq(UInt<2>(0h2), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _current_request_tag_has_response_space_T_4) node _current_request_tag_has_response_space_T_6 = eq(UInt<2>(0h3), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _current_request_tag_has_response_space_T_6) node _current_request_tag_has_response_space_T_8 = or(_current_request_tag_has_response_space_T_1, _current_request_tag_has_response_space_T_3) node _current_request_tag_has_response_space_T_9 = or(_current_request_tag_has_response_space_T_8, _current_request_tag_has_response_space_T_5) node current_request_tag_has_response_space = or(_current_request_tag_has_response_space_T_9, _current_request_tag_has_response_space_T_7) node _outstanding_req_addr_io_enq_bits_addrindex_T = and(request_input.bits.addr, UInt<5>(0h1f)) connect outstanding_req_addr.io.enq.bits.addrindex, _outstanding_req_addr_io_enq_bits_addrindex_T connect outstanding_req_addr.io.enq.bits.tag, tags_for_issue_Q.io.deq.bits node _request_latency_injection_q_io_enq_valid_T = and(request_input.valid, tlb_ready) node _request_latency_injection_q_io_enq_valid_T_1 = and(_request_latency_injection_q_io_enq_valid_T, outstanding_req_addr.io.enq.ready) node _request_latency_injection_q_io_enq_valid_T_2 = and(_request_latency_injection_q_io_enq_valid_T_1, free_outstanding_op_slots) node _request_latency_injection_q_io_enq_valid_T_3 = and(_request_latency_injection_q_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _request_latency_injection_q_io_enq_valid_T_4 = and(_request_latency_injection_q_io_enq_valid_T_3, current_request_tag_has_response_space) connect request_latency_injection_q.io.enq.valid, _request_latency_injection_q_io_enq_valid_T_4 node _request_input_ready_T = and(request_latency_injection_q.io.enq.ready, tlb_ready) node _request_input_ready_T_1 = and(_request_input_ready_T, outstanding_req_addr.io.enq.ready) node _request_input_ready_T_2 = and(_request_input_ready_T_1, free_outstanding_op_slots) node _request_input_ready_T_3 = and(_request_input_ready_T_2, tags_for_issue_Q.io.deq.valid) node _request_input_ready_T_4 = and(_request_input_ready_T_3, current_request_tag_has_response_space) connect request_input.ready, _request_input_ready_T_4 node _outstanding_req_addr_io_enq_valid_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _outstanding_req_addr_io_enq_valid_T_1 = and(_outstanding_req_addr_io_enq_valid_T, tlb_ready) node _outstanding_req_addr_io_enq_valid_T_2 = and(_outstanding_req_addr_io_enq_valid_T_1, free_outstanding_op_slots) node _outstanding_req_addr_io_enq_valid_T_3 = and(_outstanding_req_addr_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _outstanding_req_addr_io_enq_valid_T_4 = and(_outstanding_req_addr_io_enq_valid_T_3, current_request_tag_has_response_space) connect outstanding_req_addr.io.enq.valid, _outstanding_req_addr_io_enq_valid_T_4 node _tags_for_issue_Q_io_deq_ready_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_1 = and(_tags_for_issue_Q_io_deq_ready_T, tlb_ready) node _tags_for_issue_Q_io_deq_ready_T_2 = and(_tags_for_issue_Q_io_deq_ready_T_1, outstanding_req_addr.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_3 = and(_tags_for_issue_Q_io_deq_ready_T_2, free_outstanding_op_slots) node _tags_for_issue_Q_io_deq_ready_T_4 = and(_tags_for_issue_Q_io_deq_ready_T_3, current_request_tag_has_response_space) connect tags_for_issue_Q.io.deq.ready, _tags_for_issue_Q_io_deq_ready_T_4 connect masterNodeOut.a.bits, request_latency_injection_q.io.deq.bits connect masterNodeOut.a.valid, request_latency_injection_q.io.deq.valid connect request_latency_injection_q.io.deq.ready, masterNodeOut.a.ready node _T_39 = and(masterNodeOut.a.ready, masterNodeOut.a.valid) when _T_39 : node _T_40 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_40 : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_13 node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_14 node _T_45 = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _T_46 = and(_T_45, tlb_ready) node _T_47 = and(_T_46, outstanding_req_addr.io.enq.ready) node _T_48 = and(_T_47, free_outstanding_op_slots) node _T_49 = and(_T_48, tags_for_issue_Q.io.deq.valid) node _T_50 = and(_T_49, current_request_tag_has_response_space) when _T_50 : node _T_51 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_51 : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _printf_T = asUInt(reset) node _printf_T_1 = eq(_printf_T, UInt<1>(0h0)) when _printf_T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_15 node _T_52 = asUInt(reset) node _T_53 = eq(_T_52, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "") : printf_16 node _printf_T_2 = asUInt(reset) node _printf_T_3 = eq(_printf_T_2, UInt<1>(0h0)) when _printf_T_3 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: req(write) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, data: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, request_input.bits.data, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_17 node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "") : printf_18 node _T_56 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_57 = lt(UInt<1>(0h0), _T_56) when _T_57 : node _T_58 = add(request_input.bits.addr, UInt<1>(0h0)) node _T_59 = tail(_T_58, 1) node _T_60 = dshr(request_input.bits.data, UInt<1>(0h0)) node _T_61 = bits(_T_60, 7, 0) regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_19 node _T_64 = asUInt(reset) node _T_65 = eq(_T_64, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_59, _T_61) : printf_20 node _T_66 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_67 = lt(UInt<1>(0h1), _T_66) when _T_67 : node _T_68 = add(request_input.bits.addr, UInt<1>(0h1)) node _T_69 = tail(_T_68, 1) node _T_70 = dshr(request_input.bits.data, UInt<4>(0h8)) node _T_71 = bits(_T_70, 7, 0) regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_21 node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_69, _T_71) : printf_22 node _T_76 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_77 = lt(UInt<2>(0h2), _T_76) when _T_77 : node _T_78 = add(request_input.bits.addr, UInt<2>(0h2)) node _T_79 = tail(_T_78, 1) node _T_80 = dshr(request_input.bits.data, UInt<5>(0h10)) node _T_81 = bits(_T_80, 7, 0) regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_23 node _T_84 = asUInt(reset) node _T_85 = eq(_T_84, UInt<1>(0h0)) when _T_85 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_79, _T_81) : printf_24 node _T_86 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_87 = lt(UInt<2>(0h3), _T_86) when _T_87 : node _T_88 = add(request_input.bits.addr, UInt<2>(0h3)) node _T_89 = tail(_T_88, 1) node _T_90 = dshr(request_input.bits.data, UInt<5>(0h18)) node _T_91 = bits(_T_90, 7, 0) regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_92 = asUInt(reset) node _T_93 = eq(_T_92, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_25 node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_89, _T_91) : printf_26 node _T_96 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_97 = lt(UInt<3>(0h4), _T_96) when _T_97 : node _T_98 = add(request_input.bits.addr, UInt<3>(0h4)) node _T_99 = tail(_T_98, 1) node _T_100 = dshr(request_input.bits.data, UInt<6>(0h20)) node _T_101 = bits(_T_100, 7, 0) regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_102 = asUInt(reset) node _T_103 = eq(_T_102, UInt<1>(0h0)) when _T_103 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_27 node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_99, _T_101) : printf_28 node _T_106 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_107 = lt(UInt<3>(0h5), _T_106) when _T_107 : node _T_108 = add(request_input.bits.addr, UInt<3>(0h5)) node _T_109 = tail(_T_108, 1) node _T_110 = dshr(request_input.bits.data, UInt<6>(0h28)) node _T_111 = bits(_T_110, 7, 0) regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_112 = asUInt(reset) node _T_113 = eq(_T_112, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_29 node _T_114 = asUInt(reset) node _T_115 = eq(_T_114, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_109, _T_111) : printf_30 node _T_116 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_117 = lt(UInt<3>(0h6), _T_116) when _T_117 : node _T_118 = add(request_input.bits.addr, UInt<3>(0h6)) node _T_119 = tail(_T_118, 1) node _T_120 = dshr(request_input.bits.data, UInt<6>(0h30)) node _T_121 = bits(_T_120, 7, 0) regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_31 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_119, _T_121) : printf_32 node _T_126 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_127 = lt(UInt<3>(0h7), _T_126) when _T_127 : node _T_128 = add(request_input.bits.addr, UInt<3>(0h7)) node _T_129 = tail(_T_128, 1) node _T_130 = dshr(request_input.bits.data, UInt<6>(0h38)) node _T_131 = bits(_T_130, 7, 0) regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_33 node _T_134 = asUInt(reset) node _T_135 = eq(_T_134, UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_129, _T_131) : printf_34 node _T_136 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_137 = lt(UInt<4>(0h8), _T_136) when _T_137 : node _T_138 = add(request_input.bits.addr, UInt<4>(0h8)) node _T_139 = tail(_T_138, 1) node _T_140 = dshr(request_input.bits.data, UInt<7>(0h40)) node _T_141 = bits(_T_140, 7, 0) regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_35 node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_139, _T_141) : printf_36 node _T_146 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_147 = lt(UInt<4>(0h9), _T_146) when _T_147 : node _T_148 = add(request_input.bits.addr, UInt<4>(0h9)) node _T_149 = tail(_T_148, 1) node _T_150 = dshr(request_input.bits.data, UInt<7>(0h48)) node _T_151 = bits(_T_150, 7, 0) regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_37 node _T_154 = asUInt(reset) node _T_155 = eq(_T_154, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_149, _T_151) : printf_38 node _T_156 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_157 = lt(UInt<4>(0ha), _T_156) when _T_157 : node _T_158 = add(request_input.bits.addr, UInt<4>(0ha)) node _T_159 = tail(_T_158, 1) node _T_160 = dshr(request_input.bits.data, UInt<7>(0h50)) node _T_161 = bits(_T_160, 7, 0) regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_39 node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_159, _T_161) : printf_40 node _T_166 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_167 = lt(UInt<4>(0hb), _T_166) when _T_167 : node _T_168 = add(request_input.bits.addr, UInt<4>(0hb)) node _T_169 = tail(_T_168, 1) node _T_170 = dshr(request_input.bits.data, UInt<7>(0h58)) node _T_171 = bits(_T_170, 7, 0) regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_41 node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_169, _T_171) : printf_42 node _T_176 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_177 = lt(UInt<4>(0hc), _T_176) when _T_177 : node _T_178 = add(request_input.bits.addr, UInt<4>(0hc)) node _T_179 = tail(_T_178, 1) node _T_180 = dshr(request_input.bits.data, UInt<7>(0h60)) node _T_181 = bits(_T_180, 7, 0) regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_43 node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_179, _T_181) : printf_44 node _T_186 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_187 = lt(UInt<4>(0hd), _T_186) when _T_187 : node _T_188 = add(request_input.bits.addr, UInt<4>(0hd)) node _T_189 = tail(_T_188, 1) node _T_190 = dshr(request_input.bits.data, UInt<7>(0h68)) node _T_191 = bits(_T_190, 7, 0) regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_45 node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_189, _T_191) : printf_46 node _T_196 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_197 = lt(UInt<4>(0he), _T_196) when _T_197 : node _T_198 = add(request_input.bits.addr, UInt<4>(0he)) node _T_199 = tail(_T_198, 1) node _T_200 = dshr(request_input.bits.data, UInt<7>(0h70)) node _T_201 = bits(_T_200, 7, 0) regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_47 node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_199, _T_201) : printf_48 node _T_206 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_207 = lt(UInt<4>(0hf), _T_206) when _T_207 : node _T_208 = add(request_input.bits.addr, UInt<4>(0hf)) node _T_209 = tail(_T_208, 1) node _T_210 = dshr(request_input.bits.data, UInt<7>(0h78)) node _T_211 = bits(_T_210, 7, 0) regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_49 node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_209, _T_211) : printf_50 node _T_216 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_217 = lt(UInt<5>(0h10), _T_216) when _T_217 : node _T_218 = add(request_input.bits.addr, UInt<5>(0h10)) node _T_219 = tail(_T_218, 1) node _T_220 = dshr(request_input.bits.data, UInt<8>(0h80)) node _T_221 = bits(_T_220, 7, 0) regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_51 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_219, _T_221) : printf_52 node _T_226 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_227 = lt(UInt<5>(0h11), _T_226) when _T_227 : node _T_228 = add(request_input.bits.addr, UInt<5>(0h11)) node _T_229 = tail(_T_228, 1) node _T_230 = dshr(request_input.bits.data, UInt<8>(0h88)) node _T_231 = bits(_T_230, 7, 0) regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_232 = asUInt(reset) node _T_233 = eq(_T_232, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_53 node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_229, _T_231) : printf_54 node _T_236 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_237 = lt(UInt<5>(0h12), _T_236) when _T_237 : node _T_238 = add(request_input.bits.addr, UInt<5>(0h12)) node _T_239 = tail(_T_238, 1) node _T_240 = dshr(request_input.bits.data, UInt<8>(0h90)) node _T_241 = bits(_T_240, 7, 0) regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_55 node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_239, _T_241) : printf_56 node _T_246 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_247 = lt(UInt<5>(0h13), _T_246) when _T_247 : node _T_248 = add(request_input.bits.addr, UInt<5>(0h13)) node _T_249 = tail(_T_248, 1) node _T_250 = dshr(request_input.bits.data, UInt<8>(0h98)) node _T_251 = bits(_T_250, 7, 0) regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_57 node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_249, _T_251) : printf_58 node _T_256 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_257 = lt(UInt<5>(0h14), _T_256) when _T_257 : node _T_258 = add(request_input.bits.addr, UInt<5>(0h14)) node _T_259 = tail(_T_258, 1) node _T_260 = dshr(request_input.bits.data, UInt<8>(0ha0)) node _T_261 = bits(_T_260, 7, 0) regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_59 node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_259, _T_261) : printf_60 node _T_266 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_267 = lt(UInt<5>(0h15), _T_266) when _T_267 : node _T_268 = add(request_input.bits.addr, UInt<5>(0h15)) node _T_269 = tail(_T_268, 1) node _T_270 = dshr(request_input.bits.data, UInt<8>(0ha8)) node _T_271 = bits(_T_270, 7, 0) regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_272 = asUInt(reset) node _T_273 = eq(_T_272, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_61 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_269, _T_271) : printf_62 node _T_276 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_277 = lt(UInt<5>(0h16), _T_276) when _T_277 : node _T_278 = add(request_input.bits.addr, UInt<5>(0h16)) node _T_279 = tail(_T_278, 1) node _T_280 = dshr(request_input.bits.data, UInt<8>(0hb0)) node _T_281 = bits(_T_280, 7, 0) regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_63 node _T_284 = asUInt(reset) node _T_285 = eq(_T_284, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_279, _T_281) : printf_64 node _T_286 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_287 = lt(UInt<5>(0h17), _T_286) when _T_287 : node _T_288 = add(request_input.bits.addr, UInt<5>(0h17)) node _T_289 = tail(_T_288, 1) node _T_290 = dshr(request_input.bits.data, UInt<8>(0hb8)) node _T_291 = bits(_T_290, 7, 0) regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_292 = asUInt(reset) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_65 node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_289, _T_291) : printf_66 node _T_296 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_297 = lt(UInt<5>(0h18), _T_296) when _T_297 : node _T_298 = add(request_input.bits.addr, UInt<5>(0h18)) node _T_299 = tail(_T_298, 1) node _T_300 = dshr(request_input.bits.data, UInt<8>(0hc0)) node _T_301 = bits(_T_300, 7, 0) regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_67 node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_299, _T_301) : printf_68 node _T_306 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_307 = lt(UInt<5>(0h19), _T_306) when _T_307 : node _T_308 = add(request_input.bits.addr, UInt<5>(0h19)) node _T_309 = tail(_T_308, 1) node _T_310 = dshr(request_input.bits.data, UInt<8>(0hc8)) node _T_311 = bits(_T_310, 7, 0) regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_69 node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_309, _T_311) : printf_70 node _T_316 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_317 = lt(UInt<5>(0h1a), _T_316) when _T_317 : node _T_318 = add(request_input.bits.addr, UInt<5>(0h1a)) node _T_319 = tail(_T_318, 1) node _T_320 = dshr(request_input.bits.data, UInt<8>(0hd0)) node _T_321 = bits(_T_320, 7, 0) regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_322 = asUInt(reset) node _T_323 = eq(_T_322, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_71 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_319, _T_321) : printf_72 node _T_326 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_327 = lt(UInt<5>(0h1b), _T_326) when _T_327 : node _T_328 = add(request_input.bits.addr, UInt<5>(0h1b)) node _T_329 = tail(_T_328, 1) node _T_330 = dshr(request_input.bits.data, UInt<8>(0hd8)) node _T_331 = bits(_T_330, 7, 0) regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_73 node _T_334 = asUInt(reset) node _T_335 = eq(_T_334, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_329, _T_331) : printf_74 node _T_336 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_337 = lt(UInt<5>(0h1c), _T_336) when _T_337 : node _T_338 = add(request_input.bits.addr, UInt<5>(0h1c)) node _T_339 = tail(_T_338, 1) node _T_340 = dshr(request_input.bits.data, UInt<8>(0he0)) node _T_341 = bits(_T_340, 7, 0) regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1)) node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1) connect loginfo_cycles_35, _loginfo_cycles_T_71 node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_75 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_339, _T_341) : printf_76 node _T_346 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_347 = lt(UInt<5>(0h1d), _T_346) when _T_347 : node _T_348 = add(request_input.bits.addr, UInt<5>(0h1d)) node _T_349 = tail(_T_348, 1) node _T_350 = dshr(request_input.bits.data, UInt<8>(0he8)) node _T_351 = bits(_T_350, 7, 0) regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1)) node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1) connect loginfo_cycles_36, _loginfo_cycles_T_73 node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_77 node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_349, _T_351) : printf_78 node _T_356 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_357 = lt(UInt<5>(0h1e), _T_356) when _T_357 : node _T_358 = add(request_input.bits.addr, UInt<5>(0h1e)) node _T_359 = tail(_T_358, 1) node _T_360 = dshr(request_input.bits.data, UInt<8>(0hf0)) node _T_361 = bits(_T_360, 7, 0) regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1)) node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1) connect loginfo_cycles_37, _loginfo_cycles_T_75 node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_79 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_359, _T_361) : printf_80 node _T_366 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_367 = lt(UInt<5>(0h1f), _T_366) when _T_367 : node _T_368 = add(request_input.bits.addr, UInt<5>(0h1f)) node _T_369 = tail(_T_368, 1) node _T_370 = dshr(request_input.bits.data, UInt<8>(0hf8)) node _T_371 = bits(_T_370, 7, 0) regreset loginfo_cycles_38 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_76 = add(loginfo_cycles_38, UInt<1>(0h1)) node _loginfo_cycles_T_77 = tail(_loginfo_cycles_T_76, 1) connect loginfo_cycles_38, _loginfo_cycles_T_77 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_38) : printf_81 node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_369, _T_371) : printf_82 inst response_latency_injection_q of LatencyInjectionQueue_19 connect response_latency_injection_q.clock, clock connect response_latency_injection_q.reset, reset connect response_latency_injection_q.io.latency_cycles, io.latency_inject_cycles connect response_latency_injection_q.io.enq, masterNodeOut.d node _selectQready_T = eq(UInt<1>(0h0), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _selectQready_T) node _selectQready_T_2 = eq(UInt<1>(0h1), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _selectQready_T_2) node _selectQready_T_4 = eq(UInt<2>(0h2), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _selectQready_T_4) node _selectQready_T_6 = eq(UInt<2>(0h3), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _selectQready_T_6) node _selectQready_T_8 = or(_selectQready_T_1, _selectQready_T_3) node _selectQready_T_9 = or(_selectQready_T_8, _selectQready_T_5) node selectQready = or(_selectQready_T_9, _selectQready_T_7) node _T_376 = and(selectQready, response_latency_injection_q.io.deq.valid) when _T_376 : connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) connect tags_for_issue_Q.io.enq.bits, response_latency_injection_q.io.deq.bits.source node _T_377 = and(selectQready, response_latency_injection_q.io.deq.valid) node _T_378 = and(_T_377, tags_for_issue_Q.io.enq.valid) when _T_378 : regreset loginfo_cycles_39 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_78 = add(loginfo_cycles_39, UInt<1>(0h1)) node _loginfo_cycles_T_79 = tail(_loginfo_cycles_T_78, 1) connect loginfo_cycles_39, _loginfo_cycles_T_79 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_39) : printf_83 node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] tags_for_issue_Q add back tag %d\n", tags_for_issue_Q.io.enq.bits) : printf_84 node _response_latency_injection_q_io_deq_ready_T = and(selectQready, tags_for_issue_Q.io.enq.ready) connect response_latency_injection_q.io.deq.ready, _response_latency_injection_q_io_deq_ready_T node _T_383 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_384 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h0)) node _T_385 = and(_T_383, _T_384) connect Queue4_L2RespInternal.io.enq.valid, _T_385 connect Queue4_L2RespInternal.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_386 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_387 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h1)) node _T_388 = and(_T_386, _T_387) connect Queue4_L2RespInternal_1.io.enq.valid, _T_388 connect Queue4_L2RespInternal_1.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_389 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_390 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h2)) node _T_391 = and(_T_389, _T_390) connect Queue4_L2RespInternal_2.io.enq.valid, _T_391 connect Queue4_L2RespInternal_2.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_392 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_393 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h3)) node _T_394 = and(_T_392, _T_393) connect Queue4_L2RespInternal_3.io.enq.valid, _T_394 connect Queue4_L2RespInternal_3.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _queueValid_T = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_1 = and(Queue4_L2RespInternal.io.deq.valid, _queueValid_T) node _queueValid_T_2 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_3 = and(Queue4_L2RespInternal_1.io.deq.valid, _queueValid_T_2) node _queueValid_T_4 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_5 = and(Queue4_L2RespInternal_2.io.deq.valid, _queueValid_T_4) node _queueValid_T_6 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_7 = and(Queue4_L2RespInternal_3.io.deq.valid, _queueValid_T_6) node _queueValid_T_8 = or(_queueValid_T_1, _queueValid_T_3) node _queueValid_T_9 = or(_queueValid_T_8, _queueValid_T_5) node queueValid = or(_queueValid_T_9, _queueValid_T_7) node resultdata_is_current_q = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data : UInt<256> when resultdata_is_current_q : node _resultdata_data_T = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_1 = dshr(Queue4_L2RespInternal.io.deq.bits.data, _resultdata_data_T) connect resultdata_data, _resultdata_data_T_1 else : connect resultdata_data, UInt<1>(0h0) node resultdata_is_current_q_1 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_1 : UInt<256> when resultdata_is_current_q_1 : node _resultdata_data_T_2 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_3 = dshr(Queue4_L2RespInternal_1.io.deq.bits.data, _resultdata_data_T_2) connect resultdata_data_1, _resultdata_data_T_3 else : connect resultdata_data_1, UInt<1>(0h0) node resultdata_is_current_q_2 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_2 : UInt<256> when resultdata_is_current_q_2 : node _resultdata_data_T_4 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_5 = dshr(Queue4_L2RespInternal_2.io.deq.bits.data, _resultdata_data_T_4) connect resultdata_data_2, _resultdata_data_T_5 else : connect resultdata_data_2, UInt<1>(0h0) node resultdata_is_current_q_3 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_3 : UInt<256> when resultdata_is_current_q_3 : node _resultdata_data_T_6 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_7 = dshr(Queue4_L2RespInternal_3.io.deq.bits.data, _resultdata_data_T_6) connect resultdata_data_3, _resultdata_data_T_7 else : connect resultdata_data_3, UInt<1>(0h0) node _resultdata_T = or(resultdata_data, resultdata_data_1) node _resultdata_T_1 = or(_resultdata_T, resultdata_data_2) node resultdata = or(_resultdata_T_1, resultdata_data_3) connect response_output.bits.data, resultdata node _response_output_valid_T = and(queueValid, outstanding_req_addr.io.deq.valid) connect response_output.valid, _response_output_valid_T node _outstanding_req_addr_io_deq_ready_T = and(queueValid, response_output.ready) connect outstanding_req_addr.io.deq.ready, _outstanding_req_addr_io_deq_ready_T node _T_395 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_396 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h0)) node _T_397 = and(_T_395, _T_396) connect Queue4_L2RespInternal.io.deq.ready, _T_397 node _T_398 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_399 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h1)) node _T_400 = and(_T_398, _T_399) connect Queue4_L2RespInternal_1.io.deq.ready, _T_400 node _T_401 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_402 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h2)) node _T_403 = and(_T_401, _T_402) connect Queue4_L2RespInternal_2.io.deq.ready, _T_403 node _T_404 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_405 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h3)) node _T_406 = and(_T_404, _T_405) connect Queue4_L2RespInternal_3.io.deq.ready, _T_406 node _T_407 = and(masterNodeOut.d.ready, masterNodeOut.d.valid) when _T_407 : node opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) when opdata : regreset loginfo_cycles_40 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_80 = add(loginfo_cycles_40, UInt<1>(0h1)) node _loginfo_cycles_T_81 = tail(_loginfo_cycles_T_80, 1) connect loginfo_cycles_40, _loginfo_cycles_T_81 node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_40) : printf_85 node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n", masterNodeOut.d.bits.data, global_memop_ackd, masterNodeOut.d.bits.source) : printf_86 else : regreset loginfo_cycles_41 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_82 = add(loginfo_cycles_41, UInt<1>(0h1)) node _loginfo_cycles_T_83 = tail(_loginfo_cycles_T_82, 1) connect loginfo_cycles_41, _loginfo_cycles_T_83 node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_41) : printf_87 node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: resp(write) opnum: %d, gettag: %d\n", global_memop_ackd, masterNodeOut.d.bits.source) : printf_88 node _T_416 = and(response_output.ready, response_output.valid) when _T_416 : regreset loginfo_cycles_42 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_84 = add(loginfo_cycles_42, UInt<1>(0h1)) node _loginfo_cycles_T_85 = tail(_loginfo_cycles_T_84, 1) connect loginfo_cycles_42, _loginfo_cycles_T_85 node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_42) : printf_89 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n", resultdata, global_memop_resp_to_user, outstanding_req_addr.io.deq.bits.tag) : printf_90 node _T_421 = and(response_latency_injection_q.io.deq.ready, response_latency_injection_q.io.deq.valid) when _T_421 : node _global_memop_ackd_T = add(global_memop_ackd, UInt<1>(0h1)) node _global_memop_ackd_T_1 = tail(_global_memop_ackd_T, 1) connect global_memop_ackd, _global_memop_ackd_T_1 node _T_422 = and(response_output.ready, response_output.valid) when _T_422 : node _global_memop_resp_to_user_T = add(global_memop_resp_to_user, UInt<1>(0h1)) node _global_memop_resp_to_user_T_1 = tail(_global_memop_resp_to_user_T, 1) connect global_memop_resp_to_user, _global_memop_resp_to_user_T_1 extmodule plusarg_reader_134 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_135 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module L2MemHelperLatencyInjection_9( // @[L2MemHelperLatencyInjection.scala:29:7] input clock, // @[L2MemHelperLatencyInjection.scala:29:7] input reset, // @[L2MemHelperLatencyInjection.scala:29:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_master_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_master_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [255:0] auto_master_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_master_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [255:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_userif_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_userif_req_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [2:0] io_userif_req_bits_size, // @[L2MemHelperLatencyInjection.scala:33:14] input [255:0] io_userif_req_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_bits_cmd, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_resp_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [255:0] io_userif_resp_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_no_memops_inflight, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_latency_inject_cycles, // @[L2MemHelperLatencyInjection.scala:33:14] input io_sfence, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [26:0] io_ptw_req_bits_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_bits_bits_need_gpa, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_ptw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_final, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hx, // @[L2MemHelperLatencyInjection.scala:33:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_d, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_g, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_u, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_r, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_level, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_homogeneous, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_is_pte, // @[L2MemHelperLatencyInjection.scala:33:14] input [3:0] io_ptw_ptbr_mode, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_ptbr_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_status_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spvp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_gstatus_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_ptw_gstatus_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_ptw_gstatus_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_uie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_0_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_0_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_1_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_1_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_2_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_2_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_3_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_3_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_4_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_4_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_5_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_5_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_6_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_6_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_7_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_7_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_status_bits_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_status_bits_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_uxl, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd_rv32, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_status_bits_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_xs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_uie // @[L2MemHelperLatencyInjection.scala:33:14] ); wire _response_latency_injection_q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:245:44] wire [1:0] _response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44] wire [255:0] _response_latency_injection_q_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:245:44] wire _Queue4_L2RespInternal_3_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_3_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_2_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_1_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _request_latency_injection_q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:151:43] wire _tags_for_issue_Q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:94:32] wire _tags_for_issue_Q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:94:32] wire [1:0] _tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32] wire _outstanding_req_addr_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:91:36] wire _outstanding_req_addr_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_addrindex; // @[L2MemHelperLatencyInjection.scala:91:36] wire [1:0] _outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36] wire _tlb_io_req_ready; // @[L2MemHelperLatencyInjection.scala:68:19] wire _tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19] wire [31:0] _tlb_io_resp_paddr; // @[L2MemHelperLatencyInjection.scala:68:19] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_valid_0 = io_userif_req_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_userif_req_bits_addr_0 = io_userif_req_bits_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] io_userif_req_bits_size_0 = io_userif_req_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_req_bits_data_0 = io_userif_req_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_bits_cmd_0 = io_userif_req_bits_cmd; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_ready_0 = io_userif_resp_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_latency_inject_cycles_0 = io_latency_inject_cycles; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_sfence_0 = io_sfence; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[L2MemHelperLatencyInjection.scala:29:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_valid_0 = io_status_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_debug_0 = io_status_bits_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_cease_0 = io_status_bits_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_wfi_0 = io_status_bits_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_status_bits_isa_0 = io_status_bits_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_dprv_0 = io_status_bits_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_dv_0 = io_status_bits_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_prv_0 = io_status_bits_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_v_0 = io_status_bits_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_0 = io_status_bits_sd; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_status_bits_zero2_0 = io_status_bits_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpv_0 = io_status_bits_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_gva_0 = io_status_bits_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mbe_0 = io_status_bits_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sbe_0 = io_status_bits_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_sxl_0 = io_status_bits_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_uxl_0 = io_status_bits_uxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_rv32_0 = io_status_bits_sd_rv32; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_status_bits_zero1_0 = io_status_bits_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tsr_0 = io_status_bits_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tw_0 = io_status_bits_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tvm_0 = io_status_bits_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mxr_0 = io_status_bits_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sum_0 = io_status_bits_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mprv_0 = io_status_bits_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_xs_0 = io_status_bits_xs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_fs_0 = io_status_bits_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_mpp_0 = io_status_bits_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_vs_0 = io_status_bits_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spp_0 = io_status_bits_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpie_0 = io_status_bits_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_ube_0 = io_status_bits_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spie_0 = io_status_bits_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_upie_0 = io_status_bits_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mie_0 = io_status_bits_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_hie_0 = io_status_bits_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sie_0 = io_status_bits_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_uie_0 = io_status_bits_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire _printf_T = reset; // @[annotations.scala:102:49] wire _printf_T_2 = reset; // @[annotations.scala:102:49] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_ube = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_upie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_hie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_uie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtw = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_hu = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire bundle_corrupt = 1'h0; // @[Edges.scala:460:17] wire _legal_T_125 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_131 = 1'h0; // @[Parameters.scala:684:54] wire bundle_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_valid = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_64 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_65 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_66 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_73 = 1'h1; // @[Parameters.scala:92:28] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] bundle_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] bundle_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_1_param = 3'h0; // @[Edges.scala:480:17] wire [255:0] bundle_data = 256'h0; // @[Edges.scala:460:17] wire [2:0] bundle_opcode = 3'h4; // @[Edges.scala:460:17] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire request_input_ready; // @[L2MemHelperLatencyInjection.scala:44:27] wire request_input_valid = io_userif_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [63:0] request_input_bits_addr = io_userif_req_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [2:0] request_input_bits_size = io_userif_req_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [255:0] request_input_bits_data = io_userif_req_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire request_input_bits_cmd = io_userif_req_bits_cmd_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire response_output_ready = io_userif_resp_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire response_output_valid; // @[L2MemHelperLatencyInjection.scala:53:29] wire [255:0] response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:53:29] wire _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:128:57] wire [2:0] auto_master_out_a_bits_opcode_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_a_bits_param_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_a_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_a_bits_source_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_address_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_mask_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_a_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_bits_corrupt_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_resp_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_no_memops_inflight_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_opcode_0 = masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_param_0 = masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_size_0 = masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_source_0 = masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_mask_0 = masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_data_0 = masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_corrupt_0 = masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_master_out_d_ready_0 = masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire _request_input_ready_T_4; // @[Misc.scala:26:53] assign io_userif_req_ready_0 = request_input_ready; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire _response_output_valid_T; // @[Misc.scala:26:53] assign io_userif_resp_valid_0 = response_output_valid; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire [255:0] resultdata; // @[L2MemHelperLatencyInjection.scala:307:15] assign io_userif_resp_bits_data_0 = response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] reg status_debug; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_cease; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_wfi; // @[L2MemHelperLatencyInjection.scala:62:19] reg [31:0] status_isa; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_dprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_dv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_prv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_v; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd; // @[L2MemHelperLatencyInjection.scala:62:19] reg [22:0] status_zero2; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_gva; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_sxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_uxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd_rv32; // @[L2MemHelperLatencyInjection.scala:62:19] reg [7:0] status_zero1; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tsr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tw; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tvm; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mxr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sum; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_xs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_fs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_mpp; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_vs; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spp; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_ube; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_upie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_hie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_uie; // @[L2MemHelperLatencyInjection.scala:62:19] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _tlb_ready_T = ~_tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19, :74:39] wire tlb_ready = _tlb_io_req_ready & _tlb_ready_T; // @[L2MemHelperLatencyInjection.scala:68:19, :74:{36,39}] reg [2:0] tags_init_reg; // @[L2MemHelperLatencyInjection.scala:98:30] wire _T_4 = tags_init_reg != 3'h4; // @[L2MemHelperLatencyInjection.scala:98:30, :99:23] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] wire [3:0] _tags_init_reg_T = {1'h0, tags_init_reg} + 4'h1; // @[L2MemHelperLatencyInjection.scala:98:30, :104:38] wire [2:0] _tags_init_reg_T_1 = _tags_init_reg_T[2:0]; // @[L2MemHelperLatencyInjection.scala:104:38] wire [70:0] _addr_mask_check_T = 71'h1 << request_input_bits_size; // @[L2MemHelperLatencyInjection.scala:44:27, :108:36] wire [71:0] _addr_mask_check_T_1 = {1'h0, _addr_mask_check_T} - 72'h1; // @[L2MemHelperLatencyInjection.scala:108:{36,64}] wire [70:0] addr_mask_check = _addr_mask_check_T_1[70:0]; // @[L2MemHelperLatencyInjection.scala:108:64] wire _assertcheck_T = ~request_input_valid; // @[L2MemHelperLatencyInjection.scala:44:27, :109:30] wire [70:0] _assertcheck_T_1 = {7'h0, addr_mask_check[63:0] & request_input_bits_addr}; // @[L2MemHelperLatencyInjection.scala:44:27, :108:64, :109:81] wire _assertcheck_T_2 = _assertcheck_T_1 == 71'h0; // @[L2MemHelperLatencyInjection.scala:108:64, :109:{81,100}] wire _assertcheck_T_3 = _assertcheck_T \| _assertcheck_T_2; // @[L2MemHelperLatencyInjection.scala:109:{30,52,100}] reg assertcheck; // @[L2MemHelperLatencyInjection.scala:109:28] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] global_memop_accepted; // @[L2MemHelperLatencyInjection.scala:117:38] wire [64:0] _global_memop_accepted_T = {1'h0, global_memop_accepted} + 65'h1; // @[L2MemHelperLatencyInjection.scala:117:38, :119:52] wire [63:0] _global_memop_accepted_T_1 = _global_memop_accepted_T[63:0]; // @[L2MemHelperLatencyInjection.scala:119:52] reg [63:0] global_memop_sent; // @[L2MemHelperLatencyInjection.scala:122:34] reg [63:0] global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:124:34] reg [63:0] global_memop_resp_to_user; // @[L2MemHelperLatencyInjection.scala:126:42] assign _io_userif_no_memops_inflight_T = global_memop_accepted == global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:117:38, :124:34, :128:57] assign io_userif_no_memops_inflight_0 = _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:29:7, :128:57] wire [64:0] _GEN = {1'h0, global_memop_sent}; // @[L2MemHelperLatencyInjection.scala:122:34, :130:54] wire [64:0] _GEN_0 = {1'h0, global_memop_ackd}; // @[L2MemHelperLatencyInjection.scala:124:34, :130:54] wire [64:0] _GEN_1 = _GEN - _GEN_0; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:130:54] assign _free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _assert_free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:131:61] assign _assert_free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54, :131:61] wire [63:0] _free_outstanding_op_slots_T_1 = _free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:130:54] wire free_outstanding_op_slots = _free_outstanding_op_slots_T_1 < 64'h4; // @[L2MemHelperLatencyInjection.scala:130:{54,75}] wire [63:0] _assert_free_outstanding_op_slots_T_1 = _assert_free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:131:61] wire assert_free_outstanding_op_slots = _assert_free_outstanding_op_slots_T_1 < 64'h5; // @[L2MemHelperLatencyInjection.scala:131:{61,82}] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] wire [64:0] _global_memop_sent_T = _GEN + 65'h1; // @[L2MemHelperLatencyInjection.scala:130:54, :140:44] wire [63:0] _global_memop_sent_T_1 = _global_memop_sent_T[63:0]; // @[L2MemHelperLatencyInjection.scala:140:44] reg [63:0] cur_cycle; // @[L2MemHelperLatencyInjection.scala:146:26] wire [64:0] _cur_cycle_T = {1'h0, cur_cycle} + 65'h1; // @[L2MemHelperLatencyInjection.scala:146:26, :147:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[L2MemHelperLatencyInjection.scala:147:26] wire [31:0] _GEN_2 = {_tlb_io_resp_paddr[31:14], _tlb_io_resp_paddr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_4; // @[Parameters.scala:137:31] assign _legal_T_4 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _legal_T_67; // @[Parameters.scala:137:31] assign _legal_T_67 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_62 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _GEN_3 = request_input_bits_size != 3'h7; // @[Parameters.scala:92:38] wire _legal_T_11; // @[Parameters.scala:92:38] assign _legal_T_11 = _GEN_3; // @[Parameters.scala:92:38] wire _legal_T_74; // @[Parameters.scala:92:38] assign _legal_T_74 = _GEN_3; // @[Parameters.scala:92:38] wire _legal_T_12 = _legal_T_11; // @[Parameters.scala:92:{33,38}] wire _legal_T_13 = _legal_T_12; // @[Parameters.scala:684:29] wire [31:0] _legal_T_14; // @[Parameters.scala:137:31] wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_16 = _legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46] wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = {_tlb_io_resp_paddr[31:17], _tlb_io_resp_paddr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_19; // @[Parameters.scala:137:31] assign _legal_T_19 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_24; // @[Parameters.scala:137:31] assign _legal_T_24 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_126; // @[Parameters.scala:137:31] assign _legal_T_126 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_21 = _legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46] wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_26 = _legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46] wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_5 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_29; // @[Parameters.scala:137:31] assign _legal_T_29 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_87; // @[Parameters.scala:137:31] assign _legal_T_87 = _GEN_5; // @[Parameters.scala:137:31] wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_31 = _legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46] wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_6 = {_tlb_io_resp_paddr[31:28], _tlb_io_resp_paddr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_34; // @[Parameters.scala:137:31] assign _legal_T_34 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_39; // @[Parameters.scala:137:31] assign _legal_T_39 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_97; // @[Parameters.scala:137:31] assign _legal_T_97 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_102; // @[Parameters.scala:137:31] assign _legal_T_102 = _GEN_6; // @[Parameters.scala:137:31] wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_36 = _legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46] wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_41 = _legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46] wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_7 = {_tlb_io_resp_paddr[31:29], _tlb_io_resp_paddr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_44; // @[Parameters.scala:137:31] assign _legal_T_44 = _GEN_7; // @[Parameters.scala:137:31] wire [31:0] _legal_T_107; // @[Parameters.scala:137:31] assign _legal_T_107 = _GEN_7; // @[Parameters.scala:137:31] wire [32:0] _legal_T_45 = {1'h0, _legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_46 = _legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_47 = _legal_T_46; // @[Parameters.scala:137:46] wire _legal_T_48 = _legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_8 = _tlb_io_resp_paddr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _legal_T_49; // @[Parameters.scala:137:31] assign _legal_T_49 = _GEN_8; // @[Parameters.scala:137:31] wire [31:0] _legal_T_112; // @[Parameters.scala:137:31] assign _legal_T_112 = _GEN_8; // @[Parameters.scala:137:31] wire [32:0] _legal_T_50 = {1'h0, _legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_51 = _legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_52 = _legal_T_51; // @[Parameters.scala:137:46] wire _legal_T_53 = _legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_54 = _legal_T_18 \| _legal_T_23; // @[Parameters.scala:685:42] wire _legal_T_55 = _legal_T_54 \| _legal_T_28; // @[Parameters.scala:685:42] wire _legal_T_56 = _legal_T_55 \| _legal_T_33; // @[Parameters.scala:685:42] wire _legal_T_57 = _legal_T_56 \| _legal_T_38; // @[Parameters.scala:685:42] wire _legal_T_58 = _legal_T_57 \| _legal_T_43; // @[Parameters.scala:685:42] wire _legal_T_59 = _legal_T_58 \| _legal_T_48; // @[Parameters.scala:685:42] wire _legal_T_60 = _legal_T_59 \| _legal_T_53; // @[Parameters.scala:685:42] wire _legal_T_61 = _legal_T_13 & _legal_T_60; // @[Parameters.scala:684:{29,54}, :685:42] wire legal = _legal_T_62 \| _legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [31:0] _a_mask_T; // @[Misc.scala:222:10] wire [3:0] bundle_size; // @[Edges.scala:460:17] wire [1:0] bundle_source; // @[Edges.scala:460:17] wire [31:0] bundle_address; // @[Edges.scala:460:17] wire [31:0] bundle_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_9 = {1'h0, request_input_bits_size}; // @[Edges.scala:463:15] assign bundle_size = _GEN_9; // @[Edges.scala:460:17, :463:15] wire [3:0] bundle_1_size; // @[Edges.scala:480:17] assign bundle_1_size = _GEN_9; // @[Edges.scala:463:15, :480:17] wire [4:0] _GEN_10 = {2'h0, request_input_bits_size}; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _a_mask_sizeOH_T = _GEN_10; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _a_mask_sizeOH_T_3 = _GEN_10; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T = _a_mask_sizeOH_T; // @[OneHot.scala:64:31] wire [2:0] a_mask_sizeOH_shiftAmount = _a_mask_sizeOH_shiftAmount_T[2:0]; // @[OneHot.scala:64:{31,49}] wire [7:0] _a_mask_sizeOH_T_1 = 8'h1 << a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _a_mask_sizeOH_T_2 = _a_mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] a_mask_sizeOH = {_a_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire _GEN_11 = request_input_bits_size > 3'h4; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21] assign a_mask_sub_sub_sub_sub_sub_0_1 = _GEN_11; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_sub_0_1_1; // @[Misc.scala:206:21] assign a_mask_sub_sub_sub_sub_sub_0_1_1 = _GEN_11; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_size = a_mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_sub_bit = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_sub_acc_T = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_sub_0_1 \| _a_mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _a_mask_sub_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_sub_0_1 \| _a_mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire a_mask_sub_sub_sub_size = a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_bit = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_0_1 \| _a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_0_1 \| _a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_2_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_2_1 = a_mask_sub_sub_sub_sub_1_1 \| _a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_3_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_3_1 = a_mask_sub_sub_sub_sub_1_1 \| _a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_size = a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_bit = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_bit_1 = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T = a_mask_sub_sub_size & a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_0_1 = a_mask_sub_sub_sub_0_1 \| _a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_1_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_1 = a_mask_sub_sub_size & a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_1_1 = a_mask_sub_sub_sub_0_1 \| _a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_2_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_2 = a_mask_sub_sub_size & a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_2_1 = a_mask_sub_sub_sub_1_1 \| _a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_3_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_3 = a_mask_sub_sub_size & a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_3_1 = a_mask_sub_sub_sub_1_1 \| _a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_4_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_4 = a_mask_sub_sub_size & a_mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_4_1 = a_mask_sub_sub_sub_2_1 \| _a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_5_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_5 = a_mask_sub_sub_size & a_mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_5_1 = a_mask_sub_sub_sub_2_1 \| _a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_6_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_6 = a_mask_sub_sub_size & a_mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_6_1 = a_mask_sub_sub_sub_3_1 \| _a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_7_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_7 = a_mask_sub_sub_size & a_mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_7_1 = a_mask_sub_sub_sub_3_1 \| _a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_size = a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_bit = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_bit_1 = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T = a_mask_sub_size & a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_0_1 = a_mask_sub_sub_0_1 \| _a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_1 = a_mask_sub_size & a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_1_1 = a_mask_sub_sub_0_1 \| _a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_2 = a_mask_sub_size & a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_2_1 = a_mask_sub_sub_1_1 \| _a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_3 = a_mask_sub_size & a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_3_1 = a_mask_sub_sub_1_1 \| _a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_4_2 = a_mask_sub_sub_2_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_4 = a_mask_sub_size & a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_4_1 = a_mask_sub_sub_2_1 \| _a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_5_2 = a_mask_sub_sub_2_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_5 = a_mask_sub_size & a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_5_1 = a_mask_sub_sub_2_1 \| _a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_6_2 = a_mask_sub_sub_3_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_6 = a_mask_sub_size & a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_6_1 = a_mask_sub_sub_3_1 \| _a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_7_2 = a_mask_sub_sub_3_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_7 = a_mask_sub_size & a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_7_1 = a_mask_sub_sub_3_1 \| _a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_8_2 = a_mask_sub_sub_4_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_8 = a_mask_sub_size & a_mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_8_1 = a_mask_sub_sub_4_1 \| _a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_sub_9_2 = a_mask_sub_sub_4_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_9 = a_mask_sub_size & a_mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_9_1 = a_mask_sub_sub_4_1 \| _a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_sub_10_2 = a_mask_sub_sub_5_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_10 = a_mask_sub_size & a_mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_10_1 = a_mask_sub_sub_5_1 \| _a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_sub_11_2 = a_mask_sub_sub_5_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_11 = a_mask_sub_size & a_mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_11_1 = a_mask_sub_sub_5_1 \| _a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_sub_12_2 = a_mask_sub_sub_6_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_12 = a_mask_sub_size & a_mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_12_1 = a_mask_sub_sub_6_1 \| _a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_sub_13_2 = a_mask_sub_sub_6_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_13 = a_mask_sub_size & a_mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_13_1 = a_mask_sub_sub_6_1 \| _a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_sub_14_2 = a_mask_sub_sub_7_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_14 = a_mask_sub_size & a_mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_14_1 = a_mask_sub_sub_7_1 \| _a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_sub_15_2 = a_mask_sub_sub_7_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_15 = a_mask_sub_size & a_mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_15_1 = a_mask_sub_sub_7_1 \| _a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_size = a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire a_mask_bit = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_bit_1 = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_size & a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc = a_mask_sub_0_1 \| _a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_size & a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_1 = a_mask_sub_0_1 \| _a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_size & a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_2 = a_mask_sub_1_1 \| _a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_size & a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_3 = a_mask_sub_1_1 \| _a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_size & a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_4 = a_mask_sub_2_1 \| _a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_size & a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_5 = a_mask_sub_2_1 \| _a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_size & a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_6 = a_mask_sub_3_1 \| _a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_size & a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_7 = a_mask_sub_3_1 \| _a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_eq_8 = a_mask_sub_4_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_8 = a_mask_size & a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_8 = a_mask_sub_4_1 \| _a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_eq_9 = a_mask_sub_4_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_9 = a_mask_size & a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_9 = a_mask_sub_4_1 \| _a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_eq_10 = a_mask_sub_5_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_10 = a_mask_size & a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_10 = a_mask_sub_5_1 \| _a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_eq_11 = a_mask_sub_5_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_11 = a_mask_size & a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_11 = a_mask_sub_5_1 \| _a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_eq_12 = a_mask_sub_6_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_12 = a_mask_size & a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_12 = a_mask_sub_6_1 \| _a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_eq_13 = a_mask_sub_6_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_13 = a_mask_size & a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_13 = a_mask_sub_6_1 \| _a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_eq_14 = a_mask_sub_7_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_14 = a_mask_size & a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_14 = a_mask_sub_7_1 \| _a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_eq_15 = a_mask_sub_7_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_15 = a_mask_size & a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_15 = a_mask_sub_7_1 \| _a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_eq_16 = a_mask_sub_8_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_16 = a_mask_size & a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_16 = a_mask_sub_8_1 \| _a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire a_mask_eq_17 = a_mask_sub_8_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_17 = a_mask_size & a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_17 = a_mask_sub_8_1 \| _a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire a_mask_eq_18 = a_mask_sub_9_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_18 = a_mask_size & a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_18 = a_mask_sub_9_1 \| _a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire a_mask_eq_19 = a_mask_sub_9_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_19 = a_mask_size & a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_19 = a_mask_sub_9_1 \| _a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire a_mask_eq_20 = a_mask_sub_10_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_20 = a_mask_size & a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_20 = a_mask_sub_10_1 \| _a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire a_mask_eq_21 = a_mask_sub_10_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_21 = a_mask_size & a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_21 = a_mask_sub_10_1 \| _a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire a_mask_eq_22 = a_mask_sub_11_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_22 = a_mask_size & a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_22 = a_mask_sub_11_1 \| _a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire a_mask_eq_23 = a_mask_sub_11_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_23 = a_mask_size & a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_23 = a_mask_sub_11_1 \| _a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire a_mask_eq_24 = a_mask_sub_12_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_24 = a_mask_size & a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_24 = a_mask_sub_12_1 \| _a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire a_mask_eq_25 = a_mask_sub_12_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_25 = a_mask_size & a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_25 = a_mask_sub_12_1 \| _a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire a_mask_eq_26 = a_mask_sub_13_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_26 = a_mask_size & a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_26 = a_mask_sub_13_1 \| _a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire a_mask_eq_27 = a_mask_sub_13_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_27 = a_mask_size & a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_27 = a_mask_sub_13_1 \| _a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire a_mask_eq_28 = a_mask_sub_14_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_28 = a_mask_size & a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_28 = a_mask_sub_14_1 \| _a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire a_mask_eq_29 = a_mask_sub_14_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_29 = a_mask_size & a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_29 = a_mask_sub_14_1 \| _a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire a_mask_eq_30 = a_mask_sub_15_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_30 = a_mask_size & a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_30 = a_mask_sub_15_1 \| _a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire a_mask_eq_31 = a_mask_sub_15_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_31 = a_mask_size & a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_31 = a_mask_sub_15_1 \| _a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] a_mask_lo_lo_lo_lo = {a_mask_acc_1, a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_lo_hi = {a_mask_acc_3, a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_lo = {a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo = {a_mask_acc_5, a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_hi_hi = {a_mask_acc_7, a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_hi = {a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo = {a_mask_lo_lo_hi, a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo = {a_mask_acc_9, a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_lo_hi = {a_mask_acc_11, a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_lo = {a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo = {a_mask_acc_13, a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_hi_hi = {a_mask_acc_15, a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_hi = {a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi = {a_mask_lo_hi_hi, a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] a_mask_lo = {a_mask_lo_hi, a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo = {a_mask_acc_17, a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_lo_hi = {a_mask_acc_19, a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_lo = {a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo = {a_mask_acc_21, a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_hi_hi = {a_mask_acc_23, a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_hi = {a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo = {a_mask_hi_lo_hi, a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo = {a_mask_acc_25, a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_lo_hi = {a_mask_acc_27, a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_lo = {a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo = {a_mask_acc_29, a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_hi_hi = {a_mask_acc_31, a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_hi = {a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi = {a_mask_hi_hi_hi, a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] a_mask_hi = {a_mask_hi_hi, a_mask_hi_lo}; // @[Misc.scala:222:10] assign _a_mask_T = {a_mask_hi, a_mask_lo}; // @[Misc.scala:222:10] assign bundle_mask = _a_mask_T; // @[Misc.scala:222:10] wire [510:0] _T_31 = {255'h0, request_input_bits_data} << {503'h0, request_input_bits_addr[4:0], 3'h0}; // @[L2MemHelperLatencyInjection.scala:44:27, :172:{58,86}] wire [32:0] _legal_T_68 = {1'h0, _legal_T_67}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_69 = _legal_T_68 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_70 = _legal_T_69; // @[Parameters.scala:137:46] wire _legal_T_71 = _legal_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_72 = _legal_T_71; // @[Parameters.scala:684:54] wire _legal_T_132 = _legal_T_72; // @[Parameters.scala:684:54, :686:26] wire _legal_T_75 = _legal_T_74; // @[Parameters.scala:92:{33,38}] wire _legal_T_76 = _legal_T_75; // @[Parameters.scala:684:29] wire [31:0] _legal_T_77; // @[Parameters.scala:137:31] wire [32:0] _legal_T_78 = {1'h0, _legal_T_77}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_79 = _legal_T_78 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_80 = _legal_T_79; // @[Parameters.scala:137:46] wire _legal_T_81 = _legal_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_82 = {_tlb_io_resp_paddr[31:21], _tlb_io_resp_paddr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_83 = {1'h0, _legal_T_82}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_84 = _legal_T_83 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_85 = _legal_T_84; // @[Parameters.scala:137:46] wire _legal_T_86 = _legal_T_85 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_88 = {1'h0, _legal_T_87}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_89 = _legal_T_88 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_90 = _legal_T_89; // @[Parameters.scala:137:46] wire _legal_T_91 = _legal_T_90 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_92 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_93 = {1'h0, _legal_T_92}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_94 = _legal_T_93 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_95 = _legal_T_94; // @[Parameters.scala:137:46] wire _legal_T_96 = _legal_T_95 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_98 = {1'h0, _legal_T_97}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_99 = _legal_T_98 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_100 = _legal_T_99; // @[Parameters.scala:137:46] wire _legal_T_101 = _legal_T_100 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_103 = {1'h0, _legal_T_102}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_104 = _legal_T_103 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_105 = _legal_T_104; // @[Parameters.scala:137:46] wire _legal_T_106 = _legal_T_105 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_108 = {1'h0, _legal_T_107}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_109 = _legal_T_108 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_110 = _legal_T_109; // @[Parameters.scala:137:46] wire _legal_T_111 = _legal_T_110 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_113 = {1'h0, _legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_114 = _legal_T_113 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_115 = _legal_T_114; // @[Parameters.scala:137:46] wire _legal_T_116 = _legal_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_117 = _legal_T_81 \| _legal_T_86; // @[Parameters.scala:685:42] wire _legal_T_118 = _legal_T_117 \| _legal_T_91; // @[Parameters.scala:685:42] wire _legal_T_119 = _legal_T_118 \| _legal_T_96; // @[Parameters.scala:685:42] wire _legal_T_120 = _legal_T_119 \| _legal_T_101; // @[Parameters.scala:685:42] wire _legal_T_121 = _legal_T_120 \| _legal_T_106; // @[Parameters.scala:685:42] wire _legal_T_122 = _legal_T_121 \| _legal_T_111; // @[Parameters.scala:685:42] wire _legal_T_123 = _legal_T_122 \| _legal_T_116; // @[Parameters.scala:685:42] wire _legal_T_124 = _legal_T_76 & _legal_T_123; // @[Parameters.scala:684:{29,54}, :685:42] wire [32:0] _legal_T_127 = {1'h0, _legal_T_126}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_128 = _legal_T_127 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_129 = _legal_T_128; // @[Parameters.scala:137:46] wire _legal_T_130 = _legal_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_133 = _legal_T_132 \| _legal_T_124; // @[Parameters.scala:684:54, :686:26] wire legal_1 = _legal_T_133; // @[Parameters.scala:686:26] wire [31:0] _a_mask_T_1; // @[Misc.scala:222:10] wire [1:0] bundle_1_source; // @[Edges.scala:480:17] wire [31:0] bundle_1_address; // @[Edges.scala:480:17] wire [31:0] bundle_1_mask; // @[Edges.scala:480:17] wire [255:0] bundle_1_data; // @[Edges.scala:480:17] wire [4:0] _a_mask_sizeOH_shiftAmount_T_1 = _a_mask_sizeOH_T_3; // @[OneHot.scala:64:31] wire [2:0] a_mask_sizeOH_shiftAmount_1 = _a_mask_sizeOH_shiftAmount_T_1[2:0]; // @[OneHot.scala:64:{31,49}] wire [7:0] _a_mask_sizeOH_T_4 = 8'h1 << a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [4:0] _a_mask_sizeOH_T_5 = _a_mask_sizeOH_T_4[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] a_mask_sizeOH_1 = {_a_mask_sizeOH_T_5[4:1], 1'h1}; // @[OneHot.scala:65:27] wire a_mask_sub_sub_sub_sub_size_1 = a_mask_sizeOH_1[4]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _a_mask_sub_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire a_mask_sub_sub_sub_size_1 = a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_4 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_5 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_2_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_6 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_2_1_1 = a_mask_sub_sub_sub_sub_1_1_1 \| _a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_3_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_7 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_3_1_1 = a_mask_sub_sub_sub_sub_1_1_1 \| _a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_size_1 = a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_nbit_1 = ~a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_8 = a_mask_sub_sub_size_1 & a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_0_1_1 = a_mask_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_1_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_9 = a_mask_sub_sub_size_1 & a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_1_1_1 = a_mask_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_2_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_10 = a_mask_sub_sub_size_1 & a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_2_1_1 = a_mask_sub_sub_sub_1_1_1 \| _a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_3_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_11 = a_mask_sub_sub_size_1 & a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_3_1_1 = a_mask_sub_sub_sub_1_1_1 \| _a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_4_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_12 = a_mask_sub_sub_size_1 & a_mask_sub_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_4_1_1 = a_mask_sub_sub_sub_2_1_1 \| _a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_5_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_13 = a_mask_sub_sub_size_1 & a_mask_sub_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_5_1_1 = a_mask_sub_sub_sub_2_1_1 \| _a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_6_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_14 = a_mask_sub_sub_size_1 & a_mask_sub_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_6_1_1 = a_mask_sub_sub_sub_3_1_1 \| _a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_7_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_15 = a_mask_sub_sub_size_1 & a_mask_sub_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_7_1_1 = a_mask_sub_sub_sub_3_1_1 \| _a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_sub_size_1 = a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_16 = a_mask_sub_size_1 & a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_0_1_1 = a_mask_sub_sub_0_1_1 \| _a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire a_mask_sub_1_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_17 = a_mask_sub_size_1 & a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_1_1_1 = a_mask_sub_sub_0_1_1 \| _a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire a_mask_sub_2_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_18 = a_mask_sub_size_1 & a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_2_1_1 = a_mask_sub_sub_1_1_1 \| _a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire a_mask_sub_3_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_19 = a_mask_sub_size_1 & a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_3_1_1 = a_mask_sub_sub_1_1_1 \| _a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire a_mask_sub_4_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_20 = a_mask_sub_size_1 & a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_4_1_1 = a_mask_sub_sub_2_1_1 \| _a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire a_mask_sub_5_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_21 = a_mask_sub_size_1 & a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_5_1_1 = a_mask_sub_sub_2_1_1 \| _a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire a_mask_sub_6_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_22 = a_mask_sub_size_1 & a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_6_1_1 = a_mask_sub_sub_3_1_1 \| _a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire a_mask_sub_7_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_23 = a_mask_sub_size_1 & a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_7_1_1 = a_mask_sub_sub_3_1_1 \| _a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire a_mask_sub_8_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_24 = a_mask_sub_size_1 & a_mask_sub_8_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_8_1_1 = a_mask_sub_sub_4_1_1 \| _a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire a_mask_sub_9_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_25 = a_mask_sub_size_1 & a_mask_sub_9_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_9_1_1 = a_mask_sub_sub_4_1_1 \| _a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire a_mask_sub_10_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_26 = a_mask_sub_size_1 & a_mask_sub_10_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_10_1_1 = a_mask_sub_sub_5_1_1 \| _a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire a_mask_sub_11_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_27 = a_mask_sub_size_1 & a_mask_sub_11_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_11_1_1 = a_mask_sub_sub_5_1_1 \| _a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire a_mask_sub_12_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_28 = a_mask_sub_size_1 & a_mask_sub_12_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_12_1_1 = a_mask_sub_sub_6_1_1 \| _a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire a_mask_sub_13_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_29 = a_mask_sub_size_1 & a_mask_sub_13_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_13_1_1 = a_mask_sub_sub_6_1_1 \| _a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire a_mask_sub_14_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_30 = a_mask_sub_size_1 & a_mask_sub_14_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_14_1_1 = a_mask_sub_sub_7_1_1 \| _a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire a_mask_sub_15_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_31 = a_mask_sub_size_1 & a_mask_sub_15_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_15_1_1 = a_mask_sub_sub_7_1_1 \| _a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire a_mask_size_1 = a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_eq_32 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_32 = a_mask_size_1 & a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_32 = a_mask_sub_0_1_1 \| _a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire a_mask_eq_33 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_33 = a_mask_size_1 & a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_33 = a_mask_sub_0_1_1 \| _a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire a_mask_eq_34 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_34 = a_mask_size_1 & a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_34 = a_mask_sub_1_1_1 \| _a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire a_mask_eq_35 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_35 = a_mask_size_1 & a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_35 = a_mask_sub_1_1_1 \| _a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire a_mask_eq_36 = a_mask_sub_2_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_36 = a_mask_size_1 & a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_36 = a_mask_sub_2_1_1 \| _a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire a_mask_eq_37 = a_mask_sub_2_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_37 = a_mask_size_1 & a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_37 = a_mask_sub_2_1_1 \| _a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire a_mask_eq_38 = a_mask_sub_3_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_38 = a_mask_size_1 & a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_38 = a_mask_sub_3_1_1 \| _a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire a_mask_eq_39 = a_mask_sub_3_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_39 = a_mask_size_1 & a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_39 = a_mask_sub_3_1_1 \| _a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire a_mask_eq_40 = a_mask_sub_4_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_40 = a_mask_size_1 & a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_40 = a_mask_sub_4_1_1 \| _a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire a_mask_eq_41 = a_mask_sub_4_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_41 = a_mask_size_1 & a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_41 = a_mask_sub_4_1_1 \| _a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire a_mask_eq_42 = a_mask_sub_5_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_42 = a_mask_size_1 & a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_42 = a_mask_sub_5_1_1 \| _a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire a_mask_eq_43 = a_mask_sub_5_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_43 = a_mask_size_1 & a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_43 = a_mask_sub_5_1_1 \| _a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire a_mask_eq_44 = a_mask_sub_6_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_44 = a_mask_size_1 & a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_44 = a_mask_sub_6_1_1 \| _a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire a_mask_eq_45 = a_mask_sub_6_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_45 = a_mask_size_1 & a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_45 = a_mask_sub_6_1_1 \| _a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire a_mask_eq_46 = a_mask_sub_7_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_46 = a_mask_size_1 & a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_46 = a_mask_sub_7_1_1 \| _a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire a_mask_eq_47 = a_mask_sub_7_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_47 = a_mask_size_1 & a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_47 = a_mask_sub_7_1_1 \| _a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire a_mask_eq_48 = a_mask_sub_8_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_48 = a_mask_size_1 & a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_48 = a_mask_sub_8_1_1 \| _a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire a_mask_eq_49 = a_mask_sub_8_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_49 = a_mask_size_1 & a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_49 = a_mask_sub_8_1_1 \| _a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire a_mask_eq_50 = a_mask_sub_9_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_50 = a_mask_size_1 & a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_50 = a_mask_sub_9_1_1 \| _a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire a_mask_eq_51 = a_mask_sub_9_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_51 = a_mask_size_1 & a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_51 = a_mask_sub_9_1_1 \| _a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire a_mask_eq_52 = a_mask_sub_10_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_52 = a_mask_size_1 & a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_52 = a_mask_sub_10_1_1 \| _a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire a_mask_eq_53 = a_mask_sub_10_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_53 = a_mask_size_1 & a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_53 = a_mask_sub_10_1_1 \| _a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire a_mask_eq_54 = a_mask_sub_11_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_54 = a_mask_size_1 & a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_54 = a_mask_sub_11_1_1 \| _a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire a_mask_eq_55 = a_mask_sub_11_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_55 = a_mask_size_1 & a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_55 = a_mask_sub_11_1_1 \| _a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire a_mask_eq_56 = a_mask_sub_12_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_56 = a_mask_size_1 & a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_56 = a_mask_sub_12_1_1 \| _a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire a_mask_eq_57 = a_mask_sub_12_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_57 = a_mask_size_1 & a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_57 = a_mask_sub_12_1_1 \| _a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire a_mask_eq_58 = a_mask_sub_13_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_58 = a_mask_size_1 & a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_58 = a_mask_sub_13_1_1 \| _a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire a_mask_eq_59 = a_mask_sub_13_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_59 = a_mask_size_1 & a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_59 = a_mask_sub_13_1_1 \| _a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire a_mask_eq_60 = a_mask_sub_14_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_60 = a_mask_size_1 & a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_60 = a_mask_sub_14_1_1 \| _a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire a_mask_eq_61 = a_mask_sub_14_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_61 = a_mask_size_1 & a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_61 = a_mask_sub_14_1_1 \| _a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire a_mask_eq_62 = a_mask_sub_15_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_62 = a_mask_size_1 & a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_62 = a_mask_sub_15_1_1 \| _a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire a_mask_eq_63 = a_mask_sub_15_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_63 = a_mask_size_1 & a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_63 = a_mask_sub_15_1_1 \| _a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] a_mask_lo_lo_lo_lo_1 = {a_mask_acc_33, a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_lo_hi_1 = {a_mask_acc_35, a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_lo_1 = {a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo_1 = {a_mask_acc_37, a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_hi_hi_1 = {a_mask_acc_39, a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_hi_1 = {a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo_1 = {a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo_1 = {a_mask_acc_41, a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_lo_hi_1 = {a_mask_acc_43, a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_lo_1 = {a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo_1 = {a_mask_acc_45, a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_hi_hi_1 = {a_mask_acc_47, a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_hi_1 = {a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi_1 = {a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] a_mask_lo_1 = {a_mask_lo_hi_1, a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo_1 = {a_mask_acc_49, a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_lo_hi_1 = {a_mask_acc_51, a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_lo_1 = {a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo_1 = {a_mask_acc_53, a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_hi_hi_1 = {a_mask_acc_55, a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_hi_1 = {a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo_1 = {a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo_1 = {a_mask_acc_57, a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_lo_hi_1 = {a_mask_acc_59, a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_lo_1 = {a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo_1 = {a_mask_acc_61, a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_hi_hi_1 = {a_mask_acc_63, a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_hi_1 = {a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi_1 = {a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] a_mask_hi_1 = {a_mask_hi_hi_1, a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _a_mask_T_1 = {a_mask_hi_1, a_mask_lo_1}; // @[Misc.scala:222:10] assign bundle_1_mask = _a_mask_T_1; // @[Misc.scala:222:10] assign bundle_1_data = _T_31[255:0]; // @[Edges.scala:480:17, :489:15] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] wire _current_request_tag_has_response_space_T = _tags_for_issue_Q_io_deq_bits == 2'h0; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_1 = _Queue4_L2RespInternal_io_enq_ready & _current_request_tag_has_response_space_T; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_2 = _tags_for_issue_Q_io_deq_bits == 2'h1; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _current_request_tag_has_response_space_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_4 = _tags_for_issue_Q_io_deq_bits == 2'h2; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _current_request_tag_has_response_space_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_6 = &_tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _current_request_tag_has_response_space_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_8 = _current_request_tag_has_response_space_T_1 \| _current_request_tag_has_response_space_T_3; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_9 = _current_request_tag_has_response_space_T_8 \| _current_request_tag_has_response_space_T_5; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire current_request_tag_has_response_space = _current_request_tag_has_response_space_T_9 \| _current_request_tag_has_response_space_T_7; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire [63:0] _outstanding_req_addr_io_enq_bits_addrindex_T = {59'h0, request_input_bits_addr[4:0]}; // @[L2MemHelperLatencyInjection.scala:44:27, :200:73] wire _request_latency_injection_q_io_enq_valid_T = request_input_valid & tlb_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_1 = _request_latency_injection_q_io_enq_valid_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_2 = _request_latency_injection_q_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_3 = _request_latency_injection_q_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_4 = _request_latency_injection_q_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _request_input_ready_T = _request_latency_injection_q_io_enq_ready & tlb_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_1 = _request_input_ready_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_2 = _request_input_ready_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_input_ready_T_3 = _request_input_ready_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] assign _request_input_ready_T_4 = _request_input_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] assign request_input_ready = _request_input_ready_T_4; // @[Misc.scala:26:53] wire _T_45 = request_input_valid & _request_latency_injection_q_io_enq_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T; // @[Misc.scala:26:53] assign _outstanding_req_addr_io_enq_valid_T = _T_45; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T; // @[Misc.scala:26:53] assign _tags_for_issue_Q_io_deq_ready_T = _T_45; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_1 = _outstanding_req_addr_io_enq_valid_T & tlb_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_2 = _outstanding_req_addr_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_3 = _outstanding_req_addr_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_4 = _outstanding_req_addr_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_1 = _tags_for_issue_Q_io_deq_ready_T & tlb_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_2 = _tags_for_issue_Q_io_deq_ready_T_1 & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_3 = _tags_for_issue_Q_io_deq_ready_T_2 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_4 = _tags_for_issue_Q_io_deq_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:26:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:26:33, :27:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:27:38] wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49] wire _printf_T_3 = ~_printf_T_2; // @[annotations.scala:102:49] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] wire _selectQready_T = _response_latency_injection_q_io_deq_bits_source == 2'h0; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_1 = _Queue4_L2RespInternal_io_enq_ready & _selectQready_T; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_2 = _response_latency_injection_q_io_deq_bits_source == 2'h1; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _selectQready_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_4 = _response_latency_injection_q_io_deq_bits_source == 2'h2; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _selectQready_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_6 = &_response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _selectQready_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_8 = _selectQready_T_1 \| _selectQready_T_3; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_9 = _selectQready_T_8 \| _selectQready_T_5; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire selectQready = _selectQready_T_9 \| _selectQready_T_7; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _T_377 = selectQready & _response_latency_injection_q_io_deq_valid; // @[Misc.scala:26:53] wire tags_for_issue_Q_io_enq_valid = _T_377 \| _T_4; // @[Misc.scala:26:53] wire [1:0] tags_for_issue_Q_io_enq_bits = _T_377 ? _response_latency_injection_q_io_deq_bits_source : tags_init_reg[1:0]; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] wire _response_latency_injection_q_io_deq_ready_T = selectQready & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_392 = _response_latency_injection_q_io_deq_valid & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_396 = _outstanding_req_addr_io_deq_bits_tag == 2'h0; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T = _T_396; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q = _T_396; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_1 = _Queue4_L2RespInternal_io_deq_valid & _queueValid_T; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_399 = _outstanding_req_addr_io_deq_bits_tag == 2'h1; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_2 = _T_399; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_1; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_1 = _T_399; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_3 = _Queue4_L2RespInternal_1_io_deq_valid & _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_402 = _outstanding_req_addr_io_deq_bits_tag == 2'h2; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_4 = _T_402; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_2; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_2 = _T_402; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_5 = _Queue4_L2RespInternal_2_io_deq_valid & _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_6 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_7 = _Queue4_L2RespInternal_3_io_deq_valid & _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_8 = _queueValid_T_1 \| _queueValid_T_3; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_9 = _queueValid_T_8 \| _queueValid_T_5; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire queueValid = _queueValid_T_9 \| _queueValid_T_7; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire [255:0] resultdata_data; // @[L2MemHelperLatencyInjection.scala:300:20] wire [7:0] _GEN_12 = {_outstanding_req_addr_io_deq_bits_addrindex, 3'h0}; // @[L2MemHelperLatencyInjection.scala:91:36, :302:78] wire [7:0] _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_2 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_4 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_6 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [255:0] _resultdata_data_T_1 = _Queue4_L2RespInternal_io_deq_bits_data >> _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data = resultdata_is_current_q ? _resultdata_data_T_1 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_3 = _Queue4_L2RespInternal_1_io_deq_bits_data >> _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_1 = resultdata_is_current_q_1 ? _resultdata_data_T_3 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_5 = _Queue4_L2RespInternal_2_io_deq_bits_data >> _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_2 = resultdata_is_current_q_2 ? _resultdata_data_T_5 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire resultdata_is_current_q_3 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27, :299:31] wire [255:0] resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_7 = _Queue4_L2RespInternal_3_io_deq_bits_data >> _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_3 = resultdata_is_current_q_3 ? _resultdata_data_T_7 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] _resultdata_T = resultdata_data \| resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_1 = _resultdata_T \| resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign resultdata = _resultdata_T_1 \| resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign response_output_bits_data = resultdata; // @[L2MemHelperLatencyInjection.scala:53:29, :307:15] assign _response_output_valid_T = queueValid & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] assign response_output_valid = _response_output_valid_T; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_deq_ready_T = queueValid & response_output_ready; // @[Misc.scala:26:53] wire _T_404 = response_output_ready & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] wire opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] wire _T_422 = response_output_ready & response_output_valid; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_1 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h1)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = and(_T_11, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_24 : node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_30 = or(_T_28, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_35 = cvt(_T_34) node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000))) node _T_37 = asSInt(_T_36) node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0))) node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_40 = cvt(_T_39) node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000))) node _T_42 = asSInt(_T_41) node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0))) node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<18>(0h2f000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<27>(0h4000000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<13>(0h1000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<30>(0h20000000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<15>(0h4000))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_38, _T_43) node _T_80 = or(_T_79, _T_48) node _T_81 = or(_T_80, _T_53) node _T_82 = or(_T_81, _T_58) node _T_83 = or(_T_82, _T_63) node _T_84 = or(_T_83, _T_68) node _T_85 = or(_T_84, _T_73) node _T_86 = or(_T_85, _T_78) node _T_87 = and(_T_33, _T_86) node _T_88 = or(UInt<1>(0h0), _T_87) node _T_89 = and(_T_32, _T_88) node _T_90 = asUInt(reset) node _T_91 = eq(_T_90, UInt<1>(0h0)) when _T_91 : node _T_92 = eq(_T_89, UInt<1>(0h0)) when _T_92 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_89, UInt<1>(0h1), "") : assert_2 node _T_93 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_94 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_95 = and(_T_93, _T_94) node _T_96 = or(UInt<1>(0h0), _T_95) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<14>(0h2000))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_103 = cvt(_T_102) node _T_104 = and(_T_103, asSInt(UInt<13>(0h1000))) node _T_105 = asSInt(_T_104) node _T_106 = eq(_T_105, asSInt(UInt<1>(0h0))) node _T_107 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<18>(0h2f000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<17>(0h10000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<27>(0h4000000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<13>(0h1000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<30>(0h20000000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<15>(0h4000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = or(_T_101, _T_106) node _T_143 = or(_T_142, _T_111) node _T_144 = or(_T_143, _T_116) node _T_145 = or(_T_144, _T_121) node _T_146 = or(_T_145, _T_126) node _T_147 = or(_T_146, _T_131) node _T_148 = or(_T_147, _T_136) node _T_149 = or(_T_148, _T_141) node _T_150 = and(_T_96, _T_149) node _T_151 = or(UInt<1>(0h0), _T_150) node _T_152 = and(UInt<1>(0h0), _T_151) node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_T_152, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_152, UInt<1>(0h1), "") : assert_3 node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(source_ok, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_159 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_159, UInt<1>(0h1), "") : assert_5 node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(is_aligned, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_166 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_166, UInt<1>(0h1), "") : assert_7 node _T_170 = not(io.in.a.bits.mask) node _T_171 = eq(_T_170, UInt<1>(0h0)) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_171, UInt<1>(0h1), "") : assert_8 node _T_175 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_175, UInt<1>(0h1), "") : assert_9 node _T_179 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_179 : node _T_180 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_181 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_184 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_185 = or(_T_183, _T_184) node _T_186 = and(_T_182, _T_185) node _T_187 = or(UInt<1>(0h0), _T_186) node _T_188 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_189 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<14>(0h2000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<13>(0h1000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h10000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<18>(0h2f000))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<17>(0h10000))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_215 = cvt(_T_214) node _T_216 = and(_T_215, asSInt(UInt<27>(0h4000000))) node _T_217 = asSInt(_T_216) node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0))) node _T_219 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_220 = cvt(_T_219) node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000))) node _T_222 = asSInt(_T_221) node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0))) node _T_224 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_225 = cvt(_T_224) node _T_226 = and(_T_225, asSInt(UInt<30>(0h20000000))) node _T_227 = asSInt(_T_226) node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_230 = cvt(_T_229) node _T_231 = and(_T_230, asSInt(UInt<15>(0h4000))) node _T_232 = asSInt(_T_231) node _T_233 = eq(_T_232, asSInt(UInt<1>(0h0))) node _T_234 = or(_T_193, _T_198) node _T_235 = or(_T_234, _T_203) node _T_236 = or(_T_235, _T_208) node _T_237 = or(_T_236, _T_213) node _T_238 = or(_T_237, _T_218) node _T_239 = or(_T_238, _T_223) node _T_240 = or(_T_239, _T_228) node _T_241 = or(_T_240, _T_233) node _T_242 = and(_T_188, _T_241) node _T_243 = or(UInt<1>(0h0), _T_242) node _T_244 = and(_T_187, _T_243) node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(_T_244, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_244, UInt<1>(0h1), "") : assert_10 node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<14>(0h2000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_258 = cvt(_T_257) node _T_259 = and(_T_258, asSInt(UInt<13>(0h1000))) node _T_260 = asSInt(_T_259) node _T_261 = eq(_T_260, asSInt(UInt<1>(0h0))) node _T_262 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_263 = cvt(_T_262) node _T_264 = and(_T_263, asSInt(UInt<17>(0h10000))) node _T_265 = asSInt(_T_264) node _T_266 = eq(_T_265, asSInt(UInt<1>(0h0))) node _T_267 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_268 = cvt(_T_267) node _T_269 = and(_T_268, asSInt(UInt<18>(0h2f000))) node _T_270 = asSInt(_T_269) node _T_271 = eq(_T_270, asSInt(UInt<1>(0h0))) node _T_272 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_273 = cvt(_T_272) node _T_274 = and(_T_273, asSInt(UInt<17>(0h10000))) node _T_275 = asSInt(_T_274) node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<27>(0h4000000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<13>(0h1000))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_288 = cvt(_T_287) node _T_289 = and(_T_288, asSInt(UInt<30>(0h20000000))) node _T_290 = asSInt(_T_289) node _T_291 = eq(_T_290, asSInt(UInt<1>(0h0))) node _T_292 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<15>(0h4000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = or(_T_256, _T_261) node _T_298 = or(_T_297, _T_266) node _T_299 = or(_T_298, _T_271) node _T_300 = or(_T_299, _T_276) node _T_301 = or(_T_300, _T_281) node _T_302 = or(_T_301, _T_286) node _T_303 = or(_T_302, _T_291) node _T_304 = or(_T_303, _T_296) node _T_305 = and(_T_251, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = and(UInt<1>(0h0), _T_306) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_307, UInt<1>(0h1), "") : assert_11 node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(source_ok, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_314 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(_T_314, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_314, UInt<1>(0h1), "") : assert_13 node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(is_aligned, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_321 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_322 = asUInt(reset) node _T_323 = eq(_T_322, UInt<1>(0h0)) when _T_323 : node _T_324 = eq(_T_321, UInt<1>(0h0)) when _T_324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_321, UInt<1>(0h1), "") : assert_15 node _T_325 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_325, UInt<1>(0h1), "") : assert_16 node _T_329 = not(io.in.a.bits.mask) node _T_330 = eq(_T_329, UInt<1>(0h0)) node _T_331 = asUInt(reset) node _T_332 = eq(_T_331, UInt<1>(0h0)) when _T_332 : node _T_333 = eq(_T_330, UInt<1>(0h0)) when _T_333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_330, UInt<1>(0h1), "") : assert_17 node _T_334 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_T_334, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_334, UInt<1>(0h1), "") : assert_18 node _T_338 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_338 : node _T_339 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_340 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_341 = and(_T_339, _T_340) node _T_342 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_343 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_344 = or(_T_342, _T_343) node _T_345 = and(_T_341, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_346, UInt<1>(0h1), "") : assert_19 node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_352 = and(_T_350, _T_351) node _T_353 = or(UInt<1>(0h0), _T_352) node _T_354 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<13>(0h1000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = and(_T_353, _T_358) node _T_360 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_361 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_362 = and(_T_360, _T_361) node _T_363 = or(UInt<1>(0h0), _T_362) node _T_364 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_365 = cvt(_T_364) node _T_366 = and(_T_365, asSInt(UInt<14>(0h2000))) node _T_367 = asSInt(_T_366) node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0))) node _T_369 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<17>(0h10000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_375 = cvt(_T_374) node _T_376 = and(_T_375, asSInt(UInt<18>(0h2f000))) node _T_377 = asSInt(_T_376) node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0))) node _T_379 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<17>(0h10000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<27>(0h4000000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<30>(0h20000000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<15>(0h4000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = or(_T_368, _T_373) node _T_405 = or(_T_404, _T_378) node _T_406 = or(_T_405, _T_383) node _T_407 = or(_T_406, _T_388) node _T_408 = or(_T_407, _T_393) node _T_409 = or(_T_408, _T_398) node _T_410 = or(_T_409, _T_403) node _T_411 = and(_T_363, _T_410) node _T_412 = or(UInt<1>(0h0), _T_359) node _T_413 = or(_T_412, _T_411) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_413, UInt<1>(0h1), "") : assert_20 node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(source_ok, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(is_aligned, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_423 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_424 = asUInt(reset) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(_T_423, UInt<1>(0h0)) when _T_426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_423, UInt<1>(0h1), "") : assert_23 node _T_427 = eq(io.in.a.bits.mask, mask) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_427, UInt<1>(0h1), "") : assert_24 node _T_431 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_431, UInt<1>(0h1), "") : assert_25 node _T_435 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_435 : node _T_436 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_437 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_440 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_441 = or(_T_439, _T_440) node _T_442 = and(_T_438, _T_441) node _T_443 = or(UInt<1>(0h0), _T_442) node _T_444 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_445 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_446 = and(_T_444, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<13>(0h1000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = and(_T_447, _T_452) node _T_454 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_455 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_456 = and(_T_454, _T_455) node _T_457 = or(UInt<1>(0h0), _T_456) node _T_458 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_459 = cvt(_T_458) node _T_460 = and(_T_459, asSInt(UInt<14>(0h2000))) node _T_461 = asSInt(_T_460) node _T_462 = eq(_T_461, asSInt(UInt<1>(0h0))) node _T_463 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_464 = cvt(_T_463) node _T_465 = and(_T_464, asSInt(UInt<18>(0h2f000))) node _T_466 = asSInt(_T_465) node _T_467 = eq(_T_466, asSInt(UInt<1>(0h0))) node _T_468 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_469 = cvt(_T_468) node _T_470 = and(_T_469, asSInt(UInt<17>(0h10000))) node _T_471 = asSInt(_T_470) node _T_472 = eq(_T_471, asSInt(UInt<1>(0h0))) node _T_473 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_474 = cvt(_T_473) node _T_475 = and(_T_474, asSInt(UInt<27>(0h4000000))) node _T_476 = asSInt(_T_475) node _T_477 = eq(_T_476, asSInt(UInt<1>(0h0))) node _T_478 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_479 = cvt(_T_478) node _T_480 = and(_T_479, asSInt(UInt<13>(0h1000))) node _T_481 = asSInt(_T_480) node _T_482 = eq(_T_481, asSInt(UInt<1>(0h0))) node _T_483 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_484 = cvt(_T_483) node _T_485 = and(_T_484, asSInt(UInt<15>(0h4000))) node _T_486 = asSInt(_T_485) node _T_487 = eq(_T_486, asSInt(UInt<1>(0h0))) node _T_488 = or(_T_462, _T_467) node _T_489 = or(_T_488, _T_472) node _T_490 = or(_T_489, _T_477) node _T_491 = or(_T_490, _T_482) node _T_492 = or(_T_491, _T_487) node _T_493 = and(_T_457, _T_492) node _T_494 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_495 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_496 = cvt(_T_495) node _T_497 = and(_T_496, asSInt(UInt<17>(0h10000))) node _T_498 = asSInt(_T_497) node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0))) node _T_500 = and(_T_494, _T_499) node _T_501 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_502 = leq(io.in.a.bits.size, UInt<4>(0h8)) node _T_503 = and(_T_501, _T_502) node _T_504 = or(UInt<1>(0h0), _T_503) node _T_505 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_506 = cvt(_T_505) node _T_507 = and(_T_506, asSInt(UInt<30>(0h20000000))) node _T_508 = asSInt(_T_507) node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0))) node _T_510 = and(_T_504, _T_509) node _T_511 = or(UInt<1>(0h0), _T_453) node _T_512 = or(_T_511, _T_493) node _T_513 = or(_T_512, _T_500) node _T_514 = or(_T_513, _T_510) node _T_515 = and(_T_443, _T_514) node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(_T_515, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_515, UInt<1>(0h1), "") : assert_26 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(source_ok, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(is_aligned, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_525 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_526 = asUInt(reset) node _T_527 = eq(_T_526, UInt<1>(0h0)) when _T_527 : node _T_528 = eq(_T_525, UInt<1>(0h0)) when _T_528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_525, UInt<1>(0h1), "") : assert_29 node _T_529 = eq(io.in.a.bits.mask, mask) node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(_T_529, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_529, UInt<1>(0h1), "") : assert_30 node _T_533 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_533 : node _T_534 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_535 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_536 = and(_T_534, _T_535) node _T_537 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_538 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_539 = or(_T_537, _T_538) node _T_540 = and(_T_536, _T_539) node _T_541 = or(UInt<1>(0h0), _T_540) node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = or(UInt<1>(0h0), _T_544) node _T_546 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_547 = cvt(_T_546) node _T_548 = and(_T_547, asSInt(UInt<13>(0h1000))) node _T_549 = asSInt(_T_548) node _T_550 = eq(_T_549, asSInt(UInt<1>(0h0))) node _T_551 = and(_T_545, _T_550) node _T_552 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_553 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_554 = and(_T_552, _T_553) node _T_555 = or(UInt<1>(0h0), _T_554) node _T_556 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_557 = cvt(_T_556) node _T_558 = and(_T_557, asSInt(UInt<14>(0h2000))) node _T_559 = asSInt(_T_558) node _T_560 = eq(_T_559, asSInt(UInt<1>(0h0))) node _T_561 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<18>(0h2f000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_567 = cvt(_T_566) node _T_568 = and(_T_567, asSInt(UInt<17>(0h10000))) node _T_569 = asSInt(_T_568) node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0))) node _T_571 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<27>(0h4000000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<13>(0h1000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<15>(0h4000))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = or(_T_560, _T_565) node _T_587 = or(_T_586, _T_570) node _T_588 = or(_T_587, _T_575) node _T_589 = or(_T_588, _T_580) node _T_590 = or(_T_589, _T_585) node _T_591 = and(_T_555, _T_590) node _T_592 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_593 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_594 = cvt(_T_593) node _T_595 = and(_T_594, asSInt(UInt<17>(0h10000))) node _T_596 = asSInt(_T_595) node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0))) node _T_598 = and(_T_592, _T_597) node _T_599 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_600 = leq(io.in.a.bits.size, UInt<4>(0h8)) node _T_601 = and(_T_599, _T_600) node _T_602 = or(UInt<1>(0h0), _T_601) node _T_603 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_604 = cvt(_T_603) node _T_605 = and(_T_604, asSInt(UInt<30>(0h20000000))) node _T_606 = asSInt(_T_605) node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0))) node _T_608 = and(_T_602, _T_607) node _T_609 = or(UInt<1>(0h0), _T_551) node _T_610 = or(_T_609, _T_591) node _T_611 = or(_T_610, _T_598) node _T_612 = or(_T_611, _T_608) node _T_613 = and(_T_541, _T_612) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_613, UInt<1>(0h1), "") : assert_31 node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(source_ok, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(is_aligned, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_623 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_623, UInt<1>(0h1), "") : assert_34 node _T_627 = not(mask) node _T_628 = and(io.in.a.bits.mask, _T_627) node _T_629 = eq(_T_628, UInt<1>(0h0)) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_629, UInt<1>(0h1), "") : assert_35 node _T_633 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_633 : node _T_634 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_635 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_636 = and(_T_634, _T_635) node _T_637 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_638 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_639 = or(_T_637, _T_638) node _T_640 = and(_T_636, _T_639) node _T_641 = or(UInt<1>(0h0), _T_640) node _T_642 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_643 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_644 = and(_T_642, _T_643) node _T_645 = or(UInt<1>(0h0), _T_644) node _T_646 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<14>(0h2000))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_652 = cvt(_T_651) node _T_653 = and(_T_652, asSInt(UInt<13>(0h1000))) node _T_654 = asSInt(_T_653) node _T_655 = eq(_T_654, asSInt(UInt<1>(0h0))) node _T_656 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_657 = cvt(_T_656) node _T_658 = and(_T_657, asSInt(UInt<18>(0h2f000))) node _T_659 = asSInt(_T_658) node _T_660 = eq(_T_659, asSInt(UInt<1>(0h0))) node _T_661 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_662 = cvt(_T_661) node _T_663 = and(_T_662, asSInt(UInt<17>(0h10000))) node _T_664 = asSInt(_T_663) node _T_665 = eq(_T_664, asSInt(UInt<1>(0h0))) node _T_666 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_667 = cvt(_T_666) node _T_668 = and(_T_667, asSInt(UInt<27>(0h4000000))) node _T_669 = asSInt(_T_668) node _T_670 = eq(_T_669, asSInt(UInt<1>(0h0))) node _T_671 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_672 = cvt(_T_671) node _T_673 = and(_T_672, asSInt(UInt<13>(0h1000))) node _T_674 = asSInt(_T_673) node _T_675 = eq(_T_674, asSInt(UInt<1>(0h0))) node _T_676 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_677 = cvt(_T_676) node _T_678 = and(_T_677, asSInt(UInt<15>(0h4000))) node _T_679 = asSInt(_T_678) node _T_680 = eq(_T_679, asSInt(UInt<1>(0h0))) node _T_681 = or(_T_650, _T_655) node _T_682 = or(_T_681, _T_660) node _T_683 = or(_T_682, _T_665) node _T_684 = or(_T_683, _T_670) node _T_685 = or(_T_684, _T_675) node _T_686 = or(_T_685, _T_680) node _T_687 = and(_T_645, _T_686) node _T_688 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_689 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_690 = cvt(_T_689) node _T_691 = and(_T_690, asSInt(UInt<17>(0h10000))) node _T_692 = asSInt(_T_691) node _T_693 = eq(_T_692, asSInt(UInt<1>(0h0))) node _T_694 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_695 = cvt(_T_694) node _T_696 = and(_T_695, asSInt(UInt<30>(0h20000000))) node _T_697 = asSInt(_T_696) node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0))) node _T_699 = or(_T_693, _T_698) node _T_700 = and(_T_688, _T_699) node _T_701 = or(UInt<1>(0h0), _T_687) node _T_702 = or(_T_701, _T_700) node _T_703 = and(_T_641, _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_703, UInt<1>(0h1), "") : assert_36 node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(source_ok, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(is_aligned, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_713 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_713, UInt<1>(0h1), "") : assert_39 node _T_717 = eq(io.in.a.bits.mask, mask) node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(_T_717, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_717, UInt<1>(0h1), "") : assert_40 node _T_721 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_721 : node _T_722 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_723 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_726 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_727 = or(_T_725, _T_726) node _T_728 = and(_T_724, _T_727) node _T_729 = or(UInt<1>(0h0), _T_728) node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_731 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_732 = and(_T_730, _T_731) node _T_733 = or(UInt<1>(0h0), _T_732) node _T_734 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_735 = cvt(_T_734) node _T_736 = and(_T_735, asSInt(UInt<14>(0h2000))) node _T_737 = asSInt(_T_736) node _T_738 = eq(_T_737, asSInt(UInt<1>(0h0))) node _T_739 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_740 = cvt(_T_739) node _T_741 = and(_T_740, asSInt(UInt<13>(0h1000))) node _T_742 = asSInt(_T_741) node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0))) node _T_744 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_745 = cvt(_T_744) node _T_746 = and(_T_745, asSInt(UInt<18>(0h2f000))) node _T_747 = asSInt(_T_746) node _T_748 = eq(_T_747, asSInt(UInt<1>(0h0))) node _T_749 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<17>(0h10000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<27>(0h4000000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<13>(0h1000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<15>(0h4000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = or(_T_738, _T_743) node _T_770 = or(_T_769, _T_748) node _T_771 = or(_T_770, _T_753) node _T_772 = or(_T_771, _T_758) node _T_773 = or(_T_772, _T_763) node _T_774 = or(_T_773, _T_768) node _T_775 = and(_T_733, _T_774) node _T_776 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_777 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_778 = cvt(_T_777) node _T_779 = and(_T_778, asSInt(UInt<17>(0h10000))) node _T_780 = asSInt(_T_779) node _T_781 = eq(_T_780, asSInt(UInt<1>(0h0))) node _T_782 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_783 = cvt(_T_782) node _T_784 = and(_T_783, asSInt(UInt<30>(0h20000000))) node _T_785 = asSInt(_T_784) node _T_786 = eq(_T_785, asSInt(UInt<1>(0h0))) node _T_787 = or(_T_781, _T_786) node _T_788 = and(_T_776, _T_787) node _T_789 = or(UInt<1>(0h0), _T_775) node _T_790 = or(_T_789, _T_788) node _T_791 = and(_T_729, _T_790) node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(_T_791, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_791, UInt<1>(0h1), "") : assert_41 node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(source_ok, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_798 = asUInt(reset) node _T_799 = eq(_T_798, UInt<1>(0h0)) when _T_799 : node _T_800 = eq(is_aligned, UInt<1>(0h0)) when _T_800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_801 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_801, UInt<1>(0h1), "") : assert_44 node _T_805 = eq(io.in.a.bits.mask, mask) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_805, UInt<1>(0h1), "") : assert_45 node _T_809 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_809 : node _T_810 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_811 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_812 = and(_T_810, _T_811) node _T_813 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_814 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_815 = or(_T_813, _T_814) node _T_816 = and(_T_812, _T_815) node _T_817 = or(UInt<1>(0h0), _T_816) node _T_818 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_819 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_820 = and(_T_818, _T_819) node _T_821 = or(UInt<1>(0h0), _T_820) node _T_822 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_823 = cvt(_T_822) node _T_824 = and(_T_823, asSInt(UInt<13>(0h1000))) node _T_825 = asSInt(_T_824) node _T_826 = eq(_T_825, asSInt(UInt<1>(0h0))) node _T_827 = and(_T_821, _T_826) node _T_828 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_829 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<14>(0h2000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<17>(0h10000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<18>(0h2f000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<30>(0h20000000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<15>(0h4000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = or(_T_833, _T_838) node _T_870 = or(_T_869, _T_843) node _T_871 = or(_T_870, _T_848) node _T_872 = or(_T_871, _T_853) node _T_873 = or(_T_872, _T_858) node _T_874 = or(_T_873, _T_863) node _T_875 = or(_T_874, _T_868) node _T_876 = and(_T_828, _T_875) node _T_877 = or(UInt<1>(0h0), _T_827) node _T_878 = or(_T_877, _T_876) node _T_879 = and(_T_817, _T_878) node _T_880 = asUInt(reset) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(_T_879, UInt<1>(0h0)) when _T_882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_879, UInt<1>(0h1), "") : assert_46 node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(source_ok, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(is_aligned, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_889 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_889, UInt<1>(0h1), "") : assert_49 node _T_893 = eq(io.in.a.bits.mask, mask) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_893, UInt<1>(0h1), "") : assert_50 node _T_897 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(_T_897, UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_897, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_901 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_901, UInt<1>(0h1), "") : assert_52 node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h1)) node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_2 connect _source_ok_WIRE_1[1], _source_ok_T_3 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_905 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_905 : node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(source_ok_1, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_909 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(_T_909, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_909, UInt<1>(0h1), "") : assert_54 node _T_913 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_913, UInt<1>(0h1), "") : assert_55 node _T_917 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_917, UInt<1>(0h1), "") : assert_56 node _T_921 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_921, UInt<1>(0h1), "") : assert_57 node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_925 : node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(source_ok_1, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(sink_ok, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_932 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_932, UInt<1>(0h1), "") : assert_60 node _T_936 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_936, UInt<1>(0h1), "") : assert_61 node _T_940 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_940, UInt<1>(0h1), "") : assert_62 node _T_944 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(_T_944, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_944, UInt<1>(0h1), "") : assert_63 node _T_948 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_949 = or(UInt<1>(0h1), _T_948) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_949, UInt<1>(0h1), "") : assert_64 node _T_953 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_953 : node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(source_ok_1, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(sink_ok, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_960 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_960, UInt<1>(0h1), "") : assert_67 node _T_964 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_964, UInt<1>(0h1), "") : assert_68 node _T_968 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_968, UInt<1>(0h1), "") : assert_69 node _T_972 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_973 = or(_T_972, io.in.d.bits.corrupt) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_973, UInt<1>(0h1), "") : assert_70 node _T_977 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_978 = or(UInt<1>(0h1), _T_977) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_978, UInt<1>(0h1), "") : assert_71 node _T_982 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_982 : node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(source_ok_1, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_986 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_986, UInt<1>(0h1), "") : assert_73 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_990, UInt<1>(0h1), "") : assert_74 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_995, UInt<1>(0h1), "") : assert_75 node _T_999 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(source_ok_1, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1003 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(_T_1003, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1003, UInt<1>(0h1), "") : assert_77 node _T_1007 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1008 = or(_T_1007, io.in.d.bits.corrupt) node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(_T_1008, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1008, UInt<1>(0h1), "") : assert_78 node _T_1012 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1013 = or(UInt<1>(0h1), _T_1012) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_79 node _T_1017 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1017 : node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(source_ok_1, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1021 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_81 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_82 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1034 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_T_1034, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1034, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1038 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1042 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1043 = asUInt(reset) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) when _T_1044 : node _T_1045 = eq(_T_1042, UInt<1>(0h0)) when _T_1045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1042, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1046 = eq(a_first, UInt<1>(0h0)) node _T_1047 = and(io.in.a.valid, _T_1046) when _T_1047 : node _T_1048 = eq(io.in.a.bits.opcode, opcode) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_87 node _T_1052 = eq(io.in.a.bits.param, param) node _T_1053 = asUInt(reset) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) when _T_1054 : node _T_1055 = eq(_T_1052, UInt<1>(0h0)) when _T_1055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1052, UInt<1>(0h1), "") : assert_88 node _T_1056 = eq(io.in.a.bits.size, size) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_89 node _T_1060 = eq(io.in.a.bits.source, source) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_90 node _T_1064 = eq(io.in.a.bits.address, address) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_91 node _T_1068 = and(io.in.a.ready, io.in.a.valid) node _T_1069 = and(_T_1068, a_first) when _T_1069 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1070 = eq(d_first, UInt<1>(0h0)) node _T_1071 = and(io.in.d.valid, _T_1070) when _T_1071 : node _T_1072 = eq(io.in.d.bits.opcode, opcode_1) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_92 node _T_1076 = eq(io.in.d.bits.param, param_1) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_93 node _T_1080 = eq(io.in.d.bits.size, size_1) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_94 node _T_1084 = eq(io.in.d.bits.source, source_1) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_95 node _T_1088 = eq(io.in.d.bits.sink, sink) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_96 node _T_1092 = eq(io.in.d.bits.denied, denied) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_97 node _T_1096 = and(io.in.d.ready, io.in.d.valid) node _T_1097 = and(_T_1096, d_first) when _T_1097 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2> connect a_set, UInt<2>(0h0) wire a_set_wo_ready : UInt<2> connect a_set_wo_ready, UInt<2>(0h0) wire a_opcodes_set : UInt<8> connect a_opcodes_set, UInt<8>(0h0) wire a_sizes_set : UInt<16> connect a_sizes_set, UInt<16>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1098 = and(io.in.a.valid, a_first_1) node _T_1099 = and(_T_1098, UInt<1>(0h1)) when _T_1099 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1100 = and(io.in.a.ready, io.in.a.valid) node _T_1101 = and(_T_1100, a_first_1) node _T_1102 = and(_T_1101, UInt<1>(0h1)) when _T_1102 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1103 = dshr(inflight, io.in.a.bits.source) node _T_1104 = bits(_T_1103, 0, 0) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2> connect d_clr, UInt<2>(0h0) wire d_clr_wo_ready : UInt<2> connect d_clr_wo_ready, UInt<2>(0h0) wire d_opcodes_clr : UInt<8> connect d_opcodes_clr, UInt<8>(0h0) wire d_sizes_clr : UInt<16> connect d_sizes_clr, UInt<16>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1109 = and(io.in.d.valid, d_first_1) node _T_1110 = and(_T_1109, UInt<1>(0h1)) node _T_1111 = eq(d_release_ack, UInt<1>(0h0)) node _T_1112 = and(_T_1110, _T_1111) when _T_1112 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1113 = and(io.in.d.ready, io.in.d.valid) node _T_1114 = and(_T_1113, d_first_1) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = eq(d_release_ack, UInt<1>(0h0)) node _T_1117 = and(_T_1115, _T_1116) when _T_1117 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1118 = and(io.in.d.valid, d_first_1) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = eq(d_release_ack, UInt<1>(0h0)) node _T_1121 = and(_T_1119, _T_1120) when _T_1121 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1122 = dshr(inflight, io.in.d.bits.source) node _T_1123 = bits(_T_1122, 0, 0) node _T_1124 = or(_T_1123, same_cycle_resp) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1128 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1129 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1130 = or(_T_1128, _T_1129) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_100 node _T_1134 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_101 else : node _T_1138 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1139 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1140 = or(_T_1138, _T_1139) node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(_T_1140, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1140, UInt<1>(0h1), "") : assert_102 node _T_1144 = eq(io.in.d.bits.size, a_size_lookup) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_103 node _T_1148 = and(io.in.d.valid, d_first_1) node _T_1149 = and(_T_1148, a_first_1) node _T_1150 = and(_T_1149, io.in.a.valid) node _T_1151 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1152 = and(_T_1150, _T_1151) node _T_1153 = eq(d_release_ack, UInt<1>(0h0)) node _T_1154 = and(_T_1152, _T_1153) when _T_1154 : node _T_1155 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1156 = or(_T_1155, io.in.a.ready) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_104 node _T_1160 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1161 = orr(a_set_wo_ready) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) node _T_1163 = or(_T_1160, _T_1162) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_2 node _T_1167 = orr(inflight) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) node _T_1169 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1170 = or(_T_1168, _T_1169) node _T_1171 = lt(watchdog, plusarg_reader.out) node _T_1172 = or(_T_1170, _T_1171) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1176 = and(io.in.a.ready, io.in.a.valid) node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = or(_T_1176, _T_1177) when _T_1178 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2> connect c_set, UInt<2>(0h0) wire c_set_wo_ready : UInt<2> connect c_set_wo_ready, UInt<2>(0h0) wire c_opcodes_set : UInt<8> connect c_opcodes_set, UInt<8>(0h0) wire c_sizes_set : UInt<16> connect c_sizes_set, UInt<16>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1179 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1180 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1181 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1182 = and(_T_1180, _T_1181) node _T_1183 = and(_T_1179, _T_1182) when _T_1183 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1184 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1185 = and(_T_1184, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1186 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1187 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = and(_T_1185, _T_1188) when _T_1189 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1190 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1191 = bits(_T_1190, 0, 0) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2> connect d_clr_1, UInt<2>(0h0) wire d_clr_wo_ready_1 : UInt<2> connect d_clr_wo_ready_1, UInt<2>(0h0) wire d_opcodes_clr_1 : UInt<8> connect d_opcodes_clr_1, UInt<8>(0h0) wire d_sizes_clr_1 : UInt<16> connect d_sizes_clr_1, UInt<16>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1196 = and(io.in.d.valid, d_first_2) node _T_1197 = and(_T_1196, UInt<1>(0h1)) node _T_1198 = and(_T_1197, d_release_ack_1) when _T_1198 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1199 = and(io.in.d.ready, io.in.d.valid) node _T_1200 = and(_T_1199, d_first_2) node _T_1201 = and(_T_1200, UInt<1>(0h1)) node _T_1202 = and(_T_1201, d_release_ack_1) when _T_1202 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1203 = and(io.in.d.valid, d_first_2) node _T_1204 = and(_T_1203, UInt<1>(0h1)) node _T_1205 = and(_T_1204, d_release_ack_1) when _T_1205 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1206 = dshr(inflight_1, io.in.d.bits.source) node _T_1207 = bits(_T_1206, 0, 0) node _T_1208 = or(_T_1207, same_cycle_resp_1) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1212 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_109 else : node _T_1216 = eq(io.in.d.bits.size, c_size_lookup) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_110 node _T_1220 = and(io.in.d.valid, d_first_2) node _T_1221 = and(_T_1220, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1222 = and(_T_1221, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1223 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1224, d_release_ack_1) node _T_1226 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1227 = and(_T_1225, _T_1226) when _T_1227 : node _T_1228 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1229 = or(_T_1228, _WIRE_23.ready) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_111 node _T_1233 = orr(c_set_wo_ready) when _T_1233 : node _T_1234 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1235 = asUInt(reset) node _T_1236 = eq(_T_1235, UInt<1>(0h0)) when _T_1236 : node _T_1237 = eq(_T_1234, UInt<1>(0h0)) when _T_1237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1234, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_3 node _T_1238 = orr(inflight_1) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) node _T_1240 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1241 = or(_T_1239, _T_1240) node _T_1242 = lt(watchdog_1, plusarg_reader_1.out) node _T_1243 = or(_T_1241, _T_1242) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1247 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1248 = and(io.in.d.ready, io.in.d.valid) node _T_1249 = or(_T_1247, _T_1248) when _T_1249 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_bufferable, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_modifiable, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_readalloc, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_writealloc, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_privileged, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_secure, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_fetch, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_bufferable_0 = io_in_a_bits_user_amba_prot_bufferable; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_modifiable_0 = io_in_a_bits_user_amba_prot_modifiable; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_readalloc_0 = io_in_a_bits_user_amba_prot_readalloc; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_writealloc_0 = io_in_a_bits_user_amba_prot_writealloc; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_privileged_0 = io_in_a_bits_user_amba_prot_privileged; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_secure_0 = io_in_a_bits_user_amba_prot_secure; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_fetch_0 = io_in_a_bits_user_amba_prot_fetch; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [15:0] c_sizes_set = 16'h0; // @[Monitor.scala:741:34] wire [7:0] c_opcodes_set = 8'h0; // @[Monitor.scala:740:34] wire [1:0] c_set = 2'h0; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready = 2'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _T_1176 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1176; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1176; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1249 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1249; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1249; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1249; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_1102 = _T_1176 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1102 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1102 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1102 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1102 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1102 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1148 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1148 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_1117 = _T_1249 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1117 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1117 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1117 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1220 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1220 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_1202 = _T_1249 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1202 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1202 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1202 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_28 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_39 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_28( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_39 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_36 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_36 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_36( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_36 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<10>(0h200))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = and(_T_19, _T_24) node _T_26 = or(UInt<1>(0h0), _T_25) node _T_27 = and(_T_18, _T_26) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 node _T_31 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_32 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_33 = and(_T_31, _T_32) node _T_34 = or(UInt<1>(0h0), _T_33) node _T_35 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<10>(0h200))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = and(_T_34, _T_39) node _T_41 = or(UInt<1>(0h0), _T_40) node _T_42 = and(UInt<1>(0h0), _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_42, UInt<1>(0h1), "") : assert_3 node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_49 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_49, UInt<1>(0h1), "") : assert_5 node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(is_aligned, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_56 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_56, UInt<1>(0h1), "") : assert_7 node _T_60 = not(io.in.a.bits.mask) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_61, UInt<1>(0h1), "") : assert_8 node _T_65 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_69 : node _T_70 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_71 = and(UInt<1>(0h0), _T_70) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<10>(0h200))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = and(_T_73, _T_78) node _T_80 = or(UInt<1>(0h0), _T_79) node _T_81 = and(_T_72, _T_80) node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(_T_81, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_81, UInt<1>(0h1), "") : assert_10 node _T_85 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_86 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_87 = and(_T_85, _T_86) node _T_88 = or(UInt<1>(0h0), _T_87) node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<10>(0h200))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = and(_T_88, _T_93) node _T_95 = or(UInt<1>(0h0), _T_94) node _T_96 = and(UInt<1>(0h0), _T_95) node _T_97 = asUInt(reset) node _T_98 = eq(_T_97, UInt<1>(0h0)) when _T_98 : node _T_99 = eq(_T_96, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_96, UInt<1>(0h1), "") : assert_11 node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_103 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_103, UInt<1>(0h1), "") : assert_13 node _T_107 = asUInt(reset) node _T_108 = eq(_T_107, UInt<1>(0h0)) when _T_108 : node _T_109 = eq(is_aligned, UInt<1>(0h0)) when _T_109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_110 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_110, UInt<1>(0h1), "") : assert_15 node _T_114 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_114, UInt<1>(0h1), "") : assert_16 node _T_118 = not(io.in.a.bits.mask) node _T_119 = eq(_T_118, UInt<1>(0h0)) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_119, UInt<1>(0h1), "") : assert_17 node _T_123 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_T_123, UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_123, UInt<1>(0h1), "") : assert_18 node _T_127 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_127 : node _T_128 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_129 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_130 = and(_T_128, _T_129) node _T_131 = or(UInt<1>(0h0), _T_130) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_131, UInt<1>(0h1), "") : assert_19 node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_136 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_137 = and(_T_135, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<10>(0h200))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = and(_T_138, _T_143) node _T_145 = or(UInt<1>(0h0), _T_144) node _T_146 = asUInt(reset) node _T_147 = eq(_T_146, UInt<1>(0h0)) when _T_147 : node _T_148 = eq(_T_145, UInt<1>(0h0)) when _T_148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_145, UInt<1>(0h1), "") : assert_20 node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(is_aligned, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_155 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_155, UInt<1>(0h1), "") : assert_23 node _T_159 = eq(io.in.a.bits.mask, mask) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_159, UInt<1>(0h1), "") : assert_24 node _T_163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_163, UInt<1>(0h1), "") : assert_25 node _T_167 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_169 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_170 = and(_T_168, _T_169) node _T_171 = or(UInt<1>(0h0), _T_170) node _T_172 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_173 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_174 = and(_T_172, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<10>(0h200))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = and(_T_175, _T_180) node _T_182 = or(UInt<1>(0h0), _T_181) node _T_183 = and(_T_171, _T_182) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_183, UInt<1>(0h1), "") : assert_26 node _T_187 = asUInt(reset) node _T_188 = eq(_T_187, UInt<1>(0h0)) when _T_188 : node _T_189 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(is_aligned, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_193 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_193, UInt<1>(0h1), "") : assert_29 node _T_197 = eq(io.in.a.bits.mask, mask) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_197, UInt<1>(0h1), "") : assert_30 node _T_201 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_201 : node _T_202 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_203 = and(UInt<1>(0h0), _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_206 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_207 = and(_T_205, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<10>(0h200))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = and(_T_208, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(_T_204, _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_216, UInt<1>(0h1), "") : assert_31 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(is_aligned, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_226 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(_T_226, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_226, UInt<1>(0h1), "") : assert_34 node _T_230 = not(mask) node _T_231 = and(io.in.a.bits.mask, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_232, UInt<1>(0h1), "") : assert_35 node _T_236 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_236 : node _T_237 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_238 = and(UInt<1>(0h0), _T_237) node _T_239 = or(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<10>(0h200))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = and(_T_240, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = and(_T_239, _T_247) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_248, UInt<1>(0h1), "") : assert_36 node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(is_aligned, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_258 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_258, UInt<1>(0h1), "") : assert_39 node _T_262 = eq(io.in.a.bits.mask, mask) node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_T_262, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_262, UInt<1>(0h1), "") : assert_40 node _T_266 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_266 : node _T_267 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_268 = and(UInt<1>(0h0), _T_267) node _T_269 = or(UInt<1>(0h0), _T_268) node _T_270 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_271 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<10>(0h200))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = and(_T_270, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = and(_T_269, _T_277) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_278, UInt<1>(0h1), "") : assert_41 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : node _T_284 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(is_aligned, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_288 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_288, UInt<1>(0h1), "") : assert_44 node _T_292 = eq(io.in.a.bits.mask, mask) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_292, UInt<1>(0h1), "") : assert_45 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_296 : node _T_297 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_298 = and(UInt<1>(0h0), _T_297) node _T_299 = or(UInt<1>(0h0), _T_298) node _T_300 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<10>(0h200))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = and(_T_300, _T_305) node _T_307 = or(UInt<1>(0h0), _T_306) node _T_308 = and(_T_299, _T_307) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_308, UInt<1>(0h1), "") : assert_46 node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(is_aligned, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_318 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_318, UInt<1>(0h1), "") : assert_49 node _T_322 = eq(io.in.a.bits.mask, mask) node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(_T_322, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_322, UInt<1>(0h1), "") : assert_50 node _T_326 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_327 = asUInt(reset) node _T_328 = eq(_T_327, UInt<1>(0h0)) when _T_328 : node _T_329 = eq(_T_326, UInt<1>(0h0)) when _T_329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_326, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_330 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_331 = asUInt(reset) node _T_332 = eq(_T_331, UInt<1>(0h0)) when _T_332 : node _T_333 = eq(_T_330, UInt<1>(0h0)) when _T_333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_330, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_334 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_334 : node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_338 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_338, UInt<1>(0h1), "") : assert_54 node _T_342 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_342, UInt<1>(0h1), "") : assert_55 node _T_346 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_346, UInt<1>(0h1), "") : assert_56 node _T_350 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(_T_350, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_350, UInt<1>(0h1), "") : assert_57 node _T_354 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_354 : node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(sink_ok, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_361 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_361, UInt<1>(0h1), "") : assert_60 node _T_365 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_365, UInt<1>(0h1), "") : assert_61 node _T_369 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_369, UInt<1>(0h1), "") : assert_62 node _T_373 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_373, UInt<1>(0h1), "") : assert_63 node _T_377 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_378 = or(UInt<1>(0h1), _T_377) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_378, UInt<1>(0h1), "") : assert_64 node _T_382 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_382 : node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(sink_ok, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_389 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_389, UInt<1>(0h1), "") : assert_67 node _T_393 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_393, UInt<1>(0h1), "") : assert_68 node _T_397 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_397, UInt<1>(0h1), "") : assert_69 node _T_401 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_402 = or(_T_401, io.in.d.bits.corrupt) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_402, UInt<1>(0h1), "") : assert_70 node _T_406 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_407 = or(UInt<1>(0h1), _T_406) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_407, UInt<1>(0h1), "") : assert_71 node _T_411 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_411 : node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_415 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_415, UInt<1>(0h1), "") : assert_73 node _T_419 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_419, UInt<1>(0h1), "") : assert_74 node _T_423 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_424 = or(UInt<1>(0h1), _T_423) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_424, UInt<1>(0h1), "") : assert_75 node _T_428 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_428 : node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_432 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_432, UInt<1>(0h1), "") : assert_77 node _T_436 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_437 = or(_T_436, io.in.d.bits.corrupt) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_437, UInt<1>(0h1), "") : assert_78 node _T_441 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_442 = or(UInt<1>(0h1), _T_441) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_442, UInt<1>(0h1), "") : assert_79 node _T_446 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_450 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_450, UInt<1>(0h1), "") : assert_81 node _T_454 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_454, UInt<1>(0h1), "") : assert_82 node _T_458 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_459 = or(UInt<1>(0h1), _T_458) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_459, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_463 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_463, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_467 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_467, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_471 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_471, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_475 = eq(a_first, UInt<1>(0h0)) node _T_476 = and(io.in.a.valid, _T_475) when _T_476 : node _T_477 = eq(io.in.a.bits.opcode, opcode) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_477, UInt<1>(0h1), "") : assert_87 node _T_481 = eq(io.in.a.bits.param, param) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_481, UInt<1>(0h1), "") : assert_88 node _T_485 = eq(io.in.a.bits.size, size) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_485, UInt<1>(0h1), "") : assert_89 node _T_489 = eq(io.in.a.bits.source, source) node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_T_489, UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_489, UInt<1>(0h1), "") : assert_90 node _T_493 = eq(io.in.a.bits.address, address) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_493, UInt<1>(0h1), "") : assert_91 node _T_497 = and(io.in.a.ready, io.in.a.valid) node _T_498 = and(_T_497, a_first) when _T_498 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_499 = eq(d_first, UInt<1>(0h0)) node _T_500 = and(io.in.d.valid, _T_499) when _T_500 : node _T_501 = eq(io.in.d.bits.opcode, opcode_1) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_501, UInt<1>(0h1), "") : assert_92 node _T_505 = eq(io.in.d.bits.param, param_1) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_505, UInt<1>(0h1), "") : assert_93 node _T_509 = eq(io.in.d.bits.size, size_1) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_509, UInt<1>(0h1), "") : assert_94 node _T_513 = eq(io.in.d.bits.source, source_1) node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_T_513, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_513, UInt<1>(0h1), "") : assert_95 node _T_517 = eq(io.in.d.bits.sink, sink) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_517, UInt<1>(0h1), "") : assert_96 node _T_521 = eq(io.in.d.bits.denied, denied) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_521, UInt<1>(0h1), "") : assert_97 node _T_525 = and(io.in.d.ready, io.in.d.valid) node _T_526 = and(_T_525, d_first) when _T_526 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_527 = and(io.in.a.valid, a_first_1) node _T_528 = and(_T_527, UInt<1>(0h1)) when _T_528 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_529 = and(io.in.a.ready, io.in.a.valid) node _T_530 = and(_T_529, a_first_1) node _T_531 = and(_T_530, UInt<1>(0h1)) when _T_531 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_532 = dshr(inflight, io.in.a.bits.source) node _T_533 = bits(_T_532, 0, 0) node _T_534 = eq(_T_533, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_534, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_538 = and(io.in.d.valid, d_first_1) node _T_539 = and(_T_538, UInt<1>(0h1)) node _T_540 = eq(d_release_ack, UInt<1>(0h0)) node _T_541 = and(_T_539, _T_540) when _T_541 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_542 = and(io.in.d.ready, io.in.d.valid) node _T_543 = and(_T_542, d_first_1) node _T_544 = and(_T_543, UInt<1>(0h1)) node _T_545 = eq(d_release_ack, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) when _T_546 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_551 = dshr(inflight, io.in.d.bits.source) node _T_552 = bits(_T_551, 0, 0) node _T_553 = or(_T_552, same_cycle_resp) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_553, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_557 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_558 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_559 = or(_T_557, _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_559, UInt<1>(0h1), "") : assert_100 node _T_563 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_563, UInt<1>(0h1), "") : assert_101 else : node _T_567 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_568 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_569 = or(_T_567, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_569, UInt<1>(0h1), "") : assert_102 node _T_573 = eq(io.in.d.bits.size, a_size_lookup) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_573, UInt<1>(0h1), "") : assert_103 node _T_577 = and(io.in.d.valid, d_first_1) node _T_578 = and(_T_577, a_first_1) node _T_579 = and(_T_578, io.in.a.valid) node _T_580 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_581 = and(_T_579, _T_580) node _T_582 = eq(d_release_ack, UInt<1>(0h0)) node _T_583 = and(_T_581, _T_582) when _T_583 : node _T_584 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_585 = or(_T_584, io.in.a.ready) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_585, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_96 node _T_589 = orr(inflight) node _T_590 = eq(_T_589, UInt<1>(0h0)) node _T_591 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_592 = or(_T_590, _T_591) node _T_593 = lt(watchdog, plusarg_reader.out) node _T_594 = or(_T_592, _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_594, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_598 = and(io.in.a.ready, io.in.a.valid) node _T_599 = and(io.in.d.ready, io.in.d.valid) node _T_600 = or(_T_598, _T_599) when _T_600 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_601 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_602 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_603 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_604 = and(_T_602, _T_603) node _T_605 = and(_T_601, _T_604) when _T_605 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_606 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_607 = and(_T_606, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_608 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_609 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_610 = and(_T_608, _T_609) node _T_611 = and(_T_607, _T_610) when _T_611 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_612 = dshr(inflight_1, _WIRE_15.bits.source) node _T_613 = bits(_T_612, 0, 0) node _T_614 = eq(_T_613, UInt<1>(0h0)) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_614, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_618 = and(io.in.d.valid, d_first_2) node _T_619 = and(_T_618, UInt<1>(0h1)) node _T_620 = and(_T_619, d_release_ack_1) when _T_620 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_621 = and(io.in.d.ready, io.in.d.valid) node _T_622 = and(_T_621, d_first_2) node _T_623 = and(_T_622, UInt<1>(0h1)) node _T_624 = and(_T_623, d_release_ack_1) when _T_624 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_625 = and(io.in.d.valid, d_first_2) node _T_626 = and(_T_625, UInt<1>(0h1)) node _T_627 = and(_T_626, d_release_ack_1) when _T_627 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_628 = dshr(inflight_1, io.in.d.bits.source) node _T_629 = bits(_T_628, 0, 0) node _T_630 = or(_T_629, same_cycle_resp_1) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_630, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_634 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_634, UInt<1>(0h1), "") : assert_108 else : node _T_638 = eq(io.in.d.bits.size, c_size_lookup) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_638, UInt<1>(0h1), "") : assert_109 node _T_642 = and(io.in.d.valid, d_first_2) node _T_643 = and(_T_642, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_644 = and(_T_643, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_645 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_646 = and(_T_644, _T_645) node _T_647 = and(_T_646, d_release_ack_1) node _T_648 = eq(c_probe_ack, UInt<1>(0h0)) node _T_649 = and(_T_647, _T_648) when _T_649 : node _T_650 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_651 = or(_T_650, _WIRE_23.ready) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_651, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_97 node _T_655 = orr(inflight_1) node _T_656 = eq(_T_655, UInt<1>(0h0)) node _T_657 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_658 = or(_T_656, _T_657) node _T_659 = lt(watchdog_1, plusarg_reader_1.out) node _T_660 = or(_T_658, _T_659) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_660, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_664 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_665 = and(io.in.d.ready, io.in.d.valid) node _T_666 = or(_T_664, _T_665) when _T_666 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_48( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_598 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_598; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_598; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_666 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_666; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_666; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_666; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_528 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_528; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_528; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_598 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_577 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_577 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_666 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_642 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_642 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_666 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_88 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_105 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_88( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_105 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLUART : input clock : Clock input reset : Reset output auto : { int_xing_out : { sync : UInt<1>[1]}, flip control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, io_out : { txd : UInt<1>, flip rxd : UInt<1>}} inst buffer of TLBuffer_a29d64s14k1z2u connect buffer.clock, clock connect buffer.reset, reset inst intsource of IntSyncCrossingSource_n1x1_5 connect intsource.clock, clock connect intsource.reset, reset wire ioNodeOut : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeOut.rxd invalidate ioNodeOut.txd wire intnodeOut : UInt<1>[1] invalidate intnodeOut[0] wire controlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlNodeIn.d.bits.corrupt invalidate controlNodeIn.d.bits.data invalidate controlNodeIn.d.bits.denied invalidate controlNodeIn.d.bits.sink invalidate controlNodeIn.d.bits.source invalidate controlNodeIn.d.bits.size invalidate controlNodeIn.d.bits.param invalidate controlNodeIn.d.bits.opcode invalidate controlNodeIn.d.valid invalidate controlNodeIn.d.ready invalidate controlNodeIn.a.bits.corrupt invalidate controlNodeIn.a.bits.data invalidate controlNodeIn.a.bits.mask invalidate controlNodeIn.a.bits.address invalidate controlNodeIn.a.bits.source invalidate controlNodeIn.a.bits.size invalidate controlNodeIn.a.bits.param invalidate controlNodeIn.a.bits.opcode invalidate controlNodeIn.a.valid invalidate controlNodeIn.a.ready inst monitor of TLMonitor_63 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, controlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, controlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, controlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, controlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, controlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, controlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, controlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, controlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, controlNodeIn.d.valid connect monitor.io.in.d.ready, controlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, controlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, controlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, controlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, controlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, controlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, controlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, controlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, controlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, controlNodeIn.a.valid connect monitor.io.in.a.ready, controlNodeIn.a.ready wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingOut.d.bits.corrupt invalidate controlXingOut.d.bits.data invalidate controlXingOut.d.bits.denied invalidate controlXingOut.d.bits.sink invalidate controlXingOut.d.bits.source invalidate controlXingOut.d.bits.size invalidate controlXingOut.d.bits.param invalidate controlXingOut.d.bits.opcode invalidate controlXingOut.d.valid invalidate controlXingOut.d.ready invalidate controlXingOut.a.bits.corrupt invalidate controlXingOut.a.bits.data invalidate controlXingOut.a.bits.mask invalidate controlXingOut.a.bits.address invalidate controlXingOut.a.bits.source invalidate controlXingOut.a.bits.size invalidate controlXingOut.a.bits.param invalidate controlXingOut.a.bits.opcode invalidate controlXingOut.a.valid invalidate controlXingOut.a.ready wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingIn.d.bits.corrupt invalidate controlXingIn.d.bits.data invalidate controlXingIn.d.bits.denied invalidate controlXingIn.d.bits.sink invalidate controlXingIn.d.bits.source invalidate controlXingIn.d.bits.size invalidate controlXingIn.d.bits.param invalidate controlXingIn.d.bits.opcode invalidate controlXingIn.d.valid invalidate controlXingIn.d.ready invalidate controlXingIn.a.bits.corrupt invalidate controlXingIn.a.bits.data invalidate controlXingIn.a.bits.mask invalidate controlXingIn.a.bits.address invalidate controlXingIn.a.bits.source invalidate controlXingIn.a.bits.size invalidate controlXingIn.a.bits.param invalidate controlXingIn.a.bits.opcode invalidate controlXingIn.a.valid invalidate controlXingIn.a.ready connect controlXingOut, controlXingIn wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn connect intsource.auto.in[0], intnodeOut[0] connect buffer.auto.out.d, controlNodeIn.d connect controlNodeIn.a.bits, buffer.auto.out.a.bits connect controlNodeIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, controlNodeIn.a.ready connect buffer.auto.in, controlXingOut connect intXingIn, intsource.auto.out connect auto.io_out, ioNodeOut connect controlXingIn, auto.control_xing_in connect auto.int_xing_out, intXingOut inst txm of UARTTx connect txm.clock, clock connect txm.reset, reset inst txq of Queue8_UInt8 connect txq.clock, clock connect txq.reset, reset inst rxm of UARTRx connect rxm.clock, clock connect rxm.reset, reset inst rxq of Queue8_UInt8_1 connect rxq.clock, clock connect rxq.reset, reset regreset div : UInt<16>, clock, reset, UInt<16>(0h10f4) regreset txen : UInt<1>, clock, reset, UInt<1>(0h0) regreset rxen : UInt<1>, clock, reset, UInt<1>(0h0) regreset enwire4 : UInt<1>, clock, reset, UInt<1>(0h0) regreset invpol : UInt<1>, clock, reset, UInt<1>(0h0) regreset enparity : UInt<1>, clock, reset, UInt<1>(0h0) regreset parity : UInt<1>, clock, reset, UInt<1>(0h0) regreset errorparity : UInt<1>, clock, reset, UInt<1>(0h0) regreset errie : UInt<1>, clock, reset, UInt<1>(0h0) regreset txwm : UInt<4>, clock, reset, UInt<4>(0h0) regreset rxwm : UInt<4>, clock, reset, UInt<4>(0h0) regreset nstop : UInt<1>, clock, reset, UInt<1>(0h0) regreset data8or9 : UInt<1>, clock, reset, UInt<1>(0h1) connect txm.io.en, txen connect txm.io.in, txq.io.deq connect txm.io.div, div connect txm.io.nstop, nstop connect ioNodeOut.txd, txm.io.out connect rxm.io.en, rxen connect rxm.io.in, ioNodeOut.rxd connect rxq.io.enq.valid, rxm.io.out.valid connect rxq.io.enq.bits, rxm.io.out.bits connect rxm.io.div, div node _tx_busy_T = orr(txq.io.count) node _tx_busy_T_1 = or(txm.io.tx_busy, _tx_busy_T) node tx_busy = and(_tx_busy_T_1, txen) wire _ie_WIRE : { rxwm : UInt<1>, txwm : UInt<1>} connect _ie_WIRE.txwm, UInt<1>(0h0) connect _ie_WIRE.rxwm, UInt<1>(0h0) regreset ie : { rxwm : UInt<1>, txwm : UInt<1>}, clock, reset, _ie_WIRE wire ip : { rxwm : UInt<1>, txwm : UInt<1>} node _ip_txwm_T = lt(txq.io.count, txwm) connect ip.txwm, _ip_txwm_T node _ip_rxwm_T = gt(rxq.io.count, rxwm) connect ip.rxwm, _ip_rxwm_T node _intnodeOut_0_T = and(ip.txwm, ie.txwm) node _intnodeOut_0_T_1 = and(ip.rxwm, ie.rxwm) node _intnodeOut_0_T_2 = or(_intnodeOut_0_T, _intnodeOut_0_T_1) connect intnodeOut[0], _intnodeOut_0_T_2 wire quash : UInt<1> node _T = eq(txq.io.enq.ready, UInt<1>(0h0)) node _T_1 = eq(rxq.io.deq.valid, UInt<1>(0h0)) wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} node _in_bits_read_T = eq(controlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(controlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, controlNodeIn.a.bits.data connect in.bits.mask, controlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, controlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, controlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h3)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) node _out_T_6 = eq(out_findex, UInt<9>(0h0)) node _out_T_7 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[16] wire out_wivalid : UInt<1>[16] wire out_roready : UInt<1>[16] wire out_woready : UInt<1>[16] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_8 = bits(out_front.bits.data, 7, 0) node _out_txq_io_enq_valid_T = eq(quash, UInt<1>(0h0)) node _out_txq_io_enq_valid_T_1 = and(out_f_woready, _out_txq_io_enq_valid_T) connect txq.io.enq.valid, _out_txq_io_enq_valid_T_1 connect txq.io.enq.bits, _out_T_8 node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) node _out_T_10 = and(UInt<1>(0h1), out_f_woready) node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) node _out_T_13 = eq(out_romask, UInt<1>(0h0)) node _out_T_14 = eq(out_womask, UInt<1>(0h0)) node _out_T_15 = or(UInt<1>(0h0), UInt<8>(0h0)) node _out_T_16 = bits(_out_T_15, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 30, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 30, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 30, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 30, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_17 = bits(out_front.bits.data, 30, 8) node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_22 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_23 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_16, UInt<8>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_24 = or(out_prepend, UInt<31>(0h0)) node _out_T_25 = bits(_out_T_24, 30, 0) node _out_rimask_T_2 = bits(out_frontMask, 31, 31) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 31, 31) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 31, 31) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 31, 31) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_26 = bits(out_front.bits.data, 31, 31) node _out_quash_T = bits(_out_T_26, 0, 0) node _out_quash_T_1 = and(out_f_woready_2, _out_quash_T) connect quash, _out_quash_T_1 node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_29 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_30 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_31 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_32 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_25, UInt<31>(0h0)) node out_prepend_1 = cat(_T, _out_prepend_T_1) node _out_T_33 = or(out_prepend_1, UInt<32>(0h0)) node _out_T_34 = bits(_out_T_33, 31, 0) node _out_rimask_T_3 = bits(out_frontMask, 39, 32) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 39, 32) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 39, 32) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 39, 32) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) connect rxq.io.deq.ready, out_f_roready_3 node _out_T_35 = bits(out_front.bits.data, 39, 32) node _out_T_36 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_37 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_38 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_34, UInt<32>(0h0)) node out_prepend_2 = cat(rxq.io.deq.bits, _out_prepend_T_2) node _out_T_42 = or(out_prepend_2, UInt<40>(0h0)) node _out_T_43 = bits(_out_T_42, 39, 0) node _out_rimask_T_4 = bits(out_frontMask, 62, 40) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 62, 40) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 62, 40) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 62, 40) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_44 = bits(out_front.bits.data, 62, 40) node _out_T_45 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_46 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_49 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_50 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_43, UInt<40>(0h0)) node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3) node _out_T_51 = or(out_prepend_3, UInt<63>(0h0)) node _out_T_52 = bits(_out_T_51, 62, 0) node _out_rimask_T_5 = bits(out_frontMask, 63, 63) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 63, 63) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 63, 63) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 63, 63) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_53 = bits(out_front.bits.data, 63, 63) node _out_T_54 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_55 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_56 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_57 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_58 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_59 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_52, UInt<63>(0h0)) node out_prepend_4 = cat(_T_1, _out_prepend_T_4) node _out_T_60 = or(out_prepend_4, UInt<64>(0h0)) node _out_T_61 = bits(_out_T_60, 63, 0) node _out_rimask_T_6 = bits(out_frontMask, 0, 0) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 0, 0) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 0, 0) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 0, 0) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_62 = bits(out_front.bits.data, 0, 0) when out_f_woready_6 : connect txen, _out_T_62 node _out_T_63 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_64 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_65 = and(out_f_wivalid_6, UInt<1>(0h1)) node _out_T_66 = and(UInt<1>(0h1), out_f_woready_6) node _out_T_67 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_68 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_69 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_70 = eq(out_womask_6, UInt<1>(0h0)) node _out_T_71 = or(txen, UInt<1>(0h0)) node _out_T_72 = bits(_out_T_71, 0, 0) node _out_rimask_T_7 = bits(out_frontMask, 1, 1) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 1, 1) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 1, 1) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 1, 1) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_73 = bits(out_front.bits.data, 1, 1) when out_f_woready_7 : connect nstop, _out_T_73 node _out_T_74 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_75 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_76 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_77 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_78 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_79 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_80 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_81 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_72, UInt<1>(0h0)) node out_prepend_5 = cat(nstop, _out_prepend_T_5) node _out_T_82 = or(out_prepend_5, UInt<2>(0h0)) node _out_T_83 = bits(_out_T_82, 1, 0) node _out_rimask_T_8 = bits(out_frontMask, 19, 16) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 19, 16) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 19, 16) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 19, 16) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_84 = bits(out_front.bits.data, 19, 16) when out_f_woready_8 : connect txwm, _out_T_84 node _out_T_85 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_86 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_87 = and(out_f_wivalid_8, UInt<1>(0h1)) node _out_T_88 = and(UInt<1>(0h1), out_f_woready_8) node _out_T_89 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_90 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_91 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_92 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_83, UInt<16>(0h0)) node out_prepend_6 = cat(txwm, _out_prepend_T_6) node _out_T_93 = or(out_prepend_6, UInt<20>(0h0)) node _out_T_94 = bits(_out_T_93, 19, 0) node _out_rimask_T_9 = bits(out_frontMask, 32, 32) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 32, 32) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 32, 32) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 32, 32) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_95 = bits(out_front.bits.data, 32, 32) when out_f_woready_9 : connect rxen, _out_T_95 node _out_T_96 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_97 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_98 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_99 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_100 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_101 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_102 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_103 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_94, UInt<32>(0h0)) node out_prepend_7 = cat(rxen, _out_prepend_T_7) node _out_T_104 = or(out_prepend_7, UInt<33>(0h0)) node _out_T_105 = bits(_out_T_104, 32, 0) node _out_rimask_T_10 = bits(out_frontMask, 51, 48) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 51, 48) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 51, 48) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 51, 48) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_106 = bits(out_front.bits.data, 51, 48) when out_f_woready_10 : connect rxwm, _out_T_106 node _out_T_107 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_108 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_109 = and(out_f_wivalid_10, UInt<1>(0h1)) node _out_T_110 = and(UInt<1>(0h1), out_f_woready_10) node _out_T_111 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_112 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_113 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_114 = eq(out_womask_10, UInt<1>(0h0)) node _out_prepend_T_8 = or(_out_T_105, UInt<48>(0h0)) node out_prepend_8 = cat(rxwm, _out_prepend_T_8) node _out_T_115 = or(out_prepend_8, UInt<52>(0h0)) node _out_T_116 = bits(_out_T_115, 51, 0) node _out_rimask_T_11 = bits(out_frontMask, 0, 0) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 0, 0) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 0, 0) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 0, 0) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_117 = bits(out_front.bits.data, 0, 0) when out_f_woready_11 : connect ie.txwm, _out_T_117 node _out_T_118 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_119 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_120 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_121 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_122 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_123 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_124 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_125 = eq(out_womask_11, UInt<1>(0h0)) node _out_T_126 = or(ie.txwm, UInt<1>(0h0)) node _out_T_127 = bits(_out_T_126, 0, 0) node _out_rimask_T_12 = bits(out_frontMask, 1, 1) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 1, 1) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 1, 1) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 1, 1) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_128 = bits(out_front.bits.data, 1, 1) when out_f_woready_12 : connect ie.rxwm, _out_T_128 node _out_T_129 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_130 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_131 = and(out_f_wivalid_12, UInt<1>(0h1)) node _out_T_132 = and(UInt<1>(0h1), out_f_woready_12) node _out_T_133 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_134 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_135 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_136 = eq(out_womask_12, UInt<1>(0h0)) node _out_prepend_T_9 = or(_out_T_127, UInt<1>(0h0)) node out_prepend_9 = cat(ie.rxwm, _out_prepend_T_9) node _out_T_137 = or(out_prepend_9, UInt<2>(0h0)) node _out_T_138 = bits(_out_T_137, 1, 0) node _out_rimask_T_13 = bits(out_frontMask, 32, 32) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 32, 32) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 32, 32) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 32, 32) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) node _out_T_139 = bits(out_front.bits.data, 32, 32) node _out_T_140 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_141 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_142 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_143 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_144 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_145 = eq(out_womask_13, UInt<1>(0h0)) node _out_prepend_T_10 = or(_out_T_138, UInt<32>(0h0)) node out_prepend_10 = cat(ip.txwm, _out_prepend_T_10) node _out_T_146 = or(out_prepend_10, UInt<33>(0h0)) node _out_T_147 = bits(_out_T_146, 32, 0) node _out_rimask_T_14 = bits(out_frontMask, 33, 33) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 33, 33) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 33, 33) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 33, 33) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_148 = bits(out_front.bits.data, 33, 33) node _out_T_149 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_150 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_151 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_152 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_153 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_154 = eq(out_womask_14, UInt<1>(0h0)) node _out_prepend_T_11 = or(_out_T_147, UInt<33>(0h0)) node out_prepend_11 = cat(ip.rxwm, _out_prepend_T_11) node _out_T_155 = or(out_prepend_11, UInt<34>(0h0)) node _out_T_156 = bits(_out_T_155, 33, 0) node _out_rimask_T_15 = bits(out_frontMask, 15, 0) node out_rimask_15 = orr(_out_rimask_T_15) node _out_wimask_T_15 = bits(out_frontMask, 15, 0) node out_wimask_15 = andr(_out_wimask_T_15) node _out_romask_T_15 = bits(out_backMask, 15, 0) node out_romask_15 = orr(_out_romask_T_15) node _out_womask_T_15 = bits(out_backMask, 15, 0) node out_womask_15 = andr(_out_womask_T_15) node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) node out_f_roready_15 = and(out_roready[15], out_romask_15) node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) node out_f_woready_15 = and(out_woready[15], out_womask_15) node _out_T_157 = bits(out_front.bits.data, 15, 0) when out_f_woready_15 : connect div, _out_T_157 node _out_T_158 = and(out_f_rivalid_15, UInt<1>(0h1)) node _out_T_159 = and(UInt<1>(0h1), out_f_roready_15) node _out_T_160 = and(out_f_wivalid_15, UInt<1>(0h1)) node _out_T_161 = and(UInt<1>(0h1), out_f_woready_15) node _out_T_162 = eq(out_rimask_15, UInt<1>(0h0)) node _out_T_163 = eq(out_wimask_15, UInt<1>(0h0)) node _out_T_164 = eq(out_romask_15, UInt<1>(0h0)) node _out_T_165 = eq(out_womask_15, UInt<1>(0h0)) node _out_T_166 = or(div, UInt<16>(0h0)) node _out_T_167 = bits(_out_T_166, 15, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex = cat(_out_iindex_T_1, _out_iindex_T) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node out_oindex = cat(_out_oindex_T_1, _out_oindex_T) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[10], _out_rifireMux_T_7 connect out_rivalid[9], _out_rifireMux_T_7 connect out_rivalid[8], _out_rifireMux_T_7 connect out_rivalid[7], _out_rifireMux_T_7 connect out_rivalid[6], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_4) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[14], _out_rifireMux_T_11 connect out_rivalid[13], _out_rifireMux_T_11 connect out_rivalid[12], _out_rifireMux_T_11 connect out_rivalid[11], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_6) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[15], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[10], _out_wifireMux_T_8 connect out_wivalid[9], _out_wifireMux_T_8 connect out_wivalid[8], _out_wifireMux_T_8 connect out_wivalid[7], _out_wifireMux_T_8 connect out_wivalid[6], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_4) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[14], _out_wifireMux_T_12 connect out_wivalid[13], _out_wifireMux_T_12 connect out_wivalid[12], _out_wifireMux_T_12 connect out_wivalid[11], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_6) connect out_wifireMux_out_3, UInt<1>(0h1) connect out_wivalid[15], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[10], _out_rofireMux_T_7 connect out_roready[9], _out_rofireMux_T_7 connect out_roready[8], _out_rofireMux_T_7 connect out_roready[7], _out_rofireMux_T_7 connect out_roready[6], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_5) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[14], _out_rofireMux_T_11 connect out_roready[13], _out_rofireMux_T_11 connect out_roready[12], _out_rofireMux_T_11 connect out_roready[11], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_7) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[15], _out_rofireMux_T_15 node _out_rofireMux_T_16 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[10], _out_wofireMux_T_8 connect out_woready[9], _out_wofireMux_T_8 connect out_woready[8], _out_wofireMux_T_8 connect out_woready[7], _out_wofireMux_T_8 connect out_woready[6], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_5) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[14], _out_wofireMux_T_12 connect out_woready[13], _out_wofireMux_T_12 connect out_woready[12], _out_wofireMux_T_12 connect out_woready[11], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_7) connect out_wofireMux_out_3, UInt<1>(0h1) connect out_woready[15], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 connect _out_out_bits_data_WIRE[2], _out_T_5 connect _out_out_bits_data_WIRE[3], _out_T_7 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_61 connect _out_out_bits_data_WIRE_1[1], _out_T_116 connect _out_out_bits_data_WIRE_1[2], _out_T_156 connect _out_out_bits_data_WIRE_1[3], _out_T_167 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, controlNodeIn.a.valid connect controlNodeIn.a.ready, in.ready connect controlNodeIn.d.valid, out.valid connect out.ready, controlNodeIn.d.ready wire controlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect controlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect controlNodeIn_d_bits_d.param, UInt<1>(0h0) connect controlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect controlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect controlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect controlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate controlNodeIn_d_bits_d.data connect controlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect controlNodeIn.d.bits.corrupt, controlNodeIn_d_bits_d.corrupt connect controlNodeIn.d.bits.data, controlNodeIn_d_bits_d.data connect controlNodeIn.d.bits.denied, controlNodeIn_d_bits_d.denied connect controlNodeIn.d.bits.sink, controlNodeIn_d_bits_d.sink connect controlNodeIn.d.bits.source, controlNodeIn_d_bits_d.source connect controlNodeIn.d.bits.size, controlNodeIn_d_bits_d.size connect controlNodeIn.d.bits.param, controlNodeIn_d_bits_d.param connect controlNodeIn.d.bits.opcode, controlNodeIn_d_bits_d.opcode connect controlNodeIn.d.bits.data, out.bits.data node _controlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect controlNodeIn.d.bits.opcode, _controlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<14>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<14>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)	module TLUART( // @[UART.scala:127:25] input clock, // @[UART.scala:127:25] input reset, // @[UART.scala:127:25] output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_io_out_txd, // @[LazyModuleImp.scala:107:25] input auto_io_out_rxd // @[LazyModuleImp.scala:107:25] ); wire out_woready_2; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] wire out_backSel_0; // @[RegisterRouter.scala:87:24] wire quash; // @[RegisterRouter.scala:87:24] wire _rxq_io_deq_valid; // @[UART.scala:133:19] wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19] wire [3:0] _rxq_io_count; // @[UART.scala:133:19] wire _rxm_io_out_valid; // @[UART.scala:132:19] wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19] wire _txq_io_enq_ready; // @[UART.scala:130:19] wire _txq_io_deq_valid; // @[UART.scala:130:19] wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19] wire [3:0] _txq_io_count; // @[UART.scala:130:19] wire _txm_io_in_ready; // @[UART.scala:129:19] reg [15:0] div; // @[UART.scala:135:20] reg txen; // @[UART.scala:141:21] reg rxen; // @[UART.scala:142:21] reg [3:0] txwm; // @[UART.scala:149:21] reg [3:0] rxwm; // @[UART.scala:150:21] reg nstop; // @[UART.scala:151:22] reg ie_rxwm; // @[UART.scala:186:19] reg ie_txwm; // @[UART.scala:186:19] wire ip_txwm = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28] wire ip_rxwm = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28] wire in_bits_read = auto_control_xing_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_7 = auto_control_xing_in_a_bits_address[11:5] == 7'h0; // @[RegisterRouter.scala:75:19, :87:24] assign quash = out_woready_2 & auto_control_xing_in_a_bits_mask[3] & auto_control_xing_in_a_bits_data[31]; // @[RegisterRouter.scala:87:24] assign out_backSel_0 = auto_control_xing_in_a_bits_address[4:3] == 2'h0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = auto_control_xing_in_a_valid & auto_control_xing_in_d_ready; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] assign out_woready_2 = _out_wofireMux_T_2 & out_backSel_0 & _out_T_7; // @[RegisterRouter.scala:87:24] wire out_woready_9 = _out_wofireMux_T_2 & auto_control_xing_in_a_bits_address[4:3] == 2'h1 & _out_T_7; // @[RegisterRouter.scala:87:24] wire out_woready_12 = _out_wofireMux_T_2 & auto_control_xing_in_a_bits_address[4:3] == 2'h2 & _out_T_7; // @[RegisterRouter.scala:87:24] wire [3:0][63:0] _GEN = {{{48'h0, div}}, {{30'h0, ip_rxwm, ip_txwm, 30'h0, ie_rxwm, ie_txwm}}, {{12'h0, rxwm, 15'h0, rxen, 12'h0, txwm, 14'h0, nstop, txen}}, {{~_rxq_io_deq_valid, 23'h0, _rxq_io_deq_bits, ~_txq_io_enq_ready, 31'h0}}}; // @[MuxLiteral.scala:49:{10,48}] wire [2:0] controlXingIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] always @(posedge clock) begin // @[UART.scala:127:25] if (reset) begin // @[UART.scala:127:25] div <= 16'h10F4; // @[UART.scala:135:20] txen <= 1'h0; // @[UART.scala:127:25, :141:21] rxen <= 1'h0; // @[UART.scala:127:25, :142:21] txwm <= 4'h0; // @[UART.scala:149:21] rxwm <= 4'h0; // @[UART.scala:150:21] nstop <= 1'h0; // @[UART.scala:127:25, :151:22] ie_rxwm <= 1'h0; // @[UART.scala:127:25, :186:19] ie_txwm <= 1'h0; // @[UART.scala:127:25, :186:19] end else begin // @[UART.scala:127:25] if (_out_wofireMux_T_2 & (&(auto_control_xing_in_a_bits_address[4:3])) & _out_T_7 & (&{{8{auto_control_xing_in_a_bits_mask[1]}}, {8{auto_control_xing_in_a_bits_mask[0]}}})) // @[RegisterRouter.scala:87:24] div <= auto_control_xing_in_a_bits_data[15:0]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] txen <= auto_control_xing_in_a_bits_data[0]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[4]) // @[RegisterRouter.scala:87:24] rxen <= auto_control_xing_in_a_bits_data[32]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[2]) // @[RegisterRouter.scala:87:24] txwm <= auto_control_xing_in_a_bits_data[19:16]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[6]) // @[RegisterRouter.scala:87:24] rxwm <= auto_control_xing_in_a_bits_data[51:48]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] nstop <= auto_control_xing_in_a_bits_data[1]; // @[RegisterRouter.scala:87:24] if (out_woready_12 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] ie_rxwm <= auto_control_xing_in_a_bits_data[1]; // @[RegisterRouter.scala:87:24] if (out_woready_12 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] ie_txwm <= auto_control_xing_in_a_bits_data[0]; // @[RegisterRouter.scala:87:24] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_6 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] connect auto.out, nodeOut connect nodeIn, auto.in inst reg of AsyncResetRegVec_w1_i0_6 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] connect reg.io.en, UInt<1>(0h1) node _T = bits(reg.io.q, 0, 0) connect nodeOut.sync[0], _T	module IntSyncCrossingSource_n1x1_6( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_6 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SBToTL : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}} output io : { flip rdEn : UInt<1>, flip wrEn : UInt<1>, flip addrIn : UInt<128>, flip dataIn : UInt<128>, flip sizeIn : UInt<3>, rdLegal : UInt<1>, wrLegal : UInt<1>, rdDone : UInt<1>, wrDone : UInt<1>, respError : UInt<1>, dataOut : UInt<8>, rdLoad : UInt<1>[8], sbStateOut : UInt<3>} input rf_reset : Reset wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut regreset sbState : UInt, clock, reset, UInt<1>(0h0) inst d_q of Queue2_TLBundleD_a32d8s1k1z4u connect d_q.clock, clock connect d_q.reset, reset connect d_q.io.enq.valid, nodeOut.d.valid connect d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect d_q.io.enq.bits.data, nodeOut.d.bits.data connect d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect d_q.io.enq.bits.source, nodeOut.d.bits.source connect d_q.io.enq.bits.size, nodeOut.d.bits.size connect d_q.io.enq.bits.param, nodeOut.d.bits.param connect d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, d_q.io.enq.ready node _q_io_deq_ready_T = eq(sbState, UInt<2>(0h3)) node _q_io_deq_ready_T_1 = eq(sbState, UInt<3>(0h4)) node _q_io_deq_ready_T_2 = or(_q_io_deq_ready_T, _q_io_deq_ready_T_1) connect d_q.io.deq.ready, _q_io_deq_ready_T_2 wire muxedData : UInt<8> connect muxedData, UInt<8>(0h0) regreset counter : UInt<4>, clock, reset, UInt<4>(0h0) wire vecData : UInt<8>[8] node _vecData_0_T = bits(io.dataIn, 7, 0) connect vecData[0], _vecData_0_T node _vecData_1_T = bits(io.dataIn, 15, 8) connect vecData[1], _vecData_1_T node _vecData_2_T = bits(io.dataIn, 23, 16) connect vecData[2], _vecData_2_T node _vecData_3_T = bits(io.dataIn, 31, 24) connect vecData[3], _vecData_3_T node _vecData_4_T = bits(io.dataIn, 39, 32) connect vecData[4], _vecData_4_T node _vecData_5_T = bits(io.dataIn, 47, 40) connect vecData[5], _vecData_5_T node _vecData_6_T = bits(io.dataIn, 55, 48) connect vecData[6], _vecData_6_T node _vecData_7_T = bits(io.dataIn, 63, 56) connect vecData[7], _vecData_7_T node _muxedData_T = bits(counter, 2, 0) connect muxedData, vecData[_muxedData_T] node _rdLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _rdLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _rdLegal_addr_T_2 = and(_rdLegal_addr_T, _rdLegal_addr_T_1) node _rdLegal_addr_T_3 = or(UInt<1>(0h1), _rdLegal_addr_T_2) node _rdLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _rdLegal_addr_T_5 = cvt(_rdLegal_addr_T_4) node _rdLegal_addr_T_6 = and(_rdLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _rdLegal_addr_T_7 = asSInt(_rdLegal_addr_T_6) node _rdLegal_addr_T_8 = eq(_rdLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h3000)) node _rdLegal_addr_T_10 = cvt(_rdLegal_addr_T_9) node _rdLegal_addr_T_11 = and(_rdLegal_addr_T_10, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_12 = asSInt(_rdLegal_addr_T_11) node _rdLegal_addr_T_13 = eq(_rdLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_14 = xor(io.addrIn, UInt<17>(0h10000)) node _rdLegal_addr_T_15 = cvt(_rdLegal_addr_T_14) node _rdLegal_addr_T_16 = and(_rdLegal_addr_T_15, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_17 = asSInt(_rdLegal_addr_T_16) node _rdLegal_addr_T_18 = eq(_rdLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_19 = xor(io.addrIn, UInt<21>(0h100000)) node _rdLegal_addr_T_20 = cvt(_rdLegal_addr_T_19) node _rdLegal_addr_T_21 = and(_rdLegal_addr_T_20, asSInt(UInt<18>(0h2f000))) node _rdLegal_addr_T_22 = asSInt(_rdLegal_addr_T_21) node _rdLegal_addr_T_23 = eq(_rdLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_24 = xor(io.addrIn, UInt<26>(0h2000000)) node _rdLegal_addr_T_25 = cvt(_rdLegal_addr_T_24) node _rdLegal_addr_T_26 = and(_rdLegal_addr_T_25, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_27 = asSInt(_rdLegal_addr_T_26) node _rdLegal_addr_T_28 = eq(_rdLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_29 = xor(io.addrIn, UInt<28>(0hc000000)) node _rdLegal_addr_T_30 = cvt(_rdLegal_addr_T_29) node _rdLegal_addr_T_31 = and(_rdLegal_addr_T_30, asSInt(UInt<27>(0h4000000))) node _rdLegal_addr_T_32 = asSInt(_rdLegal_addr_T_31) node _rdLegal_addr_T_33 = eq(_rdLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_34 = xor(io.addrIn, UInt<29>(0h10020000)) node _rdLegal_addr_T_35 = cvt(_rdLegal_addr_T_34) node _rdLegal_addr_T_36 = and(_rdLegal_addr_T_35, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_37 = asSInt(_rdLegal_addr_T_36) node _rdLegal_addr_T_38 = eq(_rdLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_39 = xor(io.addrIn, UInt<32>(0h80000000)) node _rdLegal_addr_T_40 = cvt(_rdLegal_addr_T_39) node _rdLegal_addr_T_41 = and(_rdLegal_addr_T_40, asSInt(UInt<19>(0h40000))) node _rdLegal_addr_T_42 = asSInt(_rdLegal_addr_T_41) node _rdLegal_addr_T_43 = eq(_rdLegal_addr_T_42, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_44 = or(_rdLegal_addr_T_8, _rdLegal_addr_T_13) node _rdLegal_addr_T_45 = or(_rdLegal_addr_T_44, _rdLegal_addr_T_18) node _rdLegal_addr_T_46 = or(_rdLegal_addr_T_45, _rdLegal_addr_T_23) node _rdLegal_addr_T_47 = or(_rdLegal_addr_T_46, _rdLegal_addr_T_28) node _rdLegal_addr_T_48 = or(_rdLegal_addr_T_47, _rdLegal_addr_T_33) node _rdLegal_addr_T_49 = or(_rdLegal_addr_T_48, _rdLegal_addr_T_38) node _rdLegal_addr_T_50 = or(_rdLegal_addr_T_49, _rdLegal_addr_T_43) node _rdLegal_addr_T_51 = and(_rdLegal_addr_T_3, _rdLegal_addr_T_50) node rdLegal_addr = or(UInt<1>(0h0), _rdLegal_addr_T_51) node _wrLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _wrLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _wrLegal_addr_T_2 = and(_wrLegal_addr_T, _wrLegal_addr_T_1) node _wrLegal_addr_T_3 = or(UInt<1>(0h1), _wrLegal_addr_T_2) node _wrLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _wrLegal_addr_T_5 = cvt(_wrLegal_addr_T_4) node _wrLegal_addr_T_6 = and(_wrLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _wrLegal_addr_T_7 = asSInt(_wrLegal_addr_T_6) node _wrLegal_addr_T_8 = eq(_wrLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h3000)) node _wrLegal_addr_T_10 = cvt(_wrLegal_addr_T_9) node _wrLegal_addr_T_11 = and(_wrLegal_addr_T_10, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_12 = asSInt(_wrLegal_addr_T_11) node _wrLegal_addr_T_13 = eq(_wrLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_14 = xor(io.addrIn, UInt<21>(0h100000)) node _wrLegal_addr_T_15 = cvt(_wrLegal_addr_T_14) node _wrLegal_addr_T_16 = and(_wrLegal_addr_T_15, asSInt(UInt<18>(0h2f000))) node _wrLegal_addr_T_17 = asSInt(_wrLegal_addr_T_16) node _wrLegal_addr_T_18 = eq(_wrLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_19 = xor(io.addrIn, UInt<26>(0h2000000)) node _wrLegal_addr_T_20 = cvt(_wrLegal_addr_T_19) node _wrLegal_addr_T_21 = and(_wrLegal_addr_T_20, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_22 = asSInt(_wrLegal_addr_T_21) node _wrLegal_addr_T_23 = eq(_wrLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_24 = xor(io.addrIn, UInt<28>(0hc000000)) node _wrLegal_addr_T_25 = cvt(_wrLegal_addr_T_24) node _wrLegal_addr_T_26 = and(_wrLegal_addr_T_25, asSInt(UInt<27>(0h4000000))) node _wrLegal_addr_T_27 = asSInt(_wrLegal_addr_T_26) node _wrLegal_addr_T_28 = eq(_wrLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_29 = xor(io.addrIn, UInt<29>(0h10020000)) node _wrLegal_addr_T_30 = cvt(_wrLegal_addr_T_29) node _wrLegal_addr_T_31 = and(_wrLegal_addr_T_30, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_32 = asSInt(_wrLegal_addr_T_31) node _wrLegal_addr_T_33 = eq(_wrLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_34 = xor(io.addrIn, UInt<32>(0h80000000)) node _wrLegal_addr_T_35 = cvt(_wrLegal_addr_T_34) node _wrLegal_addr_T_36 = and(_wrLegal_addr_T_35, asSInt(UInt<19>(0h40000))) node _wrLegal_addr_T_37 = asSInt(_wrLegal_addr_T_36) node _wrLegal_addr_T_38 = eq(_wrLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_39 = or(_wrLegal_addr_T_8, _wrLegal_addr_T_13) node _wrLegal_addr_T_40 = or(_wrLegal_addr_T_39, _wrLegal_addr_T_18) node _wrLegal_addr_T_41 = or(_wrLegal_addr_T_40, _wrLegal_addr_T_23) node _wrLegal_addr_T_42 = or(_wrLegal_addr_T_41, _wrLegal_addr_T_28) node _wrLegal_addr_T_43 = or(_wrLegal_addr_T_42, _wrLegal_addr_T_33) node _wrLegal_addr_T_44 = or(_wrLegal_addr_T_43, _wrLegal_addr_T_38) node _wrLegal_addr_T_45 = and(_wrLegal_addr_T_3, _wrLegal_addr_T_44) node _wrLegal_addr_T_46 = or(UInt<1>(0h0), UInt<1>(0h0)) node _wrLegal_addr_T_47 = xor(io.addrIn, UInt<17>(0h10000)) node _wrLegal_addr_T_48 = cvt(_wrLegal_addr_T_47) node _wrLegal_addr_T_49 = and(_wrLegal_addr_T_48, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_50 = asSInt(_wrLegal_addr_T_49) node _wrLegal_addr_T_51 = eq(_wrLegal_addr_T_50, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_52 = and(_wrLegal_addr_T_46, _wrLegal_addr_T_51) node _wrLegal_addr_T_53 = or(UInt<1>(0h0), _wrLegal_addr_T_45) node wrLegal_addr = or(_wrLegal_addr_T_53, _wrLegal_addr_T_52) node _gbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _gbits_legal_T_2 = and(_gbits_legal_T, _gbits_legal_T_1) node _gbits_legal_T_3 = or(UInt<1>(0h0), _gbits_legal_T_2) node _gbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _gbits_legal_T_5 = cvt(_gbits_legal_T_4) node _gbits_legal_T_6 = and(_gbits_legal_T_5, asSInt(UInt<33>(0h8a113000))) node _gbits_legal_T_7 = asSInt(_gbits_legal_T_6) node _gbits_legal_T_8 = eq(_gbits_legal_T_7, asSInt(UInt<1>(0h0))) node _gbits_legal_T_9 = and(_gbits_legal_T_3, _gbits_legal_T_8) node _gbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _gbits_legal_T_12 = and(_gbits_legal_T_10, _gbits_legal_T_11) node _gbits_legal_T_13 = or(UInt<1>(0h0), _gbits_legal_T_12) node _gbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _gbits_legal_T_15 = cvt(_gbits_legal_T_14) node _gbits_legal_T_16 = and(_gbits_legal_T_15, asSInt(UInt<33>(0h8a112000))) node _gbits_legal_T_17 = asSInt(_gbits_legal_T_16) node _gbits_legal_T_18 = eq(_gbits_legal_T_17, asSInt(UInt<1>(0h0))) node _gbits_legal_T_19 = xor(io.addrIn, UInt<17>(0h10000)) node _gbits_legal_T_20 = cvt(_gbits_legal_T_19) node _gbits_legal_T_21 = and(_gbits_legal_T_20, asSInt(UInt<33>(0h8a110000))) node _gbits_legal_T_22 = asSInt(_gbits_legal_T_21) node _gbits_legal_T_23 = eq(_gbits_legal_T_22, asSInt(UInt<1>(0h0))) node _gbits_legal_T_24 = xor(io.addrIn, UInt<21>(0h100000)) node _gbits_legal_T_25 = cvt(_gbits_legal_T_24) node _gbits_legal_T_26 = and(_gbits_legal_T_25, asSInt(UInt<33>(0h8a103000))) node _gbits_legal_T_27 = asSInt(_gbits_legal_T_26) node _gbits_legal_T_28 = eq(_gbits_legal_T_27, asSInt(UInt<1>(0h0))) node _gbits_legal_T_29 = xor(io.addrIn, UInt<26>(0h2000000)) node _gbits_legal_T_30 = cvt(_gbits_legal_T_29) node _gbits_legal_T_31 = and(_gbits_legal_T_30, asSInt(UInt<33>(0h8a110000))) node _gbits_legal_T_32 = asSInt(_gbits_legal_T_31) node _gbits_legal_T_33 = eq(_gbits_legal_T_32, asSInt(UInt<1>(0h0))) node _gbits_legal_T_34 = xor(io.addrIn, UInt<28>(0h8000000)) node _gbits_legal_T_35 = cvt(_gbits_legal_T_34) node _gbits_legal_T_36 = and(_gbits_legal_T_35, asSInt(UInt<33>(0h88000000))) node _gbits_legal_T_37 = asSInt(_gbits_legal_T_36) node _gbits_legal_T_38 = eq(_gbits_legal_T_37, asSInt(UInt<1>(0h0))) node _gbits_legal_T_39 = xor(io.addrIn, UInt<32>(0h80000000)) node _gbits_legal_T_40 = cvt(_gbits_legal_T_39) node _gbits_legal_T_41 = and(_gbits_legal_T_40, asSInt(UInt<33>(0h8a100000))) node _gbits_legal_T_42 = asSInt(_gbits_legal_T_41) node _gbits_legal_T_43 = eq(_gbits_legal_T_42, asSInt(UInt<1>(0h0))) node _gbits_legal_T_44 = or(_gbits_legal_T_18, _gbits_legal_T_23) node _gbits_legal_T_45 = or(_gbits_legal_T_44, _gbits_legal_T_28) node _gbits_legal_T_46 = or(_gbits_legal_T_45, _gbits_legal_T_33) node _gbits_legal_T_47 = or(_gbits_legal_T_46, _gbits_legal_T_38) node _gbits_legal_T_48 = or(_gbits_legal_T_47, _gbits_legal_T_43) node _gbits_legal_T_49 = and(_gbits_legal_T_13, _gbits_legal_T_48) node _gbits_legal_T_50 = or(UInt<1>(0h0), _gbits_legal_T_9) node gbits_legal = or(_gbits_legal_T_50, _gbits_legal_T_49) wire gbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect gbits.opcode, UInt<3>(0h4) connect gbits.param, UInt<1>(0h0) connect gbits.size, io.sizeIn connect gbits.source, UInt<1>(0h0) connect gbits.address, io.addrIn node _gbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node gbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect gbits.mask, UInt<1>(0h1) invalidate gbits.data connect gbits.corrupt, UInt<1>(0h0) node _pfbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _pfbits_legal_T_2 = and(_pfbits_legal_T, _pfbits_legal_T_1) node _pfbits_legal_T_3 = or(UInt<1>(0h0), _pfbits_legal_T_2) node _pfbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _pfbits_legal_T_5 = cvt(_pfbits_legal_T_4) node _pfbits_legal_T_6 = and(_pfbits_legal_T_5, asSInt(UInt<33>(0h8a113000))) node _pfbits_legal_T_7 = asSInt(_pfbits_legal_T_6) node _pfbits_legal_T_8 = eq(_pfbits_legal_T_7, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_9 = and(_pfbits_legal_T_3, _pfbits_legal_T_8) node _pfbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _pfbits_legal_T_12 = and(_pfbits_legal_T_10, _pfbits_legal_T_11) node _pfbits_legal_T_13 = or(UInt<1>(0h0), _pfbits_legal_T_12) node _pfbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _pfbits_legal_T_15 = cvt(_pfbits_legal_T_14) node _pfbits_legal_T_16 = and(_pfbits_legal_T_15, asSInt(UInt<33>(0h8a112000))) node _pfbits_legal_T_17 = asSInt(_pfbits_legal_T_16) node _pfbits_legal_T_18 = eq(_pfbits_legal_T_17, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_19 = xor(io.addrIn, UInt<21>(0h100000)) node _pfbits_legal_T_20 = cvt(_pfbits_legal_T_19) node _pfbits_legal_T_21 = and(_pfbits_legal_T_20, asSInt(UInt<33>(0h8a103000))) node _pfbits_legal_T_22 = asSInt(_pfbits_legal_T_21) node _pfbits_legal_T_23 = eq(_pfbits_legal_T_22, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_24 = xor(io.addrIn, UInt<26>(0h2000000)) node _pfbits_legal_T_25 = cvt(_pfbits_legal_T_24) node _pfbits_legal_T_26 = and(_pfbits_legal_T_25, asSInt(UInt<33>(0h8a110000))) node _pfbits_legal_T_27 = asSInt(_pfbits_legal_T_26) node _pfbits_legal_T_28 = eq(_pfbits_legal_T_27, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_29 = xor(io.addrIn, UInt<28>(0h8000000)) node _pfbits_legal_T_30 = cvt(_pfbits_legal_T_29) node _pfbits_legal_T_31 = and(_pfbits_legal_T_30, asSInt(UInt<33>(0h88000000))) node _pfbits_legal_T_32 = asSInt(_pfbits_legal_T_31) node _pfbits_legal_T_33 = eq(_pfbits_legal_T_32, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_34 = xor(io.addrIn, UInt<32>(0h80000000)) node _pfbits_legal_T_35 = cvt(_pfbits_legal_T_34) node _pfbits_legal_T_36 = and(_pfbits_legal_T_35, asSInt(UInt<33>(0h8a100000))) node _pfbits_legal_T_37 = asSInt(_pfbits_legal_T_36) node _pfbits_legal_T_38 = eq(_pfbits_legal_T_37, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_39 = or(_pfbits_legal_T_18, _pfbits_legal_T_23) node _pfbits_legal_T_40 = or(_pfbits_legal_T_39, _pfbits_legal_T_28) node _pfbits_legal_T_41 = or(_pfbits_legal_T_40, _pfbits_legal_T_33) node _pfbits_legal_T_42 = or(_pfbits_legal_T_41, _pfbits_legal_T_38) node _pfbits_legal_T_43 = and(_pfbits_legal_T_13, _pfbits_legal_T_42) node _pfbits_legal_T_44 = or(UInt<1>(0h0), UInt<1>(0h0)) node _pfbits_legal_T_45 = xor(io.addrIn, UInt<17>(0h10000)) node _pfbits_legal_T_46 = cvt(_pfbits_legal_T_45) node _pfbits_legal_T_47 = and(_pfbits_legal_T_46, asSInt(UInt<33>(0h8a110000))) node _pfbits_legal_T_48 = asSInt(_pfbits_legal_T_47) node _pfbits_legal_T_49 = eq(_pfbits_legal_T_48, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_50 = and(_pfbits_legal_T_44, _pfbits_legal_T_49) node _pfbits_legal_T_51 = or(UInt<1>(0h0), _pfbits_legal_T_9) node _pfbits_legal_T_52 = or(_pfbits_legal_T_51, _pfbits_legal_T_43) node pfbits_legal = or(_pfbits_legal_T_52, _pfbits_legal_T_50) wire pfbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect pfbits.opcode, UInt<1>(0h0) connect pfbits.param, UInt<1>(0h0) connect pfbits.size, io.sizeIn connect pfbits.source, UInt<1>(0h0) connect pfbits.address, io.addrIn node _pfbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node pfbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect pfbits.mask, UInt<1>(0h1) connect pfbits.data, muxedData connect pfbits.corrupt, UInt<1>(0h0) connect io.rdLegal, rdLegal_addr connect io.wrLegal, wrLegal_addr connect io.sbStateOut, sbState node _T = eq(sbState, UInt<1>(0h1)) when _T : connect nodeOut.a.bits, gbits else : connect nodeOut.a.bits, pfbits node respError = or(d_q.io.deq.bits.denied, d_q.io.deq.bits.corrupt) connect io.respError, respError node _wrTxValid_T = eq(sbState, UInt<2>(0h2)) node _wrTxValid_T_1 = and(_wrTxValid_T, nodeOut.a.valid) node wrTxValid = and(_wrTxValid_T_1, nodeOut.a.ready) node _rdTxValid_T = eq(sbState, UInt<2>(0h3)) node _rdTxValid_T_1 = and(_rdTxValid_T, d_q.io.deq.valid) node rdTxValid = and(_rdTxValid_T_1, d_q.io.deq.ready) node _txLast_T = dshl(UInt<1>(0h1), io.sizeIn) node _txLast_T_1 = sub(_txLast_T, UInt<1>(0h1)) node _txLast_T_2 = tail(_txLast_T_1, 1) node txLast = eq(counter, _txLast_T_2) node _counter_T = or(wrTxValid, rdTxValid) node _counter_T_1 = and(_counter_T, txLast) node _counter_T_2 = or(wrTxValid, rdTxValid) node _counter_T_3 = add(counter, UInt<1>(0h1)) node _counter_T_4 = tail(_counter_T_3, 1) node _counter_T_5 = mux(_counter_T_2, _counter_T_4, counter) node _counter_T_6 = mux(_counter_T_1, UInt<1>(0h0), _counter_T_5) connect counter, _counter_T_6 node _io_rdLoad_0_T = eq(counter, UInt<1>(0h0)) node _io_rdLoad_0_T_1 = and(rdTxValid, _io_rdLoad_0_T) connect io.rdLoad[0], _io_rdLoad_0_T_1 node _io_rdLoad_1_T = eq(counter, UInt<1>(0h1)) node _io_rdLoad_1_T_1 = and(rdTxValid, _io_rdLoad_1_T) connect io.rdLoad[1], _io_rdLoad_1_T_1 node _io_rdLoad_2_T = eq(counter, UInt<2>(0h2)) node _io_rdLoad_2_T_1 = and(rdTxValid, _io_rdLoad_2_T) connect io.rdLoad[2], _io_rdLoad_2_T_1 node _io_rdLoad_3_T = eq(counter, UInt<2>(0h3)) node _io_rdLoad_3_T_1 = and(rdTxValid, _io_rdLoad_3_T) connect io.rdLoad[3], _io_rdLoad_3_T_1 node _io_rdLoad_4_T = eq(counter, UInt<3>(0h4)) node _io_rdLoad_4_T_1 = and(rdTxValid, _io_rdLoad_4_T) connect io.rdLoad[4], _io_rdLoad_4_T_1 node _io_rdLoad_5_T = eq(counter, UInt<3>(0h5)) node _io_rdLoad_5_T_1 = and(rdTxValid, _io_rdLoad_5_T) connect io.rdLoad[5], _io_rdLoad_5_T_1 node _io_rdLoad_6_T = eq(counter, UInt<3>(0h6)) node _io_rdLoad_6_T_1 = and(rdTxValid, _io_rdLoad_6_T) connect io.rdLoad[6], _io_rdLoad_6_T_1 node _io_rdLoad_7_T = eq(counter, UInt<3>(0h7)) node _io_rdLoad_7_T_1 = and(rdTxValid, _io_rdLoad_7_T) connect io.rdLoad[7], _io_rdLoad_7_T_1 node _T_1 = eq(sbState, UInt<1>(0h0)) when _T_1 : node _sbState_T = and(io.rdEn, io.rdLegal) node _sbState_T_1 = and(io.wrEn, io.wrLegal) node _sbState_T_2 = mux(_sbState_T_1, UInt<2>(0h2), sbState) node _sbState_T_3 = mux(_sbState_T, UInt<1>(0h1), _sbState_T_2) connect sbState, _sbState_T_3 else : node _T_2 = eq(sbState, UInt<1>(0h1)) when _T_2 : node _sbState_T_4 = and(nodeOut.a.valid, nodeOut.a.ready) node _sbState_T_5 = mux(_sbState_T_4, UInt<2>(0h3), sbState) connect sbState, _sbState_T_5 else : node _T_3 = eq(sbState, UInt<2>(0h2)) when _T_3 : node _sbState_T_6 = and(wrTxValid, txLast) node _sbState_T_7 = mux(_sbState_T_6, UInt<3>(0h4), sbState) connect sbState, _sbState_T_7 else : node _T_4 = eq(sbState, UInt<2>(0h3)) when _T_4 : node _sbState_T_8 = and(rdTxValid, txLast) node _sbState_T_9 = mux(_sbState_T_8, UInt<1>(0h0), sbState) connect sbState, _sbState_T_9 else : node _T_5 = eq(sbState, UInt<3>(0h4)) when _T_5 : node _sbState_T_10 = and(d_q.io.deq.valid, d_q.io.deq.ready) node _sbState_T_11 = mux(_sbState_T_10, UInt<1>(0h0), sbState) connect sbState, _sbState_T_11 node _io_rdDone_T = and(rdTxValid, txLast) connect io.rdDone, _io_rdDone_T node _io_wrDone_T = eq(sbState, UInt<3>(0h4)) node _io_wrDone_T_1 = and(_io_wrDone_T, d_q.io.deq.valid) node _io_wrDone_T_2 = and(_io_wrDone_T_1, d_q.io.deq.ready) connect io.wrDone, _io_wrDone_T_2 connect io.dataOut, d_q.io.deq.bits.data node _nodeOut_a_valid_T = eq(sbState, UInt<1>(0h1)) node _nodeOut_a_valid_T_1 = eq(sbState, UInt<2>(0h2)) node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<8>(0h0) connect _WIRE.bits.mask, UInt<1>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) node _T_6 = eq(sbState, UInt<1>(0h0)) node _T_7 = eq(sbState, UInt<1>(0h1)) node _T_8 = or(_T_6, _T_7) node _T_9 = eq(sbState, UInt<2>(0h2)) node _T_10 = or(_T_8, _T_9) node _T_11 = eq(sbState, UInt<2>(0h3)) node _T_12 = or(_T_10, _T_11) node _T_13 = eq(sbState, UInt<3>(0h4)) node _T_14 = or(_T_12, _T_13) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed: SBA state machine in undefined state\n at SBA.scala:373 assert (sbState === Idle.id.U \|\|\n") : printf assert(clock, _T_14, UInt<1>(0h1), "") : assert node _T_18 = eq(sbState, UInt<1>(0h0)) node _T_19 = eq(sbState, UInt<1>(0h1)) node _T_20 = eq(sbState, UInt<2>(0h2)) node _T_21 = eq(sbState, UInt<2>(0h3)) node _T_22 = eq(sbState, UInt<3>(0h4)) node _T_23 = eq(io.rdLegal, UInt<1>(0h0)) node _T_24 = and(io.rdEn, _T_23) node _T_25 = eq(io.wrLegal, UInt<1>(0h0)) node _T_26 = and(io.wrEn, _T_25) extmodule plusarg_reader_74 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_75 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module SBToTL( // @[SBA.scala:273:9] input clock, // @[SBA.scala:273:9] input reset, // @[SBA.scala:273:9] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_rdEn, // @[SBA.scala:274:16] input io_wrEn, // @[SBA.scala:274:16] input [127:0] io_addrIn, // @[SBA.scala:274:16] input [127:0] io_dataIn, // @[SBA.scala:274:16] input [2:0] io_sizeIn, // @[SBA.scala:274:16] output io_rdLegal, // @[SBA.scala:274:16] output io_wrLegal, // @[SBA.scala:274:16] output io_rdDone, // @[SBA.scala:274:16] output io_wrDone, // @[SBA.scala:274:16] output io_respError, // @[SBA.scala:274:16] output [7:0] io_dataOut, // @[SBA.scala:274:16] output io_rdLoad_0, // @[SBA.scala:274:16] output io_rdLoad_1, // @[SBA.scala:274:16] output io_rdLoad_2, // @[SBA.scala:274:16] output io_rdLoad_3, // @[SBA.scala:274:16] output io_rdLoad_4, // @[SBA.scala:274:16] output io_rdLoad_5, // @[SBA.scala:274:16] output io_rdLoad_6, // @[SBA.scala:274:16] output io_rdLoad_7, // @[SBA.scala:274:16] output [2:0] io_sbStateOut, // @[SBA.scala:274:16] input rf_reset // @[SBA.scala:289:28] ); wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire auto_out_a_ready_0 = auto_out_a_ready; // @[SBA.scala:273:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[SBA.scala:273:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[SBA.scala:273:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[SBA.scala:273:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[SBA.scala:273:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[SBA.scala:273:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[SBA.scala:273:9] wire [7:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[SBA.scala:273:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[SBA.scala:273:9] wire io_rdEn_0 = io_rdEn; // @[SBA.scala:273:9] wire io_wrEn_0 = io_wrEn; // @[SBA.scala:273:9] wire [127:0] io_addrIn_0 = io_addrIn; // @[SBA.scala:273:9] wire [127:0] io_dataIn_0 = io_dataIn; // @[SBA.scala:273:9] wire [2:0] io_sizeIn_0 = io_sizeIn; // @[SBA.scala:273:9] wire auto_out_a_bits_source = 1'h0; // @[SBA.scala:273:9] wire auto_out_a_bits_corrupt = 1'h0; // @[SBA.scala:273:9] wire auto_out_d_bits_source = 1'h0; // @[SBA.scala:273:9] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire _wrLegal_addr_T_46 = 1'h0; // @[Parameters.scala:684:29] wire _wrLegal_addr_T_52 = 1'h0; // @[Parameters.scala:684:54] wire gbits_source = 1'h0; // @[Edges.scala:460:17] wire gbits_corrupt = 1'h0; // @[Edges.scala:460:17] wire _pfbits_legal_T_44 = 1'h0; // @[Parameters.scala:684:29] wire _pfbits_legal_T_50 = 1'h0; // @[Parameters.scala:684:54] wire pfbits_source = 1'h0; // @[Edges.scala:480:17] wire pfbits_corrupt = 1'h0; // @[Edges.scala:480:17] wire [2:0] auto_out_a_bits_param = 3'h0; // @[SBA.scala:273:9] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] gbits_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] pfbits_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] pfbits_param = 3'h0; // @[Edges.scala:480:17] wire auto_out_a_bits_mask = 1'h1; // @[SBA.scala:273:9] wire nodeOut_a_bits_mask = 1'h1; // @[MixedNode.scala:542:17] wire _rdLegal_addr_T = 1'h1; // @[Parameters.scala:92:28] wire _rdLegal_addr_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _wrLegal_addr_T = 1'h1; // @[Parameters.scala:92:28] wire _wrLegal_addr_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _gbits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _gbits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _gbits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _gbits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _gbits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire gbits_mask = 1'h1; // @[Edges.scala:460:17] wire gbits_a_mask_sizeOH = 1'h1; // @[Misc.scala:202:81] wire _pfbits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _pfbits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _pfbits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _pfbits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _pfbits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire pfbits_mask = 1'h1; // @[Edges.scala:480:17] wire pfbits_a_mask_sizeOH = 1'h1; // @[Misc.scala:202:81] wire [7:0] gbits_data = 8'h0; // @[Edges.scala:460:17] wire [2:0] gbits_opcode = 3'h4; // @[Edges.scala:460:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[SBA.scala:273:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[SBA.scala:273:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[SBA.scala:273:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[SBA.scala:273:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[SBA.scala:273:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[SBA.scala:273:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[SBA.scala:273:9] wire [7:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[SBA.scala:273:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[SBA.scala:273:9] wire [127:0] _rdLegal_addr_T_4 = io_addrIn_0; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_4 = io_addrIn_0; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_14 = io_addrIn_0; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_14 = io_addrIn_0; // @[Parameters.scala:137:31] wire rdLegal_addr; // @[Parameters.scala:686:26] wire [2:0] _gbits_a_mask_sizeOH_T = io_sizeIn_0; // @[Misc.scala:202:34] wire [2:0] _pfbits_a_mask_sizeOH_T = io_sizeIn_0; // @[Misc.scala:202:34] wire wrLegal_addr; // @[Parameters.scala:686:26] wire _io_rdDone_T; // @[SBA.scala:362:29] wire _io_wrDone_T_2; // @[SBA.scala:363:71] wire respError; // @[SBA.scala:335:35] wire _io_rdLoad_0_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_1_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_2_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_3_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_4_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_5_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_6_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_7_T_1; // @[SBA.scala:345:33] wire [2:0] auto_out_a_bits_opcode_0; // @[SBA.scala:273:9] wire [3:0] auto_out_a_bits_size_0; // @[SBA.scala:273:9] wire [31:0] auto_out_a_bits_address_0; // @[SBA.scala:273:9] wire [7:0] auto_out_a_bits_data_0; // @[SBA.scala:273:9] wire auto_out_a_valid_0; // @[SBA.scala:273:9] wire auto_out_d_ready_0; // @[SBA.scala:273:9] wire io_rdLoad_0_0; // @[SBA.scala:273:9] wire io_rdLoad_1_0; // @[SBA.scala:273:9] wire io_rdLoad_2_0; // @[SBA.scala:273:9] wire io_rdLoad_3_0; // @[SBA.scala:273:9] wire io_rdLoad_4_0; // @[SBA.scala:273:9] wire io_rdLoad_5_0; // @[SBA.scala:273:9] wire io_rdLoad_6_0; // @[SBA.scala:273:9] wire io_rdLoad_7_0; // @[SBA.scala:273:9] wire io_rdLegal_0; // @[SBA.scala:273:9] wire io_wrLegal_0; // @[SBA.scala:273:9] wire io_rdDone_0; // @[SBA.scala:273:9] wire io_wrDone_0; // @[SBA.scala:273:9] wire io_respError_0; // @[SBA.scala:273:9] wire [7:0] io_dataOut_0; // @[SBA.scala:273:9] wire [2:0] io_sbStateOut_0; // @[SBA.scala:273:9] wire _nodeOut_a_valid_T_2; // @[SBA.scala:366:52] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[SBA.scala:273:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[SBA.scala:273:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[SBA.scala:273:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[SBA.scala:273:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[SBA.scala:273:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[SBA.scala:273:9] reg [2:0] sbState; // @[SBA.scala:295:26] assign io_sbStateOut_0 = sbState; // @[SBA.scala:273:9, :295:26] wire _T_21 = sbState == 3'h3; // @[SBA.scala:295:26, :299:25] wire _q_io_deq_ready_T; // @[SBA.scala:299:25] assign _q_io_deq_ready_T = _T_21; // @[SBA.scala:299:25] wire _rdTxValid_T; // @[SBA.scala:339:29] assign _rdTxValid_T = _T_21; // @[SBA.scala:299:25, :339:29] wire _T_22 = sbState == 3'h4; // @[SBA.scala:295:26, :299:62] wire _q_io_deq_ready_T_1; // @[SBA.scala:299:62] assign _q_io_deq_ready_T_1 = _T_22; // @[SBA.scala:299:62] wire _io_wrDone_T; // @[SBA.scala:363:28] assign _io_wrDone_T = _T_22; // @[SBA.scala:299:62, :363:28] wire _q_io_deq_ready_T_2 = _q_io_deq_ready_T \| _q_io_deq_ready_T_1; // @[SBA.scala:299:{25,50,62}] wire [7:0] muxedData; // @[SBA.scala:301:29] wire [7:0] pfbits_data = muxedData; // @[Edges.scala:480:17] reg [3:0] counter; // @[SBA.scala:307:26] wire [7:0] _vecData_0_T; // @[SBA.scala:309:63] wire [7:0] _vecData_1_T; // @[SBA.scala:309:63] wire [7:0] _vecData_2_T; // @[SBA.scala:309:63] wire [7:0] _vecData_3_T; // @[SBA.scala:309:63] wire [7:0] _vecData_4_T; // @[SBA.scala:309:63] wire [7:0] _vecData_5_T; // @[SBA.scala:309:63] wire [7:0] _vecData_6_T; // @[SBA.scala:309:63] wire [7:0] _vecData_7_T; // @[SBA.scala:309:63] wire [7:0] vecData_0; // @[SBA.scala:308:25] wire [7:0] vecData_1; // @[SBA.scala:308:25] wire [7:0] vecData_2; // @[SBA.scala:308:25] wire [7:0] vecData_3; // @[SBA.scala:308:25] wire [7:0] vecData_4; // @[SBA.scala:308:25] wire [7:0] vecData_5; // @[SBA.scala:308:25] wire [7:0] vecData_6; // @[SBA.scala:308:25] wire [7:0] vecData_7; // @[SBA.scala:308:25] assign _vecData_0_T = io_dataIn_0[7:0]; // @[SBA.scala:273:9, :309:63] assign vecData_0 = _vecData_0_T; // @[SBA.scala:308:25, :309:63] assign _vecData_1_T = io_dataIn_0[15:8]; // @[SBA.scala:273:9, :309:63] assign vecData_1 = _vecData_1_T; // @[SBA.scala:308:25, :309:63] assign _vecData_2_T = io_dataIn_0[23:16]; // @[SBA.scala:273:9, :309:63] assign vecData_2 = _vecData_2_T; // @[SBA.scala:308:25, :309:63] assign _vecData_3_T = io_dataIn_0[31:24]; // @[SBA.scala:273:9, :309:63] assign vecData_3 = _vecData_3_T; // @[SBA.scala:308:25, :309:63] assign _vecData_4_T = io_dataIn_0[39:32]; // @[SBA.scala:273:9, :309:63] assign vecData_4 = _vecData_4_T; // @[SBA.scala:308:25, :309:63] assign _vecData_5_T = io_dataIn_0[47:40]; // @[SBA.scala:273:9, :309:63] assign vecData_5 = _vecData_5_T; // @[SBA.scala:308:25, :309:63] assign _vecData_6_T = io_dataIn_0[55:48]; // @[SBA.scala:273:9, :309:63] assign vecData_6 = _vecData_6_T; // @[SBA.scala:308:25, :309:63] assign _vecData_7_T = io_dataIn_0[63:56]; // @[SBA.scala:273:9, :309:63] assign vecData_7 = _vecData_7_T; // @[SBA.scala:308:25, :309:63] wire [2:0] _muxedData_T = counter[2:0]; // @[SBA.scala:307:26, :310:33] wire [7:0][7:0] _GEN = {{vecData_7}, {vecData_6}, {vecData_5}, {vecData_4}, {vecData_3}, {vecData_2}, {vecData_1}, {vecData_0}}; // @[SBA.scala:308:25, :310:15] assign muxedData = _GEN[_muxedData_T]; // @[SBA.scala:301:29, :310:{15,33}] wire _rdLegal_addr_T_1 = ~(io_sizeIn_0[2]); // @[Parameters.scala:92:38] wire _rdLegal_addr_T_2 = _rdLegal_addr_T_1; // @[Parameters.scala:92:{33,38}] wire [128:0] _rdLegal_addr_T_5 = {1'h0, _rdLegal_addr_T_4}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_6 = _rdLegal_addr_T_5 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_7 = _rdLegal_addr_T_6; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_8 = _rdLegal_addr_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_0 = {io_addrIn_0[127:14], io_addrIn_0[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_9; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_9 = _GEN_0; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_9; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_9 = _GEN_0; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_4; // @[Parameters.scala:137:31] assign _gbits_legal_T_4 = _GEN_0; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_4; // @[Parameters.scala:137:31] assign _pfbits_legal_T_4 = _GEN_0; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_10 = {1'h0, _rdLegal_addr_T_9}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_11 = _rdLegal_addr_T_10 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_12 = _rdLegal_addr_T_11; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_13 = _rdLegal_addr_T_12 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_1 = {io_addrIn_0[127:17], io_addrIn_0[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_14; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_14 = _GEN_1; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_47; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_19; // @[Parameters.scala:137:31] assign _gbits_legal_T_19 = _GEN_1; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_45; // @[Parameters.scala:137:31] assign _pfbits_legal_T_45 = _GEN_1; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_15 = {1'h0, _rdLegal_addr_T_14}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_16 = _rdLegal_addr_T_15 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_17 = _rdLegal_addr_T_16; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_18 = _rdLegal_addr_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_2 = {io_addrIn_0[127:21], io_addrIn_0[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_19; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_19 = _GEN_2; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_14; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_14 = _GEN_2; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_24; // @[Parameters.scala:137:31] assign _gbits_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_19; // @[Parameters.scala:137:31] assign _pfbits_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_20 = {1'h0, _rdLegal_addr_T_19}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_21 = _rdLegal_addr_T_20 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_22 = _rdLegal_addr_T_21; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_23 = _rdLegal_addr_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_3 = {io_addrIn_0[127:26], io_addrIn_0[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_24; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_24 = _GEN_3; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_19; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_19 = _GEN_3; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_29; // @[Parameters.scala:137:31] assign _gbits_legal_T_29 = _GEN_3; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_24; // @[Parameters.scala:137:31] assign _pfbits_legal_T_24 = _GEN_3; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_25 = {1'h0, _rdLegal_addr_T_24}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_26 = _rdLegal_addr_T_25 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_27 = _rdLegal_addr_T_26; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_28 = _rdLegal_addr_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_4 = {io_addrIn_0[127:28], io_addrIn_0[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_29; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_29 = _GEN_4; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_24; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_24 = _GEN_4; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_30 = {1'h0, _rdLegal_addr_T_29}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_31 = _rdLegal_addr_T_30 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_32 = _rdLegal_addr_T_31; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_33 = _rdLegal_addr_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_5 = {io_addrIn_0[127:29], io_addrIn_0[28:0] ^ 29'h10020000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_34; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_34 = _GEN_5; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_29; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_29 = _GEN_5; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_35 = {1'h0, _rdLegal_addr_T_34}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_36 = _rdLegal_addr_T_35 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_37 = _rdLegal_addr_T_36; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_38 = _rdLegal_addr_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] gbits_address = io_addrIn_0[31:0]; // @[Edges.scala:460:17] wire [31:0] pfbits_address = io_addrIn_0[31:0]; // @[Edges.scala:480:17] wire [127:0] _GEN_6 = {io_addrIn_0[127:32], io_addrIn_0[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_39; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_39 = _GEN_6; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_34; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_34 = _GEN_6; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_39; // @[Parameters.scala:137:31] assign _gbits_legal_T_39 = _GEN_6; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_34; // @[Parameters.scala:137:31] assign _pfbits_legal_T_34 = _GEN_6; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_40 = {1'h0, _rdLegal_addr_T_39}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_41 = _rdLegal_addr_T_40 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFC0000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_42 = _rdLegal_addr_T_41; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_43 = _rdLegal_addr_T_42 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _rdLegal_addr_T_44 = _rdLegal_addr_T_8 \| _rdLegal_addr_T_13; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_45 = _rdLegal_addr_T_44 \| _rdLegal_addr_T_18; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_46 = _rdLegal_addr_T_45 \| _rdLegal_addr_T_23; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_47 = _rdLegal_addr_T_46 \| _rdLegal_addr_T_28; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_48 = _rdLegal_addr_T_47 \| _rdLegal_addr_T_33; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_49 = _rdLegal_addr_T_48 \| _rdLegal_addr_T_38; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_50 = _rdLegal_addr_T_49 \| _rdLegal_addr_T_43; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_51 = _rdLegal_addr_T_50; // @[Parameters.scala:684:54, :685:42] assign rdLegal_addr = _rdLegal_addr_T_51; // @[Parameters.scala:684:54, :686:26] assign io_rdLegal_0 = rdLegal_addr; // @[Parameters.scala:686:26] wire _wrLegal_addr_T_1 = ~(io_sizeIn_0[2]); // @[Parameters.scala:92:38] wire _wrLegal_addr_T_2 = _wrLegal_addr_T_1; // @[Parameters.scala:92:{33,38}] wire [128:0] _wrLegal_addr_T_5 = {1'h0, _wrLegal_addr_T_4}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_6 = _wrLegal_addr_T_5 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_7 = _wrLegal_addr_T_6; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_8 = _wrLegal_addr_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _wrLegal_addr_T_10 = {1'h0, _wrLegal_addr_T_9}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_11 = _wrLegal_addr_T_10 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_12 = _wrLegal_addr_T_11; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_13 = _wrLegal_addr_T_12 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _wrLegal_addr_T_15 = {1'h0, _wrLegal_addr_T_14}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_16 = _wrLegal_addr_T_15 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_17 = _wrLegal_addr_T_16; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_18 = _wrLegal_addr_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _wrLegal_addr_T_20 = {1'h0, _wrLegal_addr_T_19}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_21 = _wrLegal_addr_T_20 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_22 = _wrLegal_addr_T_21; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_23 = _wrLegal_addr_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _wrLegal_addr_T_25 = {1'h0, _wrLegal_addr_T_24}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_26 = _wrLegal_addr_T_25 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_27 = _wrLegal_addr_T_26; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_28 = _wrLegal_addr_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _wrLegal_addr_T_30 = {1'h0, _wrLegal_addr_T_29}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_31 = _wrLegal_addr_T_30 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_32 = _wrLegal_addr_T_31; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_33 = _wrLegal_addr_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _wrLegal_addr_T_35 = {1'h0, _wrLegal_addr_T_34}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_36 = _wrLegal_addr_T_35 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFC0000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_37 = _wrLegal_addr_T_36; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_38 = _wrLegal_addr_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _wrLegal_addr_T_39 = _wrLegal_addr_T_8 \| _wrLegal_addr_T_13; // @[Parameters.scala:685:42] wire _wrLegal_addr_T_40 = _wrLegal_addr_T_39 \| _wrLegal_addr_T_18; // @[Parameters.scala:685:42] wire _wrLegal_addr_T_41 = _wrLegal_addr_T_40 \| _wrLegal_addr_T_23; // @[Parameters.scala:685:42] wire _wrLegal_addr_T_42 = _wrLegal_addr_T_41 \| _wrLegal_addr_T_28; // @[Parameters.scala:685:42] wire _wrLegal_addr_T_43 = _wrLegal_addr_T_42 \| _wrLegal_addr_T_33; // @[Parameters.scala:685:42] wire _wrLegal_addr_T_44 = _wrLegal_addr_T_43 \| _wrLegal_addr_T_38; // @[Parameters.scala:685:42] wire _wrLegal_addr_T_45 = _wrLegal_addr_T_44; // @[Parameters.scala:684:54, :685:42] wire _wrLegal_addr_T_53 = _wrLegal_addr_T_45; // @[Parameters.scala:684:54, :686:26] wire [128:0] _wrLegal_addr_T_48 = {1'h0, _wrLegal_addr_T_47}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_49 = _wrLegal_addr_T_48 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_50 = _wrLegal_addr_T_49; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_51 = _wrLegal_addr_T_50 == 129'h0; // @[Parameters.scala:137:{46,59}] assign wrLegal_addr = _wrLegal_addr_T_53; // @[Parameters.scala:686:26] assign io_wrLegal_0 = wrLegal_addr; // @[Parameters.scala:686:26] wire [128:0] _gbits_legal_T_5 = {1'h0, _gbits_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_6 = _gbits_legal_T_5 & 129'h8A113000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_7 = _gbits_legal_T_6; // @[Parameters.scala:137:46] wire _gbits_legal_T_8 = _gbits_legal_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _gbits_legal_T_9 = _gbits_legal_T_8; // @[Parameters.scala:684:54] wire _gbits_legal_T_50 = _gbits_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _GEN_7 = io_sizeIn_0 != 3'h7; // @[Parameters.scala:92:38] wire _gbits_legal_T_11; // @[Parameters.scala:92:38] assign _gbits_legal_T_11 = _GEN_7; // @[Parameters.scala:92:38] wire _pfbits_legal_T_11; // @[Parameters.scala:92:38] assign _pfbits_legal_T_11 = _GEN_7; // @[Parameters.scala:92:38] wire _gbits_legal_T_12 = _gbits_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _gbits_legal_T_13 = _gbits_legal_T_12; // @[Parameters.scala:684:29] wire [128:0] _gbits_legal_T_15 = {1'h0, _gbits_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_16 = _gbits_legal_T_15 & 129'h8A112000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_17 = _gbits_legal_T_16; // @[Parameters.scala:137:46] wire _gbits_legal_T_18 = _gbits_legal_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _gbits_legal_T_20 = {1'h0, _gbits_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_21 = _gbits_legal_T_20 & 129'h8A110000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_22 = _gbits_legal_T_21; // @[Parameters.scala:137:46] wire _gbits_legal_T_23 = _gbits_legal_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _gbits_legal_T_25 = {1'h0, _gbits_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_26 = _gbits_legal_T_25 & 129'h8A103000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_27 = _gbits_legal_T_26; // @[Parameters.scala:137:46] wire _gbits_legal_T_28 = _gbits_legal_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _gbits_legal_T_30 = {1'h0, _gbits_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_31 = _gbits_legal_T_30 & 129'h8A110000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_32 = _gbits_legal_T_31; // @[Parameters.scala:137:46] wire _gbits_legal_T_33 = _gbits_legal_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_8 = {io_addrIn_0[127:28], io_addrIn_0[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_34; // @[Parameters.scala:137:31] assign _gbits_legal_T_34 = _GEN_8; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_29; // @[Parameters.scala:137:31] assign _pfbits_legal_T_29 = _GEN_8; // @[Parameters.scala:137:31] wire [128:0] _gbits_legal_T_35 = {1'h0, _gbits_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_36 = _gbits_legal_T_35 & 129'h88000000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_37 = _gbits_legal_T_36; // @[Parameters.scala:137:46] wire _gbits_legal_T_38 = _gbits_legal_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _gbits_legal_T_40 = {1'h0, _gbits_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_41 = _gbits_legal_T_40 & 129'h8A100000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_42 = _gbits_legal_T_41; // @[Parameters.scala:137:46] wire _gbits_legal_T_43 = _gbits_legal_T_42 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _gbits_legal_T_44 = _gbits_legal_T_18 \| _gbits_legal_T_23; // @[Parameters.scala:685:42] wire _gbits_legal_T_45 = _gbits_legal_T_44 \| _gbits_legal_T_28; // @[Parameters.scala:685:42] wire _gbits_legal_T_46 = _gbits_legal_T_45 \| _gbits_legal_T_33; // @[Parameters.scala:685:42] wire _gbits_legal_T_47 = _gbits_legal_T_46 \| _gbits_legal_T_38; // @[Parameters.scala:685:42] wire _gbits_legal_T_48 = _gbits_legal_T_47 \| _gbits_legal_T_43; // @[Parameters.scala:685:42] wire _gbits_legal_T_49 = _gbits_legal_T_13 & _gbits_legal_T_48; // @[Parameters.scala:684:{29,54}, :685:42] wire gbits_legal = _gbits_legal_T_50 \| _gbits_legal_T_49; // @[Parameters.scala:684:54, :686:26] wire [3:0] gbits_size; // @[Edges.scala:460:17] wire [3:0] _GEN_9 = {1'h0, io_sizeIn_0}; // @[Edges.scala:463:15] assign gbits_size = _GEN_9; // @[Edges.scala:460:17, :463:15] wire [3:0] pfbits_size; // @[Edges.scala:480:17] assign pfbits_size = _GEN_9; // @[Edges.scala:463:15, :480:17] wire [128:0] _pfbits_legal_T_5 = {1'h0, _pfbits_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_6 = _pfbits_legal_T_5 & 129'h8A113000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_7 = _pfbits_legal_T_6; // @[Parameters.scala:137:46] wire _pfbits_legal_T_8 = _pfbits_legal_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _pfbits_legal_T_9 = _pfbits_legal_T_8; // @[Parameters.scala:684:54] wire _pfbits_legal_T_51 = _pfbits_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _pfbits_legal_T_12 = _pfbits_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _pfbits_legal_T_13 = _pfbits_legal_T_12; // @[Parameters.scala:684:29] wire [128:0] _pfbits_legal_T_15 = {1'h0, _pfbits_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_16 = _pfbits_legal_T_15 & 129'h8A112000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_17 = _pfbits_legal_T_16; // @[Parameters.scala:137:46] wire _pfbits_legal_T_18 = _pfbits_legal_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _pfbits_legal_T_20 = {1'h0, _pfbits_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_21 = _pfbits_legal_T_20 & 129'h8A103000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_22 = _pfbits_legal_T_21; // @[Parameters.scala:137:46] wire _pfbits_legal_T_23 = _pfbits_legal_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _pfbits_legal_T_25 = {1'h0, _pfbits_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_26 = _pfbits_legal_T_25 & 129'h8A110000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_27 = _pfbits_legal_T_26; // @[Parameters.scala:137:46] wire _pfbits_legal_T_28 = _pfbits_legal_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _pfbits_legal_T_30 = {1'h0, _pfbits_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_31 = _pfbits_legal_T_30 & 129'h88000000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_32 = _pfbits_legal_T_31; // @[Parameters.scala:137:46] wire _pfbits_legal_T_33 = _pfbits_legal_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _pfbits_legal_T_35 = {1'h0, _pfbits_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_36 = _pfbits_legal_T_35 & 129'h8A100000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_37 = _pfbits_legal_T_36; // @[Parameters.scala:137:46] wire _pfbits_legal_T_38 = _pfbits_legal_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _pfbits_legal_T_39 = _pfbits_legal_T_18 \| _pfbits_legal_T_23; // @[Parameters.scala:685:42] wire _pfbits_legal_T_40 = _pfbits_legal_T_39 \| _pfbits_legal_T_28; // @[Parameters.scala:685:42] wire _pfbits_legal_T_41 = _pfbits_legal_T_40 \| _pfbits_legal_T_33; // @[Parameters.scala:685:42] wire _pfbits_legal_T_42 = _pfbits_legal_T_41 \| _pfbits_legal_T_38; // @[Parameters.scala:685:42] wire _pfbits_legal_T_43 = _pfbits_legal_T_13 & _pfbits_legal_T_42; // @[Parameters.scala:684:{29,54}, :685:42] wire [128:0] _pfbits_legal_T_46 = {1'h0, _pfbits_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_47 = _pfbits_legal_T_46 & 129'h8A110000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_48 = _pfbits_legal_T_47; // @[Parameters.scala:137:46] wire _pfbits_legal_T_49 = _pfbits_legal_T_48 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _pfbits_legal_T_52 = _pfbits_legal_T_51 \| _pfbits_legal_T_43; // @[Parameters.scala:684:54, :686:26] wire pfbits_legal = _pfbits_legal_T_52; // @[Parameters.scala:686:26] wire _nodeOut_a_valid_T = sbState == 3'h1; // @[SBA.scala:295:26, :322:18, :366:28] assign nodeOut_a_bits_opcode = {_nodeOut_a_valid_T, 2'h0}; // @[SBA.scala:322:{42,54}, :323:54, :366:28] assign nodeOut_a_bits_size = _nodeOut_a_valid_T ? gbits_size : pfbits_size; // @[Edges.scala:460:17, :480:17] assign nodeOut_a_bits_address = _nodeOut_a_valid_T ? gbits_address : pfbits_address; // @[Edges.scala:460:17, :480:17] assign nodeOut_a_bits_data = _nodeOut_a_valid_T ? 8'h0 : pfbits_data; // @[Edges.scala:480:17] assign respError = _d_q_io_deq_bits_denied \| _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] assign io_respError_0 = respError; // @[SBA.scala:273:9, :335:35] wire _T_20 = sbState == 3'h2; // @[SBA.scala:295:26, :338:29] wire _wrTxValid_T; // @[SBA.scala:338:29] assign _wrTxValid_T = _T_20; // @[SBA.scala:338:29] wire _nodeOut_a_valid_T_1; // @[SBA.scala:366:64] assign _nodeOut_a_valid_T_1 = _T_20; // @[SBA.scala:338:29, :366:64] wire _wrTxValid_T_1 = _wrTxValid_T & nodeOut_a_valid; // @[SBA.scala:338:{29,53}] wire wrTxValid = _wrTxValid_T_1 & nodeOut_a_ready; // @[SBA.scala:338:{53,69}] wire _rdTxValid_T_1 = _rdTxValid_T & _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire rdTxValid = _rdTxValid_T_1 & _q_io_deq_ready_T_2; // @[SBA.scala:299:50, :339:{53,70}] wire [7:0] _txLast_T = 8'h1 << io_sizeIn_0; // @[SBA.scala:273:9, :340:39] wire [8:0] _txLast_T_1 = {1'h0, _txLast_T} - 9'h1; // @[SBA.scala:340:{39,53}] wire [7:0] _txLast_T_2 = _txLast_T_1[7:0]; // @[SBA.scala:340:53] wire txLast = {4'h0, counter} == _txLast_T_2; // @[SBA.scala:307:26, :340:{29,53}] wire _GEN_10 = wrTxValid \| rdTxValid; // @[SBA.scala:338:69, :339:70, :341:31] wire _counter_T; // @[SBA.scala:341:31] assign _counter_T = _GEN_10; // @[SBA.scala:341:31] wire _counter_T_2; // @[SBA.scala:342:31] assign _counter_T_2 = _GEN_10; // @[SBA.scala:341:31, :342:31] wire _counter_T_1 = _counter_T & txLast; // @[SBA.scala:340:29, :341:{31,45}] wire [4:0] _counter_T_3 = {1'h0, counter} + 5'h1; // @[SBA.scala:307:26, :342:63] wire [3:0] _counter_T_4 = _counter_T_3[3:0]; // @[SBA.scala:342:63] wire [3:0] _counter_T_5 = _counter_T_2 ? _counter_T_4 : counter; // @[SBA.scala:307:26, :342:{19,31,63}] wire [3:0] _counter_T_6 = _counter_T_1 ? 4'h0 : _counter_T_5; // @[SBA.scala:341:{19,45}, :342:19] wire _io_rdLoad_0_T = counter == 4'h0; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_0_T_1 = rdTxValid & _io_rdLoad_0_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_0_0 = _io_rdLoad_0_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_1_T = counter == 4'h1; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_1_T_1 = rdTxValid & _io_rdLoad_1_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_1_0 = _io_rdLoad_1_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_2_T = counter == 4'h2; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_2_T_1 = rdTxValid & _io_rdLoad_2_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_2_0 = _io_rdLoad_2_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_3_T = counter == 4'h3; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_3_T_1 = rdTxValid & _io_rdLoad_3_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_3_0 = _io_rdLoad_3_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_4_T = counter == 4'h4; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_4_T_1 = rdTxValid & _io_rdLoad_4_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_4_0 = _io_rdLoad_4_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_5_T = counter == 4'h5; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_5_T_1 = rdTxValid & _io_rdLoad_5_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_5_0 = _io_rdLoad_5_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_6_T = counter == 4'h6; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_6_T_1 = rdTxValid & _io_rdLoad_6_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_6_0 = _io_rdLoad_6_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_7_T = counter == 4'h7; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_7_T_1 = rdTxValid & _io_rdLoad_7_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_7_0 = _io_rdLoad_7_T_1; // @[SBA.scala:273:9, :345:33] wire _sbState_T = io_rdEn_0 & io_rdLegal_0; // @[SBA.scala:273:9, :350:30] wire _sbState_T_1 = io_wrEn_0 & io_wrLegal_0; // @[SBA.scala:273:9, :351:30] wire [2:0] _sbState_T_2 = _sbState_T_1 ? 3'h2 : sbState; // @[SBA.scala:295:26, :351:{21,30}] wire [2:0] _sbState_T_3 = _sbState_T ? 3'h1 : _sbState_T_2; // @[SBA.scala:350:{21,30}, :351:21] wire _sbState_T_4 = nodeOut_a_valid & nodeOut_a_ready; // @[SBA.scala:353:35] wire [2:0] _sbState_T_5 = _sbState_T_4 ? 3'h3 : sbState; // @[SBA.scala:295:26, :353:{21,35}] wire _sbState_T_6 = wrTxValid & txLast; // @[SBA.scala:338:69, :340:29, :355:32] wire [2:0] _sbState_T_7 = _sbState_T_6 ? 3'h4 : sbState; // @[SBA.scala:295:26, :355:{21,32}] wire _GEN_11 = rdTxValid & txLast; // @[SBA.scala:339:70, :340:29, :357:32] wire _sbState_T_8; // @[SBA.scala:357:32] assign _sbState_T_8 = _GEN_11; // @[SBA.scala:357:32] assign _io_rdDone_T = _GEN_11; // @[SBA.scala:357:32, :362:29] wire [2:0] _sbState_T_9 = _sbState_T_8 ? 3'h0 : sbState; // @[SBA.scala:295:26, :357:{21,32}] wire _sbState_T_10 = _d_q_io_deq_valid & _q_io_deq_ready_T_2; // @[Decoupled.scala:362:21] wire [2:0] _sbState_T_11 = _sbState_T_10 ? 3'h0 : sbState; // @[SBA.scala:295:26, :359:{21,36}] assign io_rdDone_0 = _io_rdDone_T; // @[SBA.scala:273:9, :362:29] wire _io_wrDone_T_1 = _io_wrDone_T & _d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign _io_wrDone_T_2 = _io_wrDone_T_1 & _q_io_deq_ready_T_2; // @[SBA.scala:299:50, :363:{54,71}] assign io_wrDone_0 = _io_wrDone_T_2; // @[SBA.scala:273:9, :363:71] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T \| _nodeOut_a_valid_T_1; // @[SBA.scala:366:{28,52,64}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[SBA.scala:366:52]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_180 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_324 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_180( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_324 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_41 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _source_ok_T_2 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 connect _source_ok_WIRE[2], _source_ok_T_2 node _source_ok_T_3 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_3, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_23 = cvt(_T_22) node _T_24 = and(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = asSInt(_T_24) node _T_26 = eq(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = or(_T_21, _T_26) node _T_28 = and(_T_11, _T_19) node _T_29 = and(_T_28, _T_27) node _T_30 = asUInt(reset) node _T_31 = eq(_T_30, UInt<1>(0h0)) when _T_31 : node _T_32 = eq(_T_29, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_29, UInt<1>(0h1), "") : assert_1 node _T_33 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_33 : node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_38 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_40 = or(_T_37, _T_38) node _T_41 = or(_T_40, _T_39) node _T_42 = and(_T_36, _T_41) node _T_43 = or(UInt<1>(0h0), _T_42) node _T_44 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<14>(0h2000))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<13>(0h1000))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<17>(0h10000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<18>(0h2f000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<13>(0h1000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<27>(0h4000000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = or(_T_49, _T_54) node _T_86 = or(_T_85, _T_59) node _T_87 = or(_T_86, _T_64) node _T_88 = or(_T_87, _T_69) node _T_89 = or(_T_88, _T_74) node _T_90 = or(_T_89, _T_79) node _T_91 = or(_T_90, _T_84) node _T_92 = and(_T_44, _T_91) node _T_93 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<29>(0h10000000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = and(_T_94, _T_105) node _T_107 = or(UInt<1>(0h0), _T_92) node _T_108 = or(_T_107, _T_106) node _T_109 = and(_T_43, _T_108) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_109, UInt<1>(0h1), "") : assert_2 node _T_113 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_115 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_113 connect _WIRE[1], _T_114 connect _WIRE[2], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_120 = or(_T_117, _T_118) node _T_121 = or(_T_120, _T_119) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_121 node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = or(UInt<1>(0h0), _T_124) node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = or(_T_130, _T_135) node _T_177 = or(_T_176, _T_140) node _T_178 = or(_T_177, _T_145) node _T_179 = or(_T_178, _T_150) node _T_180 = or(_T_179, _T_155) node _T_181 = or(_T_180, _T_160) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_170) node _T_184 = or(_T_183, _T_175) node _T_185 = and(_T_125, _T_184) node _T_186 = or(UInt<1>(0h0), _T_185) node _T_187 = and(_WIRE_1, _T_186) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_187, UInt<1>(0h1), "") : assert_3 node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(source_ok, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_194 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_194, UInt<1>(0h1), "") : assert_5 node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(is_aligned, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_201, UInt<1>(0h1), "") : assert_7 node _T_205 = not(io.in.a.bits.mask) node _T_206 = eq(_T_205, UInt<1>(0h0)) node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_T_206, UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_206, UInt<1>(0h1), "") : assert_8 node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_210, UInt<1>(0h1), "") : assert_9 node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_214 : node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_219 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_220 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_221 = or(_T_218, _T_219) node _T_222 = or(_T_221, _T_220) node _T_223 = and(_T_217, _T_222) node _T_224 = or(UInt<1>(0h0), _T_223) node _T_225 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<14>(0h2000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<18>(0h2f000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<27>(0h4000000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_230, _T_235) node _T_267 = or(_T_266, _T_240) node _T_268 = or(_T_267, _T_245) node _T_269 = or(_T_268, _T_250) node _T_270 = or(_T_269, _T_255) node _T_271 = or(_T_270, _T_260) node _T_272 = or(_T_271, _T_265) node _T_273 = and(_T_225, _T_272) node _T_274 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<29>(0h10000000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_280, _T_285) node _T_287 = and(_T_275, _T_286) node _T_288 = or(UInt<1>(0h0), _T_273) node _T_289 = or(_T_288, _T_287) node _T_290 = and(_T_224, _T_289) node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(_T_290, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_290, UInt<1>(0h1), "") : assert_10 node _T_294 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_295 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_296 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_294 connect _WIRE_2[1], _T_295 connect _WIRE_2[2], _T_296 node _T_297 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_298 = mux(_WIRE_2[0], _T_297, UInt<1>(0h0)) node _T_299 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_300 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = or(_T_298, _T_299) node _T_302 = or(_T_301, _T_300) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_302 node _T_303 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_304 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_305 = and(_T_303, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<14>(0h2000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_313 = cvt(_T_312) node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000))) node _T_315 = asSInt(_T_314) node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_318 = cvt(_T_317) node _T_319 = and(_T_318, asSInt(UInt<17>(0h10000))) node _T_320 = asSInt(_T_319) node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0))) node _T_322 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<18>(0h2f000))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<17>(0h10000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<27>(0h4000000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<13>(0h1000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<29>(0h10000000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = or(_T_311, _T_316) node _T_358 = or(_T_357, _T_321) node _T_359 = or(_T_358, _T_326) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_336) node _T_362 = or(_T_361, _T_341) node _T_363 = or(_T_362, _T_346) node _T_364 = or(_T_363, _T_351) node _T_365 = or(_T_364, _T_356) node _T_366 = and(_T_306, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_WIRE_3, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_368, UInt<1>(0h1), "") : assert_11 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(source_ok, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_375 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_375, UInt<1>(0h1), "") : assert_13 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(is_aligned, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_382 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_382, UInt<1>(0h1), "") : assert_15 node _T_386 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_386, UInt<1>(0h1), "") : assert_16 node _T_390 = not(io.in.a.bits.mask) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_391, UInt<1>(0h1), "") : assert_17 node _T_395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_395, UInt<1>(0h1), "") : assert_18 node _T_399 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_399 : node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_404 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_405 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_406 = or(_T_403, _T_404) node _T_407 = or(_T_406, _T_405) node _T_408 = and(_T_402, _T_407) node _T_409 = or(UInt<1>(0h0), _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_409, UInt<1>(0h1), "") : assert_19 node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = and(_T_416, _T_421) node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_433 = cvt(_T_432) node _T_434 = and(_T_433, asSInt(UInt<17>(0h10000))) node _T_435 = asSInt(_T_434) node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0))) node _T_437 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_438 = cvt(_T_437) node _T_439 = and(_T_438, asSInt(UInt<18>(0h2f000))) node _T_440 = asSInt(_T_439) node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0))) node _T_442 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_443 = cvt(_T_442) node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000))) node _T_445 = asSInt(_T_444) node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0))) node _T_447 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_453 = cvt(_T_452) node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000))) node _T_455 = asSInt(_T_454) node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0))) node _T_457 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<27>(0h4000000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<29>(0h10000000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = or(_T_431, _T_436) node _T_473 = or(_T_472, _T_441) node _T_474 = or(_T_473, _T_446) node _T_475 = or(_T_474, _T_451) node _T_476 = or(_T_475, _T_456) node _T_477 = or(_T_476, _T_461) node _T_478 = or(_T_477, _T_466) node _T_479 = or(_T_478, _T_471) node _T_480 = and(_T_426, _T_479) node _T_481 = or(UInt<1>(0h0), _T_422) node _T_482 = or(_T_481, _T_480) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_482, UInt<1>(0h1), "") : assert_20 node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(source_ok, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(is_aligned, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_492, UInt<1>(0h1), "") : assert_23 node _T_496 = eq(io.in.a.bits.mask, mask) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_496, UInt<1>(0h1), "") : assert_24 node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_500, UInt<1>(0h1), "") : assert_25 node _T_504 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_504 : node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_509 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_510 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_511 = or(_T_508, _T_509) node _T_512 = or(_T_511, _T_510) node _T_513 = and(_T_507, _T_512) node _T_514 = or(UInt<1>(0h0), _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = and(_T_518, _T_523) node _T_525 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_526 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_527 = and(_T_525, _T_526) node _T_528 = or(UInt<1>(0h0), _T_527) node _T_529 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<14>(0h2000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<18>(0h2f000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<17>(0h10000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<27>(0h4000000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<29>(0h10000000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = or(_T_533, _T_538) node _T_570 = or(_T_569, _T_543) node _T_571 = or(_T_570, _T_548) node _T_572 = or(_T_571, _T_553) node _T_573 = or(_T_572, _T_558) node _T_574 = or(_T_573, _T_563) node _T_575 = or(_T_574, _T_568) node _T_576 = and(_T_528, _T_575) node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = and(_T_577, _T_582) node _T_584 = or(UInt<1>(0h0), _T_524) node _T_585 = or(_T_584, _T_576) node _T_586 = or(_T_585, _T_583) node _T_587 = and(_T_514, _T_586) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_587, UInt<1>(0h1), "") : assert_26 node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(source_ok, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(is_aligned, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_597 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_597, UInt<1>(0h1), "") : assert_29 node _T_601 = eq(io.in.a.bits.mask, mask) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_601, UInt<1>(0h1), "") : assert_30 node _T_605 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_605 : node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_608 = and(_T_606, _T_607) node _T_609 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_610 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_611 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_612 = or(_T_609, _T_610) node _T_613 = or(_T_612, _T_611) node _T_614 = and(_T_608, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<27>(0h4000000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<29>(0h10000000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = or(_T_634, _T_639) node _T_671 = or(_T_670, _T_644) node _T_672 = or(_T_671, _T_649) node _T_673 = or(_T_672, _T_654) node _T_674 = or(_T_673, _T_659) node _T_675 = or(_T_674, _T_664) node _T_676 = or(_T_675, _T_669) node _T_677 = and(_T_629, _T_676) node _T_678 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_680 = cvt(_T_679) node _T_681 = and(_T_680, asSInt(UInt<17>(0h10000))) node _T_682 = asSInt(_T_681) node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0))) node _T_684 = and(_T_678, _T_683) node _T_685 = or(UInt<1>(0h0), _T_625) node _T_686 = or(_T_685, _T_677) node _T_687 = or(_T_686, _T_684) node _T_688 = and(_T_615, _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_688, UInt<1>(0h1), "") : assert_31 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(source_ok, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(is_aligned, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_698, UInt<1>(0h1), "") : assert_34 node _T_702 = not(mask) node _T_703 = and(io.in.a.bits.mask, _T_702) node _T_704 = eq(_T_703, UInt<1>(0h0)) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_704, UInt<1>(0h1), "") : assert_35 node _T_708 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_708 : node _T_709 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_710 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_711 = and(_T_709, _T_710) node _T_712 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_713 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_714 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_715 = or(_T_712, _T_713) node _T_716 = or(_T_715, _T_714) node _T_717 = and(_T_711, _T_716) node _T_718 = or(UInt<1>(0h0), _T_717) node _T_719 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_720 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<14>(0h2000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_749 = cvt(_T_748) node _T_750 = and(_T_749, asSInt(UInt<17>(0h10000))) node _T_751 = asSInt(_T_750) node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0))) node _T_753 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<27>(0h4000000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_764 = cvt(_T_763) node _T_765 = and(_T_764, asSInt(UInt<29>(0h10000000))) node _T_766 = asSInt(_T_765) node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0))) node _T_768 = or(_T_727, _T_732) node _T_769 = or(_T_768, _T_737) node _T_770 = or(_T_769, _T_742) node _T_771 = or(_T_770, _T_747) node _T_772 = or(_T_771, _T_752) node _T_773 = or(_T_772, _T_757) node _T_774 = or(_T_773, _T_762) node _T_775 = or(_T_774, _T_767) node _T_776 = and(_T_722, _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_776) node _T_785 = or(_T_784, _T_783) node _T_786 = and(_T_718, _T_785) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_786, UInt<1>(0h1), "") : assert_36 node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(source_ok, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(is_aligned, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_796 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_796, UInt<1>(0h1), "") : assert_39 node _T_800 = eq(io.in.a.bits.mask, mask) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_800, UInt<1>(0h1), "") : assert_40 node _T_804 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_809 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_810 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_811 = or(_T_808, _T_809) node _T_812 = or(_T_811, _T_810) node _T_813 = and(_T_807, _T_812) node _T_814 = or(UInt<1>(0h0), _T_813) node _T_815 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_816 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_817 = and(_T_815, _T_816) node _T_818 = or(UInt<1>(0h0), _T_817) node _T_819 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<14>(0h2000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<18>(0h2f000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<17>(0h10000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<29>(0h10000000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = or(_T_823, _T_828) node _T_865 = or(_T_864, _T_833) node _T_866 = or(_T_865, _T_838) node _T_867 = or(_T_866, _T_843) node _T_868 = or(_T_867, _T_848) node _T_869 = or(_T_868, _T_853) node _T_870 = or(_T_869, _T_858) node _T_871 = or(_T_870, _T_863) node _T_872 = and(_T_818, _T_871) node _T_873 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_874 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<17>(0h10000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = and(_T_873, _T_878) node _T_880 = or(UInt<1>(0h0), _T_872) node _T_881 = or(_T_880, _T_879) node _T_882 = and(_T_814, _T_881) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_882, UInt<1>(0h1), "") : assert_41 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(is_aligned, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_892, UInt<1>(0h1), "") : assert_44 node _T_896 = eq(io.in.a.bits.mask, mask) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_896, UInt<1>(0h1), "") : assert_45 node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_905 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_906 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_907 = or(_T_904, _T_905) node _T_908 = or(_T_907, _T_906) node _T_909 = and(_T_903, _T_908) node _T_910 = or(UInt<1>(0h0), _T_909) node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_912 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_913 = and(_T_911, _T_912) node _T_914 = or(UInt<1>(0h0), _T_913) node _T_915 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<13>(0h1000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = and(_T_914, _T_919) node _T_921 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<14>(0h2000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_948 = cvt(_T_947) node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000))) node _T_950 = asSInt(_T_949) node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0))) node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_953 = cvt(_T_952) node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000))) node _T_955 = asSInt(_T_954) node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0))) node _T_957 = or(_T_926, _T_931) node _T_958 = or(_T_957, _T_936) node _T_959 = or(_T_958, _T_941) node _T_960 = or(_T_959, _T_946) node _T_961 = or(_T_960, _T_951) node _T_962 = or(_T_961, _T_956) node _T_963 = and(_T_921, _T_962) node _T_964 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_965 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_966 = and(_T_964, _T_965) node _T_967 = or(UInt<1>(0h0), _T_966) node _T_968 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_969 = cvt(_T_968) node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000))) node _T_971 = asSInt(_T_970) node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0))) node _T_973 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_974 = cvt(_T_973) node _T_975 = and(_T_974, asSInt(UInt<29>(0h10000000))) node _T_976 = asSInt(_T_975) node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0))) node _T_978 = or(_T_972, _T_977) node _T_979 = and(_T_967, _T_978) node _T_980 = or(UInt<1>(0h0), _T_920) node _T_981 = or(_T_980, _T_963) node _T_982 = or(_T_981, _T_979) node _T_983 = and(_T_910, _T_982) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_983, UInt<1>(0h1), "") : assert_46 node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(source_ok, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(is_aligned, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_993 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_993, UInt<1>(0h1), "") : assert_49 node _T_997 = eq(io.in.a.bits.mask, mask) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_997, UInt<1>(0h1), "") : assert_50 node _T_1001 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1005 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_52 node _source_ok_T_4 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.d.bits.source, UInt<1>(0h1)) node _source_ok_T_6 = eq(io.in.d.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_4 connect _source_ok_WIRE_1[1], _source_ok_T_5 connect _source_ok_WIRE_1[2], _source_ok_T_6 node _source_ok_T_7 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_7, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1009 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1009 : node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(source_ok_1, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_54 node _T_1017 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_55 node _T_1021 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_56 node _T_1025 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_57 node _T_1029 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1029 : node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(source_ok_1, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(sink_ok, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1036 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_60 node _T_1040 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_61 node _T_1044 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_62 node _T_1048 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_63 node _T_1052 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1053 = or(UInt<1>(0h1), _T_1052) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_64 node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1057 : node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(source_ok_1, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(sink_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1064 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_67 node _T_1068 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_68 node _T_1072 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_69 node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1077 = or(_T_1076, io.in.d.bits.corrupt) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_70 node _T_1081 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1082 = or(UInt<1>(0h1), _T_1081) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_71 node _T_1086 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1086 : node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(source_ok_1, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1090 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_73 node _T_1094 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_74 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(UInt<1>(0h1), _T_1098) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_75 node _T_1103 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1103 : node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(source_ok_1, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1107 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_T_1107, UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1107, UInt<1>(0h1), "") : assert_77 node _T_1111 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1112 = or(_T_1111, io.in.d.bits.corrupt) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_78 node _T_1116 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1117 = or(UInt<1>(0h1), _T_1116) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_79 node _T_1121 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1121 : node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(source_ok_1, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1125 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_81 node _T_1129 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_82 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(UInt<1>(0h1), _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1138 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_84 node _T_1142 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) node _T_1144 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = or(_T_1143, _T_1148) node _T_1150 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<1>(0h0))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = or(_T_1151, _T_1156) node _T_1158 = eq(io.in.b.bits.source, UInt<2>(0h2)) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) node _T_1160 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1161 = cvt(_T_1160) node _T_1162 = and(_T_1161, asSInt(UInt<1>(0h0))) node _T_1163 = asSInt(_T_1162) node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0))) node _T_1165 = or(_T_1159, _T_1164) node _T_1166 = and(_T_1149, _T_1157) node _T_1167 = and(_T_1166, _T_1165) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _legal_source_T_2 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 connect _legal_source_WIRE[2], _legal_source_T_2 node _legal_source_T_3 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_4 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_5 = mux(_legal_source_WIRE[2], UInt<2>(0h2), UInt<1>(0h0)) node _legal_source_T_6 = or(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_7 = or(_legal_source_T_6, _legal_source_T_5) wire _legal_source_WIRE_1 : UInt<2> connect _legal_source_WIRE_1, _legal_source_T_7 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1171 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1171 : node _T_1172 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1173 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1174 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1172 connect _WIRE_4[1], _T_1173 connect _WIRE_4[2], _T_1174 node _T_1175 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1176 = mux(_WIRE_4[0], _T_1175, UInt<1>(0h0)) node _T_1177 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1178 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1179 = or(_T_1176, _T_1177) node _T_1180 = or(_T_1179, _T_1178) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1180 node _T_1181 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1182 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1183 = and(_T_1181, _T_1182) node _T_1184 = or(UInt<1>(0h0), _T_1183) node _T_1185 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1186 = cvt(_T_1185) node _T_1187 = and(_T_1186, asSInt(UInt<14>(0h2000))) node _T_1188 = asSInt(_T_1187) node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0))) node _T_1190 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<13>(0h1000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<17>(0h10000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1201 = cvt(_T_1200) node _T_1202 = and(_T_1201, asSInt(UInt<18>(0h2f000))) node _T_1203 = asSInt(_T_1202) node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0))) node _T_1205 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1206 = cvt(_T_1205) node _T_1207 = and(_T_1206, asSInt(UInt<17>(0h10000))) node _T_1208 = asSInt(_T_1207) node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0))) node _T_1210 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1211 = cvt(_T_1210) node _T_1212 = and(_T_1211, asSInt(UInt<13>(0h1000))) node _T_1213 = asSInt(_T_1212) node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1216 = cvt(_T_1215) node _T_1217 = and(_T_1216, asSInt(UInt<17>(0h10000))) node _T_1218 = asSInt(_T_1217) node _T_1219 = eq(_T_1218, asSInt(UInt<1>(0h0))) node _T_1220 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<27>(0h4000000))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<29>(0h10000000))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1189, _T_1194) node _T_1236 = or(_T_1235, _T_1199) node _T_1237 = or(_T_1236, _T_1204) node _T_1238 = or(_T_1237, _T_1209) node _T_1239 = or(_T_1238, _T_1214) node _T_1240 = or(_T_1239, _T_1219) node _T_1241 = or(_T_1240, _T_1224) node _T_1242 = or(_T_1241, _T_1229) node _T_1243 = or(_T_1242, _T_1234) node _T_1244 = and(_T_1184, _T_1243) node _T_1245 = or(UInt<1>(0h0), _T_1244) node _T_1246 = and(_WIRE_5, _T_1245) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_86 node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(address_ok, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(legal_source, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1259 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_90 node _T_1263 = eq(io.in.b.bits.mask, mask_1) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_91 node _T_1267 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(_T_1267, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1267, UInt<1>(0h1), "") : assert_92 node _T_1271 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1271 : node _T_1272 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1273 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1274 = and(_T_1272, _T_1273) node _T_1275 = or(UInt<1>(0h0), _T_1274) node _T_1276 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1277 = cvt(_T_1276) node _T_1278 = and(_T_1277, asSInt(UInt<14>(0h2000))) node _T_1279 = asSInt(_T_1278) node _T_1280 = eq(_T_1279, asSInt(UInt<1>(0h0))) node _T_1281 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1282 = cvt(_T_1281) node _T_1283 = and(_T_1282, asSInt(UInt<13>(0h1000))) node _T_1284 = asSInt(_T_1283) node _T_1285 = eq(_T_1284, asSInt(UInt<1>(0h0))) node _T_1286 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1287 = cvt(_T_1286) node _T_1288 = and(_T_1287, asSInt(UInt<17>(0h10000))) node _T_1289 = asSInt(_T_1288) node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0))) node _T_1291 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1292 = cvt(_T_1291) node _T_1293 = and(_T_1292, asSInt(UInt<18>(0h2f000))) node _T_1294 = asSInt(_T_1293) node _T_1295 = eq(_T_1294, asSInt(UInt<1>(0h0))) node _T_1296 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1297 = cvt(_T_1296) node _T_1298 = and(_T_1297, asSInt(UInt<17>(0h10000))) node _T_1299 = asSInt(_T_1298) node _T_1300 = eq(_T_1299, asSInt(UInt<1>(0h0))) node _T_1301 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1302 = cvt(_T_1301) node _T_1303 = and(_T_1302, asSInt(UInt<13>(0h1000))) node _T_1304 = asSInt(_T_1303) node _T_1305 = eq(_T_1304, asSInt(UInt<1>(0h0))) node _T_1306 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1307 = cvt(_T_1306) node _T_1308 = and(_T_1307, asSInt(UInt<17>(0h10000))) node _T_1309 = asSInt(_T_1308) node _T_1310 = eq(_T_1309, asSInt(UInt<1>(0h0))) node _T_1311 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1312 = cvt(_T_1311) node _T_1313 = and(_T_1312, asSInt(UInt<27>(0h4000000))) node _T_1314 = asSInt(_T_1313) node _T_1315 = eq(_T_1314, asSInt(UInt<1>(0h0))) node _T_1316 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1317 = cvt(_T_1316) node _T_1318 = and(_T_1317, asSInt(UInt<13>(0h1000))) node _T_1319 = asSInt(_T_1318) node _T_1320 = eq(_T_1319, asSInt(UInt<1>(0h0))) node _T_1321 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1322 = cvt(_T_1321) node _T_1323 = and(_T_1322, asSInt(UInt<29>(0h10000000))) node _T_1324 = asSInt(_T_1323) node _T_1325 = eq(_T_1324, asSInt(UInt<1>(0h0))) node _T_1326 = or(_T_1280, _T_1285) node _T_1327 = or(_T_1326, _T_1290) node _T_1328 = or(_T_1327, _T_1295) node _T_1329 = or(_T_1328, _T_1300) node _T_1330 = or(_T_1329, _T_1305) node _T_1331 = or(_T_1330, _T_1310) node _T_1332 = or(_T_1331, _T_1315) node _T_1333 = or(_T_1332, _T_1320) node _T_1334 = or(_T_1333, _T_1325) node _T_1335 = and(_T_1275, _T_1334) node _T_1336 = or(UInt<1>(0h0), _T_1335) node _T_1337 = and(UInt<1>(0h0), _T_1336) node _T_1338 = asUInt(reset) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) when _T_1339 : node _T_1340 = eq(_T_1337, UInt<1>(0h0)) when _T_1340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1337, UInt<1>(0h1), "") : assert_93 node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(address_ok, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(legal_source, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1350 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_97 node _T_1354 = eq(io.in.b.bits.mask, mask_1) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_98 node _T_1358 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_99 node _T_1362 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1362 : node _T_1363 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1364 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1365 = and(_T_1363, _T_1364) node _T_1366 = or(UInt<1>(0h0), _T_1365) node _T_1367 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1368 = cvt(_T_1367) node _T_1369 = and(_T_1368, asSInt(UInt<14>(0h2000))) node _T_1370 = asSInt(_T_1369) node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0))) node _T_1372 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1373 = cvt(_T_1372) node _T_1374 = and(_T_1373, asSInt(UInt<13>(0h1000))) node _T_1375 = asSInt(_T_1374) node _T_1376 = eq(_T_1375, asSInt(UInt<1>(0h0))) node _T_1377 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h10000))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<18>(0h2f000))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1388 = cvt(_T_1387) node _T_1389 = and(_T_1388, asSInt(UInt<17>(0h10000))) node _T_1390 = asSInt(_T_1389) node _T_1391 = eq(_T_1390, asSInt(UInt<1>(0h0))) node _T_1392 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1393 = cvt(_T_1392) node _T_1394 = and(_T_1393, asSInt(UInt<13>(0h1000))) node _T_1395 = asSInt(_T_1394) node _T_1396 = eq(_T_1395, asSInt(UInt<1>(0h0))) node _T_1397 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1398 = cvt(_T_1397) node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000))) node _T_1400 = asSInt(_T_1399) node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0))) node _T_1402 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1403 = cvt(_T_1402) node _T_1404 = and(_T_1403, asSInt(UInt<27>(0h4000000))) node _T_1405 = asSInt(_T_1404) node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0))) node _T_1407 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1408 = cvt(_T_1407) node _T_1409 = and(_T_1408, asSInt(UInt<13>(0h1000))) node _T_1410 = asSInt(_T_1409) node _T_1411 = eq(_T_1410, asSInt(UInt<1>(0h0))) node _T_1412 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1413 = cvt(_T_1412) node _T_1414 = and(_T_1413, asSInt(UInt<29>(0h10000000))) node _T_1415 = asSInt(_T_1414) node _T_1416 = eq(_T_1415, asSInt(UInt<1>(0h0))) node _T_1417 = or(_T_1371, _T_1376) node _T_1418 = or(_T_1417, _T_1381) node _T_1419 = or(_T_1418, _T_1386) node _T_1420 = or(_T_1419, _T_1391) node _T_1421 = or(_T_1420, _T_1396) node _T_1422 = or(_T_1421, _T_1401) node _T_1423 = or(_T_1422, _T_1406) node _T_1424 = or(_T_1423, _T_1411) node _T_1425 = or(_T_1424, _T_1416) node _T_1426 = and(_T_1366, _T_1425) node _T_1427 = or(UInt<1>(0h0), _T_1426) node _T_1428 = and(UInt<1>(0h0), _T_1427) node _T_1429 = asUInt(reset) node _T_1430 = eq(_T_1429, UInt<1>(0h0)) when _T_1430 : node _T_1431 = eq(_T_1428, UInt<1>(0h0)) when _T_1431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1428, UInt<1>(0h1), "") : assert_100 node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(address_ok, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1435 = asUInt(reset) node _T_1436 = eq(_T_1435, UInt<1>(0h0)) when _T_1436 : node _T_1437 = eq(legal_source, UInt<1>(0h0)) when _T_1437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1441 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_104 node _T_1445 = eq(io.in.b.bits.mask, mask_1) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_105 node _T_1449 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1449 : node _T_1450 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1451 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1452 = and(_T_1450, _T_1451) node _T_1453 = or(UInt<1>(0h0), _T_1452) node _T_1454 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1455 = cvt(_T_1454) node _T_1456 = and(_T_1455, asSInt(UInt<14>(0h2000))) node _T_1457 = asSInt(_T_1456) node _T_1458 = eq(_T_1457, asSInt(UInt<1>(0h0))) node _T_1459 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1460 = cvt(_T_1459) node _T_1461 = and(_T_1460, asSInt(UInt<13>(0h1000))) node _T_1462 = asSInt(_T_1461) node _T_1463 = eq(_T_1462, asSInt(UInt<1>(0h0))) node _T_1464 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1465 = cvt(_T_1464) node _T_1466 = and(_T_1465, asSInt(UInt<17>(0h10000))) node _T_1467 = asSInt(_T_1466) node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0))) node _T_1469 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1470 = cvt(_T_1469) node _T_1471 = and(_T_1470, asSInt(UInt<18>(0h2f000))) node _T_1472 = asSInt(_T_1471) node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0))) node _T_1474 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<17>(0h10000))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1480 = cvt(_T_1479) node _T_1481 = and(_T_1480, asSInt(UInt<13>(0h1000))) node _T_1482 = asSInt(_T_1481) node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0))) node _T_1484 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1485 = cvt(_T_1484) node _T_1486 = and(_T_1485, asSInt(UInt<17>(0h10000))) node _T_1487 = asSInt(_T_1486) node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0))) node _T_1489 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<27>(0h4000000))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1495 = cvt(_T_1494) node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000))) node _T_1497 = asSInt(_T_1496) node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0))) node _T_1499 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1500 = cvt(_T_1499) node _T_1501 = and(_T_1500, asSInt(UInt<29>(0h10000000))) node _T_1502 = asSInt(_T_1501) node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0))) node _T_1504 = or(_T_1458, _T_1463) node _T_1505 = or(_T_1504, _T_1468) node _T_1506 = or(_T_1505, _T_1473) node _T_1507 = or(_T_1506, _T_1478) node _T_1508 = or(_T_1507, _T_1483) node _T_1509 = or(_T_1508, _T_1488) node _T_1510 = or(_T_1509, _T_1493) node _T_1511 = or(_T_1510, _T_1498) node _T_1512 = or(_T_1511, _T_1503) node _T_1513 = and(_T_1453, _T_1512) node _T_1514 = or(UInt<1>(0h0), _T_1513) node _T_1515 = and(UInt<1>(0h0), _T_1514) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_106 node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(address_ok, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(legal_source, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1528 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_110 node _T_1532 = not(mask_1) node _T_1533 = and(io.in.b.bits.mask, _T_1532) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_111 node _T_1538 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1538 : node _T_1539 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1540 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1541 = and(_T_1539, _T_1540) node _T_1542 = or(UInt<1>(0h0), _T_1541) node _T_1543 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1544 = cvt(_T_1543) node _T_1545 = and(_T_1544, asSInt(UInt<14>(0h2000))) node _T_1546 = asSInt(_T_1545) node _T_1547 = eq(_T_1546, asSInt(UInt<1>(0h0))) node _T_1548 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1549 = cvt(_T_1548) node _T_1550 = and(_T_1549, asSInt(UInt<13>(0h1000))) node _T_1551 = asSInt(_T_1550) node _T_1552 = eq(_T_1551, asSInt(UInt<1>(0h0))) node _T_1553 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1554 = cvt(_T_1553) node _T_1555 = and(_T_1554, asSInt(UInt<17>(0h10000))) node _T_1556 = asSInt(_T_1555) node _T_1557 = eq(_T_1556, asSInt(UInt<1>(0h0))) node _T_1558 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1559 = cvt(_T_1558) node _T_1560 = and(_T_1559, asSInt(UInt<18>(0h2f000))) node _T_1561 = asSInt(_T_1560) node _T_1562 = eq(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1564 = cvt(_T_1563) node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000))) node _T_1566 = asSInt(_T_1565) node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0))) node _T_1568 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<13>(0h1000))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1574 = cvt(_T_1573) node _T_1575 = and(_T_1574, asSInt(UInt<17>(0h10000))) node _T_1576 = asSInt(_T_1575) node _T_1577 = eq(_T_1576, asSInt(UInt<1>(0h0))) node _T_1578 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1579 = cvt(_T_1578) node _T_1580 = and(_T_1579, asSInt(UInt<27>(0h4000000))) node _T_1581 = asSInt(_T_1580) node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0))) node _T_1583 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1584 = cvt(_T_1583) node _T_1585 = and(_T_1584, asSInt(UInt<13>(0h1000))) node _T_1586 = asSInt(_T_1585) node _T_1587 = eq(_T_1586, asSInt(UInt<1>(0h0))) node _T_1588 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1589 = cvt(_T_1588) node _T_1590 = and(_T_1589, asSInt(UInt<29>(0h10000000))) node _T_1591 = asSInt(_T_1590) node _T_1592 = eq(_T_1591, asSInt(UInt<1>(0h0))) node _T_1593 = or(_T_1547, _T_1552) node _T_1594 = or(_T_1593, _T_1557) node _T_1595 = or(_T_1594, _T_1562) node _T_1596 = or(_T_1595, _T_1567) node _T_1597 = or(_T_1596, _T_1572) node _T_1598 = or(_T_1597, _T_1577) node _T_1599 = or(_T_1598, _T_1582) node _T_1600 = or(_T_1599, _T_1587) node _T_1601 = or(_T_1600, _T_1592) node _T_1602 = and(_T_1542, _T_1601) node _T_1603 = or(UInt<1>(0h0), _T_1602) node _T_1604 = and(UInt<1>(0h0), _T_1603) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_112 node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(address_ok, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(legal_source, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1617 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_116 node _T_1621 = eq(io.in.b.bits.mask, mask_1) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_117 node _T_1625 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1625 : node _T_1626 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1627 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1628 = and(_T_1626, _T_1627) node _T_1629 = or(UInt<1>(0h0), _T_1628) node _T_1630 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1631 = cvt(_T_1630) node _T_1632 = and(_T_1631, asSInt(UInt<14>(0h2000))) node _T_1633 = asSInt(_T_1632) node _T_1634 = eq(_T_1633, asSInt(UInt<1>(0h0))) node _T_1635 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1636 = cvt(_T_1635) node _T_1637 = and(_T_1636, asSInt(UInt<13>(0h1000))) node _T_1638 = asSInt(_T_1637) node _T_1639 = eq(_T_1638, asSInt(UInt<1>(0h0))) node _T_1640 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1641 = cvt(_T_1640) node _T_1642 = and(_T_1641, asSInt(UInt<17>(0h10000))) node _T_1643 = asSInt(_T_1642) node _T_1644 = eq(_T_1643, asSInt(UInt<1>(0h0))) node _T_1645 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1646 = cvt(_T_1645) node _T_1647 = and(_T_1646, asSInt(UInt<18>(0h2f000))) node _T_1648 = asSInt(_T_1647) node _T_1649 = eq(_T_1648, asSInt(UInt<1>(0h0))) node _T_1650 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1651 = cvt(_T_1650) node _T_1652 = and(_T_1651, asSInt(UInt<17>(0h10000))) node _T_1653 = asSInt(_T_1652) node _T_1654 = eq(_T_1653, asSInt(UInt<1>(0h0))) node _T_1655 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1656 = cvt(_T_1655) node _T_1657 = and(_T_1656, asSInt(UInt<13>(0h1000))) node _T_1658 = asSInt(_T_1657) node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0))) node _T_1660 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1661 = cvt(_T_1660) node _T_1662 = and(_T_1661, asSInt(UInt<17>(0h10000))) node _T_1663 = asSInt(_T_1662) node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0))) node _T_1665 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1666 = cvt(_T_1665) node _T_1667 = and(_T_1666, asSInt(UInt<27>(0h4000000))) node _T_1668 = asSInt(_T_1667) node _T_1669 = eq(_T_1668, asSInt(UInt<1>(0h0))) node _T_1670 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1671 = cvt(_T_1670) node _T_1672 = and(_T_1671, asSInt(UInt<13>(0h1000))) node _T_1673 = asSInt(_T_1672) node _T_1674 = eq(_T_1673, asSInt(UInt<1>(0h0))) node _T_1675 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1676 = cvt(_T_1675) node _T_1677 = and(_T_1676, asSInt(UInt<29>(0h10000000))) node _T_1678 = asSInt(_T_1677) node _T_1679 = eq(_T_1678, asSInt(UInt<1>(0h0))) node _T_1680 = or(_T_1634, _T_1639) node _T_1681 = or(_T_1680, _T_1644) node _T_1682 = or(_T_1681, _T_1649) node _T_1683 = or(_T_1682, _T_1654) node _T_1684 = or(_T_1683, _T_1659) node _T_1685 = or(_T_1684, _T_1664) node _T_1686 = or(_T_1685, _T_1669) node _T_1687 = or(_T_1686, _T_1674) node _T_1688 = or(_T_1687, _T_1679) node _T_1689 = and(_T_1629, _T_1688) node _T_1690 = or(UInt<1>(0h0), _T_1689) node _T_1691 = and(UInt<1>(0h0), _T_1690) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_118 node _T_1695 = asUInt(reset) node _T_1696 = eq(_T_1695, UInt<1>(0h0)) when _T_1696 : node _T_1697 = eq(address_ok, UInt<1>(0h0)) when _T_1697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1698 = asUInt(reset) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) when _T_1699 : node _T_1700 = eq(legal_source, UInt<1>(0h0)) when _T_1700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1701 = asUInt(reset) node _T_1702 = eq(_T_1701, UInt<1>(0h0)) when _T_1702 : node _T_1703 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1704 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(_T_1704, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1704, UInt<1>(0h1), "") : assert_122 node _T_1708 = eq(io.in.b.bits.mask, mask_1) node _T_1709 = asUInt(reset) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(_T_1708, UInt<1>(0h0)) when _T_1711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1708, UInt<1>(0h1), "") : assert_123 node _T_1712 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1712 : node _T_1713 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1714 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1715 = and(_T_1713, _T_1714) node _T_1716 = or(UInt<1>(0h0), _T_1715) node _T_1717 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1718 = cvt(_T_1717) node _T_1719 = and(_T_1718, asSInt(UInt<14>(0h2000))) node _T_1720 = asSInt(_T_1719) node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0))) node _T_1722 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1723 = cvt(_T_1722) node _T_1724 = and(_T_1723, asSInt(UInt<13>(0h1000))) node _T_1725 = asSInt(_T_1724) node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0))) node _T_1727 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1728 = cvt(_T_1727) node _T_1729 = and(_T_1728, asSInt(UInt<17>(0h10000))) node _T_1730 = asSInt(_T_1729) node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0))) node _T_1732 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1733 = cvt(_T_1732) node _T_1734 = and(_T_1733, asSInt(UInt<18>(0h2f000))) node _T_1735 = asSInt(_T_1734) node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0))) node _T_1737 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1738 = cvt(_T_1737) node _T_1739 = and(_T_1738, asSInt(UInt<17>(0h10000))) node _T_1740 = asSInt(_T_1739) node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0))) node _T_1742 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1743 = cvt(_T_1742) node _T_1744 = and(_T_1743, asSInt(UInt<13>(0h1000))) node _T_1745 = asSInt(_T_1744) node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1748 = cvt(_T_1747) node _T_1749 = and(_T_1748, asSInt(UInt<17>(0h10000))) node _T_1750 = asSInt(_T_1749) node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0))) node _T_1752 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<27>(0h4000000))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1758 = cvt(_T_1757) node _T_1759 = and(_T_1758, asSInt(UInt<13>(0h1000))) node _T_1760 = asSInt(_T_1759) node _T_1761 = eq(_T_1760, asSInt(UInt<1>(0h0))) node _T_1762 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<29>(0h10000000))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1721, _T_1726) node _T_1768 = or(_T_1767, _T_1731) node _T_1769 = or(_T_1768, _T_1736) node _T_1770 = or(_T_1769, _T_1741) node _T_1771 = or(_T_1770, _T_1746) node _T_1772 = or(_T_1771, _T_1751) node _T_1773 = or(_T_1772, _T_1756) node _T_1774 = or(_T_1773, _T_1761) node _T_1775 = or(_T_1774, _T_1766) node _T_1776 = and(_T_1716, _T_1775) node _T_1777 = or(UInt<1>(0h0), _T_1776) node _T_1778 = and(UInt<1>(0h0), _T_1777) node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(_T_1778, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1778, UInt<1>(0h1), "") : assert_124 node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(address_ok, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1785 = asUInt(reset) node _T_1786 = eq(_T_1785, UInt<1>(0h0)) when _T_1786 : node _T_1787 = eq(legal_source, UInt<1>(0h0)) when _T_1787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1791 = eq(io.in.b.bits.mask, mask_1) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_128 node _T_1795 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1796 = asUInt(reset) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) when _T_1797 : node _T_1798 = eq(_T_1795, UInt<1>(0h0)) when _T_1798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1795, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1799 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_130 node _source_ok_T_8 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_9 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _source_ok_T_10 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_8 connect _source_ok_WIRE_2[1], _source_ok_T_9 connect _source_ok_WIRE_2[2], _source_ok_T_10 node _source_ok_T_11 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_11, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _T_1803 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) node _T_1805 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1806 = cvt(_T_1805) node _T_1807 = and(_T_1806, asSInt(UInt<1>(0h0))) node _T_1808 = asSInt(_T_1807) node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0))) node _T_1810 = or(_T_1804, _T_1809) node _T_1811 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1812 = eq(_T_1811, UInt<1>(0h0)) node _T_1813 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1814 = cvt(_T_1813) node _T_1815 = and(_T_1814, asSInt(UInt<1>(0h0))) node _T_1816 = asSInt(_T_1815) node _T_1817 = eq(_T_1816, asSInt(UInt<1>(0h0))) node _T_1818 = or(_T_1812, _T_1817) node _T_1819 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1820 = eq(_T_1819, UInt<1>(0h0)) node _T_1821 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1822 = cvt(_T_1821) node _T_1823 = and(_T_1822, asSInt(UInt<1>(0h0))) node _T_1824 = asSInt(_T_1823) node _T_1825 = eq(_T_1824, asSInt(UInt<1>(0h0))) node _T_1826 = or(_T_1820, _T_1825) node _T_1827 = and(_T_1810, _T_1818) node _T_1828 = and(_T_1827, _T_1826) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_131 node _T_1832 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1832 : node _T_1833 = asUInt(reset) node _T_1834 = eq(_T_1833, UInt<1>(0h0)) when _T_1834 : node _T_1835 = eq(address_ok_1, UInt<1>(0h0)) when _T_1835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1836 = asUInt(reset) node _T_1837 = eq(_T_1836, UInt<1>(0h0)) when _T_1837 : node _T_1838 = eq(source_ok_2, UInt<1>(0h0)) when _T_1838 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1839 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1840 = asUInt(reset) node _T_1841 = eq(_T_1840, UInt<1>(0h0)) when _T_1841 : node _T_1842 = eq(_T_1839, UInt<1>(0h0)) when _T_1842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1839, UInt<1>(0h1), "") : assert_134 node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1846 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_136 node _T_1850 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(_T_1850, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1850, UInt<1>(0h1), "") : assert_137 node _T_1854 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1854 : node _T_1855 = asUInt(reset) node _T_1856 = eq(_T_1855, UInt<1>(0h0)) when _T_1856 : node _T_1857 = eq(address_ok_1, UInt<1>(0h0)) when _T_1857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(source_ok_2, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1861 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(_T_1861, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1861, UInt<1>(0h1), "") : assert_140 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1868 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_142 node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1872 : node _T_1873 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1874 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1875 = and(_T_1873, _T_1874) node _T_1876 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1877 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1878 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1879 = or(_T_1876, _T_1877) node _T_1880 = or(_T_1879, _T_1878) node _T_1881 = and(_T_1875, _T_1880) node _T_1882 = or(UInt<1>(0h0), _T_1881) node _T_1883 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1884 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1885 = cvt(_T_1884) node _T_1886 = and(_T_1885, asSInt(UInt<14>(0h2000))) node _T_1887 = asSInt(_T_1886) node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0))) node _T_1889 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1890 = cvt(_T_1889) node _T_1891 = and(_T_1890, asSInt(UInt<13>(0h1000))) node _T_1892 = asSInt(_T_1891) node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1895 = cvt(_T_1894) node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000))) node _T_1897 = asSInt(_T_1896) node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0))) node _T_1899 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1900 = cvt(_T_1899) node _T_1901 = and(_T_1900, asSInt(UInt<18>(0h2f000))) node _T_1902 = asSInt(_T_1901) node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1905 = cvt(_T_1904) node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000))) node _T_1907 = asSInt(_T_1906) node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1910 = cvt(_T_1909) node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000))) node _T_1912 = asSInt(_T_1911) node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0))) node _T_1914 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1915 = cvt(_T_1914) node _T_1916 = and(_T_1915, asSInt(UInt<27>(0h4000000))) node _T_1917 = asSInt(_T_1916) node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0))) node _T_1919 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1920 = cvt(_T_1919) node _T_1921 = and(_T_1920, asSInt(UInt<13>(0h1000))) node _T_1922 = asSInt(_T_1921) node _T_1923 = eq(_T_1922, asSInt(UInt<1>(0h0))) node _T_1924 = or(_T_1888, _T_1893) node _T_1925 = or(_T_1924, _T_1898) node _T_1926 = or(_T_1925, _T_1903) node _T_1927 = or(_T_1926, _T_1908) node _T_1928 = or(_T_1927, _T_1913) node _T_1929 = or(_T_1928, _T_1918) node _T_1930 = or(_T_1929, _T_1923) node _T_1931 = and(_T_1883, _T_1930) node _T_1932 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1933 = or(UInt<1>(0h0), _T_1932) node _T_1934 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1935 = cvt(_T_1934) node _T_1936 = and(_T_1935, asSInt(UInt<17>(0h10000))) node _T_1937 = asSInt(_T_1936) node _T_1938 = eq(_T_1937, asSInt(UInt<1>(0h0))) node _T_1939 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1940 = cvt(_T_1939) node _T_1941 = and(_T_1940, asSInt(UInt<29>(0h10000000))) node _T_1942 = asSInt(_T_1941) node _T_1943 = eq(_T_1942, asSInt(UInt<1>(0h0))) node _T_1944 = or(_T_1938, _T_1943) node _T_1945 = and(_T_1933, _T_1944) node _T_1946 = or(UInt<1>(0h0), _T_1931) node _T_1947 = or(_T_1946, _T_1945) node _T_1948 = and(_T_1882, _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_143 node _T_1952 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1953 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1954 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_1952 connect _WIRE_6[1], _T_1953 connect _WIRE_6[2], _T_1954 node _T_1955 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1956 = mux(_WIRE_6[0], _T_1955, UInt<1>(0h0)) node _T_1957 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1958 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1959 = or(_T_1956, _T_1957) node _T_1960 = or(_T_1959, _T_1958) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1960 node _T_1961 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1962 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1963 = and(_T_1961, _T_1962) node _T_1964 = or(UInt<1>(0h0), _T_1963) node _T_1965 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1966 = cvt(_T_1965) node _T_1967 = and(_T_1966, asSInt(UInt<14>(0h2000))) node _T_1968 = asSInt(_T_1967) node _T_1969 = eq(_T_1968, asSInt(UInt<1>(0h0))) node _T_1970 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1971 = cvt(_T_1970) node _T_1972 = and(_T_1971, asSInt(UInt<13>(0h1000))) node _T_1973 = asSInt(_T_1972) node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0))) node _T_1975 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<17>(0h10000))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1981 = cvt(_T_1980) node _T_1982 = and(_T_1981, asSInt(UInt<18>(0h2f000))) node _T_1983 = asSInt(_T_1982) node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0))) node _T_1985 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1986 = cvt(_T_1985) node _T_1987 = and(_T_1986, asSInt(UInt<17>(0h10000))) node _T_1988 = asSInt(_T_1987) node _T_1989 = eq(_T_1988, asSInt(UInt<1>(0h0))) node _T_1990 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1991 = cvt(_T_1990) node _T_1992 = and(_T_1991, asSInt(UInt<13>(0h1000))) node _T_1993 = asSInt(_T_1992) node _T_1994 = eq(_T_1993, asSInt(UInt<1>(0h0))) node _T_1995 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1996 = cvt(_T_1995) node _T_1997 = and(_T_1996, asSInt(UInt<17>(0h10000))) node _T_1998 = asSInt(_T_1997) node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0))) node _T_2000 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2001 = cvt(_T_2000) node _T_2002 = and(_T_2001, asSInt(UInt<27>(0h4000000))) node _T_2003 = asSInt(_T_2002) node _T_2004 = eq(_T_2003, asSInt(UInt<1>(0h0))) node _T_2005 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2006 = cvt(_T_2005) node _T_2007 = and(_T_2006, asSInt(UInt<13>(0h1000))) node _T_2008 = asSInt(_T_2007) node _T_2009 = eq(_T_2008, asSInt(UInt<1>(0h0))) node _T_2010 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2011 = cvt(_T_2010) node _T_2012 = and(_T_2011, asSInt(UInt<29>(0h10000000))) node _T_2013 = asSInt(_T_2012) node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0))) node _T_2015 = or(_T_1969, _T_1974) node _T_2016 = or(_T_2015, _T_1979) node _T_2017 = or(_T_2016, _T_1984) node _T_2018 = or(_T_2017, _T_1989) node _T_2019 = or(_T_2018, _T_1994) node _T_2020 = or(_T_2019, _T_1999) node _T_2021 = or(_T_2020, _T_2004) node _T_2022 = or(_T_2021, _T_2009) node _T_2023 = or(_T_2022, _T_2014) node _T_2024 = and(_T_1964, _T_2023) node _T_2025 = or(UInt<1>(0h0), _T_2024) node _T_2026 = and(_WIRE_7, _T_2025) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_144 node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(source_ok_2, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2033 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_146 node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2040 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_148 node _T_2044 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_149 node _T_2048 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2048 : node _T_2049 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2050 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2051 = and(_T_2049, _T_2050) node _T_2052 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2053 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2054 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_2055 = or(_T_2052, _T_2053) node _T_2056 = or(_T_2055, _T_2054) node _T_2057 = and(_T_2051, _T_2056) node _T_2058 = or(UInt<1>(0h0), _T_2057) node _T_2059 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2060 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<14>(0h2000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<13>(0h1000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<17>(0h10000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<18>(0h2f000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<17>(0h10000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = or(_T_2064, _T_2069) node _T_2101 = or(_T_2100, _T_2074) node _T_2102 = or(_T_2101, _T_2079) node _T_2103 = or(_T_2102, _T_2084) node _T_2104 = or(_T_2103, _T_2089) node _T_2105 = or(_T_2104, _T_2094) node _T_2106 = or(_T_2105, _T_2099) node _T_2107 = and(_T_2059, _T_2106) node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2109 = or(UInt<1>(0h0), _T_2108) node _T_2110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2111 = cvt(_T_2110) node _T_2112 = and(_T_2111, asSInt(UInt<17>(0h10000))) node _T_2113 = asSInt(_T_2112) node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0))) node _T_2115 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2116 = cvt(_T_2115) node _T_2117 = and(_T_2116, asSInt(UInt<29>(0h10000000))) node _T_2118 = asSInt(_T_2117) node _T_2119 = eq(_T_2118, asSInt(UInt<1>(0h0))) node _T_2120 = or(_T_2114, _T_2119) node _T_2121 = and(_T_2109, _T_2120) node _T_2122 = or(UInt<1>(0h0), _T_2107) node _T_2123 = or(_T_2122, _T_2121) node _T_2124 = and(_T_2058, _T_2123) node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(_T_2124, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2124, UInt<1>(0h1), "") : assert_150 node _T_2128 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2130 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2128 connect _WIRE_8[1], _T_2129 connect _WIRE_8[2], _T_2130 node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2132 = mux(_WIRE_8[0], _T_2131, UInt<1>(0h0)) node _T_2133 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2134 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2135 = or(_T_2132, _T_2133) node _T_2136 = or(_T_2135, _T_2134) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2136 node _T_2137 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2138 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2139 = and(_T_2137, _T_2138) node _T_2140 = or(UInt<1>(0h0), _T_2139) node _T_2141 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2142 = cvt(_T_2141) node _T_2143 = and(_T_2142, asSInt(UInt<14>(0h2000))) node _T_2144 = asSInt(_T_2143) node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0))) node _T_2146 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2147 = cvt(_T_2146) node _T_2148 = and(_T_2147, asSInt(UInt<13>(0h1000))) node _T_2149 = asSInt(_T_2148) node _T_2150 = eq(_T_2149, asSInt(UInt<1>(0h0))) node _T_2151 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2152 = cvt(_T_2151) node _T_2153 = and(_T_2152, asSInt(UInt<17>(0h10000))) node _T_2154 = asSInt(_T_2153) node _T_2155 = eq(_T_2154, asSInt(UInt<1>(0h0))) node _T_2156 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2157 = cvt(_T_2156) node _T_2158 = and(_T_2157, asSInt(UInt<18>(0h2f000))) node _T_2159 = asSInt(_T_2158) node _T_2160 = eq(_T_2159, asSInt(UInt<1>(0h0))) node _T_2161 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2162 = cvt(_T_2161) node _T_2163 = and(_T_2162, asSInt(UInt<17>(0h10000))) node _T_2164 = asSInt(_T_2163) node _T_2165 = eq(_T_2164, asSInt(UInt<1>(0h0))) node _T_2166 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2167 = cvt(_T_2166) node _T_2168 = and(_T_2167, asSInt(UInt<13>(0h1000))) node _T_2169 = asSInt(_T_2168) node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0))) node _T_2171 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2172 = cvt(_T_2171) node _T_2173 = and(_T_2172, asSInt(UInt<17>(0h10000))) node _T_2174 = asSInt(_T_2173) node _T_2175 = eq(_T_2174, asSInt(UInt<1>(0h0))) node _T_2176 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2177 = cvt(_T_2176) node _T_2178 = and(_T_2177, asSInt(UInt<27>(0h4000000))) node _T_2179 = asSInt(_T_2178) node _T_2180 = eq(_T_2179, asSInt(UInt<1>(0h0))) node _T_2181 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2182 = cvt(_T_2181) node _T_2183 = and(_T_2182, asSInt(UInt<13>(0h1000))) node _T_2184 = asSInt(_T_2183) node _T_2185 = eq(_T_2184, asSInt(UInt<1>(0h0))) node _T_2186 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2187 = cvt(_T_2186) node _T_2188 = and(_T_2187, asSInt(UInt<29>(0h10000000))) node _T_2189 = asSInt(_T_2188) node _T_2190 = eq(_T_2189, asSInt(UInt<1>(0h0))) node _T_2191 = or(_T_2145, _T_2150) node _T_2192 = or(_T_2191, _T_2155) node _T_2193 = or(_T_2192, _T_2160) node _T_2194 = or(_T_2193, _T_2165) node _T_2195 = or(_T_2194, _T_2170) node _T_2196 = or(_T_2195, _T_2175) node _T_2197 = or(_T_2196, _T_2180) node _T_2198 = or(_T_2197, _T_2185) node _T_2199 = or(_T_2198, _T_2190) node _T_2200 = and(_T_2140, _T_2199) node _T_2201 = or(UInt<1>(0h0), _T_2200) node _T_2202 = and(_WIRE_9, _T_2201) node _T_2203 = asUInt(reset) node _T_2204 = eq(_T_2203, UInt<1>(0h0)) when _T_2204 : node _T_2205 = eq(_T_2202, UInt<1>(0h0)) when _T_2205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2202, UInt<1>(0h1), "") : assert_151 node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : node _T_2208 = eq(source_ok_2, UInt<1>(0h0)) when _T_2208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2209 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_153 node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2216 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2217 = asUInt(reset) node _T_2218 = eq(_T_2217, UInt<1>(0h0)) when _T_2218 : node _T_2219 = eq(_T_2216, UInt<1>(0h0)) when _T_2219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2216, UInt<1>(0h1), "") : assert_155 node _T_2220 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2220 : node _T_2221 = asUInt(reset) node _T_2222 = eq(_T_2221, UInt<1>(0h0)) when _T_2222 : node _T_2223 = eq(address_ok_1, UInt<1>(0h0)) when _T_2223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(source_ok_2, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2230 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_159 node _T_2234 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2235 = asUInt(reset) node _T_2236 = eq(_T_2235, UInt<1>(0h0)) when _T_2236 : node _T_2237 = eq(_T_2234, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2234, UInt<1>(0h1), "") : assert_160 node _T_2238 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2238 : node _T_2239 = asUInt(reset) node _T_2240 = eq(_T_2239, UInt<1>(0h0)) when _T_2240 : node _T_2241 = eq(address_ok_1, UInt<1>(0h0)) when _T_2241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(source_ok_2, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2248 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_164 node _T_2252 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2252 : node _T_2253 = asUInt(reset) node _T_2254 = eq(_T_2253, UInt<1>(0h0)) when _T_2254 : node _T_2255 = eq(address_ok_1, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2256 = asUInt(reset) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) when _T_2257 : node _T_2258 = eq(source_ok_2, UInt<1>(0h0)) when _T_2258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2262 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_168 node _T_2266 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(_T_2266, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2266, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2273 = eq(a_first, UInt<1>(0h0)) node _T_2274 = and(io.in.a.valid, _T_2273) when _T_2274 : node _T_2275 = eq(io.in.a.bits.opcode, opcode) node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : node _T_2278 = eq(_T_2275, UInt<1>(0h0)) when _T_2278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2275, UInt<1>(0h1), "") : assert_171 node _T_2279 = eq(io.in.a.bits.param, param) node _T_2280 = asUInt(reset) node _T_2281 = eq(_T_2280, UInt<1>(0h0)) when _T_2281 : node _T_2282 = eq(_T_2279, UInt<1>(0h0)) when _T_2282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2279, UInt<1>(0h1), "") : assert_172 node _T_2283 = eq(io.in.a.bits.size, size) node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(_T_2283, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2283, UInt<1>(0h1), "") : assert_173 node _T_2287 = eq(io.in.a.bits.source, source) node _T_2288 = asUInt(reset) node _T_2289 = eq(_T_2288, UInt<1>(0h0)) when _T_2289 : node _T_2290 = eq(_T_2287, UInt<1>(0h0)) when _T_2290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2287, UInt<1>(0h1), "") : assert_174 node _T_2291 = eq(io.in.a.bits.address, address) node _T_2292 = asUInt(reset) node _T_2293 = eq(_T_2292, UInt<1>(0h0)) when _T_2293 : node _T_2294 = eq(_T_2291, UInt<1>(0h0)) when _T_2294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2291, UInt<1>(0h1), "") : assert_175 node _T_2295 = and(io.in.a.ready, io.in.a.valid) node _T_2296 = and(_T_2295, a_first) when _T_2296 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2297 = eq(d_first, UInt<1>(0h0)) node _T_2298 = and(io.in.d.valid, _T_2297) when _T_2298 : node _T_2299 = eq(io.in.d.bits.opcode, opcode_1) node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : node _T_2302 = eq(_T_2299, UInt<1>(0h0)) when _T_2302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2299, UInt<1>(0h1), "") : assert_176 node _T_2303 = eq(io.in.d.bits.param, param_1) node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(_T_2303, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2303, UInt<1>(0h1), "") : assert_177 node _T_2307 = eq(io.in.d.bits.size, size_1) node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : node _T_2310 = eq(_T_2307, UInt<1>(0h0)) when _T_2310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2307, UInt<1>(0h1), "") : assert_178 node _T_2311 = eq(io.in.d.bits.source, source_1) node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : node _T_2314 = eq(_T_2311, UInt<1>(0h0)) when _T_2314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2311, UInt<1>(0h1), "") : assert_179 node _T_2315 = eq(io.in.d.bits.sink, sink) node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : node _T_2318 = eq(_T_2315, UInt<1>(0h0)) when _T_2318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2315, UInt<1>(0h1), "") : assert_180 node _T_2319 = eq(io.in.d.bits.denied, denied) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_181 node _T_2323 = and(io.in.d.ready, io.in.d.valid) node _T_2324 = and(_T_2323, d_first) when _T_2324 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2325 = eq(b_first, UInt<1>(0h0)) node _T_2326 = and(io.in.b.valid, _T_2325) when _T_2326 : node _T_2327 = eq(io.in.b.bits.opcode, opcode_2) node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : node _T_2330 = eq(_T_2327, UInt<1>(0h0)) when _T_2330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2327, UInt<1>(0h1), "") : assert_182 node _T_2331 = eq(io.in.b.bits.param, param_2) node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(_T_2331, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2331, UInt<1>(0h1), "") : assert_183 node _T_2335 = eq(io.in.b.bits.size, size_2) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_184 node _T_2339 = eq(io.in.b.bits.source, source_2) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_185 node _T_2343 = eq(io.in.b.bits.address, address_1) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_186 node _T_2347 = and(io.in.b.ready, io.in.b.valid) node _T_2348 = and(_T_2347, b_first) when _T_2348 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2349 = eq(c_first, UInt<1>(0h0)) node _T_2350 = and(io.in.c.valid, _T_2349) when _T_2350 : node _T_2351 = eq(io.in.c.bits.opcode, opcode_3) node _T_2352 = asUInt(reset) node _T_2353 = eq(_T_2352, UInt<1>(0h0)) when _T_2353 : node _T_2354 = eq(_T_2351, UInt<1>(0h0)) when _T_2354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2351, UInt<1>(0h1), "") : assert_187 node _T_2355 = eq(io.in.c.bits.param, param_3) node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(_T_2355, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2355, UInt<1>(0h1), "") : assert_188 node _T_2359 = eq(io.in.c.bits.size, size_3) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(_T_2359, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2359, UInt<1>(0h1), "") : assert_189 node _T_2363 = eq(io.in.c.bits.source, source_3) node _T_2364 = asUInt(reset) node _T_2365 = eq(_T_2364, UInt<1>(0h0)) when _T_2365 : node _T_2366 = eq(_T_2363, UInt<1>(0h0)) when _T_2366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2363, UInt<1>(0h1), "") : assert_190 node _T_2367 = eq(io.in.c.bits.address, address_2) node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(_T_2367, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2367, UInt<1>(0h1), "") : assert_191 node _T_2371 = and(io.in.c.ready, io.in.c.valid) node _T_2372 = and(_T_2371, c_first) when _T_2372 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes : UInt<24>, clock, reset, UInt<24>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<3> connect a_set, UInt<3>(0h0) wire a_set_wo_ready : UInt<3> connect a_set_wo_ready, UInt<3>(0h0) wire a_opcodes_set : UInt<12> connect a_opcodes_set, UInt<12>(0h0) wire a_sizes_set : UInt<24> connect a_sizes_set, UInt<24>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2373 = and(io.in.a.valid, a_first_1) node _T_2374 = and(_T_2373, UInt<1>(0h1)) when _T_2374 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2375 = and(io.in.a.ready, io.in.a.valid) node _T_2376 = and(_T_2375, a_first_1) node _T_2377 = and(_T_2376, UInt<1>(0h1)) when _T_2377 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2378 = dshr(inflight, io.in.a.bits.source) node _T_2379 = bits(_T_2378, 0, 0) node _T_2380 = eq(_T_2379, UInt<1>(0h0)) node _T_2381 = asUInt(reset) node _T_2382 = eq(_T_2381, UInt<1>(0h0)) when _T_2382 : node _T_2383 = eq(_T_2380, UInt<1>(0h0)) when _T_2383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2380, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<3> connect d_clr, UInt<3>(0h0) wire d_clr_wo_ready : UInt<3> connect d_clr_wo_ready, UInt<3>(0h0) wire d_opcodes_clr : UInt<12> connect d_opcodes_clr, UInt<12>(0h0) wire d_sizes_clr : UInt<24> connect d_sizes_clr, UInt<24>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2384 = and(io.in.d.valid, d_first_1) node _T_2385 = and(_T_2384, UInt<1>(0h1)) node _T_2386 = eq(d_release_ack, UInt<1>(0h0)) node _T_2387 = and(_T_2385, _T_2386) when _T_2387 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2388 = and(io.in.d.ready, io.in.d.valid) node _T_2389 = and(_T_2388, d_first_1) node _T_2390 = and(_T_2389, UInt<1>(0h1)) node _T_2391 = eq(d_release_ack, UInt<1>(0h0)) node _T_2392 = and(_T_2390, _T_2391) when _T_2392 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2393 = and(io.in.d.valid, d_first_1) node _T_2394 = and(_T_2393, UInt<1>(0h1)) node _T_2395 = eq(d_release_ack, UInt<1>(0h0)) node _T_2396 = and(_T_2394, _T_2395) when _T_2396 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2397 = dshr(inflight, io.in.d.bits.source) node _T_2398 = bits(_T_2397, 0, 0) node _T_2399 = or(_T_2398, same_cycle_resp) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2403 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2404 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2405 = or(_T_2403, _T_2404) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_194 node _T_2409 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_195 else : node _T_2413 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2414 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2415 = or(_T_2413, _T_2414) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_196 node _T_2419 = eq(io.in.d.bits.size, a_size_lookup) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_197 node _T_2423 = and(io.in.d.valid, d_first_1) node _T_2424 = and(_T_2423, a_first_1) node _T_2425 = and(_T_2424, io.in.a.valid) node _T_2426 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2427 = and(_T_2425, _T_2426) node _T_2428 = eq(d_release_ack, UInt<1>(0h0)) node _T_2429 = and(_T_2427, _T_2428) when _T_2429 : node _T_2430 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2431 = or(_T_2430, io.in.a.ready) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_198 node _T_2435 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2436 = orr(a_set_wo_ready) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) node _T_2438 = or(_T_2435, _T_2437) node _T_2439 = asUInt(reset) node _T_2440 = eq(_T_2439, UInt<1>(0h0)) when _T_2440 : node _T_2441 = eq(_T_2438, UInt<1>(0h0)) when _T_2441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2438, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_83 node _T_2442 = orr(inflight) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) node _T_2444 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2445 = or(_T_2443, _T_2444) node _T_2446 = lt(watchdog, plusarg_reader.out) node _T_2447 = or(_T_2445, _T_2446) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2451 = and(io.in.a.ready, io.in.a.valid) node _T_2452 = and(io.in.d.ready, io.in.d.valid) node _T_2453 = or(_T_2451, _T_2452) when _T_2453 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes_1 : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes_1 : UInt<24>, clock, reset, UInt<24>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<3> connect c_set, UInt<3>(0h0) wire c_set_wo_ready : UInt<3> connect c_set_wo_ready, UInt<3>(0h0) wire c_opcodes_set : UInt<12> connect c_opcodes_set, UInt<12>(0h0) wire c_sizes_set : UInt<24> connect c_sizes_set, UInt<24>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2454 = and(io.in.c.valid, c_first_1) node _T_2455 = bits(io.in.c.bits.opcode, 2, 2) node _T_2456 = bits(io.in.c.bits.opcode, 1, 1) node _T_2457 = and(_T_2455, _T_2456) node _T_2458 = and(_T_2454, _T_2457) when _T_2458 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2459 = and(io.in.c.ready, io.in.c.valid) node _T_2460 = and(_T_2459, c_first_1) node _T_2461 = bits(io.in.c.bits.opcode, 2, 2) node _T_2462 = bits(io.in.c.bits.opcode, 1, 1) node _T_2463 = and(_T_2461, _T_2462) node _T_2464 = and(_T_2460, _T_2463) when _T_2464 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2465 = dshr(inflight_1, io.in.c.bits.source) node _T_2466 = bits(_T_2465, 0, 0) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<3> connect d_clr_1, UInt<3>(0h0) wire d_clr_wo_ready_1 : UInt<3> connect d_clr_wo_ready_1, UInt<3>(0h0) wire d_opcodes_clr_1 : UInt<12> connect d_opcodes_clr_1, UInt<12>(0h0) wire d_sizes_clr_1 : UInt<24> connect d_sizes_clr_1, UInt<24>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2471 = and(io.in.d.valid, d_first_2) node _T_2472 = and(_T_2471, UInt<1>(0h1)) node _T_2473 = and(_T_2472, d_release_ack_1) when _T_2473 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2474 = and(io.in.d.ready, io.in.d.valid) node _T_2475 = and(_T_2474, d_first_2) node _T_2476 = and(_T_2475, UInt<1>(0h1)) node _T_2477 = and(_T_2476, d_release_ack_1) when _T_2477 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2478 = and(io.in.d.valid, d_first_2) node _T_2479 = and(_T_2478, UInt<1>(0h1)) node _T_2480 = and(_T_2479, d_release_ack_1) when _T_2480 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2481 = dshr(inflight_1, io.in.d.bits.source) node _T_2482 = bits(_T_2481, 0, 0) node _T_2483 = or(_T_2482, same_cycle_resp_1) node _T_2484 = asUInt(reset) node _T_2485 = eq(_T_2484, UInt<1>(0h0)) when _T_2485 : node _T_2486 = eq(_T_2483, UInt<1>(0h0)) when _T_2486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2483, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2487 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2488 = asUInt(reset) node _T_2489 = eq(_T_2488, UInt<1>(0h0)) when _T_2489 : node _T_2490 = eq(_T_2487, UInt<1>(0h0)) when _T_2490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2487, UInt<1>(0h1), "") : assert_203 else : node _T_2491 = eq(io.in.d.bits.size, c_size_lookup) node _T_2492 = asUInt(reset) node _T_2493 = eq(_T_2492, UInt<1>(0h0)) when _T_2493 : node _T_2494 = eq(_T_2491, UInt<1>(0h0)) when _T_2494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2491, UInt<1>(0h1), "") : assert_204 node _T_2495 = and(io.in.d.valid, d_first_2) node _T_2496 = and(_T_2495, c_first_1) node _T_2497 = and(_T_2496, io.in.c.valid) node _T_2498 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2499 = and(_T_2497, _T_2498) node _T_2500 = and(_T_2499, d_release_ack_1) node _T_2501 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2502 = and(_T_2500, _T_2501) when _T_2502 : node _T_2503 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2504 = or(_T_2503, io.in.c.ready) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_205 node _T_2508 = orr(c_set_wo_ready) when _T_2508 : node _T_2509 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_84 node _T_2513 = orr(inflight_1) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) node _T_2515 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2516 = or(_T_2514, _T_2515) node _T_2517 = lt(watchdog_1, plusarg_reader_1.out) node _T_2518 = or(_T_2516, _T_2517) node _T_2519 = asUInt(reset) node _T_2520 = eq(_T_2519, UInt<1>(0h0)) when _T_2520 : node _T_2521 = eq(_T_2518, UInt<1>(0h0)) when _T_2521 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2518, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2522 = and(io.in.c.ready, io.in.c.valid) node _T_2523 = and(io.in.d.ready, io.in.d.valid) node _T_2524 = or(_T_2522, _T_2523) when _T_2524 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2525 = and(io.in.d.ready, io.in.d.valid) node _T_2526 = and(_T_2525, d_first_3) node _T_2527 = bits(io.in.d.bits.opcode, 2, 2) node _T_2528 = bits(io.in.d.bits.opcode, 1, 1) node _T_2529 = eq(_T_2528, UInt<1>(0h0)) node _T_2530 = and(_T_2527, _T_2529) node _T_2531 = and(_T_2526, _T_2530) when _T_2531 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2532 = dshr(inflight_2, io.in.d.bits.sink) node _T_2533 = bits(_T_2532, 0, 0) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) node _T_2535 = asUInt(reset) node _T_2536 = eq(_T_2535, UInt<1>(0h0)) when _T_2536 : node _T_2537 = eq(_T_2534, UInt<1>(0h0)) when _T_2537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2534, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2538 = and(io.in.e.ready, io.in.e.valid) node _T_2539 = and(_T_2538, UInt<1>(0h1)) node _T_2540 = and(_T_2539, UInt<1>(0h1)) when _T_2540 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2541 = or(d_set, inflight_2) node _T_2542 = dshr(_T_2541, io.in.e.bits.sink) node _T_2543 = bits(_T_2542, 0, 0) node _T_2544 = asUInt(reset) node _T_2545 = eq(_T_2544, UInt<1>(0h0)) when _T_2545 : node _T_2546 = eq(_T_2543, UInt<1>(0h0)) when _T_2546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2543, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_41( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _legal_source_T = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31] wire _legal_source_T_4 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_6 = _legal_source_T_4; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_5 = {_legal_source_WIRE_2, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = {1'h0, _legal_source_T_6} \| _legal_source_T_5; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_23 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_24 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2540 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2540 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s5k5z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_14 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s5k5z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s5k5z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_4.bits.sink, UInt<5>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_10.bits.sink, UInt<5>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_39 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_40 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLBuffer_a32d64s5k5z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [4:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [4:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_14 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s5k5z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k5z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_45 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut	module MulFullRawFN_45( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T \| _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 \| io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 \| io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 \| _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 \| notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 \| io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BoomIOMSHR : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, mem_access : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip mem_ack : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}, clock reg grant_word : UInt<64>, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T wire size : UInt<2> connect size, req.uop.mem_size node a_data = cat(req.data, req.data) node _get_legal_T = leq(UInt<1>(0h0), req.uop.mem_size) node _get_legal_T_1 = leq(req.uop.mem_size, UInt<4>(0hc)) node _get_legal_T_2 = and(_get_legal_T, _get_legal_T_1) node _get_legal_T_3 = or(UInt<1>(0h0), _get_legal_T_2) node _get_legal_T_4 = xor(req.addr, UInt<14>(0h3000)) node _get_legal_T_5 = cvt(_get_legal_T_4) node _get_legal_T_6 = and(_get_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _get_legal_T_7 = asSInt(_get_legal_T_6) node _get_legal_T_8 = eq(_get_legal_T_7, asSInt(UInt<1>(0h0))) node _get_legal_T_9 = and(_get_legal_T_3, _get_legal_T_8) node _get_legal_T_10 = leq(UInt<1>(0h0), req.uop.mem_size) node _get_legal_T_11 = leq(req.uop.mem_size, UInt<3>(0h6)) node _get_legal_T_12 = and(_get_legal_T_10, _get_legal_T_11) node _get_legal_T_13 = or(UInt<1>(0h0), _get_legal_T_12) node _get_legal_T_14 = xor(req.addr, UInt<1>(0h0)) node _get_legal_T_15 = cvt(_get_legal_T_14) node _get_legal_T_16 = and(_get_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _get_legal_T_17 = asSInt(_get_legal_T_16) node _get_legal_T_18 = eq(_get_legal_T_17, asSInt(UInt<1>(0h0))) node _get_legal_T_19 = xor(req.addr, UInt<17>(0h10000)) node _get_legal_T_20 = cvt(_get_legal_T_19) node _get_legal_T_21 = and(_get_legal_T_20, asSInt(UInt<33>(0h98013000))) node _get_legal_T_22 = asSInt(_get_legal_T_21) node _get_legal_T_23 = eq(_get_legal_T_22, asSInt(UInt<1>(0h0))) node _get_legal_T_24 = xor(req.addr, UInt<17>(0h10000)) node _get_legal_T_25 = cvt(_get_legal_T_24) node _get_legal_T_26 = and(_get_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _get_legal_T_27 = asSInt(_get_legal_T_26) node _get_legal_T_28 = eq(_get_legal_T_27, asSInt(UInt<1>(0h0))) node _get_legal_T_29 = xor(req.addr, UInt<26>(0h2000000)) node _get_legal_T_30 = cvt(_get_legal_T_29) node _get_legal_T_31 = and(_get_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _get_legal_T_32 = asSInt(_get_legal_T_31) node _get_legal_T_33 = eq(_get_legal_T_32, asSInt(UInt<1>(0h0))) node _get_legal_T_34 = xor(req.addr, UInt<28>(0h8000000)) node _get_legal_T_35 = cvt(_get_legal_T_34) node _get_legal_T_36 = and(_get_legal_T_35, asSInt(UInt<33>(0h98000000))) node _get_legal_T_37 = asSInt(_get_legal_T_36) node _get_legal_T_38 = eq(_get_legal_T_37, asSInt(UInt<1>(0h0))) node _get_legal_T_39 = xor(req.addr, UInt<28>(0h8000000)) node _get_legal_T_40 = cvt(_get_legal_T_39) node _get_legal_T_41 = and(_get_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _get_legal_T_42 = asSInt(_get_legal_T_41) node _get_legal_T_43 = eq(_get_legal_T_42, asSInt(UInt<1>(0h0))) node _get_legal_T_44 = xor(req.addr, UInt<29>(0h10000000)) node _get_legal_T_45 = cvt(_get_legal_T_44) node _get_legal_T_46 = and(_get_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _get_legal_T_47 = asSInt(_get_legal_T_46) node _get_legal_T_48 = eq(_get_legal_T_47, asSInt(UInt<1>(0h0))) node _get_legal_T_49 = xor(req.addr, UInt<32>(0h80000000)) node _get_legal_T_50 = cvt(_get_legal_T_49) node _get_legal_T_51 = and(_get_legal_T_50, asSInt(UInt<33>(0h90000000))) node _get_legal_T_52 = asSInt(_get_legal_T_51) node _get_legal_T_53 = eq(_get_legal_T_52, asSInt(UInt<1>(0h0))) node _get_legal_T_54 = or(_get_legal_T_18, _get_legal_T_23) node _get_legal_T_55 = or(_get_legal_T_54, _get_legal_T_28) node _get_legal_T_56 = or(_get_legal_T_55, _get_legal_T_33) node _get_legal_T_57 = or(_get_legal_T_56, _get_legal_T_38) node _get_legal_T_58 = or(_get_legal_T_57, _get_legal_T_43) node _get_legal_T_59 = or(_get_legal_T_58, _get_legal_T_48) node _get_legal_T_60 = or(_get_legal_T_59, _get_legal_T_53) node _get_legal_T_61 = and(_get_legal_T_13, _get_legal_T_60) node _get_legal_T_62 = or(UInt<1>(0h0), _get_legal_T_9) node get_legal = or(_get_legal_T_62, _get_legal_T_61) wire get : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect get.opcode, UInt<3>(0h4) connect get.param, UInt<1>(0h0) connect get.size, req.uop.mem_size connect get.source, UInt<3>(0h5) connect get.address, req.addr node _get_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<4>(0h0)) node get_a_mask_sizeOH_shiftAmount = bits(_get_a_mask_sizeOH_T, 1, 0) node _get_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_a_mask_sizeOH_shiftAmount) node _get_a_mask_sizeOH_T_2 = bits(_get_a_mask_sizeOH_T_1, 3, 0) node get_a_mask_sizeOH = or(_get_a_mask_sizeOH_T_2, UInt<1>(0h1)) node get_a_mask_sub_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<3>(0h4)) node get_a_mask_sub_sub_sub_size = bits(get_a_mask_sizeOH, 3, 3) node get_a_mask_sub_sub_sub_bit = bits(req.addr, 3, 3) node get_a_mask_sub_sub_sub_nbit = eq(get_a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node get_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_sub_nbit) node _get_a_mask_sub_sub_sub_acc_T = and(get_a_mask_sub_sub_sub_size, get_a_mask_sub_sub_sub_0_2) node get_a_mask_sub_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_sub_0_1, _get_a_mask_sub_sub_sub_acc_T) node get_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_sub_bit) node _get_a_mask_sub_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_sub_size, get_a_mask_sub_sub_sub_1_2) node get_a_mask_sub_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_sub_0_1, _get_a_mask_sub_sub_sub_acc_T_1) node get_a_mask_sub_sub_size = bits(get_a_mask_sizeOH, 2, 2) node get_a_mask_sub_sub_bit = bits(req.addr, 2, 2) node get_a_mask_sub_sub_nbit = eq(get_a_mask_sub_sub_bit, UInt<1>(0h0)) node get_a_mask_sub_sub_0_2 = and(get_a_mask_sub_sub_sub_0_2, get_a_mask_sub_sub_nbit) node _get_a_mask_sub_sub_acc_T = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_0_2) node get_a_mask_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T) node get_a_mask_sub_sub_1_2 = and(get_a_mask_sub_sub_sub_0_2, get_a_mask_sub_sub_bit) node _get_a_mask_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_1_2) node get_a_mask_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T_1) node get_a_mask_sub_sub_2_2 = and(get_a_mask_sub_sub_sub_1_2, get_a_mask_sub_sub_nbit) node _get_a_mask_sub_sub_acc_T_2 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_2_2) node get_a_mask_sub_sub_2_1 = or(get_a_mask_sub_sub_sub_1_1, _get_a_mask_sub_sub_acc_T_2) node get_a_mask_sub_sub_3_2 = and(get_a_mask_sub_sub_sub_1_2, get_a_mask_sub_sub_bit) node _get_a_mask_sub_sub_acc_T_3 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_3_2) node get_a_mask_sub_sub_3_1 = or(get_a_mask_sub_sub_sub_1_1, _get_a_mask_sub_sub_acc_T_3) node get_a_mask_sub_size = bits(get_a_mask_sizeOH, 1, 1) node get_a_mask_sub_bit = bits(req.addr, 1, 1) node get_a_mask_sub_nbit = eq(get_a_mask_sub_bit, UInt<1>(0h0)) node get_a_mask_sub_0_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T = and(get_a_mask_sub_size, get_a_mask_sub_0_2) node get_a_mask_sub_0_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T) node get_a_mask_sub_1_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_bit) node _get_a_mask_sub_acc_T_1 = and(get_a_mask_sub_size, get_a_mask_sub_1_2) node get_a_mask_sub_1_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T_1) node get_a_mask_sub_2_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T_2 = and(get_a_mask_sub_size, get_a_mask_sub_2_2) node get_a_mask_sub_2_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_2) node get_a_mask_sub_3_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_bit) node _get_a_mask_sub_acc_T_3 = and(get_a_mask_sub_size, get_a_mask_sub_3_2) node get_a_mask_sub_3_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_3) node get_a_mask_sub_4_2 = and(get_a_mask_sub_sub_2_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T_4 = and(get_a_mask_sub_size, get_a_mask_sub_4_2) node get_a_mask_sub_4_1 = or(get_a_mask_sub_sub_2_1, _get_a_mask_sub_acc_T_4) node get_a_mask_sub_5_2 = and(get_a_mask_sub_sub_2_2, get_a_mask_sub_bit) node _get_a_mask_sub_acc_T_5 = and(get_a_mask_sub_size, get_a_mask_sub_5_2) node get_a_mask_sub_5_1 = or(get_a_mask_sub_sub_2_1, _get_a_mask_sub_acc_T_5) node get_a_mask_sub_6_2 = and(get_a_mask_sub_sub_3_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T_6 = and(get_a_mask_sub_size, get_a_mask_sub_6_2) node get_a_mask_sub_6_1 = or(get_a_mask_sub_sub_3_1, _get_a_mask_sub_acc_T_6) node get_a_mask_sub_7_2 = and(get_a_mask_sub_sub_3_2, get_a_mask_sub_bit) node _get_a_mask_sub_acc_T_7 = and(get_a_mask_sub_size, get_a_mask_sub_7_2) node get_a_mask_sub_7_1 = or(get_a_mask_sub_sub_3_1, _get_a_mask_sub_acc_T_7) node get_a_mask_size = bits(get_a_mask_sizeOH, 0, 0) node get_a_mask_bit = bits(req.addr, 0, 0) node get_a_mask_nbit = eq(get_a_mask_bit, UInt<1>(0h0)) node get_a_mask_eq = and(get_a_mask_sub_0_2, get_a_mask_nbit) node _get_a_mask_acc_T = and(get_a_mask_size, get_a_mask_eq) node get_a_mask_acc = or(get_a_mask_sub_0_1, _get_a_mask_acc_T) node get_a_mask_eq_1 = and(get_a_mask_sub_0_2, get_a_mask_bit) node _get_a_mask_acc_T_1 = and(get_a_mask_size, get_a_mask_eq_1) node get_a_mask_acc_1 = or(get_a_mask_sub_0_1, _get_a_mask_acc_T_1) node get_a_mask_eq_2 = and(get_a_mask_sub_1_2, get_a_mask_nbit) node _get_a_mask_acc_T_2 = and(get_a_mask_size, get_a_mask_eq_2) node get_a_mask_acc_2 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_2) node get_a_mask_eq_3 = and(get_a_mask_sub_1_2, get_a_mask_bit) node _get_a_mask_acc_T_3 = and(get_a_mask_size, get_a_mask_eq_3) node get_a_mask_acc_3 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_3) node get_a_mask_eq_4 = and(get_a_mask_sub_2_2, get_a_mask_nbit) node _get_a_mask_acc_T_4 = and(get_a_mask_size, get_a_mask_eq_4) node get_a_mask_acc_4 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_4) node get_a_mask_eq_5 = and(get_a_mask_sub_2_2, get_a_mask_bit) node _get_a_mask_acc_T_5 = and(get_a_mask_size, get_a_mask_eq_5) node get_a_mask_acc_5 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_5) node get_a_mask_eq_6 = and(get_a_mask_sub_3_2, get_a_mask_nbit) node _get_a_mask_acc_T_6 = and(get_a_mask_size, get_a_mask_eq_6) node get_a_mask_acc_6 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_6) node get_a_mask_eq_7 = and(get_a_mask_sub_3_2, get_a_mask_bit) node _get_a_mask_acc_T_7 = and(get_a_mask_size, get_a_mask_eq_7) node get_a_mask_acc_7 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_7) node get_a_mask_eq_8 = and(get_a_mask_sub_4_2, get_a_mask_nbit) node _get_a_mask_acc_T_8 = and(get_a_mask_size, get_a_mask_eq_8) node get_a_mask_acc_8 = or(get_a_mask_sub_4_1, _get_a_mask_acc_T_8) node get_a_mask_eq_9 = and(get_a_mask_sub_4_2, get_a_mask_bit) node _get_a_mask_acc_T_9 = and(get_a_mask_size, get_a_mask_eq_9) node get_a_mask_acc_9 = or(get_a_mask_sub_4_1, _get_a_mask_acc_T_9) node get_a_mask_eq_10 = and(get_a_mask_sub_5_2, get_a_mask_nbit) node _get_a_mask_acc_T_10 = and(get_a_mask_size, get_a_mask_eq_10) node get_a_mask_acc_10 = or(get_a_mask_sub_5_1, _get_a_mask_acc_T_10) node get_a_mask_eq_11 = and(get_a_mask_sub_5_2, get_a_mask_bit) node _get_a_mask_acc_T_11 = and(get_a_mask_size, get_a_mask_eq_11) node get_a_mask_acc_11 = or(get_a_mask_sub_5_1, _get_a_mask_acc_T_11) node get_a_mask_eq_12 = and(get_a_mask_sub_6_2, get_a_mask_nbit) node _get_a_mask_acc_T_12 = and(get_a_mask_size, get_a_mask_eq_12) node get_a_mask_acc_12 = or(get_a_mask_sub_6_1, _get_a_mask_acc_T_12) node get_a_mask_eq_13 = and(get_a_mask_sub_6_2, get_a_mask_bit) node _get_a_mask_acc_T_13 = and(get_a_mask_size, get_a_mask_eq_13) node get_a_mask_acc_13 = or(get_a_mask_sub_6_1, _get_a_mask_acc_T_13) node get_a_mask_eq_14 = and(get_a_mask_sub_7_2, get_a_mask_nbit) node _get_a_mask_acc_T_14 = and(get_a_mask_size, get_a_mask_eq_14) node get_a_mask_acc_14 = or(get_a_mask_sub_7_1, _get_a_mask_acc_T_14) node get_a_mask_eq_15 = and(get_a_mask_sub_7_2, get_a_mask_bit) node _get_a_mask_acc_T_15 = and(get_a_mask_size, get_a_mask_eq_15) node get_a_mask_acc_15 = or(get_a_mask_sub_7_1, _get_a_mask_acc_T_15) node get_a_mask_lo_lo_lo = cat(get_a_mask_acc_1, get_a_mask_acc) node get_a_mask_lo_lo_hi = cat(get_a_mask_acc_3, get_a_mask_acc_2) node get_a_mask_lo_lo = cat(get_a_mask_lo_lo_hi, get_a_mask_lo_lo_lo) node get_a_mask_lo_hi_lo = cat(get_a_mask_acc_5, get_a_mask_acc_4) node get_a_mask_lo_hi_hi = cat(get_a_mask_acc_7, get_a_mask_acc_6) node get_a_mask_lo_hi = cat(get_a_mask_lo_hi_hi, get_a_mask_lo_hi_lo) node get_a_mask_lo = cat(get_a_mask_lo_hi, get_a_mask_lo_lo) node get_a_mask_hi_lo_lo = cat(get_a_mask_acc_9, get_a_mask_acc_8) node get_a_mask_hi_lo_hi = cat(get_a_mask_acc_11, get_a_mask_acc_10) node get_a_mask_hi_lo = cat(get_a_mask_hi_lo_hi, get_a_mask_hi_lo_lo) node get_a_mask_hi_hi_lo = cat(get_a_mask_acc_13, get_a_mask_acc_12) node get_a_mask_hi_hi_hi = cat(get_a_mask_acc_15, get_a_mask_acc_14) node get_a_mask_hi_hi = cat(get_a_mask_hi_hi_hi, get_a_mask_hi_hi_lo) node get_a_mask_hi = cat(get_a_mask_hi_hi, get_a_mask_hi_lo) node _get_a_mask_T = cat(get_a_mask_hi, get_a_mask_lo) connect get.mask, _get_a_mask_T invalidate get.data connect get.corrupt, UInt<1>(0h0) node _put_legal_T = leq(UInt<1>(0h0), req.uop.mem_size) node _put_legal_T_1 = leq(req.uop.mem_size, UInt<4>(0hc)) node _put_legal_T_2 = and(_put_legal_T, _put_legal_T_1) node _put_legal_T_3 = or(UInt<1>(0h0), _put_legal_T_2) node _put_legal_T_4 = xor(req.addr, UInt<14>(0h3000)) node _put_legal_T_5 = cvt(_put_legal_T_4) node _put_legal_T_6 = and(_put_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _put_legal_T_7 = asSInt(_put_legal_T_6) node _put_legal_T_8 = eq(_put_legal_T_7, asSInt(UInt<1>(0h0))) node _put_legal_T_9 = and(_put_legal_T_3, _put_legal_T_8) node _put_legal_T_10 = leq(UInt<1>(0h0), req.uop.mem_size) node _put_legal_T_11 = leq(req.uop.mem_size, UInt<3>(0h6)) node _put_legal_T_12 = and(_put_legal_T_10, _put_legal_T_11) node _put_legal_T_13 = or(UInt<1>(0h0), _put_legal_T_12) node _put_legal_T_14 = xor(req.addr, UInt<1>(0h0)) node _put_legal_T_15 = cvt(_put_legal_T_14) node _put_legal_T_16 = and(_put_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _put_legal_T_17 = asSInt(_put_legal_T_16) node _put_legal_T_18 = eq(_put_legal_T_17, asSInt(UInt<1>(0h0))) node _put_legal_T_19 = xor(req.addr, UInt<21>(0h100000)) node _put_legal_T_20 = cvt(_put_legal_T_19) node _put_legal_T_21 = and(_put_legal_T_20, asSInt(UInt<33>(0h9a103000))) node _put_legal_T_22 = asSInt(_put_legal_T_21) node _put_legal_T_23 = eq(_put_legal_T_22, asSInt(UInt<1>(0h0))) node _put_legal_T_24 = xor(req.addr, UInt<26>(0h2000000)) node _put_legal_T_25 = cvt(_put_legal_T_24) node _put_legal_T_26 = and(_put_legal_T_25, asSInt(UInt<33>(0h9a110000))) node _put_legal_T_27 = asSInt(_put_legal_T_26) node _put_legal_T_28 = eq(_put_legal_T_27, asSInt(UInt<1>(0h0))) node _put_legal_T_29 = xor(req.addr, UInt<26>(0h2010000)) node _put_legal_T_30 = cvt(_put_legal_T_29) node _put_legal_T_31 = and(_put_legal_T_30, asSInt(UInt<33>(0h9a113000))) node _put_legal_T_32 = asSInt(_put_legal_T_31) node _put_legal_T_33 = eq(_put_legal_T_32, asSInt(UInt<1>(0h0))) node _put_legal_T_34 = xor(req.addr, UInt<28>(0h8000000)) node _put_legal_T_35 = cvt(_put_legal_T_34) node _put_legal_T_36 = and(_put_legal_T_35, asSInt(UInt<33>(0h98000000))) node _put_legal_T_37 = asSInt(_put_legal_T_36) node _put_legal_T_38 = eq(_put_legal_T_37, asSInt(UInt<1>(0h0))) node _put_legal_T_39 = xor(req.addr, UInt<28>(0h8000000)) node _put_legal_T_40 = cvt(_put_legal_T_39) node _put_legal_T_41 = and(_put_legal_T_40, asSInt(UInt<33>(0h9a110000))) node _put_legal_T_42 = asSInt(_put_legal_T_41) node _put_legal_T_43 = eq(_put_legal_T_42, asSInt(UInt<1>(0h0))) node _put_legal_T_44 = xor(req.addr, UInt<29>(0h10000000)) node _put_legal_T_45 = cvt(_put_legal_T_44) node _put_legal_T_46 = and(_put_legal_T_45, asSInt(UInt<33>(0h9a113000))) node _put_legal_T_47 = asSInt(_put_legal_T_46) node _put_legal_T_48 = eq(_put_legal_T_47, asSInt(UInt<1>(0h0))) node _put_legal_T_49 = xor(req.addr, UInt<32>(0h80000000)) node _put_legal_T_50 = cvt(_put_legal_T_49) node _put_legal_T_51 = and(_put_legal_T_50, asSInt(UInt<33>(0h90000000))) node _put_legal_T_52 = asSInt(_put_legal_T_51) node _put_legal_T_53 = eq(_put_legal_T_52, asSInt(UInt<1>(0h0))) node _put_legal_T_54 = or(_put_legal_T_18, _put_legal_T_23) node _put_legal_T_55 = or(_put_legal_T_54, _put_legal_T_28) node _put_legal_T_56 = or(_put_legal_T_55, _put_legal_T_33) node _put_legal_T_57 = or(_put_legal_T_56, _put_legal_T_38) node _put_legal_T_58 = or(_put_legal_T_57, _put_legal_T_43) node _put_legal_T_59 = or(_put_legal_T_58, _put_legal_T_48) node _put_legal_T_60 = or(_put_legal_T_59, _put_legal_T_53) node _put_legal_T_61 = and(_put_legal_T_13, _put_legal_T_60) node _put_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) node _put_legal_T_63 = xor(req.addr, UInt<17>(0h10000)) node _put_legal_T_64 = cvt(_put_legal_T_63) node _put_legal_T_65 = and(_put_legal_T_64, asSInt(UInt<33>(0h9a110000))) node _put_legal_T_66 = asSInt(_put_legal_T_65) node _put_legal_T_67 = eq(_put_legal_T_66, asSInt(UInt<1>(0h0))) node _put_legal_T_68 = and(_put_legal_T_62, _put_legal_T_67) node _put_legal_T_69 = or(UInt<1>(0h0), _put_legal_T_9) node _put_legal_T_70 = or(_put_legal_T_69, _put_legal_T_61) node put_legal = or(_put_legal_T_70, _put_legal_T_68) wire put : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect put.opcode, UInt<1>(0h0) connect put.param, UInt<1>(0h0) connect put.size, req.uop.mem_size connect put.source, UInt<3>(0h5) connect put.address, req.addr node _put_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<4>(0h0)) node put_a_mask_sizeOH_shiftAmount = bits(_put_a_mask_sizeOH_T, 1, 0) node _put_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), put_a_mask_sizeOH_shiftAmount) node _put_a_mask_sizeOH_T_2 = bits(_put_a_mask_sizeOH_T_1, 3, 0) node put_a_mask_sizeOH = or(_put_a_mask_sizeOH_T_2, UInt<1>(0h1)) node put_a_mask_sub_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<3>(0h4)) node put_a_mask_sub_sub_sub_size = bits(put_a_mask_sizeOH, 3, 3) node put_a_mask_sub_sub_sub_bit = bits(req.addr, 3, 3) node put_a_mask_sub_sub_sub_nbit = eq(put_a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node put_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_sub_nbit) node _put_a_mask_sub_sub_sub_acc_T = and(put_a_mask_sub_sub_sub_size, put_a_mask_sub_sub_sub_0_2) node put_a_mask_sub_sub_sub_0_1 = or(put_a_mask_sub_sub_sub_sub_0_1, _put_a_mask_sub_sub_sub_acc_T) node put_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_sub_bit) node _put_a_mask_sub_sub_sub_acc_T_1 = and(put_a_mask_sub_sub_sub_size, put_a_mask_sub_sub_sub_1_2) node put_a_mask_sub_sub_sub_1_1 = or(put_a_mask_sub_sub_sub_sub_0_1, _put_a_mask_sub_sub_sub_acc_T_1) node put_a_mask_sub_sub_size = bits(put_a_mask_sizeOH, 2, 2) node put_a_mask_sub_sub_bit = bits(req.addr, 2, 2) node put_a_mask_sub_sub_nbit = eq(put_a_mask_sub_sub_bit, UInt<1>(0h0)) node put_a_mask_sub_sub_0_2 = and(put_a_mask_sub_sub_sub_0_2, put_a_mask_sub_sub_nbit) node _put_a_mask_sub_sub_acc_T = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_0_2) node put_a_mask_sub_sub_0_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T) node put_a_mask_sub_sub_1_2 = and(put_a_mask_sub_sub_sub_0_2, put_a_mask_sub_sub_bit) node _put_a_mask_sub_sub_acc_T_1 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_1_2) node put_a_mask_sub_sub_1_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T_1) node put_a_mask_sub_sub_2_2 = and(put_a_mask_sub_sub_sub_1_2, put_a_mask_sub_sub_nbit) node _put_a_mask_sub_sub_acc_T_2 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_2_2) node put_a_mask_sub_sub_2_1 = or(put_a_mask_sub_sub_sub_1_1, _put_a_mask_sub_sub_acc_T_2) node put_a_mask_sub_sub_3_2 = and(put_a_mask_sub_sub_sub_1_2, put_a_mask_sub_sub_bit) node _put_a_mask_sub_sub_acc_T_3 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_3_2) node put_a_mask_sub_sub_3_1 = or(put_a_mask_sub_sub_sub_1_1, _put_a_mask_sub_sub_acc_T_3) node put_a_mask_sub_size = bits(put_a_mask_sizeOH, 1, 1) node put_a_mask_sub_bit = bits(req.addr, 1, 1) node put_a_mask_sub_nbit = eq(put_a_mask_sub_bit, UInt<1>(0h0)) node put_a_mask_sub_0_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_nbit) node _put_a_mask_sub_acc_T = and(put_a_mask_sub_size, put_a_mask_sub_0_2) node put_a_mask_sub_0_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T) node put_a_mask_sub_1_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_bit) node _put_a_mask_sub_acc_T_1 = and(put_a_mask_sub_size, put_a_mask_sub_1_2) node put_a_mask_sub_1_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T_1) node put_a_mask_sub_2_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_nbit) node _put_a_mask_sub_acc_T_2 = and(put_a_mask_sub_size, put_a_mask_sub_2_2) node put_a_mask_sub_2_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_2) node put_a_mask_sub_3_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_bit) node _put_a_mask_sub_acc_T_3 = and(put_a_mask_sub_size, put_a_mask_sub_3_2) node put_a_mask_sub_3_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_3) node put_a_mask_sub_4_2 = and(put_a_mask_sub_sub_2_2, put_a_mask_sub_nbit) node _put_a_mask_sub_acc_T_4 = and(put_a_mask_sub_size, put_a_mask_sub_4_2) node put_a_mask_sub_4_1 = or(put_a_mask_sub_sub_2_1, _put_a_mask_sub_acc_T_4) node put_a_mask_sub_5_2 = and(put_a_mask_sub_sub_2_2, put_a_mask_sub_bit) node _put_a_mask_sub_acc_T_5 = and(put_a_mask_sub_size, put_a_mask_sub_5_2) node put_a_mask_sub_5_1 = or(put_a_mask_sub_sub_2_1, _put_a_mask_sub_acc_T_5) node put_a_mask_sub_6_2 = and(put_a_mask_sub_sub_3_2, put_a_mask_sub_nbit) node _put_a_mask_sub_acc_T_6 = and(put_a_mask_sub_size, put_a_mask_sub_6_2) node put_a_mask_sub_6_1 = or(put_a_mask_sub_sub_3_1, _put_a_mask_sub_acc_T_6) node put_a_mask_sub_7_2 = and(put_a_mask_sub_sub_3_2, put_a_mask_sub_bit) node _put_a_mask_sub_acc_T_7 = and(put_a_mask_sub_size, put_a_mask_sub_7_2) node put_a_mask_sub_7_1 = or(put_a_mask_sub_sub_3_1, _put_a_mask_sub_acc_T_7) node put_a_mask_size = bits(put_a_mask_sizeOH, 0, 0) node put_a_mask_bit = bits(req.addr, 0, 0) node put_a_mask_nbit = eq(put_a_mask_bit, UInt<1>(0h0)) node put_a_mask_eq = and(put_a_mask_sub_0_2, put_a_mask_nbit) node _put_a_mask_acc_T = and(put_a_mask_size, put_a_mask_eq) node put_a_mask_acc = or(put_a_mask_sub_0_1, _put_a_mask_acc_T) node put_a_mask_eq_1 = and(put_a_mask_sub_0_2, put_a_mask_bit) node _put_a_mask_acc_T_1 = and(put_a_mask_size, put_a_mask_eq_1) node put_a_mask_acc_1 = or(put_a_mask_sub_0_1, _put_a_mask_acc_T_1) node put_a_mask_eq_2 = and(put_a_mask_sub_1_2, put_a_mask_nbit) node _put_a_mask_acc_T_2 = and(put_a_mask_size, put_a_mask_eq_2) node put_a_mask_acc_2 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_2) node put_a_mask_eq_3 = and(put_a_mask_sub_1_2, put_a_mask_bit) node _put_a_mask_acc_T_3 = and(put_a_mask_size, put_a_mask_eq_3) node put_a_mask_acc_3 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_3) node put_a_mask_eq_4 = and(put_a_mask_sub_2_2, put_a_mask_nbit) node _put_a_mask_acc_T_4 = and(put_a_mask_size, put_a_mask_eq_4) node put_a_mask_acc_4 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_4) node put_a_mask_eq_5 = and(put_a_mask_sub_2_2, put_a_mask_bit) node _put_a_mask_acc_T_5 = and(put_a_mask_size, put_a_mask_eq_5) node put_a_mask_acc_5 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_5) node put_a_mask_eq_6 = and(put_a_mask_sub_3_2, put_a_mask_nbit) node _put_a_mask_acc_T_6 = and(put_a_mask_size, put_a_mask_eq_6) node put_a_mask_acc_6 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_6) node put_a_mask_eq_7 = and(put_a_mask_sub_3_2, put_a_mask_bit) node _put_a_mask_acc_T_7 = and(put_a_mask_size, put_a_mask_eq_7) node put_a_mask_acc_7 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_7) node put_a_mask_eq_8 = and(put_a_mask_sub_4_2, put_a_mask_nbit) node _put_a_mask_acc_T_8 = and(put_a_mask_size, put_a_mask_eq_8) node put_a_mask_acc_8 = or(put_a_mask_sub_4_1, _put_a_mask_acc_T_8) node put_a_mask_eq_9 = and(put_a_mask_sub_4_2, put_a_mask_bit) node _put_a_mask_acc_T_9 = and(put_a_mask_size, put_a_mask_eq_9) node put_a_mask_acc_9 = or(put_a_mask_sub_4_1, _put_a_mask_acc_T_9) node put_a_mask_eq_10 = and(put_a_mask_sub_5_2, put_a_mask_nbit) node _put_a_mask_acc_T_10 = and(put_a_mask_size, put_a_mask_eq_10) node put_a_mask_acc_10 = or(put_a_mask_sub_5_1, _put_a_mask_acc_T_10) node put_a_mask_eq_11 = and(put_a_mask_sub_5_2, put_a_mask_bit) node _put_a_mask_acc_T_11 = and(put_a_mask_size, put_a_mask_eq_11) node put_a_mask_acc_11 = or(put_a_mask_sub_5_1, _put_a_mask_acc_T_11) node put_a_mask_eq_12 = and(put_a_mask_sub_6_2, put_a_mask_nbit) node _put_a_mask_acc_T_12 = and(put_a_mask_size, put_a_mask_eq_12) node put_a_mask_acc_12 = or(put_a_mask_sub_6_1, _put_a_mask_acc_T_12) node put_a_mask_eq_13 = and(put_a_mask_sub_6_2, put_a_mask_bit) node _put_a_mask_acc_T_13 = and(put_a_mask_size, put_a_mask_eq_13) node put_a_mask_acc_13 = or(put_a_mask_sub_6_1, _put_a_mask_acc_T_13) node put_a_mask_eq_14 = and(put_a_mask_sub_7_2, put_a_mask_nbit) node _put_a_mask_acc_T_14 = and(put_a_mask_size, put_a_mask_eq_14) node put_a_mask_acc_14 = or(put_a_mask_sub_7_1, _put_a_mask_acc_T_14) node put_a_mask_eq_15 = and(put_a_mask_sub_7_2, put_a_mask_bit) node _put_a_mask_acc_T_15 = and(put_a_mask_size, put_a_mask_eq_15) node put_a_mask_acc_15 = or(put_a_mask_sub_7_1, _put_a_mask_acc_T_15) node put_a_mask_lo_lo_lo = cat(put_a_mask_acc_1, put_a_mask_acc) node put_a_mask_lo_lo_hi = cat(put_a_mask_acc_3, put_a_mask_acc_2) node put_a_mask_lo_lo = cat(put_a_mask_lo_lo_hi, put_a_mask_lo_lo_lo) node put_a_mask_lo_hi_lo = cat(put_a_mask_acc_5, put_a_mask_acc_4) node put_a_mask_lo_hi_hi = cat(put_a_mask_acc_7, put_a_mask_acc_6) node put_a_mask_lo_hi = cat(put_a_mask_lo_hi_hi, put_a_mask_lo_hi_lo) node put_a_mask_lo = cat(put_a_mask_lo_hi, put_a_mask_lo_lo) node put_a_mask_hi_lo_lo = cat(put_a_mask_acc_9, put_a_mask_acc_8) node put_a_mask_hi_lo_hi = cat(put_a_mask_acc_11, put_a_mask_acc_10) node put_a_mask_hi_lo = cat(put_a_mask_hi_lo_hi, put_a_mask_hi_lo_lo) node put_a_mask_hi_hi_lo = cat(put_a_mask_acc_13, put_a_mask_acc_12) node put_a_mask_hi_hi_hi = cat(put_a_mask_acc_15, put_a_mask_acc_14) node put_a_mask_hi_hi = cat(put_a_mask_hi_hi_hi, put_a_mask_hi_hi_lo) node put_a_mask_hi = cat(put_a_mask_hi_hi, put_a_mask_hi_lo) node _put_a_mask_T = cat(put_a_mask_hi, put_a_mask_lo) connect put.mask, _put_a_mask_T connect put.data, a_data connect put.corrupt, UInt<1>(0h0) wire _atomics_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect _atomics_WIRE.corrupt, UInt<1>(0h0) connect _atomics_WIRE.data, UInt<128>(0h0) connect _atomics_WIRE.mask, UInt<16>(0h0) connect _atomics_WIRE.address, UInt<32>(0h0) connect _atomics_WIRE.source, UInt<3>(0h0) connect _atomics_WIRE.size, UInt<4>(0h0) connect _atomics_WIRE.param, UInt<3>(0h0) connect _atomics_WIRE.opcode, UInt<3>(0h0) node _atomics_legal_T = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_1 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_2 = and(_atomics_legal_T, _atomics_legal_T_1) node _atomics_legal_T_3 = or(UInt<1>(0h0), _atomics_legal_T_2) node _atomics_legal_T_4 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_5 = cvt(_atomics_legal_T_4) node _atomics_legal_T_6 = and(_atomics_legal_T_5, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_7 = asSInt(_atomics_legal_T_6) node _atomics_legal_T_8 = eq(_atomics_legal_T_7, asSInt(UInt<1>(0h0))) node _atomics_legal_T_9 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_10 = cvt(_atomics_legal_T_9) node _atomics_legal_T_11 = and(_atomics_legal_T_10, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_12 = asSInt(_atomics_legal_T_11) node _atomics_legal_T_13 = eq(_atomics_legal_T_12, asSInt(UInt<1>(0h0))) node _atomics_legal_T_14 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_15 = cvt(_atomics_legal_T_14) node _atomics_legal_T_16 = and(_atomics_legal_T_15, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_17 = asSInt(_atomics_legal_T_16) node _atomics_legal_T_18 = eq(_atomics_legal_T_17, asSInt(UInt<1>(0h0))) node _atomics_legal_T_19 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_20 = cvt(_atomics_legal_T_19) node _atomics_legal_T_21 = and(_atomics_legal_T_20, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_22 = asSInt(_atomics_legal_T_21) node _atomics_legal_T_23 = eq(_atomics_legal_T_22, asSInt(UInt<1>(0h0))) node _atomics_legal_T_24 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_25 = cvt(_atomics_legal_T_24) node _atomics_legal_T_26 = and(_atomics_legal_T_25, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_27 = asSInt(_atomics_legal_T_26) node _atomics_legal_T_28 = eq(_atomics_legal_T_27, asSInt(UInt<1>(0h0))) node _atomics_legal_T_29 = or(_atomics_legal_T_8, _atomics_legal_T_13) node _atomics_legal_T_30 = or(_atomics_legal_T_29, _atomics_legal_T_18) node _atomics_legal_T_31 = or(_atomics_legal_T_30, _atomics_legal_T_23) node _atomics_legal_T_32 = or(_atomics_legal_T_31, _atomics_legal_T_28) node _atomics_legal_T_33 = and(_atomics_legal_T_3, _atomics_legal_T_32) node _atomics_legal_T_34 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_35 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_36 = cvt(_atomics_legal_T_35) node _atomics_legal_T_37 = and(_atomics_legal_T_36, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_38 = asSInt(_atomics_legal_T_37) node _atomics_legal_T_39 = eq(_atomics_legal_T_38, asSInt(UInt<1>(0h0))) node _atomics_legal_T_40 = and(_atomics_legal_T_34, _atomics_legal_T_39) node _atomics_legal_T_41 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_42 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_43 = and(_atomics_legal_T_41, _atomics_legal_T_42) node _atomics_legal_T_44 = or(UInt<1>(0h0), _atomics_legal_T_43) node _atomics_legal_T_45 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_46 = cvt(_atomics_legal_T_45) node _atomics_legal_T_47 = and(_atomics_legal_T_46, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_48 = asSInt(_atomics_legal_T_47) node _atomics_legal_T_49 = eq(_atomics_legal_T_48, asSInt(UInt<1>(0h0))) node _atomics_legal_T_50 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_51 = cvt(_atomics_legal_T_50) node _atomics_legal_T_52 = and(_atomics_legal_T_51, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_53 = asSInt(_atomics_legal_T_52) node _atomics_legal_T_54 = eq(_atomics_legal_T_53, asSInt(UInt<1>(0h0))) node _atomics_legal_T_55 = or(_atomics_legal_T_49, _atomics_legal_T_54) node _atomics_legal_T_56 = and(_atomics_legal_T_44, _atomics_legal_T_55) node _atomics_legal_T_57 = or(UInt<1>(0h0), _atomics_legal_T_33) node _atomics_legal_T_58 = or(_atomics_legal_T_57, _atomics_legal_T_40) node atomics_legal = or(_atomics_legal_T_58, _atomics_legal_T_56) wire atomics_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a.opcode, UInt<2>(0h3) connect atomics_a.param, UInt<3>(0h3) connect atomics_a.size, req.uop.mem_size connect atomics_a.source, UInt<3>(0h5) connect atomics_a.address, req.addr node _atomics_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount = bits(_atomics_a_mask_sizeOH_T, 1, 0) node _atomics_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount) node _atomics_a_mask_sizeOH_T_2 = bits(_atomics_a_mask_sizeOH_T_1, 3, 0) node atomics_a_mask_sizeOH = or(_atomics_a_mask_sizeOH_T_2, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size = bits(atomics_a_mask_sizeOH, 3, 3) node atomics_a_mask_sub_sub_sub_bit = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit = eq(atomics_a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit) node _atomics_a_mask_sub_sub_sub_acc_T = and(atomics_a_mask_sub_sub_sub_size, atomics_a_mask_sub_sub_sub_0_2) node atomics_a_mask_sub_sub_sub_0_1 = or(atomics_a_mask_sub_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_sub_acc_T) node atomics_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit) node _atomics_a_mask_sub_sub_sub_acc_T_1 = and(atomics_a_mask_sub_sub_sub_size, atomics_a_mask_sub_sub_sub_1_2) node atomics_a_mask_sub_sub_sub_1_1 = or(atomics_a_mask_sub_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_sub_acc_T_1) node atomics_a_mask_sub_sub_size = bits(atomics_a_mask_sizeOH, 2, 2) node atomics_a_mask_sub_sub_bit = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit = eq(atomics_a_mask_sub_sub_bit, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2 = and(atomics_a_mask_sub_sub_sub_0_2, atomics_a_mask_sub_sub_nbit) node _atomics_a_mask_sub_sub_acc_T = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_0_2) node atomics_a_mask_sub_sub_0_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T) node atomics_a_mask_sub_sub_1_2 = and(atomics_a_mask_sub_sub_sub_0_2, atomics_a_mask_sub_sub_bit) node _atomics_a_mask_sub_sub_acc_T_1 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_1_2) node atomics_a_mask_sub_sub_1_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T_1) node atomics_a_mask_sub_sub_2_2 = and(atomics_a_mask_sub_sub_sub_1_2, atomics_a_mask_sub_sub_nbit) node _atomics_a_mask_sub_sub_acc_T_2 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_2_2) node atomics_a_mask_sub_sub_2_1 = or(atomics_a_mask_sub_sub_sub_1_1, _atomics_a_mask_sub_sub_acc_T_2) node atomics_a_mask_sub_sub_3_2 = and(atomics_a_mask_sub_sub_sub_1_2, atomics_a_mask_sub_sub_bit) node _atomics_a_mask_sub_sub_acc_T_3 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_3_2) node atomics_a_mask_sub_sub_3_1 = or(atomics_a_mask_sub_sub_sub_1_1, _atomics_a_mask_sub_sub_acc_T_3) node atomics_a_mask_sub_size = bits(atomics_a_mask_sizeOH, 1, 1) node atomics_a_mask_sub_bit = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit = eq(atomics_a_mask_sub_bit, UInt<1>(0h0)) node atomics_a_mask_sub_0_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_nbit) node _atomics_a_mask_sub_acc_T = and(atomics_a_mask_sub_size, atomics_a_mask_sub_0_2) node atomics_a_mask_sub_0_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T) node atomics_a_mask_sub_1_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_bit) node _atomics_a_mask_sub_acc_T_1 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_1_2) node atomics_a_mask_sub_1_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T_1) node atomics_a_mask_sub_2_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_nbit) node _atomics_a_mask_sub_acc_T_2 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_2_2) node atomics_a_mask_sub_2_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_2) node atomics_a_mask_sub_3_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_bit) node _atomics_a_mask_sub_acc_T_3 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_3_2) node atomics_a_mask_sub_3_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_3) node atomics_a_mask_sub_4_2 = and(atomics_a_mask_sub_sub_2_2, atomics_a_mask_sub_nbit) node _atomics_a_mask_sub_acc_T_4 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_4_2) node atomics_a_mask_sub_4_1 = or(atomics_a_mask_sub_sub_2_1, _atomics_a_mask_sub_acc_T_4) node atomics_a_mask_sub_5_2 = and(atomics_a_mask_sub_sub_2_2, atomics_a_mask_sub_bit) node _atomics_a_mask_sub_acc_T_5 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_5_2) node atomics_a_mask_sub_5_1 = or(atomics_a_mask_sub_sub_2_1, _atomics_a_mask_sub_acc_T_5) node atomics_a_mask_sub_6_2 = and(atomics_a_mask_sub_sub_3_2, atomics_a_mask_sub_nbit) node _atomics_a_mask_sub_acc_T_6 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_6_2) node atomics_a_mask_sub_6_1 = or(atomics_a_mask_sub_sub_3_1, _atomics_a_mask_sub_acc_T_6) node atomics_a_mask_sub_7_2 = and(atomics_a_mask_sub_sub_3_2, atomics_a_mask_sub_bit) node _atomics_a_mask_sub_acc_T_7 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_7_2) node atomics_a_mask_sub_7_1 = or(atomics_a_mask_sub_sub_3_1, _atomics_a_mask_sub_acc_T_7) node atomics_a_mask_size = bits(atomics_a_mask_sizeOH, 0, 0) node atomics_a_mask_bit = bits(req.addr, 0, 0) node atomics_a_mask_nbit = eq(atomics_a_mask_bit, UInt<1>(0h0)) node atomics_a_mask_eq = and(atomics_a_mask_sub_0_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T = and(atomics_a_mask_size, atomics_a_mask_eq) node atomics_a_mask_acc = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T) node atomics_a_mask_eq_1 = and(atomics_a_mask_sub_0_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_1 = and(atomics_a_mask_size, atomics_a_mask_eq_1) node atomics_a_mask_acc_1 = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T_1) node atomics_a_mask_eq_2 = and(atomics_a_mask_sub_1_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_2 = and(atomics_a_mask_size, atomics_a_mask_eq_2) node atomics_a_mask_acc_2 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_2) node atomics_a_mask_eq_3 = and(atomics_a_mask_sub_1_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_3 = and(atomics_a_mask_size, atomics_a_mask_eq_3) node atomics_a_mask_acc_3 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_3) node atomics_a_mask_eq_4 = and(atomics_a_mask_sub_2_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_4 = and(atomics_a_mask_size, atomics_a_mask_eq_4) node atomics_a_mask_acc_4 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_4) node atomics_a_mask_eq_5 = and(atomics_a_mask_sub_2_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_5 = and(atomics_a_mask_size, atomics_a_mask_eq_5) node atomics_a_mask_acc_5 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_5) node atomics_a_mask_eq_6 = and(atomics_a_mask_sub_3_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_6 = and(atomics_a_mask_size, atomics_a_mask_eq_6) node atomics_a_mask_acc_6 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_6) node atomics_a_mask_eq_7 = and(atomics_a_mask_sub_3_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_7 = and(atomics_a_mask_size, atomics_a_mask_eq_7) node atomics_a_mask_acc_7 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_7) node atomics_a_mask_eq_8 = and(atomics_a_mask_sub_4_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_8 = and(atomics_a_mask_size, atomics_a_mask_eq_8) node atomics_a_mask_acc_8 = or(atomics_a_mask_sub_4_1, _atomics_a_mask_acc_T_8) node atomics_a_mask_eq_9 = and(atomics_a_mask_sub_4_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_9 = and(atomics_a_mask_size, atomics_a_mask_eq_9) node atomics_a_mask_acc_9 = or(atomics_a_mask_sub_4_1, _atomics_a_mask_acc_T_9) node atomics_a_mask_eq_10 = and(atomics_a_mask_sub_5_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_10 = and(atomics_a_mask_size, atomics_a_mask_eq_10) node atomics_a_mask_acc_10 = or(atomics_a_mask_sub_5_1, _atomics_a_mask_acc_T_10) node atomics_a_mask_eq_11 = and(atomics_a_mask_sub_5_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_11 = and(atomics_a_mask_size, atomics_a_mask_eq_11) node atomics_a_mask_acc_11 = or(atomics_a_mask_sub_5_1, _atomics_a_mask_acc_T_11) node atomics_a_mask_eq_12 = and(atomics_a_mask_sub_6_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_12 = and(atomics_a_mask_size, atomics_a_mask_eq_12) node atomics_a_mask_acc_12 = or(atomics_a_mask_sub_6_1, _atomics_a_mask_acc_T_12) node atomics_a_mask_eq_13 = and(atomics_a_mask_sub_6_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_13 = and(atomics_a_mask_size, atomics_a_mask_eq_13) node atomics_a_mask_acc_13 = or(atomics_a_mask_sub_6_1, _atomics_a_mask_acc_T_13) node atomics_a_mask_eq_14 = and(atomics_a_mask_sub_7_2, atomics_a_mask_nbit) node _atomics_a_mask_acc_T_14 = and(atomics_a_mask_size, atomics_a_mask_eq_14) node atomics_a_mask_acc_14 = or(atomics_a_mask_sub_7_1, _atomics_a_mask_acc_T_14) node atomics_a_mask_eq_15 = and(atomics_a_mask_sub_7_2, atomics_a_mask_bit) node _atomics_a_mask_acc_T_15 = and(atomics_a_mask_size, atomics_a_mask_eq_15) node atomics_a_mask_acc_15 = or(atomics_a_mask_sub_7_1, _atomics_a_mask_acc_T_15) node atomics_a_mask_lo_lo_lo = cat(atomics_a_mask_acc_1, atomics_a_mask_acc) node atomics_a_mask_lo_lo_hi = cat(atomics_a_mask_acc_3, atomics_a_mask_acc_2) node atomics_a_mask_lo_lo = cat(atomics_a_mask_lo_lo_hi, atomics_a_mask_lo_lo_lo) node atomics_a_mask_lo_hi_lo = cat(atomics_a_mask_acc_5, atomics_a_mask_acc_4) node atomics_a_mask_lo_hi_hi = cat(atomics_a_mask_acc_7, atomics_a_mask_acc_6) node atomics_a_mask_lo_hi = cat(atomics_a_mask_lo_hi_hi, atomics_a_mask_lo_hi_lo) node atomics_a_mask_lo = cat(atomics_a_mask_lo_hi, atomics_a_mask_lo_lo) node atomics_a_mask_hi_lo_lo = cat(atomics_a_mask_acc_9, atomics_a_mask_acc_8) node atomics_a_mask_hi_lo_hi = cat(atomics_a_mask_acc_11, atomics_a_mask_acc_10) node atomics_a_mask_hi_lo = cat(atomics_a_mask_hi_lo_hi, atomics_a_mask_hi_lo_lo) node atomics_a_mask_hi_hi_lo = cat(atomics_a_mask_acc_13, atomics_a_mask_acc_12) node atomics_a_mask_hi_hi_hi = cat(atomics_a_mask_acc_15, atomics_a_mask_acc_14) node atomics_a_mask_hi_hi = cat(atomics_a_mask_hi_hi_hi, atomics_a_mask_hi_hi_lo) node atomics_a_mask_hi = cat(atomics_a_mask_hi_hi, atomics_a_mask_hi_lo) node _atomics_a_mask_T = cat(atomics_a_mask_hi, atomics_a_mask_lo) connect atomics_a.mask, _atomics_a_mask_T connect atomics_a.data, a_data connect atomics_a.corrupt, UInt<1>(0h0) node _atomics_legal_T_59 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_60 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_61 = and(_atomics_legal_T_59, _atomics_legal_T_60) node _atomics_legal_T_62 = or(UInt<1>(0h0), _atomics_legal_T_61) node _atomics_legal_T_63 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_64 = cvt(_atomics_legal_T_63) node _atomics_legal_T_65 = and(_atomics_legal_T_64, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_66 = asSInt(_atomics_legal_T_65) node _atomics_legal_T_67 = eq(_atomics_legal_T_66, asSInt(UInt<1>(0h0))) node _atomics_legal_T_68 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_69 = cvt(_atomics_legal_T_68) node _atomics_legal_T_70 = and(_atomics_legal_T_69, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_71 = asSInt(_atomics_legal_T_70) node _atomics_legal_T_72 = eq(_atomics_legal_T_71, asSInt(UInt<1>(0h0))) node _atomics_legal_T_73 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_74 = cvt(_atomics_legal_T_73) node _atomics_legal_T_75 = and(_atomics_legal_T_74, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_76 = asSInt(_atomics_legal_T_75) node _atomics_legal_T_77 = eq(_atomics_legal_T_76, asSInt(UInt<1>(0h0))) node _atomics_legal_T_78 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_79 = cvt(_atomics_legal_T_78) node _atomics_legal_T_80 = and(_atomics_legal_T_79, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_81 = asSInt(_atomics_legal_T_80) node _atomics_legal_T_82 = eq(_atomics_legal_T_81, asSInt(UInt<1>(0h0))) node _atomics_legal_T_83 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_84 = cvt(_atomics_legal_T_83) node _atomics_legal_T_85 = and(_atomics_legal_T_84, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_86 = asSInt(_atomics_legal_T_85) node _atomics_legal_T_87 = eq(_atomics_legal_T_86, asSInt(UInt<1>(0h0))) node _atomics_legal_T_88 = or(_atomics_legal_T_67, _atomics_legal_T_72) node _atomics_legal_T_89 = or(_atomics_legal_T_88, _atomics_legal_T_77) node _atomics_legal_T_90 = or(_atomics_legal_T_89, _atomics_legal_T_82) node _atomics_legal_T_91 = or(_atomics_legal_T_90, _atomics_legal_T_87) node _atomics_legal_T_92 = and(_atomics_legal_T_62, _atomics_legal_T_91) node _atomics_legal_T_93 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_94 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_95 = cvt(_atomics_legal_T_94) node _atomics_legal_T_96 = and(_atomics_legal_T_95, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_97 = asSInt(_atomics_legal_T_96) node _atomics_legal_T_98 = eq(_atomics_legal_T_97, asSInt(UInt<1>(0h0))) node _atomics_legal_T_99 = and(_atomics_legal_T_93, _atomics_legal_T_98) node _atomics_legal_T_100 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_101 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_102 = and(_atomics_legal_T_100, _atomics_legal_T_101) node _atomics_legal_T_103 = or(UInt<1>(0h0), _atomics_legal_T_102) node _atomics_legal_T_104 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_105 = cvt(_atomics_legal_T_104) node _atomics_legal_T_106 = and(_atomics_legal_T_105, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_107 = asSInt(_atomics_legal_T_106) node _atomics_legal_T_108 = eq(_atomics_legal_T_107, asSInt(UInt<1>(0h0))) node _atomics_legal_T_109 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_110 = cvt(_atomics_legal_T_109) node _atomics_legal_T_111 = and(_atomics_legal_T_110, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_112 = asSInt(_atomics_legal_T_111) node _atomics_legal_T_113 = eq(_atomics_legal_T_112, asSInt(UInt<1>(0h0))) node _atomics_legal_T_114 = or(_atomics_legal_T_108, _atomics_legal_T_113) node _atomics_legal_T_115 = and(_atomics_legal_T_103, _atomics_legal_T_114) node _atomics_legal_T_116 = or(UInt<1>(0h0), _atomics_legal_T_92) node _atomics_legal_T_117 = or(_atomics_legal_T_116, _atomics_legal_T_99) node atomics_legal_1 = or(_atomics_legal_T_117, _atomics_legal_T_115) wire atomics_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_1.opcode, UInt<2>(0h3) connect atomics_a_1.param, UInt<3>(0h0) connect atomics_a_1.size, req.uop.mem_size connect atomics_a_1.source, UInt<3>(0h5) connect atomics_a_1.address, req.addr node _atomics_a_mask_sizeOH_T_3 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_1 = bits(_atomics_a_mask_sizeOH_T_3, 1, 0) node _atomics_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_1) node _atomics_a_mask_sizeOH_T_5 = bits(_atomics_a_mask_sizeOH_T_4, 3, 0) node atomics_a_mask_sizeOH_1 = or(_atomics_a_mask_sizeOH_T_5, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_1 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 3, 3) node atomics_a_mask_sub_sub_sub_bit_1 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_1 = eq(atomics_a_mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_1) node _atomics_a_mask_sub_sub_sub_acc_T_2 = and(atomics_a_mask_sub_sub_sub_size_1, atomics_a_mask_sub_sub_sub_0_2_1) node atomics_a_mask_sub_sub_sub_0_1_1 = or(atomics_a_mask_sub_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_sub_acc_T_2) node atomics_a_mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_1) node _atomics_a_mask_sub_sub_sub_acc_T_3 = and(atomics_a_mask_sub_sub_sub_size_1, atomics_a_mask_sub_sub_sub_1_2_1) node atomics_a_mask_sub_sub_sub_1_1_1 = or(atomics_a_mask_sub_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_sub_acc_T_3) node atomics_a_mask_sub_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 2, 2) node atomics_a_mask_sub_sub_bit_1 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_1 = eq(atomics_a_mask_sub_sub_bit_1, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_1 = and(atomics_a_mask_sub_sub_sub_0_2_1, atomics_a_mask_sub_sub_nbit_1) node _atomics_a_mask_sub_sub_acc_T_4 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_0_2_1) node atomics_a_mask_sub_sub_0_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_4) node atomics_a_mask_sub_sub_1_2_1 = and(atomics_a_mask_sub_sub_sub_0_2_1, atomics_a_mask_sub_sub_bit_1) node _atomics_a_mask_sub_sub_acc_T_5 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_1_2_1) node atomics_a_mask_sub_sub_1_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_5) node atomics_a_mask_sub_sub_2_2_1 = and(atomics_a_mask_sub_sub_sub_1_2_1, atomics_a_mask_sub_sub_nbit_1) node _atomics_a_mask_sub_sub_acc_T_6 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_2_2_1) node atomics_a_mask_sub_sub_2_1_1 = or(atomics_a_mask_sub_sub_sub_1_1_1, _atomics_a_mask_sub_sub_acc_T_6) node atomics_a_mask_sub_sub_3_2_1 = and(atomics_a_mask_sub_sub_sub_1_2_1, atomics_a_mask_sub_sub_bit_1) node _atomics_a_mask_sub_sub_acc_T_7 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_3_2_1) node atomics_a_mask_sub_sub_3_1_1 = or(atomics_a_mask_sub_sub_sub_1_1_1, _atomics_a_mask_sub_sub_acc_T_7) node atomics_a_mask_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 1, 1) node atomics_a_mask_sub_bit_1 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_1 = eq(atomics_a_mask_sub_bit_1, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_nbit_1) node _atomics_a_mask_sub_acc_T_8 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_0_2_1) node atomics_a_mask_sub_0_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_8) node atomics_a_mask_sub_1_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_bit_1) node _atomics_a_mask_sub_acc_T_9 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_1_2_1) node atomics_a_mask_sub_1_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_9) node atomics_a_mask_sub_2_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_nbit_1) node _atomics_a_mask_sub_acc_T_10 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_2_2_1) node atomics_a_mask_sub_2_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_10) node atomics_a_mask_sub_3_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_bit_1) node _atomics_a_mask_sub_acc_T_11 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_3_2_1) node atomics_a_mask_sub_3_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_11) node atomics_a_mask_sub_4_2_1 = and(atomics_a_mask_sub_sub_2_2_1, atomics_a_mask_sub_nbit_1) node _atomics_a_mask_sub_acc_T_12 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_4_2_1) node atomics_a_mask_sub_4_1_1 = or(atomics_a_mask_sub_sub_2_1_1, _atomics_a_mask_sub_acc_T_12) node atomics_a_mask_sub_5_2_1 = and(atomics_a_mask_sub_sub_2_2_1, atomics_a_mask_sub_bit_1) node _atomics_a_mask_sub_acc_T_13 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_5_2_1) node atomics_a_mask_sub_5_1_1 = or(atomics_a_mask_sub_sub_2_1_1, _atomics_a_mask_sub_acc_T_13) node atomics_a_mask_sub_6_2_1 = and(atomics_a_mask_sub_sub_3_2_1, atomics_a_mask_sub_nbit_1) node _atomics_a_mask_sub_acc_T_14 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_6_2_1) node atomics_a_mask_sub_6_1_1 = or(atomics_a_mask_sub_sub_3_1_1, _atomics_a_mask_sub_acc_T_14) node atomics_a_mask_sub_7_2_1 = and(atomics_a_mask_sub_sub_3_2_1, atomics_a_mask_sub_bit_1) node _atomics_a_mask_sub_acc_T_15 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_7_2_1) node atomics_a_mask_sub_7_1_1 = or(atomics_a_mask_sub_sub_3_1_1, _atomics_a_mask_sub_acc_T_15) node atomics_a_mask_size_1 = bits(atomics_a_mask_sizeOH_1, 0, 0) node atomics_a_mask_bit_1 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_1 = eq(atomics_a_mask_bit_1, UInt<1>(0h0)) node atomics_a_mask_eq_16 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_16 = and(atomics_a_mask_size_1, atomics_a_mask_eq_16) node atomics_a_mask_acc_16 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_16) node atomics_a_mask_eq_17 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_17 = and(atomics_a_mask_size_1, atomics_a_mask_eq_17) node atomics_a_mask_acc_17 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_17) node atomics_a_mask_eq_18 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_18 = and(atomics_a_mask_size_1, atomics_a_mask_eq_18) node atomics_a_mask_acc_18 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_18) node atomics_a_mask_eq_19 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_19 = and(atomics_a_mask_size_1, atomics_a_mask_eq_19) node atomics_a_mask_acc_19 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_19) node atomics_a_mask_eq_20 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_20 = and(atomics_a_mask_size_1, atomics_a_mask_eq_20) node atomics_a_mask_acc_20 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_20) node atomics_a_mask_eq_21 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_21 = and(atomics_a_mask_size_1, atomics_a_mask_eq_21) node atomics_a_mask_acc_21 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_21) node atomics_a_mask_eq_22 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_22 = and(atomics_a_mask_size_1, atomics_a_mask_eq_22) node atomics_a_mask_acc_22 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_22) node atomics_a_mask_eq_23 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_23 = and(atomics_a_mask_size_1, atomics_a_mask_eq_23) node atomics_a_mask_acc_23 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_23) node atomics_a_mask_eq_24 = and(atomics_a_mask_sub_4_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_24 = and(atomics_a_mask_size_1, atomics_a_mask_eq_24) node atomics_a_mask_acc_24 = or(atomics_a_mask_sub_4_1_1, _atomics_a_mask_acc_T_24) node atomics_a_mask_eq_25 = and(atomics_a_mask_sub_4_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_25 = and(atomics_a_mask_size_1, atomics_a_mask_eq_25) node atomics_a_mask_acc_25 = or(atomics_a_mask_sub_4_1_1, _atomics_a_mask_acc_T_25) node atomics_a_mask_eq_26 = and(atomics_a_mask_sub_5_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_26 = and(atomics_a_mask_size_1, atomics_a_mask_eq_26) node atomics_a_mask_acc_26 = or(atomics_a_mask_sub_5_1_1, _atomics_a_mask_acc_T_26) node atomics_a_mask_eq_27 = and(atomics_a_mask_sub_5_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_27 = and(atomics_a_mask_size_1, atomics_a_mask_eq_27) node atomics_a_mask_acc_27 = or(atomics_a_mask_sub_5_1_1, _atomics_a_mask_acc_T_27) node atomics_a_mask_eq_28 = and(atomics_a_mask_sub_6_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_28 = and(atomics_a_mask_size_1, atomics_a_mask_eq_28) node atomics_a_mask_acc_28 = or(atomics_a_mask_sub_6_1_1, _atomics_a_mask_acc_T_28) node atomics_a_mask_eq_29 = and(atomics_a_mask_sub_6_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_29 = and(atomics_a_mask_size_1, atomics_a_mask_eq_29) node atomics_a_mask_acc_29 = or(atomics_a_mask_sub_6_1_1, _atomics_a_mask_acc_T_29) node atomics_a_mask_eq_30 = and(atomics_a_mask_sub_7_2_1, atomics_a_mask_nbit_1) node _atomics_a_mask_acc_T_30 = and(atomics_a_mask_size_1, atomics_a_mask_eq_30) node atomics_a_mask_acc_30 = or(atomics_a_mask_sub_7_1_1, _atomics_a_mask_acc_T_30) node atomics_a_mask_eq_31 = and(atomics_a_mask_sub_7_2_1, atomics_a_mask_bit_1) node _atomics_a_mask_acc_T_31 = and(atomics_a_mask_size_1, atomics_a_mask_eq_31) node atomics_a_mask_acc_31 = or(atomics_a_mask_sub_7_1_1, _atomics_a_mask_acc_T_31) node atomics_a_mask_lo_lo_lo_1 = cat(atomics_a_mask_acc_17, atomics_a_mask_acc_16) node atomics_a_mask_lo_lo_hi_1 = cat(atomics_a_mask_acc_19, atomics_a_mask_acc_18) node atomics_a_mask_lo_lo_1 = cat(atomics_a_mask_lo_lo_hi_1, atomics_a_mask_lo_lo_lo_1) node atomics_a_mask_lo_hi_lo_1 = cat(atomics_a_mask_acc_21, atomics_a_mask_acc_20) node atomics_a_mask_lo_hi_hi_1 = cat(atomics_a_mask_acc_23, atomics_a_mask_acc_22) node atomics_a_mask_lo_hi_1 = cat(atomics_a_mask_lo_hi_hi_1, atomics_a_mask_lo_hi_lo_1) node atomics_a_mask_lo_1 = cat(atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1) node atomics_a_mask_hi_lo_lo_1 = cat(atomics_a_mask_acc_25, atomics_a_mask_acc_24) node atomics_a_mask_hi_lo_hi_1 = cat(atomics_a_mask_acc_27, atomics_a_mask_acc_26) node atomics_a_mask_hi_lo_1 = cat(atomics_a_mask_hi_lo_hi_1, atomics_a_mask_hi_lo_lo_1) node atomics_a_mask_hi_hi_lo_1 = cat(atomics_a_mask_acc_29, atomics_a_mask_acc_28) node atomics_a_mask_hi_hi_hi_1 = cat(atomics_a_mask_acc_31, atomics_a_mask_acc_30) node atomics_a_mask_hi_hi_1 = cat(atomics_a_mask_hi_hi_hi_1, atomics_a_mask_hi_hi_lo_1) node atomics_a_mask_hi_1 = cat(atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1) node _atomics_a_mask_T_1 = cat(atomics_a_mask_hi_1, atomics_a_mask_lo_1) connect atomics_a_1.mask, _atomics_a_mask_T_1 connect atomics_a_1.data, a_data connect atomics_a_1.corrupt, UInt<1>(0h0) node _atomics_legal_T_118 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_119 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_120 = and(_atomics_legal_T_118, _atomics_legal_T_119) node _atomics_legal_T_121 = or(UInt<1>(0h0), _atomics_legal_T_120) node _atomics_legal_T_122 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_123 = cvt(_atomics_legal_T_122) node _atomics_legal_T_124 = and(_atomics_legal_T_123, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_125 = asSInt(_atomics_legal_T_124) node _atomics_legal_T_126 = eq(_atomics_legal_T_125, asSInt(UInt<1>(0h0))) node _atomics_legal_T_127 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_128 = cvt(_atomics_legal_T_127) node _atomics_legal_T_129 = and(_atomics_legal_T_128, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_130 = asSInt(_atomics_legal_T_129) node _atomics_legal_T_131 = eq(_atomics_legal_T_130, asSInt(UInt<1>(0h0))) node _atomics_legal_T_132 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_133 = cvt(_atomics_legal_T_132) node _atomics_legal_T_134 = and(_atomics_legal_T_133, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_135 = asSInt(_atomics_legal_T_134) node _atomics_legal_T_136 = eq(_atomics_legal_T_135, asSInt(UInt<1>(0h0))) node _atomics_legal_T_137 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_138 = cvt(_atomics_legal_T_137) node _atomics_legal_T_139 = and(_atomics_legal_T_138, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_140 = asSInt(_atomics_legal_T_139) node _atomics_legal_T_141 = eq(_atomics_legal_T_140, asSInt(UInt<1>(0h0))) node _atomics_legal_T_142 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_143 = cvt(_atomics_legal_T_142) node _atomics_legal_T_144 = and(_atomics_legal_T_143, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_145 = asSInt(_atomics_legal_T_144) node _atomics_legal_T_146 = eq(_atomics_legal_T_145, asSInt(UInt<1>(0h0))) node _atomics_legal_T_147 = or(_atomics_legal_T_126, _atomics_legal_T_131) node _atomics_legal_T_148 = or(_atomics_legal_T_147, _atomics_legal_T_136) node _atomics_legal_T_149 = or(_atomics_legal_T_148, _atomics_legal_T_141) node _atomics_legal_T_150 = or(_atomics_legal_T_149, _atomics_legal_T_146) node _atomics_legal_T_151 = and(_atomics_legal_T_121, _atomics_legal_T_150) node _atomics_legal_T_152 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_153 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_154 = cvt(_atomics_legal_T_153) node _atomics_legal_T_155 = and(_atomics_legal_T_154, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_156 = asSInt(_atomics_legal_T_155) node _atomics_legal_T_157 = eq(_atomics_legal_T_156, asSInt(UInt<1>(0h0))) node _atomics_legal_T_158 = and(_atomics_legal_T_152, _atomics_legal_T_157) node _atomics_legal_T_159 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_160 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_161 = and(_atomics_legal_T_159, _atomics_legal_T_160) node _atomics_legal_T_162 = or(UInt<1>(0h0), _atomics_legal_T_161) node _atomics_legal_T_163 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_164 = cvt(_atomics_legal_T_163) node _atomics_legal_T_165 = and(_atomics_legal_T_164, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_166 = asSInt(_atomics_legal_T_165) node _atomics_legal_T_167 = eq(_atomics_legal_T_166, asSInt(UInt<1>(0h0))) node _atomics_legal_T_168 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_169 = cvt(_atomics_legal_T_168) node _atomics_legal_T_170 = and(_atomics_legal_T_169, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_171 = asSInt(_atomics_legal_T_170) node _atomics_legal_T_172 = eq(_atomics_legal_T_171, asSInt(UInt<1>(0h0))) node _atomics_legal_T_173 = or(_atomics_legal_T_167, _atomics_legal_T_172) node _atomics_legal_T_174 = and(_atomics_legal_T_162, _atomics_legal_T_173) node _atomics_legal_T_175 = or(UInt<1>(0h0), _atomics_legal_T_151) node _atomics_legal_T_176 = or(_atomics_legal_T_175, _atomics_legal_T_158) node atomics_legal_2 = or(_atomics_legal_T_176, _atomics_legal_T_174) wire atomics_a_2 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_2.opcode, UInt<2>(0h3) connect atomics_a_2.param, UInt<3>(0h1) connect atomics_a_2.size, req.uop.mem_size connect atomics_a_2.source, UInt<3>(0h5) connect atomics_a_2.address, req.addr node _atomics_a_mask_sizeOH_T_6 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_2 = bits(_atomics_a_mask_sizeOH_T_6, 1, 0) node _atomics_a_mask_sizeOH_T_7 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_2) node _atomics_a_mask_sizeOH_T_8 = bits(_atomics_a_mask_sizeOH_T_7, 3, 0) node atomics_a_mask_sizeOH_2 = or(_atomics_a_mask_sizeOH_T_8, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_2 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 3, 3) node atomics_a_mask_sub_sub_sub_bit_2 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_2 = eq(atomics_a_mask_sub_sub_sub_bit_2, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_2) node _atomics_a_mask_sub_sub_sub_acc_T_4 = and(atomics_a_mask_sub_sub_sub_size_2, atomics_a_mask_sub_sub_sub_0_2_2) node atomics_a_mask_sub_sub_sub_0_1_2 = or(atomics_a_mask_sub_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_sub_acc_T_4) node atomics_a_mask_sub_sub_sub_1_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_2) node _atomics_a_mask_sub_sub_sub_acc_T_5 = and(atomics_a_mask_sub_sub_sub_size_2, atomics_a_mask_sub_sub_sub_1_2_2) node atomics_a_mask_sub_sub_sub_1_1_2 = or(atomics_a_mask_sub_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_sub_acc_T_5) node atomics_a_mask_sub_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 2, 2) node atomics_a_mask_sub_sub_bit_2 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_2 = eq(atomics_a_mask_sub_sub_bit_2, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_2 = and(atomics_a_mask_sub_sub_sub_0_2_2, atomics_a_mask_sub_sub_nbit_2) node _atomics_a_mask_sub_sub_acc_T_8 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_0_2_2) node atomics_a_mask_sub_sub_0_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_8) node atomics_a_mask_sub_sub_1_2_2 = and(atomics_a_mask_sub_sub_sub_0_2_2, atomics_a_mask_sub_sub_bit_2) node _atomics_a_mask_sub_sub_acc_T_9 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_1_2_2) node atomics_a_mask_sub_sub_1_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_9) node atomics_a_mask_sub_sub_2_2_2 = and(atomics_a_mask_sub_sub_sub_1_2_2, atomics_a_mask_sub_sub_nbit_2) node _atomics_a_mask_sub_sub_acc_T_10 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_2_2_2) node atomics_a_mask_sub_sub_2_1_2 = or(atomics_a_mask_sub_sub_sub_1_1_2, _atomics_a_mask_sub_sub_acc_T_10) node atomics_a_mask_sub_sub_3_2_2 = and(atomics_a_mask_sub_sub_sub_1_2_2, atomics_a_mask_sub_sub_bit_2) node _atomics_a_mask_sub_sub_acc_T_11 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_3_2_2) node atomics_a_mask_sub_sub_3_1_2 = or(atomics_a_mask_sub_sub_sub_1_1_2, _atomics_a_mask_sub_sub_acc_T_11) node atomics_a_mask_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 1, 1) node atomics_a_mask_sub_bit_2 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_2 = eq(atomics_a_mask_sub_bit_2, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_nbit_2) node _atomics_a_mask_sub_acc_T_16 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_0_2_2) node atomics_a_mask_sub_0_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_16) node atomics_a_mask_sub_1_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_bit_2) node _atomics_a_mask_sub_acc_T_17 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_1_2_2) node atomics_a_mask_sub_1_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_17) node atomics_a_mask_sub_2_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_nbit_2) node _atomics_a_mask_sub_acc_T_18 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_2_2_2) node atomics_a_mask_sub_2_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_18) node atomics_a_mask_sub_3_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_bit_2) node _atomics_a_mask_sub_acc_T_19 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_3_2_2) node atomics_a_mask_sub_3_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_19) node atomics_a_mask_sub_4_2_2 = and(atomics_a_mask_sub_sub_2_2_2, atomics_a_mask_sub_nbit_2) node _atomics_a_mask_sub_acc_T_20 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_4_2_2) node atomics_a_mask_sub_4_1_2 = or(atomics_a_mask_sub_sub_2_1_2, _atomics_a_mask_sub_acc_T_20) node atomics_a_mask_sub_5_2_2 = and(atomics_a_mask_sub_sub_2_2_2, atomics_a_mask_sub_bit_2) node _atomics_a_mask_sub_acc_T_21 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_5_2_2) node atomics_a_mask_sub_5_1_2 = or(atomics_a_mask_sub_sub_2_1_2, _atomics_a_mask_sub_acc_T_21) node atomics_a_mask_sub_6_2_2 = and(atomics_a_mask_sub_sub_3_2_2, atomics_a_mask_sub_nbit_2) node _atomics_a_mask_sub_acc_T_22 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_6_2_2) node atomics_a_mask_sub_6_1_2 = or(atomics_a_mask_sub_sub_3_1_2, _atomics_a_mask_sub_acc_T_22) node atomics_a_mask_sub_7_2_2 = and(atomics_a_mask_sub_sub_3_2_2, atomics_a_mask_sub_bit_2) node _atomics_a_mask_sub_acc_T_23 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_7_2_2) node atomics_a_mask_sub_7_1_2 = or(atomics_a_mask_sub_sub_3_1_2, _atomics_a_mask_sub_acc_T_23) node atomics_a_mask_size_2 = bits(atomics_a_mask_sizeOH_2, 0, 0) node atomics_a_mask_bit_2 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_2 = eq(atomics_a_mask_bit_2, UInt<1>(0h0)) node atomics_a_mask_eq_32 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_32 = and(atomics_a_mask_size_2, atomics_a_mask_eq_32) node atomics_a_mask_acc_32 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_32) node atomics_a_mask_eq_33 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_33 = and(atomics_a_mask_size_2, atomics_a_mask_eq_33) node atomics_a_mask_acc_33 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_33) node atomics_a_mask_eq_34 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_34 = and(atomics_a_mask_size_2, atomics_a_mask_eq_34) node atomics_a_mask_acc_34 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_34) node atomics_a_mask_eq_35 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_35 = and(atomics_a_mask_size_2, atomics_a_mask_eq_35) node atomics_a_mask_acc_35 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_35) node atomics_a_mask_eq_36 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_36 = and(atomics_a_mask_size_2, atomics_a_mask_eq_36) node atomics_a_mask_acc_36 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_36) node atomics_a_mask_eq_37 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_37 = and(atomics_a_mask_size_2, atomics_a_mask_eq_37) node atomics_a_mask_acc_37 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_37) node atomics_a_mask_eq_38 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_38 = and(atomics_a_mask_size_2, atomics_a_mask_eq_38) node atomics_a_mask_acc_38 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_38) node atomics_a_mask_eq_39 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_39 = and(atomics_a_mask_size_2, atomics_a_mask_eq_39) node atomics_a_mask_acc_39 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_39) node atomics_a_mask_eq_40 = and(atomics_a_mask_sub_4_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_40 = and(atomics_a_mask_size_2, atomics_a_mask_eq_40) node atomics_a_mask_acc_40 = or(atomics_a_mask_sub_4_1_2, _atomics_a_mask_acc_T_40) node atomics_a_mask_eq_41 = and(atomics_a_mask_sub_4_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_41 = and(atomics_a_mask_size_2, atomics_a_mask_eq_41) node atomics_a_mask_acc_41 = or(atomics_a_mask_sub_4_1_2, _atomics_a_mask_acc_T_41) node atomics_a_mask_eq_42 = and(atomics_a_mask_sub_5_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_42 = and(atomics_a_mask_size_2, atomics_a_mask_eq_42) node atomics_a_mask_acc_42 = or(atomics_a_mask_sub_5_1_2, _atomics_a_mask_acc_T_42) node atomics_a_mask_eq_43 = and(atomics_a_mask_sub_5_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_43 = and(atomics_a_mask_size_2, atomics_a_mask_eq_43) node atomics_a_mask_acc_43 = or(atomics_a_mask_sub_5_1_2, _atomics_a_mask_acc_T_43) node atomics_a_mask_eq_44 = and(atomics_a_mask_sub_6_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_44 = and(atomics_a_mask_size_2, atomics_a_mask_eq_44) node atomics_a_mask_acc_44 = or(atomics_a_mask_sub_6_1_2, _atomics_a_mask_acc_T_44) node atomics_a_mask_eq_45 = and(atomics_a_mask_sub_6_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_45 = and(atomics_a_mask_size_2, atomics_a_mask_eq_45) node atomics_a_mask_acc_45 = or(atomics_a_mask_sub_6_1_2, _atomics_a_mask_acc_T_45) node atomics_a_mask_eq_46 = and(atomics_a_mask_sub_7_2_2, atomics_a_mask_nbit_2) node _atomics_a_mask_acc_T_46 = and(atomics_a_mask_size_2, atomics_a_mask_eq_46) node atomics_a_mask_acc_46 = or(atomics_a_mask_sub_7_1_2, _atomics_a_mask_acc_T_46) node atomics_a_mask_eq_47 = and(atomics_a_mask_sub_7_2_2, atomics_a_mask_bit_2) node _atomics_a_mask_acc_T_47 = and(atomics_a_mask_size_2, atomics_a_mask_eq_47) node atomics_a_mask_acc_47 = or(atomics_a_mask_sub_7_1_2, _atomics_a_mask_acc_T_47) node atomics_a_mask_lo_lo_lo_2 = cat(atomics_a_mask_acc_33, atomics_a_mask_acc_32) node atomics_a_mask_lo_lo_hi_2 = cat(atomics_a_mask_acc_35, atomics_a_mask_acc_34) node atomics_a_mask_lo_lo_2 = cat(atomics_a_mask_lo_lo_hi_2, atomics_a_mask_lo_lo_lo_2) node atomics_a_mask_lo_hi_lo_2 = cat(atomics_a_mask_acc_37, atomics_a_mask_acc_36) node atomics_a_mask_lo_hi_hi_2 = cat(atomics_a_mask_acc_39, atomics_a_mask_acc_38) node atomics_a_mask_lo_hi_2 = cat(atomics_a_mask_lo_hi_hi_2, atomics_a_mask_lo_hi_lo_2) node atomics_a_mask_lo_2 = cat(atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2) node atomics_a_mask_hi_lo_lo_2 = cat(atomics_a_mask_acc_41, atomics_a_mask_acc_40) node atomics_a_mask_hi_lo_hi_2 = cat(atomics_a_mask_acc_43, atomics_a_mask_acc_42) node atomics_a_mask_hi_lo_2 = cat(atomics_a_mask_hi_lo_hi_2, atomics_a_mask_hi_lo_lo_2) node atomics_a_mask_hi_hi_lo_2 = cat(atomics_a_mask_acc_45, atomics_a_mask_acc_44) node atomics_a_mask_hi_hi_hi_2 = cat(atomics_a_mask_acc_47, atomics_a_mask_acc_46) node atomics_a_mask_hi_hi_2 = cat(atomics_a_mask_hi_hi_hi_2, atomics_a_mask_hi_hi_lo_2) node atomics_a_mask_hi_2 = cat(atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2) node _atomics_a_mask_T_2 = cat(atomics_a_mask_hi_2, atomics_a_mask_lo_2) connect atomics_a_2.mask, _atomics_a_mask_T_2 connect atomics_a_2.data, a_data connect atomics_a_2.corrupt, UInt<1>(0h0) node _atomics_legal_T_177 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_178 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_179 = and(_atomics_legal_T_177, _atomics_legal_T_178) node _atomics_legal_T_180 = or(UInt<1>(0h0), _atomics_legal_T_179) node _atomics_legal_T_181 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_182 = cvt(_atomics_legal_T_181) node _atomics_legal_T_183 = and(_atomics_legal_T_182, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_184 = asSInt(_atomics_legal_T_183) node _atomics_legal_T_185 = eq(_atomics_legal_T_184, asSInt(UInt<1>(0h0))) node _atomics_legal_T_186 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_187 = cvt(_atomics_legal_T_186) node _atomics_legal_T_188 = and(_atomics_legal_T_187, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_189 = asSInt(_atomics_legal_T_188) node _atomics_legal_T_190 = eq(_atomics_legal_T_189, asSInt(UInt<1>(0h0))) node _atomics_legal_T_191 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_192 = cvt(_atomics_legal_T_191) node _atomics_legal_T_193 = and(_atomics_legal_T_192, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_194 = asSInt(_atomics_legal_T_193) node _atomics_legal_T_195 = eq(_atomics_legal_T_194, asSInt(UInt<1>(0h0))) node _atomics_legal_T_196 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_197 = cvt(_atomics_legal_T_196) node _atomics_legal_T_198 = and(_atomics_legal_T_197, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_199 = asSInt(_atomics_legal_T_198) node _atomics_legal_T_200 = eq(_atomics_legal_T_199, asSInt(UInt<1>(0h0))) node _atomics_legal_T_201 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_202 = cvt(_atomics_legal_T_201) node _atomics_legal_T_203 = and(_atomics_legal_T_202, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_204 = asSInt(_atomics_legal_T_203) node _atomics_legal_T_205 = eq(_atomics_legal_T_204, asSInt(UInt<1>(0h0))) node _atomics_legal_T_206 = or(_atomics_legal_T_185, _atomics_legal_T_190) node _atomics_legal_T_207 = or(_atomics_legal_T_206, _atomics_legal_T_195) node _atomics_legal_T_208 = or(_atomics_legal_T_207, _atomics_legal_T_200) node _atomics_legal_T_209 = or(_atomics_legal_T_208, _atomics_legal_T_205) node _atomics_legal_T_210 = and(_atomics_legal_T_180, _atomics_legal_T_209) node _atomics_legal_T_211 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_212 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_213 = cvt(_atomics_legal_T_212) node _atomics_legal_T_214 = and(_atomics_legal_T_213, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_215 = asSInt(_atomics_legal_T_214) node _atomics_legal_T_216 = eq(_atomics_legal_T_215, asSInt(UInt<1>(0h0))) node _atomics_legal_T_217 = and(_atomics_legal_T_211, _atomics_legal_T_216) node _atomics_legal_T_218 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_219 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_220 = and(_atomics_legal_T_218, _atomics_legal_T_219) node _atomics_legal_T_221 = or(UInt<1>(0h0), _atomics_legal_T_220) node _atomics_legal_T_222 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_223 = cvt(_atomics_legal_T_222) node _atomics_legal_T_224 = and(_atomics_legal_T_223, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_225 = asSInt(_atomics_legal_T_224) node _atomics_legal_T_226 = eq(_atomics_legal_T_225, asSInt(UInt<1>(0h0))) node _atomics_legal_T_227 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_228 = cvt(_atomics_legal_T_227) node _atomics_legal_T_229 = and(_atomics_legal_T_228, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_230 = asSInt(_atomics_legal_T_229) node _atomics_legal_T_231 = eq(_atomics_legal_T_230, asSInt(UInt<1>(0h0))) node _atomics_legal_T_232 = or(_atomics_legal_T_226, _atomics_legal_T_231) node _atomics_legal_T_233 = and(_atomics_legal_T_221, _atomics_legal_T_232) node _atomics_legal_T_234 = or(UInt<1>(0h0), _atomics_legal_T_210) node _atomics_legal_T_235 = or(_atomics_legal_T_234, _atomics_legal_T_217) node atomics_legal_3 = or(_atomics_legal_T_235, _atomics_legal_T_233) wire atomics_a_3 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_3.opcode, UInt<2>(0h3) connect atomics_a_3.param, UInt<3>(0h2) connect atomics_a_3.size, req.uop.mem_size connect atomics_a_3.source, UInt<3>(0h5) connect atomics_a_3.address, req.addr node _atomics_a_mask_sizeOH_T_9 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_3 = bits(_atomics_a_mask_sizeOH_T_9, 1, 0) node _atomics_a_mask_sizeOH_T_10 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_3) node _atomics_a_mask_sizeOH_T_11 = bits(_atomics_a_mask_sizeOH_T_10, 3, 0) node atomics_a_mask_sizeOH_3 = or(_atomics_a_mask_sizeOH_T_11, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_3 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 3, 3) node atomics_a_mask_sub_sub_sub_bit_3 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_3 = eq(atomics_a_mask_sub_sub_sub_bit_3, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_3) node _atomics_a_mask_sub_sub_sub_acc_T_6 = and(atomics_a_mask_sub_sub_sub_size_3, atomics_a_mask_sub_sub_sub_0_2_3) node atomics_a_mask_sub_sub_sub_0_1_3 = or(atomics_a_mask_sub_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_sub_acc_T_6) node atomics_a_mask_sub_sub_sub_1_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_3) node _atomics_a_mask_sub_sub_sub_acc_T_7 = and(atomics_a_mask_sub_sub_sub_size_3, atomics_a_mask_sub_sub_sub_1_2_3) node atomics_a_mask_sub_sub_sub_1_1_3 = or(atomics_a_mask_sub_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_sub_acc_T_7) node atomics_a_mask_sub_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 2, 2) node atomics_a_mask_sub_sub_bit_3 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_3 = eq(atomics_a_mask_sub_sub_bit_3, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_3 = and(atomics_a_mask_sub_sub_sub_0_2_3, atomics_a_mask_sub_sub_nbit_3) node _atomics_a_mask_sub_sub_acc_T_12 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_0_2_3) node atomics_a_mask_sub_sub_0_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_12) node atomics_a_mask_sub_sub_1_2_3 = and(atomics_a_mask_sub_sub_sub_0_2_3, atomics_a_mask_sub_sub_bit_3) node _atomics_a_mask_sub_sub_acc_T_13 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_1_2_3) node atomics_a_mask_sub_sub_1_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_13) node atomics_a_mask_sub_sub_2_2_3 = and(atomics_a_mask_sub_sub_sub_1_2_3, atomics_a_mask_sub_sub_nbit_3) node _atomics_a_mask_sub_sub_acc_T_14 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_2_2_3) node atomics_a_mask_sub_sub_2_1_3 = or(atomics_a_mask_sub_sub_sub_1_1_3, _atomics_a_mask_sub_sub_acc_T_14) node atomics_a_mask_sub_sub_3_2_3 = and(atomics_a_mask_sub_sub_sub_1_2_3, atomics_a_mask_sub_sub_bit_3) node _atomics_a_mask_sub_sub_acc_T_15 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_3_2_3) node atomics_a_mask_sub_sub_3_1_3 = or(atomics_a_mask_sub_sub_sub_1_1_3, _atomics_a_mask_sub_sub_acc_T_15) node atomics_a_mask_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 1, 1) node atomics_a_mask_sub_bit_3 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_3 = eq(atomics_a_mask_sub_bit_3, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_nbit_3) node _atomics_a_mask_sub_acc_T_24 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_0_2_3) node atomics_a_mask_sub_0_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_24) node atomics_a_mask_sub_1_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_bit_3) node _atomics_a_mask_sub_acc_T_25 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_1_2_3) node atomics_a_mask_sub_1_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_25) node atomics_a_mask_sub_2_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_nbit_3) node _atomics_a_mask_sub_acc_T_26 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_2_2_3) node atomics_a_mask_sub_2_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_26) node atomics_a_mask_sub_3_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_bit_3) node _atomics_a_mask_sub_acc_T_27 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_3_2_3) node atomics_a_mask_sub_3_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_27) node atomics_a_mask_sub_4_2_3 = and(atomics_a_mask_sub_sub_2_2_3, atomics_a_mask_sub_nbit_3) node _atomics_a_mask_sub_acc_T_28 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_4_2_3) node atomics_a_mask_sub_4_1_3 = or(atomics_a_mask_sub_sub_2_1_3, _atomics_a_mask_sub_acc_T_28) node atomics_a_mask_sub_5_2_3 = and(atomics_a_mask_sub_sub_2_2_3, atomics_a_mask_sub_bit_3) node _atomics_a_mask_sub_acc_T_29 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_5_2_3) node atomics_a_mask_sub_5_1_3 = or(atomics_a_mask_sub_sub_2_1_3, _atomics_a_mask_sub_acc_T_29) node atomics_a_mask_sub_6_2_3 = and(atomics_a_mask_sub_sub_3_2_3, atomics_a_mask_sub_nbit_3) node _atomics_a_mask_sub_acc_T_30 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_6_2_3) node atomics_a_mask_sub_6_1_3 = or(atomics_a_mask_sub_sub_3_1_3, _atomics_a_mask_sub_acc_T_30) node atomics_a_mask_sub_7_2_3 = and(atomics_a_mask_sub_sub_3_2_3, atomics_a_mask_sub_bit_3) node _atomics_a_mask_sub_acc_T_31 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_7_2_3) node atomics_a_mask_sub_7_1_3 = or(atomics_a_mask_sub_sub_3_1_3, _atomics_a_mask_sub_acc_T_31) node atomics_a_mask_size_3 = bits(atomics_a_mask_sizeOH_3, 0, 0) node atomics_a_mask_bit_3 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_3 = eq(atomics_a_mask_bit_3, UInt<1>(0h0)) node atomics_a_mask_eq_48 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_48 = and(atomics_a_mask_size_3, atomics_a_mask_eq_48) node atomics_a_mask_acc_48 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_48) node atomics_a_mask_eq_49 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_49 = and(atomics_a_mask_size_3, atomics_a_mask_eq_49) node atomics_a_mask_acc_49 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_49) node atomics_a_mask_eq_50 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_50 = and(atomics_a_mask_size_3, atomics_a_mask_eq_50) node atomics_a_mask_acc_50 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_50) node atomics_a_mask_eq_51 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_51 = and(atomics_a_mask_size_3, atomics_a_mask_eq_51) node atomics_a_mask_acc_51 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_51) node atomics_a_mask_eq_52 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_52 = and(atomics_a_mask_size_3, atomics_a_mask_eq_52) node atomics_a_mask_acc_52 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_52) node atomics_a_mask_eq_53 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_53 = and(atomics_a_mask_size_3, atomics_a_mask_eq_53) node atomics_a_mask_acc_53 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_53) node atomics_a_mask_eq_54 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_54 = and(atomics_a_mask_size_3, atomics_a_mask_eq_54) node atomics_a_mask_acc_54 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_54) node atomics_a_mask_eq_55 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_55 = and(atomics_a_mask_size_3, atomics_a_mask_eq_55) node atomics_a_mask_acc_55 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_55) node atomics_a_mask_eq_56 = and(atomics_a_mask_sub_4_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_56 = and(atomics_a_mask_size_3, atomics_a_mask_eq_56) node atomics_a_mask_acc_56 = or(atomics_a_mask_sub_4_1_3, _atomics_a_mask_acc_T_56) node atomics_a_mask_eq_57 = and(atomics_a_mask_sub_4_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_57 = and(atomics_a_mask_size_3, atomics_a_mask_eq_57) node atomics_a_mask_acc_57 = or(atomics_a_mask_sub_4_1_3, _atomics_a_mask_acc_T_57) node atomics_a_mask_eq_58 = and(atomics_a_mask_sub_5_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_58 = and(atomics_a_mask_size_3, atomics_a_mask_eq_58) node atomics_a_mask_acc_58 = or(atomics_a_mask_sub_5_1_3, _atomics_a_mask_acc_T_58) node atomics_a_mask_eq_59 = and(atomics_a_mask_sub_5_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_59 = and(atomics_a_mask_size_3, atomics_a_mask_eq_59) node atomics_a_mask_acc_59 = or(atomics_a_mask_sub_5_1_3, _atomics_a_mask_acc_T_59) node atomics_a_mask_eq_60 = and(atomics_a_mask_sub_6_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_60 = and(atomics_a_mask_size_3, atomics_a_mask_eq_60) node atomics_a_mask_acc_60 = or(atomics_a_mask_sub_6_1_3, _atomics_a_mask_acc_T_60) node atomics_a_mask_eq_61 = and(atomics_a_mask_sub_6_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_61 = and(atomics_a_mask_size_3, atomics_a_mask_eq_61) node atomics_a_mask_acc_61 = or(atomics_a_mask_sub_6_1_3, _atomics_a_mask_acc_T_61) node atomics_a_mask_eq_62 = and(atomics_a_mask_sub_7_2_3, atomics_a_mask_nbit_3) node _atomics_a_mask_acc_T_62 = and(atomics_a_mask_size_3, atomics_a_mask_eq_62) node atomics_a_mask_acc_62 = or(atomics_a_mask_sub_7_1_3, _atomics_a_mask_acc_T_62) node atomics_a_mask_eq_63 = and(atomics_a_mask_sub_7_2_3, atomics_a_mask_bit_3) node _atomics_a_mask_acc_T_63 = and(atomics_a_mask_size_3, atomics_a_mask_eq_63) node atomics_a_mask_acc_63 = or(atomics_a_mask_sub_7_1_3, _atomics_a_mask_acc_T_63) node atomics_a_mask_lo_lo_lo_3 = cat(atomics_a_mask_acc_49, atomics_a_mask_acc_48) node atomics_a_mask_lo_lo_hi_3 = cat(atomics_a_mask_acc_51, atomics_a_mask_acc_50) node atomics_a_mask_lo_lo_3 = cat(atomics_a_mask_lo_lo_hi_3, atomics_a_mask_lo_lo_lo_3) node atomics_a_mask_lo_hi_lo_3 = cat(atomics_a_mask_acc_53, atomics_a_mask_acc_52) node atomics_a_mask_lo_hi_hi_3 = cat(atomics_a_mask_acc_55, atomics_a_mask_acc_54) node atomics_a_mask_lo_hi_3 = cat(atomics_a_mask_lo_hi_hi_3, atomics_a_mask_lo_hi_lo_3) node atomics_a_mask_lo_3 = cat(atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3) node atomics_a_mask_hi_lo_lo_3 = cat(atomics_a_mask_acc_57, atomics_a_mask_acc_56) node atomics_a_mask_hi_lo_hi_3 = cat(atomics_a_mask_acc_59, atomics_a_mask_acc_58) node atomics_a_mask_hi_lo_3 = cat(atomics_a_mask_hi_lo_hi_3, atomics_a_mask_hi_lo_lo_3) node atomics_a_mask_hi_hi_lo_3 = cat(atomics_a_mask_acc_61, atomics_a_mask_acc_60) node atomics_a_mask_hi_hi_hi_3 = cat(atomics_a_mask_acc_63, atomics_a_mask_acc_62) node atomics_a_mask_hi_hi_3 = cat(atomics_a_mask_hi_hi_hi_3, atomics_a_mask_hi_hi_lo_3) node atomics_a_mask_hi_3 = cat(atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3) node _atomics_a_mask_T_3 = cat(atomics_a_mask_hi_3, atomics_a_mask_lo_3) connect atomics_a_3.mask, _atomics_a_mask_T_3 connect atomics_a_3.data, a_data connect atomics_a_3.corrupt, UInt<1>(0h0) node _atomics_legal_T_236 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_237 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_238 = and(_atomics_legal_T_236, _atomics_legal_T_237) node _atomics_legal_T_239 = or(UInt<1>(0h0), _atomics_legal_T_238) node _atomics_legal_T_240 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_241 = cvt(_atomics_legal_T_240) node _atomics_legal_T_242 = and(_atomics_legal_T_241, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_243 = asSInt(_atomics_legal_T_242) node _atomics_legal_T_244 = eq(_atomics_legal_T_243, asSInt(UInt<1>(0h0))) node _atomics_legal_T_245 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_246 = cvt(_atomics_legal_T_245) node _atomics_legal_T_247 = and(_atomics_legal_T_246, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_248 = asSInt(_atomics_legal_T_247) node _atomics_legal_T_249 = eq(_atomics_legal_T_248, asSInt(UInt<1>(0h0))) node _atomics_legal_T_250 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_251 = cvt(_atomics_legal_T_250) node _atomics_legal_T_252 = and(_atomics_legal_T_251, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_253 = asSInt(_atomics_legal_T_252) node _atomics_legal_T_254 = eq(_atomics_legal_T_253, asSInt(UInt<1>(0h0))) node _atomics_legal_T_255 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_256 = cvt(_atomics_legal_T_255) node _atomics_legal_T_257 = and(_atomics_legal_T_256, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_258 = asSInt(_atomics_legal_T_257) node _atomics_legal_T_259 = eq(_atomics_legal_T_258, asSInt(UInt<1>(0h0))) node _atomics_legal_T_260 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_261 = cvt(_atomics_legal_T_260) node _atomics_legal_T_262 = and(_atomics_legal_T_261, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_263 = asSInt(_atomics_legal_T_262) node _atomics_legal_T_264 = eq(_atomics_legal_T_263, asSInt(UInt<1>(0h0))) node _atomics_legal_T_265 = or(_atomics_legal_T_244, _atomics_legal_T_249) node _atomics_legal_T_266 = or(_atomics_legal_T_265, _atomics_legal_T_254) node _atomics_legal_T_267 = or(_atomics_legal_T_266, _atomics_legal_T_259) node _atomics_legal_T_268 = or(_atomics_legal_T_267, _atomics_legal_T_264) node _atomics_legal_T_269 = and(_atomics_legal_T_239, _atomics_legal_T_268) node _atomics_legal_T_270 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_271 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_272 = cvt(_atomics_legal_T_271) node _atomics_legal_T_273 = and(_atomics_legal_T_272, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_274 = asSInt(_atomics_legal_T_273) node _atomics_legal_T_275 = eq(_atomics_legal_T_274, asSInt(UInt<1>(0h0))) node _atomics_legal_T_276 = and(_atomics_legal_T_270, _atomics_legal_T_275) node _atomics_legal_T_277 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_278 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_279 = and(_atomics_legal_T_277, _atomics_legal_T_278) node _atomics_legal_T_280 = or(UInt<1>(0h0), _atomics_legal_T_279) node _atomics_legal_T_281 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_282 = cvt(_atomics_legal_T_281) node _atomics_legal_T_283 = and(_atomics_legal_T_282, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_284 = asSInt(_atomics_legal_T_283) node _atomics_legal_T_285 = eq(_atomics_legal_T_284, asSInt(UInt<1>(0h0))) node _atomics_legal_T_286 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_287 = cvt(_atomics_legal_T_286) node _atomics_legal_T_288 = and(_atomics_legal_T_287, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_289 = asSInt(_atomics_legal_T_288) node _atomics_legal_T_290 = eq(_atomics_legal_T_289, asSInt(UInt<1>(0h0))) node _atomics_legal_T_291 = or(_atomics_legal_T_285, _atomics_legal_T_290) node _atomics_legal_T_292 = and(_atomics_legal_T_280, _atomics_legal_T_291) node _atomics_legal_T_293 = or(UInt<1>(0h0), _atomics_legal_T_269) node _atomics_legal_T_294 = or(_atomics_legal_T_293, _atomics_legal_T_276) node atomics_legal_4 = or(_atomics_legal_T_294, _atomics_legal_T_292) wire atomics_a_4 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_4.opcode, UInt<2>(0h2) connect atomics_a_4.param, UInt<3>(0h4) connect atomics_a_4.size, req.uop.mem_size connect atomics_a_4.source, UInt<3>(0h5) connect atomics_a_4.address, req.addr node _atomics_a_mask_sizeOH_T_12 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_4 = bits(_atomics_a_mask_sizeOH_T_12, 1, 0) node _atomics_a_mask_sizeOH_T_13 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_4) node _atomics_a_mask_sizeOH_T_14 = bits(_atomics_a_mask_sizeOH_T_13, 3, 0) node atomics_a_mask_sizeOH_4 = or(_atomics_a_mask_sizeOH_T_14, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_4 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 3, 3) node atomics_a_mask_sub_sub_sub_bit_4 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_4 = eq(atomics_a_mask_sub_sub_sub_bit_4, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_4) node _atomics_a_mask_sub_sub_sub_acc_T_8 = and(atomics_a_mask_sub_sub_sub_size_4, atomics_a_mask_sub_sub_sub_0_2_4) node atomics_a_mask_sub_sub_sub_0_1_4 = or(atomics_a_mask_sub_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_sub_acc_T_8) node atomics_a_mask_sub_sub_sub_1_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_4) node _atomics_a_mask_sub_sub_sub_acc_T_9 = and(atomics_a_mask_sub_sub_sub_size_4, atomics_a_mask_sub_sub_sub_1_2_4) node atomics_a_mask_sub_sub_sub_1_1_4 = or(atomics_a_mask_sub_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_sub_acc_T_9) node atomics_a_mask_sub_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 2, 2) node atomics_a_mask_sub_sub_bit_4 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_4 = eq(atomics_a_mask_sub_sub_bit_4, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_4 = and(atomics_a_mask_sub_sub_sub_0_2_4, atomics_a_mask_sub_sub_nbit_4) node _atomics_a_mask_sub_sub_acc_T_16 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_0_2_4) node atomics_a_mask_sub_sub_0_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_16) node atomics_a_mask_sub_sub_1_2_4 = and(atomics_a_mask_sub_sub_sub_0_2_4, atomics_a_mask_sub_sub_bit_4) node _atomics_a_mask_sub_sub_acc_T_17 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_1_2_4) node atomics_a_mask_sub_sub_1_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_17) node atomics_a_mask_sub_sub_2_2_4 = and(atomics_a_mask_sub_sub_sub_1_2_4, atomics_a_mask_sub_sub_nbit_4) node _atomics_a_mask_sub_sub_acc_T_18 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_2_2_4) node atomics_a_mask_sub_sub_2_1_4 = or(atomics_a_mask_sub_sub_sub_1_1_4, _atomics_a_mask_sub_sub_acc_T_18) node atomics_a_mask_sub_sub_3_2_4 = and(atomics_a_mask_sub_sub_sub_1_2_4, atomics_a_mask_sub_sub_bit_4) node _atomics_a_mask_sub_sub_acc_T_19 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_3_2_4) node atomics_a_mask_sub_sub_3_1_4 = or(atomics_a_mask_sub_sub_sub_1_1_4, _atomics_a_mask_sub_sub_acc_T_19) node atomics_a_mask_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 1, 1) node atomics_a_mask_sub_bit_4 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_4 = eq(atomics_a_mask_sub_bit_4, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_nbit_4) node _atomics_a_mask_sub_acc_T_32 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_0_2_4) node atomics_a_mask_sub_0_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_32) node atomics_a_mask_sub_1_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_bit_4) node _atomics_a_mask_sub_acc_T_33 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_1_2_4) node atomics_a_mask_sub_1_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_33) node atomics_a_mask_sub_2_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_nbit_4) node _atomics_a_mask_sub_acc_T_34 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_2_2_4) node atomics_a_mask_sub_2_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_34) node atomics_a_mask_sub_3_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_bit_4) node _atomics_a_mask_sub_acc_T_35 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_3_2_4) node atomics_a_mask_sub_3_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_35) node atomics_a_mask_sub_4_2_4 = and(atomics_a_mask_sub_sub_2_2_4, atomics_a_mask_sub_nbit_4) node _atomics_a_mask_sub_acc_T_36 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_4_2_4) node atomics_a_mask_sub_4_1_4 = or(atomics_a_mask_sub_sub_2_1_4, _atomics_a_mask_sub_acc_T_36) node atomics_a_mask_sub_5_2_4 = and(atomics_a_mask_sub_sub_2_2_4, atomics_a_mask_sub_bit_4) node _atomics_a_mask_sub_acc_T_37 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_5_2_4) node atomics_a_mask_sub_5_1_4 = or(atomics_a_mask_sub_sub_2_1_4, _atomics_a_mask_sub_acc_T_37) node atomics_a_mask_sub_6_2_4 = and(atomics_a_mask_sub_sub_3_2_4, atomics_a_mask_sub_nbit_4) node _atomics_a_mask_sub_acc_T_38 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_6_2_4) node atomics_a_mask_sub_6_1_4 = or(atomics_a_mask_sub_sub_3_1_4, _atomics_a_mask_sub_acc_T_38) node atomics_a_mask_sub_7_2_4 = and(atomics_a_mask_sub_sub_3_2_4, atomics_a_mask_sub_bit_4) node _atomics_a_mask_sub_acc_T_39 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_7_2_4) node atomics_a_mask_sub_7_1_4 = or(atomics_a_mask_sub_sub_3_1_4, _atomics_a_mask_sub_acc_T_39) node atomics_a_mask_size_4 = bits(atomics_a_mask_sizeOH_4, 0, 0) node atomics_a_mask_bit_4 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_4 = eq(atomics_a_mask_bit_4, UInt<1>(0h0)) node atomics_a_mask_eq_64 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_64 = and(atomics_a_mask_size_4, atomics_a_mask_eq_64) node atomics_a_mask_acc_64 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_64) node atomics_a_mask_eq_65 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_65 = and(atomics_a_mask_size_4, atomics_a_mask_eq_65) node atomics_a_mask_acc_65 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_65) node atomics_a_mask_eq_66 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_66 = and(atomics_a_mask_size_4, atomics_a_mask_eq_66) node atomics_a_mask_acc_66 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_66) node atomics_a_mask_eq_67 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_67 = and(atomics_a_mask_size_4, atomics_a_mask_eq_67) node atomics_a_mask_acc_67 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_67) node atomics_a_mask_eq_68 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_68 = and(atomics_a_mask_size_4, atomics_a_mask_eq_68) node atomics_a_mask_acc_68 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_68) node atomics_a_mask_eq_69 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_69 = and(atomics_a_mask_size_4, atomics_a_mask_eq_69) node atomics_a_mask_acc_69 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_69) node atomics_a_mask_eq_70 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_70 = and(atomics_a_mask_size_4, atomics_a_mask_eq_70) node atomics_a_mask_acc_70 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_70) node atomics_a_mask_eq_71 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_71 = and(atomics_a_mask_size_4, atomics_a_mask_eq_71) node atomics_a_mask_acc_71 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_71) node atomics_a_mask_eq_72 = and(atomics_a_mask_sub_4_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_72 = and(atomics_a_mask_size_4, atomics_a_mask_eq_72) node atomics_a_mask_acc_72 = or(atomics_a_mask_sub_4_1_4, _atomics_a_mask_acc_T_72) node atomics_a_mask_eq_73 = and(atomics_a_mask_sub_4_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_73 = and(atomics_a_mask_size_4, atomics_a_mask_eq_73) node atomics_a_mask_acc_73 = or(atomics_a_mask_sub_4_1_4, _atomics_a_mask_acc_T_73) node atomics_a_mask_eq_74 = and(atomics_a_mask_sub_5_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_74 = and(atomics_a_mask_size_4, atomics_a_mask_eq_74) node atomics_a_mask_acc_74 = or(atomics_a_mask_sub_5_1_4, _atomics_a_mask_acc_T_74) node atomics_a_mask_eq_75 = and(atomics_a_mask_sub_5_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_75 = and(atomics_a_mask_size_4, atomics_a_mask_eq_75) node atomics_a_mask_acc_75 = or(atomics_a_mask_sub_5_1_4, _atomics_a_mask_acc_T_75) node atomics_a_mask_eq_76 = and(atomics_a_mask_sub_6_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_76 = and(atomics_a_mask_size_4, atomics_a_mask_eq_76) node atomics_a_mask_acc_76 = or(atomics_a_mask_sub_6_1_4, _atomics_a_mask_acc_T_76) node atomics_a_mask_eq_77 = and(atomics_a_mask_sub_6_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_77 = and(atomics_a_mask_size_4, atomics_a_mask_eq_77) node atomics_a_mask_acc_77 = or(atomics_a_mask_sub_6_1_4, _atomics_a_mask_acc_T_77) node atomics_a_mask_eq_78 = and(atomics_a_mask_sub_7_2_4, atomics_a_mask_nbit_4) node _atomics_a_mask_acc_T_78 = and(atomics_a_mask_size_4, atomics_a_mask_eq_78) node atomics_a_mask_acc_78 = or(atomics_a_mask_sub_7_1_4, _atomics_a_mask_acc_T_78) node atomics_a_mask_eq_79 = and(atomics_a_mask_sub_7_2_4, atomics_a_mask_bit_4) node _atomics_a_mask_acc_T_79 = and(atomics_a_mask_size_4, atomics_a_mask_eq_79) node atomics_a_mask_acc_79 = or(atomics_a_mask_sub_7_1_4, _atomics_a_mask_acc_T_79) node atomics_a_mask_lo_lo_lo_4 = cat(atomics_a_mask_acc_65, atomics_a_mask_acc_64) node atomics_a_mask_lo_lo_hi_4 = cat(atomics_a_mask_acc_67, atomics_a_mask_acc_66) node atomics_a_mask_lo_lo_4 = cat(atomics_a_mask_lo_lo_hi_4, atomics_a_mask_lo_lo_lo_4) node atomics_a_mask_lo_hi_lo_4 = cat(atomics_a_mask_acc_69, atomics_a_mask_acc_68) node atomics_a_mask_lo_hi_hi_4 = cat(atomics_a_mask_acc_71, atomics_a_mask_acc_70) node atomics_a_mask_lo_hi_4 = cat(atomics_a_mask_lo_hi_hi_4, atomics_a_mask_lo_hi_lo_4) node atomics_a_mask_lo_4 = cat(atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4) node atomics_a_mask_hi_lo_lo_4 = cat(atomics_a_mask_acc_73, atomics_a_mask_acc_72) node atomics_a_mask_hi_lo_hi_4 = cat(atomics_a_mask_acc_75, atomics_a_mask_acc_74) node atomics_a_mask_hi_lo_4 = cat(atomics_a_mask_hi_lo_hi_4, atomics_a_mask_hi_lo_lo_4) node atomics_a_mask_hi_hi_lo_4 = cat(atomics_a_mask_acc_77, atomics_a_mask_acc_76) node atomics_a_mask_hi_hi_hi_4 = cat(atomics_a_mask_acc_79, atomics_a_mask_acc_78) node atomics_a_mask_hi_hi_4 = cat(atomics_a_mask_hi_hi_hi_4, atomics_a_mask_hi_hi_lo_4) node atomics_a_mask_hi_4 = cat(atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4) node _atomics_a_mask_T_4 = cat(atomics_a_mask_hi_4, atomics_a_mask_lo_4) connect atomics_a_4.mask, _atomics_a_mask_T_4 connect atomics_a_4.data, a_data connect atomics_a_4.corrupt, UInt<1>(0h0) node _atomics_legal_T_295 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_296 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_297 = and(_atomics_legal_T_295, _atomics_legal_T_296) node _atomics_legal_T_298 = or(UInt<1>(0h0), _atomics_legal_T_297) node _atomics_legal_T_299 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_300 = cvt(_atomics_legal_T_299) node _atomics_legal_T_301 = and(_atomics_legal_T_300, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_302 = asSInt(_atomics_legal_T_301) node _atomics_legal_T_303 = eq(_atomics_legal_T_302, asSInt(UInt<1>(0h0))) node _atomics_legal_T_304 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_305 = cvt(_atomics_legal_T_304) node _atomics_legal_T_306 = and(_atomics_legal_T_305, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_307 = asSInt(_atomics_legal_T_306) node _atomics_legal_T_308 = eq(_atomics_legal_T_307, asSInt(UInt<1>(0h0))) node _atomics_legal_T_309 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_310 = cvt(_atomics_legal_T_309) node _atomics_legal_T_311 = and(_atomics_legal_T_310, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_312 = asSInt(_atomics_legal_T_311) node _atomics_legal_T_313 = eq(_atomics_legal_T_312, asSInt(UInt<1>(0h0))) node _atomics_legal_T_314 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_315 = cvt(_atomics_legal_T_314) node _atomics_legal_T_316 = and(_atomics_legal_T_315, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_317 = asSInt(_atomics_legal_T_316) node _atomics_legal_T_318 = eq(_atomics_legal_T_317, asSInt(UInt<1>(0h0))) node _atomics_legal_T_319 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_320 = cvt(_atomics_legal_T_319) node _atomics_legal_T_321 = and(_atomics_legal_T_320, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_322 = asSInt(_atomics_legal_T_321) node _atomics_legal_T_323 = eq(_atomics_legal_T_322, asSInt(UInt<1>(0h0))) node _atomics_legal_T_324 = or(_atomics_legal_T_303, _atomics_legal_T_308) node _atomics_legal_T_325 = or(_atomics_legal_T_324, _atomics_legal_T_313) node _atomics_legal_T_326 = or(_atomics_legal_T_325, _atomics_legal_T_318) node _atomics_legal_T_327 = or(_atomics_legal_T_326, _atomics_legal_T_323) node _atomics_legal_T_328 = and(_atomics_legal_T_298, _atomics_legal_T_327) node _atomics_legal_T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_330 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_331 = cvt(_atomics_legal_T_330) node _atomics_legal_T_332 = and(_atomics_legal_T_331, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_333 = asSInt(_atomics_legal_T_332) node _atomics_legal_T_334 = eq(_atomics_legal_T_333, asSInt(UInt<1>(0h0))) node _atomics_legal_T_335 = and(_atomics_legal_T_329, _atomics_legal_T_334) node _atomics_legal_T_336 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_337 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_338 = and(_atomics_legal_T_336, _atomics_legal_T_337) node _atomics_legal_T_339 = or(UInt<1>(0h0), _atomics_legal_T_338) node _atomics_legal_T_340 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_341 = cvt(_atomics_legal_T_340) node _atomics_legal_T_342 = and(_atomics_legal_T_341, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_343 = asSInt(_atomics_legal_T_342) node _atomics_legal_T_344 = eq(_atomics_legal_T_343, asSInt(UInt<1>(0h0))) node _atomics_legal_T_345 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_346 = cvt(_atomics_legal_T_345) node _atomics_legal_T_347 = and(_atomics_legal_T_346, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_348 = asSInt(_atomics_legal_T_347) node _atomics_legal_T_349 = eq(_atomics_legal_T_348, asSInt(UInt<1>(0h0))) node _atomics_legal_T_350 = or(_atomics_legal_T_344, _atomics_legal_T_349) node _atomics_legal_T_351 = and(_atomics_legal_T_339, _atomics_legal_T_350) node _atomics_legal_T_352 = or(UInt<1>(0h0), _atomics_legal_T_328) node _atomics_legal_T_353 = or(_atomics_legal_T_352, _atomics_legal_T_335) node atomics_legal_5 = or(_atomics_legal_T_353, _atomics_legal_T_351) wire atomics_a_5 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_5.opcode, UInt<2>(0h2) connect atomics_a_5.param, UInt<3>(0h0) connect atomics_a_5.size, req.uop.mem_size connect atomics_a_5.source, UInt<3>(0h5) connect atomics_a_5.address, req.addr node _atomics_a_mask_sizeOH_T_15 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_5 = bits(_atomics_a_mask_sizeOH_T_15, 1, 0) node _atomics_a_mask_sizeOH_T_16 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_5) node _atomics_a_mask_sizeOH_T_17 = bits(_atomics_a_mask_sizeOH_T_16, 3, 0) node atomics_a_mask_sizeOH_5 = or(_atomics_a_mask_sizeOH_T_17, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_5 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 3, 3) node atomics_a_mask_sub_sub_sub_bit_5 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_5 = eq(atomics_a_mask_sub_sub_sub_bit_5, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_5) node _atomics_a_mask_sub_sub_sub_acc_T_10 = and(atomics_a_mask_sub_sub_sub_size_5, atomics_a_mask_sub_sub_sub_0_2_5) node atomics_a_mask_sub_sub_sub_0_1_5 = or(atomics_a_mask_sub_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_sub_acc_T_10) node atomics_a_mask_sub_sub_sub_1_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_5) node _atomics_a_mask_sub_sub_sub_acc_T_11 = and(atomics_a_mask_sub_sub_sub_size_5, atomics_a_mask_sub_sub_sub_1_2_5) node atomics_a_mask_sub_sub_sub_1_1_5 = or(atomics_a_mask_sub_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_sub_acc_T_11) node atomics_a_mask_sub_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 2, 2) node atomics_a_mask_sub_sub_bit_5 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_5 = eq(atomics_a_mask_sub_sub_bit_5, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_5 = and(atomics_a_mask_sub_sub_sub_0_2_5, atomics_a_mask_sub_sub_nbit_5) node _atomics_a_mask_sub_sub_acc_T_20 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_0_2_5) node atomics_a_mask_sub_sub_0_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_20) node atomics_a_mask_sub_sub_1_2_5 = and(atomics_a_mask_sub_sub_sub_0_2_5, atomics_a_mask_sub_sub_bit_5) node _atomics_a_mask_sub_sub_acc_T_21 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_1_2_5) node atomics_a_mask_sub_sub_1_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_21) node atomics_a_mask_sub_sub_2_2_5 = and(atomics_a_mask_sub_sub_sub_1_2_5, atomics_a_mask_sub_sub_nbit_5) node _atomics_a_mask_sub_sub_acc_T_22 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_2_2_5) node atomics_a_mask_sub_sub_2_1_5 = or(atomics_a_mask_sub_sub_sub_1_1_5, _atomics_a_mask_sub_sub_acc_T_22) node atomics_a_mask_sub_sub_3_2_5 = and(atomics_a_mask_sub_sub_sub_1_2_5, atomics_a_mask_sub_sub_bit_5) node _atomics_a_mask_sub_sub_acc_T_23 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_3_2_5) node atomics_a_mask_sub_sub_3_1_5 = or(atomics_a_mask_sub_sub_sub_1_1_5, _atomics_a_mask_sub_sub_acc_T_23) node atomics_a_mask_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 1, 1) node atomics_a_mask_sub_bit_5 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_5 = eq(atomics_a_mask_sub_bit_5, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_nbit_5) node _atomics_a_mask_sub_acc_T_40 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_0_2_5) node atomics_a_mask_sub_0_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_40) node atomics_a_mask_sub_1_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_bit_5) node _atomics_a_mask_sub_acc_T_41 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_1_2_5) node atomics_a_mask_sub_1_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_41) node atomics_a_mask_sub_2_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_nbit_5) node _atomics_a_mask_sub_acc_T_42 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_2_2_5) node atomics_a_mask_sub_2_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_42) node atomics_a_mask_sub_3_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_bit_5) node _atomics_a_mask_sub_acc_T_43 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_3_2_5) node atomics_a_mask_sub_3_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_43) node atomics_a_mask_sub_4_2_5 = and(atomics_a_mask_sub_sub_2_2_5, atomics_a_mask_sub_nbit_5) node _atomics_a_mask_sub_acc_T_44 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_4_2_5) node atomics_a_mask_sub_4_1_5 = or(atomics_a_mask_sub_sub_2_1_5, _atomics_a_mask_sub_acc_T_44) node atomics_a_mask_sub_5_2_5 = and(atomics_a_mask_sub_sub_2_2_5, atomics_a_mask_sub_bit_5) node _atomics_a_mask_sub_acc_T_45 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_5_2_5) node atomics_a_mask_sub_5_1_5 = or(atomics_a_mask_sub_sub_2_1_5, _atomics_a_mask_sub_acc_T_45) node atomics_a_mask_sub_6_2_5 = and(atomics_a_mask_sub_sub_3_2_5, atomics_a_mask_sub_nbit_5) node _atomics_a_mask_sub_acc_T_46 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_6_2_5) node atomics_a_mask_sub_6_1_5 = or(atomics_a_mask_sub_sub_3_1_5, _atomics_a_mask_sub_acc_T_46) node atomics_a_mask_sub_7_2_5 = and(atomics_a_mask_sub_sub_3_2_5, atomics_a_mask_sub_bit_5) node _atomics_a_mask_sub_acc_T_47 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_7_2_5) node atomics_a_mask_sub_7_1_5 = or(atomics_a_mask_sub_sub_3_1_5, _atomics_a_mask_sub_acc_T_47) node atomics_a_mask_size_5 = bits(atomics_a_mask_sizeOH_5, 0, 0) node atomics_a_mask_bit_5 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_5 = eq(atomics_a_mask_bit_5, UInt<1>(0h0)) node atomics_a_mask_eq_80 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_80 = and(atomics_a_mask_size_5, atomics_a_mask_eq_80) node atomics_a_mask_acc_80 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_80) node atomics_a_mask_eq_81 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_81 = and(atomics_a_mask_size_5, atomics_a_mask_eq_81) node atomics_a_mask_acc_81 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_81) node atomics_a_mask_eq_82 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_82 = and(atomics_a_mask_size_5, atomics_a_mask_eq_82) node atomics_a_mask_acc_82 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_82) node atomics_a_mask_eq_83 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_83 = and(atomics_a_mask_size_5, atomics_a_mask_eq_83) node atomics_a_mask_acc_83 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_83) node atomics_a_mask_eq_84 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_84 = and(atomics_a_mask_size_5, atomics_a_mask_eq_84) node atomics_a_mask_acc_84 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_84) node atomics_a_mask_eq_85 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_85 = and(atomics_a_mask_size_5, atomics_a_mask_eq_85) node atomics_a_mask_acc_85 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_85) node atomics_a_mask_eq_86 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_86 = and(atomics_a_mask_size_5, atomics_a_mask_eq_86) node atomics_a_mask_acc_86 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_86) node atomics_a_mask_eq_87 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_87 = and(atomics_a_mask_size_5, atomics_a_mask_eq_87) node atomics_a_mask_acc_87 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_87) node atomics_a_mask_eq_88 = and(atomics_a_mask_sub_4_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_88 = and(atomics_a_mask_size_5, atomics_a_mask_eq_88) node atomics_a_mask_acc_88 = or(atomics_a_mask_sub_4_1_5, _atomics_a_mask_acc_T_88) node atomics_a_mask_eq_89 = and(atomics_a_mask_sub_4_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_89 = and(atomics_a_mask_size_5, atomics_a_mask_eq_89) node atomics_a_mask_acc_89 = or(atomics_a_mask_sub_4_1_5, _atomics_a_mask_acc_T_89) node atomics_a_mask_eq_90 = and(atomics_a_mask_sub_5_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_90 = and(atomics_a_mask_size_5, atomics_a_mask_eq_90) node atomics_a_mask_acc_90 = or(atomics_a_mask_sub_5_1_5, _atomics_a_mask_acc_T_90) node atomics_a_mask_eq_91 = and(atomics_a_mask_sub_5_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_91 = and(atomics_a_mask_size_5, atomics_a_mask_eq_91) node atomics_a_mask_acc_91 = or(atomics_a_mask_sub_5_1_5, _atomics_a_mask_acc_T_91) node atomics_a_mask_eq_92 = and(atomics_a_mask_sub_6_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_92 = and(atomics_a_mask_size_5, atomics_a_mask_eq_92) node atomics_a_mask_acc_92 = or(atomics_a_mask_sub_6_1_5, _atomics_a_mask_acc_T_92) node atomics_a_mask_eq_93 = and(atomics_a_mask_sub_6_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_93 = and(atomics_a_mask_size_5, atomics_a_mask_eq_93) node atomics_a_mask_acc_93 = or(atomics_a_mask_sub_6_1_5, _atomics_a_mask_acc_T_93) node atomics_a_mask_eq_94 = and(atomics_a_mask_sub_7_2_5, atomics_a_mask_nbit_5) node _atomics_a_mask_acc_T_94 = and(atomics_a_mask_size_5, atomics_a_mask_eq_94) node atomics_a_mask_acc_94 = or(atomics_a_mask_sub_7_1_5, _atomics_a_mask_acc_T_94) node atomics_a_mask_eq_95 = and(atomics_a_mask_sub_7_2_5, atomics_a_mask_bit_5) node _atomics_a_mask_acc_T_95 = and(atomics_a_mask_size_5, atomics_a_mask_eq_95) node atomics_a_mask_acc_95 = or(atomics_a_mask_sub_7_1_5, _atomics_a_mask_acc_T_95) node atomics_a_mask_lo_lo_lo_5 = cat(atomics_a_mask_acc_81, atomics_a_mask_acc_80) node atomics_a_mask_lo_lo_hi_5 = cat(atomics_a_mask_acc_83, atomics_a_mask_acc_82) node atomics_a_mask_lo_lo_5 = cat(atomics_a_mask_lo_lo_hi_5, atomics_a_mask_lo_lo_lo_5) node atomics_a_mask_lo_hi_lo_5 = cat(atomics_a_mask_acc_85, atomics_a_mask_acc_84) node atomics_a_mask_lo_hi_hi_5 = cat(atomics_a_mask_acc_87, atomics_a_mask_acc_86) node atomics_a_mask_lo_hi_5 = cat(atomics_a_mask_lo_hi_hi_5, atomics_a_mask_lo_hi_lo_5) node atomics_a_mask_lo_5 = cat(atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5) node atomics_a_mask_hi_lo_lo_5 = cat(atomics_a_mask_acc_89, atomics_a_mask_acc_88) node atomics_a_mask_hi_lo_hi_5 = cat(atomics_a_mask_acc_91, atomics_a_mask_acc_90) node atomics_a_mask_hi_lo_5 = cat(atomics_a_mask_hi_lo_hi_5, atomics_a_mask_hi_lo_lo_5) node atomics_a_mask_hi_hi_lo_5 = cat(atomics_a_mask_acc_93, atomics_a_mask_acc_92) node atomics_a_mask_hi_hi_hi_5 = cat(atomics_a_mask_acc_95, atomics_a_mask_acc_94) node atomics_a_mask_hi_hi_5 = cat(atomics_a_mask_hi_hi_hi_5, atomics_a_mask_hi_hi_lo_5) node atomics_a_mask_hi_5 = cat(atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5) node _atomics_a_mask_T_5 = cat(atomics_a_mask_hi_5, atomics_a_mask_lo_5) connect atomics_a_5.mask, _atomics_a_mask_T_5 connect atomics_a_5.data, a_data connect atomics_a_5.corrupt, UInt<1>(0h0) node _atomics_legal_T_354 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_355 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_356 = and(_atomics_legal_T_354, _atomics_legal_T_355) node _atomics_legal_T_357 = or(UInt<1>(0h0), _atomics_legal_T_356) node _atomics_legal_T_358 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_359 = cvt(_atomics_legal_T_358) node _atomics_legal_T_360 = and(_atomics_legal_T_359, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_361 = asSInt(_atomics_legal_T_360) node _atomics_legal_T_362 = eq(_atomics_legal_T_361, asSInt(UInt<1>(0h0))) node _atomics_legal_T_363 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_364 = cvt(_atomics_legal_T_363) node _atomics_legal_T_365 = and(_atomics_legal_T_364, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_366 = asSInt(_atomics_legal_T_365) node _atomics_legal_T_367 = eq(_atomics_legal_T_366, asSInt(UInt<1>(0h0))) node _atomics_legal_T_368 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_369 = cvt(_atomics_legal_T_368) node _atomics_legal_T_370 = and(_atomics_legal_T_369, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_371 = asSInt(_atomics_legal_T_370) node _atomics_legal_T_372 = eq(_atomics_legal_T_371, asSInt(UInt<1>(0h0))) node _atomics_legal_T_373 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_374 = cvt(_atomics_legal_T_373) node _atomics_legal_T_375 = and(_atomics_legal_T_374, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_376 = asSInt(_atomics_legal_T_375) node _atomics_legal_T_377 = eq(_atomics_legal_T_376, asSInt(UInt<1>(0h0))) node _atomics_legal_T_378 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_379 = cvt(_atomics_legal_T_378) node _atomics_legal_T_380 = and(_atomics_legal_T_379, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_381 = asSInt(_atomics_legal_T_380) node _atomics_legal_T_382 = eq(_atomics_legal_T_381, asSInt(UInt<1>(0h0))) node _atomics_legal_T_383 = or(_atomics_legal_T_362, _atomics_legal_T_367) node _atomics_legal_T_384 = or(_atomics_legal_T_383, _atomics_legal_T_372) node _atomics_legal_T_385 = or(_atomics_legal_T_384, _atomics_legal_T_377) node _atomics_legal_T_386 = or(_atomics_legal_T_385, _atomics_legal_T_382) node _atomics_legal_T_387 = and(_atomics_legal_T_357, _atomics_legal_T_386) node _atomics_legal_T_388 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_389 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_390 = cvt(_atomics_legal_T_389) node _atomics_legal_T_391 = and(_atomics_legal_T_390, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_392 = asSInt(_atomics_legal_T_391) node _atomics_legal_T_393 = eq(_atomics_legal_T_392, asSInt(UInt<1>(0h0))) node _atomics_legal_T_394 = and(_atomics_legal_T_388, _atomics_legal_T_393) node _atomics_legal_T_395 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_396 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_397 = and(_atomics_legal_T_395, _atomics_legal_T_396) node _atomics_legal_T_398 = or(UInt<1>(0h0), _atomics_legal_T_397) node _atomics_legal_T_399 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_400 = cvt(_atomics_legal_T_399) node _atomics_legal_T_401 = and(_atomics_legal_T_400, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_402 = asSInt(_atomics_legal_T_401) node _atomics_legal_T_403 = eq(_atomics_legal_T_402, asSInt(UInt<1>(0h0))) node _atomics_legal_T_404 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_405 = cvt(_atomics_legal_T_404) node _atomics_legal_T_406 = and(_atomics_legal_T_405, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_407 = asSInt(_atomics_legal_T_406) node _atomics_legal_T_408 = eq(_atomics_legal_T_407, asSInt(UInt<1>(0h0))) node _atomics_legal_T_409 = or(_atomics_legal_T_403, _atomics_legal_T_408) node _atomics_legal_T_410 = and(_atomics_legal_T_398, _atomics_legal_T_409) node _atomics_legal_T_411 = or(UInt<1>(0h0), _atomics_legal_T_387) node _atomics_legal_T_412 = or(_atomics_legal_T_411, _atomics_legal_T_394) node atomics_legal_6 = or(_atomics_legal_T_412, _atomics_legal_T_410) wire atomics_a_6 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_6.opcode, UInt<2>(0h2) connect atomics_a_6.param, UInt<3>(0h1) connect atomics_a_6.size, req.uop.mem_size connect atomics_a_6.source, UInt<3>(0h5) connect atomics_a_6.address, req.addr node _atomics_a_mask_sizeOH_T_18 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_6 = bits(_atomics_a_mask_sizeOH_T_18, 1, 0) node _atomics_a_mask_sizeOH_T_19 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_6) node _atomics_a_mask_sizeOH_T_20 = bits(_atomics_a_mask_sizeOH_T_19, 3, 0) node atomics_a_mask_sizeOH_6 = or(_atomics_a_mask_sizeOH_T_20, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_6 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 3, 3) node atomics_a_mask_sub_sub_sub_bit_6 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_6 = eq(atomics_a_mask_sub_sub_sub_bit_6, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_6) node _atomics_a_mask_sub_sub_sub_acc_T_12 = and(atomics_a_mask_sub_sub_sub_size_6, atomics_a_mask_sub_sub_sub_0_2_6) node atomics_a_mask_sub_sub_sub_0_1_6 = or(atomics_a_mask_sub_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_sub_acc_T_12) node atomics_a_mask_sub_sub_sub_1_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_6) node _atomics_a_mask_sub_sub_sub_acc_T_13 = and(atomics_a_mask_sub_sub_sub_size_6, atomics_a_mask_sub_sub_sub_1_2_6) node atomics_a_mask_sub_sub_sub_1_1_6 = or(atomics_a_mask_sub_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_sub_acc_T_13) node atomics_a_mask_sub_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 2, 2) node atomics_a_mask_sub_sub_bit_6 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_6 = eq(atomics_a_mask_sub_sub_bit_6, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_6 = and(atomics_a_mask_sub_sub_sub_0_2_6, atomics_a_mask_sub_sub_nbit_6) node _atomics_a_mask_sub_sub_acc_T_24 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_0_2_6) node atomics_a_mask_sub_sub_0_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_24) node atomics_a_mask_sub_sub_1_2_6 = and(atomics_a_mask_sub_sub_sub_0_2_6, atomics_a_mask_sub_sub_bit_6) node _atomics_a_mask_sub_sub_acc_T_25 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_1_2_6) node atomics_a_mask_sub_sub_1_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_25) node atomics_a_mask_sub_sub_2_2_6 = and(atomics_a_mask_sub_sub_sub_1_2_6, atomics_a_mask_sub_sub_nbit_6) node _atomics_a_mask_sub_sub_acc_T_26 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_2_2_6) node atomics_a_mask_sub_sub_2_1_6 = or(atomics_a_mask_sub_sub_sub_1_1_6, _atomics_a_mask_sub_sub_acc_T_26) node atomics_a_mask_sub_sub_3_2_6 = and(atomics_a_mask_sub_sub_sub_1_2_6, atomics_a_mask_sub_sub_bit_6) node _atomics_a_mask_sub_sub_acc_T_27 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_3_2_6) node atomics_a_mask_sub_sub_3_1_6 = or(atomics_a_mask_sub_sub_sub_1_1_6, _atomics_a_mask_sub_sub_acc_T_27) node atomics_a_mask_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 1, 1) node atomics_a_mask_sub_bit_6 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_6 = eq(atomics_a_mask_sub_bit_6, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_nbit_6) node _atomics_a_mask_sub_acc_T_48 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_0_2_6) node atomics_a_mask_sub_0_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_48) node atomics_a_mask_sub_1_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_bit_6) node _atomics_a_mask_sub_acc_T_49 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_1_2_6) node atomics_a_mask_sub_1_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_49) node atomics_a_mask_sub_2_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_nbit_6) node _atomics_a_mask_sub_acc_T_50 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_2_2_6) node atomics_a_mask_sub_2_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_50) node atomics_a_mask_sub_3_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_bit_6) node _atomics_a_mask_sub_acc_T_51 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_3_2_6) node atomics_a_mask_sub_3_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_51) node atomics_a_mask_sub_4_2_6 = and(atomics_a_mask_sub_sub_2_2_6, atomics_a_mask_sub_nbit_6) node _atomics_a_mask_sub_acc_T_52 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_4_2_6) node atomics_a_mask_sub_4_1_6 = or(atomics_a_mask_sub_sub_2_1_6, _atomics_a_mask_sub_acc_T_52) node atomics_a_mask_sub_5_2_6 = and(atomics_a_mask_sub_sub_2_2_6, atomics_a_mask_sub_bit_6) node _atomics_a_mask_sub_acc_T_53 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_5_2_6) node atomics_a_mask_sub_5_1_6 = or(atomics_a_mask_sub_sub_2_1_6, _atomics_a_mask_sub_acc_T_53) node atomics_a_mask_sub_6_2_6 = and(atomics_a_mask_sub_sub_3_2_6, atomics_a_mask_sub_nbit_6) node _atomics_a_mask_sub_acc_T_54 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_6_2_6) node atomics_a_mask_sub_6_1_6 = or(atomics_a_mask_sub_sub_3_1_6, _atomics_a_mask_sub_acc_T_54) node atomics_a_mask_sub_7_2_6 = and(atomics_a_mask_sub_sub_3_2_6, atomics_a_mask_sub_bit_6) node _atomics_a_mask_sub_acc_T_55 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_7_2_6) node atomics_a_mask_sub_7_1_6 = or(atomics_a_mask_sub_sub_3_1_6, _atomics_a_mask_sub_acc_T_55) node atomics_a_mask_size_6 = bits(atomics_a_mask_sizeOH_6, 0, 0) node atomics_a_mask_bit_6 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_6 = eq(atomics_a_mask_bit_6, UInt<1>(0h0)) node atomics_a_mask_eq_96 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_96 = and(atomics_a_mask_size_6, atomics_a_mask_eq_96) node atomics_a_mask_acc_96 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_96) node atomics_a_mask_eq_97 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_97 = and(atomics_a_mask_size_6, atomics_a_mask_eq_97) node atomics_a_mask_acc_97 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_97) node atomics_a_mask_eq_98 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_98 = and(atomics_a_mask_size_6, atomics_a_mask_eq_98) node atomics_a_mask_acc_98 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_98) node atomics_a_mask_eq_99 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_99 = and(atomics_a_mask_size_6, atomics_a_mask_eq_99) node atomics_a_mask_acc_99 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_99) node atomics_a_mask_eq_100 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_100 = and(atomics_a_mask_size_6, atomics_a_mask_eq_100) node atomics_a_mask_acc_100 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_100) node atomics_a_mask_eq_101 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_101 = and(atomics_a_mask_size_6, atomics_a_mask_eq_101) node atomics_a_mask_acc_101 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_101) node atomics_a_mask_eq_102 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_102 = and(atomics_a_mask_size_6, atomics_a_mask_eq_102) node atomics_a_mask_acc_102 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_102) node atomics_a_mask_eq_103 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_103 = and(atomics_a_mask_size_6, atomics_a_mask_eq_103) node atomics_a_mask_acc_103 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_103) node atomics_a_mask_eq_104 = and(atomics_a_mask_sub_4_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_104 = and(atomics_a_mask_size_6, atomics_a_mask_eq_104) node atomics_a_mask_acc_104 = or(atomics_a_mask_sub_4_1_6, _atomics_a_mask_acc_T_104) node atomics_a_mask_eq_105 = and(atomics_a_mask_sub_4_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_105 = and(atomics_a_mask_size_6, atomics_a_mask_eq_105) node atomics_a_mask_acc_105 = or(atomics_a_mask_sub_4_1_6, _atomics_a_mask_acc_T_105) node atomics_a_mask_eq_106 = and(atomics_a_mask_sub_5_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_106 = and(atomics_a_mask_size_6, atomics_a_mask_eq_106) node atomics_a_mask_acc_106 = or(atomics_a_mask_sub_5_1_6, _atomics_a_mask_acc_T_106) node atomics_a_mask_eq_107 = and(atomics_a_mask_sub_5_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_107 = and(atomics_a_mask_size_6, atomics_a_mask_eq_107) node atomics_a_mask_acc_107 = or(atomics_a_mask_sub_5_1_6, _atomics_a_mask_acc_T_107) node atomics_a_mask_eq_108 = and(atomics_a_mask_sub_6_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_108 = and(atomics_a_mask_size_6, atomics_a_mask_eq_108) node atomics_a_mask_acc_108 = or(atomics_a_mask_sub_6_1_6, _atomics_a_mask_acc_T_108) node atomics_a_mask_eq_109 = and(atomics_a_mask_sub_6_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_109 = and(atomics_a_mask_size_6, atomics_a_mask_eq_109) node atomics_a_mask_acc_109 = or(atomics_a_mask_sub_6_1_6, _atomics_a_mask_acc_T_109) node atomics_a_mask_eq_110 = and(atomics_a_mask_sub_7_2_6, atomics_a_mask_nbit_6) node _atomics_a_mask_acc_T_110 = and(atomics_a_mask_size_6, atomics_a_mask_eq_110) node atomics_a_mask_acc_110 = or(atomics_a_mask_sub_7_1_6, _atomics_a_mask_acc_T_110) node atomics_a_mask_eq_111 = and(atomics_a_mask_sub_7_2_6, atomics_a_mask_bit_6) node _atomics_a_mask_acc_T_111 = and(atomics_a_mask_size_6, atomics_a_mask_eq_111) node atomics_a_mask_acc_111 = or(atomics_a_mask_sub_7_1_6, _atomics_a_mask_acc_T_111) node atomics_a_mask_lo_lo_lo_6 = cat(atomics_a_mask_acc_97, atomics_a_mask_acc_96) node atomics_a_mask_lo_lo_hi_6 = cat(atomics_a_mask_acc_99, atomics_a_mask_acc_98) node atomics_a_mask_lo_lo_6 = cat(atomics_a_mask_lo_lo_hi_6, atomics_a_mask_lo_lo_lo_6) node atomics_a_mask_lo_hi_lo_6 = cat(atomics_a_mask_acc_101, atomics_a_mask_acc_100) node atomics_a_mask_lo_hi_hi_6 = cat(atomics_a_mask_acc_103, atomics_a_mask_acc_102) node atomics_a_mask_lo_hi_6 = cat(atomics_a_mask_lo_hi_hi_6, atomics_a_mask_lo_hi_lo_6) node atomics_a_mask_lo_6 = cat(atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6) node atomics_a_mask_hi_lo_lo_6 = cat(atomics_a_mask_acc_105, atomics_a_mask_acc_104) node atomics_a_mask_hi_lo_hi_6 = cat(atomics_a_mask_acc_107, atomics_a_mask_acc_106) node atomics_a_mask_hi_lo_6 = cat(atomics_a_mask_hi_lo_hi_6, atomics_a_mask_hi_lo_lo_6) node atomics_a_mask_hi_hi_lo_6 = cat(atomics_a_mask_acc_109, atomics_a_mask_acc_108) node atomics_a_mask_hi_hi_hi_6 = cat(atomics_a_mask_acc_111, atomics_a_mask_acc_110) node atomics_a_mask_hi_hi_6 = cat(atomics_a_mask_hi_hi_hi_6, atomics_a_mask_hi_hi_lo_6) node atomics_a_mask_hi_6 = cat(atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6) node _atomics_a_mask_T_6 = cat(atomics_a_mask_hi_6, atomics_a_mask_lo_6) connect atomics_a_6.mask, _atomics_a_mask_T_6 connect atomics_a_6.data, a_data connect atomics_a_6.corrupt, UInt<1>(0h0) node _atomics_legal_T_413 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_414 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_415 = and(_atomics_legal_T_413, _atomics_legal_T_414) node _atomics_legal_T_416 = or(UInt<1>(0h0), _atomics_legal_T_415) node _atomics_legal_T_417 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_418 = cvt(_atomics_legal_T_417) node _atomics_legal_T_419 = and(_atomics_legal_T_418, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_420 = asSInt(_atomics_legal_T_419) node _atomics_legal_T_421 = eq(_atomics_legal_T_420, asSInt(UInt<1>(0h0))) node _atomics_legal_T_422 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_423 = cvt(_atomics_legal_T_422) node _atomics_legal_T_424 = and(_atomics_legal_T_423, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_425 = asSInt(_atomics_legal_T_424) node _atomics_legal_T_426 = eq(_atomics_legal_T_425, asSInt(UInt<1>(0h0))) node _atomics_legal_T_427 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_428 = cvt(_atomics_legal_T_427) node _atomics_legal_T_429 = and(_atomics_legal_T_428, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_430 = asSInt(_atomics_legal_T_429) node _atomics_legal_T_431 = eq(_atomics_legal_T_430, asSInt(UInt<1>(0h0))) node _atomics_legal_T_432 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_433 = cvt(_atomics_legal_T_432) node _atomics_legal_T_434 = and(_atomics_legal_T_433, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_435 = asSInt(_atomics_legal_T_434) node _atomics_legal_T_436 = eq(_atomics_legal_T_435, asSInt(UInt<1>(0h0))) node _atomics_legal_T_437 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_438 = cvt(_atomics_legal_T_437) node _atomics_legal_T_439 = and(_atomics_legal_T_438, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_440 = asSInt(_atomics_legal_T_439) node _atomics_legal_T_441 = eq(_atomics_legal_T_440, asSInt(UInt<1>(0h0))) node _atomics_legal_T_442 = or(_atomics_legal_T_421, _atomics_legal_T_426) node _atomics_legal_T_443 = or(_atomics_legal_T_442, _atomics_legal_T_431) node _atomics_legal_T_444 = or(_atomics_legal_T_443, _atomics_legal_T_436) node _atomics_legal_T_445 = or(_atomics_legal_T_444, _atomics_legal_T_441) node _atomics_legal_T_446 = and(_atomics_legal_T_416, _atomics_legal_T_445) node _atomics_legal_T_447 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_448 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_449 = cvt(_atomics_legal_T_448) node _atomics_legal_T_450 = and(_atomics_legal_T_449, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_451 = asSInt(_atomics_legal_T_450) node _atomics_legal_T_452 = eq(_atomics_legal_T_451, asSInt(UInt<1>(0h0))) node _atomics_legal_T_453 = and(_atomics_legal_T_447, _atomics_legal_T_452) node _atomics_legal_T_454 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_455 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_456 = and(_atomics_legal_T_454, _atomics_legal_T_455) node _atomics_legal_T_457 = or(UInt<1>(0h0), _atomics_legal_T_456) node _atomics_legal_T_458 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_459 = cvt(_atomics_legal_T_458) node _atomics_legal_T_460 = and(_atomics_legal_T_459, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_461 = asSInt(_atomics_legal_T_460) node _atomics_legal_T_462 = eq(_atomics_legal_T_461, asSInt(UInt<1>(0h0))) node _atomics_legal_T_463 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_464 = cvt(_atomics_legal_T_463) node _atomics_legal_T_465 = and(_atomics_legal_T_464, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_466 = asSInt(_atomics_legal_T_465) node _atomics_legal_T_467 = eq(_atomics_legal_T_466, asSInt(UInt<1>(0h0))) node _atomics_legal_T_468 = or(_atomics_legal_T_462, _atomics_legal_T_467) node _atomics_legal_T_469 = and(_atomics_legal_T_457, _atomics_legal_T_468) node _atomics_legal_T_470 = or(UInt<1>(0h0), _atomics_legal_T_446) node _atomics_legal_T_471 = or(_atomics_legal_T_470, _atomics_legal_T_453) node atomics_legal_7 = or(_atomics_legal_T_471, _atomics_legal_T_469) wire atomics_a_7 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_7.opcode, UInt<2>(0h2) connect atomics_a_7.param, UInt<3>(0h2) connect atomics_a_7.size, req.uop.mem_size connect atomics_a_7.source, UInt<3>(0h5) connect atomics_a_7.address, req.addr node _atomics_a_mask_sizeOH_T_21 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_7 = bits(_atomics_a_mask_sizeOH_T_21, 1, 0) node _atomics_a_mask_sizeOH_T_22 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_7) node _atomics_a_mask_sizeOH_T_23 = bits(_atomics_a_mask_sizeOH_T_22, 3, 0) node atomics_a_mask_sizeOH_7 = or(_atomics_a_mask_sizeOH_T_23, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_7 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 3, 3) node atomics_a_mask_sub_sub_sub_bit_7 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_7 = eq(atomics_a_mask_sub_sub_sub_bit_7, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_7) node _atomics_a_mask_sub_sub_sub_acc_T_14 = and(atomics_a_mask_sub_sub_sub_size_7, atomics_a_mask_sub_sub_sub_0_2_7) node atomics_a_mask_sub_sub_sub_0_1_7 = or(atomics_a_mask_sub_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_sub_acc_T_14) node atomics_a_mask_sub_sub_sub_1_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_7) node _atomics_a_mask_sub_sub_sub_acc_T_15 = and(atomics_a_mask_sub_sub_sub_size_7, atomics_a_mask_sub_sub_sub_1_2_7) node atomics_a_mask_sub_sub_sub_1_1_7 = or(atomics_a_mask_sub_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_sub_acc_T_15) node atomics_a_mask_sub_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 2, 2) node atomics_a_mask_sub_sub_bit_7 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_7 = eq(atomics_a_mask_sub_sub_bit_7, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_7 = and(atomics_a_mask_sub_sub_sub_0_2_7, atomics_a_mask_sub_sub_nbit_7) node _atomics_a_mask_sub_sub_acc_T_28 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_0_2_7) node atomics_a_mask_sub_sub_0_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_28) node atomics_a_mask_sub_sub_1_2_7 = and(atomics_a_mask_sub_sub_sub_0_2_7, atomics_a_mask_sub_sub_bit_7) node _atomics_a_mask_sub_sub_acc_T_29 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_1_2_7) node atomics_a_mask_sub_sub_1_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_29) node atomics_a_mask_sub_sub_2_2_7 = and(atomics_a_mask_sub_sub_sub_1_2_7, atomics_a_mask_sub_sub_nbit_7) node _atomics_a_mask_sub_sub_acc_T_30 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_2_2_7) node atomics_a_mask_sub_sub_2_1_7 = or(atomics_a_mask_sub_sub_sub_1_1_7, _atomics_a_mask_sub_sub_acc_T_30) node atomics_a_mask_sub_sub_3_2_7 = and(atomics_a_mask_sub_sub_sub_1_2_7, atomics_a_mask_sub_sub_bit_7) node _atomics_a_mask_sub_sub_acc_T_31 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_3_2_7) node atomics_a_mask_sub_sub_3_1_7 = or(atomics_a_mask_sub_sub_sub_1_1_7, _atomics_a_mask_sub_sub_acc_T_31) node atomics_a_mask_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 1, 1) node atomics_a_mask_sub_bit_7 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_7 = eq(atomics_a_mask_sub_bit_7, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_nbit_7) node _atomics_a_mask_sub_acc_T_56 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_0_2_7) node atomics_a_mask_sub_0_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_56) node atomics_a_mask_sub_1_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_bit_7) node _atomics_a_mask_sub_acc_T_57 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_1_2_7) node atomics_a_mask_sub_1_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_57) node atomics_a_mask_sub_2_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_nbit_7) node _atomics_a_mask_sub_acc_T_58 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_2_2_7) node atomics_a_mask_sub_2_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_58) node atomics_a_mask_sub_3_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_bit_7) node _atomics_a_mask_sub_acc_T_59 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_3_2_7) node atomics_a_mask_sub_3_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_59) node atomics_a_mask_sub_4_2_7 = and(atomics_a_mask_sub_sub_2_2_7, atomics_a_mask_sub_nbit_7) node _atomics_a_mask_sub_acc_T_60 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_4_2_7) node atomics_a_mask_sub_4_1_7 = or(atomics_a_mask_sub_sub_2_1_7, _atomics_a_mask_sub_acc_T_60) node atomics_a_mask_sub_5_2_7 = and(atomics_a_mask_sub_sub_2_2_7, atomics_a_mask_sub_bit_7) node _atomics_a_mask_sub_acc_T_61 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_5_2_7) node atomics_a_mask_sub_5_1_7 = or(atomics_a_mask_sub_sub_2_1_7, _atomics_a_mask_sub_acc_T_61) node atomics_a_mask_sub_6_2_7 = and(atomics_a_mask_sub_sub_3_2_7, atomics_a_mask_sub_nbit_7) node _atomics_a_mask_sub_acc_T_62 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_6_2_7) node atomics_a_mask_sub_6_1_7 = or(atomics_a_mask_sub_sub_3_1_7, _atomics_a_mask_sub_acc_T_62) node atomics_a_mask_sub_7_2_7 = and(atomics_a_mask_sub_sub_3_2_7, atomics_a_mask_sub_bit_7) node _atomics_a_mask_sub_acc_T_63 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_7_2_7) node atomics_a_mask_sub_7_1_7 = or(atomics_a_mask_sub_sub_3_1_7, _atomics_a_mask_sub_acc_T_63) node atomics_a_mask_size_7 = bits(atomics_a_mask_sizeOH_7, 0, 0) node atomics_a_mask_bit_7 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_7 = eq(atomics_a_mask_bit_7, UInt<1>(0h0)) node atomics_a_mask_eq_112 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_112 = and(atomics_a_mask_size_7, atomics_a_mask_eq_112) node atomics_a_mask_acc_112 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_112) node atomics_a_mask_eq_113 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_113 = and(atomics_a_mask_size_7, atomics_a_mask_eq_113) node atomics_a_mask_acc_113 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_113) node atomics_a_mask_eq_114 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_114 = and(atomics_a_mask_size_7, atomics_a_mask_eq_114) node atomics_a_mask_acc_114 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_114) node atomics_a_mask_eq_115 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_115 = and(atomics_a_mask_size_7, atomics_a_mask_eq_115) node atomics_a_mask_acc_115 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_115) node atomics_a_mask_eq_116 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_116 = and(atomics_a_mask_size_7, atomics_a_mask_eq_116) node atomics_a_mask_acc_116 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_116) node atomics_a_mask_eq_117 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_117 = and(atomics_a_mask_size_7, atomics_a_mask_eq_117) node atomics_a_mask_acc_117 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_117) node atomics_a_mask_eq_118 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_118 = and(atomics_a_mask_size_7, atomics_a_mask_eq_118) node atomics_a_mask_acc_118 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_118) node atomics_a_mask_eq_119 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_119 = and(atomics_a_mask_size_7, atomics_a_mask_eq_119) node atomics_a_mask_acc_119 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_119) node atomics_a_mask_eq_120 = and(atomics_a_mask_sub_4_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_120 = and(atomics_a_mask_size_7, atomics_a_mask_eq_120) node atomics_a_mask_acc_120 = or(atomics_a_mask_sub_4_1_7, _atomics_a_mask_acc_T_120) node atomics_a_mask_eq_121 = and(atomics_a_mask_sub_4_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_121 = and(atomics_a_mask_size_7, atomics_a_mask_eq_121) node atomics_a_mask_acc_121 = or(atomics_a_mask_sub_4_1_7, _atomics_a_mask_acc_T_121) node atomics_a_mask_eq_122 = and(atomics_a_mask_sub_5_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_122 = and(atomics_a_mask_size_7, atomics_a_mask_eq_122) node atomics_a_mask_acc_122 = or(atomics_a_mask_sub_5_1_7, _atomics_a_mask_acc_T_122) node atomics_a_mask_eq_123 = and(atomics_a_mask_sub_5_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_123 = and(atomics_a_mask_size_7, atomics_a_mask_eq_123) node atomics_a_mask_acc_123 = or(atomics_a_mask_sub_5_1_7, _atomics_a_mask_acc_T_123) node atomics_a_mask_eq_124 = and(atomics_a_mask_sub_6_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_124 = and(atomics_a_mask_size_7, atomics_a_mask_eq_124) node atomics_a_mask_acc_124 = or(atomics_a_mask_sub_6_1_7, _atomics_a_mask_acc_T_124) node atomics_a_mask_eq_125 = and(atomics_a_mask_sub_6_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_125 = and(atomics_a_mask_size_7, atomics_a_mask_eq_125) node atomics_a_mask_acc_125 = or(atomics_a_mask_sub_6_1_7, _atomics_a_mask_acc_T_125) node atomics_a_mask_eq_126 = and(atomics_a_mask_sub_7_2_7, atomics_a_mask_nbit_7) node _atomics_a_mask_acc_T_126 = and(atomics_a_mask_size_7, atomics_a_mask_eq_126) node atomics_a_mask_acc_126 = or(atomics_a_mask_sub_7_1_7, _atomics_a_mask_acc_T_126) node atomics_a_mask_eq_127 = and(atomics_a_mask_sub_7_2_7, atomics_a_mask_bit_7) node _atomics_a_mask_acc_T_127 = and(atomics_a_mask_size_7, atomics_a_mask_eq_127) node atomics_a_mask_acc_127 = or(atomics_a_mask_sub_7_1_7, _atomics_a_mask_acc_T_127) node atomics_a_mask_lo_lo_lo_7 = cat(atomics_a_mask_acc_113, atomics_a_mask_acc_112) node atomics_a_mask_lo_lo_hi_7 = cat(atomics_a_mask_acc_115, atomics_a_mask_acc_114) node atomics_a_mask_lo_lo_7 = cat(atomics_a_mask_lo_lo_hi_7, atomics_a_mask_lo_lo_lo_7) node atomics_a_mask_lo_hi_lo_7 = cat(atomics_a_mask_acc_117, atomics_a_mask_acc_116) node atomics_a_mask_lo_hi_hi_7 = cat(atomics_a_mask_acc_119, atomics_a_mask_acc_118) node atomics_a_mask_lo_hi_7 = cat(atomics_a_mask_lo_hi_hi_7, atomics_a_mask_lo_hi_lo_7) node atomics_a_mask_lo_7 = cat(atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7) node atomics_a_mask_hi_lo_lo_7 = cat(atomics_a_mask_acc_121, atomics_a_mask_acc_120) node atomics_a_mask_hi_lo_hi_7 = cat(atomics_a_mask_acc_123, atomics_a_mask_acc_122) node atomics_a_mask_hi_lo_7 = cat(atomics_a_mask_hi_lo_hi_7, atomics_a_mask_hi_lo_lo_7) node atomics_a_mask_hi_hi_lo_7 = cat(atomics_a_mask_acc_125, atomics_a_mask_acc_124) node atomics_a_mask_hi_hi_hi_7 = cat(atomics_a_mask_acc_127, atomics_a_mask_acc_126) node atomics_a_mask_hi_hi_7 = cat(atomics_a_mask_hi_hi_hi_7, atomics_a_mask_hi_hi_lo_7) node atomics_a_mask_hi_7 = cat(atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7) node _atomics_a_mask_T_7 = cat(atomics_a_mask_hi_7, atomics_a_mask_lo_7) connect atomics_a_7.mask, _atomics_a_mask_T_7 connect atomics_a_7.data, a_data connect atomics_a_7.corrupt, UInt<1>(0h0) node _atomics_legal_T_472 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_473 = leq(req.uop.mem_size, UInt<2>(0h3)) node _atomics_legal_T_474 = and(_atomics_legal_T_472, _atomics_legal_T_473) node _atomics_legal_T_475 = or(UInt<1>(0h0), _atomics_legal_T_474) node _atomics_legal_T_476 = xor(req.addr, UInt<1>(0h0)) node _atomics_legal_T_477 = cvt(_atomics_legal_T_476) node _atomics_legal_T_478 = and(_atomics_legal_T_477, asSInt(UInt<33>(0h9c110000))) node _atomics_legal_T_479 = asSInt(_atomics_legal_T_478) node _atomics_legal_T_480 = eq(_atomics_legal_T_479, asSInt(UInt<1>(0h0))) node _atomics_legal_T_481 = xor(req.addr, UInt<21>(0h100000)) node _atomics_legal_T_482 = cvt(_atomics_legal_T_481) node _atomics_legal_T_483 = and(_atomics_legal_T_482, asSInt(UInt<33>(0h9e101000))) node _atomics_legal_T_484 = asSInt(_atomics_legal_T_483) node _atomics_legal_T_485 = eq(_atomics_legal_T_484, asSInt(UInt<1>(0h0))) node _atomics_legal_T_486 = xor(req.addr, UInt<26>(0h2010000)) node _atomics_legal_T_487 = cvt(_atomics_legal_T_486) node _atomics_legal_T_488 = and(_atomics_legal_T_487, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_489 = asSInt(_atomics_legal_T_488) node _atomics_legal_T_490 = eq(_atomics_legal_T_489, asSInt(UInt<1>(0h0))) node _atomics_legal_T_491 = xor(req.addr, UInt<28>(0hc000000)) node _atomics_legal_T_492 = cvt(_atomics_legal_T_491) node _atomics_legal_T_493 = and(_atomics_legal_T_492, asSInt(UInt<33>(0h9c000000))) node _atomics_legal_T_494 = asSInt(_atomics_legal_T_493) node _atomics_legal_T_495 = eq(_atomics_legal_T_494, asSInt(UInt<1>(0h0))) node _atomics_legal_T_496 = xor(req.addr, UInt<29>(0h10000000)) node _atomics_legal_T_497 = cvt(_atomics_legal_T_496) node _atomics_legal_T_498 = and(_atomics_legal_T_497, asSInt(UInt<33>(0h9e111000))) node _atomics_legal_T_499 = asSInt(_atomics_legal_T_498) node _atomics_legal_T_500 = eq(_atomics_legal_T_499, asSInt(UInt<1>(0h0))) node _atomics_legal_T_501 = or(_atomics_legal_T_480, _atomics_legal_T_485) node _atomics_legal_T_502 = or(_atomics_legal_T_501, _atomics_legal_T_490) node _atomics_legal_T_503 = or(_atomics_legal_T_502, _atomics_legal_T_495) node _atomics_legal_T_504 = or(_atomics_legal_T_503, _atomics_legal_T_500) node _atomics_legal_T_505 = and(_atomics_legal_T_475, _atomics_legal_T_504) node _atomics_legal_T_506 = or(UInt<1>(0h0), UInt<1>(0h0)) node _atomics_legal_T_507 = xor(req.addr, UInt<17>(0h10000)) node _atomics_legal_T_508 = cvt(_atomics_legal_T_507) node _atomics_legal_T_509 = and(_atomics_legal_T_508, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_510 = asSInt(_atomics_legal_T_509) node _atomics_legal_T_511 = eq(_atomics_legal_T_510, asSInt(UInt<1>(0h0))) node _atomics_legal_T_512 = and(_atomics_legal_T_506, _atomics_legal_T_511) node _atomics_legal_T_513 = leq(UInt<1>(0h0), req.uop.mem_size) node _atomics_legal_T_514 = leq(req.uop.mem_size, UInt<3>(0h4)) node _atomics_legal_T_515 = and(_atomics_legal_T_513, _atomics_legal_T_514) node _atomics_legal_T_516 = or(UInt<1>(0h0), _atomics_legal_T_515) node _atomics_legal_T_517 = xor(req.addr, UInt<28>(0h8000000)) node _atomics_legal_T_518 = cvt(_atomics_legal_T_517) node _atomics_legal_T_519 = and(_atomics_legal_T_518, asSInt(UInt<33>(0h9e110000))) node _atomics_legal_T_520 = asSInt(_atomics_legal_T_519) node _atomics_legal_T_521 = eq(_atomics_legal_T_520, asSInt(UInt<1>(0h0))) node _atomics_legal_T_522 = xor(req.addr, UInt<32>(0h80000000)) node _atomics_legal_T_523 = cvt(_atomics_legal_T_522) node _atomics_legal_T_524 = and(_atomics_legal_T_523, asSInt(UInt<33>(0h90000000))) node _atomics_legal_T_525 = asSInt(_atomics_legal_T_524) node _atomics_legal_T_526 = eq(_atomics_legal_T_525, asSInt(UInt<1>(0h0))) node _atomics_legal_T_527 = or(_atomics_legal_T_521, _atomics_legal_T_526) node _atomics_legal_T_528 = and(_atomics_legal_T_516, _atomics_legal_T_527) node _atomics_legal_T_529 = or(UInt<1>(0h0), _atomics_legal_T_505) node _atomics_legal_T_530 = or(_atomics_legal_T_529, _atomics_legal_T_512) node atomics_legal_8 = or(_atomics_legal_T_530, _atomics_legal_T_528) wire atomics_a_8 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect atomics_a_8.opcode, UInt<2>(0h2) connect atomics_a_8.param, UInt<3>(0h3) connect atomics_a_8.size, req.uop.mem_size connect atomics_a_8.source, UInt<3>(0h5) connect atomics_a_8.address, req.addr node _atomics_a_mask_sizeOH_T_24 = or(req.uop.mem_size, UInt<4>(0h0)) node atomics_a_mask_sizeOH_shiftAmount_8 = bits(_atomics_a_mask_sizeOH_T_24, 1, 0) node _atomics_a_mask_sizeOH_T_25 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_8) node _atomics_a_mask_sizeOH_T_26 = bits(_atomics_a_mask_sizeOH_T_25, 3, 0) node atomics_a_mask_sizeOH_8 = or(_atomics_a_mask_sizeOH_T_26, UInt<1>(0h1)) node atomics_a_mask_sub_sub_sub_sub_0_1_8 = geq(req.uop.mem_size, UInt<3>(0h4)) node atomics_a_mask_sub_sub_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 3, 3) node atomics_a_mask_sub_sub_sub_bit_8 = bits(req.addr, 3, 3) node atomics_a_mask_sub_sub_sub_nbit_8 = eq(atomics_a_mask_sub_sub_sub_bit_8, UInt<1>(0h0)) node atomics_a_mask_sub_sub_sub_0_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_nbit_8) node _atomics_a_mask_sub_sub_sub_acc_T_16 = and(atomics_a_mask_sub_sub_sub_size_8, atomics_a_mask_sub_sub_sub_0_2_8) node atomics_a_mask_sub_sub_sub_0_1_8 = or(atomics_a_mask_sub_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_sub_acc_T_16) node atomics_a_mask_sub_sub_sub_1_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_sub_bit_8) node _atomics_a_mask_sub_sub_sub_acc_T_17 = and(atomics_a_mask_sub_sub_sub_size_8, atomics_a_mask_sub_sub_sub_1_2_8) node atomics_a_mask_sub_sub_sub_1_1_8 = or(atomics_a_mask_sub_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_sub_acc_T_17) node atomics_a_mask_sub_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 2, 2) node atomics_a_mask_sub_sub_bit_8 = bits(req.addr, 2, 2) node atomics_a_mask_sub_sub_nbit_8 = eq(atomics_a_mask_sub_sub_bit_8, UInt<1>(0h0)) node atomics_a_mask_sub_sub_0_2_8 = and(atomics_a_mask_sub_sub_sub_0_2_8, atomics_a_mask_sub_sub_nbit_8) node _atomics_a_mask_sub_sub_acc_T_32 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_0_2_8) node atomics_a_mask_sub_sub_0_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_32) node atomics_a_mask_sub_sub_1_2_8 = and(atomics_a_mask_sub_sub_sub_0_2_8, atomics_a_mask_sub_sub_bit_8) node _atomics_a_mask_sub_sub_acc_T_33 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_1_2_8) node atomics_a_mask_sub_sub_1_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_33) node atomics_a_mask_sub_sub_2_2_8 = and(atomics_a_mask_sub_sub_sub_1_2_8, atomics_a_mask_sub_sub_nbit_8) node _atomics_a_mask_sub_sub_acc_T_34 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_2_2_8) node atomics_a_mask_sub_sub_2_1_8 = or(atomics_a_mask_sub_sub_sub_1_1_8, _atomics_a_mask_sub_sub_acc_T_34) node atomics_a_mask_sub_sub_3_2_8 = and(atomics_a_mask_sub_sub_sub_1_2_8, atomics_a_mask_sub_sub_bit_8) node _atomics_a_mask_sub_sub_acc_T_35 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_3_2_8) node atomics_a_mask_sub_sub_3_1_8 = or(atomics_a_mask_sub_sub_sub_1_1_8, _atomics_a_mask_sub_sub_acc_T_35) node atomics_a_mask_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 1, 1) node atomics_a_mask_sub_bit_8 = bits(req.addr, 1, 1) node atomics_a_mask_sub_nbit_8 = eq(atomics_a_mask_sub_bit_8, UInt<1>(0h0)) node atomics_a_mask_sub_0_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_nbit_8) node _atomics_a_mask_sub_acc_T_64 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_0_2_8) node atomics_a_mask_sub_0_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_64) node atomics_a_mask_sub_1_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_bit_8) node _atomics_a_mask_sub_acc_T_65 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_1_2_8) node atomics_a_mask_sub_1_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_65) node atomics_a_mask_sub_2_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_nbit_8) node _atomics_a_mask_sub_acc_T_66 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_2_2_8) node atomics_a_mask_sub_2_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_66) node atomics_a_mask_sub_3_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_bit_8) node _atomics_a_mask_sub_acc_T_67 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_3_2_8) node atomics_a_mask_sub_3_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_67) node atomics_a_mask_sub_4_2_8 = and(atomics_a_mask_sub_sub_2_2_8, atomics_a_mask_sub_nbit_8) node _atomics_a_mask_sub_acc_T_68 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_4_2_8) node atomics_a_mask_sub_4_1_8 = or(atomics_a_mask_sub_sub_2_1_8, _atomics_a_mask_sub_acc_T_68) node atomics_a_mask_sub_5_2_8 = and(atomics_a_mask_sub_sub_2_2_8, atomics_a_mask_sub_bit_8) node _atomics_a_mask_sub_acc_T_69 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_5_2_8) node atomics_a_mask_sub_5_1_8 = or(atomics_a_mask_sub_sub_2_1_8, _atomics_a_mask_sub_acc_T_69) node atomics_a_mask_sub_6_2_8 = and(atomics_a_mask_sub_sub_3_2_8, atomics_a_mask_sub_nbit_8) node _atomics_a_mask_sub_acc_T_70 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_6_2_8) node atomics_a_mask_sub_6_1_8 = or(atomics_a_mask_sub_sub_3_1_8, _atomics_a_mask_sub_acc_T_70) node atomics_a_mask_sub_7_2_8 = and(atomics_a_mask_sub_sub_3_2_8, atomics_a_mask_sub_bit_8) node _atomics_a_mask_sub_acc_T_71 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_7_2_8) node atomics_a_mask_sub_7_1_8 = or(atomics_a_mask_sub_sub_3_1_8, _atomics_a_mask_sub_acc_T_71) node atomics_a_mask_size_8 = bits(atomics_a_mask_sizeOH_8, 0, 0) node atomics_a_mask_bit_8 = bits(req.addr, 0, 0) node atomics_a_mask_nbit_8 = eq(atomics_a_mask_bit_8, UInt<1>(0h0)) node atomics_a_mask_eq_128 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_128 = and(atomics_a_mask_size_8, atomics_a_mask_eq_128) node atomics_a_mask_acc_128 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_128) node atomics_a_mask_eq_129 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_129 = and(atomics_a_mask_size_8, atomics_a_mask_eq_129) node atomics_a_mask_acc_129 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_129) node atomics_a_mask_eq_130 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_130 = and(atomics_a_mask_size_8, atomics_a_mask_eq_130) node atomics_a_mask_acc_130 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_130) node atomics_a_mask_eq_131 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_131 = and(atomics_a_mask_size_8, atomics_a_mask_eq_131) node atomics_a_mask_acc_131 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_131) node atomics_a_mask_eq_132 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_132 = and(atomics_a_mask_size_8, atomics_a_mask_eq_132) node atomics_a_mask_acc_132 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_132) node atomics_a_mask_eq_133 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_133 = and(atomics_a_mask_size_8, atomics_a_mask_eq_133) node atomics_a_mask_acc_133 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_133) node atomics_a_mask_eq_134 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_134 = and(atomics_a_mask_size_8, atomics_a_mask_eq_134) node atomics_a_mask_acc_134 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_134) node atomics_a_mask_eq_135 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_135 = and(atomics_a_mask_size_8, atomics_a_mask_eq_135) node atomics_a_mask_acc_135 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_135) node atomics_a_mask_eq_136 = and(atomics_a_mask_sub_4_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_136 = and(atomics_a_mask_size_8, atomics_a_mask_eq_136) node atomics_a_mask_acc_136 = or(atomics_a_mask_sub_4_1_8, _atomics_a_mask_acc_T_136) node atomics_a_mask_eq_137 = and(atomics_a_mask_sub_4_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_137 = and(atomics_a_mask_size_8, atomics_a_mask_eq_137) node atomics_a_mask_acc_137 = or(atomics_a_mask_sub_4_1_8, _atomics_a_mask_acc_T_137) node atomics_a_mask_eq_138 = and(atomics_a_mask_sub_5_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_138 = and(atomics_a_mask_size_8, atomics_a_mask_eq_138) node atomics_a_mask_acc_138 = or(atomics_a_mask_sub_5_1_8, _atomics_a_mask_acc_T_138) node atomics_a_mask_eq_139 = and(atomics_a_mask_sub_5_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_139 = and(atomics_a_mask_size_8, atomics_a_mask_eq_139) node atomics_a_mask_acc_139 = or(atomics_a_mask_sub_5_1_8, _atomics_a_mask_acc_T_139) node atomics_a_mask_eq_140 = and(atomics_a_mask_sub_6_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_140 = and(atomics_a_mask_size_8, atomics_a_mask_eq_140) node atomics_a_mask_acc_140 = or(atomics_a_mask_sub_6_1_8, _atomics_a_mask_acc_T_140) node atomics_a_mask_eq_141 = and(atomics_a_mask_sub_6_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_141 = and(atomics_a_mask_size_8, atomics_a_mask_eq_141) node atomics_a_mask_acc_141 = or(atomics_a_mask_sub_6_1_8, _atomics_a_mask_acc_T_141) node atomics_a_mask_eq_142 = and(atomics_a_mask_sub_7_2_8, atomics_a_mask_nbit_8) node _atomics_a_mask_acc_T_142 = and(atomics_a_mask_size_8, atomics_a_mask_eq_142) node atomics_a_mask_acc_142 = or(atomics_a_mask_sub_7_1_8, _atomics_a_mask_acc_T_142) node atomics_a_mask_eq_143 = and(atomics_a_mask_sub_7_2_8, atomics_a_mask_bit_8) node _atomics_a_mask_acc_T_143 = and(atomics_a_mask_size_8, atomics_a_mask_eq_143) node atomics_a_mask_acc_143 = or(atomics_a_mask_sub_7_1_8, _atomics_a_mask_acc_T_143) node atomics_a_mask_lo_lo_lo_8 = cat(atomics_a_mask_acc_129, atomics_a_mask_acc_128) node atomics_a_mask_lo_lo_hi_8 = cat(atomics_a_mask_acc_131, atomics_a_mask_acc_130) node atomics_a_mask_lo_lo_8 = cat(atomics_a_mask_lo_lo_hi_8, atomics_a_mask_lo_lo_lo_8) node atomics_a_mask_lo_hi_lo_8 = cat(atomics_a_mask_acc_133, atomics_a_mask_acc_132) node atomics_a_mask_lo_hi_hi_8 = cat(atomics_a_mask_acc_135, atomics_a_mask_acc_134) node atomics_a_mask_lo_hi_8 = cat(atomics_a_mask_lo_hi_hi_8, atomics_a_mask_lo_hi_lo_8) node atomics_a_mask_lo_8 = cat(atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8) node atomics_a_mask_hi_lo_lo_8 = cat(atomics_a_mask_acc_137, atomics_a_mask_acc_136) node atomics_a_mask_hi_lo_hi_8 = cat(atomics_a_mask_acc_139, atomics_a_mask_acc_138) node atomics_a_mask_hi_lo_8 = cat(atomics_a_mask_hi_lo_hi_8, atomics_a_mask_hi_lo_lo_8) node atomics_a_mask_hi_hi_lo_8 = cat(atomics_a_mask_acc_141, atomics_a_mask_acc_140) node atomics_a_mask_hi_hi_hi_8 = cat(atomics_a_mask_acc_143, atomics_a_mask_acc_142) node atomics_a_mask_hi_hi_8 = cat(atomics_a_mask_hi_hi_hi_8, atomics_a_mask_hi_hi_lo_8) node atomics_a_mask_hi_8 = cat(atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8) node _atomics_a_mask_T_8 = cat(atomics_a_mask_hi_8, atomics_a_mask_lo_8) connect atomics_a_8.mask, _atomics_a_mask_T_8 connect atomics_a_8.data, a_data connect atomics_a_8.corrupt, UInt<1>(0h0) node _atomics_T = eq(UInt<3>(0h4), req.uop.mem_cmd) node _atomics_T_1 = mux(_atomics_T, atomics_a, _atomics_WIRE) node _atomics_T_2 = eq(UInt<4>(0h9), req.uop.mem_cmd) node _atomics_T_3 = mux(_atomics_T_2, atomics_a_1, _atomics_T_1) node _atomics_T_4 = eq(UInt<4>(0ha), req.uop.mem_cmd) node _atomics_T_5 = mux(_atomics_T_4, atomics_a_2, _atomics_T_3) node _atomics_T_6 = eq(UInt<4>(0hb), req.uop.mem_cmd) node _atomics_T_7 = mux(_atomics_T_6, atomics_a_3, _atomics_T_5) node _atomics_T_8 = eq(UInt<4>(0h8), req.uop.mem_cmd) node _atomics_T_9 = mux(_atomics_T_8, atomics_a_4, _atomics_T_7) node _atomics_T_10 = eq(UInt<4>(0hc), req.uop.mem_cmd) node _atomics_T_11 = mux(_atomics_T_10, atomics_a_5, _atomics_T_9) node _atomics_T_12 = eq(UInt<4>(0hd), req.uop.mem_cmd) node _atomics_T_13 = mux(_atomics_T_12, atomics_a_6, _atomics_T_11) node _atomics_T_14 = eq(UInt<4>(0he), req.uop.mem_cmd) node _atomics_T_15 = mux(_atomics_T_14, atomics_a_7, _atomics_T_13) node _atomics_T_16 = eq(UInt<4>(0hf), req.uop.mem_cmd) node atomics = mux(_atomics_T_16, atomics_a_8, _atomics_T_15) node _T = eq(state, UInt<2>(0h0)) node _T_1 = neq(req.uop.mem_cmd, UInt<3>(0h7)) node _T_2 = or(_T, _T_1) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:454 assert(state === s_idle || req.uop.mem_cmd =/= M_XSC)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_mem_access_valid_T = eq(state, UInt<2>(0h1)) connect io.mem_access.valid, _io_mem_access_valid_T node _io_mem_access_bits_T = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _io_mem_access_bits_T_1 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _io_mem_access_bits_T_2 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _io_mem_access_bits_T_3 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _io_mem_access_bits_T_4 = or(_io_mem_access_bits_T, _io_mem_access_bits_T_1) node _io_mem_access_bits_T_5 = or(_io_mem_access_bits_T_4, _io_mem_access_bits_T_2) node _io_mem_access_bits_T_6 = or(_io_mem_access_bits_T_5, _io_mem_access_bits_T_3) node _io_mem_access_bits_T_7 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _io_mem_access_bits_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _io_mem_access_bits_T_9 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _io_mem_access_bits_T_10 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _io_mem_access_bits_T_11 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _io_mem_access_bits_T_12 = or(_io_mem_access_bits_T_7, _io_mem_access_bits_T_8) node _io_mem_access_bits_T_13 = or(_io_mem_access_bits_T_12, _io_mem_access_bits_T_9) node _io_mem_access_bits_T_14 = or(_io_mem_access_bits_T_13, _io_mem_access_bits_T_10) node _io_mem_access_bits_T_15 = or(_io_mem_access_bits_T_14, _io_mem_access_bits_T_11) node _io_mem_access_bits_T_16 = or(_io_mem_access_bits_T_6, _io_mem_access_bits_T_15) node _io_mem_access_bits_T_17 = eq(req.uop.mem_cmd, UInt<1>(0h0)) node _io_mem_access_bits_T_18 = eq(req.uop.mem_cmd, UInt<5>(0h10)) node _io_mem_access_bits_T_19 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _io_mem_access_bits_T_20 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _io_mem_access_bits_T_21 = or(_io_mem_access_bits_T_17, _io_mem_access_bits_T_18) node _io_mem_access_bits_T_22 = or(_io_mem_access_bits_T_21, _io_mem_access_bits_T_19) node _io_mem_access_bits_T_23 = or(_io_mem_access_bits_T_22, _io_mem_access_bits_T_20) node _io_mem_access_bits_T_24 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _io_mem_access_bits_T_25 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _io_mem_access_bits_T_26 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _io_mem_access_bits_T_27 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _io_mem_access_bits_T_28 = or(_io_mem_access_bits_T_24, _io_mem_access_bits_T_25) node _io_mem_access_bits_T_29 = or(_io_mem_access_bits_T_28, _io_mem_access_bits_T_26) node _io_mem_access_bits_T_30 = or(_io_mem_access_bits_T_29, _io_mem_access_bits_T_27) node _io_mem_access_bits_T_31 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _io_mem_access_bits_T_32 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _io_mem_access_bits_T_33 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _io_mem_access_bits_T_34 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _io_mem_access_bits_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _io_mem_access_bits_T_36 = or(_io_mem_access_bits_T_31, _io_mem_access_bits_T_32) node _io_mem_access_bits_T_37 = or(_io_mem_access_bits_T_36, _io_mem_access_bits_T_33) node _io_mem_access_bits_T_38 = or(_io_mem_access_bits_T_37, _io_mem_access_bits_T_34) node _io_mem_access_bits_T_39 = or(_io_mem_access_bits_T_38, _io_mem_access_bits_T_35) node _io_mem_access_bits_T_40 = or(_io_mem_access_bits_T_30, _io_mem_access_bits_T_39) node _io_mem_access_bits_T_41 = or(_io_mem_access_bits_T_23, _io_mem_access_bits_T_40) node _io_mem_access_bits_T_42 = mux(_io_mem_access_bits_T_41, get, put) node _io_mem_access_bits_T_43 = mux(_io_mem_access_bits_T_16, atomics, _io_mem_access_bits_T_42) connect io.mem_access.bits, _io_mem_access_bits_T_43 node _send_resp_T = eq(req.uop.mem_cmd, UInt<1>(0h0)) node _send_resp_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h10)) node _send_resp_T_2 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _send_resp_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _send_resp_T_4 = or(_send_resp_T, _send_resp_T_1) node _send_resp_T_5 = or(_send_resp_T_4, _send_resp_T_2) node _send_resp_T_6 = or(_send_resp_T_5, _send_resp_T_3) node _send_resp_T_7 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _send_resp_T_8 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _send_resp_T_9 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _send_resp_T_10 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _send_resp_T_11 = or(_send_resp_T_7, _send_resp_T_8) node _send_resp_T_12 = or(_send_resp_T_11, _send_resp_T_9) node _send_resp_T_13 = or(_send_resp_T_12, _send_resp_T_10) node _send_resp_T_14 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _send_resp_T_15 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _send_resp_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _send_resp_T_17 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _send_resp_T_18 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _send_resp_T_19 = or(_send_resp_T_14, _send_resp_T_15) node _send_resp_T_20 = or(_send_resp_T_19, _send_resp_T_16) node _send_resp_T_21 = or(_send_resp_T_20, _send_resp_T_17) node _send_resp_T_22 = or(_send_resp_T_21, _send_resp_T_18) node _send_resp_T_23 = or(_send_resp_T_13, _send_resp_T_22) node send_resp = or(_send_resp_T_6, _send_resp_T_23) node _io_resp_valid_T = eq(state, UInt<2>(0h3)) node _io_resp_valid_T_1 = and(_io_resp_valid_T, send_resp) connect io.resp.valid, _io_resp_valid_T_1 connect io.resp.bits.is_hella, req.is_hella connect io.resp.bits.uop, req.uop node _io_resp_bits_data_shifted_T = bits(req.addr, 2, 2) node _io_resp_bits_data_shifted_T_1 = bits(grant_word, 63, 32) node _io_resp_bits_data_shifted_T_2 = bits(grant_word, 31, 0) node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2) node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted) node _io_resp_bits_data_T = eq(size, UInt<2>(0h2)) node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero) node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31) node _io_resp_bits_data_T_3 = and(req.uop.mem_signed, _io_resp_bits_data_T_2) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_resp_bits_data_T_5 = bits(grant_word, 63, 32) node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5) node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed) node _io_resp_bits_data_shifted_T_3 = bits(req.addr, 1, 1) node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16) node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0) node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5) node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1) node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1) node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15) node _io_resp_bits_data_T_11 = and(req.uop.mem_signed, _io_resp_bits_data_T_10) node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16) node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13) node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1) node _io_resp_bits_data_shifted_T_6 = bits(req.addr, 0, 0) node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8) node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0) node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8) node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2) node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2) node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7) node _io_resp_bits_data_T_19 = and(req.uop.mem_signed, _io_resp_bits_data_T_18) node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8) node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21) node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2) connect io.resp.bits.data, _io_resp_bits_data_T_23 node _T_6 = and(io.req.ready, io.req.valid) when _T_6 : connect req, io.req.bits connect state, UInt<2>(0h1) node _T_7 = and(io.mem_access.ready, io.mem_access.valid) when _T_7 : connect state, UInt<2>(0h2) node _T_8 = eq(state, UInt<2>(0h2)) node _T_9 = and(_T_8, io.mem_ack.valid) when _T_9 : connect state, UInt<2>(0h3) node _T_10 = eq(req.uop.mem_cmd, UInt<1>(0h0)) node _T_11 = eq(req.uop.mem_cmd, UInt<5>(0h10)) node _T_12 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _T_13 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _T_14 = or(_T_10, _T_11) node _T_15 = or(_T_14, _T_12) node _T_16 = or(_T_15, _T_13) node _T_17 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _T_18 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _T_19 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _T_20 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _T_21 = or(_T_17, _T_18) node _T_22 = or(_T_21, _T_19) node _T_23 = or(_T_22, _T_20) node _T_24 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _T_25 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _T_26 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _T_27 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _T_28 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _T_29 = or(_T_24, _T_25) node _T_30 = or(_T_29, _T_26) node _T_31 = or(_T_30, _T_27) node _T_32 = or(_T_31, _T_28) node _T_33 = or(_T_23, _T_32) node _T_34 = or(_T_16, _T_33) when _T_34 : node _grant_word_shift_T = bits(req.addr, 3, 3) node grant_word_shift = cat(_grant_word_shift_T, UInt<6>(0h0)) node _grant_word_T = dshr(io.mem_ack.bits.data, grant_word_shift) node _grant_word_T_1 = bits(_grant_word_T, 63, 0) connect grant_word, _grant_word_T_1 node _T_35 = eq(state, UInt<2>(0h3)) when _T_35 : node _T_36 = eq(send_resp, UInt<1>(0h0)) node _T_37 = and(io.resp.ready, io.resp.valid) node _T_38 = or(_T_36, _T_37) when _T_38 : connect state, UInt<2>(0h0)

module BoomIOMSHR( // @[mshrs.scala:402:7] input clock, // @[mshrs.scala:402:7] input reset, // @[mshrs.scala:402:7] output io_req_ready, // @[mshrs.scala:405:14] input io_req_valid, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_uopc, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_inst, // @[mshrs.scala:405:14] input [31:0] io_req_bits_uop_debug_inst, // @[mshrs.scala:405:14] input io_req_bits_uop_is_rvc, // @[mshrs.scala:405:14] input [39:0] io_req_bits_uop_debug_pc, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_iq_type, // @[mshrs.scala:405:14] input [9:0] io_req_bits_uop_fu_code, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] input io_req_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_iw_state, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] input io_req_bits_uop_is_br, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jalr, // @[mshrs.scala:405:14] input io_req_bits_uop_is_jal, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sfb, // @[mshrs.scala:405:14] input [15:0] io_req_bits_uop_br_mask, // @[mshrs.scala:405:14] input [3:0] io_req_bits_uop_br_tag, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ftq_idx, // @[mshrs.scala:405:14] input io_req_bits_uop_edge_inst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_pc_lob, // @[mshrs.scala:405:14] input io_req_bits_uop_taken, // @[mshrs.scala:405:14] input [19:0] io_req_bits_uop_imm_packed, // @[mshrs.scala:405:14] input [11:0] io_req_bits_uop_csr_addr, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_rob_idx, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ldq_idx, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_stq_idx, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_rxq_idx, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_pdst, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs1, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs2, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_prs3, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_ppred, // @[mshrs.scala:405:14] input io_req_bits_uop_prs1_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs2_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_prs3_busy, // @[mshrs.scala:405:14] input io_req_bits_uop_ppred_busy, // @[mshrs.scala:405:14] input [6:0] io_req_bits_uop_stale_pdst, // @[mshrs.scala:405:14] input io_req_bits_uop_exception, // @[mshrs.scala:405:14] input [63:0] io_req_bits_uop_exc_cause, // @[mshrs.scala:405:14] input io_req_bits_uop_bypassable, // @[mshrs.scala:405:14] input [4:0] io_req_bits_uop_mem_cmd, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_mem_size, // @[mshrs.scala:405:14] input io_req_bits_uop_mem_signed, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fence, // @[mshrs.scala:405:14] input io_req_bits_uop_is_fencei, // @[mshrs.scala:405:14] input io_req_bits_uop_is_amo, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_ldq, // @[mshrs.scala:405:14] input io_req_bits_uop_uses_stq, // @[mshrs.scala:405:14] input io_req_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] input io_req_bits_uop_is_unique, // @[mshrs.scala:405:14] input io_req_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_ldst, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs1, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs2, // @[mshrs.scala:405:14] input [5:0] io_req_bits_uop_lrs3, // @[mshrs.scala:405:14] input io_req_bits_uop_ldst_val, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_dst_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] input io_req_bits_uop_frs3_en, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_val, // @[mshrs.scala:405:14] input io_req_bits_uop_fp_single, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] input io_req_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] input io_req_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] input [39:0] io_req_bits_addr, // @[mshrs.scala:405:14] input [63:0] io_req_bits_data, // @[mshrs.scala:405:14] input io_req_bits_is_hella, // @[mshrs.scala:405:14] input io_resp_ready, // @[mshrs.scala:405:14] output io_resp_valid, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:405:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:405:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:405:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:405:14] output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:405:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:405:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:405:14] output io_resp_bits_uop_taken, // @[mshrs.scala:405:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:405:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:405:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:405:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:405:14] output io_resp_bits_uop_exception, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:405:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:405:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:405:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:405:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:405:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:405:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:405:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:405:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:405:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:405:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:405:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:405:14] output io_resp_bits_is_hella, // @[mshrs.scala:405:14] input io_mem_access_ready, // @[mshrs.scala:405:14] output io_mem_access_valid, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_opcode, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_param, // @[mshrs.scala:405:14] output [3:0] io_mem_access_bits_size, // @[mshrs.scala:405:14] output [2:0] io_mem_access_bits_source, // @[mshrs.scala:405:14] output [31:0] io_mem_access_bits_address, // @[mshrs.scala:405:14] output [15:0] io_mem_access_bits_mask, // @[mshrs.scala:405:14] output [127:0] io_mem_access_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_valid, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_opcode, // @[mshrs.scala:405:14] input [1:0] io_mem_ack_bits_param, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_size, // @[mshrs.scala:405:14] input [2:0] io_mem_ack_bits_source, // @[mshrs.scala:405:14] input [3:0] io_mem_ack_bits_sink, // @[mshrs.scala:405:14] input io_mem_ack_bits_denied, // @[mshrs.scala:405:14] input [127:0] io_mem_ack_bits_data, // @[mshrs.scala:405:14] input io_mem_ack_bits_corrupt // @[mshrs.scala:405:14] ); wire io_req_valid_0 = io_req_valid; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[mshrs.scala:402:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[mshrs.scala:402:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[mshrs.scala:402:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[mshrs.scala:402:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[mshrs.scala:402:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[mshrs.scala:402:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[mshrs.scala:402:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[mshrs.scala:402:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[mshrs.scala:402:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[mshrs.scala:402:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[mshrs.scala:402:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[mshrs.scala:402:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[mshrs.scala:402:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[mshrs.scala:402:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[mshrs.scala:402:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[mshrs.scala:402:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[mshrs.scala:402:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[mshrs.scala:402:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[mshrs.scala:402:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[mshrs.scala:402:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[mshrs.scala:402:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[mshrs.scala:402:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[mshrs.scala:402:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[mshrs.scala:402:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[mshrs.scala:402:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[mshrs.scala:402:7] wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[mshrs.scala:402:7] wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[mshrs.scala:402:7] wire io_req_bits_is_hella_0 = io_req_bits_is_hella; // @[mshrs.scala:402:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:402:7] wire io_mem_access_ready_0 = io_mem_access_ready; // @[mshrs.scala:402:7] wire io_mem_ack_valid_0 = io_mem_ack_valid; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_opcode_0 = io_mem_ack_bits_opcode; // @[mshrs.scala:402:7] wire [1:0] io_mem_ack_bits_param_0 = io_mem_ack_bits_param; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_size_0 = io_mem_ack_bits_size; // @[mshrs.scala:402:7] wire [2:0] io_mem_ack_bits_source_0 = io_mem_ack_bits_source; // @[mshrs.scala:402:7] wire [3:0] io_mem_ack_bits_sink_0 = io_mem_ack_bits_sink; // @[mshrs.scala:402:7] wire io_mem_ack_bits_denied_0 = io_mem_ack_bits_denied; // @[mshrs.scala:402:7] wire [127:0] io_mem_ack_bits_data_0 = io_mem_ack_bits_data; // @[mshrs.scala:402:7] wire io_mem_ack_bits_corrupt_0 = io_mem_ack_bits_corrupt; // @[mshrs.scala:402:7] wire io_mem_access_bits_corrupt = 1'h0; // @[mshrs.scala:402:7] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire get_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire put_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_WIRE_corrupt = 1'h0; // @[mshrs.scala:439:46] wire _atomics_legal_T_34 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_40 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_93 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_99 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_152 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_158 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_2 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_211 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_217 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_3 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_270 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_276 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_4 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_329 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_335 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_5 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_388 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_394 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_6 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_447 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_453 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_7 = 1'h0; // @[Misc.scala:206:21] wire _atomics_legal_T_506 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_512 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire atomics_a_mask_sub_sub_sub_sub_0_1_8 = 1'h0; // @[Misc.scala:206:21] wire _atomics_T_1_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_3_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_5_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_7_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_9_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_11_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_13_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _atomics_T_15_corrupt = 1'h0; // @[mshrs.scala:439:75] wire atomics_corrupt = 1'h0; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_42_corrupt = 1'h0; // @[mshrs.scala:457:66] wire _io_mem_access_bits_T_43_corrupt = 1'h0; // @[mshrs.scala:457:29] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire [2:0] get_source = 3'h5; // @[Edges.scala:460:17] wire [2:0] put_source = 3'h5; // @[Edges.scala:480:17] wire [2:0] atomics_a_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_source = 3'h5; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_source = 3'h5; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_source = 3'h5; // @[mshrs.scala:457:66] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[mshrs.scala:439:46] wire [2:0] _atomics_WIRE_param = 3'h0; // @[mshrs.scala:439:46] wire [2:0] _atomics_WIRE_source = 3'h0; // @[mshrs.scala:439:46] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] _io_mem_access_bits_T_42_param = 3'h0; // @[mshrs.scala:457:66] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_41 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_42 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_43 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_44 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_59 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_100 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_101 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_102 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_103 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_118 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_119 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_120 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_121 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_159 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_160 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_161 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_177 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_178 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_179 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_180 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_220 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_221 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_236 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_237 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_238 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_239 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_277 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_278 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_279 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_280 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_295 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_296 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_297 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_298 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_336 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_337 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_338 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_339 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_354 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_355 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_356 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_357 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_395 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_396 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_397 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_398 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_413 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_414 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_415 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_416 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_454 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_455 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_456 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_457 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_472 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_473 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_474 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_475 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_513 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_514 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_515 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_516 = 1'h1; // @[Parameters.scala:684:29] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [127:0] get_data = 128'h0; // @[Edges.scala:460:17] wire [127:0] _atomics_WIRE_data = 128'h0; // @[mshrs.scala:439:46] wire [15:0] _atomics_WIRE_mask = 16'h0; // @[mshrs.scala:439:46] wire [31:0] _atomics_WIRE_address = 32'h0; // @[mshrs.scala:439:46] wire [3:0] _atomics_WIRE_size = 4'h0; // @[mshrs.scala:439:46] wire _io_req_ready_T; // @[mshrs.scala:427:25] wire _io_resp_valid_T_1; // @[mshrs.scala:461:43] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_mem_access_valid_T; // @[mshrs.scala:456:32] wire [2:0] _io_mem_access_bits_T_43_opcode; // @[mshrs.scala:457:29] wire [2:0] _io_mem_access_bits_T_43_param; // @[mshrs.scala:457:29] wire [3:0] _io_mem_access_bits_T_43_size; // @[mshrs.scala:457:29] wire [2:0] _io_mem_access_bits_T_43_source; // @[mshrs.scala:457:29] wire [31:0] _io_mem_access_bits_T_43_address; // @[mshrs.scala:457:29] wire [15:0] _io_mem_access_bits_T_43_mask; // @[mshrs.scala:457:29] wire [127:0] _io_mem_access_bits_T_43_data; // @[mshrs.scala:457:29] wire io_req_ready_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:402:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:402:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:402:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:402:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:402:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:402:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:402:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:402:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:402:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:402:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:402:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:402:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:402:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:402:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:402:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:402:7] wire io_resp_valid_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_opcode_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_param_0; // @[mshrs.scala:402:7] wire [3:0] io_mem_access_bits_size_0; // @[mshrs.scala:402:7] wire [2:0] io_mem_access_bits_source_0; // @[mshrs.scala:402:7] wire [31:0] io_mem_access_bits_address_0; // @[mshrs.scala:402:7] wire [15:0] io_mem_access_bits_mask_0; // @[mshrs.scala:402:7] wire [127:0] io_mem_access_bits_data_0; // @[mshrs.scala:402:7] wire io_mem_access_valid_0; // @[mshrs.scala:402:7] reg [6:0] req_uop_uopc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uopc_0 = req_uop_uopc; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_inst_0 = req_uop_inst; // @[mshrs.scala:402:7, :421:16] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_inst_0 = req_uop_debug_inst; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_rvc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_rvc_0 = req_uop_is_rvc; // @[mshrs.scala:402:7, :421:16] reg [39:0] req_uop_debug_pc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_pc_0 = req_uop_debug_pc; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_iq_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iq_type_0 = req_uop_iq_type; // @[mshrs.scala:402:7, :421:16] reg [9:0] req_uop_fu_code; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fu_code_0 = req_uop_fu_code; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_br_type_0 = req_uop_ctrl_br_type; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op1_sel_0 = req_uop_ctrl_op1_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op2_sel_0 = req_uop_ctrl_op2_sel; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_imm_sel_0 = req_uop_ctrl_imm_sel; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_op_fcn_0 = req_uop_ctrl_op_fcn; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_fcn_dw_0 = req_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7, :421:16] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_csr_cmd_0 = req_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_load; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_load_0 = req_uop_ctrl_is_load; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_sta; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_sta_0 = req_uop_ctrl_is_sta; // @[mshrs.scala:402:7, :421:16] reg req_uop_ctrl_is_std; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ctrl_is_std_0 = req_uop_ctrl_is_std; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_iw_state; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_state_0 = req_uop_iw_state; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p1_poisoned_0 = req_uop_iw_p1_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:421:16] assign io_resp_bits_uop_iw_p2_poisoned_0 = req_uop_iw_p2_poisoned; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_br; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_br_0 = req_uop_is_br; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jalr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jalr_0 = req_uop_is_jalr; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_jal; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_jal_0 = req_uop_is_jal; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sfb; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sfb_0 = req_uop_is_sfb; // @[mshrs.scala:402:7, :421:16] reg [15:0] req_uop_br_mask; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_mask_0 = req_uop_br_mask; // @[mshrs.scala:402:7, :421:16] reg [3:0] req_uop_br_tag; // @[mshrs.scala:421:16] assign io_resp_bits_uop_br_tag_0 = req_uop_br_tag; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ftq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ftq_idx_0 = req_uop_ftq_idx; // @[mshrs.scala:402:7, :421:16] reg req_uop_edge_inst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_edge_inst_0 = req_uop_edge_inst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pc_lob_0 = req_uop_pc_lob; // @[mshrs.scala:402:7, :421:16] reg req_uop_taken; // @[mshrs.scala:421:16] assign io_resp_bits_uop_taken_0 = req_uop_taken; // @[mshrs.scala:402:7, :421:16] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_imm_packed_0 = req_uop_imm_packed; // @[mshrs.scala:402:7, :421:16] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:421:16] assign io_resp_bits_uop_csr_addr_0 = req_uop_csr_addr; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_rob_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rob_idx_0 = req_uop_rob_idx; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ldq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldq_idx_0 = req_uop_ldq_idx; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_stq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stq_idx_0 = req_uop_stq_idx; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:421:16] assign io_resp_bits_uop_rxq_idx_0 = req_uop_rxq_idx; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_pdst_0 = req_uop_pdst; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_0 = req_uop_prs1; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_0 = req_uop_prs2; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_prs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_0 = req_uop_prs3; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_ppred; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_0 = req_uop_ppred; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs1_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs1_busy_0 = req_uop_prs1_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs2_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs2_busy_0 = req_uop_prs2_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_prs3_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_prs3_busy_0 = req_uop_prs3_busy; // @[mshrs.scala:402:7, :421:16] reg req_uop_ppred_busy; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ppred_busy_0 = req_uop_ppred_busy; // @[mshrs.scala:402:7, :421:16] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_stale_pdst_0 = req_uop_stale_pdst; // @[mshrs.scala:402:7, :421:16] reg req_uop_exception; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exception_0 = req_uop_exception; // @[mshrs.scala:402:7, :421:16] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:421:16] assign io_resp_bits_uop_exc_cause_0 = req_uop_exc_cause; // @[mshrs.scala:402:7, :421:16] reg req_uop_bypassable; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bypassable_0 = req_uop_bypassable; // @[mshrs.scala:402:7, :421:16] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_cmd_0 = req_uop_mem_cmd; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_mem_size; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_size_0 = req_uop_mem_size; // @[mshrs.scala:402:7, :421:16] wire [1:0] size = req_uop_mem_size; // @[AMOALU.scala:11:18] reg req_uop_mem_signed; // @[mshrs.scala:421:16] assign io_resp_bits_uop_mem_signed_0 = req_uop_mem_signed; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fence; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fence_0 = req_uop_is_fence; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_fencei; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_fencei_0 = req_uop_is_fencei; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_amo; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_amo_0 = req_uop_is_amo; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_ldq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_ldq_0 = req_uop_uses_ldq; // @[mshrs.scala:402:7, :421:16] reg req_uop_uses_stq; // @[mshrs.scala:421:16] assign io_resp_bits_uop_uses_stq_0 = req_uop_uses_stq; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_sys_pc2epc_0 = req_uop_is_sys_pc2epc; // @[mshrs.scala:402:7, :421:16] reg req_uop_is_unique; // @[mshrs.scala:421:16] assign io_resp_bits_uop_is_unique_0 = req_uop_is_unique; // @[mshrs.scala:402:7, :421:16] reg req_uop_flush_on_commit; // @[mshrs.scala:421:16] assign io_resp_bits_uop_flush_on_commit_0 = req_uop_flush_on_commit; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_is_rs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_is_rs1_0 = req_uop_ldst_is_rs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_ldst; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_0 = req_uop_ldst; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs1; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_0 = req_uop_lrs1; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs2; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_0 = req_uop_lrs2; // @[mshrs.scala:402:7, :421:16] reg [5:0] req_uop_lrs3; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs3_0 = req_uop_lrs3; // @[mshrs.scala:402:7, :421:16] reg req_uop_ldst_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_ldst_val_0 = req_uop_ldst_val; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_dst_rtype_0 = req_uop_dst_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs1_rtype_0 = req_uop_lrs1_rtype; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:421:16] assign io_resp_bits_uop_lrs2_rtype_0 = req_uop_lrs2_rtype; // @[mshrs.scala:402:7, :421:16] reg req_uop_frs3_en; // @[mshrs.scala:421:16] assign io_resp_bits_uop_frs3_en_0 = req_uop_frs3_en; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_val; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_val_0 = req_uop_fp_val; // @[mshrs.scala:402:7, :421:16] reg req_uop_fp_single; // @[mshrs.scala:421:16] assign io_resp_bits_uop_fp_single_0 = req_uop_fp_single; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_pf_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_pf_if_0 = req_uop_xcpt_pf_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ae_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ae_if_0 = req_uop_xcpt_ae_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_xcpt_ma_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_xcpt_ma_if_0 = req_uop_xcpt_ma_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_debug_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_debug_if_0 = req_uop_bp_debug_if; // @[mshrs.scala:402:7, :421:16] reg req_uop_bp_xcpt_if; // @[mshrs.scala:421:16] assign io_resp_bits_uop_bp_xcpt_if_0 = req_uop_bp_xcpt_if; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_fsrc_0 = req_uop_debug_fsrc; // @[mshrs.scala:402:7, :421:16] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:421:16] assign io_resp_bits_uop_debug_tsrc_0 = req_uop_debug_tsrc; // @[mshrs.scala:402:7, :421:16] reg [39:0] req_addr; // @[mshrs.scala:421:16] wire [39:0] _get_legal_T_14 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_14 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_4 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_63 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_122 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_181 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_240 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_299 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_358 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_417 = req_addr; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_476 = req_addr; // @[Parameters.scala:137:31] reg [63:0] req_data; // @[mshrs.scala:421:16] reg req_is_hella; // @[mshrs.scala:421:16] assign io_resp_bits_is_hella_0 = req_is_hella; // @[mshrs.scala:402:7, :421:16] reg [63:0] grant_word; // @[mshrs.scala:422:23] reg [1:0] state; // @[mshrs.scala:426:22] assign _io_req_ready_T = state == 2'h0; // @[mshrs.scala:426:22, :427:25] assign io_req_ready_0 = _io_req_ready_T; // @[mshrs.scala:402:7, :427:25] wire [127:0] a_data = {2{req_data}}; // @[mshrs.scala:421:16, :434:23] wire [127:0] put_data = a_data; // @[Edges.scala:480:17] wire [127:0] atomics_a_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_1_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_2_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_3_data = a_data; // @[Edges.scala:534:17] wire [127:0] atomics_a_4_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_5_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_6_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_7_data = a_data; // @[Edges.scala:517:17] wire [127:0] atomics_a_8_data = a_data; // @[Edges.scala:517:17] wire [39:0] _GEN = {req_addr[39:14], req_addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_62 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_0 = {req_addr[39:17], req_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31] assign _put_legal_T_63 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_35; // @[Parameters.scala:137:31] assign _atomics_legal_T_35 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_94; // @[Parameters.scala:137:31] assign _atomics_legal_T_94 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_153; // @[Parameters.scala:137:31] assign _atomics_legal_T_153 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_212; // @[Parameters.scala:137:31] assign _atomics_legal_T_212 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_271; // @[Parameters.scala:137:31] assign _atomics_legal_T_271 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_330; // @[Parameters.scala:137:31] assign _atomics_legal_T_330 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_389; // @[Parameters.scala:137:31] assign _atomics_legal_T_389 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_448; // @[Parameters.scala:137:31] assign _atomics_legal_T_448 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_507; // @[Parameters.scala:137:31] assign _atomics_legal_T_507 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {req_addr[39:26], req_addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {req_addr[39:28], req_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31] assign _put_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_45; // @[Parameters.scala:137:31] assign _atomics_legal_T_45 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_104; // @[Parameters.scala:137:31] assign _atomics_legal_T_104 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_163; // @[Parameters.scala:137:31] assign _atomics_legal_T_163 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_222; // @[Parameters.scala:137:31] assign _atomics_legal_T_222 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_281; // @[Parameters.scala:137:31] assign _atomics_legal_T_281 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_340; // @[Parameters.scala:137:31] assign _atomics_legal_T_340 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_399; // @[Parameters.scala:137:31] assign _atomics_legal_T_399 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_458; // @[Parameters.scala:137:31] assign _atomics_legal_T_458 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_517; // @[Parameters.scala:137:31] assign _atomics_legal_T_517 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {req_addr[39:29], req_addr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31] assign _get_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31] assign _put_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31] assign _atomics_legal_T_24 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31] assign _atomics_legal_T_142 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_201; // @[Parameters.scala:137:31] assign _atomics_legal_T_201 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_260; // @[Parameters.scala:137:31] assign _atomics_legal_T_260 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_319; // @[Parameters.scala:137:31] assign _atomics_legal_T_319 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_378; // @[Parameters.scala:137:31] assign _atomics_legal_T_378 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_437; // @[Parameters.scala:137:31] assign _atomics_legal_T_437 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_496; // @[Parameters.scala:137:31] assign _atomics_legal_T_496 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46] wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] get_address = req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] atomics_a_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = req_addr[31:0]; // @[Edges.scala:517:17] wire [39:0] _GEN_4 = {req_addr[39:32], req_addr[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31] assign _get_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31] assign _put_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_50; // @[Parameters.scala:137:31] assign _atomics_legal_T_50 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_109; // @[Parameters.scala:137:31] assign _atomics_legal_T_109 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_168; // @[Parameters.scala:137:31] assign _atomics_legal_T_168 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_227; // @[Parameters.scala:137:31] assign _atomics_legal_T_227 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_286; // @[Parameters.scala:137:31] assign _atomics_legal_T_286 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_345; // @[Parameters.scala:137:31] assign _atomics_legal_T_345 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_404; // @[Parameters.scala:137:31] assign _atomics_legal_T_404 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_463; // @[Parameters.scala:137:31] assign _atomics_legal_T_463 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_522; // @[Parameters.scala:137:31] assign _atomics_legal_T_522 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46] wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_54 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_55 = _get_legal_T_54 | _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_56 = _get_legal_T_55 | _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_57 = _get_legal_T_56 | _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_58 = _get_legal_T_57 | _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_59 = _get_legal_T_58 | _get_legal_T_48; // @[Parameters.scala:685:42] wire _get_legal_T_60 = _get_legal_T_59 | _get_legal_T_53; // @[Parameters.scala:685:42] wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_62 | _get_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [15:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [15:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_5 = {2'h0, req_uop_mem_size}; // @[Edges.scala:463:15] assign get_size = _GEN_5; // @[Edges.scala:460:17, :463:15] wire [3:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_5; // @[Misc.scala:202:34] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_5; // @[Edges.scala:463:15, :480:17] wire [3:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_5; // @[Edges.scala:463:15, :534:17] wire [3:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_5; // @[Misc.scala:202:34] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_5; // @[Edges.scala:463:15, :517:17] wire [3:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_5; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_size = get_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_sub_bit = req_addr[3]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_sub_bit = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_1 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_2 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_3 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_4 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_5 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_6 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_7 = req_addr[3]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_sub_bit_8 = req_addr[3]; // @[Misc.scala:210:26] wire _grant_word_shift_T = req_addr[3]; // @[package.scala:163:13] wire get_a_mask_sub_sub_sub_1_2 = get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_sub_nbit = ~get_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_sub_0_2 = get_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_sub_acc_T = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_0_1 = _get_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _get_a_mask_sub_sub_sub_acc_T_1 = get_a_mask_sub_sub_sub_size & get_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_sub_1_1 = _get_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = req_addr[2]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T = req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_sub_0_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_2_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T_2 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_2_1 = get_a_mask_sub_sub_sub_1_1 | _get_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_sub_3_2 = get_a_mask_sub_sub_sub_1_2 & get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_sub_acc_T_3 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_3_1 = get_a_mask_sub_sub_sub_1_1 | _get_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = req_addr[1]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_3 = req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_4_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_4 = get_a_mask_sub_size & get_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_4_1 = get_a_mask_sub_sub_2_1 | _get_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_5_2 = get_a_mask_sub_sub_2_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_5 = get_a_mask_sub_size & get_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_5_1 = get_a_mask_sub_sub_2_1 | _get_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_6_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_6 = get_a_mask_sub_size & get_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_6_1 = get_a_mask_sub_sub_3_1 | _get_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_7_2 = get_a_mask_sub_sub_3_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_7 = get_a_mask_sub_size & get_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_7_1 = get_a_mask_sub_sub_3_1 | _get_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = req_addr[0]; // @[Misc.scala:210:26] wire _io_resp_bits_data_shifted_T_6 = req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_8 = get_a_mask_sub_4_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_8 = get_a_mask_size & get_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_8 = get_a_mask_sub_4_1 | _get_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_9 = get_a_mask_sub_4_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_9 = get_a_mask_size & get_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_9 = get_a_mask_sub_4_1 | _get_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_10 = get_a_mask_sub_5_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_10 = get_a_mask_size & get_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_10 = get_a_mask_sub_5_1 | _get_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_11 = get_a_mask_sub_5_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_11 = get_a_mask_size & get_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_11 = get_a_mask_sub_5_1 | _get_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_12 = get_a_mask_sub_6_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_12 = get_a_mask_size & get_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_12 = get_a_mask_sub_6_1 | _get_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_13 = get_a_mask_sub_6_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_13 = get_a_mask_size & get_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_13 = get_a_mask_sub_6_1 | _get_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_14 = get_a_mask_sub_7_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_14 = get_a_mask_size & get_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_14 = get_a_mask_sub_7_1 | _get_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_15 = get_a_mask_sub_7_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_15 = get_a_mask_size & get_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_15 = get_a_mask_sub_7_1 | _get_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_lo = {get_a_mask_lo_lo_hi, get_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_lo_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_hi = {get_a_mask_lo_hi_hi, get_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo_lo = {get_a_mask_acc_9, get_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_lo_hi = {get_a_mask_acc_11, get_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_lo = {get_a_mask_hi_lo_hi, get_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_hi_lo = {get_a_mask_acc_13, get_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi_hi = {get_a_mask_acc_15, get_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_hi = {get_a_mask_hi_hi_hi, get_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_69 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_6 = {req_addr[39:21], req_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31] assign _atomics_legal_T_68 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31] assign _atomics_legal_T_127 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31] assign _atomics_legal_T_186 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31] assign _atomics_legal_T_245 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31] assign _atomics_legal_T_304 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_363; // @[Parameters.scala:137:31] assign _atomics_legal_T_363 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_422; // @[Parameters.scala:137:31] assign _atomics_legal_T_422 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_481; // @[Parameters.scala:137:31] assign _atomics_legal_T_481 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_7 = {req_addr[39:26], req_addr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31] assign _atomics_legal_T_73 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31] assign _atomics_legal_T_132 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31] assign _atomics_legal_T_191 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31] assign _atomics_legal_T_250 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_309; // @[Parameters.scala:137:31] assign _atomics_legal_T_309 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_368; // @[Parameters.scala:137:31] assign _atomics_legal_T_368 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_427; // @[Parameters.scala:137:31] assign _atomics_legal_T_427 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_486; // @[Parameters.scala:137:31] assign _atomics_legal_T_486 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46] wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46] wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46] wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_54 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_55 = _put_legal_T_54 | _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_56 = _put_legal_T_55 | _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_57 = _put_legal_T_56 | _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_58 = _put_legal_T_57 | _put_legal_T_43; // @[Parameters.scala:685:42] wire _put_legal_T_59 = _put_legal_T_58 | _put_legal_T_48; // @[Parameters.scala:685:42] wire _put_legal_T_60 = _put_legal_T_59 | _put_legal_T_53; // @[Parameters.scala:685:42] wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46] wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_70 = _put_legal_T_69 | _put_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_70; // @[Parameters.scala:686:26] wire [15:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [15:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_size = put_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_sub_1_2 = put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_sub_nbit = ~put_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_sub_0_2 = put_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_sub_acc_T = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_0_1 = _put_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _put_a_mask_sub_sub_sub_acc_T_1 = put_a_mask_sub_sub_sub_size & put_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_sub_1_1 = _put_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_sub_0_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_2_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T_2 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_2_1 = put_a_mask_sub_sub_sub_1_1 | _put_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_sub_3_2 = put_a_mask_sub_sub_sub_1_2 & put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_sub_acc_T_3 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_3_1 = put_a_mask_sub_sub_sub_1_1 | _put_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_4_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_4 = put_a_mask_sub_size & put_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_4_1 = put_a_mask_sub_sub_2_1 | _put_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_5_2 = put_a_mask_sub_sub_2_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_5 = put_a_mask_sub_size & put_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_5_1 = put_a_mask_sub_sub_2_1 | _put_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_6_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_6 = put_a_mask_sub_size & put_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_6_1 = put_a_mask_sub_sub_3_1 | _put_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_7_2 = put_a_mask_sub_sub_3_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_7 = put_a_mask_sub_size & put_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_7_1 = put_a_mask_sub_sub_3_1 | _put_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_8 = put_a_mask_sub_4_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_8 = put_a_mask_size & put_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_8 = put_a_mask_sub_4_1 | _put_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_9 = put_a_mask_sub_4_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_9 = put_a_mask_size & put_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_9 = put_a_mask_sub_4_1 | _put_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_10 = put_a_mask_sub_5_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_10 = put_a_mask_size & put_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_10 = put_a_mask_sub_5_1 | _put_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_11 = put_a_mask_sub_5_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_11 = put_a_mask_size & put_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_11 = put_a_mask_sub_5_1 | _put_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_12 = put_a_mask_sub_6_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_12 = put_a_mask_size & put_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_12 = put_a_mask_sub_6_1 | _put_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_13 = put_a_mask_sub_6_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_13 = put_a_mask_size & put_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_13 = put_a_mask_sub_6_1 | _put_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_14 = put_a_mask_sub_7_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_14 = put_a_mask_size & put_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_14 = put_a_mask_sub_7_1 | _put_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_15 = put_a_mask_sub_7_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_15 = put_a_mask_size & put_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_15 = put_a_mask_sub_7_1 | _put_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_lo = {put_a_mask_lo_lo_hi, put_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_lo_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo_hi = {put_a_mask_lo_hi_hi, put_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo_lo = {put_a_mask_acc_9, put_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_lo_hi = {put_a_mask_acc_11, put_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_lo = {put_a_mask_hi_lo_hi, put_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_hi_lo = {put_a_mask_acc_13, put_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi_hi = {put_a_mask_acc_15, put_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi_hi = {put_a_mask_hi_hi_hi, put_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {req_addr[39:28], req_addr[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31] assign _atomics_legal_T_19 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31] assign _atomics_legal_T_78 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31] assign _atomics_legal_T_137 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31] assign _atomics_legal_T_196 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_255; // @[Parameters.scala:137:31] assign _atomics_legal_T_255 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_314; // @[Parameters.scala:137:31] assign _atomics_legal_T_314 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_373; // @[Parameters.scala:137:31] assign _atomics_legal_T_373 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_432; // @[Parameters.scala:137:31] assign _atomics_legal_T_432 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_491; // @[Parameters.scala:137:31] assign _atomics_legal_T_491 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46] wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46] wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_29 = _atomics_legal_T_8 | _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_30 = _atomics_legal_T_29 | _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_31 = _atomics_legal_T_30 | _atomics_legal_T_23; // @[Parameters.scala:685:42] wire _atomics_legal_T_32 = _atomics_legal_T_31 | _atomics_legal_T_28; // @[Parameters.scala:685:42] wire _atomics_legal_T_33 = _atomics_legal_T_32; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_57 = _atomics_legal_T_33; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_36 = {1'h0, _atomics_legal_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_38 = _atomics_legal_T_37; // @[Parameters.scala:137:46] wire _atomics_legal_T_39 = _atomics_legal_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_46 = {1'h0, _atomics_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_47 = _atomics_legal_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_48 = _atomics_legal_T_47; // @[Parameters.scala:137:46] wire _atomics_legal_T_49 = _atomics_legal_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_51 = {1'h0, _atomics_legal_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_52 = _atomics_legal_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_53 = _atomics_legal_T_52; // @[Parameters.scala:137:46] wire _atomics_legal_T_54 = _atomics_legal_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_55 = _atomics_legal_T_49 | _atomics_legal_T_54; // @[Parameters.scala:685:42] wire _atomics_legal_T_56 = _atomics_legal_T_55; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_58 = _atomics_legal_T_57; // @[Parameters.scala:686:26] wire atomics_legal = _atomics_legal_T_58 | _atomics_legal_T_56; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [15:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size = atomics_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit = ~atomics_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1 = _atomics_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_sub_size & atomics_a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_sub_0_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1 = atomics_a_mask_sub_sub_sub_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2 = atomics_a_mask_sub_sub_sub_1_2 & atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1 = atomics_a_mask_sub_sub_sub_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size & atomics_a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1 = atomics_a_mask_sub_sub_2_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2 = atomics_a_mask_sub_sub_2_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size & atomics_a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1 = atomics_a_mask_sub_sub_2_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size & atomics_a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1 = atomics_a_mask_sub_sub_3_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2 = atomics_a_mask_sub_sub_3_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size & atomics_a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1 = atomics_a_mask_sub_sub_3_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_4_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_4_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_4_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_4_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_5_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_5_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_5_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_5_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_6_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_6_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_6_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_6_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_7_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_7_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_7_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_7_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo = {atomics_a_mask_lo_lo_hi, atomics_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi = {atomics_a_mask_lo_hi_hi, atomics_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo = {atomics_a_mask_hi_lo_hi, atomics_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi = {atomics_a_mask_hi_hi_hi, atomics_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46] wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46] wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46] wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46] wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_88 = _atomics_legal_T_67 | _atomics_legal_T_72; // @[Parameters.scala:685:42] wire _atomics_legal_T_89 = _atomics_legal_T_88 | _atomics_legal_T_77; // @[Parameters.scala:685:42] wire _atomics_legal_T_90 = _atomics_legal_T_89 | _atomics_legal_T_82; // @[Parameters.scala:685:42] wire _atomics_legal_T_91 = _atomics_legal_T_90 | _atomics_legal_T_87; // @[Parameters.scala:685:42] wire _atomics_legal_T_92 = _atomics_legal_T_91; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_116 = _atomics_legal_T_92; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_95 = {1'h0, _atomics_legal_T_94}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_96 = _atomics_legal_T_95 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_97 = _atomics_legal_T_96; // @[Parameters.scala:137:46] wire _atomics_legal_T_98 = _atomics_legal_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_105 = {1'h0, _atomics_legal_T_104}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_106 = _atomics_legal_T_105 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_107 = _atomics_legal_T_106; // @[Parameters.scala:137:46] wire _atomics_legal_T_108 = _atomics_legal_T_107 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_110 = {1'h0, _atomics_legal_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_111 = _atomics_legal_T_110 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_112 = _atomics_legal_T_111; // @[Parameters.scala:137:46] wire _atomics_legal_T_113 = _atomics_legal_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_114 = _atomics_legal_T_108 | _atomics_legal_T_113; // @[Parameters.scala:685:42] wire _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_117 = _atomics_legal_T_116; // @[Parameters.scala:686:26] wire atomics_legal_1 = _atomics_legal_T_117 | _atomics_legal_T_115; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [15:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_1 = atomics_a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_sub_size_1 & atomics_a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_1 = _atomics_a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_sub_0_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_1 = atomics_a_mask_sub_sub_sub_1_2_1 & atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_1 = atomics_a_mask_sub_sub_sub_1_1_1 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_1 = atomics_a_mask_sub_sub_2_1_1 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_1 = atomics_a_mask_sub_sub_2_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_1 = atomics_a_mask_sub_sub_2_1_1 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_1 = atomics_a_mask_sub_sub_3_1_1 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_1 = atomics_a_mask_sub_sub_3_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_1 = atomics_a_mask_sub_sub_3_1_1 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_1 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_1 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_1 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_1 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_1 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_1 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_1 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_1 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_1 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_4_1_1 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_4_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_1 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_4_1_1 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_1 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_5_1_1 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_5_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_1 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_5_1_1 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_1 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_6_1_1 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_6_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_1 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_6_1_1 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_1 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_7_1_1 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_7_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_1 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_7_1_1 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_1 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_1 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_lo_lo_hi_1, atomics_a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_1 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_1 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_lo_hi_hi_1, atomics_a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_1 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_1 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_hi_lo_hi_1, atomics_a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_1 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_1 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_hi_hi_hi_1, atomics_a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46] wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46] wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46] wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46] wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46] wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_147 = _atomics_legal_T_126 | _atomics_legal_T_131; // @[Parameters.scala:685:42] wire _atomics_legal_T_148 = _atomics_legal_T_147 | _atomics_legal_T_136; // @[Parameters.scala:685:42] wire _atomics_legal_T_149 = _atomics_legal_T_148 | _atomics_legal_T_141; // @[Parameters.scala:685:42] wire _atomics_legal_T_150 = _atomics_legal_T_149 | _atomics_legal_T_146; // @[Parameters.scala:685:42] wire _atomics_legal_T_151 = _atomics_legal_T_150; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_175 = _atomics_legal_T_151; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_154 = {1'h0, _atomics_legal_T_153}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_155 = _atomics_legal_T_154 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_156 = _atomics_legal_T_155; // @[Parameters.scala:137:46] wire _atomics_legal_T_157 = _atomics_legal_T_156 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_164 = {1'h0, _atomics_legal_T_163}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_165 = _atomics_legal_T_164 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_166 = _atomics_legal_T_165; // @[Parameters.scala:137:46] wire _atomics_legal_T_167 = _atomics_legal_T_166 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_169 = {1'h0, _atomics_legal_T_168}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_170 = _atomics_legal_T_169 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_171 = _atomics_legal_T_170; // @[Parameters.scala:137:46] wire _atomics_legal_T_172 = _atomics_legal_T_171 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_173 = _atomics_legal_T_167 | _atomics_legal_T_172; // @[Parameters.scala:685:42] wire _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_176 = _atomics_legal_T_175; // @[Parameters.scala:686:26] wire atomics_legal_2 = _atomics_legal_T_176 | _atomics_legal_T_174; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [15:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_2 = atomics_a_mask_sizeOH_2[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_sub_size_2 & atomics_a_mask_sub_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_2 = _atomics_a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_sub_0_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_2 = atomics_a_mask_sub_sub_sub_1_2_2 & atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_2 = atomics_a_mask_sub_sub_sub_1_1_2 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_4_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_2 = atomics_a_mask_sub_sub_2_1_2 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_2 = atomics_a_mask_sub_sub_2_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_5_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_2 = atomics_a_mask_sub_sub_2_1_2 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_6_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_2 = atomics_a_mask_sub_sub_3_1_2 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_2 = atomics_a_mask_sub_sub_3_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_7_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_2 = atomics_a_mask_sub_sub_3_1_2 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_2 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_2 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_2 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_2 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_2 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_2 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_2 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_2 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_2 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_4_1_2 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_4_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_2 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_4_1_2 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_2 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_5_1_2 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_5_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_2 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_5_1_2 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_2 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_6_1_2 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_6_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_2 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_6_1_2 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_2 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_7_1_2 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_7_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_2 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_7_1_2 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_2 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_2 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_lo_lo_hi_2, atomics_a_mask_lo_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_2 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_2 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_lo_hi_hi_2, atomics_a_mask_lo_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_2 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_2 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_hi_lo_hi_2, atomics_a_mask_hi_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_2 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_2 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_hi_hi_hi_2, atomics_a_mask_hi_hi_lo_2}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46] wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46] wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46] wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46] wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_202 = {1'h0, _atomics_legal_T_201}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_203 = _atomics_legal_T_202 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_204 = _atomics_legal_T_203; // @[Parameters.scala:137:46] wire _atomics_legal_T_205 = _atomics_legal_T_204 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_206 = _atomics_legal_T_185 | _atomics_legal_T_190; // @[Parameters.scala:685:42] wire _atomics_legal_T_207 = _atomics_legal_T_206 | _atomics_legal_T_195; // @[Parameters.scala:685:42] wire _atomics_legal_T_208 = _atomics_legal_T_207 | _atomics_legal_T_200; // @[Parameters.scala:685:42] wire _atomics_legal_T_209 = _atomics_legal_T_208 | _atomics_legal_T_205; // @[Parameters.scala:685:42] wire _atomics_legal_T_210 = _atomics_legal_T_209; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_234 = _atomics_legal_T_210; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_213 = {1'h0, _atomics_legal_T_212}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_214 = _atomics_legal_T_213 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_215 = _atomics_legal_T_214; // @[Parameters.scala:137:46] wire _atomics_legal_T_216 = _atomics_legal_T_215 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_223 = {1'h0, _atomics_legal_T_222}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_224 = _atomics_legal_T_223 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_225 = _atomics_legal_T_224; // @[Parameters.scala:137:46] wire _atomics_legal_T_226 = _atomics_legal_T_225 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_228 = {1'h0, _atomics_legal_T_227}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_229 = _atomics_legal_T_228 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_230 = _atomics_legal_T_229; // @[Parameters.scala:137:46] wire _atomics_legal_T_231 = _atomics_legal_T_230 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_232 = _atomics_legal_T_226 | _atomics_legal_T_231; // @[Parameters.scala:685:42] wire _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_235 = _atomics_legal_T_234; // @[Parameters.scala:686:26] wire atomics_legal_3 = _atomics_legal_T_235 | _atomics_legal_T_233; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [15:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_3 = atomics_a_mask_sizeOH_3[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_sub_size_3 & atomics_a_mask_sub_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_3 = _atomics_a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_sub_0_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_3 = atomics_a_mask_sub_sub_sub_1_2_3 & atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_3 = atomics_a_mask_sub_sub_sub_1_1_3 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_4_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_3 = atomics_a_mask_sub_sub_2_1_3 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_3 = atomics_a_mask_sub_sub_2_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_5_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_3 = atomics_a_mask_sub_sub_2_1_3 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_6_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_3 = atomics_a_mask_sub_sub_3_1_3 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_3 = atomics_a_mask_sub_sub_3_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_7_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_3 = atomics_a_mask_sub_sub_3_1_3 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_3 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_3 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_3 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_3 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_3 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_3 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_3 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_3 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_3 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_4_1_3 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_4_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_3 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_4_1_3 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_3 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_5_1_3 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_5_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_3 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_5_1_3 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_3 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_6_1_3 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_6_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_3 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_6_1_3 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_3 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_7_1_3 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_7_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_3 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_7_1_3 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_3 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_3 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_lo_lo_hi_3, atomics_a_mask_lo_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_3 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_3 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_lo_hi_hi_3, atomics_a_mask_lo_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_3 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_3 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_hi_lo_hi_3, atomics_a_mask_hi_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_3 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_3 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_hi_hi_hi_3, atomics_a_mask_hi_hi_lo_3}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46] wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46] wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46] wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_256 = {1'h0, _atomics_legal_T_255}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_257 = _atomics_legal_T_256 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_258 = _atomics_legal_T_257; // @[Parameters.scala:137:46] wire _atomics_legal_T_259 = _atomics_legal_T_258 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_261 = {1'h0, _atomics_legal_T_260}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_262 = _atomics_legal_T_261 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_263 = _atomics_legal_T_262; // @[Parameters.scala:137:46] wire _atomics_legal_T_264 = _atomics_legal_T_263 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_265 = _atomics_legal_T_244 | _atomics_legal_T_249; // @[Parameters.scala:685:42] wire _atomics_legal_T_266 = _atomics_legal_T_265 | _atomics_legal_T_254; // @[Parameters.scala:685:42] wire _atomics_legal_T_267 = _atomics_legal_T_266 | _atomics_legal_T_259; // @[Parameters.scala:685:42] wire _atomics_legal_T_268 = _atomics_legal_T_267 | _atomics_legal_T_264; // @[Parameters.scala:685:42] wire _atomics_legal_T_269 = _atomics_legal_T_268; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_293 = _atomics_legal_T_269; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_272 = {1'h0, _atomics_legal_T_271}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_273 = _atomics_legal_T_272 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_274 = _atomics_legal_T_273; // @[Parameters.scala:137:46] wire _atomics_legal_T_275 = _atomics_legal_T_274 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_282 = {1'h0, _atomics_legal_T_281}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_283 = _atomics_legal_T_282 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_284 = _atomics_legal_T_283; // @[Parameters.scala:137:46] wire _atomics_legal_T_285 = _atomics_legal_T_284 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_287 = {1'h0, _atomics_legal_T_286}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_288 = _atomics_legal_T_287 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_289 = _atomics_legal_T_288; // @[Parameters.scala:137:46] wire _atomics_legal_T_290 = _atomics_legal_T_289 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_291 = _atomics_legal_T_285 | _atomics_legal_T_290; // @[Parameters.scala:685:42] wire _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_294 = _atomics_legal_T_293; // @[Parameters.scala:686:26] wire atomics_legal_4 = _atomics_legal_T_294 | _atomics_legal_T_292; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [15:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_4 = atomics_a_mask_sizeOH_4[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_sub_size_4 & atomics_a_mask_sub_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_4 = _atomics_a_mask_sub_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_sub_0_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_18 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 | _atomics_a_mask_sub_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_4 = atomics_a_mask_sub_sub_sub_1_2_4 & atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_19 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_4 = atomics_a_mask_sub_sub_sub_1_1_4 | _atomics_a_mask_sub_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_36 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_4_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_4 = atomics_a_mask_sub_sub_2_1_4 | _atomics_a_mask_sub_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_4 = atomics_a_mask_sub_sub_2_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_37 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_5_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_4 = atomics_a_mask_sub_sub_2_1_4 | _atomics_a_mask_sub_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_38 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_6_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_4 = atomics_a_mask_sub_sub_3_1_4 | _atomics_a_mask_sub_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_4 = atomics_a_mask_sub_sub_3_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_39 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_7_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_4 = atomics_a_mask_sub_sub_3_1_4 | _atomics_a_mask_sub_acc_T_39; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_4 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_4 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_4 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_4 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_4 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_4 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_4 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_4 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_72 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_72 = atomics_a_mask_size_4 & atomics_a_mask_eq_72; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_72 = atomics_a_mask_sub_4_1_4 | _atomics_a_mask_acc_T_72; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_73 = atomics_a_mask_sub_4_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_73 = atomics_a_mask_size_4 & atomics_a_mask_eq_73; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_73 = atomics_a_mask_sub_4_1_4 | _atomics_a_mask_acc_T_73; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_74 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_74 = atomics_a_mask_size_4 & atomics_a_mask_eq_74; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_74 = atomics_a_mask_sub_5_1_4 | _atomics_a_mask_acc_T_74; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_75 = atomics_a_mask_sub_5_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_75 = atomics_a_mask_size_4 & atomics_a_mask_eq_75; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_75 = atomics_a_mask_sub_5_1_4 | _atomics_a_mask_acc_T_75; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_76 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_76 = atomics_a_mask_size_4 & atomics_a_mask_eq_76; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_76 = atomics_a_mask_sub_6_1_4 | _atomics_a_mask_acc_T_76; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_77 = atomics_a_mask_sub_6_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_77 = atomics_a_mask_size_4 & atomics_a_mask_eq_77; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_77 = atomics_a_mask_sub_6_1_4 | _atomics_a_mask_acc_T_77; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_78 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_78 = atomics_a_mask_size_4 & atomics_a_mask_eq_78; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_78 = atomics_a_mask_sub_7_1_4 | _atomics_a_mask_acc_T_78; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_79 = atomics_a_mask_sub_7_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_79 = atomics_a_mask_size_4 & atomics_a_mask_eq_79; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_79 = atomics_a_mask_sub_7_1_4 | _atomics_a_mask_acc_T_79; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_4 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_4 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_lo_lo_hi_4, atomics_a_mask_lo_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_4 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_4 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_lo_hi_hi_4, atomics_a_mask_lo_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_4 = {atomics_a_mask_acc_73, atomics_a_mask_acc_72}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_4 = {atomics_a_mask_acc_75, atomics_a_mask_acc_74}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_hi_lo_hi_4, atomics_a_mask_hi_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_4 = {atomics_a_mask_acc_77, atomics_a_mask_acc_76}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_4 = {atomics_a_mask_acc_79, atomics_a_mask_acc_78}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_hi_hi_hi_4, atomics_a_mask_hi_hi_lo_4}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46] wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46] wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_310 = {1'h0, _atomics_legal_T_309}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_311 = _atomics_legal_T_310 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_312 = _atomics_legal_T_311; // @[Parameters.scala:137:46] wire _atomics_legal_T_313 = _atomics_legal_T_312 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_315 = {1'h0, _atomics_legal_T_314}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_316 = _atomics_legal_T_315 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_317 = _atomics_legal_T_316; // @[Parameters.scala:137:46] wire _atomics_legal_T_318 = _atomics_legal_T_317 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_320 = {1'h0, _atomics_legal_T_319}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_321 = _atomics_legal_T_320 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_322 = _atomics_legal_T_321; // @[Parameters.scala:137:46] wire _atomics_legal_T_323 = _atomics_legal_T_322 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_324 = _atomics_legal_T_303 | _atomics_legal_T_308; // @[Parameters.scala:685:42] wire _atomics_legal_T_325 = _atomics_legal_T_324 | _atomics_legal_T_313; // @[Parameters.scala:685:42] wire _atomics_legal_T_326 = _atomics_legal_T_325 | _atomics_legal_T_318; // @[Parameters.scala:685:42] wire _atomics_legal_T_327 = _atomics_legal_T_326 | _atomics_legal_T_323; // @[Parameters.scala:685:42] wire _atomics_legal_T_328 = _atomics_legal_T_327; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_352 = _atomics_legal_T_328; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_331 = {1'h0, _atomics_legal_T_330}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_332 = _atomics_legal_T_331 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_333 = _atomics_legal_T_332; // @[Parameters.scala:137:46] wire _atomics_legal_T_334 = _atomics_legal_T_333 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_341 = {1'h0, _atomics_legal_T_340}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_342 = _atomics_legal_T_341 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_343 = _atomics_legal_T_342; // @[Parameters.scala:137:46] wire _atomics_legal_T_344 = _atomics_legal_T_343 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_346 = {1'h0, _atomics_legal_T_345}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_347 = _atomics_legal_T_346 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_348 = _atomics_legal_T_347; // @[Parameters.scala:137:46] wire _atomics_legal_T_349 = _atomics_legal_T_348 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_350 = _atomics_legal_T_344 | _atomics_legal_T_349; // @[Parameters.scala:685:42] wire _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_353 = _atomics_legal_T_352; // @[Parameters.scala:686:26] wire atomics_legal_5 = _atomics_legal_T_353 | _atomics_legal_T_351; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [15:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_5 = atomics_a_mask_sizeOH_5[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_sub_size_5 & atomics_a_mask_sub_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_5 = _atomics_a_mask_sub_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_20 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_sub_0_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_21 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_22 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 | _atomics_a_mask_sub_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_5 = atomics_a_mask_sub_sub_sub_1_2_5 & atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_23 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_5 = atomics_a_mask_sub_sub_sub_1_1_5 | _atomics_a_mask_sub_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_40 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_41 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_42 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_43 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_44 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_4_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_5 = atomics_a_mask_sub_sub_2_1_5 | _atomics_a_mask_sub_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_5 = atomics_a_mask_sub_sub_2_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_45 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_5_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_5 = atomics_a_mask_sub_sub_2_1_5 | _atomics_a_mask_sub_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_46 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_6_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_5 = atomics_a_mask_sub_sub_3_1_5 | _atomics_a_mask_sub_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_5 = atomics_a_mask_sub_sub_3_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_47 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_7_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_5 = atomics_a_mask_sub_sub_3_1_5 | _atomics_a_mask_sub_acc_T_47; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_80 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_80 = atomics_a_mask_size_5 & atomics_a_mask_eq_80; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_80 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_80; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_81 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_81 = atomics_a_mask_size_5 & atomics_a_mask_eq_81; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_81 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_81; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_82 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_82 = atomics_a_mask_size_5 & atomics_a_mask_eq_82; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_82 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_82; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_83 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_83 = atomics_a_mask_size_5 & atomics_a_mask_eq_83; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_83 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_83; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_84 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_84 = atomics_a_mask_size_5 & atomics_a_mask_eq_84; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_84 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_84; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_85 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_85 = atomics_a_mask_size_5 & atomics_a_mask_eq_85; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_85 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_85; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_86 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_86 = atomics_a_mask_size_5 & atomics_a_mask_eq_86; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_86 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_86; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_87 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_87 = atomics_a_mask_size_5 & atomics_a_mask_eq_87; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_87 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_87; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_88 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_88 = atomics_a_mask_size_5 & atomics_a_mask_eq_88; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_88 = atomics_a_mask_sub_4_1_5 | _atomics_a_mask_acc_T_88; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_89 = atomics_a_mask_sub_4_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_89 = atomics_a_mask_size_5 & atomics_a_mask_eq_89; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_89 = atomics_a_mask_sub_4_1_5 | _atomics_a_mask_acc_T_89; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_90 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_90 = atomics_a_mask_size_5 & atomics_a_mask_eq_90; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_90 = atomics_a_mask_sub_5_1_5 | _atomics_a_mask_acc_T_90; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_91 = atomics_a_mask_sub_5_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_91 = atomics_a_mask_size_5 & atomics_a_mask_eq_91; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_91 = atomics_a_mask_sub_5_1_5 | _atomics_a_mask_acc_T_91; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_92 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_92 = atomics_a_mask_size_5 & atomics_a_mask_eq_92; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_92 = atomics_a_mask_sub_6_1_5 | _atomics_a_mask_acc_T_92; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_93 = atomics_a_mask_sub_6_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_93 = atomics_a_mask_size_5 & atomics_a_mask_eq_93; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_93 = atomics_a_mask_sub_6_1_5 | _atomics_a_mask_acc_T_93; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_94 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_94 = atomics_a_mask_size_5 & atomics_a_mask_eq_94; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_94 = atomics_a_mask_sub_7_1_5 | _atomics_a_mask_acc_T_94; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_95 = atomics_a_mask_sub_7_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_95 = atomics_a_mask_size_5 & atomics_a_mask_eq_95; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_95 = atomics_a_mask_sub_7_1_5 | _atomics_a_mask_acc_T_95; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_5 = {atomics_a_mask_acc_81, atomics_a_mask_acc_80}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_5 = {atomics_a_mask_acc_83, atomics_a_mask_acc_82}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_lo_lo_hi_5, atomics_a_mask_lo_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_5 = {atomics_a_mask_acc_85, atomics_a_mask_acc_84}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_5 = {atomics_a_mask_acc_87, atomics_a_mask_acc_86}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_lo_hi_hi_5, atomics_a_mask_lo_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_5 = {atomics_a_mask_acc_89, atomics_a_mask_acc_88}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_5 = {atomics_a_mask_acc_91, atomics_a_mask_acc_90}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_hi_lo_hi_5, atomics_a_mask_hi_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_5 = {atomics_a_mask_acc_93, atomics_a_mask_acc_92}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_5 = {atomics_a_mask_acc_95, atomics_a_mask_acc_94}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_hi_hi_hi_5, atomics_a_mask_hi_hi_lo_5}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46] wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_364 = {1'h0, _atomics_legal_T_363}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_365 = _atomics_legal_T_364 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_366 = _atomics_legal_T_365; // @[Parameters.scala:137:46] wire _atomics_legal_T_367 = _atomics_legal_T_366 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_369 = {1'h0, _atomics_legal_T_368}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_370 = _atomics_legal_T_369 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_371 = _atomics_legal_T_370; // @[Parameters.scala:137:46] wire _atomics_legal_T_372 = _atomics_legal_T_371 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_374 = {1'h0, _atomics_legal_T_373}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_375 = _atomics_legal_T_374 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_376 = _atomics_legal_T_375; // @[Parameters.scala:137:46] wire _atomics_legal_T_377 = _atomics_legal_T_376 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_379 = {1'h0, _atomics_legal_T_378}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_380 = _atomics_legal_T_379 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_381 = _atomics_legal_T_380; // @[Parameters.scala:137:46] wire _atomics_legal_T_382 = _atomics_legal_T_381 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_383 = _atomics_legal_T_362 | _atomics_legal_T_367; // @[Parameters.scala:685:42] wire _atomics_legal_T_384 = _atomics_legal_T_383 | _atomics_legal_T_372; // @[Parameters.scala:685:42] wire _atomics_legal_T_385 = _atomics_legal_T_384 | _atomics_legal_T_377; // @[Parameters.scala:685:42] wire _atomics_legal_T_386 = _atomics_legal_T_385 | _atomics_legal_T_382; // @[Parameters.scala:685:42] wire _atomics_legal_T_387 = _atomics_legal_T_386; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_411 = _atomics_legal_T_387; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_390 = {1'h0, _atomics_legal_T_389}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_391 = _atomics_legal_T_390 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_392 = _atomics_legal_T_391; // @[Parameters.scala:137:46] wire _atomics_legal_T_393 = _atomics_legal_T_392 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_400 = {1'h0, _atomics_legal_T_399}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_401 = _atomics_legal_T_400 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_402 = _atomics_legal_T_401; // @[Parameters.scala:137:46] wire _atomics_legal_T_403 = _atomics_legal_T_402 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_405 = {1'h0, _atomics_legal_T_404}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_406 = _atomics_legal_T_405 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_407 = _atomics_legal_T_406; // @[Parameters.scala:137:46] wire _atomics_legal_T_408 = _atomics_legal_T_407 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_409 = _atomics_legal_T_403 | _atomics_legal_T_408; // @[Parameters.scala:685:42] wire _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_412 = _atomics_legal_T_411; // @[Parameters.scala:686:26] wire atomics_legal_6 = _atomics_legal_T_412 | _atomics_legal_T_410; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [15:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_6 = atomics_a_mask_sizeOH_6[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_sub_size_6 & atomics_a_mask_sub_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_6 = _atomics_a_mask_sub_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_24 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_sub_0_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_25 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_26 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 | _atomics_a_mask_sub_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_6 = atomics_a_mask_sub_sub_sub_1_2_6 & atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_27 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_6 = atomics_a_mask_sub_sub_sub_1_1_6 | _atomics_a_mask_sub_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_48 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_49 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_50 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_51 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_52 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_4_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_6 = atomics_a_mask_sub_sub_2_1_6 | _atomics_a_mask_sub_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_6 = atomics_a_mask_sub_sub_2_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_53 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_5_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_6 = atomics_a_mask_sub_sub_2_1_6 | _atomics_a_mask_sub_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_54 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_6_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_6 = atomics_a_mask_sub_sub_3_1_6 | _atomics_a_mask_sub_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_6 = atomics_a_mask_sub_sub_3_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_55 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_7_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_6 = atomics_a_mask_sub_sub_3_1_6 | _atomics_a_mask_sub_acc_T_55; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_96 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_96 = atomics_a_mask_size_6 & atomics_a_mask_eq_96; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_96 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_96; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_97 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_97 = atomics_a_mask_size_6 & atomics_a_mask_eq_97; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_97 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_97; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_98 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_98 = atomics_a_mask_size_6 & atomics_a_mask_eq_98; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_98 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_98; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_99 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_99 = atomics_a_mask_size_6 & atomics_a_mask_eq_99; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_99 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_99; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_100 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_100 = atomics_a_mask_size_6 & atomics_a_mask_eq_100; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_100 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_100; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_101 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_101 = atomics_a_mask_size_6 & atomics_a_mask_eq_101; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_101 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_101; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_102 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_102 = atomics_a_mask_size_6 & atomics_a_mask_eq_102; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_102 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_102; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_103 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_103 = atomics_a_mask_size_6 & atomics_a_mask_eq_103; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_103 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_103; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_104 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_104 = atomics_a_mask_size_6 & atomics_a_mask_eq_104; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_104 = atomics_a_mask_sub_4_1_6 | _atomics_a_mask_acc_T_104; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_105 = atomics_a_mask_sub_4_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_105 = atomics_a_mask_size_6 & atomics_a_mask_eq_105; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_105 = atomics_a_mask_sub_4_1_6 | _atomics_a_mask_acc_T_105; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_106 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_106 = atomics_a_mask_size_6 & atomics_a_mask_eq_106; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_106 = atomics_a_mask_sub_5_1_6 | _atomics_a_mask_acc_T_106; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_107 = atomics_a_mask_sub_5_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_107 = atomics_a_mask_size_6 & atomics_a_mask_eq_107; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_107 = atomics_a_mask_sub_5_1_6 | _atomics_a_mask_acc_T_107; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_108 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_108 = atomics_a_mask_size_6 & atomics_a_mask_eq_108; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_108 = atomics_a_mask_sub_6_1_6 | _atomics_a_mask_acc_T_108; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_109 = atomics_a_mask_sub_6_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_109 = atomics_a_mask_size_6 & atomics_a_mask_eq_109; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_109 = atomics_a_mask_sub_6_1_6 | _atomics_a_mask_acc_T_109; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_110 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_110 = atomics_a_mask_size_6 & atomics_a_mask_eq_110; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_110 = atomics_a_mask_sub_7_1_6 | _atomics_a_mask_acc_T_110; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_111 = atomics_a_mask_sub_7_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_111 = atomics_a_mask_size_6 & atomics_a_mask_eq_111; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_111 = atomics_a_mask_sub_7_1_6 | _atomics_a_mask_acc_T_111; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_6 = {atomics_a_mask_acc_97, atomics_a_mask_acc_96}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_6 = {atomics_a_mask_acc_99, atomics_a_mask_acc_98}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_lo_lo_hi_6, atomics_a_mask_lo_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_6 = {atomics_a_mask_acc_101, atomics_a_mask_acc_100}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_6 = {atomics_a_mask_acc_103, atomics_a_mask_acc_102}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_lo_hi_hi_6, atomics_a_mask_lo_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_6 = {atomics_a_mask_acc_105, atomics_a_mask_acc_104}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_6 = {atomics_a_mask_acc_107, atomics_a_mask_acc_106}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_hi_lo_hi_6, atomics_a_mask_hi_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_6 = {atomics_a_mask_acc_109, atomics_a_mask_acc_108}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_6 = {atomics_a_mask_acc_111, atomics_a_mask_acc_110}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_hi_hi_hi_6, atomics_a_mask_hi_hi_lo_6}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_418 = {1'h0, _atomics_legal_T_417}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_419 = _atomics_legal_T_418 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_420 = _atomics_legal_T_419; // @[Parameters.scala:137:46] wire _atomics_legal_T_421 = _atomics_legal_T_420 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_423 = {1'h0, _atomics_legal_T_422}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_424 = _atomics_legal_T_423 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_425 = _atomics_legal_T_424; // @[Parameters.scala:137:46] wire _atomics_legal_T_426 = _atomics_legal_T_425 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_428 = {1'h0, _atomics_legal_T_427}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_429 = _atomics_legal_T_428 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_430 = _atomics_legal_T_429; // @[Parameters.scala:137:46] wire _atomics_legal_T_431 = _atomics_legal_T_430 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_433 = {1'h0, _atomics_legal_T_432}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_434 = _atomics_legal_T_433 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_435 = _atomics_legal_T_434; // @[Parameters.scala:137:46] wire _atomics_legal_T_436 = _atomics_legal_T_435 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_438 = {1'h0, _atomics_legal_T_437}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_440 = _atomics_legal_T_439; // @[Parameters.scala:137:46] wire _atomics_legal_T_441 = _atomics_legal_T_440 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_442 = _atomics_legal_T_421 | _atomics_legal_T_426; // @[Parameters.scala:685:42] wire _atomics_legal_T_443 = _atomics_legal_T_442 | _atomics_legal_T_431; // @[Parameters.scala:685:42] wire _atomics_legal_T_444 = _atomics_legal_T_443 | _atomics_legal_T_436; // @[Parameters.scala:685:42] wire _atomics_legal_T_445 = _atomics_legal_T_444 | _atomics_legal_T_441; // @[Parameters.scala:685:42] wire _atomics_legal_T_446 = _atomics_legal_T_445; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_470 = _atomics_legal_T_446; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_449 = {1'h0, _atomics_legal_T_448}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_450 = _atomics_legal_T_449 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_451 = _atomics_legal_T_450; // @[Parameters.scala:137:46] wire _atomics_legal_T_452 = _atomics_legal_T_451 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_459 = {1'h0, _atomics_legal_T_458}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_460 = _atomics_legal_T_459 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_461 = _atomics_legal_T_460; // @[Parameters.scala:137:46] wire _atomics_legal_T_462 = _atomics_legal_T_461 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_464 = {1'h0, _atomics_legal_T_463}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_465 = _atomics_legal_T_464 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_466 = _atomics_legal_T_465; // @[Parameters.scala:137:46] wire _atomics_legal_T_467 = _atomics_legal_T_466 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_468 = _atomics_legal_T_462 | _atomics_legal_T_467; // @[Parameters.scala:685:42] wire _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_471 = _atomics_legal_T_470; // @[Parameters.scala:686:26] wire atomics_legal_7 = _atomics_legal_T_471 | _atomics_legal_T_469; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [15:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_7 = atomics_a_mask_sizeOH_7[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_sub_size_7 & atomics_a_mask_sub_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_7 = _atomics_a_mask_sub_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_28 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_sub_0_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_29 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_30 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 | _atomics_a_mask_sub_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_7 = atomics_a_mask_sub_sub_sub_1_2_7 & atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_31 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_7 = atomics_a_mask_sub_sub_sub_1_1_7 | _atomics_a_mask_sub_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_56 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_57 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_58 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_59 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_60 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_4_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_7 = atomics_a_mask_sub_sub_2_1_7 | _atomics_a_mask_sub_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_7 = atomics_a_mask_sub_sub_2_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_61 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_5_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_7 = atomics_a_mask_sub_sub_2_1_7 | _atomics_a_mask_sub_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_62 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_6_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_7 = atomics_a_mask_sub_sub_3_1_7 | _atomics_a_mask_sub_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_7 = atomics_a_mask_sub_sub_3_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_63 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_7_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_7 = atomics_a_mask_sub_sub_3_1_7 | _atomics_a_mask_sub_acc_T_63; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_112 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_112 = atomics_a_mask_size_7 & atomics_a_mask_eq_112; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_112 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_112; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_113 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_113 = atomics_a_mask_size_7 & atomics_a_mask_eq_113; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_113 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_113; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_114 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_114 = atomics_a_mask_size_7 & atomics_a_mask_eq_114; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_114 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_114; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_115 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_115 = atomics_a_mask_size_7 & atomics_a_mask_eq_115; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_115 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_115; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_116 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_116 = atomics_a_mask_size_7 & atomics_a_mask_eq_116; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_116 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_116; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_117 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_117 = atomics_a_mask_size_7 & atomics_a_mask_eq_117; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_117 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_117; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_118 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_118 = atomics_a_mask_size_7 & atomics_a_mask_eq_118; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_118 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_118; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_119 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_119 = atomics_a_mask_size_7 & atomics_a_mask_eq_119; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_119 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_119; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_120 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_120 = atomics_a_mask_size_7 & atomics_a_mask_eq_120; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_120 = atomics_a_mask_sub_4_1_7 | _atomics_a_mask_acc_T_120; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_121 = atomics_a_mask_sub_4_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_121 = atomics_a_mask_size_7 & atomics_a_mask_eq_121; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_121 = atomics_a_mask_sub_4_1_7 | _atomics_a_mask_acc_T_121; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_122 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_122 = atomics_a_mask_size_7 & atomics_a_mask_eq_122; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_122 = atomics_a_mask_sub_5_1_7 | _atomics_a_mask_acc_T_122; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_123 = atomics_a_mask_sub_5_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_123 = atomics_a_mask_size_7 & atomics_a_mask_eq_123; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_123 = atomics_a_mask_sub_5_1_7 | _atomics_a_mask_acc_T_123; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_124 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_124 = atomics_a_mask_size_7 & atomics_a_mask_eq_124; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_124 = atomics_a_mask_sub_6_1_7 | _atomics_a_mask_acc_T_124; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_125 = atomics_a_mask_sub_6_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_125 = atomics_a_mask_size_7 & atomics_a_mask_eq_125; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_125 = atomics_a_mask_sub_6_1_7 | _atomics_a_mask_acc_T_125; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_126 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_126 = atomics_a_mask_size_7 & atomics_a_mask_eq_126; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_126 = atomics_a_mask_sub_7_1_7 | _atomics_a_mask_acc_T_126; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_127 = atomics_a_mask_sub_7_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_127 = atomics_a_mask_size_7 & atomics_a_mask_eq_127; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_127 = atomics_a_mask_sub_7_1_7 | _atomics_a_mask_acc_T_127; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_7 = {atomics_a_mask_acc_113, atomics_a_mask_acc_112}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_7 = {atomics_a_mask_acc_115, atomics_a_mask_acc_114}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_lo_lo_hi_7, atomics_a_mask_lo_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_7 = {atomics_a_mask_acc_117, atomics_a_mask_acc_116}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_7 = {atomics_a_mask_acc_119, atomics_a_mask_acc_118}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_lo_hi_hi_7, atomics_a_mask_lo_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_7 = {atomics_a_mask_acc_121, atomics_a_mask_acc_120}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_7 = {atomics_a_mask_acc_123, atomics_a_mask_acc_122}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_hi_lo_hi_7, atomics_a_mask_hi_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_7 = {atomics_a_mask_acc_125, atomics_a_mask_acc_124}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_7 = {atomics_a_mask_acc_127, atomics_a_mask_acc_126}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_hi_hi_hi_7, atomics_a_mask_hi_hi_lo_7}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_477 = {1'h0, _atomics_legal_T_476}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_478 = _atomics_legal_T_477 & 41'h9C110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_479 = _atomics_legal_T_478; // @[Parameters.scala:137:46] wire _atomics_legal_T_480 = _atomics_legal_T_479 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_482 = {1'h0, _atomics_legal_T_481}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_483 = _atomics_legal_T_482 & 41'h9E101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_484 = _atomics_legal_T_483; // @[Parameters.scala:137:46] wire _atomics_legal_T_485 = _atomics_legal_T_484 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_487 = {1'h0, _atomics_legal_T_486}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_488 = _atomics_legal_T_487 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_489 = _atomics_legal_T_488; // @[Parameters.scala:137:46] wire _atomics_legal_T_490 = _atomics_legal_T_489 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_492 = {1'h0, _atomics_legal_T_491}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_493 = _atomics_legal_T_492 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_494 = _atomics_legal_T_493; // @[Parameters.scala:137:46] wire _atomics_legal_T_495 = _atomics_legal_T_494 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_497 = {1'h0, _atomics_legal_T_496}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_498 = _atomics_legal_T_497 & 41'h9E111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_499 = _atomics_legal_T_498; // @[Parameters.scala:137:46] wire _atomics_legal_T_500 = _atomics_legal_T_499 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_501 = _atomics_legal_T_480 | _atomics_legal_T_485; // @[Parameters.scala:685:42] wire _atomics_legal_T_502 = _atomics_legal_T_501 | _atomics_legal_T_490; // @[Parameters.scala:685:42] wire _atomics_legal_T_503 = _atomics_legal_T_502 | _atomics_legal_T_495; // @[Parameters.scala:685:42] wire _atomics_legal_T_504 = _atomics_legal_T_503 | _atomics_legal_T_500; // @[Parameters.scala:685:42] wire _atomics_legal_T_505 = _atomics_legal_T_504; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_529 = _atomics_legal_T_505; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_508 = {1'h0, _atomics_legal_T_507}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_509 = _atomics_legal_T_508 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_510 = _atomics_legal_T_509; // @[Parameters.scala:137:46] wire _atomics_legal_T_511 = _atomics_legal_T_510 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_518 = {1'h0, _atomics_legal_T_517}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_519 = _atomics_legal_T_518 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_520 = _atomics_legal_T_519; // @[Parameters.scala:137:46] wire _atomics_legal_T_521 = _atomics_legal_T_520 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_523 = {1'h0, _atomics_legal_T_522}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_524 = _atomics_legal_T_523 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_525 = _atomics_legal_T_524; // @[Parameters.scala:137:46] wire _atomics_legal_T_526 = _atomics_legal_T_525 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_527 = _atomics_legal_T_521 | _atomics_legal_T_526; // @[Parameters.scala:685:42] wire _atomics_legal_T_528 = _atomics_legal_T_527; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_530 = _atomics_legal_T_529; // @[Parameters.scala:686:26] wire atomics_legal_8 = _atomics_legal_T_530 | _atomics_legal_T_528; // @[Parameters.scala:684:54, :686:26] wire [15:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [15:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [3:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25; // @[OneHot.scala:65:{12,27}] wire [3:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[3:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_size_8 = atomics_a_mask_sizeOH_8[3]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_0_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire _atomics_a_mask_sub_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_sub_size_8 & atomics_a_mask_sub_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_sub_1_1_8 = _atomics_a_mask_sub_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_32 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_sub_0_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_33 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_2_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_34 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_2_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 | _atomics_a_mask_sub_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_sub_3_2_8 = atomics_a_mask_sub_sub_sub_1_2_8 & atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_sub_acc_T_35 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_3_1_8 = atomics_a_mask_sub_sub_sub_1_1_8 | _atomics_a_mask_sub_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_64 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_65 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_66 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_67 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_4_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_68 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_4_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_4_1_8 = atomics_a_mask_sub_sub_2_1_8 | _atomics_a_mask_sub_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_5_2_8 = atomics_a_mask_sub_sub_2_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_69 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_5_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_5_1_8 = atomics_a_mask_sub_sub_2_1_8 | _atomics_a_mask_sub_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_6_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_70 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_6_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_6_1_8 = atomics_a_mask_sub_sub_3_1_8 | _atomics_a_mask_sub_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_7_2_8 = atomics_a_mask_sub_sub_3_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_71 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_7_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_7_1_8 = atomics_a_mask_sub_sub_3_1_8 | _atomics_a_mask_sub_acc_T_71; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_128 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_128 = atomics_a_mask_size_8 & atomics_a_mask_eq_128; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_128 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_128; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_129 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_129 = atomics_a_mask_size_8 & atomics_a_mask_eq_129; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_129 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_129; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_130 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_130 = atomics_a_mask_size_8 & atomics_a_mask_eq_130; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_130 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_130; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_131 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_131 = atomics_a_mask_size_8 & atomics_a_mask_eq_131; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_131 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_131; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_132 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_132 = atomics_a_mask_size_8 & atomics_a_mask_eq_132; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_132 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_132; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_133 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_133 = atomics_a_mask_size_8 & atomics_a_mask_eq_133; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_133 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_133; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_134 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_134 = atomics_a_mask_size_8 & atomics_a_mask_eq_134; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_134 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_134; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_135 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_135 = atomics_a_mask_size_8 & atomics_a_mask_eq_135; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_135 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_135; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_136 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_136 = atomics_a_mask_size_8 & atomics_a_mask_eq_136; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_136 = atomics_a_mask_sub_4_1_8 | _atomics_a_mask_acc_T_136; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_137 = atomics_a_mask_sub_4_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_137 = atomics_a_mask_size_8 & atomics_a_mask_eq_137; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_137 = atomics_a_mask_sub_4_1_8 | _atomics_a_mask_acc_T_137; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_138 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_138 = atomics_a_mask_size_8 & atomics_a_mask_eq_138; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_138 = atomics_a_mask_sub_5_1_8 | _atomics_a_mask_acc_T_138; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_139 = atomics_a_mask_sub_5_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_139 = atomics_a_mask_size_8 & atomics_a_mask_eq_139; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_139 = atomics_a_mask_sub_5_1_8 | _atomics_a_mask_acc_T_139; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_140 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_140 = atomics_a_mask_size_8 & atomics_a_mask_eq_140; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_140 = atomics_a_mask_sub_6_1_8 | _atomics_a_mask_acc_T_140; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_141 = atomics_a_mask_sub_6_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_141 = atomics_a_mask_size_8 & atomics_a_mask_eq_141; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_141 = atomics_a_mask_sub_6_1_8 | _atomics_a_mask_acc_T_141; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_142 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_142 = atomics_a_mask_size_8 & atomics_a_mask_eq_142; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_142 = atomics_a_mask_sub_7_1_8 | _atomics_a_mask_acc_T_142; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_143 = atomics_a_mask_sub_7_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_143 = atomics_a_mask_size_8 & atomics_a_mask_eq_143; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_143 = atomics_a_mask_sub_7_1_8 | _atomics_a_mask_acc_T_143; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_lo_8 = {atomics_a_mask_acc_129, atomics_a_mask_acc_128}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_lo_hi_8 = {atomics_a_mask_acc_131, atomics_a_mask_acc_130}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_lo_lo_hi_8, atomics_a_mask_lo_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_lo_hi_lo_8 = {atomics_a_mask_acc_133, atomics_a_mask_acc_132}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_hi_8 = {atomics_a_mask_acc_135, atomics_a_mask_acc_134}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_lo_hi_hi_8, atomics_a_mask_lo_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_lo_8 = {atomics_a_mask_acc_137, atomics_a_mask_acc_136}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_lo_hi_8 = {atomics_a_mask_acc_139, atomics_a_mask_acc_138}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_hi_lo_hi_8, atomics_a_mask_hi_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_hi_lo_8 = {atomics_a_mask_acc_141, atomics_a_mask_acc_140}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_hi_8 = {atomics_a_mask_acc_143, atomics_a_mask_acc_142}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_hi_hi_hi_8, atomics_a_mask_hi_hi_lo_8}; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire _T_17 = req_uop_mem_cmd == 5'h4; // @[mshrs.scala:421:16, :439:75] wire _atomics_T; // @[mshrs.scala:439:75] assign _atomics_T = _T_17; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T; // @[package.scala:16:47] assign _io_mem_access_bits_T = _T_17; // @[package.scala:16:47] wire _io_mem_access_bits_T_24; // @[package.scala:16:47] assign _io_mem_access_bits_T_24 = _T_17; // @[package.scala:16:47] wire _send_resp_T_7; // @[package.scala:16:47] assign _send_resp_T_7 = _T_17; // @[package.scala:16:47] wire [2:0] _GEN_9 = _atomics_T ? 3'h3 : 3'h0; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_opcode; // @[mshrs.scala:439:75] assign _atomics_T_1_opcode = _GEN_9; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_1_param; // @[mshrs.scala:439:75] assign _atomics_T_1_param = _GEN_9; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire [2:0] _atomics_T_1_source = _atomics_T ? 3'h5 : 3'h0; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [15:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 16'h0; // @[Edges.scala:534:17] wire [127:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 128'h0; // @[Edges.scala:534:17] wire _T_18 = req_uop_mem_cmd == 5'h9; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_2; // @[mshrs.scala:439:75] assign _atomics_T_2 = _T_18; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_1; // @[package.scala:16:47] assign _io_mem_access_bits_T_1 = _T_18; // @[package.scala:16:47] wire _io_mem_access_bits_T_25; // @[package.scala:16:47] assign _io_mem_access_bits_T_25 = _T_18; // @[package.scala:16:47] wire _send_resp_T_8; // @[package.scala:16:47] assign _send_resp_T_8 = _T_18; // @[package.scala:16:47] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire [2:0] _atomics_T_3_source = _atomics_T_2 ? 3'h5 : _atomics_T_1_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire _T_19 = req_uop_mem_cmd == 5'hA; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_4; // @[mshrs.scala:439:75] assign _atomics_T_4 = _T_19; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_2; // @[package.scala:16:47] assign _io_mem_access_bits_T_2 = _T_19; // @[package.scala:16:47] wire _io_mem_access_bits_T_26; // @[package.scala:16:47] assign _io_mem_access_bits_T_26 = _T_19; // @[package.scala:16:47] wire _send_resp_T_9; // @[package.scala:16:47] assign _send_resp_T_9 = _T_19; // @[package.scala:16:47] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire [2:0] _atomics_T_5_source = _atomics_T_4 ? 3'h5 : _atomics_T_3_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire _T_20 = req_uop_mem_cmd == 5'hB; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_6; // @[mshrs.scala:439:75] assign _atomics_T_6 = _T_20; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_3; // @[package.scala:16:47] assign _io_mem_access_bits_T_3 = _T_20; // @[package.scala:16:47] wire _io_mem_access_bits_T_27; // @[package.scala:16:47] assign _io_mem_access_bits_T_27 = _T_20; // @[package.scala:16:47] wire _send_resp_T_10; // @[package.scala:16:47] assign _send_resp_T_10 = _T_20; // @[package.scala:16:47] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire [2:0] _atomics_T_7_source = _atomics_T_6 ? 3'h5 : _atomics_T_5_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [15:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [127:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire _T_24 = req_uop_mem_cmd == 5'h8; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_8; // @[mshrs.scala:439:75] assign _atomics_T_8 = _T_24; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_7; // @[package.scala:16:47] assign _io_mem_access_bits_T_7 = _T_24; // @[package.scala:16:47] wire _io_mem_access_bits_T_31; // @[package.scala:16:47] assign _io_mem_access_bits_T_31 = _T_24; // @[package.scala:16:47] wire _send_resp_T_14; // @[package.scala:16:47] assign _send_resp_T_14 = _T_24; // @[package.scala:16:47] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_9_source = _atomics_T_8 ? 3'h5 : _atomics_T_7_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire _T_25 = req_uop_mem_cmd == 5'hC; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_10; // @[mshrs.scala:439:75] assign _atomics_T_10 = _T_25; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_8; // @[package.scala:16:47] assign _io_mem_access_bits_T_8 = _T_25; // @[package.scala:16:47] wire _io_mem_access_bits_T_32; // @[package.scala:16:47] assign _io_mem_access_bits_T_32 = _T_25; // @[package.scala:16:47] wire _send_resp_T_15; // @[package.scala:16:47] assign _send_resp_T_15 = _T_25; // @[package.scala:16:47] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_11_source = _atomics_T_10 ? 3'h5 : _atomics_T_9_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire _T_26 = req_uop_mem_cmd == 5'hD; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_12; // @[mshrs.scala:439:75] assign _atomics_T_12 = _T_26; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_9; // @[package.scala:16:47] assign _io_mem_access_bits_T_9 = _T_26; // @[package.scala:16:47] wire _io_mem_access_bits_T_33; // @[package.scala:16:47] assign _io_mem_access_bits_T_33 = _T_26; // @[package.scala:16:47] wire _send_resp_T_16; // @[package.scala:16:47] assign _send_resp_T_16 = _T_26; // @[package.scala:16:47] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_13_source = _atomics_T_12 ? 3'h5 : _atomics_T_11_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire _T_27 = req_uop_mem_cmd == 5'hE; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_14; // @[mshrs.scala:439:75] assign _atomics_T_14 = _T_27; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_10; // @[package.scala:16:47] assign _io_mem_access_bits_T_10 = _T_27; // @[package.scala:16:47] wire _io_mem_access_bits_T_34; // @[package.scala:16:47] assign _io_mem_access_bits_T_34 = _T_27; // @[package.scala:16:47] wire _send_resp_T_17; // @[package.scala:16:47] assign _send_resp_T_17 = _T_27; // @[package.scala:16:47] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[mshrs.scala:439:75] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[mshrs.scala:439:75] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire [2:0] _atomics_T_15_source = _atomics_T_14 ? 3'h5 : _atomics_T_13_source; // @[mshrs.scala:439:75] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [15:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [127:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire _T_28 = req_uop_mem_cmd == 5'hF; // @[mshrs.scala:421:16, :439:75] wire _atomics_T_16; // @[mshrs.scala:439:75] assign _atomics_T_16 = _T_28; // @[mshrs.scala:439:75] wire _io_mem_access_bits_T_11; // @[package.scala:16:47] assign _io_mem_access_bits_T_11 = _T_28; // @[package.scala:16:47] wire _io_mem_access_bits_T_35; // @[package.scala:16:47] assign _io_mem_access_bits_T_35 = _T_28; // @[package.scala:16:47] wire _send_resp_T_18; // @[package.scala:16:47] assign _send_resp_T_18 = _T_28; // @[package.scala:16:47] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[mshrs.scala:439:75] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[mshrs.scala:439:75] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire [2:0] atomics_source = _atomics_T_16 ? 3'h5 : _atomics_T_15_source; // @[mshrs.scala:439:75] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [15:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [127:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17]

Generate the Verilog code corresponding to this FIRRTL code module ALUUnit : input clock : Clock input reset : Reset output io : { flip kill : UInt<1>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, ftq_info : { valid : UInt<1>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<8>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>}[2], pred_data : UInt<1>, imm_data : UInt<64>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, brinfo : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}} connect io.resp.bits.fflags.valid, UInt<1>(0h0) invalidate io.resp.bits.fflags.bits connect io.resp.bits.predicated, UInt<1>(0h0) connect io.req.ready, UInt<1>(0h1) node _block_pc_T = not(io.req.bits.ftq_info[0].pc) node _block_pc_T_1 = or(_block_pc_T, UInt<6>(0h3f)) node block_pc = not(_block_pc_T_1) node _uop_pc_T = or(block_pc, io.req.bits.uop.pc_lob) node _uop_pc_T_1 = mux(io.req.bits.uop.edge_inst, UInt<2>(0h2), UInt<1>(0h0)) node _uop_pc_T_2 = sub(_uop_pc_T, _uop_pc_T_1) node uop_pc = tail(_uop_pc_T_2, 1) node _op1_shamt_T = eq(io.req.bits.uop.fcn_op, UInt<1>(0h0)) node _op1_shamt_T_1 = bits(io.req.bits.uop.pimm, 2, 1) node op1_shamt = mux(_op1_shamt_T, _op1_shamt_T_1, UInt<1>(0h0)) node _op1_shl_T = eq(io.req.bits.uop.fcn_dw, UInt<1>(0h0)) node _op1_shl_T_1 = bits(io.req.bits.rs1_data, 31, 0) node _op1_shl_T_2 = mux(_op1_shl_T, _op1_shl_T_1, io.req.bits.rs1_data) node op1_shl = dshl(_op1_shl_T_2, op1_shamt) node _op1_data_T = bits(uop_pc, 39, 39) node _op1_data_T_1 = mux(_op1_data_T, UInt<24>(0hffffff), UInt<24>(0h0)) node _op1_data_T_2 = cat(_op1_data_T_1, uop_pc) node _op1_data_T_3 = eq(UInt<2>(0h0), io.req.bits.uop.op1_sel) node _op1_data_T_4 = mux(_op1_data_T_3, io.req.bits.rs1_data, UInt<1>(0h0)) node _op1_data_T_5 = eq(UInt<2>(0h2), io.req.bits.uop.op1_sel) node _op1_data_T_6 = mux(_op1_data_T_5, _op1_data_T_2, _op1_data_T_4) node _op1_data_T_7 = eq(UInt<2>(0h3), io.req.bits.uop.op1_sel) node op1_data = mux(_op1_data_T_7, op1_shl, _op1_data_T_6) node _op2_oh_T = bits(io.req.bits.uop.op2_sel, 0, 0) node _op2_oh_T_1 = mux(_op2_oh_T, io.req.bits.rs2_data, io.req.bits.imm_data) node _op2_oh_T_2 = bits(_op2_oh_T_1, 5, 0) node op2_oh = dshl(UInt<1>(0h1), _op2_oh_T_2) node _op2_data_T = bits(io.req.bits.uop.prs1, 4, 0) node _op2_data_T_1 = mux(io.req.bits.uop.is_rvc, UInt<2>(0h2), UInt<3>(0h4)) node _op2_data_T_2 = eq(UInt<3>(0h1), io.req.bits.uop.op2_sel) node _op2_data_T_3 = mux(_op2_data_T_2, io.req.bits.imm_data, UInt<1>(0h0)) node _op2_data_T_4 = eq(UInt<3>(0h4), io.req.bits.uop.op2_sel) node _op2_data_T_5 = mux(_op2_data_T_4, _op2_data_T, _op2_data_T_3) node _op2_data_T_6 = eq(UInt<3>(0h0), io.req.bits.uop.op2_sel) node _op2_data_T_7 = mux(_op2_data_T_6, io.req.bits.rs2_data, _op2_data_T_5) node _op2_data_T_8 = eq(UInt<3>(0h3), io.req.bits.uop.op2_sel) node _op2_data_T_9 = mux(_op2_data_T_8, _op2_data_T_1, _op2_data_T_7) node _op2_data_T_10 = eq(UInt<3>(0h5), io.req.bits.uop.op2_sel) node _op2_data_T_11 = mux(_op2_data_T_10, op2_oh, _op2_data_T_9) node _op2_data_T_12 = eq(UInt<3>(0h6), io.req.bits.uop.op2_sel) node op2_data = mux(_op2_data_T_12, op2_oh, _op2_data_T_11) inst alu of ALU connect alu.clock, clock connect alu.reset, reset connect alu.io.in1, op1_data connect alu.io.in2, op2_data connect alu.io.fn, io.req.bits.uop.fcn_op node _alu_io_dw_T = eq(io.req.bits.uop.op1_sel, UInt<2>(0h3)) node _alu_io_dw_T_1 = mux(_alu_io_dw_T, UInt<1>(0h1), io.req.bits.uop.fcn_dw) connect alu.io.dw, _alu_io_dw_T_1 node br_eq = eq(io.req.bits.rs1_data, io.req.bits.rs2_data) node br_ltu = lt(io.req.bits.rs1_data, io.req.bits.rs2_data) node _br_lt_T = bits(io.req.bits.rs1_data, 63, 63) node _br_lt_T_1 = bits(io.req.bits.rs2_data, 63, 63) node _br_lt_T_2 = xor(_br_lt_T, _br_lt_T_1) node _br_lt_T_3 = not(_br_lt_T_2) node _br_lt_T_4 = and(_br_lt_T_3, br_ltu) node _br_lt_T_5 = bits(io.req.bits.rs1_data, 63, 63) node _br_lt_T_6 = bits(io.req.bits.rs2_data, 63, 63) node _br_lt_T_7 = not(_br_lt_T_6) node _br_lt_T_8 = and(_br_lt_T_5, _br_lt_T_7) node br_lt = or(_br_lt_T_4, _br_lt_T_8) node _pc_sel_T = eq(br_eq, UInt<1>(0h0)) node _pc_sel_T_1 = mux(_pc_sel_T, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_2 = mux(br_eq, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_3 = eq(br_lt, UInt<1>(0h0)) node _pc_sel_T_4 = mux(_pc_sel_T_3, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_5 = eq(br_ltu, UInt<1>(0h0)) node _pc_sel_T_6 = mux(_pc_sel_T_5, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_7 = mux(br_lt, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_8 = mux(br_ltu, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_9 = eq(UInt<4>(0h0), io.req.bits.uop.br_type) node _pc_sel_T_10 = mux(_pc_sel_T_9, UInt<2>(0h0), UInt<2>(0h0)) node _pc_sel_T_11 = eq(UInt<4>(0h1), io.req.bits.uop.br_type) node _pc_sel_T_12 = mux(_pc_sel_T_11, _pc_sel_T_1, _pc_sel_T_10) node _pc_sel_T_13 = eq(UInt<4>(0h2), io.req.bits.uop.br_type) node _pc_sel_T_14 = mux(_pc_sel_T_13, _pc_sel_T_2, _pc_sel_T_12) node _pc_sel_T_15 = eq(UInt<4>(0h3), io.req.bits.uop.br_type) node _pc_sel_T_16 = mux(_pc_sel_T_15, _pc_sel_T_4, _pc_sel_T_14) node _pc_sel_T_17 = eq(UInt<4>(0h4), io.req.bits.uop.br_type) node _pc_sel_T_18 = mux(_pc_sel_T_17, _pc_sel_T_6, _pc_sel_T_16) node _pc_sel_T_19 = eq(UInt<4>(0h5), io.req.bits.uop.br_type) node _pc_sel_T_20 = mux(_pc_sel_T_19, _pc_sel_T_7, _pc_sel_T_18) node _pc_sel_T_21 = eq(UInt<4>(0h6), io.req.bits.uop.br_type) node _pc_sel_T_22 = mux(_pc_sel_T_21, _pc_sel_T_8, _pc_sel_T_20) node _pc_sel_T_23 = eq(UInt<4>(0h7), io.req.bits.uop.br_type) node _pc_sel_T_24 = mux(_pc_sel_T_23, UInt<2>(0h1), _pc_sel_T_22) node _pc_sel_T_25 = eq(UInt<4>(0h8), io.req.bits.uop.br_type) node pc_sel = mux(_pc_sel_T_25, UInt<2>(0h2), _pc_sel_T_24) node _is_taken_T = neq(io.req.bits.uop.br_type, UInt<3>(0h3)) node _is_taken_T_1 = and(io.req.valid, _is_taken_T) node _is_taken_T_2 = neq(pc_sel, UInt<2>(0h0)) node is_taken = and(_is_taken_T_1, _is_taken_T_2) node _target_offset_T = bits(io.req.bits.imm_data, 20, 0) node target_offset = asSInt(_target_offset_T) wire mispredict : UInt<1> connect mispredict, UInt<1>(0h0) node _is_br_T = eq(io.req.bits.uop.br_type, UInt<4>(0h1)) node _is_br_T_1 = eq(io.req.bits.uop.br_type, UInt<4>(0h2)) node _is_br_T_2 = eq(io.req.bits.uop.br_type, UInt<4>(0h3)) node _is_br_T_3 = eq(io.req.bits.uop.br_type, UInt<4>(0h4)) node _is_br_T_4 = eq(io.req.bits.uop.br_type, UInt<4>(0h5)) node _is_br_T_5 = eq(io.req.bits.uop.br_type, UInt<4>(0h6)) node _is_br_T_6 = or(_is_br_T, _is_br_T_1) node _is_br_T_7 = or(_is_br_T_6, _is_br_T_2) node _is_br_T_8 = or(_is_br_T_7, _is_br_T_3) node _is_br_T_9 = or(_is_br_T_8, _is_br_T_4) node _is_br_T_10 = or(_is_br_T_9, _is_br_T_5) node _is_br_T_11 = and(io.req.valid, _is_br_T_10) node _is_br_T_12 = eq(io.req.bits.uop.is_sfb, UInt<1>(0h0)) node is_br = and(_is_br_T_11, _is_br_T_12) node _is_jal_T = eq(io.req.bits.uop.br_type, UInt<4>(0h7)) node is_jal = and(io.req.valid, _is_jal_T) node _is_jalr_T = eq(io.req.bits.uop.br_type, UInt<4>(0h8)) node is_jalr = and(io.req.valid, _is_jalr_T) node jalr_target_base = asSInt(io.req.bits.rs1_data) wire jalr_target_xlen : UInt<64> node _jalr_target_xlen_T = add(jalr_target_base, target_offset) node _jalr_target_xlen_T_1 = tail(_jalr_target_xlen_T, 1) node _jalr_target_xlen_T_2 = asSInt(_jalr_target_xlen_T_1) node _jalr_target_xlen_T_3 = asUInt(_jalr_target_xlen_T_2) connect jalr_target_xlen, _jalr_target_xlen_T_3 node _jalr_target_a_T = asSInt(jalr_target_xlen) node jalr_target_a = shr(_jalr_target_a_T, 39) node _jalr_target_msb_T = eq(jalr_target_a, asSInt(UInt<1>(0h0))) node _jalr_target_msb_T_1 = eq(jalr_target_a, asSInt(UInt<1>(0h1))) node _jalr_target_msb_T_2 = or(_jalr_target_msb_T, _jalr_target_msb_T_1) node _jalr_target_msb_T_3 = bits(jalr_target_xlen, 39, 39) node _jalr_target_msb_T_4 = bits(jalr_target_xlen, 38, 38) node _jalr_target_msb_T_5 = eq(_jalr_target_msb_T_4, UInt<1>(0h0)) node jalr_target_msb = mux(_jalr_target_msb_T_2, _jalr_target_msb_T_3, _jalr_target_msb_T_5) node _jalr_target_T = bits(jalr_target_xlen, 38, 0) node _jalr_target_T_1 = cat(jalr_target_msb, _jalr_target_T) node _jalr_target_T_2 = asSInt(_jalr_target_T_1) node _jalr_target_T_3 = and(_jalr_target_T_2, asSInt(UInt<2>(0h2))) node _jalr_target_T_4 = asSInt(_jalr_target_T_3) node jalr_target = asUInt(_jalr_target_T_4) node _cfi_idx_T = eq(io.req.bits.ftq_info[0].entry.start_bank, UInt<1>(0h1)) node _cfi_idx_T_1 = shl(UInt<1>(0h1), 3) node _cfi_idx_T_2 = mux(_cfi_idx_T, _cfi_idx_T_1, UInt<1>(0h0)) node _cfi_idx_T_3 = xor(io.req.bits.uop.pc_lob, _cfi_idx_T_2) node cfi_idx = bits(_cfi_idx_T_3, 3, 1) node _T = or(is_br, is_jalr) when _T : node _T_1 = eq(pc_sel, UInt<2>(0h0)) when _T_1 : connect mispredict, io.req.bits.uop.taken node _T_2 = eq(pc_sel, UInt<2>(0h1)) when _T_2 : node _mispredict_T = eq(io.req.bits.uop.taken, UInt<1>(0h0)) connect mispredict, _mispredict_T node _T_3 = eq(pc_sel, UInt<2>(0h2)) when _T_3 : node _mispredict_T_1 = eq(io.req.bits.ftq_info[1].valid, UInt<1>(0h0)) node _mispredict_T_2 = neq(io.req.bits.ftq_info[1].pc, jalr_target) node _mispredict_T_3 = or(_mispredict_T_1, _mispredict_T_2) node _mispredict_T_4 = eq(io.req.bits.ftq_info[0].entry.cfi_idx.valid, UInt<1>(0h0)) node _mispredict_T_5 = or(_mispredict_T_3, _mispredict_T_4) node _mispredict_T_6 = neq(io.req.bits.ftq_info[0].entry.cfi_idx.bits, cfi_idx) node _mispredict_T_7 = or(_mispredict_T_5, _mispredict_T_6) connect mispredict, _mispredict_T_7 wire brinfo : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}} node _brinfo_valid_T = or(is_br, is_jalr) connect brinfo.valid, _brinfo_valid_T connect brinfo.bits.mispredict, mispredict connect brinfo.bits.uop, io.req.bits.uop node _brinfo_bits_cfi_type_T = mux(is_br, UInt<3>(0h1), UInt<3>(0h0)) node _brinfo_bits_cfi_type_T_1 = mux(is_jalr, UInt<3>(0h3), _brinfo_bits_cfi_type_T) connect brinfo.bits.cfi_type, _brinfo_bits_cfi_type_T_1 connect brinfo.bits.taken, is_taken connect brinfo.bits.pc_sel, pc_sel invalidate brinfo.bits.jalr_target connect brinfo.bits.jalr_target, jalr_target connect brinfo.bits.target_offset, target_offset connect io.brinfo, brinfo node _alu_out_T = eq(io.req.bits.uop.br_type, UInt<4>(0h0)) node _alu_out_T_1 = and(_alu_out_T, io.req.bits.uop.is_sfb) node _alu_out_T_2 = and(_alu_out_T_1, UInt<1>(0h1)) node _alu_out_T_3 = and(_alu_out_T_2, io.req.bits.pred_data) node _alu_out_T_4 = mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data) node _alu_out_T_5 = mux(io.req.bits.uop.is_mov, io.req.bits.rs2_data, alu.io.out) node alu_out = mux(_alu_out_T_3, _alu_out_T_4, _alu_out_T_5) connect io.resp.valid, io.req.valid connect io.resp.bits.uop, io.req.bits.uop node _io_resp_bits_data_T = neq(io.req.bits.uop.br_type, UInt<4>(0h0)) node _io_resp_bits_data_T_1 = and(_io_resp_bits_data_T, io.req.bits.uop.is_sfb) node _io_resp_bits_data_T_2 = and(_io_resp_bits_data_T_1, UInt<1>(0h1)) node _io_resp_bits_data_T_3 = eq(pc_sel, UInt<2>(0h1)) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_2, _io_resp_bits_data_T_3, alu_out) connect io.resp.bits.data, _io_resp_bits_data_T_4 node _io_resp_bits_predicated_T = eq(io.req.bits.uop.br_type, UInt<4>(0h0)) node _io_resp_bits_predicated_T_1 = and(_io_resp_bits_predicated_T, io.req.bits.uop.is_sfb) node _io_resp_bits_predicated_T_2 = and(_io_resp_bits_predicated_T_1, UInt<1>(0h1)) node _io_resp_bits_predicated_T_3 = and(_io_resp_bits_predicated_T_2, io.req.bits.pred_data) connect io.resp.bits.predicated, _io_resp_bits_predicated_T_3 node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(io.resp.ready, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at functional-unit.scala:292 assert(io.resp.ready)\n") : printf assert(clock, io.resp.ready, UInt<1>(0h1), "") : assert

module ALUUnit( // @[functional-unit.scala:133:7] input clock, // @[functional-unit.scala:133:7] input reset, // @[functional-unit.scala:133:7] input io_kill, // @[functional-unit.scala:105:14] input io_req_valid, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_type, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_eret, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rocc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:105:14] input io_req_bits_uop_taken, // @[functional-unit.scala:105:14] input io_req_bits_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_op2_sel, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_req_bits_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:105:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:105:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:105:14] input io_req_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_fcn_op, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_typ, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_imm_data, // @[functional-unit.scala:105:14] output io_resp_valid, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:105:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_type, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_eret, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rocc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_mov, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:105:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:105:14] output io_resp_bits_uop_imm_rename, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_imm_sel, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_pimm, // @[functional-unit.scala:105:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_op1_sel, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_op2_sel, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:105:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:105:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_fcn_op, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_fp_rm, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_typ, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_data, // @[functional-unit.scala:105:14] input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:105:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_type, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_eret, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rocc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:105:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:105:14] input io_brupdate_b2_taken, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:105:14] input [20:0] io_brupdate_b2_target_offset // @[functional-unit.scala:105:14] ); wire [63:0] _alu_io_out; // @[functional-unit.scala:173:19] wire io_kill_0 = io_kill; // @[functional-unit.scala:133:7] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:133:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_br_type_0 = io_req_bits_uop_br_type; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_eret_0 = io_req_bits_uop_is_eret; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_mov_0 = io_req_bits_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:133:7] wire io_req_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_pimm_0 = io_req_bits_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:133:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:133:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_imm_data_0 = io_req_bits_imm_data; // @[functional-unit.scala:133:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:133:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:133:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:133:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:133:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:133:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:133:7] wire [3:0] _cfi_idx_T_1 = 4'h8; // @[functional-unit.scala:234:90] wire [39:0] _block_pc_T = 40'hFFFFFFFFFF; // @[util.scala:245:{7,11}] wire [39:0] _block_pc_T_1 = 40'hFFFFFFFFFF; // @[util.scala:245:{7,11}] wire [1:0] _pc_sel_T_10 = 2'h0; // @[functional-unit.scala:188:48] wire [3:0] _cfi_idx_T_2 = 4'h0; // @[functional-unit.scala:234:35] wire [4:0] io_req_bits_ftq_info_0_entry_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_0_ghist_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_1_entry_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_1_ghist_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_resp_bits_fflags_bits = 5'h0; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_ftq_info_0_entry_ras_top = 40'h0; // @[util.scala:245:5] wire [39:0] io_req_bits_ftq_info_0_pc = 40'h0; // @[util.scala:245:5] wire [39:0] io_req_bits_ftq_info_1_entry_ras_top = 40'h0; // @[util.scala:245:5] wire [39:0] io_req_bits_ftq_info_1_pc = 40'h0; // @[util.scala:245:5] wire [39:0] block_pc = 40'h0; // @[util.scala:245:5] wire [7:0] io_req_bits_ftq_info_0_entry_br_mask = 8'h0; // @[functional-unit.scala:105:14, :133:7] wire [7:0] io_req_bits_ftq_info_1_entry_br_mask = 8'h0; // @[functional-unit.scala:105:14, :133:7] wire [2:0] io_req_bits_ftq_info_0_entry_cfi_idx_bits = 3'h0; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_ftq_info_0_entry_cfi_type = 3'h0; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_ftq_info_1_entry_cfi_idx_bits = 3'h0; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_ftq_info_1_entry_cfi_type = 3'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_start_bank = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_start_bank = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:133:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:133:7] wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:133:7] wire _cfi_idx_T = 1'h0; // @[functional-unit.scala:234:77] wire _alu_out_T_3 = 1'h0; // @[functional-unit.scala:285:51] wire _io_resp_bits_predicated_T_3 = 1'h0; // @[functional-unit.scala:291:60] wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_ftq_info_0_ghist_old_history = 64'h0; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_ftq_info_1_ghist_old_history = 64'h0; // @[functional-unit.scala:133:7] wire io_req_ready = 1'h1; // @[functional-unit.scala:133:7] wire io_resp_ready = 1'h1; // @[functional-unit.scala:133:7] wire _mispredict_T_1 = 1'h1; // @[functional-unit.scala:245:22] wire _mispredict_T_3 = 1'h1; // @[functional-unit.scala:245:53] wire _mispredict_T_4 = 1'h1; // @[functional-unit.scala:247:22] wire _mispredict_T_5 = 1'h1; // @[functional-unit.scala:246:67] wire _mispredict_T_7 = 1'h1; // @[functional-unit.scala:247:67] wire io_resp_valid_0 = io_req_valid_0; // @[functional-unit.scala:133:7] wire [31:0] io_resp_bits_uop_inst_0 = io_req_bits_uop_inst_0; // @[functional-unit.scala:133:7] wire [31:0] brinfo_bits_uop_inst = io_req_bits_uop_inst_0; // @[functional-unit.scala:133:7, :252:20] wire [31:0] io_resp_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7] wire [31:0] brinfo_bits_uop_debug_inst = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_rvc = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7, :252:20] wire [39:0] io_resp_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7] wire [39:0] brinfo_bits_uop_debug_pc = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_0 = io_req_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_1 = io_req_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_2 = io_req_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_3 = io_req_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_0 = io_req_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_1 = io_req_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_2 = io_req_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_3 = io_req_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_4 = io_req_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_5 = io_req_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_6 = io_req_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_7 = io_req_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_8 = io_req_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_9 = io_req_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued = io_req_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued_partial_agen = io_req_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued_partial_dgen = io_req_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_iw_p1_speculative_child = io_req_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_iw_p2_speculative_child = io_req_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p1_bypass_hint = io_req_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p2_bypass_hint = io_req_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p3_bypass_hint = io_req_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_dis_col_sel = io_req_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [15:0] io_resp_bits_uop_br_mask_0 = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:133:7] wire [15:0] brinfo_bits_uop_br_mask = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_br_tag_0 = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_br_tag = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_br_type_0 = io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_br_type = io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sfb = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_fence_0 = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_fence = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_fencei = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sfence = io_req_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_amo_0 = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_amo = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_eret_0 = io_req_bits_uop_is_eret_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_eret = io_req_bits_uop_is_eret_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_rocc = io_req_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_mov_0 = io_req_bits_uop_is_mov_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_mov = io_req_bits_uop_is_mov_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ftq_idx = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_edge_inst = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7] wire [5:0] _cfi_idx_T_3 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7, :234:30] wire [5:0] brinfo_bits_uop_pc_lob = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_taken_0 = io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_taken = io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_imm_rename = io_req_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_imm_sel = io_req_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_pimm_0 = io_req_bits_uop_pimm_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_pimm = io_req_bits_uop_pimm_0; // @[functional-unit.scala:133:7, :252:20] wire [19:0] io_resp_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7] wire [19:0] brinfo_bits_uop_imm_packed = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_op1_sel = io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_op2_sel = io_req_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ldst = io_req_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_wen = io_req_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren1 = io_req_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren2 = io_req_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren3 = io_req_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_swap12 = io_req_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_swap23 = io_req_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_ctrl_typeTagIn = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_ctrl_typeTagOut = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fromint = io_req_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_toint = io_req_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fastpipe = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fma = io_req_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_div = io_req_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_sqrt = io_req_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_wflags = io_req_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_vec = io_req_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_rob_idx = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ldq_idx = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_stq_idx = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_rxq_idx = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_pdst_0 = io_req_bits_uop_pdst_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_pdst = io_req_bits_uop_pdst_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs1_0 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs1 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs2_0 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs2 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs3_0 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs3 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ppred_0 = io_req_bits_uop_ppred_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ppred = io_req_bits_uop_ppred_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs1_busy = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs2_busy = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs3_busy = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_ppred_busy = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_stale_pdst = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_exception_0 = io_req_bits_uop_exception_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_exception = io_req_bits_uop_exception_0; // @[functional-unit.scala:133:7, :252:20] wire [63:0] io_resp_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7] wire [63:0] brinfo_bits_uop_exc_cause = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_mem_cmd = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_mem_size_0 = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_mem_size = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_mem_signed = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_uses_ldq = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_uses_stq = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_unique_0 = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_unique = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_flush_on_commit = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_csr_cmd = io_req_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_ldst_0 = io_req_bits_uop_ldst_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_ldst = io_req_bits_uop_ldst_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs1_0 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs1 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs2_0 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs2 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs3_0 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs3 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_dst_rtype = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_lrs1_rtype = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_lrs2_rtype = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_frs3_en = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fcn_dw = io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_fcn_op = io_req_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_val_0 = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_val = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_fp_rm = io_req_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_typ = io_req_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_bp_debug_if = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_debug_fsrc = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_debug_tsrc = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7, :252:20] wire [63:0] jalr_target_base = io_req_bits_rs1_data_0; // @[functional-unit.scala:133:7, :229:47] wire [63:0] _io_resp_bits_data_T_4; // @[functional-unit.scala:290:27] wire brinfo_valid; // @[functional-unit.scala:252:20] wire brinfo_bits_mispredict; // @[functional-unit.scala:252:20] wire brinfo_bits_taken; // @[functional-unit.scala:252:20] wire [2:0] brinfo_bits_cfi_type; // @[functional-unit.scala:252:20] wire [1:0] brinfo_bits_pc_sel; // @[functional-unit.scala:252:20] wire [39:0] brinfo_bits_jalr_target; // @[functional-unit.scala:252:20] wire [20:0] brinfo_bits_target_offset; // @[functional-unit.scala:252:20] wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [31:0] io_brinfo_bits_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_brinfo_bits_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_brinfo_bits_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [15:0] io_brinfo_bits_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_br_type; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_fence; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_amo; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_eret; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_taken; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_brinfo_bits_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_op2_sel; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_rob_idx; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ppred; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_brinfo_bits_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_mem_size; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_unique; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_mispredict; // @[functional-unit.scala:133:7] wire io_brinfo_bits_taken; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_cfi_type; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_pc_sel; // @[functional-unit.scala:133:7] wire [39:0] io_brinfo_bits_jalr_target; // @[functional-unit.scala:133:7] wire [20:0] io_brinfo_bits_target_offset; // @[functional-unit.scala:133:7] wire io_brinfo_valid; // @[functional-unit.scala:133:7] wire [39:0] _uop_pc_T = {34'h0, io_req_bits_uop_pc_lob_0}; // @[functional-unit.scala:133:7, :150:26] wire [1:0] _uop_pc_T_1 = {io_req_bits_uop_edge_inst_0, 1'h0}; // @[functional-unit.scala:133:7, :150:45] wire [40:0] _uop_pc_T_2 = {1'h0, _uop_pc_T} - {39'h0, _uop_pc_T_1}; // @[functional-unit.scala:150:{26,40,45}] wire [39:0] uop_pc = _uop_pc_T_2[39:0]; // @[functional-unit.scala:150:40] wire _op1_shamt_T = io_req_bits_uop_fcn_op_0 == 5'h0; // @[functional-unit.scala:133:7, :151:34] wire [1:0] _op1_shamt_T_1 = io_req_bits_uop_pimm_0[2:1]; // @[functional-unit.scala:133:7, :151:66] wire [1:0] op1_shamt = _op1_shamt_T ? _op1_shamt_T_1 : 2'h0; // @[functional-unit.scala:151:{22,34,66}] wire _op1_shl_T = ~io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :152:32] wire [31:0] _op1_shl_T_1 = io_req_bits_rs1_data_0[31:0]; // @[functional-unit.scala:133:7, :153:25] wire [63:0] _op1_shl_T_2 = _op1_shl_T ? {32'h0, _op1_shl_T_1} : io_req_bits_rs1_data_0; // @[functional-unit.scala:133:7, :152:{20,32}, :153:25] wire [66:0] op1_shl = {3'h0, _op1_shl_T_2} << op1_shamt; // @[functional-unit.scala:151:22, :152:20, :153:55] wire _op1_data_T = uop_pc[39]; // @[util.scala:269:46] wire [23:0] _op1_data_T_1 = {24{_op1_data_T}}; // @[util.scala:269:{25,46}] wire [63:0] _op1_data_T_2 = {_op1_data_T_1, uop_pc}; // @[util.scala:269:{20,25}] wire _op1_data_T_3 = io_req_bits_uop_op1_sel_0 == 2'h0; // @[functional-unit.scala:133:7, :155:45] wire [63:0] _op1_data_T_4 = _op1_data_T_3 ? io_req_bits_rs1_data_0 : 64'h0; // @[functional-unit.scala:133:7, :155:45] wire _op1_data_T_5 = io_req_bits_uop_op1_sel_0 == 2'h2; // @[functional-unit.scala:133:7, :155:45] wire [63:0] _op1_data_T_6 = _op1_data_T_5 ? _op1_data_T_2 : _op1_data_T_4; // @[util.scala:269:20] wire _op1_data_T_7 = &io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :155:45] wire [66:0] op1_data = _op1_data_T_7 ? op1_shl : {3'h0, _op1_data_T_6}; // @[functional-unit.scala:153:55, :155:45] wire _op2_oh_T = io_req_bits_uop_op2_sel_0[0]; // @[functional-unit.scala:133:7, :162:40] wire [63:0] _op2_oh_T_1 = _op2_oh_T ? io_req_bits_rs2_data_0 : io_req_bits_imm_data_0; // @[functional-unit.scala:133:7, :162:{28,40}] wire [5:0] _op2_oh_T_2 = _op2_oh_T_1[5:0]; // @[functional-unit.scala:162:28, :163:38] wire [63:0] op2_oh = 64'h1 << _op2_oh_T_2; // @[OneHot.scala:58:35] wire [4:0] _op2_data_T = io_req_bits_uop_prs1_0[4:0]; // @[functional-unit.scala:133:7, :166:37] wire [2:0] _op2_data_T_1 = io_req_bits_uop_is_rvc_0 ? 3'h2 : 3'h4; // @[functional-unit.scala:133:7, :168:20] wire _op2_data_T_2 = io_req_bits_uop_op2_sel_0 == 3'h1; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_3 = _op2_data_T_2 ? io_req_bits_imm_data_0 : 64'h0; // @[functional-unit.scala:133:7, :164:45] wire _op2_data_T_4 = io_req_bits_uop_op2_sel_0 == 3'h4; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_5 = _op2_data_T_4 ? {59'h0, _op2_data_T} : _op2_data_T_3; // @[functional-unit.scala:164:45, :166:37] wire _op2_data_T_6 = io_req_bits_uop_op2_sel_0 == 3'h0; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_7 = _op2_data_T_6 ? io_req_bits_rs2_data_0 : _op2_data_T_5; // @[functional-unit.scala:133:7, :164:45] wire _op2_data_T_8 = io_req_bits_uop_op2_sel_0 == 3'h3; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_9 = _op2_data_T_8 ? {61'h0, _op2_data_T_1} : _op2_data_T_7; // @[functional-unit.scala:164:45, :168:20] wire _op2_data_T_10 = io_req_bits_uop_op2_sel_0 == 3'h5; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_11 = _op2_data_T_10 ? op2_oh : _op2_data_T_9; // @[OneHot.scala:58:35] wire _op2_data_T_12 = io_req_bits_uop_op2_sel_0 == 3'h6; // @[functional-unit.scala:133:7, :164:45] wire [63:0] op2_data = _op2_data_T_12 ? op2_oh : _op2_data_T_11; // @[OneHot.scala:58:35] wire _alu_io_dw_T = &io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :155:45, :178:33] wire _alu_io_dw_T_1 = _alu_io_dw_T | io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :178:{20,33}] wire br_eq = io_req_bits_rs1_data_0 == io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :183:21] wire br_ltu = io_req_bits_rs1_data_0 < io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :184:28] wire _br_lt_T = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:133:7, :185:22] wire _br_lt_T_5 = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:133:7, :185:22, :186:20] wire _br_lt_T_1 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:133:7, :185:36] wire _br_lt_T_6 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:133:7, :185:36, :186:35] wire _br_lt_T_2 = _br_lt_T ^ _br_lt_T_1; // @[functional-unit.scala:185:{22,31,36}] wire _br_lt_T_3 = ~_br_lt_T_2; // @[functional-unit.scala:185:{17,31}] wire _br_lt_T_4 = _br_lt_T_3 & br_ltu; // @[functional-unit.scala:184:28, :185:{17,46}] wire _br_lt_T_7 = ~_br_lt_T_6; // @[functional-unit.scala:186:{31,35}] wire _br_lt_T_8 = _br_lt_T_5 & _br_lt_T_7; // @[functional-unit.scala:186:{20,29,31}] wire br_lt = _br_lt_T_4 | _br_lt_T_8; // @[functional-unit.scala:185:{46,55}, :186:29] wire _pc_sel_T = ~br_eq; // @[functional-unit.scala:183:21, :190:38] wire [1:0] _pc_sel_T_1 = {1'h0, _pc_sel_T}; // @[functional-unit.scala:190:{37,38}] wire [1:0] _pc_sel_T_2 = {1'h0, br_eq}; // @[functional-unit.scala:183:21, :191:37] wire _pc_sel_T_3 = ~br_lt; // @[functional-unit.scala:185:55, :192:38] wire [1:0] _pc_sel_T_4 = {1'h0, _pc_sel_T_3}; // @[functional-unit.scala:192:{37,38}] wire _pc_sel_T_5 = ~br_ltu; // @[functional-unit.scala:184:28, :193:38] wire [1:0] _pc_sel_T_6 = {1'h0, _pc_sel_T_5}; // @[functional-unit.scala:193:{37,38}] wire [1:0] _pc_sel_T_7 = {1'h0, br_lt}; // @[functional-unit.scala:185:55, :194:37] wire [1:0] _pc_sel_T_8 = {1'h0, br_ltu}; // @[functional-unit.scala:184:28, :195:37] wire _pc_sel_T_9 = ~(|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _GEN = io_req_bits_uop_br_type_0 == 4'h1; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_11; // @[functional-unit.scala:188:48] assign _pc_sel_T_11 = _GEN; // @[functional-unit.scala:188:48] wire _is_br_T; // @[package.scala:16:47] assign _is_br_T = _GEN; // @[package.scala:16:47] wire [1:0] _pc_sel_T_12 = _pc_sel_T_11 ? _pc_sel_T_1 : 2'h0; // @[functional-unit.scala:188:48, :190:37] wire _GEN_0 = io_req_bits_uop_br_type_0 == 4'h2; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_13; // @[functional-unit.scala:188:48] assign _pc_sel_T_13 = _GEN_0; // @[functional-unit.scala:188:48] wire _is_br_T_1; // @[package.scala:16:47] assign _is_br_T_1 = _GEN_0; // @[package.scala:16:47] wire [1:0] _pc_sel_T_14 = _pc_sel_T_13 ? _pc_sel_T_2 : _pc_sel_T_12; // @[functional-unit.scala:188:48, :191:37] wire _GEN_1 = io_req_bits_uop_br_type_0 == 4'h3; // @[functional-unit.scala:133:7, :188:48, :201:33] wire _pc_sel_T_15; // @[functional-unit.scala:188:48] assign _pc_sel_T_15 = _GEN_1; // @[functional-unit.scala:188:48] wire _is_br_T_2; // @[package.scala:16:47] assign _is_br_T_2 = _GEN_1; // @[package.scala:16:47] wire [1:0] _pc_sel_T_16 = _pc_sel_T_15 ? _pc_sel_T_4 : _pc_sel_T_14; // @[functional-unit.scala:188:48, :192:37] wire _GEN_2 = io_req_bits_uop_br_type_0 == 4'h4; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_17; // @[functional-unit.scala:188:48] assign _pc_sel_T_17 = _GEN_2; // @[functional-unit.scala:188:48] wire _is_br_T_3; // @[package.scala:16:47] assign _is_br_T_3 = _GEN_2; // @[package.scala:16:47] wire [1:0] _pc_sel_T_18 = _pc_sel_T_17 ? _pc_sel_T_6 : _pc_sel_T_16; // @[functional-unit.scala:188:48, :193:37] wire _GEN_3 = io_req_bits_uop_br_type_0 == 4'h5; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_19; // @[functional-unit.scala:188:48] assign _pc_sel_T_19 = _GEN_3; // @[functional-unit.scala:188:48] wire _is_br_T_4; // @[package.scala:16:47] assign _is_br_T_4 = _GEN_3; // @[package.scala:16:47] wire [1:0] _pc_sel_T_20 = _pc_sel_T_19 ? _pc_sel_T_7 : _pc_sel_T_18; // @[functional-unit.scala:188:48, :194:37] wire _GEN_4 = io_req_bits_uop_br_type_0 == 4'h6; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_21; // @[functional-unit.scala:188:48] assign _pc_sel_T_21 = _GEN_4; // @[functional-unit.scala:188:48] wire _is_br_T_5; // @[package.scala:16:47] assign _is_br_T_5 = _GEN_4; // @[package.scala:16:47] wire [1:0] _pc_sel_T_22 = _pc_sel_T_21 ? _pc_sel_T_8 : _pc_sel_T_20; // @[functional-unit.scala:188:48, :195:37] wire _GEN_5 = io_req_bits_uop_br_type_0 == 4'h7; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_23; // @[functional-unit.scala:188:48] assign _pc_sel_T_23 = _GEN_5; // @[functional-unit.scala:188:48] wire _is_jal_T; // @[micro-op.scala:118:34] assign _is_jal_T = _GEN_5; // @[functional-unit.scala:188:48] wire [1:0] _pc_sel_T_24 = _pc_sel_T_23 ? 2'h1 : _pc_sel_T_22; // @[functional-unit.scala:188:48] wire _GEN_6 = io_req_bits_uop_br_type_0 == 4'h8; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_25; // @[functional-unit.scala:188:48] assign _pc_sel_T_25 = _GEN_6; // @[functional-unit.scala:188:48] wire _is_jalr_T; // @[micro-op.scala:119:34] assign _is_jalr_T = _GEN_6; // @[functional-unit.scala:188:48] wire [1:0] pc_sel = _pc_sel_T_25 ? 2'h2 : _pc_sel_T_24; // @[functional-unit.scala:188:48] assign brinfo_bits_pc_sel = pc_sel; // @[functional-unit.scala:188:48, :252:20] wire _is_taken_T = io_req_bits_uop_br_type_0 != 4'h3; // @[functional-unit.scala:133:7, :201:33] wire _is_taken_T_1 = io_req_valid_0 & _is_taken_T; // @[functional-unit.scala:133:7, :200:31, :201:33] wire _is_taken_T_2 = |pc_sel; // @[functional-unit.scala:188:48, :202:28] wire is_taken = _is_taken_T_1 & _is_taken_T_2; // @[functional-unit.scala:200:31, :201:43, :202:28] assign brinfo_bits_taken = is_taken; // @[functional-unit.scala:201:43, :252:20] wire [20:0] _target_offset_T = io_req_bits_imm_data_0[20:0]; // @[functional-unit.scala:133:7, :208:33] wire [20:0] target_offset = _target_offset_T; // @[functional-unit.scala:208:{33,40}] assign brinfo_bits_target_offset = target_offset; // @[functional-unit.scala:208:40, :252:20] wire mispredict; // @[functional-unit.scala:223:28] assign brinfo_bits_mispredict = mispredict; // @[functional-unit.scala:223:28, :252:20] wire _is_br_T_6 = _is_br_T | _is_br_T_1; // @[package.scala:16:47, :81:59] wire _is_br_T_7 = _is_br_T_6 | _is_br_T_2; // @[package.scala:16:47, :81:59] wire _is_br_T_8 = _is_br_T_7 | _is_br_T_3; // @[package.scala:16:47, :81:59] wire _is_br_T_9 = _is_br_T_8 | _is_br_T_4; // @[package.scala:16:47, :81:59] wire _is_br_T_10 = _is_br_T_9 | _is_br_T_5; // @[package.scala:16:47, :81:59] wire _is_br_T_11 = io_req_valid_0 & _is_br_T_10; // @[package.scala:81:59] wire _is_br_T_12 = ~io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7, :225:53] wire is_br = _is_br_T_11 & _is_br_T_12; // @[functional-unit.scala:225:{37,50,53}] wire is_jal = io_req_valid_0 & _is_jal_T; // @[functional-unit.scala:133:7, :226:37] wire is_jalr = io_req_valid_0 & _is_jalr_T; // @[functional-unit.scala:133:7, :227:37] wire [63:0] _jalr_target_xlen_T_3; // @[functional-unit.scala:231:58] wire [63:0] jalr_target_xlen; // @[functional-unit.scala:230:30] wire [63:0] _jalr_target_a_T = jalr_target_xlen; // @[functional-unit.scala:215:16, :230:30] wire [64:0] _jalr_target_xlen_T = {jalr_target_base[63], jalr_target_base} + {{44{target_offset[20]}}, target_offset}; // @[functional-unit.scala:208:40, :229:47, :231:41] wire [63:0] _jalr_target_xlen_T_1 = _jalr_target_xlen_T[63:0]; // @[functional-unit.scala:231:41] wire [63:0] _jalr_target_xlen_T_2 = _jalr_target_xlen_T_1; // @[functional-unit.scala:231:41] assign _jalr_target_xlen_T_3 = _jalr_target_xlen_T_2; // @[functional-unit.scala:231:{41,58}] assign jalr_target_xlen = _jalr_target_xlen_T_3; // @[functional-unit.scala:230:30, :231:58] wire [24:0] jalr_target_a = _jalr_target_a_T[63:39]; // @[functional-unit.scala:215:{16,23}] wire _jalr_target_msb_T = jalr_target_a == 25'h0; // @[functional-unit.scala:215:23, :216:21] wire _jalr_target_msb_T_1 = &jalr_target_a; // @[functional-unit.scala:215:23, :216:34] wire _jalr_target_msb_T_2 = _jalr_target_msb_T | _jalr_target_msb_T_1; // @[functional-unit.scala:216:{21,29,34}] wire _jalr_target_msb_T_3 = jalr_target_xlen[39]; // @[functional-unit.scala:216:46, :230:30] wire _jalr_target_msb_T_4 = jalr_target_xlen[38]; // @[functional-unit.scala:216:62, :230:30] wire _jalr_target_msb_T_5 = ~_jalr_target_msb_T_4; // @[functional-unit.scala:216:{59,62}] wire jalr_target_msb = _jalr_target_msb_T_2 ? _jalr_target_msb_T_3 : _jalr_target_msb_T_5; // @[functional-unit.scala:216:{18,29,46,59}] wire [38:0] _jalr_target_T = jalr_target_xlen[38:0]; // @[functional-unit.scala:217:16, :230:30] wire [39:0] _jalr_target_T_1 = {jalr_target_msb, _jalr_target_T}; // @[functional-unit.scala:216:18, :217:{8,16}] wire [39:0] _jalr_target_T_2 = _jalr_target_T_1; // @[functional-unit.scala:217:8, :232:79] wire [39:0] _jalr_target_T_3 = _jalr_target_T_2 & 40'hFFFFFFFFFE; // @[functional-unit.scala:232:{79,86}] wire [39:0] _jalr_target_T_4 = _jalr_target_T_3; // @[functional-unit.scala:232:86] wire [39:0] jalr_target = _jalr_target_T_4; // @[functional-unit.scala:232:{86,94}] assign brinfo_bits_jalr_target = jalr_target; // @[functional-unit.scala:232:94, :252:20] wire [2:0] cfi_idx = _cfi_idx_T_3[3:1]; // @[functional-unit.scala:234:{30,120}] wire _brinfo_valid_T = is_br | is_jalr; // @[functional-unit.scala:225:50, :227:37, :237:15, :255:34] wire _mispredict_T = ~io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7, :242:21] wire _mispredict_T_2 = |jalr_target; // @[functional-unit.scala:232:94, :246:50] wire _mispredict_T_6 = |cfi_idx; // @[functional-unit.scala:234:120, :248:66] assign mispredict = _brinfo_valid_T & (pc_sel == 2'h2 | (pc_sel == 2'h1 ? _mispredict_T : ~(|pc_sel) & io_req_bits_uop_taken_0)); // @[functional-unit.scala:133:7, :188:48, :202:28, :223:28, :237:27, :238:{18,32}, :239:18, :241:{18,32}, :242:{18,21}, :244:{18,31}, :245:18, :255:34] assign io_brinfo_valid = brinfo_valid; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_inst = brinfo_bits_uop_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_inst = brinfo_bits_uop_debug_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_rvc = brinfo_bits_uop_is_rvc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_pc = brinfo_bits_uop_debug_pc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_0 = brinfo_bits_uop_iq_type_0; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_1 = brinfo_bits_uop_iq_type_1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_2 = brinfo_bits_uop_iq_type_2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_3 = brinfo_bits_uop_iq_type_3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_0 = brinfo_bits_uop_fu_code_0; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_1 = brinfo_bits_uop_fu_code_1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_2 = brinfo_bits_uop_fu_code_2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_3 = brinfo_bits_uop_fu_code_3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_4 = brinfo_bits_uop_fu_code_4; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_5 = brinfo_bits_uop_fu_code_5; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_6 = brinfo_bits_uop_fu_code_6; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_7 = brinfo_bits_uop_fu_code_7; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_8 = brinfo_bits_uop_fu_code_8; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_9 = brinfo_bits_uop_fu_code_9; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued = brinfo_bits_uop_iw_issued; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued_partial_agen = brinfo_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued_partial_dgen = brinfo_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p1_speculative_child = brinfo_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p2_speculative_child = brinfo_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p1_bypass_hint = brinfo_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p2_bypass_hint = brinfo_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p3_bypass_hint = brinfo_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_dis_col_sel = brinfo_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_mask = brinfo_bits_uop_br_mask; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_tag = brinfo_bits_uop_br_tag; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_type = brinfo_bits_uop_br_type; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sfb = brinfo_bits_uop_is_sfb; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_fence = brinfo_bits_uop_is_fence; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_fencei = brinfo_bits_uop_is_fencei; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sfence = brinfo_bits_uop_is_sfence; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_amo = brinfo_bits_uop_is_amo; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_eret = brinfo_bits_uop_is_eret; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sys_pc2epc = brinfo_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_rocc = brinfo_bits_uop_is_rocc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_mov = brinfo_bits_uop_is_mov; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ftq_idx = brinfo_bits_uop_ftq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_edge_inst = brinfo_bits_uop_edge_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pc_lob = brinfo_bits_uop_pc_lob; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_taken = brinfo_bits_uop_taken; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_rename = brinfo_bits_uop_imm_rename; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_sel = brinfo_bits_uop_imm_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pimm = brinfo_bits_uop_pimm; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_packed = brinfo_bits_uop_imm_packed; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_op1_sel = brinfo_bits_uop_op1_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_op2_sel = brinfo_bits_uop_op2_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ldst = brinfo_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_wen = brinfo_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren1 = brinfo_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren2 = brinfo_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren3 = brinfo_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_swap12 = brinfo_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_swap23 = brinfo_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_typeTagIn = brinfo_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_typeTagOut = brinfo_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fromint = brinfo_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_toint = brinfo_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fastpipe = brinfo_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fma = brinfo_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_div = brinfo_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_sqrt = brinfo_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_wflags = brinfo_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_vec = brinfo_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_rob_idx = brinfo_bits_uop_rob_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldq_idx = brinfo_bits_uop_ldq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_stq_idx = brinfo_bits_uop_stq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_rxq_idx = brinfo_bits_uop_rxq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pdst = brinfo_bits_uop_pdst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs1 = brinfo_bits_uop_prs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs2 = brinfo_bits_uop_prs2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs3 = brinfo_bits_uop_prs3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ppred = brinfo_bits_uop_ppred; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs1_busy = brinfo_bits_uop_prs1_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs2_busy = brinfo_bits_uop_prs2_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs3_busy = brinfo_bits_uop_prs3_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ppred_busy = brinfo_bits_uop_ppred_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_stale_pdst = brinfo_bits_uop_stale_pdst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_exception = brinfo_bits_uop_exception; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_exc_cause = brinfo_bits_uop_exc_cause; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_cmd = brinfo_bits_uop_mem_cmd; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_size = brinfo_bits_uop_mem_size; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_signed = brinfo_bits_uop_mem_signed; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_uses_ldq = brinfo_bits_uop_uses_ldq; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_uses_stq = brinfo_bits_uop_uses_stq; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_unique = brinfo_bits_uop_is_unique; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_flush_on_commit = brinfo_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_csr_cmd = brinfo_bits_uop_csr_cmd; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldst_is_rs1 = brinfo_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldst = brinfo_bits_uop_ldst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs1 = brinfo_bits_uop_lrs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs2 = brinfo_bits_uop_lrs2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs3 = brinfo_bits_uop_lrs3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_dst_rtype = brinfo_bits_uop_dst_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs1_rtype = brinfo_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs2_rtype = brinfo_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_frs3_en = brinfo_bits_uop_frs3_en; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fcn_dw = brinfo_bits_uop_fcn_dw; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fcn_op = brinfo_bits_uop_fcn_op; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_val = brinfo_bits_uop_fp_val; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_rm = brinfo_bits_uop_fp_rm; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_typ = brinfo_bits_uop_fp_typ; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_pf_if = brinfo_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_ae_if = brinfo_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_ma_if = brinfo_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_bp_debug_if = brinfo_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_bp_xcpt_if = brinfo_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_fsrc = brinfo_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_tsrc = brinfo_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_mispredict = brinfo_bits_mispredict; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_taken = brinfo_bits_taken; // @[functional-unit.scala:133:7, :252:20] wire [2:0] _brinfo_bits_cfi_type_T_1; // @[functional-unit.scala:258:36] assign io_brinfo_bits_cfi_type = brinfo_bits_cfi_type; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_pc_sel = brinfo_bits_pc_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_jalr_target = brinfo_bits_jalr_target; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_target_offset = brinfo_bits_target_offset; // @[functional-unit.scala:133:7, :252:20] assign brinfo_valid = _brinfo_valid_T; // @[functional-unit.scala:252:20, :255:34] wire [2:0] _brinfo_bits_cfi_type_T = {2'h0, is_br}; // @[functional-unit.scala:225:50, :259:36] assign _brinfo_bits_cfi_type_T_1 = is_jalr ? 3'h3 : _brinfo_bits_cfi_type_T; // @[functional-unit.scala:227:37, :258:36, :259:36] assign brinfo_bits_cfi_type = _brinfo_bits_cfi_type_T_1; // @[functional-unit.scala:252:20, :258:36] wire _alu_out_T = ~(|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _alu_out_T_1 = _alu_out_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _alu_out_T_2 = _alu_out_T_1; // @[micro-op.scala:121:{42,52}] wire [63:0] _alu_out_T_4 = io_req_bits_uop_ldst_is_rs1_0 ? io_req_bits_rs1_data_0 : io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :286:10] wire [63:0] _alu_out_T_5 = io_req_bits_uop_is_mov_0 ? io_req_bits_rs2_data_0 : _alu_io_out; // @[functional-unit.scala:133:7, :173:19, :287:10] wire [63:0] alu_out = _alu_out_T_5; // @[functional-unit.scala:285:20, :287:10] wire _io_resp_bits_data_T = |io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7, :188:48] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _io_resp_bits_data_T_2 = _io_resp_bits_data_T_1; // @[micro-op.scala:120:{42,52}] wire _io_resp_bits_data_T_3 = pc_sel == 2'h1; // @[functional-unit.scala:188:48, :290:62] assign _io_resp_bits_data_T_4 = _io_resp_bits_data_T_2 ? {63'h0, _io_resp_bits_data_T_3} : alu_out; // @[OneHot.scala:58:35] assign io_resp_bits_data_0 = _io_resp_bits_data_T_4; // @[functional-unit.scala:133:7, :290:27] wire _io_resp_bits_predicated_T = ~(|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _io_resp_bits_predicated_T_1 = _io_resp_bits_predicated_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _io_resp_bits_predicated_T_2 = _io_resp_bits_predicated_T_1; // @[micro-op.scala:121:{42,52}] ALU alu ( // @[functional-unit.scala:173:19] .clock (clock), .reset (reset), .io_dw (_alu_io_dw_T_1), // @[functional-unit.scala:178:20] .io_fn (io_req_bits_uop_fcn_op_0), // @[functional-unit.scala:133:7] .io_in2 (op2_data), // @[functional-unit.scala:164:45] .io_in1 (op1_data[63:0]), // @[functional-unit.scala:155:45, :175:14] .io_out (_alu_io_out) ); // @[functional-unit.scala:173:19] assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_1 = io_resp_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_2 = io_resp_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_3 = io_resp_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_1 = io_resp_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_2 = io_resp_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_3 = io_resp_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_4 = io_resp_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_5 = io_resp_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_6 = io_resp_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_7 = io_resp_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_8 = io_resp_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_9 = io_resp_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued = io_resp_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued_partial_agen = io_resp_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued_partial_dgen = io_resp_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p1_speculative_child = io_resp_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p2_speculative_child = io_resp_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p1_bypass_hint = io_resp_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p2_bypass_hint = io_resp_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p3_bypass_hint = io_resp_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_dis_col_sel = io_resp_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_type = io_resp_bits_uop_br_type_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sfence = io_resp_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_eret = io_resp_bits_uop_is_eret_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_rocc = io_resp_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_mov = io_resp_bits_uop_is_mov_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_rename = io_resp_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_sel = io_resp_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pimm = io_resp_bits_uop_pimm_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_op1_sel = io_resp_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_op2_sel = io_resp_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ldst = io_resp_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_wen = io_resp_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren1 = io_resp_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren2 = io_resp_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren3 = io_resp_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_swap12 = io_resp_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_swap23 = io_resp_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_typeTagIn = io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_typeTagOut = io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fromint = io_resp_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_toint = io_resp_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fastpipe = io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fma = io_resp_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_div = io_resp_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_sqrt = io_resp_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_wflags = io_resp_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_vec = io_resp_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_csr_cmd = io_resp_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fcn_dw = io_resp_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fcn_op = io_resp_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_rm = io_resp_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_typ = io_resp_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:133:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_36 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_36( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_44 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_300 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_44( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_300 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_83 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_135 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_83( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_135 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLXbar_sbus_i2_o2_a32d32s6k3z4u : input clock : Clock input reset : Reset output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready inst monitor of TLMonitor connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_1 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}[2] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.mask, UInt<4>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<32>(0h0) connect _WIRE_4.bits.mask, UInt<4>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<6>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_16.bits.sink, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_18.bits.sink, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_20.bits.sink, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_22.bits.sink, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt connect in[1].a.bits.data, anonIn_1.a.bits.data connect in[1].a.bits.mask, anonIn_1.a.bits.mask connect in[1].a.bits.address, anonIn_1.a.bits.address connect in[1].a.bits.source, anonIn_1.a.bits.source connect in[1].a.bits.size, anonIn_1.a.bits.size connect in[1].a.bits.param, anonIn_1.a.bits.param connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode connect in[1].a.valid, anonIn_1.a.valid connect anonIn_1.a.ready, in[1].a.ready node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<6>(0h20)) connect in[1].a.bits.source, _in_1_a_bits_source_T wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.mask, UInt<4>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<32>(0h0) connect _WIRE_26.bits.mask, UInt<4>(0h0) connect _WIRE_26.bits.address, UInt<32>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<32>(0h0) connect _WIRE_28.bits.mask, UInt<4>(0h0) connect _WIRE_28.bits.address, UInt<32>(0h0) connect _WIRE_28.bits.source, UInt<6>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.ready, UInt<1>(0h1) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<32>(0h0) connect _WIRE_30.bits.mask, UInt<4>(0h0) connect _WIRE_30.bits.address, UInt<32>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<4>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.valid, UInt<1>(0h0) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<32>(0h0) connect _WIRE_32.bits.address, UInt<32>(0h0) connect _WIRE_32.bits.source, UInt<6>(0h0) connect _WIRE_32.bits.size, UInt<4>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<32>(0h0) connect _WIRE_34.bits.address, UInt<32>(0h0) connect _WIRE_34.bits.source, UInt<1>(0h0) connect _WIRE_34.bits.size, UInt<4>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<32>(0h0) connect _WIRE_36.bits.address, UInt<32>(0h0) connect _WIRE_36.bits.source, UInt<6>(0h0) connect _WIRE_36.bits.size, UInt<4>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.valid, UInt<1>(0h0) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<32>(0h0) connect _WIRE_38.bits.address, UInt<32>(0h0) connect _WIRE_38.bits.source, UInt<1>(0h0) connect _WIRE_38.bits.size, UInt<4>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.ready, UInt<1>(0h1) connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt connect anonIn_1.d.bits.data, in[1].d.bits.data connect anonIn_1.d.bits.denied, in[1].d.bits.denied connect anonIn_1.d.bits.sink, in[1].d.bits.sink connect anonIn_1.d.bits.source, in[1].d.bits.source connect anonIn_1.d.bits.size, in[1].d.bits.size connect anonIn_1.d.bits.param, in[1].d.bits.param connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode connect anonIn_1.d.valid, in[1].d.valid connect in[1].d.ready, anonIn_1.d.ready node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 0, 0) connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1 wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_40.bits.sink, UInt<3>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_42.bits.sink, UInt<3>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_44.bits.sink, UInt<3>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.valid, UInt<1>(0h0) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_46.bits.sink, UInt<3>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<32>(0h0) connect _WIRE_48.bits.mask, UInt<4>(0h0) connect _WIRE_48.bits.address, UInt<32>(0h0) connect _WIRE_48.bits.source, UInt<6>(0h0) connect _WIRE_48.bits.size, UInt<4>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<32>(0h0) connect _WIRE_50.bits.mask, UInt<4>(0h0) connect _WIRE_50.bits.address, UInt<29>(0h0) connect _WIRE_50.bits.source, UInt<6>(0h0) connect _WIRE_50.bits.size, UInt<4>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<32>(0h0) connect _WIRE_52.bits.mask, UInt<4>(0h0) connect _WIRE_52.bits.address, UInt<32>(0h0) connect _WIRE_52.bits.source, UInt<6>(0h0) connect _WIRE_52.bits.size, UInt<4>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<32>(0h0) connect _WIRE_54.bits.mask, UInt<4>(0h0) connect _WIRE_54.bits.address, UInt<29>(0h0) connect _WIRE_54.bits.source, UInt<6>(0h0) connect _WIRE_54.bits.size, UInt<4>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<32>(0h0) connect _WIRE_56.bits.address, UInt<32>(0h0) connect _WIRE_56.bits.source, UInt<6>(0h0) connect _WIRE_56.bits.size, UInt<4>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<32>(0h0) connect _WIRE_58.bits.address, UInt<29>(0h0) connect _WIRE_58.bits.source, UInt<6>(0h0) connect _WIRE_58.bits.size, UInt<4>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<32>(0h0) connect _WIRE_60.bits.address, UInt<32>(0h0) connect _WIRE_60.bits.source, UInt<6>(0h0) connect _WIRE_60.bits.size, UInt<4>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<32>(0h0) connect _WIRE_62.bits.address, UInt<29>(0h0) connect _WIRE_62.bits.source, UInt<6>(0h0) connect _WIRE_62.bits.size, UInt<4>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_64.bits.sink, UInt<3>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_68.bits.sink, UInt<3>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<32>(0h0) connect _WIRE_72.bits.mask, UInt<4>(0h0) connect _WIRE_72.bits.address, UInt<32>(0h0) connect _WIRE_72.bits.source, UInt<6>(0h0) connect _WIRE_72.bits.size, UInt<4>(0h0) connect _WIRE_72.bits.param, UInt<2>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.mask invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode invalidate _WIRE_73.valid invalidate _WIRE_73.ready wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_74.bits.corrupt, UInt<1>(0h0) connect _WIRE_74.bits.data, UInt<32>(0h0) connect _WIRE_74.bits.mask, UInt<4>(0h0) connect _WIRE_74.bits.address, UInt<32>(0h0) connect _WIRE_74.bits.source, UInt<6>(0h0) connect _WIRE_74.bits.size, UInt<3>(0h0) connect _WIRE_74.bits.param, UInt<2>(0h0) connect _WIRE_74.bits.opcode, UInt<3>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.corrupt invalidate _WIRE_75.bits.data invalidate _WIRE_75.bits.mask invalidate _WIRE_75.bits.address invalidate _WIRE_75.bits.source invalidate _WIRE_75.bits.size invalidate _WIRE_75.bits.param invalidate _WIRE_75.bits.opcode invalidate _WIRE_75.valid invalidate _WIRE_75.ready wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<32>(0h0) connect _WIRE_76.bits.mask, UInt<4>(0h0) connect _WIRE_76.bits.address, UInt<32>(0h0) connect _WIRE_76.bits.source, UInt<6>(0h0) connect _WIRE_76.bits.size, UInt<4>(0h0) connect _WIRE_76.bits.param, UInt<2>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready connect _WIRE_77.valid, UInt<1>(0h0) wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_78.bits.corrupt, UInt<1>(0h0) connect _WIRE_78.bits.data, UInt<32>(0h0) connect _WIRE_78.bits.mask, UInt<4>(0h0) connect _WIRE_78.bits.address, UInt<32>(0h0) connect _WIRE_78.bits.source, UInt<6>(0h0) connect _WIRE_78.bits.size, UInt<3>(0h0) connect _WIRE_78.bits.param, UInt<2>(0h0) connect _WIRE_78.bits.opcode, UInt<3>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready connect _WIRE_79.ready, UInt<1>(0h1) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<32>(0h0) connect _WIRE_80.bits.address, UInt<32>(0h0) connect _WIRE_80.bits.source, UInt<6>(0h0) connect _WIRE_80.bits.size, UInt<4>(0h0) connect _WIRE_80.bits.param, UInt<3>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode invalidate _WIRE_81.valid invalidate _WIRE_81.ready wire _WIRE_82 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_82.bits.corrupt, UInt<1>(0h0) connect _WIRE_82.bits.data, UInt<32>(0h0) connect _WIRE_82.bits.address, UInt<32>(0h0) connect _WIRE_82.bits.source, UInt<6>(0h0) connect _WIRE_82.bits.size, UInt<3>(0h0) connect _WIRE_82.bits.param, UInt<3>(0h0) connect _WIRE_82.bits.opcode, UInt<3>(0h0) connect _WIRE_82.valid, UInt<1>(0h0) connect _WIRE_82.ready, UInt<1>(0h0) wire _WIRE_83 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_83.bits, _WIRE_82.bits connect _WIRE_83.valid, _WIRE_82.valid connect _WIRE_83.ready, _WIRE_82.ready invalidate _WIRE_83.bits.corrupt invalidate _WIRE_83.bits.data invalidate _WIRE_83.bits.address invalidate _WIRE_83.bits.source invalidate _WIRE_83.bits.size invalidate _WIRE_83.bits.param invalidate _WIRE_83.bits.opcode invalidate _WIRE_83.valid invalidate _WIRE_83.ready wire _WIRE_84 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_84.bits.corrupt, UInt<1>(0h0) connect _WIRE_84.bits.data, UInt<32>(0h0) connect _WIRE_84.bits.address, UInt<32>(0h0) connect _WIRE_84.bits.source, UInt<6>(0h0) connect _WIRE_84.bits.size, UInt<4>(0h0) connect _WIRE_84.bits.param, UInt<3>(0h0) connect _WIRE_84.bits.opcode, UInt<3>(0h0) connect _WIRE_84.valid, UInt<1>(0h0) connect _WIRE_84.ready, UInt<1>(0h0) wire _WIRE_85 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_85.bits, _WIRE_84.bits connect _WIRE_85.valid, _WIRE_84.valid connect _WIRE_85.ready, _WIRE_84.ready connect _WIRE_85.ready, UInt<1>(0h1) wire _WIRE_86 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_86.bits.corrupt, UInt<1>(0h0) connect _WIRE_86.bits.data, UInt<32>(0h0) connect _WIRE_86.bits.address, UInt<32>(0h0) connect _WIRE_86.bits.source, UInt<6>(0h0) connect _WIRE_86.bits.size, UInt<3>(0h0) connect _WIRE_86.bits.param, UInt<3>(0h0) connect _WIRE_86.bits.opcode, UInt<3>(0h0) connect _WIRE_86.valid, UInt<1>(0h0) connect _WIRE_86.ready, UInt<1>(0h0) wire _WIRE_87 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_87.bits, _WIRE_86.bits connect _WIRE_87.valid, _WIRE_86.valid connect _WIRE_87.ready, _WIRE_86.ready connect _WIRE_87.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_88 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_88.bits.sink, UInt<3>(0h0) connect _WIRE_88.valid, UInt<1>(0h0) connect _WIRE_88.ready, UInt<1>(0h0) wire _WIRE_89 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_89.bits, _WIRE_88.bits connect _WIRE_89.valid, _WIRE_88.valid connect _WIRE_89.ready, _WIRE_88.ready invalidate _WIRE_89.bits.sink invalidate _WIRE_89.valid invalidate _WIRE_89.ready wire _WIRE_90 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_90.bits.sink, UInt<3>(0h0) connect _WIRE_90.valid, UInt<1>(0h0) connect _WIRE_90.ready, UInt<1>(0h0) wire _WIRE_91 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_91.bits, _WIRE_90.bits connect _WIRE_91.valid, _WIRE_90.valid connect _WIRE_91.ready, _WIRE_90.ready invalidate _WIRE_91.bits.sink invalidate _WIRE_91.valid invalidate _WIRE_91.ready wire _WIRE_92 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_92.bits.sink, UInt<3>(0h0) connect _WIRE_92.valid, UInt<1>(0h0) connect _WIRE_92.ready, UInt<1>(0h0) wire _WIRE_93 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_93.bits, _WIRE_92.bits connect _WIRE_93.valid, _WIRE_92.valid connect _WIRE_93.ready, _WIRE_92.ready connect _WIRE_93.ready, UInt<1>(0h1) wire _WIRE_94 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_94.bits.sink, UInt<3>(0h0) connect _WIRE_94.valid, UInt<1>(0h0) connect _WIRE_94.ready, UInt<1>(0h0) wire _WIRE_95 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_95.bits, _WIRE_94.bits connect _WIRE_95.valid, _WIRE_94.valid connect _WIRE_95.ready, _WIRE_94.ready connect _WIRE_95.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<32>(0h0) connect _addressC_WIRE.bits.address, UInt<32>(0h0) connect _addressC_WIRE.bits.source, UInt<6>(0h0) connect _addressC_WIRE.bits.size, UInt<4>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE_2.bits.data, UInt<32>(0h0) connect _addressC_WIRE_2.bits.address, UInt<32>(0h0) connect _addressC_WIRE_2.bits.source, UInt<6>(0h0) connect _addressC_WIRE_2.bits.size, UInt<4>(0h0) connect _addressC_WIRE_2.bits.param, UInt<3>(0h0) connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE_2.valid, UInt<1>(0h0) connect _addressC_WIRE_2.ready, UInt<1>(0h0) wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_11 = cvt(_requestAIO_T_10) node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_13 = asSInt(_requestAIO_T_12) node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0))) node _requestAIO_T_15 = or(_requestAIO_T_4, _requestAIO_T_9) node _requestAIO_T_16 = or(_requestAIO_T_15, _requestAIO_T_14) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_16) node _requestAIO_T_17 = xor(in[0].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_18 = cvt(_requestAIO_T_17) node _requestAIO_T_19 = and(_requestAIO_T_18, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_20 = asSInt(_requestAIO_T_19) node _requestAIO_T_21 = eq(_requestAIO_T_20, asSInt(UInt<1>(0h0))) node _requestAIO_T_22 = xor(in[0].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_23 = cvt(_requestAIO_T_22) node _requestAIO_T_24 = and(_requestAIO_T_23, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_25 = asSInt(_requestAIO_T_24) node _requestAIO_T_26 = eq(_requestAIO_T_25, asSInt(UInt<1>(0h0))) node _requestAIO_T_27 = or(_requestAIO_T_21, _requestAIO_T_26) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_27) node _requestAIO_T_28 = xor(in[1].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_29 = cvt(_requestAIO_T_28) node _requestAIO_T_30 = and(_requestAIO_T_29, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_31 = asSInt(_requestAIO_T_30) node _requestAIO_T_32 = eq(_requestAIO_T_31, asSInt(UInt<1>(0h0))) node _requestAIO_T_33 = xor(in[1].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_34 = cvt(_requestAIO_T_33) node _requestAIO_T_35 = and(_requestAIO_T_34, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_36 = asSInt(_requestAIO_T_35) node _requestAIO_T_37 = eq(_requestAIO_T_36, asSInt(UInt<1>(0h0))) node _requestAIO_T_38 = xor(in[1].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_39 = cvt(_requestAIO_T_38) node _requestAIO_T_40 = and(_requestAIO_T_39, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_41 = asSInt(_requestAIO_T_40) node _requestAIO_T_42 = eq(_requestAIO_T_41, asSInt(UInt<1>(0h0))) node _requestAIO_T_43 = or(_requestAIO_T_32, _requestAIO_T_37) node _requestAIO_T_44 = or(_requestAIO_T_43, _requestAIO_T_42) node requestAIO_1_0 = or(UInt<1>(0h0), _requestAIO_T_44) node _requestAIO_T_45 = xor(in[1].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_46 = cvt(_requestAIO_T_45) node _requestAIO_T_47 = and(_requestAIO_T_46, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_48 = asSInt(_requestAIO_T_47) node _requestAIO_T_49 = eq(_requestAIO_T_48, asSInt(UInt<1>(0h0))) node _requestAIO_T_50 = xor(in[1].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_51 = cvt(_requestAIO_T_50) node _requestAIO_T_52 = and(_requestAIO_T_51, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_53 = asSInt(_requestAIO_T_52) node _requestAIO_T_54 = eq(_requestAIO_T_53, asSInt(UInt<1>(0h0))) node _requestAIO_T_55 = or(_requestAIO_T_49, _requestAIO_T_54) node requestAIO_1_1 = or(UInt<1>(0h0), _requestAIO_T_55) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) node _requestCIO_T_10 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0)) node _requestCIO_T_11 = cvt(_requestCIO_T_10) node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0))) node _requestCIO_T_13 = asSInt(_requestCIO_T_12) node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0))) node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_14) node _requestCIO_T_15 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0)) node _requestCIO_T_16 = cvt(_requestCIO_T_15) node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0))) node _requestCIO_T_18 = asSInt(_requestCIO_T_17) node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0))) node requestCIO_1_1 = or(UInt<1>(0h1), _requestCIO_T_19) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<32>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<4>(0h0) connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE.bits.source, UInt<6>(0h0) connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 5) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<32>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<4>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<6>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<1>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 0, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 1) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<5>(0h10)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<1>(0h1)) node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9) wire _requestBOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_4.bits.data, UInt<32>(0h0) connect _requestBOI_WIRE_4.bits.mask, UInt<4>(0h0) connect _requestBOI_WIRE_4.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_4.bits.source, UInt<6>(0h0) connect _requestBOI_WIRE_4.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_4.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_4.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_4.valid, UInt<1>(0h0) connect _requestBOI_WIRE_4.ready, UInt<1>(0h0) wire _requestBOI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_5.bits, _requestBOI_WIRE_4.bits connect _requestBOI_WIRE_5.valid, _requestBOI_WIRE_4.valid connect _requestBOI_WIRE_5.ready, _requestBOI_WIRE_4.ready node _requestBOI_uncommonBits_T_2 = or(_requestBOI_WIRE_5.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 4, 0) node _requestBOI_T_10 = shr(_requestBOI_WIRE_5.bits.source, 5) node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h0)) node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2) node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12) node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<5>(0h1f)) node requestBOI_1_0 = and(_requestBOI_T_13, _requestBOI_T_14) wire _requestBOI_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_6.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_6.bits.data, UInt<32>(0h0) connect _requestBOI_WIRE_6.bits.mask, UInt<4>(0h0) connect _requestBOI_WIRE_6.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_6.bits.source, UInt<6>(0h0) connect _requestBOI_WIRE_6.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_6.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_6.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_6.valid, UInt<1>(0h0) connect _requestBOI_WIRE_6.ready, UInt<1>(0h0) wire _requestBOI_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _requestBOI_WIRE_7.bits, _requestBOI_WIRE_6.bits connect _requestBOI_WIRE_7.valid, _requestBOI_WIRE_6.valid connect _requestBOI_WIRE_7.ready, _requestBOI_WIRE_6.ready node _requestBOI_uncommonBits_T_3 = or(_requestBOI_WIRE_7.bits.source, UInt<1>(0h0)) node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 0, 0) node _requestBOI_T_15 = shr(_requestBOI_WIRE_7.bits.source, 1) node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<5>(0h10)) node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3) node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17) node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<1>(0h1)) node requestBOI_1_1 = and(_requestBOI_T_18, _requestBOI_T_19) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0) node _requestDOI_T = shr(out[0].d.bits.source, 5) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<1>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 0, 0) node _requestDOI_T_5 = shr(out[0].d.bits.source, 1) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<5>(0h10)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<1>(0h1)) node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9) node _requestDOI_uncommonBits_T_2 = or(out[1].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 4, 0) node _requestDOI_T_10 = shr(out[1].d.bits.source, 5) node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h0)) node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2) node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12) node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<5>(0h1f)) node requestDOI_1_0 = and(_requestDOI_T_13, _requestDOI_T_14) node _requestDOI_uncommonBits_T_3 = or(out[1].d.bits.source, UInt<1>(0h0)) node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 0, 0) node _requestDOI_T_15 = shr(out[1].d.bits.source, 1) node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<5>(0h10)) node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3) node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17) node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<1>(0h1)) node requestDOI_1_1 = and(_requestDOI_T_18, _requestDOI_T_19) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE.bits.sink, UInt<3>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_2.bits.sink, UInt<3>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _requestEIO_uncommonBits_T = or(_requestEIO_WIRE_3.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0) node _requestEIO_T = shr(_requestEIO_WIRE_3.bits.sink, 3) node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0)) node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits) node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2) node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7)) node requestEIO_0_1 = and(_requestEIO_T_3, _requestEIO_T_4) wire _requestEIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_4.bits.sink, UInt<3>(0h0) connect _requestEIO_WIRE_4.valid, UInt<1>(0h0) connect _requestEIO_WIRE_4.ready, UInt<1>(0h0) wire _requestEIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_5.bits, _requestEIO_WIRE_4.bits connect _requestEIO_WIRE_5.valid, _requestEIO_WIRE_4.valid connect _requestEIO_WIRE_5.ready, _requestEIO_WIRE_4.ready wire _requestEIO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_6.bits.sink, UInt<3>(0h0) connect _requestEIO_WIRE_6.valid, UInt<1>(0h0) connect _requestEIO_WIRE_6.ready, UInt<1>(0h0) wire _requestEIO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _requestEIO_WIRE_7.bits, _requestEIO_WIRE_6.bits connect _requestEIO_WIRE_7.valid, _requestEIO_WIRE_6.valid connect _requestEIO_WIRE_7.ready, _requestEIO_WIRE_6.ready node _requestEIO_uncommonBits_T_1 = or(_requestEIO_WIRE_7.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0) node _requestEIO_T_5 = shr(_requestEIO_WIRE_7.bits.sink, 3) node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0)) node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1) node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7) node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7)) node requestEIO_1_1 = and(_requestEIO_T_8, _requestEIO_T_9) node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 2) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 2) node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<32>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<4>(0h0) connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE.bits.source, UInt<6>(0h0) connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 2) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<32>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<4>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<6>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 2) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<32>(0h0) connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE.bits.source, UInt<6>(0h0) connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 2) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.data, UInt<32>(0h0) connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE_2.bits.source, UInt<6>(0h0) connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE_2.valid, UInt<1>(0h0) connect _beatsCI_WIRE_2.ready, UInt<1>(0h0) wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size) node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 2) node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0) node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 2) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 2) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _beatsEI_WIRE.bits.sink, UInt<3>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _beatsEI_WIRE_2.bits.sink, UInt<3>(0h0) connect _beatsEI_WIRE_2.valid, UInt<1>(0h0) connect _beatsEI_WIRE_2.ready, UInt<1>(0h0) wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsAOI_filtered_1[0].bits, in[1].a.bits node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 connect portsAOI_filtered_1[1].bits, in[1].a.bits node _portsAOI_filtered_1_valid_T_2 = or(requestAIO_1_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_1_valid_T_2) connect portsAOI_filtered_1[1].valid, _portsAOI_filtered_1_valid_T_3 node _portsAOI_in_1_a_ready_T = mux(requestAIO_1_0, portsAOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsAOI_in_1_a_ready_T_1 = mux(requestAIO_1_1, portsAOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsAOI_in_1_a_ready_T_2 = or(_portsAOI_in_1_a_ready_T, _portsAOI_in_1_a_ready_T_1) wire _portsAOI_in_1_a_ready_WIRE : UInt<1> connect _portsAOI_in_1_a_ready_WIRE, _portsAOI_in_1_a_ready_T_2 connect in[1].a.ready, _portsAOI_in_1_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<32>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<4>(0h0) connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE.bits.source, UInt<6>(0h0) connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T) connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1) wire _portsBIO_WIRE_2 : UInt<1> connect _portsBIO_WIRE_2, _portsBIO_T_2 connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2 wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_3.bits.data, UInt<32>(0h0) connect _portsBIO_WIRE_3.bits.mask, UInt<4>(0h0) connect _portsBIO_WIRE_3.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE_3.bits.source, UInt<6>(0h0) connect _portsBIO_WIRE_3.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE_3.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_3.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_3.valid, UInt<1>(0h0) connect _portsBIO_WIRE_3.ready, UInt<1>(0h0) wire _portsBIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _portsBIO_WIRE_4.bits, _portsBIO_WIRE_3.bits connect _portsBIO_WIRE_4.valid, _portsBIO_WIRE_3.valid connect _portsBIO_WIRE_4.ready, _portsBIO_WIRE_3.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_4.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_4.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect portsBIO_filtered_1[1].bits, _portsBIO_WIRE_4.bits node _portsBIO_filtered_1_valid_T_2 = or(requestBOI_1_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_3 = and(_portsBIO_WIRE_4.valid, _portsBIO_filtered_1_valid_T_2) connect portsBIO_filtered_1[1].valid, _portsBIO_filtered_1_valid_T_3 node _portsBIO_T_3 = mux(requestBOI_1_0, portsBIO_filtered_1[0].ready, UInt<1>(0h0)) node _portsBIO_T_4 = mux(requestBOI_1_1, portsBIO_filtered_1[1].ready, UInt<1>(0h0)) node _portsBIO_T_5 = or(_portsBIO_T_3, _portsBIO_T_4) wire _portsBIO_WIRE_5 : UInt<1> connect _portsBIO_WIRE_5, _portsBIO_T_5 connect _portsBIO_WIRE_4.ready, _portsBIO_WIRE_5 wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<32>(0h0) connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE.bits.source, UInt<6>(0h0) connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_2 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _portsCOI_WIRE_3.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE_3.bits.data, UInt<32>(0h0) connect _portsCOI_WIRE_3.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE_3.bits.source, UInt<6>(0h0) connect _portsCOI_WIRE_3.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE_3.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE_3.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE_3.valid, UInt<1>(0h0) connect _portsCOI_WIRE_3.ready, UInt<1>(0h0) wire _portsCOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _portsCOI_WIRE_4.bits, _portsCOI_WIRE_3.bits connect _portsCOI_WIRE_4.valid, _portsCOI_WIRE_3.valid connect _portsCOI_WIRE_4.ready, _portsCOI_WIRE_3.ready wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_4.bits node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_4.valid, _portsCOI_filtered_0_valid_T_2) connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 connect portsCOI_filtered_1[1].bits, _portsCOI_WIRE_4.bits node _portsCOI_filtered_1_valid_T_2 = or(requestCIO_1_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_3 = and(_portsCOI_WIRE_4.valid, _portsCOI_filtered_1_valid_T_2) connect portsCOI_filtered_1[1].valid, _portsCOI_filtered_1_valid_T_3 node _portsCOI_T_3 = mux(requestCIO_1_0, portsCOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsCOI_T_4 = mux(requestCIO_1_1, portsCOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsCOI_T_5 = or(_portsCOI_T_3, _portsCOI_T_4) wire _portsCOI_WIRE_5 : UInt<1> connect _portsCOI_WIRE_5, _portsCOI_T_5 connect _portsCOI_WIRE_4.ready, _portsCOI_WIRE_5 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[1].bits.data, out[0].d.bits.data connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[1].bits.source, out[0].d.bits.source connect portsDIO_filtered[1].bits.size, out[0].d.bits.size connect portsDIO_filtered[1].bits.param, out[0].d.bits.param connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) wire _portsDIO_out_0_d_ready_WIRE : UInt<1> connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[2] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect portsDIO_filtered_1[1].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[1].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[1].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[1].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[1].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[1].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[1].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[1].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_1_valid_T_2 = or(requestDOI_1_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_1_valid_T_2) connect portsDIO_filtered_1[1].valid, _portsDIO_filtered_1_valid_T_3 node _portsDIO_out_1_d_ready_T = mux(requestDOI_1_0, portsDIO_filtered_1[0].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_1 = mux(requestDOI_1_1, portsDIO_filtered_1[1].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_2 = or(_portsDIO_out_1_d_ready_T, _portsDIO_out_1_d_ready_T_1) wire _portsDIO_out_1_d_ready_WIRE : UInt<1> connect _portsDIO_out_1_d_ready_WIRE, _portsDIO_out_1_d_ready_T_2 connect out[1].d.ready, _portsDIO_out_1_d_ready_WIRE wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _portsEOI_WIRE.bits.sink, UInt<3>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(requestEIO_0_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(requestEIO_0_1, portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_2 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _portsEOI_WIRE_3.bits.sink, UInt<3>(0h0) connect _portsEOI_WIRE_3.valid, UInt<1>(0h0) connect _portsEOI_WIRE_3.ready, UInt<1>(0h0) wire _portsEOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _portsEOI_WIRE_4.bits, _portsEOI_WIRE_3.bits connect _portsEOI_WIRE_4.valid, _portsEOI_WIRE_3.valid connect _portsEOI_WIRE_4.ready, _portsEOI_WIRE_3.ready wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2] connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_4.bits node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_4.valid, _portsEOI_filtered_0_valid_T_2) connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 connect portsEOI_filtered_1[1].bits, _portsEOI_WIRE_4.bits node _portsEOI_filtered_1_valid_T_2 = or(requestEIO_1_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_3 = and(_portsEOI_WIRE_4.valid, _portsEOI_filtered_1_valid_T_2) connect portsEOI_filtered_1[1].valid, _portsEOI_filtered_1_valid_T_3 node _portsEOI_T_3 = mux(UInt<1>(0h0), portsEOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsEOI_T_4 = mux(requestEIO_1_1, portsEOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsEOI_T_5 = or(_portsEOI_T_3, _portsEOI_T_4) wire _portsEOI_WIRE_5 : UInt<1> connect _portsEOI_WIRE_5, _portsEOI_T_5 connect _portsEOI_WIRE_4.ready, _portsEOI_WIRE_5 regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, out[0].a.ready) node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsAOI_filtered[0].valid) node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) connect portsAOI_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) wire _out_0_a_valid_WIRE : UInt<1> connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) connect out[0].a.valid, _out_0_a_valid_T_4 wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) wire _out_0_a_bits_WIRE_1 : UInt<1> connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) wire _out_0_a_bits_WIRE_2 : UInt<32> connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) wire _out_0_a_bits_WIRE_3 : UInt<4> connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 wire _out_0_a_bits_WIRE_4 : { } connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 wire _out_0_a_bits_WIRE_5 : { } connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) wire _out_0_a_bits_WIRE_6 : UInt<32> connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11 connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6 node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) wire _out_0_a_bits_WIRE_7 : UInt<6> connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14 connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7 node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) wire _out_0_a_bits_WIRE_8 : UInt<4> connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17 connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8 node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) wire _out_0_a_bits_WIRE_9 : UInt<3> connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20 connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9 node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) wire _out_0_a_bits_WIRE_10 : UInt<3> connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23 connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10 connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt connect out[0].a.bits.data, _out_0_a_bits_WIRE.data connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask connect out[0].a.bits.address, _out_0_a_bits_WIRE.address connect out[0].a.bits.source, _out_0_a_bits_WIRE.source connect out[0].a.bits.size, _out_0_a_bits_WIRE.size connect out[0].a.bits.param, _out_0_a_bits_WIRE.param connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode wire _WIRE_96 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_96.bits.corrupt, UInt<1>(0h0) connect _WIRE_96.bits.data, UInt<32>(0h0) connect _WIRE_96.bits.address, UInt<32>(0h0) connect _WIRE_96.bits.source, UInt<6>(0h0) connect _WIRE_96.bits.size, UInt<4>(0h0) connect _WIRE_96.bits.param, UInt<3>(0h0) connect _WIRE_96.bits.opcode, UInt<3>(0h0) connect _WIRE_96.valid, UInt<1>(0h0) connect _WIRE_96.ready, UInt<1>(0h0) wire _WIRE_97 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_97.bits, _WIRE_96.bits connect _WIRE_97.valid, _WIRE_96.valid connect _WIRE_97.ready, _WIRE_96.ready invalidate _WIRE_97.bits.corrupt invalidate _WIRE_97.bits.data invalidate _WIRE_97.bits.address invalidate _WIRE_97.bits.source invalidate _WIRE_97.bits.size invalidate _WIRE_97.bits.param invalidate _WIRE_97.bits.opcode wire _WIRE_98 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_98.bits.sink, UInt<3>(0h0) connect _WIRE_98.valid, UInt<1>(0h0) connect _WIRE_98.ready, UInt<1>(0h0) wire _WIRE_99 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_99.bits, _WIRE_98.bits connect _WIRE_99.valid, _WIRE_98.valid connect _WIRE_99.ready, _WIRE_98.ready invalidate _WIRE_99.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0) node idle_1 = eq(beatsLeft_1, UInt<1>(0h0)) node latch_1 = and(idle_1, out[1].a.ready) node _readys_T_10 = cat(portsAOI_filtered_1[1].valid, portsAOI_filtered[1].valid) node readys_valid_1 = bits(_readys_T_10, 1, 0) node _readys_T_11 = eq(readys_valid_1, _readys_T_10) node _readys_T_12 = asUInt(reset) node _readys_T_13 = eq(_readys_T_12, UInt<1>(0h0)) when _readys_T_13 : node _readys_T_14 = eq(_readys_T_11, UInt<1>(0h0)) when _readys_T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_1 assert(clock, _readys_T_11, UInt<1>(0h1), "") : readys_assert_1 regreset readys_mask_1 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_2 = not(readys_mask_1) node _readys_filter_T_3 = and(readys_valid_1, _readys_filter_T_2) node readys_filter_1 = cat(_readys_filter_T_3, readys_valid_1) node _readys_unready_T_5 = shr(readys_filter_1, 1) node _readys_unready_T_6 = or(readys_filter_1, _readys_unready_T_5) node _readys_unready_T_7 = bits(_readys_unready_T_6, 3, 0) node _readys_unready_T_8 = shr(_readys_unready_T_7, 1) node _readys_unready_T_9 = shl(readys_mask_1, 2) node readys_unready_1 = or(_readys_unready_T_8, _readys_unready_T_9) node _readys_readys_T_3 = shr(readys_unready_1, 2) node _readys_readys_T_4 = bits(readys_unready_1, 1, 0) node _readys_readys_T_5 = and(_readys_readys_T_3, _readys_readys_T_4) node readys_readys_1 = not(_readys_readys_T_5) node _readys_T_15 = orr(readys_valid_1) node _readys_T_16 = and(latch_1, _readys_T_15) when _readys_T_16 : node _readys_mask_T_5 = and(readys_readys_1, readys_valid_1) node _readys_mask_T_6 = shl(_readys_mask_T_5, 1) node _readys_mask_T_7 = bits(_readys_mask_T_6, 1, 0) node _readys_mask_T_8 = or(_readys_mask_T_5, _readys_mask_T_7) node _readys_mask_T_9 = bits(_readys_mask_T_8, 1, 0) connect readys_mask_1, _readys_mask_T_9 node _readys_T_17 = bits(readys_readys_1, 1, 0) node _readys_T_18 = bits(_readys_T_17, 0, 0) node _readys_T_19 = bits(_readys_T_17, 1, 1) wire readys_1 : UInt<1>[2] connect readys_1[0], _readys_T_18 connect readys_1[1], _readys_T_19 node _winner_T_2 = and(readys_1[0], portsAOI_filtered[1].valid) node _winner_T_3 = and(readys_1[1], portsAOI_filtered_1[1].valid) wire winner_1 : UInt<1>[2] connect winner_1[0], _winner_T_2 connect winner_1[1], _winner_T_3 node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0]) node _prefixOR_T_1 = or(prefixOR_1_1, winner_1[1]) node _T_17 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_18 = eq(winner_1[0], UInt<1>(0h0)) node _T_19 = or(_T_17, _T_18) node _T_20 = eq(prefixOR_1_1, UInt<1>(0h0)) node _T_21 = eq(winner_1[1], UInt<1>(0h0)) node _T_22 = or(_T_20, _T_21) node _T_23 = and(_T_19, _T_22) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_2 assert(clock, _T_23, UInt<1>(0h1), "") : assert_2 node _T_27 = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid) node _T_28 = eq(_T_27, UInt<1>(0h0)) node _T_29 = or(winner_1[0], winner_1[1]) node _T_30 = or(_T_28, _T_29) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_3 assert(clock, _T_30, UInt<1>(0h1), "") : assert_3 node maskedBeats_0_1 = mux(winner_1[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1_1 = mux(winner_1[1], beatsAI_1, UInt<1>(0h0)) node initBeats_1 = or(maskedBeats_0_1, maskedBeats_1_1) node _beatsLeft_T_4 = and(out[1].a.ready, out[1].a.valid) node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4) node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1) node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6) connect beatsLeft_1, _beatsLeft_T_7 wire _state_WIRE_1 : UInt<1>[2] connect _state_WIRE_1[0], UInt<1>(0h0) connect _state_WIRE_1[1], UInt<1>(0h0) regreset state_1 : UInt<1>[2], clock, reset, _state_WIRE_1 node muxState_1 = mux(idle_1, winner_1, state_1) connect state_1, muxState_1 node allowed_1 = mux(idle_1, readys_1, state_1) node _filtered_1_ready_T = and(out[1].a.ready, allowed_1[0]) connect portsAOI_filtered[1].ready, _filtered_1_ready_T node _filtered_1_ready_T_1 = and(out[1].a.ready, allowed_1[1]) connect portsAOI_filtered_1[1].ready, _filtered_1_ready_T_1 node _out_1_a_valid_T = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid) node _out_1_a_valid_T_1 = mux(state_1[0], portsAOI_filtered[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_2 = mux(state_1[1], portsAOI_filtered_1[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_3 = or(_out_1_a_valid_T_1, _out_1_a_valid_T_2) wire _out_1_a_valid_WIRE : UInt<1> connect _out_1_a_valid_WIRE, _out_1_a_valid_T_3 node _out_1_a_valid_T_4 = mux(idle_1, _out_1_a_valid_T, _out_1_a_valid_WIRE) connect out[1].a.valid, _out_1_a_valid_T_4 wire _out_1_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} node _out_1_a_bits_T = mux(muxState_1[0], portsAOI_filtered[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_1 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_2 = or(_out_1_a_bits_T, _out_1_a_bits_T_1) wire _out_1_a_bits_WIRE_1 : UInt<1> connect _out_1_a_bits_WIRE_1, _out_1_a_bits_T_2 connect _out_1_a_bits_WIRE.corrupt, _out_1_a_bits_WIRE_1 node _out_1_a_bits_T_3 = mux(muxState_1[0], portsAOI_filtered[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_4 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_5 = or(_out_1_a_bits_T_3, _out_1_a_bits_T_4) wire _out_1_a_bits_WIRE_2 : UInt<32> connect _out_1_a_bits_WIRE_2, _out_1_a_bits_T_5 connect _out_1_a_bits_WIRE.data, _out_1_a_bits_WIRE_2 node _out_1_a_bits_T_6 = mux(muxState_1[0], portsAOI_filtered[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_7 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_8 = or(_out_1_a_bits_T_6, _out_1_a_bits_T_7) wire _out_1_a_bits_WIRE_3 : UInt<4> connect _out_1_a_bits_WIRE_3, _out_1_a_bits_T_8 connect _out_1_a_bits_WIRE.mask, _out_1_a_bits_WIRE_3 wire _out_1_a_bits_WIRE_4 : { } connect _out_1_a_bits_WIRE.echo, _out_1_a_bits_WIRE_4 wire _out_1_a_bits_WIRE_5 : { } connect _out_1_a_bits_WIRE.user, _out_1_a_bits_WIRE_5 node _out_1_a_bits_T_9 = mux(muxState_1[0], portsAOI_filtered[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_10 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_11 = or(_out_1_a_bits_T_9, _out_1_a_bits_T_10) wire _out_1_a_bits_WIRE_6 : UInt<32> connect _out_1_a_bits_WIRE_6, _out_1_a_bits_T_11 connect _out_1_a_bits_WIRE.address, _out_1_a_bits_WIRE_6 node _out_1_a_bits_T_12 = mux(muxState_1[0], portsAOI_filtered[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_13 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_14 = or(_out_1_a_bits_T_12, _out_1_a_bits_T_13) wire _out_1_a_bits_WIRE_7 : UInt<6> connect _out_1_a_bits_WIRE_7, _out_1_a_bits_T_14 connect _out_1_a_bits_WIRE.source, _out_1_a_bits_WIRE_7 node _out_1_a_bits_T_15 = mux(muxState_1[0], portsAOI_filtered[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_16 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_17 = or(_out_1_a_bits_T_15, _out_1_a_bits_T_16) wire _out_1_a_bits_WIRE_8 : UInt<4> connect _out_1_a_bits_WIRE_8, _out_1_a_bits_T_17 connect _out_1_a_bits_WIRE.size, _out_1_a_bits_WIRE_8 node _out_1_a_bits_T_18 = mux(muxState_1[0], portsAOI_filtered[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_19 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_20 = or(_out_1_a_bits_T_18, _out_1_a_bits_T_19) wire _out_1_a_bits_WIRE_9 : UInt<3> connect _out_1_a_bits_WIRE_9, _out_1_a_bits_T_20 connect _out_1_a_bits_WIRE.param, _out_1_a_bits_WIRE_9 node _out_1_a_bits_T_21 = mux(muxState_1[0], portsAOI_filtered[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_22 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_23 = or(_out_1_a_bits_T_21, _out_1_a_bits_T_22) wire _out_1_a_bits_WIRE_10 : UInt<3> connect _out_1_a_bits_WIRE_10, _out_1_a_bits_T_23 connect _out_1_a_bits_WIRE.opcode, _out_1_a_bits_WIRE_10 connect out[1].a.bits.corrupt, _out_1_a_bits_WIRE.corrupt connect out[1].a.bits.data, _out_1_a_bits_WIRE.data connect out[1].a.bits.mask, _out_1_a_bits_WIRE.mask connect out[1].a.bits.address, _out_1_a_bits_WIRE.address connect out[1].a.bits.source, _out_1_a_bits_WIRE.source connect out[1].a.bits.size, _out_1_a_bits_WIRE.size connect out[1].a.bits.param, _out_1_a_bits_WIRE.param connect out[1].a.bits.opcode, _out_1_a_bits_WIRE.opcode wire _WIRE_100 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_100.bits.corrupt, UInt<1>(0h0) connect _WIRE_100.bits.data, UInt<32>(0h0) connect _WIRE_100.bits.address, UInt<32>(0h0) connect _WIRE_100.bits.source, UInt<6>(0h0) connect _WIRE_100.bits.size, UInt<4>(0h0) connect _WIRE_100.bits.param, UInt<3>(0h0) connect _WIRE_100.bits.opcode, UInt<3>(0h0) connect _WIRE_100.valid, UInt<1>(0h0) connect _WIRE_100.ready, UInt<1>(0h0) wire _WIRE_101 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_101.bits, _WIRE_100.bits connect _WIRE_101.valid, _WIRE_100.valid connect _WIRE_101.ready, _WIRE_100.ready invalidate _WIRE_101.bits.corrupt invalidate _WIRE_101.bits.data invalidate _WIRE_101.bits.address invalidate _WIRE_101.bits.source invalidate _WIRE_101.bits.size invalidate _WIRE_101.bits.param invalidate _WIRE_101.bits.opcode wire _WIRE_102 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_102.bits.sink, UInt<3>(0h0) connect _WIRE_102.valid, UInt<1>(0h0) connect _WIRE_102.ready, UInt<1>(0h0) wire _WIRE_103 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_103.bits, _WIRE_102.bits connect _WIRE_103.valid, _WIRE_102.valid connect _WIRE_103.ready, _WIRE_102.ready invalidate _WIRE_103.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsCOI_filtered_1[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered_1[1].ready, UInt<1>(0h0) wire _WIRE_104 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_104.bits.corrupt, UInt<1>(0h0) connect _WIRE_104.bits.data, UInt<32>(0h0) connect _WIRE_104.bits.mask, UInt<4>(0h0) connect _WIRE_104.bits.address, UInt<32>(0h0) connect _WIRE_104.bits.source, UInt<6>(0h0) connect _WIRE_104.bits.size, UInt<4>(0h0) connect _WIRE_104.bits.param, UInt<2>(0h0) connect _WIRE_104.bits.opcode, UInt<3>(0h0) connect _WIRE_104.valid, UInt<1>(0h0) connect _WIRE_104.ready, UInt<1>(0h0) wire _WIRE_105 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_105.bits, _WIRE_104.bits connect _WIRE_105.valid, _WIRE_104.valid connect _WIRE_105.ready, _WIRE_104.ready invalidate _WIRE_105.bits.corrupt invalidate _WIRE_105.bits.data invalidate _WIRE_105.bits.mask invalidate _WIRE_105.bits.address invalidate _WIRE_105.bits.source invalidate _WIRE_105.bits.size invalidate _WIRE_105.bits.param invalidate _WIRE_105.bits.opcode regreset beatsLeft_2 : UInt, clock, reset, UInt<1>(0h0) node idle_2 = eq(beatsLeft_2, UInt<1>(0h0)) node latch_2 = and(idle_2, in[0].d.ready) node _readys_T_20 = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid_2 = bits(_readys_T_20, 1, 0) node _readys_T_21 = eq(readys_valid_2, _readys_T_20) node _readys_T_22 = asUInt(reset) node _readys_T_23 = eq(_readys_T_22, UInt<1>(0h0)) when _readys_T_23 : node _readys_T_24 = eq(_readys_T_21, UInt<1>(0h0)) when _readys_T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_2 assert(clock, _readys_T_21, UInt<1>(0h1), "") : readys_assert_2 regreset readys_mask_2 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_4 = not(readys_mask_2) node _readys_filter_T_5 = and(readys_valid_2, _readys_filter_T_4) node readys_filter_2 = cat(_readys_filter_T_5, readys_valid_2) node _readys_unready_T_10 = shr(readys_filter_2, 1) node _readys_unready_T_11 = or(readys_filter_2, _readys_unready_T_10) node _readys_unready_T_12 = bits(_readys_unready_T_11, 3, 0) node _readys_unready_T_13 = shr(_readys_unready_T_12, 1) node _readys_unready_T_14 = shl(readys_mask_2, 2) node readys_unready_2 = or(_readys_unready_T_13, _readys_unready_T_14) node _readys_readys_T_6 = shr(readys_unready_2, 2) node _readys_readys_T_7 = bits(readys_unready_2, 1, 0) node _readys_readys_T_8 = and(_readys_readys_T_6, _readys_readys_T_7) node readys_readys_2 = not(_readys_readys_T_8) node _readys_T_25 = orr(readys_valid_2) node _readys_T_26 = and(latch_2, _readys_T_25) when _readys_T_26 : node _readys_mask_T_10 = and(readys_readys_2, readys_valid_2) node _readys_mask_T_11 = shl(_readys_mask_T_10, 1) node _readys_mask_T_12 = bits(_readys_mask_T_11, 1, 0) node _readys_mask_T_13 = or(_readys_mask_T_10, _readys_mask_T_12) node _readys_mask_T_14 = bits(_readys_mask_T_13, 1, 0) connect readys_mask_2, _readys_mask_T_14 node _readys_T_27 = bits(readys_readys_2, 1, 0) node _readys_T_28 = bits(_readys_T_27, 0, 0) node _readys_T_29 = bits(_readys_T_27, 1, 1) wire readys_2 : UInt<1>[2] connect readys_2[0], _readys_T_28 connect readys_2[1], _readys_T_29 node _winner_T_4 = and(readys_2[0], portsDIO_filtered[0].valid) node _winner_T_5 = and(readys_2[1], portsDIO_filtered_1[0].valid) wire winner_2 : UInt<1>[2] connect winner_2[0], _winner_T_4 connect winner_2[1], _winner_T_5 node prefixOR_1_2 = or(UInt<1>(0h0), winner_2[0]) node _prefixOR_T_2 = or(prefixOR_1_2, winner_2[1]) node _T_34 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_35 = eq(winner_2[0], UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = eq(prefixOR_1_2, UInt<1>(0h0)) node _T_38 = eq(winner_2[1], UInt<1>(0h0)) node _T_39 = or(_T_37, _T_38) node _T_40 = and(_T_36, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_4 assert(clock, _T_40, UInt<1>(0h1), "") : assert_4 node _T_44 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_45 = eq(_T_44, UInt<1>(0h0)) node _T_46 = or(winner_2[0], winner_2[1]) node _T_47 = or(_T_45, _T_46) node _T_48 = asUInt(reset) node _T_49 = eq(_T_48, UInt<1>(0h0)) when _T_49 : node _T_50 = eq(_T_47, UInt<1>(0h0)) when _T_50 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_5 assert(clock, _T_47, UInt<1>(0h1), "") : assert_5 node maskedBeats_0_2 = mux(winner_2[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_2 = mux(winner_2[1], beatsDO_1, UInt<1>(0h0)) node initBeats_2 = or(maskedBeats_0_2, maskedBeats_1_2) node _beatsLeft_T_8 = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_9 = sub(beatsLeft_2, _beatsLeft_T_8) node _beatsLeft_T_10 = tail(_beatsLeft_T_9, 1) node _beatsLeft_T_11 = mux(latch_2, initBeats_2, _beatsLeft_T_10) connect beatsLeft_2, _beatsLeft_T_11 wire _state_WIRE_2 : UInt<1>[2] connect _state_WIRE_2[0], UInt<1>(0h0) connect _state_WIRE_2[1], UInt<1>(0h0) regreset state_2 : UInt<1>[2], clock, reset, _state_WIRE_2 node muxState_2 = mux(idle_2, winner_2, state_2) connect state_2, muxState_2 node allowed_2 = mux(idle_2, readys_2, state_2) node _filtered_0_ready_T_2 = and(in[0].d.ready, allowed_2[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T_2 node _filtered_0_ready_T_3 = and(in[0].d.ready, allowed_2[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_3 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state_2[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state_2[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle_2, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState_2[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState_2[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<32> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState_2[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState_2[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<3> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState_2[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<6> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState_2[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<4> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState_2[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState_2[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) wire _WIRE_106 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_106.bits.corrupt, UInt<1>(0h0) connect _WIRE_106.bits.data, UInt<32>(0h0) connect _WIRE_106.bits.mask, UInt<4>(0h0) connect _WIRE_106.bits.address, UInt<32>(0h0) connect _WIRE_106.bits.source, UInt<6>(0h0) connect _WIRE_106.bits.size, UInt<4>(0h0) connect _WIRE_106.bits.param, UInt<2>(0h0) connect _WIRE_106.bits.opcode, UInt<3>(0h0) connect _WIRE_106.valid, UInt<1>(0h0) connect _WIRE_106.ready, UInt<1>(0h0) wire _WIRE_107 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_107.bits, _WIRE_106.bits connect _WIRE_107.valid, _WIRE_106.valid connect _WIRE_107.ready, _WIRE_106.ready invalidate _WIRE_107.bits.corrupt invalidate _WIRE_107.bits.data invalidate _WIRE_107.bits.mask invalidate _WIRE_107.bits.address invalidate _WIRE_107.bits.source invalidate _WIRE_107.bits.size invalidate _WIRE_107.bits.param invalidate _WIRE_107.bits.opcode regreset beatsLeft_3 : UInt, clock, reset, UInt<1>(0h0) node idle_3 = eq(beatsLeft_3, UInt<1>(0h0)) node latch_3 = and(idle_3, in[1].d.ready) node _readys_T_30 = cat(portsDIO_filtered_1[1].valid, portsDIO_filtered[1].valid) node readys_valid_3 = bits(_readys_T_30, 1, 0) node _readys_T_31 = eq(readys_valid_3, _readys_T_30) node _readys_T_32 = asUInt(reset) node _readys_T_33 = eq(_readys_T_32, UInt<1>(0h0)) when _readys_T_33 : node _readys_T_34 = eq(_readys_T_31, UInt<1>(0h0)) when _readys_T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_3 assert(clock, _readys_T_31, UInt<1>(0h1), "") : readys_assert_3 regreset readys_mask_3 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_6 = not(readys_mask_3) node _readys_filter_T_7 = and(readys_valid_3, _readys_filter_T_6) node readys_filter_3 = cat(_readys_filter_T_7, readys_valid_3) node _readys_unready_T_15 = shr(readys_filter_3, 1) node _readys_unready_T_16 = or(readys_filter_3, _readys_unready_T_15) node _readys_unready_T_17 = bits(_readys_unready_T_16, 3, 0) node _readys_unready_T_18 = shr(_readys_unready_T_17, 1) node _readys_unready_T_19 = shl(readys_mask_3, 2) node readys_unready_3 = or(_readys_unready_T_18, _readys_unready_T_19) node _readys_readys_T_9 = shr(readys_unready_3, 2) node _readys_readys_T_10 = bits(readys_unready_3, 1, 0) node _readys_readys_T_11 = and(_readys_readys_T_9, _readys_readys_T_10) node readys_readys_3 = not(_readys_readys_T_11) node _readys_T_35 = orr(readys_valid_3) node _readys_T_36 = and(latch_3, _readys_T_35) when _readys_T_36 : node _readys_mask_T_15 = and(readys_readys_3, readys_valid_3) node _readys_mask_T_16 = shl(_readys_mask_T_15, 1) node _readys_mask_T_17 = bits(_readys_mask_T_16, 1, 0) node _readys_mask_T_18 = or(_readys_mask_T_15, _readys_mask_T_17) node _readys_mask_T_19 = bits(_readys_mask_T_18, 1, 0) connect readys_mask_3, _readys_mask_T_19 node _readys_T_37 = bits(readys_readys_3, 1, 0) node _readys_T_38 = bits(_readys_T_37, 0, 0) node _readys_T_39 = bits(_readys_T_37, 1, 1) wire readys_3 : UInt<1>[2] connect readys_3[0], _readys_T_38 connect readys_3[1], _readys_T_39 node _winner_T_6 = and(readys_3[0], portsDIO_filtered[1].valid) node _winner_T_7 = and(readys_3[1], portsDIO_filtered_1[1].valid) wire winner_3 : UInt<1>[2] connect winner_3[0], _winner_T_6 connect winner_3[1], _winner_T_7 node prefixOR_1_3 = or(UInt<1>(0h0), winner_3[0]) node _prefixOR_T_3 = or(prefixOR_1_3, winner_3[1]) node _T_51 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_52 = eq(winner_3[0], UInt<1>(0h0)) node _T_53 = or(_T_51, _T_52) node _T_54 = eq(prefixOR_1_3, UInt<1>(0h0)) node _T_55 = eq(winner_3[1], UInt<1>(0h0)) node _T_56 = or(_T_54, _T_55) node _T_57 = and(_T_53, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_6 assert(clock, _T_57, UInt<1>(0h1), "") : assert_6 node _T_61 = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid) node _T_62 = eq(_T_61, UInt<1>(0h0)) node _T_63 = or(winner_3[0], winner_3[1]) node _T_64 = or(_T_62, _T_63) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_7 assert(clock, _T_64, UInt<1>(0h1), "") : assert_7 node maskedBeats_0_3 = mux(winner_3[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_3 = mux(winner_3[1], beatsDO_1, UInt<1>(0h0)) node initBeats_3 = or(maskedBeats_0_3, maskedBeats_1_3) node _beatsLeft_T_12 = and(in[1].d.ready, in[1].d.valid) node _beatsLeft_T_13 = sub(beatsLeft_3, _beatsLeft_T_12) node _beatsLeft_T_14 = tail(_beatsLeft_T_13, 1) node _beatsLeft_T_15 = mux(latch_3, initBeats_3, _beatsLeft_T_14) connect beatsLeft_3, _beatsLeft_T_15 wire _state_WIRE_3 : UInt<1>[2] connect _state_WIRE_3[0], UInt<1>(0h0) connect _state_WIRE_3[1], UInt<1>(0h0) regreset state_3 : UInt<1>[2], clock, reset, _state_WIRE_3 node muxState_3 = mux(idle_3, winner_3, state_3) connect state_3, muxState_3 node allowed_3 = mux(idle_3, readys_3, state_3) node _filtered_1_ready_T_2 = and(in[1].d.ready, allowed_3[0]) connect portsDIO_filtered[1].ready, _filtered_1_ready_T_2 node _filtered_1_ready_T_3 = and(in[1].d.ready, allowed_3[1]) connect portsDIO_filtered_1[1].ready, _filtered_1_ready_T_3 node _in_1_d_valid_T = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid) node _in_1_d_valid_T_1 = mux(state_3[0], portsDIO_filtered[1].valid, UInt<1>(0h0)) node _in_1_d_valid_T_2 = mux(state_3[1], portsDIO_filtered_1[1].valid, UInt<1>(0h0)) node _in_1_d_valid_T_3 = or(_in_1_d_valid_T_1, _in_1_d_valid_T_2) wire _in_1_d_valid_WIRE : UInt<1> connect _in_1_d_valid_WIRE, _in_1_d_valid_T_3 node _in_1_d_valid_T_4 = mux(idle_3, _in_1_d_valid_T, _in_1_d_valid_WIRE) connect in[1].d.valid, _in_1_d_valid_T_4 wire _in_1_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} node _in_1_d_bits_T = mux(muxState_3[0], portsDIO_filtered[1].bits.corrupt, UInt<1>(0h0)) node _in_1_d_bits_T_1 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.corrupt, UInt<1>(0h0)) node _in_1_d_bits_T_2 = or(_in_1_d_bits_T, _in_1_d_bits_T_1) wire _in_1_d_bits_WIRE_1 : UInt<1> connect _in_1_d_bits_WIRE_1, _in_1_d_bits_T_2 connect _in_1_d_bits_WIRE.corrupt, _in_1_d_bits_WIRE_1 node _in_1_d_bits_T_3 = mux(muxState_3[0], portsDIO_filtered[1].bits.data, UInt<1>(0h0)) node _in_1_d_bits_T_4 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.data, UInt<1>(0h0)) node _in_1_d_bits_T_5 = or(_in_1_d_bits_T_3, _in_1_d_bits_T_4) wire _in_1_d_bits_WIRE_2 : UInt<32> connect _in_1_d_bits_WIRE_2, _in_1_d_bits_T_5 connect _in_1_d_bits_WIRE.data, _in_1_d_bits_WIRE_2 wire _in_1_d_bits_WIRE_3 : { } connect _in_1_d_bits_WIRE.echo, _in_1_d_bits_WIRE_3 wire _in_1_d_bits_WIRE_4 : { } connect _in_1_d_bits_WIRE.user, _in_1_d_bits_WIRE_4 node _in_1_d_bits_T_6 = mux(muxState_3[0], portsDIO_filtered[1].bits.denied, UInt<1>(0h0)) node _in_1_d_bits_T_7 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.denied, UInt<1>(0h0)) node _in_1_d_bits_T_8 = or(_in_1_d_bits_T_6, _in_1_d_bits_T_7) wire _in_1_d_bits_WIRE_5 : UInt<1> connect _in_1_d_bits_WIRE_5, _in_1_d_bits_T_8 connect _in_1_d_bits_WIRE.denied, _in_1_d_bits_WIRE_5 node _in_1_d_bits_T_9 = mux(muxState_3[0], portsDIO_filtered[1].bits.sink, UInt<1>(0h0)) node _in_1_d_bits_T_10 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.sink, UInt<1>(0h0)) node _in_1_d_bits_T_11 = or(_in_1_d_bits_T_9, _in_1_d_bits_T_10) wire _in_1_d_bits_WIRE_6 : UInt<3> connect _in_1_d_bits_WIRE_6, _in_1_d_bits_T_11 connect _in_1_d_bits_WIRE.sink, _in_1_d_bits_WIRE_6 node _in_1_d_bits_T_12 = mux(muxState_3[0], portsDIO_filtered[1].bits.source, UInt<1>(0h0)) node _in_1_d_bits_T_13 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.source, UInt<1>(0h0)) node _in_1_d_bits_T_14 = or(_in_1_d_bits_T_12, _in_1_d_bits_T_13) wire _in_1_d_bits_WIRE_7 : UInt<6> connect _in_1_d_bits_WIRE_7, _in_1_d_bits_T_14 connect _in_1_d_bits_WIRE.source, _in_1_d_bits_WIRE_7 node _in_1_d_bits_T_15 = mux(muxState_3[0], portsDIO_filtered[1].bits.size, UInt<1>(0h0)) node _in_1_d_bits_T_16 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.size, UInt<1>(0h0)) node _in_1_d_bits_T_17 = or(_in_1_d_bits_T_15, _in_1_d_bits_T_16) wire _in_1_d_bits_WIRE_8 : UInt<4> connect _in_1_d_bits_WIRE_8, _in_1_d_bits_T_17 connect _in_1_d_bits_WIRE.size, _in_1_d_bits_WIRE_8 node _in_1_d_bits_T_18 = mux(muxState_3[0], portsDIO_filtered[1].bits.param, UInt<1>(0h0)) node _in_1_d_bits_T_19 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.param, UInt<1>(0h0)) node _in_1_d_bits_T_20 = or(_in_1_d_bits_T_18, _in_1_d_bits_T_19) wire _in_1_d_bits_WIRE_9 : UInt<2> connect _in_1_d_bits_WIRE_9, _in_1_d_bits_T_20 connect _in_1_d_bits_WIRE.param, _in_1_d_bits_WIRE_9 node _in_1_d_bits_T_21 = mux(muxState_3[0], portsDIO_filtered[1].bits.opcode, UInt<1>(0h0)) node _in_1_d_bits_T_22 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.opcode, UInt<1>(0h0)) node _in_1_d_bits_T_23 = or(_in_1_d_bits_T_21, _in_1_d_bits_T_22) wire _in_1_d_bits_WIRE_10 : UInt<3> connect _in_1_d_bits_WIRE_10, _in_1_d_bits_T_23 connect _in_1_d_bits_WIRE.opcode, _in_1_d_bits_WIRE_10 connect in[1].d.bits.corrupt, _in_1_d_bits_WIRE.corrupt connect in[1].d.bits.data, _in_1_d_bits_WIRE.data connect in[1].d.bits.denied, _in_1_d_bits_WIRE.denied connect in[1].d.bits.sink, _in_1_d_bits_WIRE.sink connect in[1].d.bits.source, _in_1_d_bits_WIRE.source connect in[1].d.bits.size, _in_1_d_bits_WIRE.size connect in[1].d.bits.param, _in_1_d_bits_WIRE.param connect in[1].d.bits.opcode, _in_1_d_bits_WIRE.opcode connect portsBIO_filtered[1].ready, UInt<1>(0h0) connect portsBIO_filtered_1[1].ready, UInt<1>(0h0)

module TLXbar_sbus_i2_o2_a32d32s6k3z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [2:0] out_1_d_bits_sink; // @[Xbar.scala:216:19] wire [3:0] out_1_d_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [5:0] in_1_a_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param_0 = auto_anon_out_0_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink_0 = auto_anon_out_0_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire _readys_T_12 = reset; // @[Arbiter.scala:22:12] wire _readys_T_22 = reset; // @[Arbiter.scala:22:12] wire _readys_T_32 = reset; // @[Arbiter.scala:22:12] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire requestBOI_uncommonBits_1 = 1'h0; // @[Parameters.scala:52:56] wire _requestBOI_T_6 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_8 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:56:48] wire _requestBOI_WIRE_4_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_4_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_5_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_5_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_10 = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_6_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_6_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_6_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_7_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_7_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_7_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire requestBOI_uncommonBits_3 = 1'h0; // @[Parameters.scala:52:56] wire _requestBOI_T_16 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_18 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_1_1 = 1'h0; // @[Parameters.scala:56:48] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_4_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_4_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_5_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_5_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_6_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_6_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_7_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_7_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_4_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_4_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T_2 = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_T_3 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_4 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_T_5 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T_3 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_4 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_5 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_4_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_4_valid = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_1_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_2 = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T_3 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_4 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_5 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3_1 = 1'h0; // @[Arbiter.scala:88:34] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_14 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_19 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_11 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_13 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_14 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_19 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_14 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_19 = 1'h1; // @[Parameters.scala:57:20] wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_0_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_1_1 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_6_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_7_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestEIO_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _requestEIO_WIRE_1_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _requestEIO_WIRE_2_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _requestEIO_WIRE_3_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _requestEIO_uncommonBits_T = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestEIO_uncommonBits = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _requestEIO_WIRE_4_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _requestEIO_WIRE_5_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _requestEIO_WIRE_6_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _requestEIO_WIRE_7_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _requestEIO_uncommonBits_T_1 = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestEIO_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsEI_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _beatsEI_WIRE_1_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _beatsEI_WIRE_2_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _beatsEI_WIRE_3_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsEOI_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _portsEOI_WIRE_1_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] portsEOI_filtered_0_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_1_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsEOI_WIRE_3_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] _portsEOI_WIRE_4_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] portsEOI_filtered_1_0_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_1_1_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _addressC_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_10 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_15 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_6_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_6_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_7_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_7_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _beatsCI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _portsBIO_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _portsBIO_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_1_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsCOI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsCOI_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_0_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_1_bits_data = 32'h0; // @[Xbar.scala:352:24] wire [5:0] _addressC_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _addressC_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _addressC_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _addressC_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _requestBOI_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _requestBOI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _requestBOI_uncommonBits_T = 6'h0; // @[Parameters.scala:52:29] wire [5:0] _requestBOI_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _requestBOI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _requestBOI_uncommonBits_T_1 = 6'h0; // @[Parameters.scala:52:29] wire [5:0] _requestBOI_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _requestBOI_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _requestBOI_uncommonBits_T_2 = 6'h0; // @[Parameters.scala:52:29] wire [5:0] _requestBOI_WIRE_6_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _requestBOI_WIRE_7_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _requestBOI_uncommonBits_T_3 = 6'h0; // @[Parameters.scala:52:29] wire [5:0] _beatsBO_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _beatsBO_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _beatsBO_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _beatsBO_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _beatsCI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _beatsCI_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _beatsCI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _portsBIO_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _portsBIO_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] portsBIO_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsBIO_filtered_1_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] _portsBIO_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:74] wire [5:0] _portsBIO_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:264:61] wire [5:0] portsBIO_filtered_1_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsBIO_filtered_1_1_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] _portsCOI_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _portsCOI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] portsCOI_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsCOI_filtered_1_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] _portsCOI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _portsCOI_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] portsCOI_filtered_1_0_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [5:0] portsCOI_filtered_1_1_bits_source = 6'h0; // @[Xbar.scala:352:24] wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_2_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_3_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_4_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_5_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_6_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_6_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _requestBOI_WIRE_7_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _requestBOI_WIRE_7_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_2_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _beatsBO_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _beatsBO_WIRE_3_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] beatsBO_decode_1 = 4'h0; // @[Edges.scala:220:59] wire [3:0] beatsBO_1 = 4'h0; // @[Edges.scala:221:14] wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _portsBIO_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_0_bits_mask = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_mask = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsBIO_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_3_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _portsBIO_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _portsBIO_WIRE_4_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] portsBIO_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_0_bits_mask = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_1_bits_mask = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _portsCOI_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_1_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_4_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_5_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_6_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_7_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_4_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [9:0] beatsBO_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] beatsBO_0 = 10'h0; // @[Edges.scala:221:14] wire [9:0] beatsCI_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] beatsCI_0 = 10'h0; // @[Edges.scala:221:14] wire [9:0] beatsCI_decode_1 = 10'h0; // @[Edges.scala:220:59] wire [9:0] beatsCI_1 = 10'h0; // @[Edges.scala:221:14] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [20:0] _beatsBO_decode_T_3 = 21'h3F; // @[package.scala:243:71] wire [4:0] requestBOI_uncommonBits = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _requestBOI_T_5 = 5'h0; // @[Parameters.scala:54:10] wire [4:0] requestBOI_uncommonBits_2 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _requestBOI_T_15 = 5'h0; // @[Parameters.scala:54:10] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_11 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_12 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_13 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_16 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_18 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = auto_anon_out_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [5:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [4:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [31:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire [3:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69] assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [31:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [5:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [5:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [31:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [5:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [3:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [5:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [31:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [5:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [31:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_1_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_1_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [5:0] _in_1_a_bits_source_T; // @[Xbar.scala:166:55] wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_1_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [5:0] portsAOI_filtered_1_1_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_28 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_1_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_1_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_1_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_1_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_1_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_1_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_1_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_1_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [5:0] _in_1_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire _in_1_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [31:0] _in_1_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire _in_1_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire [5:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [5:0] in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign _in_1_a_bits_source_T = {5'h10, anonIn_1_a_bits_source}; // @[Xbar.scala:166:55] assign in_1_a_bits_source = _in_1_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign _anonIn_d_bits_source_T_1 = in_1_d_bits_source[0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [5:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [5:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] _requestDOI_uncommonBits_T_1 = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [5:0] portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _out_1_a_valid_T_4; // @[Arbiter.scala:96:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19] wire [3:0] _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] wire [31:0] _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] wire _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_1_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_1_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_1_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [5:0] _requestDOI_uncommonBits_T_2 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] _requestDOI_uncommonBits_T_3 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [5:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [5:0] portsDIO_filtered_1_1_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_1_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_1_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsDIO_filtered_1_1_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_1_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire [3:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address[28:0]; // @[Xbar.scala:216:19, :222:41] assign out_0_d_bits_sink = {2'h0, _out_0_d_bits_sink_T}; // @[Xbar.scala:216:19, :251:{28,53}] assign x1_anonOut_a_bits_size = out_1_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41] assign out_1_d_bits_size = {1'h0, x1_anonOut_d_bits_size}; // @[Xbar.scala:216:19, :250:29] assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_5 = {in_0_a_bits_address[31:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_10 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_11 = {1'h0, _requestAIO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_12 = _requestAIO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_13 = _requestAIO_T_12; // @[Parameters.scala:137:46] wire _requestAIO_T_14 = _requestAIO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_15 = _requestAIO_T_4 | _requestAIO_T_9; // @[Xbar.scala:291:92] wire _requestAIO_T_16 = _requestAIO_T_15 | _requestAIO_T_14; // @[Xbar.scala:291:92] wire requestAIO_0_0 = _requestAIO_T_16; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_17 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_18 = {1'h0, _requestAIO_T_17}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_19 = _requestAIO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_20 = _requestAIO_T_19; // @[Parameters.scala:137:46] wire _requestAIO_T_21 = _requestAIO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_22 = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_23 = {1'h0, _requestAIO_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_24 = _requestAIO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_25 = _requestAIO_T_24; // @[Parameters.scala:137:46] wire _requestAIO_T_26 = _requestAIO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_27 = _requestAIO_T_21 | _requestAIO_T_26; // @[Xbar.scala:291:92] wire requestAIO_0_1 = _requestAIO_T_27; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_29 = {1'h0, _requestAIO_T_28}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_30 = _requestAIO_T_29 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_31 = _requestAIO_T_30; // @[Parameters.scala:137:46] wire _requestAIO_T_32 = _requestAIO_T_31 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_33 = {in_1_a_bits_address[31:17], in_1_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_34 = {1'h0, _requestAIO_T_33}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_35 = _requestAIO_T_34 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_36 = _requestAIO_T_35; // @[Parameters.scala:137:46] wire _requestAIO_T_37 = _requestAIO_T_36 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_38 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_39 = {1'h0, _requestAIO_T_38}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_40 = _requestAIO_T_39 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_41 = _requestAIO_T_40; // @[Parameters.scala:137:46] wire _requestAIO_T_42 = _requestAIO_T_41 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_43 = _requestAIO_T_32 | _requestAIO_T_37; // @[Xbar.scala:291:92] wire _requestAIO_T_44 = _requestAIO_T_43 | _requestAIO_T_42; // @[Xbar.scala:291:92] wire requestAIO_1_0 = _requestAIO_T_44; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T_2 = requestAIO_1_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_45 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_46 = {1'h0, _requestAIO_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_47 = _requestAIO_T_46 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_48 = _requestAIO_T_47; // @[Parameters.scala:137:46] wire _requestAIO_T_49 = _requestAIO_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_50 = in_1_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_51 = {1'h0, _requestAIO_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_52 = _requestAIO_T_51 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_53 = _requestAIO_T_52; // @[Parameters.scala:137:46] wire _requestAIO_T_54 = _requestAIO_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_55 = _requestAIO_T_49 | _requestAIO_T_54; // @[Xbar.scala:291:92] wire requestAIO_1_1 = _requestAIO_T_55; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T_2 = requestAIO_1_1; // @[Xbar.scala:307:107, :355:54] wire [4:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T = out_0_d_bits_source[5]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1[0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _requestDOI_T_5 = out_0_d_bits_source[5:1]; // @[Xbar.scala:216:19] wire _requestDOI_T_6 = _requestDOI_T_5 == 5'h10; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_8 = _requestDOI_T_6; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_1 = _requestDOI_T_8; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire [4:0] requestDOI_uncommonBits_2 = _requestDOI_uncommonBits_T_2[4:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_10 = out_1_d_bits_source[5]; // @[Xbar.scala:216:19] wire _requestDOI_T_11 = ~_requestDOI_T_10; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_13 = _requestDOI_T_11; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_0 = _requestDOI_T_13; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T_2 = requestDOI_1_0; // @[Xbar.scala:355:54] wire requestDOI_uncommonBits_3 = _requestDOI_uncommonBits_T_3[0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _requestDOI_T_15 = out_1_d_bits_source[5:1]; // @[Xbar.scala:216:19] wire _requestDOI_T_16 = _requestDOI_T_15 == 5'h10; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_18 = _requestDOI_T_16; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_1 = _requestDOI_T_18; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_1_valid_T_2 = requestDOI_1_1; // @[Xbar.scala:355:54] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] beatsAI_decode = _beatsAI_decode_T_2[11:2]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [9:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:2]; // @[package.scala:243:46] wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [9:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] beatsDO_decode = _beatsDO_decode_T_2[11:2]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [9:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [20:0] _beatsDO_decode_T_3 = 21'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [3:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:2]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [3:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 4'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_1_ready_T; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_1; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:355:40] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_3 = in_1_a_valid & _portsAOI_filtered_0_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_3 = in_1_a_valid & _portsAOI_filtered_1_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_1_valid = _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_1_a_ready_T = requestAIO_1_0 & portsAOI_filtered_1_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_1_a_ready_T_1 = requestAIO_1_1 & portsAOI_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_1_a_ready_T_2 = _portsAOI_in_1_a_ready_T | _portsAOI_in_1_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_1_a_ready_WIRE = _portsAOI_in_1_a_ready_T_2; // @[Mux.scala:30:73] assign in_1_a_ready = _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_2; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_2; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_3; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_3; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:355:40] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] assign _portsDIO_filtered_0_valid_T_3 = out_1_d_valid & _portsDIO_filtered_0_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_3 = out_1_d_valid & _portsDIO_filtered_1_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_1_valid = _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_1_d_ready_T = requestDOI_1_0 & portsDIO_filtered_1_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_1 = requestDOI_1_1 & portsDIO_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_2 = _portsDIO_out_1_d_ready_T | _portsDIO_out_1_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_1_d_ready_WIRE = _portsDIO_out_1_d_ready_T_2; // @[Mux.scala:30:73] assign out_1_d_ready = _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73] reg [9:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 10'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire [9:0] maskedBeats_0 = winner_0 ? beatsAI_0 : 10'h0; // @[Edges.scala:221:14] wire [9:0] maskedBeats_1 = winner_1 ? beatsAI_1 : 10'h0; // @[Edges.scala:221:14] wire [9:0] initBeats = maskedBeats_0 | maskedBeats_1; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T = out_0_a_ready & out_0_a_valid; // @[Decoupled.scala:51:35] wire [10:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {10'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_2 = _beatsLeft_T_1[9:0]; // @[Arbiter.scala:85:52] wire [9:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_0_ready_T = out_0_a_ready & allowed_0; // @[Xbar.scala:216:19] assign portsAOI_filtered_0_ready = _filtered_0_ready_T; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_1 = out_0_a_ready & allowed_1; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_0_ready = _filtered_0_ready_T_1; // @[Xbar.scala:352:24] wire _out_0_a_valid_T_1 = state_0 & portsAOI_filtered_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_2 = state_1 & portsAOI_filtered_1_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_3 = _out_0_a_valid_T_1 | _out_0_a_valid_T_2; // @[Mux.scala:30:73] wire _out_0_a_valid_WIRE = _out_0_a_valid_T_3; // @[Mux.scala:30:73] assign _out_0_a_valid_T_4 = idle ? _out_0_a_valid_T : _out_0_a_valid_WIRE; // @[Mux.scala:30:73] assign out_0_a_valid = _out_0_a_valid_T_4; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73] assign out_0_a_bits_opcode = _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73] assign out_0_a_bits_param = _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73] assign out_0_a_bits_size = _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73] assign out_0_a_bits_source = _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73] assign out_0_a_bits_address = _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73] assign out_0_a_bits_mask = _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73] assign out_0_a_bits_data = _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73] assign out_0_a_bits_corrupt = _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T = muxState_0 & portsAOI_filtered_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = muxState_1 & portsAOI_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = _out_0_a_bits_T | _out_0_a_bits_T_1; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_1 = _out_0_a_bits_T_2; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_corrupt = _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_3 = muxState_0 ? portsAOI_filtered_0_bits_data : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_4 = muxState_1 ? portsAOI_filtered_1_0_bits_data : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_5 = _out_0_a_bits_T_3 | _out_0_a_bits_T_4; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_2 = _out_0_a_bits_T_5; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_data = _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_6 = muxState_0 ? portsAOI_filtered_0_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_7 = muxState_1 ? portsAOI_filtered_1_0_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_8 = _out_0_a_bits_T_6 | _out_0_a_bits_T_7; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_3 = _out_0_a_bits_T_8; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_mask = _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_9 = muxState_0 ? portsAOI_filtered_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_10 = muxState_1 ? portsAOI_filtered_1_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_11 = _out_0_a_bits_T_9 | _out_0_a_bits_T_10; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_6 = _out_0_a_bits_T_11; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_address = _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_T_12 = muxState_0 ? portsAOI_filtered_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_T_13 = muxState_1 ? portsAOI_filtered_1_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_0_a_bits_T_14 = _out_0_a_bits_T_12 | _out_0_a_bits_T_13; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_7 = _out_0_a_bits_T_14; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_source = _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_15 = muxState_0 ? portsAOI_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_16 = muxState_1 ? portsAOI_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_17 = _out_0_a_bits_T_15 | _out_0_a_bits_T_16; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_8 = _out_0_a_bits_T_17; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_size = _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_18 = muxState_0 ? portsAOI_filtered_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_19 = muxState_1 ? portsAOI_filtered_1_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_20 = _out_0_a_bits_T_18 | _out_0_a_bits_T_19; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_9 = _out_0_a_bits_T_20; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_param = _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_21 = muxState_0 ? portsAOI_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_22 = muxState_1 ? portsAOI_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_23 = _out_0_a_bits_T_21 | _out_0_a_bits_T_22; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_10 = _out_0_a_bits_T_23; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_opcode = _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73] reg [9:0] beatsLeft_1; // @[Arbiter.scala:60:30] wire idle_1 = beatsLeft_1 == 10'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_1 = idle_1 & out_1_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T_10 = {portsAOI_filtered_1_1_valid, portsAOI_filtered_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_1 = _readys_T_10; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_11 = readys_valid_1 == _readys_T_10; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_13 = ~_readys_T_12; // @[Arbiter.scala:22:12] wire _readys_T_14 = ~_readys_T_11; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_1; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_2 = ~readys_mask_1; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_3 = readys_valid_1 & _readys_filter_T_2; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_1 = {_readys_filter_T_3, readys_valid_1}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_5 = readys_filter_1[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_6 = {readys_filter_1[3], readys_filter_1[2:0] | _readys_unready_T_5}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_7 = _readys_unready_T_6; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_8 = _readys_unready_T_7[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_9 = {readys_mask_1, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_1 = {1'h0, _readys_unready_T_8} | _readys_unready_T_9; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_3 = readys_unready_1[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_4 = readys_unready_1[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_5 = _readys_readys_T_3 & _readys_readys_T_4; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_1 = ~_readys_readys_T_5; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_17 = readys_readys_1; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_15 = |readys_valid_1; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_16 = latch_1 & _readys_T_15; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_5 = readys_readys_1 & readys_valid_1; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_6 = {_readys_mask_T_5, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_7 = _readys_mask_T_6[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_8 = _readys_mask_T_5 | _readys_mask_T_7; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_9 = _readys_mask_T_8; // @[package.scala:253:43, :254:17] wire _readys_T_18 = _readys_T_17[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_0 = _readys_T_18; // @[Arbiter.scala:68:{27,76}] wire _readys_T_19 = _readys_T_17[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_1 = _readys_T_19; // @[Arbiter.scala:68:{27,76}] wire _winner_T_2 = readys_1_0 & portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] wire winner_1_0 = _winner_T_2; // @[Arbiter.scala:71:{27,69}] wire _winner_T_3 = readys_1_1 & portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_1_1 = _winner_T_3; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_1 = prefixOR_1_1 | winner_1_1; // @[Arbiter.scala:71:27, :76:48] wire _out_1_a_valid_T = portsAOI_filtered_1_valid | portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire [9:0] maskedBeats_0_1 = winner_1_0 ? beatsAI_0 : 10'h0; // @[Edges.scala:221:14] wire [9:0] maskedBeats_1_1 = winner_1_1 ? beatsAI_1 : 10'h0; // @[Edges.scala:221:14] wire [9:0] initBeats_1 = maskedBeats_0_1 | maskedBeats_1_1; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_4 = out_1_a_ready & out_1_a_valid; // @[Decoupled.scala:51:35] wire [10:0] _beatsLeft_T_5 = {1'h0, beatsLeft_1} - {10'h0, _beatsLeft_T_4}; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_6 = _beatsLeft_T_5[9:0]; // @[Arbiter.scala:85:52] wire [9:0] _beatsLeft_T_7 = latch_1 ? initBeats_1 : _beatsLeft_T_6; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_1_0; // @[Arbiter.scala:88:26] reg state_1_1; // @[Arbiter.scala:88:26] wire muxState_1_0 = idle_1 ? winner_1_0 : state_1_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_1_0 = idle_1 ? readys_1_0 : state_1_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1_1 = idle_1 ? readys_1_1 : state_1_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T = out_1_a_ready & allowed_1_0; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_ready = _filtered_1_ready_T; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_1 = out_1_a_ready & allowed_1_1; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_1_ready = _filtered_1_ready_T_1; // @[Xbar.scala:352:24] wire _out_1_a_valid_T_1 = state_1_0 & portsAOI_filtered_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_2 = state_1_1 & portsAOI_filtered_1_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_3 = _out_1_a_valid_T_1 | _out_1_a_valid_T_2; // @[Mux.scala:30:73] wire _out_1_a_valid_WIRE = _out_1_a_valid_T_3; // @[Mux.scala:30:73] assign _out_1_a_valid_T_4 = idle_1 ? _out_1_a_valid_T : _out_1_a_valid_WIRE; // @[Mux.scala:30:73] assign out_1_a_valid = _out_1_a_valid_T_4; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73] assign out_1_a_bits_opcode = _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73] assign out_1_a_bits_param = _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73] assign out_1_a_bits_size = _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73] assign out_1_a_bits_source = _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73] assign out_1_a_bits_address = _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73] assign out_1_a_bits_mask = _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73] assign out_1_a_bits_data = _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73] assign out_1_a_bits_corrupt = _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T = muxState_1_0 & portsAOI_filtered_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_1 = muxState_1_1 & portsAOI_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_2 = _out_1_a_bits_T | _out_1_a_bits_T_1; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_1 = _out_1_a_bits_T_2; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_corrupt = _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_3 = muxState_1_0 ? portsAOI_filtered_1_bits_data : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_4 = muxState_1_1 ? portsAOI_filtered_1_1_bits_data : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_5 = _out_1_a_bits_T_3 | _out_1_a_bits_T_4; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_2 = _out_1_a_bits_T_5; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_data = _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_6 = muxState_1_0 ? portsAOI_filtered_1_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_7 = muxState_1_1 ? portsAOI_filtered_1_1_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_8 = _out_1_a_bits_T_6 | _out_1_a_bits_T_7; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_3 = _out_1_a_bits_T_8; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_mask = _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_9 = muxState_1_0 ? portsAOI_filtered_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_10 = muxState_1_1 ? portsAOI_filtered_1_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_11 = _out_1_a_bits_T_9 | _out_1_a_bits_T_10; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_6 = _out_1_a_bits_T_11; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_address = _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_T_12 = muxState_1_0 ? portsAOI_filtered_1_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_T_13 = muxState_1_1 ? portsAOI_filtered_1_1_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _out_1_a_bits_T_14 = _out_1_a_bits_T_12 | _out_1_a_bits_T_13; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_7 = _out_1_a_bits_T_14; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_source = _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_15 = muxState_1_0 ? portsAOI_filtered_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_16 = muxState_1_1 ? portsAOI_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_17 = _out_1_a_bits_T_15 | _out_1_a_bits_T_16; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_8 = _out_1_a_bits_T_17; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_size = _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_18 = muxState_1_0 ? portsAOI_filtered_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_19 = muxState_1_1 ? portsAOI_filtered_1_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_20 = _out_1_a_bits_T_18 | _out_1_a_bits_T_19; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_9 = _out_1_a_bits_T_20; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_param = _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_21 = muxState_1_0 ? portsAOI_filtered_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_22 = muxState_1_1 ? portsAOI_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_23 = _out_1_a_bits_T_21 | _out_1_a_bits_T_22; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_10 = _out_1_a_bits_T_23; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_opcode = _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73] reg [9:0] beatsLeft_2; // @[Arbiter.scala:60:30] wire idle_2 = beatsLeft_2 == 10'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_2 = idle_2 & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_20 = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_2 = _readys_T_20; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_21 = readys_valid_2 == _readys_T_20; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_23 = ~_readys_T_22; // @[Arbiter.scala:22:12] wire _readys_T_24 = ~_readys_T_21; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_2; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_4 = ~readys_mask_2; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_5 = readys_valid_2 & _readys_filter_T_4; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_2 = {_readys_filter_T_5, readys_valid_2}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_10 = readys_filter_2[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_11 = {readys_filter_2[3], readys_filter_2[2:0] | _readys_unready_T_10}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_12 = _readys_unready_T_11; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_13 = _readys_unready_T_12[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_14 = {readys_mask_2, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_2 = {1'h0, _readys_unready_T_13} | _readys_unready_T_14; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_6 = readys_unready_2[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_7 = readys_unready_2[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_8 = _readys_readys_T_6 & _readys_readys_T_7; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_2 = ~_readys_readys_T_8; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_27 = readys_readys_2; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_25 = |readys_valid_2; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_26 = latch_2 & _readys_T_25; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_10 = readys_readys_2 & readys_valid_2; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_11 = {_readys_mask_T_10, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_12 = _readys_mask_T_11[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_13 = _readys_mask_T_10 | _readys_mask_T_12; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_14 = _readys_mask_T_13; // @[package.scala:253:43, :254:17] wire _readys_T_28 = _readys_T_27[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_0 = _readys_T_28; // @[Arbiter.scala:68:{27,76}] wire _readys_T_29 = _readys_T_27[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_1 = _readys_T_29; // @[Arbiter.scala:68:{27,76}] wire _winner_T_4 = readys_2_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_2_0 = _winner_T_4; // @[Arbiter.scala:71:{27,69}] wire _winner_T_5 = readys_2_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_2_1 = _winner_T_5; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_2 = winner_2_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_2 = prefixOR_1_2 | winner_2_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire [9:0] maskedBeats_0_2 = winner_2_0 ? beatsDO_0 : 10'h0; // @[Edges.scala:221:14] wire [3:0] maskedBeats_1_2 = winner_2_1 ? beatsDO_1 : 4'h0; // @[Edges.scala:221:14] wire [9:0] initBeats_2 = {maskedBeats_0_2[9:4], maskedBeats_0_2[3:0] | maskedBeats_1_2}; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_8 = in_0_d_ready & in_0_d_valid; // @[Decoupled.scala:51:35] wire [10:0] _beatsLeft_T_9 = {1'h0, beatsLeft_2} - {10'h0, _beatsLeft_T_8}; // @[Decoupled.scala:51:35] wire [9:0] _beatsLeft_T_10 = _beatsLeft_T_9[9:0]; // @[Arbiter.scala:85:52] wire [9:0] _beatsLeft_T_11 = latch_2 ? initBeats_2 : _beatsLeft_T_10; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_2_0; // @[Arbiter.scala:88:26] reg state_2_1; // @[Arbiter.scala:88:26] wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_2_0 = idle_2 ? readys_2_0 : state_2_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2_1 = idle_2 ? readys_2_1 : state_2_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_0_ready_T_2 = in_0_d_ready & allowed_2_0; // @[Xbar.scala:159:18] assign portsDIO_filtered_0_ready = _filtered_0_ready_T_2; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_3 = in_0_d_ready & allowed_2_1; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_0_ready = _filtered_0_ready_T_3; // @[Xbar.scala:352:24] wire _in_0_d_valid_T_1 = state_2_0 & portsDIO_filtered_0_valid; // @[Mux.scala:30:73] wire _in_0_d_valid_T_2 = state_2_1 & portsDIO_filtered_1_0_valid; // @[Mux.scala:30:73] wire _in_0_d_valid_T_3 = _in_0_d_valid_T_1 | _in_0_d_valid_T_2; // @[Mux.scala:30:73] wire _in_0_d_valid_WIRE = _in_0_d_valid_T_3; // @[Mux.scala:30:73] assign _in_0_d_valid_T_4 = idle_2 ? _in_0_d_valid_T : _in_0_d_valid_WIRE; // @[Mux.scala:30:73] assign in_0_d_valid = _in_0_d_valid_T_4; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73] assign in_0_d_bits_opcode = _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73] assign in_0_d_bits_param = _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73] assign in_0_d_bits_size = _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] wire [5:0] _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73] assign in_0_d_bits_source = _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73] assign in_0_d_bits_sink = _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73] assign in_0_d_bits_denied = _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] wire [31:0] _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73] assign in_0_d_bits_data = _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73] assign in_0_d_bits_corrupt = _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T = muxState_2_0 & portsDIO_filtered_0_bits_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T_1 = muxState_2_1 & portsDIO_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = _in_0_d_bits_T | _in_0_d_bits_T_1; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_1 = _in_0_d_bits_T_2; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_corrupt = _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73] wire [31:0] _in_0_d_bits_T_3 = muxState_2_0 ? portsDIO_filtered_0_bits_data : 32'h0; // @[Mux.scala:30:73] wire [31:0] _in_0_d_bits_T_4 = muxState_2_1 ? portsDIO_filtered_1_0_bits_data : 32'h0; // @[Mux.scala:30:73] wire [31:0] _in_0_d_bits_T_5 = _in_0_d_bits_T_3 | _in_0_d_bits_T_4; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_2 = _in_0_d_bits_T_5; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_data = _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = muxState_2_0 & portsDIO_filtered_0_bits_denied; // @[Mux.scala:30:73] wire _in_0_d_bits_T_7 = muxState_2_1 & portsDIO_filtered_1_0_bits_denied; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = _in_0_d_bits_T_6 | _in_0_d_bits_T_7; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_5 = _in_0_d_bits_T_8; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_denied = _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_9 = muxState_2_0 ? portsDIO_filtered_0_bits_sink : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_10 = muxState_2_1 ? portsDIO_filtered_1_0_bits_sink : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_11 = _in_0_d_bits_T_9 | _in_0_d_bits_T_10; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_6 = _in_0_d_bits_T_11; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_sink = _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73] wire [5:0] _in_0_d_bits_T_12 = muxState_2_0 ? portsDIO_filtered_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _in_0_d_bits_T_13 = muxState_2_1 ? portsDIO_filtered_1_0_bits_source : 6'h0; // @[Mux.scala:30:73] wire [5:0] _in_0_d_bits_T_14 = _in_0_d_bits_T_12 | _in_0_d_bits_T_13; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_7 = _in_0_d_bits_T_14; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_source = _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_15 = muxState_2_0 ? portsDIO_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_16 = muxState_2_1 ? portsDIO_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_17 = _in_0_d_bits_T_15 | _in_0_d_bits_T_16; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_8 = _in_0_d_bits_T_17; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_size = _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_18 = muxState_2_0 ? portsDIO_filtered_0_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_19 = muxState_2_1 ? portsDIO_filtered_1_0_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = _in_0_d_bits_T_18 | _in_0_d_bits_T_19; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_9 = _in_0_d_bits_T_20; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_param = _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_21 = muxState_2_0 ? portsDIO_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_22 = muxState_2_1 ? portsDIO_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_23 = _in_0_d_bits_T_21 | _in_0_d_bits_T_22; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_10 = _in_0_d_bits_T_23; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_opcode = _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73] reg [9:0] beatsLeft_3; // @[Arbiter.scala:60:30] wire idle_3 = beatsLeft_3 == 10'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_3 = idle_3 & in_1_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_30 = {portsDIO_filtered_1_1_valid, portsDIO_filtered_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_3 = _readys_T_30; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_31 = readys_valid_3 == _readys_T_30; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_33 = ~_readys_T_32; // @[Arbiter.scala:22:12] wire _readys_T_34 = ~_readys_T_31; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_3; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_6 = ~readys_mask_3; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_7 = readys_valid_3 & _readys_filter_T_6; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_3 = {_readys_filter_T_7, readys_valid_3}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_15 = readys_filter_3[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_16 = {readys_filter_3[3], readys_filter_3[2:0] | _readys_unready_T_15}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_17 = _readys_unready_T_16; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_18 = _readys_unready_T_17[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_19 = {readys_mask_3, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_3 = {1'h0, _readys_unready_T_18} | _readys_unready_T_19; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_9 = readys_unready_3[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_10 = readys_unready_3[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_11 = _readys_readys_T_9 & _readys_readys_T_10; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_3 = ~_readys_readys_T_11; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_37 = readys_readys_3; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_35 = |readys_valid_3; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_36 = latch_3 & _readys_T_35; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_15 = readys_readys_3 & readys_valid_3; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_16 = {_readys_mask_T_15, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_17 = _readys_mask_T_16[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_18 = _readys_mask_T_15 | _readys_mask_T_17; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_19 = _readys_mask_T_18; // @[package.scala:253:43, :254:17] wire _readys_T_38 = _readys_T_37[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_0 = _readys_T_38; // @[Arbiter.scala:68:{27,76}] wire _readys_T_39 = _readys_T_37[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_1 = _readys_T_39; // @[Arbiter.scala:68:{27,76}] wire _winner_T_6 = readys_3_0 & portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] wire winner_3_0 = _winner_T_6; // @[Arbiter.scala:71:{27,69}] wire _winner_T_7 = readys_3_1 & portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_3_1 = _winner_T_7; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_3 = winner_3_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_3 = prefixOR_1_3 | winner_3_1; // @[Arbiter.scala:71:27, :76:48] wire _in_1_d_valid_T = portsDIO_filtered_1_valid | portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24]

Generate the Verilog code corresponding to this FIRRTL code module TLCToNoC_11 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<129>, egress_id : UInt}}} inst q of Queue1_TLBundleC_a32d128s7k6z4c_11 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 4) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T) node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_4) node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_5) node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8) node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_10) node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_11) node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<7>(0h40)) node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16) node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<8>(0h80)) node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18) node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20) node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_22) node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_23) node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<8>(0hc0)) node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26) node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28) node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0he), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<5>(0h10), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h12), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h14), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h16), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h24)) connect q.io.enq.bits.source, _q_io_enq_bits_source_T

module TLCToNoC_11( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [7:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0; // @[package.scala:243:{46,71,76}] reg [7:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 8'h1 | tail_beats1 == 8'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 8'h0; // @[Edges.scala:229:27] tail_counter <= 8'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0) : head_counter - 8'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLXbar_prcibus_i1_o2_a21d64s8k1z3u : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_62 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 7, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<21>(0h0) connect _WIRE_30.bits.source, UInt<8>(0h0) connect _WIRE_30.bits.size, UInt<3>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<21>(0h0) connect _WIRE_32.bits.source, UInt<8>(0h0) connect _WIRE_32.bits.size, UInt<3>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<21>(0h0) connect _WIRE_34.bits.source, UInt<8>(0h0) connect _WIRE_34.bits.size, UInt<3>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<21>(0h0) connect _WIRE_36.bits.source, UInt<8>(0h0) connect _WIRE_36.bits.size, UInt<3>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.ready, UInt<1>(0h1) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<21>(0h0) connect _WIRE_38.bits.source, UInt<8>(0h0) connect _WIRE_38.bits.size, UInt<3>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.ready, UInt<1>(0h1) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<21>(0h0) connect _WIRE_48.bits.source, UInt<8>(0h0) connect _WIRE_48.bits.size, UInt<3>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<21>(0h0) connect _WIRE_50.bits.source, UInt<8>(0h0) connect _WIRE_50.bits.size, UInt<3>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<21>(0h0) connect _WIRE_52.bits.source, UInt<8>(0h0) connect _WIRE_52.bits.size, UInt<3>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<21>(0h0) connect _WIRE_54.bits.source, UInt<8>(0h0) connect _WIRE_54.bits.size, UInt<3>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<21>(0h0) connect _WIRE_56.bits.source, UInt<8>(0h0) connect _WIRE_56.bits.size, UInt<3>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<21>(0h0) connect _WIRE_58.bits.source, UInt<8>(0h0) connect _WIRE_58.bits.size, UInt<3>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<21>(0h0) connect _WIRE_60.bits.source, UInt<8>(0h0) connect _WIRE_60.bits.size, UInt<3>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<21>(0h0) connect _WIRE_62.bits.source, UInt<8>(0h0) connect _WIRE_62.bits.size, UInt<3>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<21>(0h0) connect _addressC_WIRE.bits.source, UInt<8>(0h0) connect _addressC_WIRE.bits.size, UInt<3>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<18>(0h10000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<18>(0h10000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<21>(0h0) connect _requestBOI_WIRE.bits.source, UInt<8>(0h0) connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<8>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 7, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 8) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<8>(0hff)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<21>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<8>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 7, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 8) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<8>(0hff)) node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<8>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 7, 0) node _requestDOI_T = shr(out[0].d.bits.source, 8) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<8>(0hff)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<8>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 7, 0) node _requestDOI_T_5 = shr(out[1].d.bits.source, 8) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<8>(0hff)) node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<21>(0h0) connect _beatsBO_WIRE.bits.source, UInt<8>(0h0) connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<21>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<21>(0h0) connect _beatsCI_WIRE.bits.source, UInt<8>(0h0) connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<21>(0h0) connect _portsBIO_WIRE.bits.source, UInt<8>(0h0) connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.address, UInt<21>(0h0) connect _portsBIO_WIRE_2.bits.source, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<21>(0h0) connect _portsCOI_WIRE.bits.source, UInt<8>(0h0) connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_2 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect out[0].d.ready, portsDIO_filtered[0].ready wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect out[1].d.ready, portsDIO_filtered_1[0].ready wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_2 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 connect out[0].a, portsAOI_filtered[0] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.address, UInt<21>(0h0) connect _WIRE_72.bits.source, UInt<8>(0h0) connect _WIRE_72.bits.size, UInt<3>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_74.bits.sink, UInt<1>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect out[1].a, portsAOI_filtered[1] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.address, UInt<21>(0h0) connect _WIRE_76.bits.source, UInt<8>(0h0) connect _WIRE_76.bits.size, UInt<3>(0h0) connect _WIRE_76.bits.param, UInt<3>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_78.bits.sink, UInt<1>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<64>(0h0) connect _WIRE_80.bits.mask, UInt<8>(0h0) connect _WIRE_80.bits.address, UInt<21>(0h0) connect _WIRE_80.bits.source, UInt<8>(0h0) connect _WIRE_80.bits.size, UInt<3>(0h0) connect _WIRE_80.bits.param, UInt<2>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.mask invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, in[0].d.ready) node _readys_T = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsDIO_filtered[0].valid) node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<64> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<1> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<8> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<3> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)

module TLXbar_prcibus_i1_o2_a21d64s8k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire [7:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [63:0] auto_anon_out_1_d_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] out_1_d_bits_data = 64'h0; // @[Xbar.scala:216:19] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _in_0_d_bits_T_4 = 64'h0; // @[Mux.scala:30:73] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] x1_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] in_0_d_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_WIRE_param = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_19 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_in_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_d_bits_sink = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_denied = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _out_1_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_WIRE_sink = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_denied = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_7 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_10 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_11 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_6 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [20:0] _addressC_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _addressC_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _requestCIO_T = 21'h0; // @[Parameters.scala:137:31] wire [20:0] _requestCIO_T_5 = 21'h0; // @[Parameters.scala:137:31] wire [20:0] _requestBOI_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _requestBOI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _requestBOI_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _requestBOI_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsBO_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _beatsBO_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsBO_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _beatsBO_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsCI_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _beatsCI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _portsBIO_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _portsBIO_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] portsBIO_filtered_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] _portsBIO_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _portsBIO_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] portsBIO_filtered_1_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] _portsCOI_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _portsCOI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] portsCOI_filtered_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] portsCOI_filtered_1_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [7:0] _addressC_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _addressC_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _requestBOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_uncommonBits_T = 8'h0; // @[Parameters.scala:52:29] wire [7:0] requestBOI_uncommonBits = 8'h0; // @[Parameters.scala:52:56] wire [7:0] _requestBOI_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_uncommonBits_T_1 = 8'h0; // @[Parameters.scala:52:29] wire [7:0] requestBOI_uncommonBits_1 = 8'h0; // @[Parameters.scala:52:56] wire [7:0] _beatsBO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsCI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _beatsCI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _portsBIO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_source = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsCOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _portsCOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] portsCOI_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24] wire [7:0] portsCOI_filtered_1_bits_source = 8'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [21:0] _requestCIO_T_1 = 22'h0; // @[Parameters.scala:137:41] wire [21:0] _requestCIO_T_2 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_3 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_6 = 22'h0; // @[Parameters.scala:137:41] wire [21:0] _requestCIO_T_7 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_8 = 22'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [7:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [7:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [7:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [20:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [7:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [7:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [7:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [20:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [20:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [20:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [7:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [7:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [7:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [7:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [7:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [21:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [21:0] _requestAIO_T_2 = _requestAIO_T_1 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 22'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [20:0] _requestAIO_T_5 = {in_0_a_bits_address[20:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [21:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [21:0] _requestAIO_T_7 = _requestAIO_T_6 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 22'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [7:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [7:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_1 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T

module MulAddRecFNToRaw_preMul_e8_s24_1( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [8:0] rawC_exp = 9'h0; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _sNatCAlignDist_T = {sExpAlignedProd[10], sExpAlignedProd}; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _sNatCAlignDist_T - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_14 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 55, 55) wire common_expOut : UInt<12> wire common_fractOut : UInt<52> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 11, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 11, 11) node roundMask_lsbs = bits(_roundMask_T_1, 10, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 10, 10) node roundMask_lsbs_1 = bits(roundMask_lsbs, 9, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 9, 9) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 8, 0) node roundMask_msb_3 = bits(roundMask_lsbs_2, 8, 8) node roundMask_lsbs_3 = bits(roundMask_lsbs_2, 7, 0) node roundMask_msb_4 = bits(roundMask_lsbs_3, 7, 7) node roundMask_lsbs_4 = bits(roundMask_lsbs_3, 6, 0) node roundMask_msb_5 = bits(roundMask_lsbs_4, 6, 6) node roundMask_lsbs_5 = bits(roundMask_lsbs_4, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_5) node _roundMask_T_2 = bits(roundMask_shift, 63, 13) node _roundMask_T_3 = bits(_roundMask_T_2, 31, 0) node _roundMask_T_4 = shl(UInt<16>(0hffff), 16) node _roundMask_T_5 = xor(UInt<32>(0hffffffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 16) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 15, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 16) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 23, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 8) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 8) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 23, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 8) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 27, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 4) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 4) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 27, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 4) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 29, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 2) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 2) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 29, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 2) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_35, 30, 0) node _roundMask_T_44 = shl(_roundMask_T_43, 1) node _roundMask_T_45 = xor(_roundMask_T_35, _roundMask_T_44) node _roundMask_T_46 = shr(_roundMask_T_42, 1) node _roundMask_T_47 = and(_roundMask_T_46, _roundMask_T_45) node _roundMask_T_48 = bits(_roundMask_T_42, 30, 0) node _roundMask_T_49 = shl(_roundMask_T_48, 1) node _roundMask_T_50 = not(_roundMask_T_45) node _roundMask_T_51 = and(_roundMask_T_49, _roundMask_T_50) node _roundMask_T_52 = or(_roundMask_T_47, _roundMask_T_51) node _roundMask_T_53 = bits(_roundMask_T_2, 50, 32) node _roundMask_T_54 = bits(_roundMask_T_53, 15, 0) node _roundMask_T_55 = shl(UInt<8>(0hff), 8) node _roundMask_T_56 = xor(UInt<16>(0hffff), _roundMask_T_55) node _roundMask_T_57 = shr(_roundMask_T_54, 8) node _roundMask_T_58 = and(_roundMask_T_57, _roundMask_T_56) node _roundMask_T_59 = bits(_roundMask_T_54, 7, 0) node _roundMask_T_60 = shl(_roundMask_T_59, 8) node _roundMask_T_61 = not(_roundMask_T_56) node _roundMask_T_62 = and(_roundMask_T_60, _roundMask_T_61) node _roundMask_T_63 = or(_roundMask_T_58, _roundMask_T_62) node _roundMask_T_64 = bits(_roundMask_T_56, 11, 0) node _roundMask_T_65 = shl(_roundMask_T_64, 4) node _roundMask_T_66 = xor(_roundMask_T_56, _roundMask_T_65) node _roundMask_T_67 = shr(_roundMask_T_63, 4) node _roundMask_T_68 = and(_roundMask_T_67, _roundMask_T_66) node _roundMask_T_69 = bits(_roundMask_T_63, 11, 0) node _roundMask_T_70 = shl(_roundMask_T_69, 4) node _roundMask_T_71 = not(_roundMask_T_66) node _roundMask_T_72 = and(_roundMask_T_70, _roundMask_T_71) node _roundMask_T_73 = or(_roundMask_T_68, _roundMask_T_72) node _roundMask_T_74 = bits(_roundMask_T_66, 13, 0) node _roundMask_T_75 = shl(_roundMask_T_74, 2) node _roundMask_T_76 = xor(_roundMask_T_66, _roundMask_T_75) node _roundMask_T_77 = shr(_roundMask_T_73, 2) node _roundMask_T_78 = and(_roundMask_T_77, _roundMask_T_76) node _roundMask_T_79 = bits(_roundMask_T_73, 13, 0) node _roundMask_T_80 = shl(_roundMask_T_79, 2) node _roundMask_T_81 = not(_roundMask_T_76) node _roundMask_T_82 = and(_roundMask_T_80, _roundMask_T_81) node _roundMask_T_83 = or(_roundMask_T_78, _roundMask_T_82) node _roundMask_T_84 = bits(_roundMask_T_76, 14, 0) node _roundMask_T_85 = shl(_roundMask_T_84, 1) node _roundMask_T_86 = xor(_roundMask_T_76, _roundMask_T_85) node _roundMask_T_87 = shr(_roundMask_T_83, 1) node _roundMask_T_88 = and(_roundMask_T_87, _roundMask_T_86) node _roundMask_T_89 = bits(_roundMask_T_83, 14, 0) node _roundMask_T_90 = shl(_roundMask_T_89, 1) node _roundMask_T_91 = not(_roundMask_T_86) node _roundMask_T_92 = and(_roundMask_T_90, _roundMask_T_91) node _roundMask_T_93 = or(_roundMask_T_88, _roundMask_T_92) node _roundMask_T_94 = bits(_roundMask_T_53, 18, 16) node _roundMask_T_95 = bits(_roundMask_T_94, 1, 0) node _roundMask_T_96 = bits(_roundMask_T_95, 0, 0) node _roundMask_T_97 = bits(_roundMask_T_95, 1, 1) node _roundMask_T_98 = cat(_roundMask_T_96, _roundMask_T_97) node _roundMask_T_99 = bits(_roundMask_T_94, 2, 2) node _roundMask_T_100 = cat(_roundMask_T_98, _roundMask_T_99) node _roundMask_T_101 = cat(_roundMask_T_93, _roundMask_T_100) node _roundMask_T_102 = cat(_roundMask_T_52, _roundMask_T_101) node _roundMask_T_103 = not(_roundMask_T_102) node _roundMask_T_104 = mux(roundMask_msb_5, UInt<1>(0h0), _roundMask_T_103) node _roundMask_T_105 = not(_roundMask_T_104) node _roundMask_T_106 = not(_roundMask_T_105) node _roundMask_T_107 = mux(roundMask_msb_4, UInt<1>(0h0), _roundMask_T_106) node _roundMask_T_108 = not(_roundMask_T_107) node _roundMask_T_109 = not(_roundMask_T_108) node _roundMask_T_110 = mux(roundMask_msb_3, UInt<1>(0h0), _roundMask_T_109) node _roundMask_T_111 = not(_roundMask_T_110) node _roundMask_T_112 = not(_roundMask_T_111) node _roundMask_T_113 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_112) node _roundMask_T_114 = not(_roundMask_T_113) node _roundMask_T_115 = cat(_roundMask_T_114, UInt<3>(0h7)) node roundMask_msb_6 = bits(roundMask_lsbs_1, 9, 9) node roundMask_lsbs_6 = bits(roundMask_lsbs_1, 8, 0) node roundMask_msb_7 = bits(roundMask_lsbs_6, 8, 8) node roundMask_lsbs_7 = bits(roundMask_lsbs_6, 7, 0) node roundMask_msb_8 = bits(roundMask_lsbs_7, 7, 7) node roundMask_lsbs_8 = bits(roundMask_lsbs_7, 6, 0) node roundMask_msb_9 = bits(roundMask_lsbs_8, 6, 6) node roundMask_lsbs_9 = bits(roundMask_lsbs_8, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_9) node _roundMask_T_116 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_117 = bits(_roundMask_T_116, 1, 0) node _roundMask_T_118 = bits(_roundMask_T_117, 0, 0) node _roundMask_T_119 = bits(_roundMask_T_117, 1, 1) node _roundMask_T_120 = cat(_roundMask_T_118, _roundMask_T_119) node _roundMask_T_121 = bits(_roundMask_T_116, 2, 2) node _roundMask_T_122 = cat(_roundMask_T_120, _roundMask_T_121) node _roundMask_T_123 = mux(roundMask_msb_9, _roundMask_T_122, UInt<1>(0h0)) node _roundMask_T_124 = mux(roundMask_msb_8, _roundMask_T_123, UInt<1>(0h0)) node _roundMask_T_125 = mux(roundMask_msb_7, _roundMask_T_124, UInt<1>(0h0)) node _roundMask_T_126 = mux(roundMask_msb_6, _roundMask_T_125, UInt<1>(0h0)) node _roundMask_T_127 = mux(roundMask_msb_1, _roundMask_T_115, _roundMask_T_126) node _roundMask_T_128 = mux(roundMask_msb, _roundMask_T_127, UInt<1>(0h0)) node _roundMask_T_129 = or(_roundMask_T_128, doShiftSigDown1) node roundMask = cat(_roundMask_T_129, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<55>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 53) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 11, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 52, 1) node _common_fractOut_T_1 = bits(roundedSig, 51, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 10) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<11>(0h3ce))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 54, 54) node _roundCarry_T_1 = bits(roundedSig, 53, 53) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 11) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<12>(0he00), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<12>(0h3ce)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<12>(0h400), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<12>(0h200), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<12>(0h3ce), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<12>(0hbff), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<12>(0hc00), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<12>(0he00), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<52>(0h8000000000000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<52>(0hfffffffffffff), UInt<52>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_14( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:58:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [31:0] _roundMask_T_5 = 32'hFFFF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_4 = 32'hFFFF0000; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_10 = 32'hFFFF0000; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_13 = 24'hFFFF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_14 = 32'hFFFF00; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_15 = 32'hFF00FF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_20 = 32'hFF00FF00; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_23 = 28'hFF00FF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_24 = 32'hFF00FF0; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_25 = 32'hF0F0F0F; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_30 = 32'hF0F0F0F0; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_33 = 30'hF0F0F0F; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_34 = 32'h3C3C3C3C; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_35 = 32'h33333333; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_40 = 32'hCCCCCCCC; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_43 = 31'h33333333; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_44 = 32'h66666666; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_45 = 32'h55555555; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_50 = 32'hAAAAAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_56 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_55 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_61 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_64 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_65 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_66 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_71 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_74 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_75 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_76 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_81 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_84 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_85 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_86 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_91 = 16'hAAAA; // @[primitives.scala:77:20] wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [55:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire _common_underflow_T_7 = io_detectTininess_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :222:49] wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[55]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [11:0] _roundMask_T = io_in_sExp_0[11:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [11:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[11]; // @[primitives.scala:52:21, :58:25] wire [10:0] roundMask_lsbs = _roundMask_T_1[10:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[10]; // @[primitives.scala:58:25, :59:26] wire [9:0] roundMask_lsbs_1 = roundMask_lsbs[9:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_6 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26] wire [8:0] roundMask_lsbs_2 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26] wire [8:0] roundMask_lsbs_6 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26] wire roundMask_msb_3 = roundMask_lsbs_2[8]; // @[primitives.scala:58:25, :59:26] wire [7:0] roundMask_lsbs_3 = roundMask_lsbs_2[7:0]; // @[primitives.scala:59:26] wire roundMask_msb_4 = roundMask_lsbs_3[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_4 = roundMask_lsbs_3[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_5 = roundMask_lsbs_4[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_5 = roundMask_lsbs_4[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_5); // @[primitives.scala:59:26, :76:56] wire [50:0] _roundMask_T_2 = roundMask_shift[63:13]; // @[primitives.scala:76:56, :78:22] wire [31:0] _roundMask_T_3 = _roundMask_T_2[31:0]; // @[primitives.scala:77:20, :78:22] wire [15:0] _roundMask_T_6 = _roundMask_T_3[31:16]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_7 = {16'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_8 = _roundMask_T_3[15:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_9 = {_roundMask_T_8, 16'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_11 = _roundMask_T_9 & 32'hFFFF0000; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_16 = _roundMask_T_12[31:8]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_17 = {8'h0, _roundMask_T_16 & 24'hFF00FF}; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_18 = _roundMask_T_12[23:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_19 = {_roundMask_T_18, 8'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_21 = _roundMask_T_19 & 32'hFF00FF00; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_26 = _roundMask_T_22[31:4]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_27 = {4'h0, _roundMask_T_26 & 28'hF0F0F0F}; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_28 = _roundMask_T_22[27:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_29 = {_roundMask_T_28, 4'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_31 = _roundMask_T_29 & 32'hF0F0F0F0; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_36 = _roundMask_T_32[31:2]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_37 = {2'h0, _roundMask_T_36 & 30'h33333333}; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_38 = _roundMask_T_32[29:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_39 = {_roundMask_T_38, 2'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_41 = _roundMask_T_39 & 32'hCCCCCCCC; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_46 = _roundMask_T_42[31:1]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_47 = {1'h0, _roundMask_T_46 & 31'h55555555}; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_48 = _roundMask_T_42[30:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_49 = {_roundMask_T_48, 1'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_51 = _roundMask_T_49 & 32'hAAAAAAAA; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_52 = _roundMask_T_47 | _roundMask_T_51; // @[primitives.scala:77:20] wire [18:0] _roundMask_T_53 = _roundMask_T_2[50:32]; // @[primitives.scala:77:20, :78:22] wire [15:0] _roundMask_T_54 = _roundMask_T_53[15:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_57 = _roundMask_T_54[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_58 = {8'h0, _roundMask_T_57}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_59 = _roundMask_T_54[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_60 = {_roundMask_T_59, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_62 = _roundMask_T_60 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_63 = _roundMask_T_58 | _roundMask_T_62; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_67 = _roundMask_T_63[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_68 = {4'h0, _roundMask_T_67 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_69 = _roundMask_T_63[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_70 = {_roundMask_T_69, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_72 = _roundMask_T_70 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_73 = _roundMask_T_68 | _roundMask_T_72; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_77 = _roundMask_T_73[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_78 = {2'h0, _roundMask_T_77 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_79 = _roundMask_T_73[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_80 = {_roundMask_T_79, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_82 = _roundMask_T_80 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_83 = _roundMask_T_78 | _roundMask_T_82; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_87 = _roundMask_T_83[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_88 = {1'h0, _roundMask_T_87 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_89 = _roundMask_T_83[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_90 = {_roundMask_T_89, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_92 = _roundMask_T_90 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_93 = _roundMask_T_88 | _roundMask_T_92; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_94 = _roundMask_T_53[18:16]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_95 = _roundMask_T_94[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_96 = _roundMask_T_95[0]; // @[primitives.scala:77:20] wire _roundMask_T_97 = _roundMask_T_95[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_98 = {_roundMask_T_96, _roundMask_T_97}; // @[primitives.scala:77:20] wire _roundMask_T_99 = _roundMask_T_94[2]; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_100 = {_roundMask_T_98, _roundMask_T_99}; // @[primitives.scala:77:20] wire [18:0] _roundMask_T_101 = {_roundMask_T_93, _roundMask_T_100}; // @[primitives.scala:77:20] wire [50:0] _roundMask_T_102 = {_roundMask_T_52, _roundMask_T_101}; // @[primitives.scala:77:20] wire [50:0] _roundMask_T_103 = ~_roundMask_T_102; // @[primitives.scala:73:32, :77:20] wire [50:0] _roundMask_T_104 = roundMask_msb_5 ? 51'h0 : _roundMask_T_103; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_105 = ~_roundMask_T_104; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_106 = ~_roundMask_T_105; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_107 = roundMask_msb_4 ? 51'h0 : _roundMask_T_106; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_108 = ~_roundMask_T_107; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_109 = ~_roundMask_T_108; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_110 = roundMask_msb_3 ? 51'h0 : _roundMask_T_109; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_111 = ~_roundMask_T_110; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_112 = ~_roundMask_T_111; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_113 = roundMask_msb_2 ? 51'h0 : _roundMask_T_112; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_114 = ~_roundMask_T_113; // @[primitives.scala:73:{17,21}] wire [53:0] _roundMask_T_115 = {_roundMask_T_114, 3'h7}; // @[primitives.scala:68:58, :73:17] wire roundMask_msb_7 = roundMask_lsbs_6[8]; // @[primitives.scala:58:25, :59:26] wire [7:0] roundMask_lsbs_7 = roundMask_lsbs_6[7:0]; // @[primitives.scala:59:26] wire roundMask_msb_8 = roundMask_lsbs_7[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_8 = roundMask_lsbs_7[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_9 = roundMask_lsbs_8[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_9 = roundMask_lsbs_8[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_9); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_116 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_117 = _roundMask_T_116[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_118 = _roundMask_T_117[0]; // @[primitives.scala:77:20] wire _roundMask_T_119 = _roundMask_T_117[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_120 = {_roundMask_T_118, _roundMask_T_119}; // @[primitives.scala:77:20] wire _roundMask_T_121 = _roundMask_T_116[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_122 = {_roundMask_T_120, _roundMask_T_121}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_123 = roundMask_msb_9 ? _roundMask_T_122 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [2:0] _roundMask_T_124 = roundMask_msb_8 ? _roundMask_T_123 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [2:0] _roundMask_T_125 = roundMask_msb_7 ? _roundMask_T_124 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [2:0] _roundMask_T_126 = roundMask_msb_6 ? _roundMask_T_125 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [53:0] _roundMask_T_127 = roundMask_msb_1 ? _roundMask_T_115 : {51'h0, _roundMask_T_126}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [53:0] _roundMask_T_128 = roundMask_msb ? _roundMask_T_127 : 54'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [53:0] _roundMask_T_129 = {_roundMask_T_128[53:1], _roundMask_T_128[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [55:0] roundMask = {_roundMask_T_129, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [56:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [55:0] shiftedRoundMask = _shiftedRoundMask_T[56:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [55:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [55:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [55:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [55:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [55:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [54:0] _roundedSig_T_6 = roundMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [54:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [55:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [55:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [54:0] _roundedSig_T_14 = roundPosMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [54:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [13:0] sRoundedExp = {io_in_sExp_0[12], io_in_sExp_0} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[13:10]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 14'sh3CE; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[12:11]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_7 & _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:{49,77}, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [11:0] _expOut_T_5 = pegMinNonzeroMagOut ? 12'hC31 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [11:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [11:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [11:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 10'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [11:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [11:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [11:0] _expOut_T_14 = pegMinNonzeroMagOut ? 12'h3CE : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [11:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [11:0] _expOut_T_16 = pegMaxFiniteMagOut ? 12'hBFF : 12'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [11:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [11:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [11:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [51:0] _fractOut_T_4 = {52{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [51:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Router_15 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}}, flip ingress_nodes_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_15 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire debugNodeOut : { va_stall : UInt[2], sa_stall : UInt[2]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in connect auto.egress_nodes_out, egressNodesOut connect auto.debug_out, debugNodeOut inst input_unit_0_from_1 of InputUnit_15 connect input_unit_0_from_1.clock, clock connect input_unit_0_from_1.reset, reset inst ingress_unit_1_from_3 of IngressUnit_25 connect ingress_unit_1_from_3.clock, clock connect ingress_unit_1_from_3.reset, reset inst output_unit_0_to_3 of OutputUnit_15 connect output_unit_0_to_3.clock, clock connect output_unit_0_to_3.reset, reset inst egress_unit_1_to_3 of EgressUnit_21 connect egress_unit_1_to_3.clock, clock connect egress_unit_1_to_3.reset, reset inst switch of Switch_15 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_15 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_15 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_15 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_3 = bits(_fires_count_T_2, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_3 connect input_unit_0_from_1.io.in, destNodesIn connect ingress_unit_1_from_3.io.in, ingressNodesIn.flit connect output_unit_0_to_3.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_3.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_3.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_3.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_3.io.out.valid connect egress_unit_1_to_3.io.out.ready, egressNodesOut.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_1.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_3.io.router_req connect input_unit_0_from_1.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_3.io.router_resp, route_computer.io.resp.`1` connect vc_allocator.io.req.`0`, input_unit_0_from_1.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_3.io.vcalloc_req connect input_unit_0_from_1.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_3.io.vcalloc_resp, vc_allocator.io.resp.`1` connect output_unit_0_to_3.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_3.io.allocs, vc_allocator.io.out_allocs.`1` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_3.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_3.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_3.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_3.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_3.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_3.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_3.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_3.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_3.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_3.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_3.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_3.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_3.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_3.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_3.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_3.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_3.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_3.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_3.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_3.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_3.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_3.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_3.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_3.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_3.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_3.io.channel_status[0].occupied connect input_unit_0_from_1.io.out_credit_available.`0`[0], output_unit_0_to_3.io.credit_available[0] connect input_unit_0_from_1.io.out_credit_available.`0`[1], output_unit_0_to_3.io.credit_available[1] connect input_unit_0_from_1.io.out_credit_available.`0`[2], output_unit_0_to_3.io.credit_available[2] connect input_unit_0_from_1.io.out_credit_available.`0`[3], output_unit_0_to_3.io.credit_available[3] connect input_unit_0_from_1.io.out_credit_available.`1`[0], egress_unit_1_to_3.io.credit_available[0] connect ingress_unit_1_from_3.io.out_credit_available.`0`[0], output_unit_0_to_3.io.credit_available[0] connect ingress_unit_1_from_3.io.out_credit_available.`0`[1], output_unit_0_to_3.io.credit_available[1] connect ingress_unit_1_from_3.io.out_credit_available.`0`[2], output_unit_0_to_3.io.credit_available[2] connect ingress_unit_1_from_3.io.out_credit_available.`0`[3], output_unit_0_to_3.io.credit_available[3] connect ingress_unit_1_from_3.io.out_credit_available.`1`[0], egress_unit_1_to_3.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_1.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_3.io.salloc_req[0] connect output_unit_0_to_3.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_3.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_3.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_3.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_3.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_3.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_3.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_3.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect egress_unit_1_to_3.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_3.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_1.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_3.io.out[0] connect output_unit_0_to_3.io.in, switch.io.out.`0` connect egress_unit_1_to_3.io.in, switch.io.out.`1` reg REG : { `1` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect input_unit_0_from_1.io.block, UInt<1>(0h0) connect ingress_unit_1_from_3.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_1.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_3.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_1.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_3.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_33 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 1 2 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i3 2 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d 2 e3 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20

module Router_15( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_1_to_3_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_3_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_3_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_3_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_3_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _ingress_unit_1_from_3_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_1_from_3_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_3_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_3_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_3_io_in_ready; // @[Router.scala:116:13] wire [1:0] _input_unit_0_from_1_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_1_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_1_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_1_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_1_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_1_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_1_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_3_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_193 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_345 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_193( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_345 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_58 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<17>(0h10000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = and(_T_207, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = and(_T_206, _T_214) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_215, UInt<1>(0h1), "") : assert_26 node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(is_aligned, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_225 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(io.in.a.bits.mask, mask) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_229, UInt<1>(0h1), "") : assert_30 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_237 = shr(io.in.a.bits.source, 12) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_5) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = and(_T_245, _T_250) node _T_252 = or(UInt<1>(0h0), _T_251) node _T_253 = and(_T_244, _T_252) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_253, UInt<1>(0h1), "") : assert_31 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(is_aligned, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_263 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_263, UInt<1>(0h1), "") : assert_34 node _T_267 = not(mask) node _T_268 = and(io.in.a.bits.mask, _T_267) node _T_269 = eq(_T_268, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_269, UInt<1>(0h1), "") : assert_35 node _T_273 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_277 = shr(io.in.a.bits.source, 12) node _T_278 = eq(_T_277, UInt<1>(0h0)) node _T_279 = leq(UInt<1>(0h0), uncommonBits_6) node _T_280 = and(_T_278, _T_279) node _T_281 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_282 = and(_T_280, _T_281) node _T_283 = and(_T_276, _T_282) node _T_284 = or(UInt<1>(0h0), _T_283) node _T_285 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = and(_T_285, _T_290) node _T_292 = or(UInt<1>(0h0), _T_291) node _T_293 = and(_T_284, _T_292) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_293, UInt<1>(0h1), "") : assert_36 node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(is_aligned, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_303 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(_T_303, UInt<1>(0h0)) when _T_306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_303, UInt<1>(0h1), "") : assert_39 node _T_307 = eq(io.in.a.bits.mask, mask) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_307, UInt<1>(0h1), "") : assert_40 node _T_311 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_311 : node _T_312 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_313 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_315 = shr(io.in.a.bits.source, 12) node _T_316 = eq(_T_315, UInt<1>(0h0)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_7) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_320 = and(_T_318, _T_319) node _T_321 = and(_T_314, _T_320) node _T_322 = or(UInt<1>(0h0), _T_321) node _T_323 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = and(_T_323, _T_328) node _T_330 = or(UInt<1>(0h0), _T_329) node _T_331 = and(_T_322, _T_330) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_331, UInt<1>(0h1), "") : assert_41 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(is_aligned, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_341 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(_T_341, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_341, UInt<1>(0h1), "") : assert_44 node _T_345 = eq(io.in.a.bits.mask, mask) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_345, UInt<1>(0h1), "") : assert_45 node _T_349 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_349 : node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_352 = and(_T_350, _T_351) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_353 = shr(io.in.a.bits.source, 12) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = leq(UInt<1>(0h0), uncommonBits_8) node _T_356 = and(_T_354, _T_355) node _T_357 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_358 = and(_T_356, _T_357) node _T_359 = and(_T_352, _T_358) node _T_360 = or(UInt<1>(0h0), _T_359) node _T_361 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = and(_T_361, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = and(_T_360, _T_368) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_369, UInt<1>(0h1), "") : assert_46 node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(is_aligned, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_379 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_379, UInt<1>(0h1), "") : assert_49 node _T_383 = eq(io.in.a.bits.mask, mask) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_383, UInt<1>(0h1), "") : assert_50 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_387, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_391 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_391, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_395 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_395 : node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_399 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_399, UInt<1>(0h1), "") : assert_54 node _T_403 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_403, UInt<1>(0h1), "") : assert_55 node _T_407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_407, UInt<1>(0h1), "") : assert_56 node _T_411 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_411, UInt<1>(0h1), "") : assert_57 node _T_415 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_415 : node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(sink_ok, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_422 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_422, UInt<1>(0h1), "") : assert_60 node _T_426 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_426, UInt<1>(0h1), "") : assert_61 node _T_430 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_431 = asUInt(reset) node _T_432 = eq(_T_431, UInt<1>(0h0)) when _T_432 : node _T_433 = eq(_T_430, UInt<1>(0h0)) when _T_433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_430, UInt<1>(0h1), "") : assert_62 node _T_434 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_434, UInt<1>(0h1), "") : assert_63 node _T_438 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_439, UInt<1>(0h1), "") : assert_64 node _T_443 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_443 : node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(sink_ok, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_450 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_450, UInt<1>(0h1), "") : assert_67 node _T_454 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_454, UInt<1>(0h1), "") : assert_68 node _T_458 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(_T_458, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_458, UInt<1>(0h1), "") : assert_69 node _T_462 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_463 = or(_T_462, io.in.d.bits.corrupt) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_463, UInt<1>(0h1), "") : assert_70 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_468, UInt<1>(0h1), "") : assert_71 node _T_472 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_472 : node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_476 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_476, UInt<1>(0h1), "") : assert_73 node _T_480 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_480, UInt<1>(0h1), "") : assert_74 node _T_484 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_485, UInt<1>(0h1), "") : assert_75 node _T_489 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_493 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_493, UInt<1>(0h1), "") : assert_77 node _T_497 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_498 = or(_T_497, io.in.d.bits.corrupt) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_498, UInt<1>(0h1), "") : assert_78 node _T_502 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = asUInt(reset) node _T_505 = eq(_T_504, UInt<1>(0h0)) when _T_505 : node _T_506 = eq(_T_503, UInt<1>(0h0)) when _T_506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_503, UInt<1>(0h1), "") : assert_79 node _T_507 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_507 : node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_511 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(_T_511, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_511, UInt<1>(0h1), "") : assert_81 node _T_515 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(_T_515, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_515, UInt<1>(0h1), "") : assert_82 node _T_519 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_520, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_524 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_524, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_528 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_528, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_532 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_532, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_536 = eq(a_first, UInt<1>(0h0)) node _T_537 = and(io.in.a.valid, _T_536) when _T_537 : node _T_538 = eq(io.in.a.bits.opcode, opcode) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_538, UInt<1>(0h1), "") : assert_87 node _T_542 = eq(io.in.a.bits.param, param) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_542, UInt<1>(0h1), "") : assert_88 node _T_546 = eq(io.in.a.bits.size, size) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_546, UInt<1>(0h1), "") : assert_89 node _T_550 = eq(io.in.a.bits.source, source) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_550, UInt<1>(0h1), "") : assert_90 node _T_554 = eq(io.in.a.bits.address, address) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_554, UInt<1>(0h1), "") : assert_91 node _T_558 = and(io.in.a.ready, io.in.a.valid) node _T_559 = and(_T_558, a_first) when _T_559 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_560 = eq(d_first, UInt<1>(0h0)) node _T_561 = and(io.in.d.valid, _T_560) when _T_561 : node _T_562 = eq(io.in.d.bits.opcode, opcode_1) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_562, UInt<1>(0h1), "") : assert_92 node _T_566 = eq(io.in.d.bits.param, param_1) node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(_T_566, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_566, UInt<1>(0h1), "") : assert_93 node _T_570 = eq(io.in.d.bits.size, size_1) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_570, UInt<1>(0h1), "") : assert_94 node _T_574 = eq(io.in.d.bits.source, source_1) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_574, UInt<1>(0h1), "") : assert_95 node _T_578 = eq(io.in.d.bits.sink, sink) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_578, UInt<1>(0h1), "") : assert_96 node _T_582 = eq(io.in.d.bits.denied, denied) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_582, UInt<1>(0h1), "") : assert_97 node _T_586 = and(io.in.d.ready, io.in.d.valid) node _T_587 = and(_T_586, d_first) when _T_587 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_588 = and(io.in.a.valid, a_first_1) node _T_589 = and(_T_588, UInt<1>(0h1)) when _T_589 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_590 = and(io.in.a.ready, io.in.a.valid) node _T_591 = and(_T_590, a_first_1) node _T_592 = and(_T_591, UInt<1>(0h1)) when _T_592 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_593 = dshr(inflight, io.in.a.bits.source) node _T_594 = bits(_T_593, 0, 0) node _T_595 = eq(_T_594, UInt<1>(0h0)) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_595, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_599 = and(io.in.d.valid, d_first_1) node _T_600 = and(_T_599, UInt<1>(0h1)) node _T_601 = eq(d_release_ack, UInt<1>(0h0)) node _T_602 = and(_T_600, _T_601) when _T_602 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_603 = and(io.in.d.ready, io.in.d.valid) node _T_604 = and(_T_603, d_first_1) node _T_605 = and(_T_604, UInt<1>(0h1)) node _T_606 = eq(d_release_ack, UInt<1>(0h0)) node _T_607 = and(_T_605, _T_606) when _T_607 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_608 = and(io.in.d.valid, d_first_1) node _T_609 = and(_T_608, UInt<1>(0h1)) node _T_610 = eq(d_release_ack, UInt<1>(0h0)) node _T_611 = and(_T_609, _T_610) when _T_611 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_612 = dshr(inflight, io.in.d.bits.source) node _T_613 = bits(_T_612, 0, 0) node _T_614 = or(_T_613, same_cycle_resp) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_614, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_618 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_619 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_620 = or(_T_618, _T_619) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_620, UInt<1>(0h1), "") : assert_100 node _T_624 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_624, UInt<1>(0h1), "") : assert_101 else : node _T_628 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_629 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_630 = or(_T_628, _T_629) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_630, UInt<1>(0h1), "") : assert_102 node _T_634 = eq(io.in.d.bits.size, a_size_lookup) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_634, UInt<1>(0h1), "") : assert_103 node _T_638 = and(io.in.d.valid, d_first_1) node _T_639 = and(_T_638, a_first_1) node _T_640 = and(_T_639, io.in.a.valid) node _T_641 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_642 = and(_T_640, _T_641) node _T_643 = eq(d_release_ack, UInt<1>(0h0)) node _T_644 = and(_T_642, _T_643) when _T_644 : node _T_645 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_646 = or(_T_645, io.in.a.ready) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_646, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_118 node _T_650 = orr(inflight) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_653 = or(_T_651, _T_652) node _T_654 = lt(watchdog, plusarg_reader.out) node _T_655 = or(_T_653, _T_654) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_655, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_659 = and(io.in.a.ready, io.in.a.valid) node _T_660 = and(io.in.d.ready, io.in.d.valid) node _T_661 = or(_T_659, _T_660) when _T_661 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_662 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<17>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_663 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_664 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_665 = and(_T_663, _T_664) node _T_666 = and(_T_662, _T_665) when _T_666 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_667 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_668 = and(_T_667, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_669 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_673 = dshr(inflight_1, _WIRE_15.bits.source) node _T_674 = bits(_T_673, 0, 0) node _T_675 = eq(_T_674, UInt<1>(0h0)) node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(_T_675, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_675, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_679 = and(io.in.d.valid, d_first_2) node _T_680 = and(_T_679, UInt<1>(0h1)) node _T_681 = and(_T_680, d_release_ack_1) when _T_681 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_682 = and(io.in.d.ready, io.in.d.valid) node _T_683 = and(_T_682, d_first_2) node _T_684 = and(_T_683, UInt<1>(0h1)) node _T_685 = and(_T_684, d_release_ack_1) when _T_685 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_686 = and(io.in.d.valid, d_first_2) node _T_687 = and(_T_686, UInt<1>(0h1)) node _T_688 = and(_T_687, d_release_ack_1) when _T_688 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_689 = dshr(inflight_1, io.in.d.bits.source) node _T_690 = bits(_T_689, 0, 0) node _T_691 = or(_T_690, same_cycle_resp_1) node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(_T_691, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_691, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_695 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_696 = asUInt(reset) node _T_697 = eq(_T_696, UInt<1>(0h0)) when _T_697 : node _T_698 = eq(_T_695, UInt<1>(0h0)) when _T_698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_695, UInt<1>(0h1), "") : assert_108 else : node _T_699 = eq(io.in.d.bits.size, c_size_lookup) node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(_T_699, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_699, UInt<1>(0h1), "") : assert_109 node _T_703 = and(io.in.d.valid, d_first_2) node _T_704 = and(_T_703, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_705 = and(_T_704, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_706 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_707 = and(_T_705, _T_706) node _T_708 = and(_T_707, d_release_ack_1) node _T_709 = eq(c_probe_ack, UInt<1>(0h0)) node _T_710 = and(_T_708, _T_709) when _T_710 : node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_712 = or(_T_711, _WIRE_23.ready) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_119 node _T_716 = orr(inflight_1) node _T_717 = eq(_T_716, UInt<1>(0h0)) node _T_718 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_719 = or(_T_717, _T_718) node _T_720 = lt(watchdog_1, plusarg_reader_1.out) node _T_721 = or(_T_719, _T_720) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_721, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_725 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_726 = and(io.in.d.ready, io.in.d.valid) node _T_727 = or(_T_725, _T_726) when _T_727 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_58( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [8255:0] _inflight_opcodes_T_4 = 8256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [8255:0] _inflight_sizes_T_4 = 8256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [2063:0] _inflight_T_4 = 2064'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [8255:0] d_opcodes_clr_1 = 8256'h0; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1 = 8256'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2063:0] d_clr_1 = 2064'h0; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1 = 2064'h0; // @[Monitor.scala:775:34] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_659; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_592 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_4 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_605 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_12 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_21 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_12( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_21 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_Registered : output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut.sync, nodeIn

module IntSyncCrossingSource_n1x1_Registered(); // @[Crossing.scala:48:9] wire auto_in_0 = 1'h0; // @[Crossing.scala:48:9] wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:48:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_263 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_487 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_263( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_487 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BeatMerger : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { shift : UInt<6>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<8>, len : UInt<16>, block_stride : UInt<16>, spad_row_offset : UInt<9>, lg_len_req : UInt<3>, bytes_to_read : UInt<7>, cmd_id : UInt<3>}}, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<128>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<512>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, mask : UInt<1>[64], last : UInt<1>}}} reg req : { valid : UInt<1>, bits : { shift : UInt<6>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<8>, len : UInt<16>, block_stride : UInt<16>, spad_row_offset : UInt<9>, lg_len_req : UInt<3>, bytes_to_read : UInt<7>, cmd_id : UInt<3>}}, clock reg buffer : UInt<512>, clock node rowBytes = mux(req.bits.has_acc_bitwidth, UInt<7>(0h40), UInt<5>(0h10)) reg bytesSent : UInt<7>, clock reg bytesRead : UInt<7>, clock node _bytesReadAfterShift_T = gt(bytesRead, req.bits.shift) node _bytesReadAfterShift_T_1 = sub(bytesRead, req.bits.shift) node _bytesReadAfterShift_T_2 = tail(_bytesReadAfterShift_T_1, 1) node bytesReadAfterShift = mux(_bytesReadAfterShift_T, _bytesReadAfterShift_T_2, UInt<1>(0h0)) node _bytesDiscarded_T = sub(bytesRead, bytesReadAfterShift) node bytesDiscarded = tail(_bytesDiscarded_T, 1) node _usefulBytesRead_T = lt(bytesReadAfterShift, req.bits.bytes_to_read) node usefulBytesRead = mux(_usefulBytesRead_T, bytesReadAfterShift, req.bits.bytes_to_read) node _bytesSent_next_spad_row_offset_T = eq(bytesSent, UInt<1>(0h0)) node bytesSent_next_spad_row_offset = mux(_bytesSent_next_spad_row_offset_T, req.bits.spad_row_offset, UInt<1>(0h0)) node _bytesSent_next_T = sub(rowBytes, bytesSent_next_spad_row_offset) node _bytesSent_next_T_1 = tail(_bytesSent_next_T, 1) node _bytesSent_next_T_2 = add(bytesSent, _bytesSent_next_T_1) node _bytesSent_next_T_3 = gt(_bytesSent_next_T_2, req.bits.bytes_to_read) node _bytesSent_next_T_4 = add(bytesSent, _bytesSent_next_T_1) node _bytesSent_next_T_5 = tail(_bytesSent_next_T_4, 1) node bytesSent_next = mux(_bytesSent_next_T_3, req.bits.bytes_to_read, _bytesSent_next_T_5) node last_sending = eq(bytesSent_next, req.bits.bytes_to_read) node _last_reading_T = dshl(UInt<1>(0h1), req.bits.lg_len_req) node _last_reading_T_1 = sub(_last_reading_T, bytesRead) node _last_reading_T_2 = tail(_last_reading_T_1, 1) node last_reading = geq(UInt<5>(0h10), _last_reading_T_2) node _io_req_ready_T = eq(req.valid, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _io_in_ready_T = and(io.req.ready, io.req.valid) node _io_in_ready_T_1 = dshl(UInt<1>(0h1), req.bits.lg_len_req) node _io_in_ready_T_2 = neq(bytesRead, _io_in_ready_T_1) node _io_in_ready_T_3 = and(req.valid, _io_in_ready_T_2) node _io_in_ready_T_4 = or(_io_in_ready_T, _io_in_ready_T_3) connect io.in.ready, _io_in_ready_T_4 node _io_out_valid_T = gt(usefulBytesRead, bytesSent) node _io_out_valid_T_1 = and(req.valid, _io_out_valid_T) node _io_out_valid_T_2 = sub(usefulBytesRead, bytesSent) node _io_out_valid_T_3 = tail(_io_out_valid_T_2, 1) node _io_out_valid_T_4 = geq(_io_out_valid_T_3, rowBytes) node _io_out_valid_T_5 = eq(usefulBytesRead, req.bits.bytes_to_read) node _io_out_valid_T_6 = or(_io_out_valid_T_4, _io_out_valid_T_5) node _io_out_valid_T_7 = and(_io_out_valid_T_1, _io_out_valid_T_6) connect io.out.valid, _io_out_valid_T_7 node _io_out_bits_data_T = mul(bytesSent, UInt<4>(0h8)) node _io_out_bits_data_T_1 = dshr(buffer, _io_out_bits_data_T) node _io_out_bits_data_T_2 = eq(bytesSent, UInt<1>(0h0)) node _io_out_bits_data_T_3 = mul(req.bits.spad_row_offset, UInt<4>(0h8)) node _io_out_bits_data_T_4 = mux(_io_out_bits_data_T_2, _io_out_bits_data_T_3, UInt<1>(0h0)) node _io_out_bits_data_T_5 = dshl(_io_out_bits_data_T_1, _io_out_bits_data_T_4) connect io.out.bits.data, _io_out_bits_data_T_5 node _spad_row_offset_T = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset = mux(_spad_row_offset_T, req.bits.spad_row_offset, UInt<1>(0h0)) node _T = geq(UInt<1>(0h0), spad_row_offset) node _T_1 = sub(req.bits.bytes_to_read, bytesSent) node _T_2 = tail(_T_1, 1) node _T_3 = add(spad_row_offset, _T_2) node _T_4 = lt(UInt<1>(0h0), _T_3) node _T_5 = and(_T, _T_4) node _spad_row_offset_T_1 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_1 = mux(_spad_row_offset_T_1, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_6 = geq(UInt<1>(0h1), spad_row_offset_1) node _T_7 = sub(req.bits.bytes_to_read, bytesSent) node _T_8 = tail(_T_7, 1) node _T_9 = add(spad_row_offset_1, _T_8) node _T_10 = lt(UInt<1>(0h1), _T_9) node _T_11 = and(_T_6, _T_10) node _spad_row_offset_T_2 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_2 = mux(_spad_row_offset_T_2, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_12 = geq(UInt<2>(0h2), spad_row_offset_2) node _T_13 = sub(req.bits.bytes_to_read, bytesSent) node _T_14 = tail(_T_13, 1) node _T_15 = add(spad_row_offset_2, _T_14) node _T_16 = lt(UInt<2>(0h2), _T_15) node _T_17 = and(_T_12, _T_16) node _spad_row_offset_T_3 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_3 = mux(_spad_row_offset_T_3, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_18 = geq(UInt<2>(0h3), spad_row_offset_3) node _T_19 = sub(req.bits.bytes_to_read, bytesSent) node _T_20 = tail(_T_19, 1) node _T_21 = add(spad_row_offset_3, _T_20) node _T_22 = lt(UInt<2>(0h3), _T_21) node _T_23 = and(_T_18, _T_22) node _spad_row_offset_T_4 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_4 = mux(_spad_row_offset_T_4, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_24 = geq(UInt<3>(0h4), spad_row_offset_4) node _T_25 = sub(req.bits.bytes_to_read, bytesSent) node _T_26 = tail(_T_25, 1) node _T_27 = add(spad_row_offset_4, _T_26) node _T_28 = lt(UInt<3>(0h4), _T_27) node _T_29 = and(_T_24, _T_28) node _spad_row_offset_T_5 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_5 = mux(_spad_row_offset_T_5, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_30 = geq(UInt<3>(0h5), spad_row_offset_5) node _T_31 = sub(req.bits.bytes_to_read, bytesSent) node _T_32 = tail(_T_31, 1) node _T_33 = add(spad_row_offset_5, _T_32) node _T_34 = lt(UInt<3>(0h5), _T_33) node _T_35 = and(_T_30, _T_34) node _spad_row_offset_T_6 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_6 = mux(_spad_row_offset_T_6, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_36 = geq(UInt<3>(0h6), spad_row_offset_6) node _T_37 = sub(req.bits.bytes_to_read, bytesSent) node _T_38 = tail(_T_37, 1) node _T_39 = add(spad_row_offset_6, _T_38) node _T_40 = lt(UInt<3>(0h6), _T_39) node _T_41 = and(_T_36, _T_40) node _spad_row_offset_T_7 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_7 = mux(_spad_row_offset_T_7, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_42 = geq(UInt<3>(0h7), spad_row_offset_7) node _T_43 = sub(req.bits.bytes_to_read, bytesSent) node _T_44 = tail(_T_43, 1) node _T_45 = add(spad_row_offset_7, _T_44) node _T_46 = lt(UInt<3>(0h7), _T_45) node _T_47 = and(_T_42, _T_46) node _spad_row_offset_T_8 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_8 = mux(_spad_row_offset_T_8, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_48 = geq(UInt<4>(0h8), spad_row_offset_8) node _T_49 = sub(req.bits.bytes_to_read, bytesSent) node _T_50 = tail(_T_49, 1) node _T_51 = add(spad_row_offset_8, _T_50) node _T_52 = lt(UInt<4>(0h8), _T_51) node _T_53 = and(_T_48, _T_52) node _spad_row_offset_T_9 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_9 = mux(_spad_row_offset_T_9, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_54 = geq(UInt<4>(0h9), spad_row_offset_9) node _T_55 = sub(req.bits.bytes_to_read, bytesSent) node _T_56 = tail(_T_55, 1) node _T_57 = add(spad_row_offset_9, _T_56) node _T_58 = lt(UInt<4>(0h9), _T_57) node _T_59 = and(_T_54, _T_58) node _spad_row_offset_T_10 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_10 = mux(_spad_row_offset_T_10, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_60 = geq(UInt<4>(0ha), spad_row_offset_10) node _T_61 = sub(req.bits.bytes_to_read, bytesSent) node _T_62 = tail(_T_61, 1) node _T_63 = add(spad_row_offset_10, _T_62) node _T_64 = lt(UInt<4>(0ha), _T_63) node _T_65 = and(_T_60, _T_64) node _spad_row_offset_T_11 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_11 = mux(_spad_row_offset_T_11, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_66 = geq(UInt<4>(0hb), spad_row_offset_11) node _T_67 = sub(req.bits.bytes_to_read, bytesSent) node _T_68 = tail(_T_67, 1) node _T_69 = add(spad_row_offset_11, _T_68) node _T_70 = lt(UInt<4>(0hb), _T_69) node _T_71 = and(_T_66, _T_70) node _spad_row_offset_T_12 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_12 = mux(_spad_row_offset_T_12, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_72 = geq(UInt<4>(0hc), spad_row_offset_12) node _T_73 = sub(req.bits.bytes_to_read, bytesSent) node _T_74 = tail(_T_73, 1) node _T_75 = add(spad_row_offset_12, _T_74) node _T_76 = lt(UInt<4>(0hc), _T_75) node _T_77 = and(_T_72, _T_76) node _spad_row_offset_T_13 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_13 = mux(_spad_row_offset_T_13, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_78 = geq(UInt<4>(0hd), spad_row_offset_13) node _T_79 = sub(req.bits.bytes_to_read, bytesSent) node _T_80 = tail(_T_79, 1) node _T_81 = add(spad_row_offset_13, _T_80) node _T_82 = lt(UInt<4>(0hd), _T_81) node _T_83 = and(_T_78, _T_82) node _spad_row_offset_T_14 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_14 = mux(_spad_row_offset_T_14, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_84 = geq(UInt<4>(0he), spad_row_offset_14) node _T_85 = sub(req.bits.bytes_to_read, bytesSent) node _T_86 = tail(_T_85, 1) node _T_87 = add(spad_row_offset_14, _T_86) node _T_88 = lt(UInt<4>(0he), _T_87) node _T_89 = and(_T_84, _T_88) node _spad_row_offset_T_15 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_15 = mux(_spad_row_offset_T_15, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_90 = geq(UInt<4>(0hf), spad_row_offset_15) node _T_91 = sub(req.bits.bytes_to_read, bytesSent) node _T_92 = tail(_T_91, 1) node _T_93 = add(spad_row_offset_15, _T_92) node _T_94 = lt(UInt<4>(0hf), _T_93) node _T_95 = and(_T_90, _T_94) node _spad_row_offset_T_16 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_16 = mux(_spad_row_offset_T_16, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_96 = geq(UInt<5>(0h10), spad_row_offset_16) node _T_97 = sub(req.bits.bytes_to_read, bytesSent) node _T_98 = tail(_T_97, 1) node _T_99 = add(spad_row_offset_16, _T_98) node _T_100 = lt(UInt<5>(0h10), _T_99) node _T_101 = and(_T_96, _T_100) node _spad_row_offset_T_17 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_17 = mux(_spad_row_offset_T_17, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_102 = geq(UInt<5>(0h11), spad_row_offset_17) node _T_103 = sub(req.bits.bytes_to_read, bytesSent) node _T_104 = tail(_T_103, 1) node _T_105 = add(spad_row_offset_17, _T_104) node _T_106 = lt(UInt<5>(0h11), _T_105) node _T_107 = and(_T_102, _T_106) node _spad_row_offset_T_18 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_18 = mux(_spad_row_offset_T_18, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_108 = geq(UInt<5>(0h12), spad_row_offset_18) node _T_109 = sub(req.bits.bytes_to_read, bytesSent) node _T_110 = tail(_T_109, 1) node _T_111 = add(spad_row_offset_18, _T_110) node _T_112 = lt(UInt<5>(0h12), _T_111) node _T_113 = and(_T_108, _T_112) node _spad_row_offset_T_19 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_19 = mux(_spad_row_offset_T_19, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_114 = geq(UInt<5>(0h13), spad_row_offset_19) node _T_115 = sub(req.bits.bytes_to_read, bytesSent) node _T_116 = tail(_T_115, 1) node _T_117 = add(spad_row_offset_19, _T_116) node _T_118 = lt(UInt<5>(0h13), _T_117) node _T_119 = and(_T_114, _T_118) node _spad_row_offset_T_20 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_20 = mux(_spad_row_offset_T_20, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_120 = geq(UInt<5>(0h14), spad_row_offset_20) node _T_121 = sub(req.bits.bytes_to_read, bytesSent) node _T_122 = tail(_T_121, 1) node _T_123 = add(spad_row_offset_20, _T_122) node _T_124 = lt(UInt<5>(0h14), _T_123) node _T_125 = and(_T_120, _T_124) node _spad_row_offset_T_21 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_21 = mux(_spad_row_offset_T_21, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_126 = geq(UInt<5>(0h15), spad_row_offset_21) node _T_127 = sub(req.bits.bytes_to_read, bytesSent) node _T_128 = tail(_T_127, 1) node _T_129 = add(spad_row_offset_21, _T_128) node _T_130 = lt(UInt<5>(0h15), _T_129) node _T_131 = and(_T_126, _T_130) node _spad_row_offset_T_22 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_22 = mux(_spad_row_offset_T_22, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_132 = geq(UInt<5>(0h16), spad_row_offset_22) node _T_133 = sub(req.bits.bytes_to_read, bytesSent) node _T_134 = tail(_T_133, 1) node _T_135 = add(spad_row_offset_22, _T_134) node _T_136 = lt(UInt<5>(0h16), _T_135) node _T_137 = and(_T_132, _T_136) node _spad_row_offset_T_23 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_23 = mux(_spad_row_offset_T_23, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_138 = geq(UInt<5>(0h17), spad_row_offset_23) node _T_139 = sub(req.bits.bytes_to_read, bytesSent) node _T_140 = tail(_T_139, 1) node _T_141 = add(spad_row_offset_23, _T_140) node _T_142 = lt(UInt<5>(0h17), _T_141) node _T_143 = and(_T_138, _T_142) node _spad_row_offset_T_24 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_24 = mux(_spad_row_offset_T_24, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_144 = geq(UInt<5>(0h18), spad_row_offset_24) node _T_145 = sub(req.bits.bytes_to_read, bytesSent) node _T_146 = tail(_T_145, 1) node _T_147 = add(spad_row_offset_24, _T_146) node _T_148 = lt(UInt<5>(0h18), _T_147) node _T_149 = and(_T_144, _T_148) node _spad_row_offset_T_25 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_25 = mux(_spad_row_offset_T_25, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_150 = geq(UInt<5>(0h19), spad_row_offset_25) node _T_151 = sub(req.bits.bytes_to_read, bytesSent) node _T_152 = tail(_T_151, 1) node _T_153 = add(spad_row_offset_25, _T_152) node _T_154 = lt(UInt<5>(0h19), _T_153) node _T_155 = and(_T_150, _T_154) node _spad_row_offset_T_26 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_26 = mux(_spad_row_offset_T_26, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_156 = geq(UInt<5>(0h1a), spad_row_offset_26) node _T_157 = sub(req.bits.bytes_to_read, bytesSent) node _T_158 = tail(_T_157, 1) node _T_159 = add(spad_row_offset_26, _T_158) node _T_160 = lt(UInt<5>(0h1a), _T_159) node _T_161 = and(_T_156, _T_160) node _spad_row_offset_T_27 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_27 = mux(_spad_row_offset_T_27, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_162 = geq(UInt<5>(0h1b), spad_row_offset_27) node _T_163 = sub(req.bits.bytes_to_read, bytesSent) node _T_164 = tail(_T_163, 1) node _T_165 = add(spad_row_offset_27, _T_164) node _T_166 = lt(UInt<5>(0h1b), _T_165) node _T_167 = and(_T_162, _T_166) node _spad_row_offset_T_28 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_28 = mux(_spad_row_offset_T_28, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_168 = geq(UInt<5>(0h1c), spad_row_offset_28) node _T_169 = sub(req.bits.bytes_to_read, bytesSent) node _T_170 = tail(_T_169, 1) node _T_171 = add(spad_row_offset_28, _T_170) node _T_172 = lt(UInt<5>(0h1c), _T_171) node _T_173 = and(_T_168, _T_172) node _spad_row_offset_T_29 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_29 = mux(_spad_row_offset_T_29, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_174 = geq(UInt<5>(0h1d), spad_row_offset_29) node _T_175 = sub(req.bits.bytes_to_read, bytesSent) node _T_176 = tail(_T_175, 1) node _T_177 = add(spad_row_offset_29, _T_176) node _T_178 = lt(UInt<5>(0h1d), _T_177) node _T_179 = and(_T_174, _T_178) node _spad_row_offset_T_30 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_30 = mux(_spad_row_offset_T_30, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_180 = geq(UInt<5>(0h1e), spad_row_offset_30) node _T_181 = sub(req.bits.bytes_to_read, bytesSent) node _T_182 = tail(_T_181, 1) node _T_183 = add(spad_row_offset_30, _T_182) node _T_184 = lt(UInt<5>(0h1e), _T_183) node _T_185 = and(_T_180, _T_184) node _spad_row_offset_T_31 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_31 = mux(_spad_row_offset_T_31, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_186 = geq(UInt<5>(0h1f), spad_row_offset_31) node _T_187 = sub(req.bits.bytes_to_read, bytesSent) node _T_188 = tail(_T_187, 1) node _T_189 = add(spad_row_offset_31, _T_188) node _T_190 = lt(UInt<5>(0h1f), _T_189) node _T_191 = and(_T_186, _T_190) node _spad_row_offset_T_32 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_32 = mux(_spad_row_offset_T_32, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_192 = geq(UInt<6>(0h20), spad_row_offset_32) node _T_193 = sub(req.bits.bytes_to_read, bytesSent) node _T_194 = tail(_T_193, 1) node _T_195 = add(spad_row_offset_32, _T_194) node _T_196 = lt(UInt<6>(0h20), _T_195) node _T_197 = and(_T_192, _T_196) node _spad_row_offset_T_33 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_33 = mux(_spad_row_offset_T_33, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_198 = geq(UInt<6>(0h21), spad_row_offset_33) node _T_199 = sub(req.bits.bytes_to_read, bytesSent) node _T_200 = tail(_T_199, 1) node _T_201 = add(spad_row_offset_33, _T_200) node _T_202 = lt(UInt<6>(0h21), _T_201) node _T_203 = and(_T_198, _T_202) node _spad_row_offset_T_34 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_34 = mux(_spad_row_offset_T_34, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_204 = geq(UInt<6>(0h22), spad_row_offset_34) node _T_205 = sub(req.bits.bytes_to_read, bytesSent) node _T_206 = tail(_T_205, 1) node _T_207 = add(spad_row_offset_34, _T_206) node _T_208 = lt(UInt<6>(0h22), _T_207) node _T_209 = and(_T_204, _T_208) node _spad_row_offset_T_35 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_35 = mux(_spad_row_offset_T_35, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_210 = geq(UInt<6>(0h23), spad_row_offset_35) node _T_211 = sub(req.bits.bytes_to_read, bytesSent) node _T_212 = tail(_T_211, 1) node _T_213 = add(spad_row_offset_35, _T_212) node _T_214 = lt(UInt<6>(0h23), _T_213) node _T_215 = and(_T_210, _T_214) node _spad_row_offset_T_36 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_36 = mux(_spad_row_offset_T_36, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_216 = geq(UInt<6>(0h24), spad_row_offset_36) node _T_217 = sub(req.bits.bytes_to_read, bytesSent) node _T_218 = tail(_T_217, 1) node _T_219 = add(spad_row_offset_36, _T_218) node _T_220 = lt(UInt<6>(0h24), _T_219) node _T_221 = and(_T_216, _T_220) node _spad_row_offset_T_37 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_37 = mux(_spad_row_offset_T_37, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_222 = geq(UInt<6>(0h25), spad_row_offset_37) node _T_223 = sub(req.bits.bytes_to_read, bytesSent) node _T_224 = tail(_T_223, 1) node _T_225 = add(spad_row_offset_37, _T_224) node _T_226 = lt(UInt<6>(0h25), _T_225) node _T_227 = and(_T_222, _T_226) node _spad_row_offset_T_38 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_38 = mux(_spad_row_offset_T_38, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_228 = geq(UInt<6>(0h26), spad_row_offset_38) node _T_229 = sub(req.bits.bytes_to_read, bytesSent) node _T_230 = tail(_T_229, 1) node _T_231 = add(spad_row_offset_38, _T_230) node _T_232 = lt(UInt<6>(0h26), _T_231) node _T_233 = and(_T_228, _T_232) node _spad_row_offset_T_39 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_39 = mux(_spad_row_offset_T_39, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_234 = geq(UInt<6>(0h27), spad_row_offset_39) node _T_235 = sub(req.bits.bytes_to_read, bytesSent) node _T_236 = tail(_T_235, 1) node _T_237 = add(spad_row_offset_39, _T_236) node _T_238 = lt(UInt<6>(0h27), _T_237) node _T_239 = and(_T_234, _T_238) node _spad_row_offset_T_40 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_40 = mux(_spad_row_offset_T_40, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_240 = geq(UInt<6>(0h28), spad_row_offset_40) node _T_241 = sub(req.bits.bytes_to_read, bytesSent) node _T_242 = tail(_T_241, 1) node _T_243 = add(spad_row_offset_40, _T_242) node _T_244 = lt(UInt<6>(0h28), _T_243) node _T_245 = and(_T_240, _T_244) node _spad_row_offset_T_41 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_41 = mux(_spad_row_offset_T_41, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_246 = geq(UInt<6>(0h29), spad_row_offset_41) node _T_247 = sub(req.bits.bytes_to_read, bytesSent) node _T_248 = tail(_T_247, 1) node _T_249 = add(spad_row_offset_41, _T_248) node _T_250 = lt(UInt<6>(0h29), _T_249) node _T_251 = and(_T_246, _T_250) node _spad_row_offset_T_42 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_42 = mux(_spad_row_offset_T_42, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_252 = geq(UInt<6>(0h2a), spad_row_offset_42) node _T_253 = sub(req.bits.bytes_to_read, bytesSent) node _T_254 = tail(_T_253, 1) node _T_255 = add(spad_row_offset_42, _T_254) node _T_256 = lt(UInt<6>(0h2a), _T_255) node _T_257 = and(_T_252, _T_256) node _spad_row_offset_T_43 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_43 = mux(_spad_row_offset_T_43, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_258 = geq(UInt<6>(0h2b), spad_row_offset_43) node _T_259 = sub(req.bits.bytes_to_read, bytesSent) node _T_260 = tail(_T_259, 1) node _T_261 = add(spad_row_offset_43, _T_260) node _T_262 = lt(UInt<6>(0h2b), _T_261) node _T_263 = and(_T_258, _T_262) node _spad_row_offset_T_44 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_44 = mux(_spad_row_offset_T_44, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_264 = geq(UInt<6>(0h2c), spad_row_offset_44) node _T_265 = sub(req.bits.bytes_to_read, bytesSent) node _T_266 = tail(_T_265, 1) node _T_267 = add(spad_row_offset_44, _T_266) node _T_268 = lt(UInt<6>(0h2c), _T_267) node _T_269 = and(_T_264, _T_268) node _spad_row_offset_T_45 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_45 = mux(_spad_row_offset_T_45, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_270 = geq(UInt<6>(0h2d), spad_row_offset_45) node _T_271 = sub(req.bits.bytes_to_read, bytesSent) node _T_272 = tail(_T_271, 1) node _T_273 = add(spad_row_offset_45, _T_272) node _T_274 = lt(UInt<6>(0h2d), _T_273) node _T_275 = and(_T_270, _T_274) node _spad_row_offset_T_46 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_46 = mux(_spad_row_offset_T_46, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_276 = geq(UInt<6>(0h2e), spad_row_offset_46) node _T_277 = sub(req.bits.bytes_to_read, bytesSent) node _T_278 = tail(_T_277, 1) node _T_279 = add(spad_row_offset_46, _T_278) node _T_280 = lt(UInt<6>(0h2e), _T_279) node _T_281 = and(_T_276, _T_280) node _spad_row_offset_T_47 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_47 = mux(_spad_row_offset_T_47, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_282 = geq(UInt<6>(0h2f), spad_row_offset_47) node _T_283 = sub(req.bits.bytes_to_read, bytesSent) node _T_284 = tail(_T_283, 1) node _T_285 = add(spad_row_offset_47, _T_284) node _T_286 = lt(UInt<6>(0h2f), _T_285) node _T_287 = and(_T_282, _T_286) node _spad_row_offset_T_48 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_48 = mux(_spad_row_offset_T_48, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_288 = geq(UInt<6>(0h30), spad_row_offset_48) node _T_289 = sub(req.bits.bytes_to_read, bytesSent) node _T_290 = tail(_T_289, 1) node _T_291 = add(spad_row_offset_48, _T_290) node _T_292 = lt(UInt<6>(0h30), _T_291) node _T_293 = and(_T_288, _T_292) node _spad_row_offset_T_49 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_49 = mux(_spad_row_offset_T_49, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_294 = geq(UInt<6>(0h31), spad_row_offset_49) node _T_295 = sub(req.bits.bytes_to_read, bytesSent) node _T_296 = tail(_T_295, 1) node _T_297 = add(spad_row_offset_49, _T_296) node _T_298 = lt(UInt<6>(0h31), _T_297) node _T_299 = and(_T_294, _T_298) node _spad_row_offset_T_50 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_50 = mux(_spad_row_offset_T_50, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_300 = geq(UInt<6>(0h32), spad_row_offset_50) node _T_301 = sub(req.bits.bytes_to_read, bytesSent) node _T_302 = tail(_T_301, 1) node _T_303 = add(spad_row_offset_50, _T_302) node _T_304 = lt(UInt<6>(0h32), _T_303) node _T_305 = and(_T_300, _T_304) node _spad_row_offset_T_51 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_51 = mux(_spad_row_offset_T_51, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_306 = geq(UInt<6>(0h33), spad_row_offset_51) node _T_307 = sub(req.bits.bytes_to_read, bytesSent) node _T_308 = tail(_T_307, 1) node _T_309 = add(spad_row_offset_51, _T_308) node _T_310 = lt(UInt<6>(0h33), _T_309) node _T_311 = and(_T_306, _T_310) node _spad_row_offset_T_52 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_52 = mux(_spad_row_offset_T_52, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_312 = geq(UInt<6>(0h34), spad_row_offset_52) node _T_313 = sub(req.bits.bytes_to_read, bytesSent) node _T_314 = tail(_T_313, 1) node _T_315 = add(spad_row_offset_52, _T_314) node _T_316 = lt(UInt<6>(0h34), _T_315) node _T_317 = and(_T_312, _T_316) node _spad_row_offset_T_53 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_53 = mux(_spad_row_offset_T_53, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_318 = geq(UInt<6>(0h35), spad_row_offset_53) node _T_319 = sub(req.bits.bytes_to_read, bytesSent) node _T_320 = tail(_T_319, 1) node _T_321 = add(spad_row_offset_53, _T_320) node _T_322 = lt(UInt<6>(0h35), _T_321) node _T_323 = and(_T_318, _T_322) node _spad_row_offset_T_54 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_54 = mux(_spad_row_offset_T_54, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_324 = geq(UInt<6>(0h36), spad_row_offset_54) node _T_325 = sub(req.bits.bytes_to_read, bytesSent) node _T_326 = tail(_T_325, 1) node _T_327 = add(spad_row_offset_54, _T_326) node _T_328 = lt(UInt<6>(0h36), _T_327) node _T_329 = and(_T_324, _T_328) node _spad_row_offset_T_55 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_55 = mux(_spad_row_offset_T_55, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_330 = geq(UInt<6>(0h37), spad_row_offset_55) node _T_331 = sub(req.bits.bytes_to_read, bytesSent) node _T_332 = tail(_T_331, 1) node _T_333 = add(spad_row_offset_55, _T_332) node _T_334 = lt(UInt<6>(0h37), _T_333) node _T_335 = and(_T_330, _T_334) node _spad_row_offset_T_56 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_56 = mux(_spad_row_offset_T_56, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_336 = geq(UInt<6>(0h38), spad_row_offset_56) node _T_337 = sub(req.bits.bytes_to_read, bytesSent) node _T_338 = tail(_T_337, 1) node _T_339 = add(spad_row_offset_56, _T_338) node _T_340 = lt(UInt<6>(0h38), _T_339) node _T_341 = and(_T_336, _T_340) node _spad_row_offset_T_57 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_57 = mux(_spad_row_offset_T_57, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_342 = geq(UInt<6>(0h39), spad_row_offset_57) node _T_343 = sub(req.bits.bytes_to_read, bytesSent) node _T_344 = tail(_T_343, 1) node _T_345 = add(spad_row_offset_57, _T_344) node _T_346 = lt(UInt<6>(0h39), _T_345) node _T_347 = and(_T_342, _T_346) node _spad_row_offset_T_58 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_58 = mux(_spad_row_offset_T_58, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_348 = geq(UInt<6>(0h3a), spad_row_offset_58) node _T_349 = sub(req.bits.bytes_to_read, bytesSent) node _T_350 = tail(_T_349, 1) node _T_351 = add(spad_row_offset_58, _T_350) node _T_352 = lt(UInt<6>(0h3a), _T_351) node _T_353 = and(_T_348, _T_352) node _spad_row_offset_T_59 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_59 = mux(_spad_row_offset_T_59, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_354 = geq(UInt<6>(0h3b), spad_row_offset_59) node _T_355 = sub(req.bits.bytes_to_read, bytesSent) node _T_356 = tail(_T_355, 1) node _T_357 = add(spad_row_offset_59, _T_356) node _T_358 = lt(UInt<6>(0h3b), _T_357) node _T_359 = and(_T_354, _T_358) node _spad_row_offset_T_60 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_60 = mux(_spad_row_offset_T_60, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_360 = geq(UInt<6>(0h3c), spad_row_offset_60) node _T_361 = sub(req.bits.bytes_to_read, bytesSent) node _T_362 = tail(_T_361, 1) node _T_363 = add(spad_row_offset_60, _T_362) node _T_364 = lt(UInt<6>(0h3c), _T_363) node _T_365 = and(_T_360, _T_364) node _spad_row_offset_T_61 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_61 = mux(_spad_row_offset_T_61, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_366 = geq(UInt<6>(0h3d), spad_row_offset_61) node _T_367 = sub(req.bits.bytes_to_read, bytesSent) node _T_368 = tail(_T_367, 1) node _T_369 = add(spad_row_offset_61, _T_368) node _T_370 = lt(UInt<6>(0h3d), _T_369) node _T_371 = and(_T_366, _T_370) node _spad_row_offset_T_62 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_62 = mux(_spad_row_offset_T_62, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_372 = geq(UInt<6>(0h3e), spad_row_offset_62) node _T_373 = sub(req.bits.bytes_to_read, bytesSent) node _T_374 = tail(_T_373, 1) node _T_375 = add(spad_row_offset_62, _T_374) node _T_376 = lt(UInt<6>(0h3e), _T_375) node _T_377 = and(_T_372, _T_376) node _spad_row_offset_T_63 = eq(bytesSent, UInt<1>(0h0)) node spad_row_offset_63 = mux(_spad_row_offset_T_63, req.bits.spad_row_offset, UInt<1>(0h0)) node _T_378 = geq(UInt<6>(0h3f), spad_row_offset_63) node _T_379 = sub(req.bits.bytes_to_read, bytesSent) node _T_380 = tail(_T_379, 1) node _T_381 = add(spad_row_offset_63, _T_380) node _T_382 = lt(UInt<6>(0h3f), _T_381) node _T_383 = and(_T_378, _T_382) wire _WIRE : UInt<1>[64] connect _WIRE[0], _T_5 connect _WIRE[1], _T_11 connect _WIRE[2], _T_17 connect _WIRE[3], _T_23 connect _WIRE[4], _T_29 connect _WIRE[5], _T_35 connect _WIRE[6], _T_41 connect _WIRE[7], _T_47 connect _WIRE[8], _T_53 connect _WIRE[9], _T_59 connect _WIRE[10], _T_65 connect _WIRE[11], _T_71 connect _WIRE[12], _T_77 connect _WIRE[13], _T_83 connect _WIRE[14], _T_89 connect _WIRE[15], _T_95 connect _WIRE[16], _T_101 connect _WIRE[17], _T_107 connect _WIRE[18], _T_113 connect _WIRE[19], _T_119 connect _WIRE[20], _T_125 connect _WIRE[21], _T_131 connect _WIRE[22], _T_137 connect _WIRE[23], _T_143 connect _WIRE[24], _T_149 connect _WIRE[25], _T_155 connect _WIRE[26], _T_161 connect _WIRE[27], _T_167 connect _WIRE[28], _T_173 connect _WIRE[29], _T_179 connect _WIRE[30], _T_185 connect _WIRE[31], _T_191 connect _WIRE[32], _T_197 connect _WIRE[33], _T_203 connect _WIRE[34], _T_209 connect _WIRE[35], _T_215 connect _WIRE[36], _T_221 connect _WIRE[37], _T_227 connect _WIRE[38], _T_233 connect _WIRE[39], _T_239 connect _WIRE[40], _T_245 connect _WIRE[41], _T_251 connect _WIRE[42], _T_257 connect _WIRE[43], _T_263 connect _WIRE[44], _T_269 connect _WIRE[45], _T_275 connect _WIRE[46], _T_281 connect _WIRE[47], _T_287 connect _WIRE[48], _T_293 connect _WIRE[49], _T_299 connect _WIRE[50], _T_305 connect _WIRE[51], _T_311 connect _WIRE[52], _T_317 connect _WIRE[53], _T_323 connect _WIRE[54], _T_329 connect _WIRE[55], _T_335 connect _WIRE[56], _T_341 connect _WIRE[57], _T_347 connect _WIRE[58], _T_353 connect _WIRE[59], _T_359 connect _WIRE[60], _T_365 connect _WIRE[61], _T_371 connect _WIRE[62], _T_377 connect _WIRE[63], _T_383 connect io.out.bits.mask, _WIRE node _io_out_bits_addr_total_bytes_sent_T = add(req.bits.spad_row_offset, bytesSent) node io_out_bits_addr_total_bytes_sent = tail(_io_out_bits_addr_total_bytes_sent_T, 1) node _io_out_bits_addr_T = div(io_out_bits_addr_total_bytes_sent, UInt<9>(0h40)) node _io_out_bits_addr_T_1 = div(io_out_bits_addr_total_bytes_sent, UInt<9>(0h10)) node _io_out_bits_addr_T_2 = mux(req.bits.has_acc_bitwidth, _io_out_bits_addr_T, _io_out_bits_addr_T_1) node _io_out_bits_addr_T_3 = mul(req.bits.block_stride, _io_out_bits_addr_T_2) node _io_out_bits_addr_T_4 = add(req.bits.addr, _io_out_bits_addr_T_3) node _io_out_bits_addr_T_5 = tail(_io_out_bits_addr_T_4, 1) connect io.out.bits.addr, _io_out_bits_addr_T_5 connect io.out.bits.is_acc, req.bits.is_acc connect io.out.bits.accumulate, req.bits.accumulate connect io.out.bits.has_acc_bitwidth, req.bits.has_acc_bitwidth connect io.out.bits.last, last_sending connect io.out.bits.accumulate, req.bits.accumulate connect io.out.bits.has_acc_bitwidth, req.bits.has_acc_bitwidth node _T_384 = dshl(UInt<1>(0h1), req.bits.lg_len_req) node _T_385 = eq(bytesRead, _T_384) node _T_386 = eq(bytesSent, req.bits.bytes_to_read) node _T_387 = and(_T_385, _T_386) when _T_387 : connect req.valid, UInt<1>(0h0) node _T_388 = and(io.out.ready, io.out.valid) when _T_388 : connect bytesSent, bytesSent_next node _T_389 = dshl(UInt<1>(0h1), req.bits.lg_len_req) node _T_390 = eq(bytesRead, _T_389) node _T_391 = and(last_sending, _T_390) when _T_391 : connect req.valid, UInt<1>(0h0) connect io.req.ready, UInt<1>(0h1) node _T_392 = and(io.req.ready, io.req.valid) when _T_392 : connect req.valid, UInt<1>(0h1) connect req.bits, io.req.bits connect bytesRead, UInt<1>(0h0) connect bytesSent, UInt<1>(0h0) node _T_393 = and(io.in.ready, io.in.valid) when _T_393 : node _current_bytesRead_T = and(io.req.ready, io.req.valid) node current_bytesRead = mux(_current_bytesRead_T, UInt<1>(0h0), bytesRead) node _current_bytesDiscarded_T = and(io.req.ready, io.req.valid) node current_bytesDiscarded = mux(_current_bytesDiscarded_T, UInt<1>(0h0), bytesDiscarded) node _current_usefulBytesRead_T = and(io.req.ready, io.req.valid) node current_usefulBytesRead = mux(_current_usefulBytesRead_T, UInt<1>(0h0), usefulBytesRead) node _current_shift_T = and(io.req.ready, io.req.valid) node current_shift = mux(_current_shift_T, io.req.bits.shift, req.bits.shift) node _current_lg_len_req_T = and(io.req.ready, io.req.valid) node current_lg_len_req = mux(_current_lg_len_req_T, io.req.bits.lg_len_req, req.bits.lg_len_req) node current_len_req = dshl(UInt<1>(0h1), current_lg_len_req) node _T_394 = sub(current_shift, current_bytesDiscarded) node _T_395 = tail(_T_394, 1) node _T_396 = leq(_T_395, UInt<5>(0h10)) when _T_396 : node _rshift_T = sub(current_shift, current_bytesDiscarded) node _rshift_T_1 = tail(_rshift_T, 1) node rshift = mul(_rshift_T_1, UInt<4>(0h8)) node lshift = mul(current_usefulBytesRead, UInt<4>(0h8)) node _mask_T = not(UInt<128>(0h0)) node _mask_T_1 = dshr(_mask_T, rshift) node _mask_T_2 = dshl(_mask_T_1, lshift) node mask = not(_mask_T_2) node _buffer_T = and(buffer, mask) node _buffer_T_1 = dshr(io.in.bits, rshift) node _buffer_T_2 = dshl(_buffer_T_1, lshift) node _buffer_T_3 = or(_buffer_T, _buffer_T_2) connect buffer, _buffer_T_3 node _bytesRead_T = add(current_bytesRead, UInt<5>(0h10)) node _bytesRead_T_1 = gt(_bytesRead_T, current_len_req) node _bytesRead_T_2 = add(current_bytesRead, UInt<5>(0h10)) node _bytesRead_T_3 = tail(_bytesRead_T_2, 1) node _bytesRead_T_4 = mux(_bytesRead_T_1, current_len_req, _bytesRead_T_3) connect bytesRead, _bytesRead_T_4 node _T_397 = and(io.req.ready, io.req.valid) node _T_398 = eq(_T_397, UInt<1>(0h0)) node _T_399 = eq(bytesSent, req.bits.bytes_to_read) node _T_400 = and(_T_398, _T_399) node _T_401 = and(_T_400, last_reading) when _T_401 : connect req.valid, UInt<1>(0h0) node _T_402 = asUInt(reset) when _T_402 : connect req.valid, UInt<1>(0h0)

module BeatMerger( // @[BeatMerger.scala:30:7] input clock, // @[BeatMerger.scala:30:7] input reset, // @[BeatMerger.scala:30:7] output io_req_ready, // @[BeatMerger.scala:33:14] input io_req_valid, // @[BeatMerger.scala:33:14] input [5:0] io_req_bits_shift, // @[BeatMerger.scala:33:14] input [13:0] io_req_bits_addr, // @[BeatMerger.scala:33:14] input io_req_bits_is_acc, // @[BeatMerger.scala:33:14] input io_req_bits_accumulate, // @[BeatMerger.scala:33:14] input io_req_bits_has_acc_bitwidth, // @[BeatMerger.scala:33:14] input [31:0] io_req_bits_scale, // @[BeatMerger.scala:33:14] input [15:0] io_req_bits_repeats, // @[BeatMerger.scala:33:14] input [7:0] io_req_bits_pixel_repeats, // @[BeatMerger.scala:33:14] input [15:0] io_req_bits_len, // @[BeatMerger.scala:33:14] input [15:0] io_req_bits_block_stride, // @[BeatMerger.scala:33:14] input [8:0] io_req_bits_spad_row_offset, // @[BeatMerger.scala:33:14] input [2:0] io_req_bits_lg_len_req, // @[BeatMerger.scala:33:14] input [6:0] io_req_bits_bytes_to_read, // @[BeatMerger.scala:33:14] input [2:0] io_req_bits_cmd_id, // @[BeatMerger.scala:33:14] output io_in_ready, // @[BeatMerger.scala:33:14] input io_in_valid, // @[BeatMerger.scala:33:14] input [127:0] io_in_bits, // @[BeatMerger.scala:33:14] input io_out_ready, // @[BeatMerger.scala:33:14] output io_out_valid, // @[BeatMerger.scala:33:14] output [511:0] io_out_bits_data, // @[BeatMerger.scala:33:14] output [13:0] io_out_bits_addr, // @[BeatMerger.scala:33:14] output io_out_bits_is_acc, // @[BeatMerger.scala:33:14] output io_out_bits_accumulate, // @[BeatMerger.scala:33:14] output io_out_bits_has_acc_bitwidth, // @[BeatMerger.scala:33:14] output io_out_bits_mask_0, // @[BeatMerger.scala:33:14] output io_out_bits_mask_1, // @[BeatMerger.scala:33:14] output io_out_bits_mask_2, // @[BeatMerger.scala:33:14] output io_out_bits_mask_3, // @[BeatMerger.scala:33:14] output io_out_bits_mask_4, // @[BeatMerger.scala:33:14] output io_out_bits_mask_5, // @[BeatMerger.scala:33:14] output io_out_bits_mask_6, // @[BeatMerger.scala:33:14] output io_out_bits_mask_7, // @[BeatMerger.scala:33:14] output io_out_bits_mask_8, // @[BeatMerger.scala:33:14] output io_out_bits_mask_9, // @[BeatMerger.scala:33:14] output io_out_bits_mask_10, // @[BeatMerger.scala:33:14] output io_out_bits_mask_11, // @[BeatMerger.scala:33:14] output io_out_bits_mask_12, // @[BeatMerger.scala:33:14] output io_out_bits_mask_13, // @[BeatMerger.scala:33:14] output io_out_bits_mask_14, // @[BeatMerger.scala:33:14] output io_out_bits_mask_15, // @[BeatMerger.scala:33:14] output io_out_bits_mask_16, // @[BeatMerger.scala:33:14] output io_out_bits_mask_17, // @[BeatMerger.scala:33:14] output io_out_bits_mask_18, // @[BeatMerger.scala:33:14] output io_out_bits_mask_19, // @[BeatMerger.scala:33:14] output io_out_bits_mask_20, // @[BeatMerger.scala:33:14] output io_out_bits_mask_21, // @[BeatMerger.scala:33:14] output io_out_bits_mask_22, // @[BeatMerger.scala:33:14] output io_out_bits_mask_23, // @[BeatMerger.scala:33:14] output io_out_bits_mask_24, // @[BeatMerger.scala:33:14] output io_out_bits_mask_25, // @[BeatMerger.scala:33:14] output io_out_bits_mask_26, // @[BeatMerger.scala:33:14] output io_out_bits_mask_27, // @[BeatMerger.scala:33:14] output io_out_bits_mask_28, // @[BeatMerger.scala:33:14] output io_out_bits_mask_29, // @[BeatMerger.scala:33:14] output io_out_bits_mask_30, // @[BeatMerger.scala:33:14] output io_out_bits_mask_31, // @[BeatMerger.scala:33:14] output io_out_bits_mask_32, // @[BeatMerger.scala:33:14] output io_out_bits_mask_33, // @[BeatMerger.scala:33:14] output io_out_bits_mask_34, // @[BeatMerger.scala:33:14] output io_out_bits_mask_35, // @[BeatMerger.scala:33:14] output io_out_bits_mask_36, // @[BeatMerger.scala:33:14] output io_out_bits_mask_37, // @[BeatMerger.scala:33:14] output io_out_bits_mask_38, // @[BeatMerger.scala:33:14] output io_out_bits_mask_39, // @[BeatMerger.scala:33:14] output io_out_bits_mask_40, // @[BeatMerger.scala:33:14] output io_out_bits_mask_41, // @[BeatMerger.scala:33:14] output io_out_bits_mask_42, // @[BeatMerger.scala:33:14] output io_out_bits_mask_43, // @[BeatMerger.scala:33:14] output io_out_bits_mask_44, // @[BeatMerger.scala:33:14] output io_out_bits_mask_45, // @[BeatMerger.scala:33:14] output io_out_bits_mask_46, // @[BeatMerger.scala:33:14] output io_out_bits_mask_47, // @[BeatMerger.scala:33:14] output io_out_bits_mask_48, // @[BeatMerger.scala:33:14] output io_out_bits_mask_49, // @[BeatMerger.scala:33:14] output io_out_bits_mask_50, // @[BeatMerger.scala:33:14] output io_out_bits_mask_51, // @[BeatMerger.scala:33:14] output io_out_bits_mask_52, // @[BeatMerger.scala:33:14] output io_out_bits_mask_53, // @[BeatMerger.scala:33:14] output io_out_bits_mask_54, // @[BeatMerger.scala:33:14] output io_out_bits_mask_55, // @[BeatMerger.scala:33:14] output io_out_bits_mask_56, // @[BeatMerger.scala:33:14] output io_out_bits_mask_57, // @[BeatMerger.scala:33:14] output io_out_bits_mask_58, // @[BeatMerger.scala:33:14] output io_out_bits_mask_59, // @[BeatMerger.scala:33:14] output io_out_bits_mask_60, // @[BeatMerger.scala:33:14] output io_out_bits_mask_61, // @[BeatMerger.scala:33:14] output io_out_bits_mask_62, // @[BeatMerger.scala:33:14] output io_out_bits_mask_63, // @[BeatMerger.scala:33:14] output io_out_bits_last // @[BeatMerger.scala:33:14] ); wire io_req_valid_0 = io_req_valid; // @[BeatMerger.scala:30:7] wire [5:0] io_req_bits_shift_0 = io_req_bits_shift; // @[BeatMerger.scala:30:7] wire [13:0] io_req_bits_addr_0 = io_req_bits_addr; // @[BeatMerger.scala:30:7] wire io_req_bits_is_acc_0 = io_req_bits_is_acc; // @[BeatMerger.scala:30:7] wire io_req_bits_accumulate_0 = io_req_bits_accumulate; // @[BeatMerger.scala:30:7] wire io_req_bits_has_acc_bitwidth_0 = io_req_bits_has_acc_bitwidth; // @[BeatMerger.scala:30:7] wire [31:0] io_req_bits_scale_0 = io_req_bits_scale; // @[BeatMerger.scala:30:7] wire [15:0] io_req_bits_repeats_0 = io_req_bits_repeats; // @[BeatMerger.scala:30:7] wire [7:0] io_req_bits_pixel_repeats_0 = io_req_bits_pixel_repeats; // @[BeatMerger.scala:30:7] wire [15:0] io_req_bits_len_0 = io_req_bits_len; // @[BeatMerger.scala:30:7] wire [15:0] io_req_bits_block_stride_0 = io_req_bits_block_stride; // @[BeatMerger.scala:30:7] wire [8:0] io_req_bits_spad_row_offset_0 = io_req_bits_spad_row_offset; // @[BeatMerger.scala:30:7] wire [2:0] io_req_bits_lg_len_req_0 = io_req_bits_lg_len_req; // @[BeatMerger.scala:30:7] wire [6:0] io_req_bits_bytes_to_read_0 = io_req_bits_bytes_to_read; // @[BeatMerger.scala:30:7] wire [2:0] io_req_bits_cmd_id_0 = io_req_bits_cmd_id; // @[BeatMerger.scala:30:7] wire io_in_valid_0 = io_in_valid; // @[BeatMerger.scala:30:7] wire [127:0] io_in_bits_0 = io_in_bits; // @[BeatMerger.scala:30:7] wire io_out_ready_0 = io_out_ready; // @[BeatMerger.scala:30:7] wire [127:0] _mask_T = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[BeatMerger.scala:126:23] wire _io_in_ready_T_4; // @[BeatMerger.scala:66:30] wire _io_out_valid_T_7; // @[BeatMerger.scala:68:60] wire last_sending; // @[BeatMerger.scala:61:37] wire io_req_ready_0; // @[BeatMerger.scala:30:7] wire io_in_ready_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_0_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_1_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_2_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_3_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_4_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_5_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_6_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_7_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_8_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_9_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_10_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_11_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_12_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_13_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_14_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_15_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_16_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_17_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_18_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_19_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_20_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_21_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_22_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_23_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_24_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_25_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_26_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_27_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_28_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_29_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_30_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_31_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_32_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_33_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_34_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_35_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_36_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_37_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_38_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_39_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_40_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_41_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_42_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_43_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_44_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_45_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_46_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_47_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_48_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_49_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_50_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_51_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_52_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_53_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_54_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_55_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_56_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_57_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_58_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_59_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_60_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_61_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_62_0; // @[BeatMerger.scala:30:7] wire io_out_bits_mask_63_0; // @[BeatMerger.scala:30:7] wire [511:0] io_out_bits_data_0; // @[BeatMerger.scala:30:7] wire [13:0] io_out_bits_addr_0; // @[BeatMerger.scala:30:7] wire io_out_bits_is_acc_0; // @[BeatMerger.scala:30:7] wire io_out_bits_accumulate_0; // @[BeatMerger.scala:30:7] wire io_out_bits_has_acc_bitwidth_0; // @[BeatMerger.scala:30:7] wire io_out_bits_last_0; // @[BeatMerger.scala:30:7] wire io_out_valid_0; // @[BeatMerger.scala:30:7] reg req_valid; // @[BeatMerger.scala:43:16] reg [5:0] req_bits_shift; // @[BeatMerger.scala:43:16] reg [13:0] req_bits_addr; // @[BeatMerger.scala:43:16] reg req_bits_is_acc; // @[BeatMerger.scala:43:16] assign io_out_bits_is_acc_0 = req_bits_is_acc; // @[BeatMerger.scala:30:7, :43:16] reg req_bits_accumulate; // @[BeatMerger.scala:43:16] assign io_out_bits_accumulate_0 = req_bits_accumulate; // @[BeatMerger.scala:30:7, :43:16] reg req_bits_has_acc_bitwidth; // @[BeatMerger.scala:43:16] assign io_out_bits_has_acc_bitwidth_0 = req_bits_has_acc_bitwidth; // @[BeatMerger.scala:30:7, :43:16] reg [31:0] req_bits_scale; // @[BeatMerger.scala:43:16] reg [15:0] req_bits_repeats; // @[BeatMerger.scala:43:16] reg [7:0] req_bits_pixel_repeats; // @[BeatMerger.scala:43:16] reg [15:0] req_bits_len; // @[BeatMerger.scala:43:16] reg [15:0] req_bits_block_stride; // @[BeatMerger.scala:43:16] reg [8:0] req_bits_spad_row_offset; // @[BeatMerger.scala:43:16] reg [2:0] req_bits_lg_len_req; // @[BeatMerger.scala:43:16] reg [6:0] req_bits_bytes_to_read; // @[BeatMerger.scala:43:16] reg [2:0] req_bits_cmd_id; // @[BeatMerger.scala:43:16] reg [511:0] buffer; // @[BeatMerger.scala:46:19] wire [6:0] rowBytes = req_bits_has_acc_bitwidth ? 7'h40 : 7'h10; // @[BeatMerger.scala:43:16, :48:21, :121:50] reg [6:0] bytesSent; // @[BeatMerger.scala:50:22] reg [6:0] bytesRead; // @[BeatMerger.scala:51:22] wire _bytesReadAfterShift_T = bytesRead > {1'h0, req_bits_shift}; // @[BeatMerger.scala:43:16, :51:22, :52:43] wire [7:0] _GEN = {1'h0, bytesRead}; // @[BeatMerger.scala:51:22, :52:71] wire [7:0] _bytesReadAfterShift_T_1 = _GEN - {2'h0, req_bits_shift}; // @[BeatMerger.scala:43:16, :52:71] wire [6:0] _bytesReadAfterShift_T_2 = _bytesReadAfterShift_T_1[6:0]; // @[BeatMerger.scala:52:71] wire [6:0] bytesReadAfterShift = _bytesReadAfterShift_T ? _bytesReadAfterShift_T_2 : 7'h0; // @[BeatMerger.scala:52:{32,43,71}] wire [7:0] _bytesDiscarded_T = _GEN - {1'h0, bytesReadAfterShift}; // @[BeatMerger.scala:52:{32,71}, :53:34] wire [6:0] bytesDiscarded = _bytesDiscarded_T[6:0]; // @[BeatMerger.scala:53:34] wire _usefulBytesRead_T = bytesReadAfterShift < req_bits_bytes_to_read; // @[Util.scala:109:12] wire [6:0] usefulBytesRead = _usefulBytesRead_T ? bytesReadAfterShift : req_bits_bytes_to_read; // @[Util.scala:109:{8,12}] wire _GEN_0 = bytesSent == 7'h0; // @[BeatMerger.scala:50:22, :57:41] wire _bytesSent_next_spad_row_offset_T; // @[BeatMerger.scala:57:41] assign _bytesSent_next_spad_row_offset_T = _GEN_0; // @[BeatMerger.scala:57:41] wire _io_out_bits_data_T_2; // @[BeatMerger.scala:70:70] assign _io_out_bits_data_T_2 = _GEN_0; // @[BeatMerger.scala:57:41, :70:70] wire _spad_row_offset_T; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_1; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_1 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_2; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_2 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_3; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_3 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_4; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_4 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_5; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_5 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_6; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_6 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_7; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_7 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_8; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_8 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_9; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_9 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_10; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_10 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_11; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_11 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_12; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_12 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_13; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_13 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_14; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_14 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_15; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_15 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_16; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_16 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_17; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_17 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_18; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_18 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_19; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_19 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_20; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_20 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_21; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_21 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_22; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_22 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_23; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_23 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_24; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_24 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_25; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_25 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_26; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_26 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_27; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_27 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_28; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_28 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_29; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_29 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_30; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_30 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_31; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_31 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_32; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_32 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_33; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_33 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_34; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_34 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_35; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_35 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_36; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_36 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_37; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_37 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_38; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_38 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_39; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_39 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_40; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_40 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_41; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_41 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_42; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_42 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_43; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_43 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_44; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_44 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_45; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_45 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_46; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_46 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_47; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_47 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_48; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_48 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_49; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_49 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_50; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_50 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_51; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_51 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_52; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_52 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_53; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_53 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_54; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_54 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_55; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_55 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_56; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_56 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_57; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_57 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_58; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_58 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_59; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_59 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_60; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_60 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_61; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_61 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_62; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_62 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire _spad_row_offset_T_63; // @[BeatMerger.scala:72:41] assign _spad_row_offset_T_63 = _GEN_0; // @[BeatMerger.scala:57:41, :72:41] wire [8:0] bytesSent_next_spad_row_offset = _bytesSent_next_spad_row_offset_T ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :57:{30,41}] wire [9:0] _bytesSent_next_T = {3'h0, rowBytes} - {1'h0, bytesSent_next_spad_row_offset}; // @[BeatMerger.scala:48:21, :57:30, :58:32] wire [8:0] _bytesSent_next_T_1 = _bytesSent_next_T[8:0]; // @[BeatMerger.scala:58:32] wire [9:0] _GEN_1 = {3'h0, bytesSent}; // @[Util.scala:35:11] wire [9:0] _GEN_2 = _GEN_1 + {1'h0, _bytesSent_next_T_1}; // @[Util.scala:35:11] wire [9:0] _bytesSent_next_T_2; // @[Util.scala:35:11] assign _bytesSent_next_T_2 = _GEN_2; // @[Util.scala:35:11] wire [9:0] _bytesSent_next_T_4; // @[Util.scala:35:30] assign _bytesSent_next_T_4 = _GEN_2; // @[Util.scala:35:{11,30}] wire _bytesSent_next_T_3 = _bytesSent_next_T_2 > {3'h0, req_bits_bytes_to_read}; // @[Util.scala:35:{11,16}] wire [8:0] _bytesSent_next_T_5 = _bytesSent_next_T_4[8:0]; // @[Util.scala:35:30] wire [8:0] _GEN_3 = {2'h0, req_bits_bytes_to_read}; // @[Util.scala:35:8] wire [8:0] bytesSent_next = _bytesSent_next_T_3 ? _GEN_3 : _bytesSent_next_T_5; // @[Util.scala:35:{8,16,30}] assign last_sending = bytesSent_next == _GEN_3; // @[Util.scala:35:8] assign io_out_bits_last_0 = last_sending; // @[BeatMerger.scala:30:7, :61:37] wire [7:0] _T_389 = 8'h1 << req_bits_lg_len_req; // @[BeatMerger.scala:43:16, :62:42] wire [7:0] _last_reading_T; // @[BeatMerger.scala:62:42] assign _last_reading_T = _T_389; // @[BeatMerger.scala:62:42] wire [7:0] _io_in_ready_T_1; // @[BeatMerger.scala:66:66] assign _io_in_ready_T_1 = _T_389; // @[BeatMerger.scala:62:42, :66:66] wire [8:0] _last_reading_T_1 = {1'h0, _last_reading_T} - {2'h0, bytesRead}; // @[BeatMerger.scala:51:22, :52:71, :62:{42,73}] wire [7:0] _last_reading_T_2 = _last_reading_T_1[7:0]; // @[BeatMerger.scala:62:73] wire last_reading = _last_reading_T_2 < 8'h11; // @[BeatMerger.scala:62:{34,73}] wire _io_req_ready_T = ~req_valid; // @[BeatMerger.scala:43:16, :64:19] wire _T_397 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire _io_in_ready_T; // @[Decoupled.scala:51:35] assign _io_in_ready_T = _T_397; // @[Decoupled.scala:51:35] wire _current_bytesRead_T; // @[Decoupled.scala:51:35] assign _current_bytesRead_T = _T_397; // @[Decoupled.scala:51:35] wire _current_bytesDiscarded_T; // @[Decoupled.scala:51:35] assign _current_bytesDiscarded_T = _T_397; // @[Decoupled.scala:51:35] wire _current_usefulBytesRead_T; // @[Decoupled.scala:51:35] assign _current_usefulBytesRead_T = _T_397; // @[Decoupled.scala:51:35] wire _current_shift_T; // @[Decoupled.scala:51:35] assign _current_shift_T = _T_397; // @[Decoupled.scala:51:35] wire _current_lg_len_req_T; // @[Decoupled.scala:51:35] assign _current_lg_len_req_T = _T_397; // @[Decoupled.scala:51:35] wire _io_in_ready_T_2 = _GEN != _io_in_ready_T_1; // @[BeatMerger.scala:52:71, :66:{57,66}] wire _io_in_ready_T_3 = req_valid & _io_in_ready_T_2; // @[BeatMerger.scala:43:16, :66:{44,57}] assign _io_in_ready_T_4 = _io_in_ready_T | _io_in_ready_T_3; // @[Decoupled.scala:51:35] assign io_in_ready_0 = _io_in_ready_T_4; // @[BeatMerger.scala:30:7, :66:30] wire _io_out_valid_T = usefulBytesRead > bytesSent; // @[Util.scala:109:8] wire _io_out_valid_T_1 = req_valid & _io_out_valid_T; // @[BeatMerger.scala:43:16, :68:{29,48}] wire [7:0] _io_out_valid_T_2 = {1'h0, usefulBytesRead} - {1'h0, bytesSent}; // @[Util.scala:109:8] wire [6:0] _io_out_valid_T_3 = _io_out_valid_T_2[6:0]; // @[BeatMerger.scala:68:80] wire _io_out_valid_T_4 = _io_out_valid_T_3 >= rowBytes; // @[BeatMerger.scala:48:21, :68:{80,92}] wire _io_out_valid_T_5 = usefulBytesRead == req_bits_bytes_to_read; // @[Util.scala:109:8] wire _io_out_valid_T_6 = _io_out_valid_T_4 | _io_out_valid_T_5; // @[BeatMerger.scala:68:{92,104}, :69:21] assign _io_out_valid_T_7 = _io_out_valid_T_1 & _io_out_valid_T_6; // @[BeatMerger.scala:68:{29,60,104}] assign io_out_valid_0 = _io_out_valid_T_7; // @[BeatMerger.scala:30:7, :68:60] wire [10:0] _io_out_bits_data_T = {1'h0, bytesSent, 3'h0}; // @[BeatMerger.scala:50:22, :70:45] wire [511:0] _io_out_bits_data_T_1 = buffer >> _io_out_bits_data_T; // @[BeatMerger.scala:46:19, :70:{31,45}] wire [12:0] _io_out_bits_data_T_3 = {1'h0, req_bits_spad_row_offset, 3'h0}; // @[BeatMerger.scala:43:16, :70:104] wire [12:0] _io_out_bits_data_T_4 = _io_out_bits_data_T_2 ? _io_out_bits_data_T_3 : 13'h0; // @[BeatMerger.scala:70:{59,70,104}] wire [8702:0] _io_out_bits_data_T_5 = {8191'h0, _io_out_bits_data_T_1} << _io_out_bits_data_T_4; // @[BeatMerger.scala:70:{31,53,59}] assign io_out_bits_data_0 = _io_out_bits_data_T_5[511:0]; // @[BeatMerger.scala:30:7, :70:{20,53}] wire [8:0] spad_row_offset = _spad_row_offset_T ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _GEN_4 = {3'h0, req_bits_bytes_to_read - bytesSent}; // @[BeatMerger.scala:43:16, :50:22, :74:{29,56}] assign io_out_bits_mask_0_0 = spad_row_offset == 9'h0 & (|({1'h0, spad_row_offset} + _GEN_4)); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_1 = _spad_row_offset_T_1 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_9 = {1'h0, spad_row_offset_1} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_1_0 = spad_row_offset_1 < 9'h2 & (|(_T_9[9:1])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_2 = _spad_row_offset_T_2 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_2_0 = spad_row_offset_2 < 9'h3 & {1'h0, spad_row_offset_2} + _GEN_4 > 10'h2; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_3 = _spad_row_offset_T_3 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_21 = {1'h0, spad_row_offset_3} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_3_0 = spad_row_offset_3 < 9'h4 & (|(_T_21[9:2])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_4 = _spad_row_offset_T_4 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_4_0 = spad_row_offset_4 < 9'h5 & {1'h0, spad_row_offset_4} + _GEN_4 > 10'h4; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_5 = _spad_row_offset_T_5 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_5_0 = spad_row_offset_5 < 9'h6 & {1'h0, spad_row_offset_5} + _GEN_4 > 10'h5; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_6 = _spad_row_offset_T_6 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_6_0 = spad_row_offset_6 < 9'h7 & {1'h0, spad_row_offset_6} + _GEN_4 > 10'h6; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_7 = _spad_row_offset_T_7 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_45 = {1'h0, spad_row_offset_7} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_7_0 = spad_row_offset_7 < 9'h8 & (|(_T_45[9:3])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_8 = _spad_row_offset_T_8 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_8_0 = spad_row_offset_8 < 9'h9 & {1'h0, spad_row_offset_8} + _GEN_4 > 10'h8; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_9 = _spad_row_offset_T_9 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_9_0 = spad_row_offset_9 < 9'hA & {1'h0, spad_row_offset_9} + _GEN_4 > 10'h9; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_10 = _spad_row_offset_T_10 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_10_0 = spad_row_offset_10 < 9'hB & {1'h0, spad_row_offset_10} + _GEN_4 > 10'hA; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_11 = _spad_row_offset_T_11 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_11_0 = spad_row_offset_11 < 9'hC & {1'h0, spad_row_offset_11} + _GEN_4 > 10'hB; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_12 = _spad_row_offset_T_12 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_12_0 = spad_row_offset_12 < 9'hD & {1'h0, spad_row_offset_12} + _GEN_4 > 10'hC; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_13 = _spad_row_offset_T_13 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_13_0 = spad_row_offset_13 < 9'hE & {1'h0, spad_row_offset_13} + _GEN_4 > 10'hD; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_14 = _spad_row_offset_T_14 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_14_0 = spad_row_offset_14 < 9'hF & {1'h0, spad_row_offset_14} + _GEN_4 > 10'hE; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_15 = _spad_row_offset_T_15 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_93 = {1'h0, spad_row_offset_15} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_15_0 = spad_row_offset_15 < 9'h10 & (|(_T_93[9:4])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_16 = _spad_row_offset_T_16 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_16_0 = spad_row_offset_16 < 9'h11 & {1'h0, spad_row_offset_16} + _GEN_4 > 10'h10; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_17 = _spad_row_offset_T_17 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_17_0 = spad_row_offset_17 < 9'h12 & {1'h0, spad_row_offset_17} + _GEN_4 > 10'h11; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_18 = _spad_row_offset_T_18 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_18_0 = spad_row_offset_18 < 9'h13 & {1'h0, spad_row_offset_18} + _GEN_4 > 10'h12; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_19 = _spad_row_offset_T_19 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_19_0 = spad_row_offset_19 < 9'h14 & {1'h0, spad_row_offset_19} + _GEN_4 > 10'h13; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_20 = _spad_row_offset_T_20 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_20_0 = spad_row_offset_20 < 9'h15 & {1'h0, spad_row_offset_20} + _GEN_4 > 10'h14; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_21 = _spad_row_offset_T_21 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_21_0 = spad_row_offset_21 < 9'h16 & {1'h0, spad_row_offset_21} + _GEN_4 > 10'h15; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_22 = _spad_row_offset_T_22 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_22_0 = spad_row_offset_22 < 9'h17 & {1'h0, spad_row_offset_22} + _GEN_4 > 10'h16; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_23 = _spad_row_offset_T_23 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_23_0 = spad_row_offset_23 < 9'h18 & {1'h0, spad_row_offset_23} + _GEN_4 > 10'h17; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_24 = _spad_row_offset_T_24 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_24_0 = spad_row_offset_24 < 9'h19 & {1'h0, spad_row_offset_24} + _GEN_4 > 10'h18; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_25 = _spad_row_offset_T_25 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_25_0 = spad_row_offset_25 < 9'h1A & {1'h0, spad_row_offset_25} + _GEN_4 > 10'h19; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_26 = _spad_row_offset_T_26 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_26_0 = spad_row_offset_26 < 9'h1B & {1'h0, spad_row_offset_26} + _GEN_4 > 10'h1A; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_27 = _spad_row_offset_T_27 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_27_0 = spad_row_offset_27 < 9'h1C & {1'h0, spad_row_offset_27} + _GEN_4 > 10'h1B; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_28 = _spad_row_offset_T_28 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_28_0 = spad_row_offset_28 < 9'h1D & {1'h0, spad_row_offset_28} + _GEN_4 > 10'h1C; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_29 = _spad_row_offset_T_29 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_29_0 = spad_row_offset_29 < 9'h1E & {1'h0, spad_row_offset_29} + _GEN_4 > 10'h1D; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_30 = _spad_row_offset_T_30 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_30_0 = spad_row_offset_30 < 9'h1F & {1'h0, spad_row_offset_30} + _GEN_4 > 10'h1E; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_31 = _spad_row_offset_T_31 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_189 = {1'h0, spad_row_offset_31} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_31_0 = spad_row_offset_31 < 9'h20 & (|(_T_189[9:5])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_32 = _spad_row_offset_T_32 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_32_0 = spad_row_offset_32 < 9'h21 & {1'h0, spad_row_offset_32} + _GEN_4 > 10'h20; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_33 = _spad_row_offset_T_33 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_33_0 = spad_row_offset_33 < 9'h22 & {1'h0, spad_row_offset_33} + _GEN_4 > 10'h21; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_34 = _spad_row_offset_T_34 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_34_0 = spad_row_offset_34 < 9'h23 & {1'h0, spad_row_offset_34} + _GEN_4 > 10'h22; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_35 = _spad_row_offset_T_35 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_35_0 = spad_row_offset_35 < 9'h24 & {1'h0, spad_row_offset_35} + _GEN_4 > 10'h23; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_36 = _spad_row_offset_T_36 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_36_0 = spad_row_offset_36 < 9'h25 & {1'h0, spad_row_offset_36} + _GEN_4 > 10'h24; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_37 = _spad_row_offset_T_37 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_37_0 = spad_row_offset_37 < 9'h26 & {1'h0, spad_row_offset_37} + _GEN_4 > 10'h25; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_38 = _spad_row_offset_T_38 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_38_0 = spad_row_offset_38 < 9'h27 & {1'h0, spad_row_offset_38} + _GEN_4 > 10'h26; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_39 = _spad_row_offset_T_39 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_39_0 = spad_row_offset_39 < 9'h28 & {1'h0, spad_row_offset_39} + _GEN_4 > 10'h27; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_40 = _spad_row_offset_T_40 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_40_0 = spad_row_offset_40 < 9'h29 & {1'h0, spad_row_offset_40} + _GEN_4 > 10'h28; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_41 = _spad_row_offset_T_41 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_41_0 = spad_row_offset_41 < 9'h2A & {1'h0, spad_row_offset_41} + _GEN_4 > 10'h29; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_42 = _spad_row_offset_T_42 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_42_0 = spad_row_offset_42 < 9'h2B & {1'h0, spad_row_offset_42} + _GEN_4 > 10'h2A; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_43 = _spad_row_offset_T_43 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_43_0 = spad_row_offset_43 < 9'h2C & {1'h0, spad_row_offset_43} + _GEN_4 > 10'h2B; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_44 = _spad_row_offset_T_44 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_44_0 = spad_row_offset_44 < 9'h2D & {1'h0, spad_row_offset_44} + _GEN_4 > 10'h2C; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_45 = _spad_row_offset_T_45 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_45_0 = spad_row_offset_45 < 9'h2E & {1'h0, spad_row_offset_45} + _GEN_4 > 10'h2D; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_46 = _spad_row_offset_T_46 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_46_0 = spad_row_offset_46 < 9'h2F & {1'h0, spad_row_offset_46} + _GEN_4 > 10'h2E; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_47 = _spad_row_offset_T_47 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_47_0 = spad_row_offset_47 < 9'h30 & {1'h0, spad_row_offset_47} + _GEN_4 > 10'h2F; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_48 = _spad_row_offset_T_48 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_48_0 = spad_row_offset_48 < 9'h31 & {1'h0, spad_row_offset_48} + _GEN_4 > 10'h30; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_49 = _spad_row_offset_T_49 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_49_0 = spad_row_offset_49 < 9'h32 & {1'h0, spad_row_offset_49} + _GEN_4 > 10'h31; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_50 = _spad_row_offset_T_50 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_50_0 = spad_row_offset_50 < 9'h33 & {1'h0, spad_row_offset_50} + _GEN_4 > 10'h32; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_51 = _spad_row_offset_T_51 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_51_0 = spad_row_offset_51 < 9'h34 & {1'h0, spad_row_offset_51} + _GEN_4 > 10'h33; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_52 = _spad_row_offset_T_52 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_52_0 = spad_row_offset_52 < 9'h35 & {1'h0, spad_row_offset_52} + _GEN_4 > 10'h34; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_53 = _spad_row_offset_T_53 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_53_0 = spad_row_offset_53 < 9'h36 & {1'h0, spad_row_offset_53} + _GEN_4 > 10'h35; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_54 = _spad_row_offset_T_54 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_54_0 = spad_row_offset_54 < 9'h37 & {1'h0, spad_row_offset_54} + _GEN_4 > 10'h36; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_55 = _spad_row_offset_T_55 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_55_0 = spad_row_offset_55 < 9'h38 & {1'h0, spad_row_offset_55} + _GEN_4 > 10'h37; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_56 = _spad_row_offset_T_56 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_56_0 = spad_row_offset_56 < 9'h39 & {1'h0, spad_row_offset_56} + _GEN_4 > 10'h38; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_57 = _spad_row_offset_T_57 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_57_0 = spad_row_offset_57 < 9'h3A & {1'h0, spad_row_offset_57} + _GEN_4 > 10'h39; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_58 = _spad_row_offset_T_58 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_58_0 = spad_row_offset_58 < 9'h3B & {1'h0, spad_row_offset_58} + _GEN_4 > 10'h3A; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_59 = _spad_row_offset_T_59 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_59_0 = spad_row_offset_59 < 9'h3C & {1'h0, spad_row_offset_59} + _GEN_4 > 10'h3B; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_60 = _spad_row_offset_T_60 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_60_0 = spad_row_offset_60 < 9'h3D & {1'h0, spad_row_offset_60} + _GEN_4 > 10'h3C; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_61 = _spad_row_offset_T_61 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_61_0 = spad_row_offset_61 < 9'h3E & {1'h0, spad_row_offset_61} + _GEN_4 > 10'h3D; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_62 = _spad_row_offset_T_62 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] assign io_out_bits_mask_62_0 = spad_row_offset_62 < 9'h3F & {1'h0, spad_row_offset_62} + _GEN_4 > 10'h3E; // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [8:0] spad_row_offset_63 = _spad_row_offset_T_63 ? req_bits_spad_row_offset : 9'h0; // @[BeatMerger.scala:43:16, :72:{30,41}] wire [9:0] _T_381 = {1'h0, spad_row_offset_63} + _GEN_4; // @[BeatMerger.scala:72:30, :74:29] assign io_out_bits_mask_63_0 = spad_row_offset_63 < 9'h40 & (|(_T_381[9:6])); // @[BeatMerger.scala:30:7, :72:30, :73:{9,28}, :74:{11,29}] wire [9:0] _io_out_bits_addr_total_bytes_sent_T = {1'h0, req_bits_spad_row_offset} + _GEN_1; // @[Util.scala:35:11] wire [8:0] io_out_bits_addr_total_bytes_sent = _io_out_bits_addr_total_bytes_sent_T[8:0]; // @[BeatMerger.scala:77:53] wire [8:0] _io_out_bits_addr_T = io_out_bits_addr_total_bytes_sent / 9'h40; // @[BeatMerger.scala:77:53, :82:84] wire [8:0] _io_out_bits_addr_T_1 = io_out_bits_addr_total_bytes_sent / 9'h10; // @[BeatMerger.scala:77:53, :83:85] wire [8:0] _io_out_bits_addr_T_2 = req_bits_has_acc_bitwidth ? _io_out_bits_addr_T : _io_out_bits_addr_T_1; // @[BeatMerger.scala:43:16, :78:8, :82:84, :83:85] wire [24:0] _io_out_bits_addr_T_3 = {9'h0, req_bits_block_stride} * {16'h0, _io_out_bits_addr_T_2}; // @[BeatMerger.scala:43:16, :76:61, :78:8] wire [25:0] _io_out_bits_addr_T_4 = {12'h0, req_bits_addr} + {1'h0, _io_out_bits_addr_T_3}; // @[BeatMerger.scala:43:16, :76:{37,61}] wire [24:0] _io_out_bits_addr_T_5 = _io_out_bits_addr_T_4[24:0]; // @[BeatMerger.scala:76:37] assign io_out_bits_addr_0 = _io_out_bits_addr_T_5[13:0]; // @[BeatMerger.scala:30:7, :76:{20,37}] wire _T_388 = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] wire _T_391 = last_sending & _GEN == _T_389; // @[BeatMerger.scala:52:71, :61:37, :62:42, :101:{24,37}] assign io_req_ready_0 = _T_388 & _T_391 | _io_req_ready_T; // @[Decoupled.scala:51:35] wire [6:0] current_bytesRead = _current_bytesRead_T ? 7'h0 : bytesRead; // @[Decoupled.scala:51:35] wire [6:0] current_bytesDiscarded = _current_bytesDiscarded_T ? 7'h0 : bytesDiscarded; // @[Decoupled.scala:51:35] wire [6:0] current_usefulBytesRead = _current_usefulBytesRead_T ? 7'h0 : usefulBytesRead; // @[Decoupled.scala:51:35] wire [5:0] current_shift = _current_shift_T ? io_req_bits_shift_0 : req_bits_shift; // @[Decoupled.scala:51:35] wire [2:0] current_lg_len_req = _current_lg_len_req_T ? io_req_bits_lg_len_req_0 : req_bits_lg_len_req; // @[Decoupled.scala:51:35] wire [7:0] current_len_req = 8'h1 << current_lg_len_req; // @[BeatMerger.scala:118:33, :119:32] wire [7:0] _rshift_T = {2'h0, current_shift} - {1'h0, current_bytesDiscarded}; // @[BeatMerger.scala:52:71, :115:37, :117:28, :121:25, :124:35] wire [6:0] _rshift_T_1 = _rshift_T[6:0]; // @[BeatMerger.scala:124:35] wire [10:0] rshift = {1'h0, _rshift_T_1, 3'h0}; // @[BeatMerger.scala:124:{35,61}] wire [10:0] lshift = {1'h0, current_usefulBytesRead, 3'h0}; // @[BeatMerger.scala:116:38, :125:44] wire [127:0] _GEN_5 = {117'h0, rshift}; // @[BeatMerger.scala:124:61, :126:41] wire [127:0] _mask_T_1 = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF >> _GEN_5; // @[BeatMerger.scala:126:41] wire [2174:0] _GEN_6 = {2164'h0, lshift}; // @[BeatMerger.scala:125:44, :126:52] wire [2174:0] _mask_T_2 = {2047'h0, _mask_T_1} << _GEN_6; // @[BeatMerger.scala:126:{41,52}] wire [2174:0] mask = ~_mask_T_2; // @[BeatMerger.scala:126:{19,52}] wire [2174:0] _buffer_T = {1663'h0, mask[511:0] & buffer}; // @[BeatMerger.scala:46:19, :126:19, :128:25] wire [127:0] _buffer_T_1 = io_in_bits_0 >> _GEN_5; // @[BeatMerger.scala:30:7, :126:41, :128:48] wire [2174:0] _buffer_T_2 = {2047'h0, _buffer_T_1} << _GEN_6; // @[BeatMerger.scala:126:52, :128:{48,59}] wire [2174:0] _buffer_T_3 = _buffer_T | _buffer_T_2; // @[BeatMerger.scala:128:{25,33,59}] wire [7:0] _GEN_7 = {1'h0, current_bytesRead} + 8'h10; // @[Util.scala:35:11] wire [7:0] _bytesRead_T; // @[Util.scala:35:11] assign _bytesRead_T = _GEN_7; // @[Util.scala:35:11] wire [7:0] _bytesRead_T_2; // @[Util.scala:35:30] assign _bytesRead_T_2 = _GEN_7; // @[Util.scala:35:{11,30}] wire _bytesRead_T_1 = _bytesRead_T > current_len_req; // @[Util.scala:35:{11,16}] wire [6:0] _bytesRead_T_3 = _bytesRead_T_2[6:0]; // @[Util.scala:35:30] wire [7:0] _bytesRead_T_4 = _bytesRead_T_1 ? current_len_req : {1'h0, _bytesRead_T_3}; // @[Util.scala:35:{8,16,30}] wire _T_399 = bytesSent == req_bits_bytes_to_read; // @[BeatMerger.scala:43:16, :50:22, :94:15] wire _T_387 = _GEN == _T_389 & _T_399; // @[BeatMerger.scala:52:71, :62:42, :93:{19,59}, :94:15] wire _T_393 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[BeatMerger.scala:30:7] req_valid <= ~(reset | _T_393 & ~_T_397 & _T_399 & last_reading) & (_T_397 | (_T_388 ? ~(_T_391 | _T_387) & req_valid : ~_T_387 & req_valid)); // @[Decoupled.scala:51:35] if (_T_397) begin // @[Decoupled.scala:51:35] req_bits_shift <= io_req_bits_shift_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_addr <= io_req_bits_addr_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_is_acc <= io_req_bits_is_acc_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_accumulate <= io_req_bits_accumulate_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_has_acc_bitwidth <= io_req_bits_has_acc_bitwidth_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_scale <= io_req_bits_scale_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_repeats <= io_req_bits_repeats_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_pixel_repeats <= io_req_bits_pixel_repeats_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_len <= io_req_bits_len_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_block_stride <= io_req_bits_block_stride_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_spad_row_offset <= io_req_bits_spad_row_offset_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_lg_len_req <= io_req_bits_lg_len_req_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_bytes_to_read <= io_req_bits_bytes_to_read_0; // @[BeatMerger.scala:30:7, :43:16] req_bits_cmd_id <= io_req_bits_cmd_id_0; // @[BeatMerger.scala:30:7, :43:16] bytesSent <= 7'h0; // @[BeatMerger.scala:50:22] end else if (_T_388) // @[Decoupled.scala:51:35] bytesSent <= bytesSent_next[6:0]; // @[Util.scala:35:8] if (_T_393 & _rshift_T[6:0] < 7'h11) // @[Decoupled.scala:51:35] buffer <= _buffer_T_3[511:0]; // @[BeatMerger.scala:46:19, :128:{14,33}] if (_T_393) // @[Decoupled.scala:51:35] bytesRead <= _bytesRead_T_4[6:0]; // @[Util.scala:35:8] else if (_T_397) // @[Decoupled.scala:51:35] bytesRead <= 7'h0; // @[BeatMerger.scala:51:22] always @(posedge) assign io_req_ready = io_req_ready_0; // @[BeatMerger.scala:30:7] assign io_in_ready = io_in_ready_0; // @[BeatMerger.scala:30:7] assign io_out_valid = io_out_valid_0; // @[BeatMerger.scala:30:7] assign io_out_bits_data = io_out_bits_data_0; // @[BeatMerger.scala:30:7] assign io_out_bits_addr = io_out_bits_addr_0; // @[BeatMerger.scala:30:7] assign io_out_bits_is_acc = io_out_bits_is_acc_0; // @[BeatMerger.scala:30:7] assign io_out_bits_accumulate = io_out_bits_accumulate_0; // @[BeatMerger.scala:30:7] assign io_out_bits_has_acc_bitwidth = io_out_bits_has_acc_bitwidth_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_0 = io_out_bits_mask_0_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_1 = io_out_bits_mask_1_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_2 = io_out_bits_mask_2_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_3 = io_out_bits_mask_3_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_4 = io_out_bits_mask_4_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_5 = io_out_bits_mask_5_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_6 = io_out_bits_mask_6_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_7 = io_out_bits_mask_7_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_8 = io_out_bits_mask_8_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_9 = io_out_bits_mask_9_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_10 = io_out_bits_mask_10_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_11 = io_out_bits_mask_11_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_12 = io_out_bits_mask_12_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_13 = io_out_bits_mask_13_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_14 = io_out_bits_mask_14_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_15 = io_out_bits_mask_15_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_16 = io_out_bits_mask_16_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_17 = io_out_bits_mask_17_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_18 = io_out_bits_mask_18_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_19 = io_out_bits_mask_19_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_20 = io_out_bits_mask_20_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_21 = io_out_bits_mask_21_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_22 = io_out_bits_mask_22_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_23 = io_out_bits_mask_23_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_24 = io_out_bits_mask_24_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_25 = io_out_bits_mask_25_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_26 = io_out_bits_mask_26_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_27 = io_out_bits_mask_27_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_28 = io_out_bits_mask_28_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_29 = io_out_bits_mask_29_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_30 = io_out_bits_mask_30_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_31 = io_out_bits_mask_31_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_32 = io_out_bits_mask_32_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_33 = io_out_bits_mask_33_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_34 = io_out_bits_mask_34_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_35 = io_out_bits_mask_35_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_36 = io_out_bits_mask_36_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_37 = io_out_bits_mask_37_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_38 = io_out_bits_mask_38_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_39 = io_out_bits_mask_39_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_40 = io_out_bits_mask_40_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_41 = io_out_bits_mask_41_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_42 = io_out_bits_mask_42_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_43 = io_out_bits_mask_43_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_44 = io_out_bits_mask_44_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_45 = io_out_bits_mask_45_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_46 = io_out_bits_mask_46_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_47 = io_out_bits_mask_47_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_48 = io_out_bits_mask_48_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_49 = io_out_bits_mask_49_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_50 = io_out_bits_mask_50_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_51 = io_out_bits_mask_51_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_52 = io_out_bits_mask_52_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_53 = io_out_bits_mask_53_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_54 = io_out_bits_mask_54_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_55 = io_out_bits_mask_55_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_56 = io_out_bits_mask_56_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_57 = io_out_bits_mask_57_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_58 = io_out_bits_mask_58_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_59 = io_out_bits_mask_59_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_60 = io_out_bits_mask_60_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_61 = io_out_bits_mask_61_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_62 = io_out_bits_mask_62_0; // @[BeatMerger.scala:30:7] assign io_out_bits_mask_63 = io_out_bits_mask_63_0; // @[BeatMerger.scala:30:7] assign io_out_bits_last = io_out_bits_last_0; // @[BeatMerger.scala:30:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLDFromBeat_SerialRAM_a64d64s8k8z8c : input clock : Clock input reset : Reset output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip beat : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<65>, head : UInt<1>, tail : UInt<1>}}} wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect io.protocol, protocol regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1) reg const_reg : UInt<30>, clock node const = mux(io.beat.bits.head, io.beat.bits.payload, const_reg) node _io_beat_ready_T = eq(io.beat.bits.tail, UInt<1>(0h0)) node _io_beat_ready_T_1 = and(is_const, _io_beat_ready_T) node _io_beat_ready_T_2 = or(_io_beat_ready_T_1, protocol.ready) connect io.beat.ready, _io_beat_ready_T_2 node _protocol_valid_T = eq(is_const, UInt<1>(0h0)) node _protocol_valid_T_1 = or(_protocol_valid_T, io.beat.bits.tail) node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.beat.valid) connect protocol.valid, _protocol_valid_T_2 wire _protocol_bits_denied_WIRE : UInt<1> connect _protocol_bits_denied_WIRE, const connect protocol.bits.denied, _protocol_bits_denied_WIRE node _T = shr(const, 1) wire _protocol_bits_sink_WIRE : UInt<8> connect _protocol_bits_sink_WIRE, _T connect protocol.bits.sink, _protocol_bits_sink_WIRE node _T_1 = shr(_T, 8) wire _protocol_bits_echo_WIRE : { } wire _protocol_bits_echo_WIRE_1 : UInt<0> connect _protocol_bits_echo_WIRE_1, _T_1 connect protocol.bits.echo, _protocol_bits_echo_WIRE node _T_2 = shr(_T_1, 0) wire _protocol_bits_user_WIRE : { } wire _protocol_bits_user_WIRE_1 : UInt<0> connect _protocol_bits_user_WIRE_1, _T_2 connect protocol.bits.user, _protocol_bits_user_WIRE node _T_3 = shr(_T_2, 0) wire _protocol_bits_source_WIRE : UInt<8> connect _protocol_bits_source_WIRE, _T_3 connect protocol.bits.source, _protocol_bits_source_WIRE node _T_4 = shr(_T_3, 8) wire _protocol_bits_size_WIRE : UInt<8> connect _protocol_bits_size_WIRE, _T_4 connect protocol.bits.size, _protocol_bits_size_WIRE node _T_5 = shr(_T_4, 8) wire _protocol_bits_param_WIRE : UInt<2> connect _protocol_bits_param_WIRE, _T_5 connect protocol.bits.param, _protocol_bits_param_WIRE node _T_6 = shr(_T_5, 2) wire _protocol_bits_opcode_WIRE : UInt<3> connect _protocol_bits_opcode_WIRE, _T_6 connect protocol.bits.opcode, _protocol_bits_opcode_WIRE node _T_7 = shr(_T_6, 3) wire _protocol_bits_corrupt_WIRE : UInt<1> connect _protocol_bits_corrupt_WIRE, io.beat.bits.payload connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE node _T_8 = shr(io.beat.bits.payload, 1) wire _protocol_bits_data_WIRE : UInt<64> connect _protocol_bits_data_WIRE, _T_8 connect protocol.bits.data, _protocol_bits_data_WIRE node _T_9 = shr(_T_8, 64) node _T_10 = and(io.beat.ready, io.beat.valid) node _T_11 = and(_T_10, io.beat.bits.head) when _T_11 : connect is_const, UInt<1>(0h0) connect const_reg, io.beat.bits.payload node _T_12 = and(io.beat.ready, io.beat.valid) node _T_13 = and(_T_12, io.beat.bits.tail) when _T_13 : connect is_const, UInt<1>(0h1)

module TLDFromBeat_SerialRAM_a64d64s8k8z8c( // @[TLChannelCompactor.scala:134:7] input clock, // @[TLChannelCompactor.scala:134:7] input reset, // @[TLChannelCompactor.scala:134:7] input io_protocol_ready, // @[TLChannelCompactor.scala:75:14] output io_protocol_valid, // @[TLChannelCompactor.scala:75:14] output [2:0] io_protocol_bits_opcode, // @[TLChannelCompactor.scala:75:14] output [1:0] io_protocol_bits_param, // @[TLChannelCompactor.scala:75:14] output [7:0] io_protocol_bits_size, // @[TLChannelCompactor.scala:75:14] output [7:0] io_protocol_bits_source, // @[TLChannelCompactor.scala:75:14] output [7:0] io_protocol_bits_sink, // @[TLChannelCompactor.scala:75:14] output io_protocol_bits_denied, // @[TLChannelCompactor.scala:75:14] output [63:0] io_protocol_bits_data, // @[TLChannelCompactor.scala:75:14] output io_protocol_bits_corrupt, // @[TLChannelCompactor.scala:75:14] output io_beat_ready, // @[TLChannelCompactor.scala:75:14] input io_beat_valid, // @[TLChannelCompactor.scala:75:14] input [64:0] io_beat_bits_payload, // @[TLChannelCompactor.scala:75:14] input io_beat_bits_head, // @[TLChannelCompactor.scala:75:14] input io_beat_bits_tail // @[TLChannelCompactor.scala:75:14] ); wire io_protocol_ready_0 = io_protocol_ready; // @[TLChannelCompactor.scala:134:7] wire io_beat_valid_0 = io_beat_valid; // @[TLChannelCompactor.scala:134:7] wire [64:0] io_beat_bits_payload_0 = io_beat_bits_payload; // @[TLChannelCompactor.scala:134:7] wire io_beat_bits_head_0 = io_beat_bits_head; // @[TLChannelCompactor.scala:134:7] wire io_beat_bits_tail_0 = io_beat_bits_tail; // @[TLChannelCompactor.scala:134:7] wire protocol_ready = io_protocol_ready_0; // @[TLChannelCompactor.scala:83:22, :134:7] wire protocol_valid; // @[TLChannelCompactor.scala:83:22] wire [2:0] protocol_bits_opcode; // @[TLChannelCompactor.scala:83:22] wire [1:0] protocol_bits_param; // @[TLChannelCompactor.scala:83:22] wire [7:0] protocol_bits_size; // @[TLChannelCompactor.scala:83:22] wire [7:0] protocol_bits_source; // @[TLChannelCompactor.scala:83:22] wire [7:0] protocol_bits_sink; // @[TLChannelCompactor.scala:83:22] wire protocol_bits_denied; // @[TLChannelCompactor.scala:83:22] wire [63:0] protocol_bits_data; // @[TLChannelCompactor.scala:83:22] wire protocol_bits_corrupt; // @[TLChannelCompactor.scala:83:22] wire _io_beat_ready_T_2; // @[TLChannelCompactor.scala:91:53] wire [2:0] io_protocol_bits_opcode_0; // @[TLChannelCompactor.scala:134:7] wire [1:0] io_protocol_bits_param_0; // @[TLChannelCompactor.scala:134:7] wire [7:0] io_protocol_bits_size_0; // @[TLChannelCompactor.scala:134:7] wire [7:0] io_protocol_bits_source_0; // @[TLChannelCompactor.scala:134:7] wire [7:0] io_protocol_bits_sink_0; // @[TLChannelCompactor.scala:134:7] wire io_protocol_bits_denied_0; // @[TLChannelCompactor.scala:134:7] wire [63:0] io_protocol_bits_data_0; // @[TLChannelCompactor.scala:134:7] wire io_protocol_bits_corrupt_0; // @[TLChannelCompactor.scala:134:7] wire io_protocol_valid_0; // @[TLChannelCompactor.scala:134:7] wire io_beat_ready_0; // @[TLChannelCompactor.scala:134:7] wire _protocol_valid_T_2; // @[TLChannelCompactor.scala:92:54] assign io_protocol_valid_0 = protocol_valid; // @[TLChannelCompactor.scala:83:22, :134:7] wire [2:0] _protocol_bits_opcode_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_opcode_0 = protocol_bits_opcode; // @[TLChannelCompactor.scala:83:22, :134:7] wire [1:0] _protocol_bits_param_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_param_0 = protocol_bits_param; // @[TLChannelCompactor.scala:83:22, :134:7] wire [7:0] _protocol_bits_size_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_size_0 = protocol_bits_size; // @[TLChannelCompactor.scala:83:22, :134:7] wire [7:0] _protocol_bits_source_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_source_0 = protocol_bits_source; // @[TLChannelCompactor.scala:83:22, :134:7] wire [7:0] _protocol_bits_sink_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_sink_0 = protocol_bits_sink; // @[TLChannelCompactor.scala:83:22, :134:7] wire _protocol_bits_denied_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_denied_0 = protocol_bits_denied; // @[TLChannelCompactor.scala:83:22, :134:7] wire [63:0] _protocol_bits_data_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_data_0 = protocol_bits_data; // @[TLChannelCompactor.scala:83:22, :134:7] wire _protocol_bits_corrupt_WIRE; // @[TLChannelCompactor.scala:97:22] assign io_protocol_bits_corrupt_0 = protocol_bits_corrupt; // @[TLChannelCompactor.scala:83:22, :134:7] reg is_const; // @[TLChannelCompactor.scala:88:25] reg [29:0] const_reg; // @[TLChannelCompactor.scala:89:22] wire [64:0] const_0 = io_beat_bits_head_0 ? io_beat_bits_payload_0 : {35'h0, const_reg}; // @[TLChannelCompactor.scala:89:22, :90:18, :134:7] wire _io_beat_ready_T = ~io_beat_bits_tail_0; // @[TLChannelCompactor.scala:91:33, :134:7] wire _io_beat_ready_T_1 = is_const & _io_beat_ready_T; // @[TLChannelCompactor.scala:88:25, :91:{30,33}] assign _io_beat_ready_T_2 = _io_beat_ready_T_1 | protocol_ready; // @[TLChannelCompactor.scala:83:22, :91:{30,53}] assign io_beat_ready_0 = _io_beat_ready_T_2; // @[TLChannelCompactor.scala:91:53, :134:7] wire _protocol_valid_T = ~is_const; // @[TLChannelCompactor.scala:88:25, :92:22] wire _protocol_valid_T_1 = _protocol_valid_T | io_beat_bits_tail_0; // @[TLChannelCompactor.scala:92:{22,32}, :134:7] assign _protocol_valid_T_2 = _protocol_valid_T_1 & io_beat_valid_0; // @[TLChannelCompactor.scala:92:{32,54}, :134:7] assign protocol_valid = _protocol_valid_T_2; // @[TLChannelCompactor.scala:83:22, :92:54] assign protocol_bits_denied = _protocol_bits_denied_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_denied_WIRE = const_0[0]; // @[TLChannelCompactor.scala:90:18, :97:22] assign protocol_bits_sink = _protocol_bits_sink_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_sink_WIRE = const_0[8:1]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13] assign protocol_bits_source = _protocol_bits_source_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_source_WIRE = const_0[16:9]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13] assign protocol_bits_size = _protocol_bits_size_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_size_WIRE = const_0[24:17]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13] assign protocol_bits_param = _protocol_bits_param_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_param_WIRE = const_0[26:25]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13] assign protocol_bits_opcode = _protocol_bits_opcode_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_opcode_WIRE = const_0[29:27]; // @[TLChannelCompactor.scala:90:18, :97:22, :98:13] assign protocol_bits_corrupt = _protocol_bits_corrupt_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] assign _protocol_bits_corrupt_WIRE = io_beat_bits_payload_0[0]; // @[TLChannelCompactor.scala:97:22, :134:7] assign _protocol_bits_data_WIRE = io_beat_bits_payload_0[64:1]; // @[TLChannelCompactor.scala:97:22, :98:13, :134:7] assign protocol_bits_data = _protocol_bits_data_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22] wire _T_12 = io_beat_ready_0 & io_beat_valid_0; // @[Decoupled.scala:51:35] wire _T_11 = _T_12 & io_beat_bits_head_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TLChannelCompactor.scala:134:7] if (reset) // @[TLChannelCompactor.scala:134:7] is_const <= 1'h1; // @[TLChannelCompactor.scala:88:25] else // @[TLChannelCompactor.scala:134:7] is_const <= _T_12 & io_beat_bits_tail_0 | ~_T_11 & is_const; // @[Decoupled.scala:51:35] if (_T_11) // @[TLChannelCompactor.scala:104:22] const_reg <= io_beat_bits_payload_0[29:0]; // @[TLChannelCompactor.scala:89:22, :104:77, :134:7] always @(posedge) assign io_protocol_valid = io_protocol_valid_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_opcode = io_protocol_bits_opcode_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_param = io_protocol_bits_param_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_size = io_protocol_bits_size_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_source = io_protocol_bits_source_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_sink = io_protocol_bits_sink_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_denied = io_protocol_bits_denied_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_data = io_protocol_bits_data_0; // @[TLChannelCompactor.scala:134:7] assign io_protocol_bits_corrupt = io_protocol_bits_corrupt_0; // @[TLChannelCompactor.scala:134:7] assign io_beat_ready = io_beat_ready_0; // @[TLChannelCompactor.scala:134:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_234 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_234( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_28 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, in_vc : UInt<0>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_56 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_28 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0ha), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _T_2 = eq(UInt<4>(0hc), io.in.bits.egress_id) node _T_3 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<3>(0h5) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h0) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0ha), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<4>(0hc), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0hb), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0hc), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0ha), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<4>(0hc), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h5)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) node _T_16 = eq(UInt<3>(0h6), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_18 = and(route_q.io.enq.valid, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_57 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_28 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] node _T_23 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_24 = and(vcalloc_q.io.enq.valid, _T_23) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_25, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _c_T = cat(c_hi, c_lo) node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node _c_T_2 = cat(c_hi_1, c_lo_1) node _c_T_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_channel_oh_0 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 2) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 1, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node _out_bundle_bits_out_virt_channel_T_3 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 1) node _out_bundle_bits_out_virt_channel_T_4 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_3) node _out_bundle_bits_out_virt_channel_T_5 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_4, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_6 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_7 = or(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_6) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<2> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_7 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1

module IngressUnit_28( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [36:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [36:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [3:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [36:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [36:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 4'hA; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'hB; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 4'hC; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 4'hD; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'hA : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hB : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'hC : 4'h0); // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h5; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h5; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_acd_router_1ClockSinkDomain : output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_1 connect routers.clock, childClock connect routers.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0 connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1 connect auto.routers_egress_nodes_out.flit.bits, routers.auto.egress_nodes_out.flit.bits connect auto.routers_egress_nodes_out.flit.valid, routers.auto.egress_nodes_out.flit.valid connect routers.auto.egress_nodes_out.flit.ready, auto.routers_egress_nodes_out.flit.ready connect auto.routers_debug_out, routers.auto.debug_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset

module TLSplitACDxBENoC_acd_router_1ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_1 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_egress_nodes_out_flit_ready (auto_routers_egress_nodes_out_flit_ready), .auto_egress_nodes_out_flit_valid (auto_routers_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (auto_routers_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (auto_routers_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (auto_routers_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_18 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_18( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_6 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state

module IssueSlot_6( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_171 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_171( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_6 : input clock : Clock input reset : Reset output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}} node _legal_address_T = xor(io.paddr, UInt<1>(0h0)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(io.paddr, UInt<21>(0h100000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) node _legal_address_T_25 = xor(io.paddr, UInt<21>(0h110000)) node _legal_address_T_26 = cvt(_legal_address_T_25) node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) node _legal_address_T_28 = asSInt(_legal_address_T_27) node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) node _legal_address_T_30 = xor(io.paddr, UInt<26>(0h2000000)) node _legal_address_T_31 = cvt(_legal_address_T_30) node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000))) node _legal_address_T_33 = asSInt(_legal_address_T_32) node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) node _legal_address_T_35 = xor(io.paddr, UInt<26>(0h2010000)) node _legal_address_T_36 = cvt(_legal_address_T_35) node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) node _legal_address_T_38 = asSInt(_legal_address_T_37) node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) node _legal_address_T_40 = xor(io.paddr, UInt<28>(0h8000000)) node _legal_address_T_41 = cvt(_legal_address_T_40) node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000))) node _legal_address_T_43 = asSInt(_legal_address_T_42) node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) node _legal_address_T_45 = xor(io.paddr, UInt<28>(0hc000000)) node _legal_address_T_46 = cvt(_legal_address_T_45) node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000))) node _legal_address_T_48 = asSInt(_legal_address_T_47) node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10020000)) node _legal_address_T_51 = cvt(_legal_address_T_50) node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) node _legal_address_T_53 = asSInt(_legal_address_T_52) node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) node _legal_address_T_55 = xor(io.paddr, UInt<32>(0h80000000)) node _legal_address_T_56 = cvt(_legal_address_T_55) node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<29>(0h10000000))) node _legal_address_T_58 = asSInt(_legal_address_T_57) node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[12] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 connect _legal_address_WIRE[5], _legal_address_T_29 connect _legal_address_WIRE[6], _legal_address_T_34 connect _legal_address_WIRE[7], _legal_address_T_39 connect _legal_address_WIRE[8], _legal_address_T_44 connect _legal_address_WIRE[9], _legal_address_T_49 connect _legal_address_WIRE[10], _legal_address_T_54 connect _legal_address_WIRE[11], _legal_address_T_59 node _legal_address_T_60 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_61 = or(_legal_address_T_60, _legal_address_WIRE[2]) node _legal_address_T_62 = or(_legal_address_T_61, _legal_address_WIRE[3]) node _legal_address_T_63 = or(_legal_address_T_62, _legal_address_WIRE[4]) node _legal_address_T_64 = or(_legal_address_T_63, _legal_address_WIRE[5]) node _legal_address_T_65 = or(_legal_address_T_64, _legal_address_WIRE[6]) node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[7]) node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[8]) node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[9]) node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[10]) node legal_address = or(_legal_address_T_69, _legal_address_WIRE[11]) node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T) node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2) node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5) node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c011000))) node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7) node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10) node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12) node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_15 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9) node _io_resp_cacheable_T_16 = or(_io_resp_cacheable_T_15, _io_resp_cacheable_T_14) node _io_resp_cacheable_T_17 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_cacheable_T_18 = cvt(_io_resp_cacheable_T_17) node _io_resp_cacheable_T_19 = and(_io_resp_cacheable_T_18, asSInt(UInt<33>(0h8c010000))) node _io_resp_cacheable_T_20 = asSInt(_io_resp_cacheable_T_19) node _io_resp_cacheable_T_21 = eq(_io_resp_cacheable_T_20, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_22 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_cacheable_T_23 = cvt(_io_resp_cacheable_T_22) node _io_resp_cacheable_T_24 = and(_io_resp_cacheable_T_23, asSInt(UInt<33>(0h80000000))) node _io_resp_cacheable_T_25 = asSInt(_io_resp_cacheable_T_24) node _io_resp_cacheable_T_26 = eq(_io_resp_cacheable_T_25, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_27 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_26) node _io_resp_cacheable_T_28 = mux(_io_resp_cacheable_T_16, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_cacheable_T_29 = mux(_io_resp_cacheable_T_27, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_cacheable_T_30 = or(_io_resp_cacheable_T_28, _io_resp_cacheable_T_29) wire _io_resp_cacheable_WIRE : UInt<1> connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_30 node _io_resp_cacheable_T_31 = and(legal_address, _io_resp_cacheable_WIRE) connect io.resp.cacheable, _io_resp_cacheable_T_31 node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_r_T_1 = cvt(_io_resp_r_T) node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0))) node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2) node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0))) node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1)) connect io.resp.r, _io_resp_r_T_5 node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_w_T_1 = cvt(_io_resp_w_T) node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2) node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0))) node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_w_T_6 = cvt(_io_resp_w_T_5) node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7) node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0))) node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_w_T_11 = cvt(_io_resp_w_T_10) node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12) node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0))) node _io_resp_w_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_16 = cvt(_io_resp_w_T_15) node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17) node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0))) node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_21 = cvt(_io_resp_w_T_20) node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22) node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0))) node _io_resp_w_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_w_T_26 = cvt(_io_resp_w_T_25) node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27) node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0))) node _io_resp_w_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_w_T_31 = cvt(_io_resp_w_T_30) node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32) node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0))) node _io_resp_w_T_35 = or(_io_resp_w_T_4, _io_resp_w_T_9) node _io_resp_w_T_36 = or(_io_resp_w_T_35, _io_resp_w_T_14) node _io_resp_w_T_37 = or(_io_resp_w_T_36, _io_resp_w_T_19) node _io_resp_w_T_38 = or(_io_resp_w_T_37, _io_resp_w_T_24) node _io_resp_w_T_39 = or(_io_resp_w_T_38, _io_resp_w_T_29) node _io_resp_w_T_40 = or(_io_resp_w_T_39, _io_resp_w_T_34) node _io_resp_w_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_w_T_42 = cvt(_io_resp_w_T_41) node _io_resp_w_T_43 = and(_io_resp_w_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_44 = asSInt(_io_resp_w_T_43) node _io_resp_w_T_45 = eq(_io_resp_w_T_44, asSInt(UInt<1>(0h0))) node _io_resp_w_T_46 = mux(_io_resp_w_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_w_T_47 = mux(_io_resp_w_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_w_T_48 = or(_io_resp_w_T_46, _io_resp_w_T_47) wire _io_resp_w_WIRE : UInt<1> connect _io_resp_w_WIRE, _io_resp_w_T_48 node _io_resp_w_T_49 = and(legal_address, _io_resp_w_WIRE) connect io.resp.w, _io_resp_w_T_49 node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_pp_T_1 = cvt(_io_resp_pp_T) node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2) node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5) node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7) node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10) node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12) node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15) node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17) node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20) node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22) node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25) node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27) node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30) node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32) node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_35 = or(_io_resp_pp_T_4, _io_resp_pp_T_9) node _io_resp_pp_T_36 = or(_io_resp_pp_T_35, _io_resp_pp_T_14) node _io_resp_pp_T_37 = or(_io_resp_pp_T_36, _io_resp_pp_T_19) node _io_resp_pp_T_38 = or(_io_resp_pp_T_37, _io_resp_pp_T_24) node _io_resp_pp_T_39 = or(_io_resp_pp_T_38, _io_resp_pp_T_29) node _io_resp_pp_T_40 = or(_io_resp_pp_T_39, _io_resp_pp_T_34) node _io_resp_pp_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_pp_T_42 = cvt(_io_resp_pp_T_41) node _io_resp_pp_T_43 = and(_io_resp_pp_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_44 = asSInt(_io_resp_pp_T_43) node _io_resp_pp_T_45 = eq(_io_resp_pp_T_44, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_46 = mux(_io_resp_pp_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_pp_T_47 = mux(_io_resp_pp_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_pp_T_48 = or(_io_resp_pp_T_46, _io_resp_pp_T_47) wire _io_resp_pp_WIRE : UInt<1> connect _io_resp_pp_WIRE, _io_resp_pp_T_48 node _io_resp_pp_T_49 = and(legal_address, _io_resp_pp_WIRE) connect io.resp.pp, _io_resp_pp_T_49 node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_al_T_1 = cvt(_io_resp_al_T) node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2) node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0))) node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_al_T_6 = cvt(_io_resp_al_T_5) node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7) node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0))) node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_al_T_11 = cvt(_io_resp_al_T_10) node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12) node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0))) node _io_resp_al_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_16 = cvt(_io_resp_al_T_15) node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17) node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0))) node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_21 = cvt(_io_resp_al_T_20) node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22) node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0))) node _io_resp_al_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_al_T_26 = cvt(_io_resp_al_T_25) node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27) node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0))) node _io_resp_al_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_al_T_31 = cvt(_io_resp_al_T_30) node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32) node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0))) node _io_resp_al_T_35 = or(_io_resp_al_T_4, _io_resp_al_T_9) node _io_resp_al_T_36 = or(_io_resp_al_T_35, _io_resp_al_T_14) node _io_resp_al_T_37 = or(_io_resp_al_T_36, _io_resp_al_T_19) node _io_resp_al_T_38 = or(_io_resp_al_T_37, _io_resp_al_T_24) node _io_resp_al_T_39 = or(_io_resp_al_T_38, _io_resp_al_T_29) node _io_resp_al_T_40 = or(_io_resp_al_T_39, _io_resp_al_T_34) node _io_resp_al_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_al_T_42 = cvt(_io_resp_al_T_41) node _io_resp_al_T_43 = and(_io_resp_al_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_44 = asSInt(_io_resp_al_T_43) node _io_resp_al_T_45 = eq(_io_resp_al_T_44, asSInt(UInt<1>(0h0))) node _io_resp_al_T_46 = mux(_io_resp_al_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_al_T_47 = mux(_io_resp_al_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_al_T_48 = or(_io_resp_al_T_46, _io_resp_al_T_47) wire _io_resp_al_WIRE : UInt<1> connect _io_resp_al_WIRE, _io_resp_al_T_48 node _io_resp_al_T_49 = and(legal_address, _io_resp_al_WIRE) connect io.resp.al, _io_resp_al_T_49 node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_aa_T_1 = cvt(_io_resp_aa_T) node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2) node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5) node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7) node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10) node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12) node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15) node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17) node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20) node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22) node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25) node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27) node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30) node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32) node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_35 = or(_io_resp_aa_T_4, _io_resp_aa_T_9) node _io_resp_aa_T_36 = or(_io_resp_aa_T_35, _io_resp_aa_T_14) node _io_resp_aa_T_37 = or(_io_resp_aa_T_36, _io_resp_aa_T_19) node _io_resp_aa_T_38 = or(_io_resp_aa_T_37, _io_resp_aa_T_24) node _io_resp_aa_T_39 = or(_io_resp_aa_T_38, _io_resp_aa_T_29) node _io_resp_aa_T_40 = or(_io_resp_aa_T_39, _io_resp_aa_T_34) node _io_resp_aa_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_aa_T_42 = cvt(_io_resp_aa_T_41) node _io_resp_aa_T_43 = and(_io_resp_aa_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_44 = asSInt(_io_resp_aa_T_43) node _io_resp_aa_T_45 = eq(_io_resp_aa_T_44, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_46 = mux(_io_resp_aa_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_aa_T_47 = mux(_io_resp_aa_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_aa_T_48 = or(_io_resp_aa_T_46, _io_resp_aa_T_47) wire _io_resp_aa_WIRE : UInt<1> connect _io_resp_aa_WIRE, _io_resp_aa_T_48 node _io_resp_aa_T_49 = and(legal_address, _io_resp_aa_WIRE) connect io.resp.aa, _io_resp_aa_T_49 node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_x_T_1 = cvt(_io_resp_x_T) node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2) node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0))) node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_x_T_6 = cvt(_io_resp_x_T_5) node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7) node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0))) node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_x_T_11 = cvt(_io_resp_x_T_10) node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12) node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0))) node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_x_T_16 = cvt(_io_resp_x_T_15) node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17) node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0))) node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_x_T_21 = cvt(_io_resp_x_T_20) node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0h90000000))) node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22) node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0))) node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9) node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14) node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19) node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24) node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000)) node _io_resp_x_T_30 = cvt(_io_resp_x_T_29) node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31) node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0))) node _io_resp_x_T_34 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_x_T_35 = cvt(_io_resp_x_T_34) node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0h9e103000))) node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36) node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0))) node _io_resp_x_T_39 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_x_T_40 = cvt(_io_resp_x_T_39) node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41) node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0))) node _io_resp_x_T_44 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_x_T_45 = cvt(_io_resp_x_T_44) node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46) node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0))) node _io_resp_x_T_49 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_x_T_50 = cvt(_io_resp_x_T_49) node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0h9c000000))) node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51) node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0))) node _io_resp_x_T_54 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_x_T_55 = cvt(_io_resp_x_T_54) node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56) node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0))) node _io_resp_x_T_59 = or(_io_resp_x_T_33, _io_resp_x_T_38) node _io_resp_x_T_60 = or(_io_resp_x_T_59, _io_resp_x_T_43) node _io_resp_x_T_61 = or(_io_resp_x_T_60, _io_resp_x_T_48) node _io_resp_x_T_62 = or(_io_resp_x_T_61, _io_resp_x_T_53) node _io_resp_x_T_63 = or(_io_resp_x_T_62, _io_resp_x_T_58) node _io_resp_x_T_64 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_x_T_65 = mux(_io_resp_x_T_63, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_x_T_66 = or(_io_resp_x_T_64, _io_resp_x_T_65) wire _io_resp_x_WIRE : UInt<1> connect _io_resp_x_WIRE, _io_resp_x_T_66 node _io_resp_x_T_67 = and(legal_address, _io_resp_x_WIRE) connect io.resp.x, _io_resp_x_T_67 node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_eff_T_1 = cvt(_io_resp_eff_T) node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0h9e112000))) node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2) node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5) node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0h9e103000))) node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7) node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10) node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12) node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15) node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17) node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_20 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20) node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0h9c000000))) node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22) node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25) node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27) node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_30 = or(_io_resp_eff_T_4, _io_resp_eff_T_9) node _io_resp_eff_T_31 = or(_io_resp_eff_T_30, _io_resp_eff_T_14) node _io_resp_eff_T_32 = or(_io_resp_eff_T_31, _io_resp_eff_T_19) node _io_resp_eff_T_33 = or(_io_resp_eff_T_32, _io_resp_eff_T_24) node _io_resp_eff_T_34 = or(_io_resp_eff_T_33, _io_resp_eff_T_29) node _io_resp_eff_T_35 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_eff_T_36 = cvt(_io_resp_eff_T_35) node _io_resp_eff_T_37 = and(_io_resp_eff_T_36, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_38 = asSInt(_io_resp_eff_T_37) node _io_resp_eff_T_39 = eq(_io_resp_eff_T_38, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_40 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_eff_T_41 = cvt(_io_resp_eff_T_40) node _io_resp_eff_T_42 = and(_io_resp_eff_T_41, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_43 = asSInt(_io_resp_eff_T_42) node _io_resp_eff_T_44 = eq(_io_resp_eff_T_43, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_45 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_eff_T_46 = cvt(_io_resp_eff_T_45) node _io_resp_eff_T_47 = and(_io_resp_eff_T_46, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_48 = asSInt(_io_resp_eff_T_47) node _io_resp_eff_T_49 = eq(_io_resp_eff_T_48, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_50 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_eff_T_51 = cvt(_io_resp_eff_T_50) node _io_resp_eff_T_52 = and(_io_resp_eff_T_51, asSInt(UInt<33>(0h90000000))) node _io_resp_eff_T_53 = asSInt(_io_resp_eff_T_52) node _io_resp_eff_T_54 = eq(_io_resp_eff_T_53, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_55 = or(_io_resp_eff_T_39, _io_resp_eff_T_44) node _io_resp_eff_T_56 = or(_io_resp_eff_T_55, _io_resp_eff_T_49) node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_54) node _io_resp_eff_T_58 = mux(_io_resp_eff_T_34, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59) wire _io_resp_eff_WIRE : UInt<1> connect _io_resp_eff_WIRE, _io_resp_eff_T_60 node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE) connect io.resp.eff, _io_resp_eff_T_61

module PMAChecker_6( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [39:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73] wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19] wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_49; // @[PMA.scala:39:19] wire _io_resp_pp_T_49; // @[PMA.scala:39:19] wire _io_resp_al_T_49; // @[PMA.scala:39:19] wire _io_resp_aa_T_49; // @[PMA.scala:39:19] wire _io_resp_x_T_67; // @[PMA.scala:39:19] wire _io_resp_eff_T_61; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31] assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_41; // @[Parameters.scala:137:31] assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31] assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_41; // @[Parameters.scala:137:31] assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31] assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31] assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31] assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31] assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_50 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31] assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31] assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31] assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31] assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31] assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89] wire [40:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46] wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89] wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46] wire _io_resp_w_T_45 = _io_resp_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73] assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89] wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46] wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73] assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46] wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89] wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46] wire _io_resp_al_T_45 = _io_resp_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73] assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89] wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46] wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73] assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73] assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73] wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46] wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46] wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46] wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89] wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89] wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89] wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73] assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_216 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_216( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_409 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_153 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_409( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_153 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_37 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_77 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_37( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_77 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_127 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_144 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_127( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_144 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_1 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _source_ok_T_2 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 connect _source_ok_WIRE[2], _source_ok_T_2 node _source_ok_T_3 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_3, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_23 = cvt(_T_22) node _T_24 = and(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = asSInt(_T_24) node _T_26 = eq(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = or(_T_21, _T_26) node _T_28 = and(_T_11, _T_19) node _T_29 = and(_T_28, _T_27) node _T_30 = asUInt(reset) node _T_31 = eq(_T_30, UInt<1>(0h0)) when _T_31 : node _T_32 = eq(_T_29, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_29, UInt<1>(0h1), "") : assert_1 node _T_33 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_33 : node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_38 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_40 = or(_T_37, _T_38) node _T_41 = or(_T_40, _T_39) node _T_42 = and(_T_36, _T_41) node _T_43 = or(UInt<1>(0h0), _T_42) node _T_44 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<14>(0h2000))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<13>(0h1000))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<17>(0h10000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<18>(0h2f000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<13>(0h1000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<27>(0h4000000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = or(_T_49, _T_54) node _T_86 = or(_T_85, _T_59) node _T_87 = or(_T_86, _T_64) node _T_88 = or(_T_87, _T_69) node _T_89 = or(_T_88, _T_74) node _T_90 = or(_T_89, _T_79) node _T_91 = or(_T_90, _T_84) node _T_92 = and(_T_44, _T_91) node _T_93 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<29>(0h10000000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = and(_T_94, _T_105) node _T_107 = or(UInt<1>(0h0), _T_92) node _T_108 = or(_T_107, _T_106) node _T_109 = and(_T_43, _T_108) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_109, UInt<1>(0h1), "") : assert_2 node _T_113 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_115 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_113 connect _WIRE[1], _T_114 connect _WIRE[2], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_120 = or(_T_117, _T_118) node _T_121 = or(_T_120, _T_119) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_121 node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = or(UInt<1>(0h0), _T_124) node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = or(_T_130, _T_135) node _T_177 = or(_T_176, _T_140) node _T_178 = or(_T_177, _T_145) node _T_179 = or(_T_178, _T_150) node _T_180 = or(_T_179, _T_155) node _T_181 = or(_T_180, _T_160) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_170) node _T_184 = or(_T_183, _T_175) node _T_185 = and(_T_125, _T_184) node _T_186 = or(UInt<1>(0h0), _T_185) node _T_187 = and(_WIRE_1, _T_186) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_187, UInt<1>(0h1), "") : assert_3 node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(source_ok, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_194 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_194, UInt<1>(0h1), "") : assert_5 node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(is_aligned, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_201, UInt<1>(0h1), "") : assert_7 node _T_205 = not(io.in.a.bits.mask) node _T_206 = eq(_T_205, UInt<1>(0h0)) node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_T_206, UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_206, UInt<1>(0h1), "") : assert_8 node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_210, UInt<1>(0h1), "") : assert_9 node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_214 : node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_219 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_220 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_221 = or(_T_218, _T_219) node _T_222 = or(_T_221, _T_220) node _T_223 = and(_T_217, _T_222) node _T_224 = or(UInt<1>(0h0), _T_223) node _T_225 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<14>(0h2000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<18>(0h2f000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<27>(0h4000000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_230, _T_235) node _T_267 = or(_T_266, _T_240) node _T_268 = or(_T_267, _T_245) node _T_269 = or(_T_268, _T_250) node _T_270 = or(_T_269, _T_255) node _T_271 = or(_T_270, _T_260) node _T_272 = or(_T_271, _T_265) node _T_273 = and(_T_225, _T_272) node _T_274 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<29>(0h10000000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_280, _T_285) node _T_287 = and(_T_275, _T_286) node _T_288 = or(UInt<1>(0h0), _T_273) node _T_289 = or(_T_288, _T_287) node _T_290 = and(_T_224, _T_289) node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(_T_290, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_290, UInt<1>(0h1), "") : assert_10 node _T_294 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_295 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_296 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_294 connect _WIRE_2[1], _T_295 connect _WIRE_2[2], _T_296 node _T_297 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_298 = mux(_WIRE_2[0], _T_297, UInt<1>(0h0)) node _T_299 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_300 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = or(_T_298, _T_299) node _T_302 = or(_T_301, _T_300) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_302 node _T_303 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_304 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_305 = and(_T_303, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<14>(0h2000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_313 = cvt(_T_312) node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000))) node _T_315 = asSInt(_T_314) node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_318 = cvt(_T_317) node _T_319 = and(_T_318, asSInt(UInt<17>(0h10000))) node _T_320 = asSInt(_T_319) node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0))) node _T_322 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<18>(0h2f000))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<17>(0h10000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<27>(0h4000000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<13>(0h1000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<29>(0h10000000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = or(_T_311, _T_316) node _T_358 = or(_T_357, _T_321) node _T_359 = or(_T_358, _T_326) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_336) node _T_362 = or(_T_361, _T_341) node _T_363 = or(_T_362, _T_346) node _T_364 = or(_T_363, _T_351) node _T_365 = or(_T_364, _T_356) node _T_366 = and(_T_306, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_WIRE_3, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_368, UInt<1>(0h1), "") : assert_11 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(source_ok, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_375 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_375, UInt<1>(0h1), "") : assert_13 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(is_aligned, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_382 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_382, UInt<1>(0h1), "") : assert_15 node _T_386 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_386, UInt<1>(0h1), "") : assert_16 node _T_390 = not(io.in.a.bits.mask) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_391, UInt<1>(0h1), "") : assert_17 node _T_395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_395, UInt<1>(0h1), "") : assert_18 node _T_399 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_399 : node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_404 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_405 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_406 = or(_T_403, _T_404) node _T_407 = or(_T_406, _T_405) node _T_408 = and(_T_402, _T_407) node _T_409 = or(UInt<1>(0h0), _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_409, UInt<1>(0h1), "") : assert_19 node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = and(_T_416, _T_421) node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_433 = cvt(_T_432) node _T_434 = and(_T_433, asSInt(UInt<17>(0h10000))) node _T_435 = asSInt(_T_434) node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0))) node _T_437 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_438 = cvt(_T_437) node _T_439 = and(_T_438, asSInt(UInt<18>(0h2f000))) node _T_440 = asSInt(_T_439) node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0))) node _T_442 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_443 = cvt(_T_442) node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000))) node _T_445 = asSInt(_T_444) node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0))) node _T_447 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_453 = cvt(_T_452) node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000))) node _T_455 = asSInt(_T_454) node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0))) node _T_457 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<27>(0h4000000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<29>(0h10000000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = or(_T_431, _T_436) node _T_473 = or(_T_472, _T_441) node _T_474 = or(_T_473, _T_446) node _T_475 = or(_T_474, _T_451) node _T_476 = or(_T_475, _T_456) node _T_477 = or(_T_476, _T_461) node _T_478 = or(_T_477, _T_466) node _T_479 = or(_T_478, _T_471) node _T_480 = and(_T_426, _T_479) node _T_481 = or(UInt<1>(0h0), _T_422) node _T_482 = or(_T_481, _T_480) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_482, UInt<1>(0h1), "") : assert_20 node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(source_ok, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(is_aligned, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_492, UInt<1>(0h1), "") : assert_23 node _T_496 = eq(io.in.a.bits.mask, mask) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_496, UInt<1>(0h1), "") : assert_24 node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_500, UInt<1>(0h1), "") : assert_25 node _T_504 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_504 : node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_509 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_510 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_511 = or(_T_508, _T_509) node _T_512 = or(_T_511, _T_510) node _T_513 = and(_T_507, _T_512) node _T_514 = or(UInt<1>(0h0), _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = and(_T_518, _T_523) node _T_525 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_526 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_527 = and(_T_525, _T_526) node _T_528 = or(UInt<1>(0h0), _T_527) node _T_529 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<14>(0h2000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<18>(0h2f000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<17>(0h10000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<27>(0h4000000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<29>(0h10000000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = or(_T_533, _T_538) node _T_570 = or(_T_569, _T_543) node _T_571 = or(_T_570, _T_548) node _T_572 = or(_T_571, _T_553) node _T_573 = or(_T_572, _T_558) node _T_574 = or(_T_573, _T_563) node _T_575 = or(_T_574, _T_568) node _T_576 = and(_T_528, _T_575) node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = and(_T_577, _T_582) node _T_584 = or(UInt<1>(0h0), _T_524) node _T_585 = or(_T_584, _T_576) node _T_586 = or(_T_585, _T_583) node _T_587 = and(_T_514, _T_586) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_587, UInt<1>(0h1), "") : assert_26 node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(source_ok, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(is_aligned, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_597 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_597, UInt<1>(0h1), "") : assert_29 node _T_601 = eq(io.in.a.bits.mask, mask) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_601, UInt<1>(0h1), "") : assert_30 node _T_605 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_605 : node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_608 = and(_T_606, _T_607) node _T_609 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_610 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_611 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_612 = or(_T_609, _T_610) node _T_613 = or(_T_612, _T_611) node _T_614 = and(_T_608, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<27>(0h4000000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<29>(0h10000000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = or(_T_634, _T_639) node _T_671 = or(_T_670, _T_644) node _T_672 = or(_T_671, _T_649) node _T_673 = or(_T_672, _T_654) node _T_674 = or(_T_673, _T_659) node _T_675 = or(_T_674, _T_664) node _T_676 = or(_T_675, _T_669) node _T_677 = and(_T_629, _T_676) node _T_678 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_680 = cvt(_T_679) node _T_681 = and(_T_680, asSInt(UInt<17>(0h10000))) node _T_682 = asSInt(_T_681) node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0))) node _T_684 = and(_T_678, _T_683) node _T_685 = or(UInt<1>(0h0), _T_625) node _T_686 = or(_T_685, _T_677) node _T_687 = or(_T_686, _T_684) node _T_688 = and(_T_615, _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_688, UInt<1>(0h1), "") : assert_31 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(source_ok, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(is_aligned, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_698, UInt<1>(0h1), "") : assert_34 node _T_702 = not(mask) node _T_703 = and(io.in.a.bits.mask, _T_702) node _T_704 = eq(_T_703, UInt<1>(0h0)) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_704, UInt<1>(0h1), "") : assert_35 node _T_708 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_708 : node _T_709 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_710 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_711 = and(_T_709, _T_710) node _T_712 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_713 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_714 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_715 = or(_T_712, _T_713) node _T_716 = or(_T_715, _T_714) node _T_717 = and(_T_711, _T_716) node _T_718 = or(UInt<1>(0h0), _T_717) node _T_719 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_720 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<14>(0h2000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_749 = cvt(_T_748) node _T_750 = and(_T_749, asSInt(UInt<17>(0h10000))) node _T_751 = asSInt(_T_750) node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0))) node _T_753 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<27>(0h4000000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_764 = cvt(_T_763) node _T_765 = and(_T_764, asSInt(UInt<29>(0h10000000))) node _T_766 = asSInt(_T_765) node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0))) node _T_768 = or(_T_727, _T_732) node _T_769 = or(_T_768, _T_737) node _T_770 = or(_T_769, _T_742) node _T_771 = or(_T_770, _T_747) node _T_772 = or(_T_771, _T_752) node _T_773 = or(_T_772, _T_757) node _T_774 = or(_T_773, _T_762) node _T_775 = or(_T_774, _T_767) node _T_776 = and(_T_722, _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_776) node _T_785 = or(_T_784, _T_783) node _T_786 = and(_T_718, _T_785) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_786, UInt<1>(0h1), "") : assert_36 node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(source_ok, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(is_aligned, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_796 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_796, UInt<1>(0h1), "") : assert_39 node _T_800 = eq(io.in.a.bits.mask, mask) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_800, UInt<1>(0h1), "") : assert_40 node _T_804 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_809 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_810 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_811 = or(_T_808, _T_809) node _T_812 = or(_T_811, _T_810) node _T_813 = and(_T_807, _T_812) node _T_814 = or(UInt<1>(0h0), _T_813) node _T_815 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_816 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_817 = and(_T_815, _T_816) node _T_818 = or(UInt<1>(0h0), _T_817) node _T_819 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<14>(0h2000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<18>(0h2f000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<17>(0h10000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<29>(0h10000000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = or(_T_823, _T_828) node _T_865 = or(_T_864, _T_833) node _T_866 = or(_T_865, _T_838) node _T_867 = or(_T_866, _T_843) node _T_868 = or(_T_867, _T_848) node _T_869 = or(_T_868, _T_853) node _T_870 = or(_T_869, _T_858) node _T_871 = or(_T_870, _T_863) node _T_872 = and(_T_818, _T_871) node _T_873 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_874 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<17>(0h10000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = and(_T_873, _T_878) node _T_880 = or(UInt<1>(0h0), _T_872) node _T_881 = or(_T_880, _T_879) node _T_882 = and(_T_814, _T_881) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_882, UInt<1>(0h1), "") : assert_41 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(is_aligned, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_892, UInt<1>(0h1), "") : assert_44 node _T_896 = eq(io.in.a.bits.mask, mask) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_896, UInt<1>(0h1), "") : assert_45 node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_905 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_906 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_907 = or(_T_904, _T_905) node _T_908 = or(_T_907, _T_906) node _T_909 = and(_T_903, _T_908) node _T_910 = or(UInt<1>(0h0), _T_909) node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_912 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_913 = and(_T_911, _T_912) node _T_914 = or(UInt<1>(0h0), _T_913) node _T_915 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<13>(0h1000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = and(_T_914, _T_919) node _T_921 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<14>(0h2000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_948 = cvt(_T_947) node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000))) node _T_950 = asSInt(_T_949) node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0))) node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_953 = cvt(_T_952) node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000))) node _T_955 = asSInt(_T_954) node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0))) node _T_957 = or(_T_926, _T_931) node _T_958 = or(_T_957, _T_936) node _T_959 = or(_T_958, _T_941) node _T_960 = or(_T_959, _T_946) node _T_961 = or(_T_960, _T_951) node _T_962 = or(_T_961, _T_956) node _T_963 = and(_T_921, _T_962) node _T_964 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_965 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_966 = and(_T_964, _T_965) node _T_967 = or(UInt<1>(0h0), _T_966) node _T_968 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_969 = cvt(_T_968) node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000))) node _T_971 = asSInt(_T_970) node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0))) node _T_973 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_974 = cvt(_T_973) node _T_975 = and(_T_974, asSInt(UInt<29>(0h10000000))) node _T_976 = asSInt(_T_975) node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0))) node _T_978 = or(_T_972, _T_977) node _T_979 = and(_T_967, _T_978) node _T_980 = or(UInt<1>(0h0), _T_920) node _T_981 = or(_T_980, _T_963) node _T_982 = or(_T_981, _T_979) node _T_983 = and(_T_910, _T_982) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_983, UInt<1>(0h1), "") : assert_46 node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(source_ok, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(is_aligned, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_993 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_993, UInt<1>(0h1), "") : assert_49 node _T_997 = eq(io.in.a.bits.mask, mask) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_997, UInt<1>(0h1), "") : assert_50 node _T_1001 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1005 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_52 node _source_ok_T_4 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.d.bits.source, UInt<1>(0h1)) node _source_ok_T_6 = eq(io.in.d.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_4 connect _source_ok_WIRE_1[1], _source_ok_T_5 connect _source_ok_WIRE_1[2], _source_ok_T_6 node _source_ok_T_7 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_7, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1009 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1009 : node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(source_ok_1, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_54 node _T_1017 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_55 node _T_1021 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_56 node _T_1025 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_57 node _T_1029 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1029 : node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(source_ok_1, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(sink_ok, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1036 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_60 node _T_1040 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_61 node _T_1044 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_62 node _T_1048 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_63 node _T_1052 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1053 = or(UInt<1>(0h1), _T_1052) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_64 node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1057 : node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(source_ok_1, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(sink_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1064 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_67 node _T_1068 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_68 node _T_1072 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_69 node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1077 = or(_T_1076, io.in.d.bits.corrupt) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_70 node _T_1081 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1082 = or(UInt<1>(0h1), _T_1081) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_71 node _T_1086 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1086 : node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(source_ok_1, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1090 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_73 node _T_1094 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_74 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(UInt<1>(0h1), _T_1098) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_75 node _T_1103 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1103 : node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(source_ok_1, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1107 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_T_1107, UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1107, UInt<1>(0h1), "") : assert_77 node _T_1111 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1112 = or(_T_1111, io.in.d.bits.corrupt) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_78 node _T_1116 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1117 = or(UInt<1>(0h1), _T_1116) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_79 node _T_1121 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1121 : node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(source_ok_1, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1125 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_81 node _T_1129 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_82 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(UInt<1>(0h1), _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1138 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_84 node _T_1142 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) node _T_1144 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = or(_T_1143, _T_1148) node _T_1150 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<1>(0h0))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = or(_T_1151, _T_1156) node _T_1158 = eq(io.in.b.bits.source, UInt<2>(0h2)) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) node _T_1160 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1161 = cvt(_T_1160) node _T_1162 = and(_T_1161, asSInt(UInt<1>(0h0))) node _T_1163 = asSInt(_T_1162) node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0))) node _T_1165 = or(_T_1159, _T_1164) node _T_1166 = and(_T_1149, _T_1157) node _T_1167 = and(_T_1166, _T_1165) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _legal_source_T_2 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 connect _legal_source_WIRE[2], _legal_source_T_2 node _legal_source_T_3 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_4 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_5 = mux(_legal_source_WIRE[2], UInt<2>(0h2), UInt<1>(0h0)) node _legal_source_T_6 = or(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_7 = or(_legal_source_T_6, _legal_source_T_5) wire _legal_source_WIRE_1 : UInt<2> connect _legal_source_WIRE_1, _legal_source_T_7 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1171 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1171 : node _T_1172 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1173 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1174 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1172 connect _WIRE_4[1], _T_1173 connect _WIRE_4[2], _T_1174 node _T_1175 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1176 = mux(_WIRE_4[0], _T_1175, UInt<1>(0h0)) node _T_1177 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1178 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1179 = or(_T_1176, _T_1177) node _T_1180 = or(_T_1179, _T_1178) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1180 node _T_1181 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1182 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1183 = and(_T_1181, _T_1182) node _T_1184 = or(UInt<1>(0h0), _T_1183) node _T_1185 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1186 = cvt(_T_1185) node _T_1187 = and(_T_1186, asSInt(UInt<14>(0h2000))) node _T_1188 = asSInt(_T_1187) node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0))) node _T_1190 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<13>(0h1000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<17>(0h10000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1201 = cvt(_T_1200) node _T_1202 = and(_T_1201, asSInt(UInt<18>(0h2f000))) node _T_1203 = asSInt(_T_1202) node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0))) node _T_1205 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1206 = cvt(_T_1205) node _T_1207 = and(_T_1206, asSInt(UInt<17>(0h10000))) node _T_1208 = asSInt(_T_1207) node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0))) node _T_1210 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1211 = cvt(_T_1210) node _T_1212 = and(_T_1211, asSInt(UInt<13>(0h1000))) node _T_1213 = asSInt(_T_1212) node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1216 = cvt(_T_1215) node _T_1217 = and(_T_1216, asSInt(UInt<17>(0h10000))) node _T_1218 = asSInt(_T_1217) node _T_1219 = eq(_T_1218, asSInt(UInt<1>(0h0))) node _T_1220 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<27>(0h4000000))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<29>(0h10000000))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1189, _T_1194) node _T_1236 = or(_T_1235, _T_1199) node _T_1237 = or(_T_1236, _T_1204) node _T_1238 = or(_T_1237, _T_1209) node _T_1239 = or(_T_1238, _T_1214) node _T_1240 = or(_T_1239, _T_1219) node _T_1241 = or(_T_1240, _T_1224) node _T_1242 = or(_T_1241, _T_1229) node _T_1243 = or(_T_1242, _T_1234) node _T_1244 = and(_T_1184, _T_1243) node _T_1245 = or(UInt<1>(0h0), _T_1244) node _T_1246 = and(_WIRE_5, _T_1245) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_86 node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(address_ok, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(legal_source, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1259 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_90 node _T_1263 = eq(io.in.b.bits.mask, mask_1) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_91 node _T_1267 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(_T_1267, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1267, UInt<1>(0h1), "") : assert_92 node _T_1271 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1271 : node _T_1272 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1273 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1274 = and(_T_1272, _T_1273) node _T_1275 = or(UInt<1>(0h0), _T_1274) node _T_1276 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1277 = cvt(_T_1276) node _T_1278 = and(_T_1277, asSInt(UInt<14>(0h2000))) node _T_1279 = asSInt(_T_1278) node _T_1280 = eq(_T_1279, asSInt(UInt<1>(0h0))) node _T_1281 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1282 = cvt(_T_1281) node _T_1283 = and(_T_1282, asSInt(UInt<13>(0h1000))) node _T_1284 = asSInt(_T_1283) node _T_1285 = eq(_T_1284, asSInt(UInt<1>(0h0))) node _T_1286 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1287 = cvt(_T_1286) node _T_1288 = and(_T_1287, asSInt(UInt<17>(0h10000))) node _T_1289 = asSInt(_T_1288) node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0))) node _T_1291 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1292 = cvt(_T_1291) node _T_1293 = and(_T_1292, asSInt(UInt<18>(0h2f000))) node _T_1294 = asSInt(_T_1293) node _T_1295 = eq(_T_1294, asSInt(UInt<1>(0h0))) node _T_1296 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1297 = cvt(_T_1296) node _T_1298 = and(_T_1297, asSInt(UInt<17>(0h10000))) node _T_1299 = asSInt(_T_1298) node _T_1300 = eq(_T_1299, asSInt(UInt<1>(0h0))) node _T_1301 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1302 = cvt(_T_1301) node _T_1303 = and(_T_1302, asSInt(UInt<13>(0h1000))) node _T_1304 = asSInt(_T_1303) node _T_1305 = eq(_T_1304, asSInt(UInt<1>(0h0))) node _T_1306 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1307 = cvt(_T_1306) node _T_1308 = and(_T_1307, asSInt(UInt<17>(0h10000))) node _T_1309 = asSInt(_T_1308) node _T_1310 = eq(_T_1309, asSInt(UInt<1>(0h0))) node _T_1311 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1312 = cvt(_T_1311) node _T_1313 = and(_T_1312, asSInt(UInt<27>(0h4000000))) node _T_1314 = asSInt(_T_1313) node _T_1315 = eq(_T_1314, asSInt(UInt<1>(0h0))) node _T_1316 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1317 = cvt(_T_1316) node _T_1318 = and(_T_1317, asSInt(UInt<13>(0h1000))) node _T_1319 = asSInt(_T_1318) node _T_1320 = eq(_T_1319, asSInt(UInt<1>(0h0))) node _T_1321 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1322 = cvt(_T_1321) node _T_1323 = and(_T_1322, asSInt(UInt<29>(0h10000000))) node _T_1324 = asSInt(_T_1323) node _T_1325 = eq(_T_1324, asSInt(UInt<1>(0h0))) node _T_1326 = or(_T_1280, _T_1285) node _T_1327 = or(_T_1326, _T_1290) node _T_1328 = or(_T_1327, _T_1295) node _T_1329 = or(_T_1328, _T_1300) node _T_1330 = or(_T_1329, _T_1305) node _T_1331 = or(_T_1330, _T_1310) node _T_1332 = or(_T_1331, _T_1315) node _T_1333 = or(_T_1332, _T_1320) node _T_1334 = or(_T_1333, _T_1325) node _T_1335 = and(_T_1275, _T_1334) node _T_1336 = or(UInt<1>(0h0), _T_1335) node _T_1337 = and(UInt<1>(0h0), _T_1336) node _T_1338 = asUInt(reset) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) when _T_1339 : node _T_1340 = eq(_T_1337, UInt<1>(0h0)) when _T_1340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1337, UInt<1>(0h1), "") : assert_93 node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(address_ok, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(legal_source, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1350 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_97 node _T_1354 = eq(io.in.b.bits.mask, mask_1) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_98 node _T_1358 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_99 node _T_1362 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1362 : node _T_1363 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1364 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1365 = and(_T_1363, _T_1364) node _T_1366 = or(UInt<1>(0h0), _T_1365) node _T_1367 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1368 = cvt(_T_1367) node _T_1369 = and(_T_1368, asSInt(UInt<14>(0h2000))) node _T_1370 = asSInt(_T_1369) node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0))) node _T_1372 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1373 = cvt(_T_1372) node _T_1374 = and(_T_1373, asSInt(UInt<13>(0h1000))) node _T_1375 = asSInt(_T_1374) node _T_1376 = eq(_T_1375, asSInt(UInt<1>(0h0))) node _T_1377 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h10000))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<18>(0h2f000))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1388 = cvt(_T_1387) node _T_1389 = and(_T_1388, asSInt(UInt<17>(0h10000))) node _T_1390 = asSInt(_T_1389) node _T_1391 = eq(_T_1390, asSInt(UInt<1>(0h0))) node _T_1392 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1393 = cvt(_T_1392) node _T_1394 = and(_T_1393, asSInt(UInt<13>(0h1000))) node _T_1395 = asSInt(_T_1394) node _T_1396 = eq(_T_1395, asSInt(UInt<1>(0h0))) node _T_1397 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1398 = cvt(_T_1397) node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000))) node _T_1400 = asSInt(_T_1399) node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0))) node _T_1402 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1403 = cvt(_T_1402) node _T_1404 = and(_T_1403, asSInt(UInt<27>(0h4000000))) node _T_1405 = asSInt(_T_1404) node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0))) node _T_1407 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1408 = cvt(_T_1407) node _T_1409 = and(_T_1408, asSInt(UInt<13>(0h1000))) node _T_1410 = asSInt(_T_1409) node _T_1411 = eq(_T_1410, asSInt(UInt<1>(0h0))) node _T_1412 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1413 = cvt(_T_1412) node _T_1414 = and(_T_1413, asSInt(UInt<29>(0h10000000))) node _T_1415 = asSInt(_T_1414) node _T_1416 = eq(_T_1415, asSInt(UInt<1>(0h0))) node _T_1417 = or(_T_1371, _T_1376) node _T_1418 = or(_T_1417, _T_1381) node _T_1419 = or(_T_1418, _T_1386) node _T_1420 = or(_T_1419, _T_1391) node _T_1421 = or(_T_1420, _T_1396) node _T_1422 = or(_T_1421, _T_1401) node _T_1423 = or(_T_1422, _T_1406) node _T_1424 = or(_T_1423, _T_1411) node _T_1425 = or(_T_1424, _T_1416) node _T_1426 = and(_T_1366, _T_1425) node _T_1427 = or(UInt<1>(0h0), _T_1426) node _T_1428 = and(UInt<1>(0h0), _T_1427) node _T_1429 = asUInt(reset) node _T_1430 = eq(_T_1429, UInt<1>(0h0)) when _T_1430 : node _T_1431 = eq(_T_1428, UInt<1>(0h0)) when _T_1431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1428, UInt<1>(0h1), "") : assert_100 node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(address_ok, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1435 = asUInt(reset) node _T_1436 = eq(_T_1435, UInt<1>(0h0)) when _T_1436 : node _T_1437 = eq(legal_source, UInt<1>(0h0)) when _T_1437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1441 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_104 node _T_1445 = eq(io.in.b.bits.mask, mask_1) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_105 node _T_1449 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1449 : node _T_1450 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1451 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1452 = and(_T_1450, _T_1451) node _T_1453 = or(UInt<1>(0h0), _T_1452) node _T_1454 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1455 = cvt(_T_1454) node _T_1456 = and(_T_1455, asSInt(UInt<14>(0h2000))) node _T_1457 = asSInt(_T_1456) node _T_1458 = eq(_T_1457, asSInt(UInt<1>(0h0))) node _T_1459 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1460 = cvt(_T_1459) node _T_1461 = and(_T_1460, asSInt(UInt<13>(0h1000))) node _T_1462 = asSInt(_T_1461) node _T_1463 = eq(_T_1462, asSInt(UInt<1>(0h0))) node _T_1464 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1465 = cvt(_T_1464) node _T_1466 = and(_T_1465, asSInt(UInt<17>(0h10000))) node _T_1467 = asSInt(_T_1466) node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0))) node _T_1469 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1470 = cvt(_T_1469) node _T_1471 = and(_T_1470, asSInt(UInt<18>(0h2f000))) node _T_1472 = asSInt(_T_1471) node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0))) node _T_1474 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<17>(0h10000))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1480 = cvt(_T_1479) node _T_1481 = and(_T_1480, asSInt(UInt<13>(0h1000))) node _T_1482 = asSInt(_T_1481) node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0))) node _T_1484 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1485 = cvt(_T_1484) node _T_1486 = and(_T_1485, asSInt(UInt<17>(0h10000))) node _T_1487 = asSInt(_T_1486) node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0))) node _T_1489 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<27>(0h4000000))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1495 = cvt(_T_1494) node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000))) node _T_1497 = asSInt(_T_1496) node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0))) node _T_1499 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1500 = cvt(_T_1499) node _T_1501 = and(_T_1500, asSInt(UInt<29>(0h10000000))) node _T_1502 = asSInt(_T_1501) node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0))) node _T_1504 = or(_T_1458, _T_1463) node _T_1505 = or(_T_1504, _T_1468) node _T_1506 = or(_T_1505, _T_1473) node _T_1507 = or(_T_1506, _T_1478) node _T_1508 = or(_T_1507, _T_1483) node _T_1509 = or(_T_1508, _T_1488) node _T_1510 = or(_T_1509, _T_1493) node _T_1511 = or(_T_1510, _T_1498) node _T_1512 = or(_T_1511, _T_1503) node _T_1513 = and(_T_1453, _T_1512) node _T_1514 = or(UInt<1>(0h0), _T_1513) node _T_1515 = and(UInt<1>(0h0), _T_1514) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_106 node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(address_ok, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(legal_source, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1528 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_110 node _T_1532 = not(mask_1) node _T_1533 = and(io.in.b.bits.mask, _T_1532) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_111 node _T_1538 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1538 : node _T_1539 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1540 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1541 = and(_T_1539, _T_1540) node _T_1542 = or(UInt<1>(0h0), _T_1541) node _T_1543 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1544 = cvt(_T_1543) node _T_1545 = and(_T_1544, asSInt(UInt<14>(0h2000))) node _T_1546 = asSInt(_T_1545) node _T_1547 = eq(_T_1546, asSInt(UInt<1>(0h0))) node _T_1548 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1549 = cvt(_T_1548) node _T_1550 = and(_T_1549, asSInt(UInt<13>(0h1000))) node _T_1551 = asSInt(_T_1550) node _T_1552 = eq(_T_1551, asSInt(UInt<1>(0h0))) node _T_1553 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1554 = cvt(_T_1553) node _T_1555 = and(_T_1554, asSInt(UInt<17>(0h10000))) node _T_1556 = asSInt(_T_1555) node _T_1557 = eq(_T_1556, asSInt(UInt<1>(0h0))) node _T_1558 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1559 = cvt(_T_1558) node _T_1560 = and(_T_1559, asSInt(UInt<18>(0h2f000))) node _T_1561 = asSInt(_T_1560) node _T_1562 = eq(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1564 = cvt(_T_1563) node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000))) node _T_1566 = asSInt(_T_1565) node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0))) node _T_1568 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<13>(0h1000))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1574 = cvt(_T_1573) node _T_1575 = and(_T_1574, asSInt(UInt<17>(0h10000))) node _T_1576 = asSInt(_T_1575) node _T_1577 = eq(_T_1576, asSInt(UInt<1>(0h0))) node _T_1578 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1579 = cvt(_T_1578) node _T_1580 = and(_T_1579, asSInt(UInt<27>(0h4000000))) node _T_1581 = asSInt(_T_1580) node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0))) node _T_1583 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1584 = cvt(_T_1583) node _T_1585 = and(_T_1584, asSInt(UInt<13>(0h1000))) node _T_1586 = asSInt(_T_1585) node _T_1587 = eq(_T_1586, asSInt(UInt<1>(0h0))) node _T_1588 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1589 = cvt(_T_1588) node _T_1590 = and(_T_1589, asSInt(UInt<29>(0h10000000))) node _T_1591 = asSInt(_T_1590) node _T_1592 = eq(_T_1591, asSInt(UInt<1>(0h0))) node _T_1593 = or(_T_1547, _T_1552) node _T_1594 = or(_T_1593, _T_1557) node _T_1595 = or(_T_1594, _T_1562) node _T_1596 = or(_T_1595, _T_1567) node _T_1597 = or(_T_1596, _T_1572) node _T_1598 = or(_T_1597, _T_1577) node _T_1599 = or(_T_1598, _T_1582) node _T_1600 = or(_T_1599, _T_1587) node _T_1601 = or(_T_1600, _T_1592) node _T_1602 = and(_T_1542, _T_1601) node _T_1603 = or(UInt<1>(0h0), _T_1602) node _T_1604 = and(UInt<1>(0h0), _T_1603) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_112 node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(address_ok, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(legal_source, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1617 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_116 node _T_1621 = eq(io.in.b.bits.mask, mask_1) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_117 node _T_1625 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1625 : node _T_1626 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1627 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1628 = and(_T_1626, _T_1627) node _T_1629 = or(UInt<1>(0h0), _T_1628) node _T_1630 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1631 = cvt(_T_1630) node _T_1632 = and(_T_1631, asSInt(UInt<14>(0h2000))) node _T_1633 = asSInt(_T_1632) node _T_1634 = eq(_T_1633, asSInt(UInt<1>(0h0))) node _T_1635 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1636 = cvt(_T_1635) node _T_1637 = and(_T_1636, asSInt(UInt<13>(0h1000))) node _T_1638 = asSInt(_T_1637) node _T_1639 = eq(_T_1638, asSInt(UInt<1>(0h0))) node _T_1640 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1641 = cvt(_T_1640) node _T_1642 = and(_T_1641, asSInt(UInt<17>(0h10000))) node _T_1643 = asSInt(_T_1642) node _T_1644 = eq(_T_1643, asSInt(UInt<1>(0h0))) node _T_1645 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1646 = cvt(_T_1645) node _T_1647 = and(_T_1646, asSInt(UInt<18>(0h2f000))) node _T_1648 = asSInt(_T_1647) node _T_1649 = eq(_T_1648, asSInt(UInt<1>(0h0))) node _T_1650 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1651 = cvt(_T_1650) node _T_1652 = and(_T_1651, asSInt(UInt<17>(0h10000))) node _T_1653 = asSInt(_T_1652) node _T_1654 = eq(_T_1653, asSInt(UInt<1>(0h0))) node _T_1655 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1656 = cvt(_T_1655) node _T_1657 = and(_T_1656, asSInt(UInt<13>(0h1000))) node _T_1658 = asSInt(_T_1657) node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0))) node _T_1660 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1661 = cvt(_T_1660) node _T_1662 = and(_T_1661, asSInt(UInt<17>(0h10000))) node _T_1663 = asSInt(_T_1662) node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0))) node _T_1665 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1666 = cvt(_T_1665) node _T_1667 = and(_T_1666, asSInt(UInt<27>(0h4000000))) node _T_1668 = asSInt(_T_1667) node _T_1669 = eq(_T_1668, asSInt(UInt<1>(0h0))) node _T_1670 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1671 = cvt(_T_1670) node _T_1672 = and(_T_1671, asSInt(UInt<13>(0h1000))) node _T_1673 = asSInt(_T_1672) node _T_1674 = eq(_T_1673, asSInt(UInt<1>(0h0))) node _T_1675 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1676 = cvt(_T_1675) node _T_1677 = and(_T_1676, asSInt(UInt<29>(0h10000000))) node _T_1678 = asSInt(_T_1677) node _T_1679 = eq(_T_1678, asSInt(UInt<1>(0h0))) node _T_1680 = or(_T_1634, _T_1639) node _T_1681 = or(_T_1680, _T_1644) node _T_1682 = or(_T_1681, _T_1649) node _T_1683 = or(_T_1682, _T_1654) node _T_1684 = or(_T_1683, _T_1659) node _T_1685 = or(_T_1684, _T_1664) node _T_1686 = or(_T_1685, _T_1669) node _T_1687 = or(_T_1686, _T_1674) node _T_1688 = or(_T_1687, _T_1679) node _T_1689 = and(_T_1629, _T_1688) node _T_1690 = or(UInt<1>(0h0), _T_1689) node _T_1691 = and(UInt<1>(0h0), _T_1690) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_118 node _T_1695 = asUInt(reset) node _T_1696 = eq(_T_1695, UInt<1>(0h0)) when _T_1696 : node _T_1697 = eq(address_ok, UInt<1>(0h0)) when _T_1697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1698 = asUInt(reset) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) when _T_1699 : node _T_1700 = eq(legal_source, UInt<1>(0h0)) when _T_1700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1701 = asUInt(reset) node _T_1702 = eq(_T_1701, UInt<1>(0h0)) when _T_1702 : node _T_1703 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1704 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(_T_1704, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1704, UInt<1>(0h1), "") : assert_122 node _T_1708 = eq(io.in.b.bits.mask, mask_1) node _T_1709 = asUInt(reset) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(_T_1708, UInt<1>(0h0)) when _T_1711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1708, UInt<1>(0h1), "") : assert_123 node _T_1712 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1712 : node _T_1713 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1714 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1715 = and(_T_1713, _T_1714) node _T_1716 = or(UInt<1>(0h0), _T_1715) node _T_1717 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1718 = cvt(_T_1717) node _T_1719 = and(_T_1718, asSInt(UInt<14>(0h2000))) node _T_1720 = asSInt(_T_1719) node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0))) node _T_1722 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1723 = cvt(_T_1722) node _T_1724 = and(_T_1723, asSInt(UInt<13>(0h1000))) node _T_1725 = asSInt(_T_1724) node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0))) node _T_1727 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1728 = cvt(_T_1727) node _T_1729 = and(_T_1728, asSInt(UInt<17>(0h10000))) node _T_1730 = asSInt(_T_1729) node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0))) node _T_1732 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1733 = cvt(_T_1732) node _T_1734 = and(_T_1733, asSInt(UInt<18>(0h2f000))) node _T_1735 = asSInt(_T_1734) node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0))) node _T_1737 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1738 = cvt(_T_1737) node _T_1739 = and(_T_1738, asSInt(UInt<17>(0h10000))) node _T_1740 = asSInt(_T_1739) node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0))) node _T_1742 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1743 = cvt(_T_1742) node _T_1744 = and(_T_1743, asSInt(UInt<13>(0h1000))) node _T_1745 = asSInt(_T_1744) node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1748 = cvt(_T_1747) node _T_1749 = and(_T_1748, asSInt(UInt<17>(0h10000))) node _T_1750 = asSInt(_T_1749) node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0))) node _T_1752 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<27>(0h4000000))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1758 = cvt(_T_1757) node _T_1759 = and(_T_1758, asSInt(UInt<13>(0h1000))) node _T_1760 = asSInt(_T_1759) node _T_1761 = eq(_T_1760, asSInt(UInt<1>(0h0))) node _T_1762 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<29>(0h10000000))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1721, _T_1726) node _T_1768 = or(_T_1767, _T_1731) node _T_1769 = or(_T_1768, _T_1736) node _T_1770 = or(_T_1769, _T_1741) node _T_1771 = or(_T_1770, _T_1746) node _T_1772 = or(_T_1771, _T_1751) node _T_1773 = or(_T_1772, _T_1756) node _T_1774 = or(_T_1773, _T_1761) node _T_1775 = or(_T_1774, _T_1766) node _T_1776 = and(_T_1716, _T_1775) node _T_1777 = or(UInt<1>(0h0), _T_1776) node _T_1778 = and(UInt<1>(0h0), _T_1777) node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(_T_1778, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1778, UInt<1>(0h1), "") : assert_124 node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(address_ok, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1785 = asUInt(reset) node _T_1786 = eq(_T_1785, UInt<1>(0h0)) when _T_1786 : node _T_1787 = eq(legal_source, UInt<1>(0h0)) when _T_1787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1791 = eq(io.in.b.bits.mask, mask_1) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_128 node _T_1795 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1796 = asUInt(reset) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) when _T_1797 : node _T_1798 = eq(_T_1795, UInt<1>(0h0)) when _T_1798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1795, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1799 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_130 node _source_ok_T_8 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_9 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _source_ok_T_10 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_8 connect _source_ok_WIRE_2[1], _source_ok_T_9 connect _source_ok_WIRE_2[2], _source_ok_T_10 node _source_ok_T_11 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_11, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _T_1803 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) node _T_1805 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1806 = cvt(_T_1805) node _T_1807 = and(_T_1806, asSInt(UInt<1>(0h0))) node _T_1808 = asSInt(_T_1807) node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0))) node _T_1810 = or(_T_1804, _T_1809) node _T_1811 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1812 = eq(_T_1811, UInt<1>(0h0)) node _T_1813 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1814 = cvt(_T_1813) node _T_1815 = and(_T_1814, asSInt(UInt<1>(0h0))) node _T_1816 = asSInt(_T_1815) node _T_1817 = eq(_T_1816, asSInt(UInt<1>(0h0))) node _T_1818 = or(_T_1812, _T_1817) node _T_1819 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1820 = eq(_T_1819, UInt<1>(0h0)) node _T_1821 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1822 = cvt(_T_1821) node _T_1823 = and(_T_1822, asSInt(UInt<1>(0h0))) node _T_1824 = asSInt(_T_1823) node _T_1825 = eq(_T_1824, asSInt(UInt<1>(0h0))) node _T_1826 = or(_T_1820, _T_1825) node _T_1827 = and(_T_1810, _T_1818) node _T_1828 = and(_T_1827, _T_1826) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_131 node _T_1832 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1832 : node _T_1833 = asUInt(reset) node _T_1834 = eq(_T_1833, UInt<1>(0h0)) when _T_1834 : node _T_1835 = eq(address_ok_1, UInt<1>(0h0)) when _T_1835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1836 = asUInt(reset) node _T_1837 = eq(_T_1836, UInt<1>(0h0)) when _T_1837 : node _T_1838 = eq(source_ok_2, UInt<1>(0h0)) when _T_1838 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1839 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1840 = asUInt(reset) node _T_1841 = eq(_T_1840, UInt<1>(0h0)) when _T_1841 : node _T_1842 = eq(_T_1839, UInt<1>(0h0)) when _T_1842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1839, UInt<1>(0h1), "") : assert_134 node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1846 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_136 node _T_1850 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(_T_1850, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1850, UInt<1>(0h1), "") : assert_137 node _T_1854 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1854 : node _T_1855 = asUInt(reset) node _T_1856 = eq(_T_1855, UInt<1>(0h0)) when _T_1856 : node _T_1857 = eq(address_ok_1, UInt<1>(0h0)) when _T_1857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(source_ok_2, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1861 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(_T_1861, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1861, UInt<1>(0h1), "") : assert_140 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1868 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_142 node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1872 : node _T_1873 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1874 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1875 = and(_T_1873, _T_1874) node _T_1876 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1877 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1878 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1879 = or(_T_1876, _T_1877) node _T_1880 = or(_T_1879, _T_1878) node _T_1881 = and(_T_1875, _T_1880) node _T_1882 = or(UInt<1>(0h0), _T_1881) node _T_1883 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1884 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1885 = cvt(_T_1884) node _T_1886 = and(_T_1885, asSInt(UInt<14>(0h2000))) node _T_1887 = asSInt(_T_1886) node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0))) node _T_1889 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1890 = cvt(_T_1889) node _T_1891 = and(_T_1890, asSInt(UInt<13>(0h1000))) node _T_1892 = asSInt(_T_1891) node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1895 = cvt(_T_1894) node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000))) node _T_1897 = asSInt(_T_1896) node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0))) node _T_1899 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1900 = cvt(_T_1899) node _T_1901 = and(_T_1900, asSInt(UInt<18>(0h2f000))) node _T_1902 = asSInt(_T_1901) node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1905 = cvt(_T_1904) node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000))) node _T_1907 = asSInt(_T_1906) node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1910 = cvt(_T_1909) node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000))) node _T_1912 = asSInt(_T_1911) node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0))) node _T_1914 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1915 = cvt(_T_1914) node _T_1916 = and(_T_1915, asSInt(UInt<27>(0h4000000))) node _T_1917 = asSInt(_T_1916) node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0))) node _T_1919 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1920 = cvt(_T_1919) node _T_1921 = and(_T_1920, asSInt(UInt<13>(0h1000))) node _T_1922 = asSInt(_T_1921) node _T_1923 = eq(_T_1922, asSInt(UInt<1>(0h0))) node _T_1924 = or(_T_1888, _T_1893) node _T_1925 = or(_T_1924, _T_1898) node _T_1926 = or(_T_1925, _T_1903) node _T_1927 = or(_T_1926, _T_1908) node _T_1928 = or(_T_1927, _T_1913) node _T_1929 = or(_T_1928, _T_1918) node _T_1930 = or(_T_1929, _T_1923) node _T_1931 = and(_T_1883, _T_1930) node _T_1932 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1933 = or(UInt<1>(0h0), _T_1932) node _T_1934 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1935 = cvt(_T_1934) node _T_1936 = and(_T_1935, asSInt(UInt<17>(0h10000))) node _T_1937 = asSInt(_T_1936) node _T_1938 = eq(_T_1937, asSInt(UInt<1>(0h0))) node _T_1939 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1940 = cvt(_T_1939) node _T_1941 = and(_T_1940, asSInt(UInt<29>(0h10000000))) node _T_1942 = asSInt(_T_1941) node _T_1943 = eq(_T_1942, asSInt(UInt<1>(0h0))) node _T_1944 = or(_T_1938, _T_1943) node _T_1945 = and(_T_1933, _T_1944) node _T_1946 = or(UInt<1>(0h0), _T_1931) node _T_1947 = or(_T_1946, _T_1945) node _T_1948 = and(_T_1882, _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_143 node _T_1952 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1953 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1954 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_1952 connect _WIRE_6[1], _T_1953 connect _WIRE_6[2], _T_1954 node _T_1955 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1956 = mux(_WIRE_6[0], _T_1955, UInt<1>(0h0)) node _T_1957 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1958 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1959 = or(_T_1956, _T_1957) node _T_1960 = or(_T_1959, _T_1958) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1960 node _T_1961 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1962 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1963 = and(_T_1961, _T_1962) node _T_1964 = or(UInt<1>(0h0), _T_1963) node _T_1965 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1966 = cvt(_T_1965) node _T_1967 = and(_T_1966, asSInt(UInt<14>(0h2000))) node _T_1968 = asSInt(_T_1967) node _T_1969 = eq(_T_1968, asSInt(UInt<1>(0h0))) node _T_1970 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1971 = cvt(_T_1970) node _T_1972 = and(_T_1971, asSInt(UInt<13>(0h1000))) node _T_1973 = asSInt(_T_1972) node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0))) node _T_1975 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<17>(0h10000))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1981 = cvt(_T_1980) node _T_1982 = and(_T_1981, asSInt(UInt<18>(0h2f000))) node _T_1983 = asSInt(_T_1982) node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0))) node _T_1985 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1986 = cvt(_T_1985) node _T_1987 = and(_T_1986, asSInt(UInt<17>(0h10000))) node _T_1988 = asSInt(_T_1987) node _T_1989 = eq(_T_1988, asSInt(UInt<1>(0h0))) node _T_1990 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1991 = cvt(_T_1990) node _T_1992 = and(_T_1991, asSInt(UInt<13>(0h1000))) node _T_1993 = asSInt(_T_1992) node _T_1994 = eq(_T_1993, asSInt(UInt<1>(0h0))) node _T_1995 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1996 = cvt(_T_1995) node _T_1997 = and(_T_1996, asSInt(UInt<17>(0h10000))) node _T_1998 = asSInt(_T_1997) node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0))) node _T_2000 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2001 = cvt(_T_2000) node _T_2002 = and(_T_2001, asSInt(UInt<27>(0h4000000))) node _T_2003 = asSInt(_T_2002) node _T_2004 = eq(_T_2003, asSInt(UInt<1>(0h0))) node _T_2005 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2006 = cvt(_T_2005) node _T_2007 = and(_T_2006, asSInt(UInt<13>(0h1000))) node _T_2008 = asSInt(_T_2007) node _T_2009 = eq(_T_2008, asSInt(UInt<1>(0h0))) node _T_2010 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2011 = cvt(_T_2010) node _T_2012 = and(_T_2011, asSInt(UInt<29>(0h10000000))) node _T_2013 = asSInt(_T_2012) node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0))) node _T_2015 = or(_T_1969, _T_1974) node _T_2016 = or(_T_2015, _T_1979) node _T_2017 = or(_T_2016, _T_1984) node _T_2018 = or(_T_2017, _T_1989) node _T_2019 = or(_T_2018, _T_1994) node _T_2020 = or(_T_2019, _T_1999) node _T_2021 = or(_T_2020, _T_2004) node _T_2022 = or(_T_2021, _T_2009) node _T_2023 = or(_T_2022, _T_2014) node _T_2024 = and(_T_1964, _T_2023) node _T_2025 = or(UInt<1>(0h0), _T_2024) node _T_2026 = and(_WIRE_7, _T_2025) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_144 node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(source_ok_2, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2033 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_146 node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2040 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_148 node _T_2044 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_149 node _T_2048 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2048 : node _T_2049 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2050 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2051 = and(_T_2049, _T_2050) node _T_2052 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2053 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2054 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_2055 = or(_T_2052, _T_2053) node _T_2056 = or(_T_2055, _T_2054) node _T_2057 = and(_T_2051, _T_2056) node _T_2058 = or(UInt<1>(0h0), _T_2057) node _T_2059 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2060 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<14>(0h2000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<13>(0h1000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<17>(0h10000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<18>(0h2f000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<17>(0h10000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = or(_T_2064, _T_2069) node _T_2101 = or(_T_2100, _T_2074) node _T_2102 = or(_T_2101, _T_2079) node _T_2103 = or(_T_2102, _T_2084) node _T_2104 = or(_T_2103, _T_2089) node _T_2105 = or(_T_2104, _T_2094) node _T_2106 = or(_T_2105, _T_2099) node _T_2107 = and(_T_2059, _T_2106) node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2109 = or(UInt<1>(0h0), _T_2108) node _T_2110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2111 = cvt(_T_2110) node _T_2112 = and(_T_2111, asSInt(UInt<17>(0h10000))) node _T_2113 = asSInt(_T_2112) node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0))) node _T_2115 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2116 = cvt(_T_2115) node _T_2117 = and(_T_2116, asSInt(UInt<29>(0h10000000))) node _T_2118 = asSInt(_T_2117) node _T_2119 = eq(_T_2118, asSInt(UInt<1>(0h0))) node _T_2120 = or(_T_2114, _T_2119) node _T_2121 = and(_T_2109, _T_2120) node _T_2122 = or(UInt<1>(0h0), _T_2107) node _T_2123 = or(_T_2122, _T_2121) node _T_2124 = and(_T_2058, _T_2123) node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(_T_2124, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2124, UInt<1>(0h1), "") : assert_150 node _T_2128 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2130 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2128 connect _WIRE_8[1], _T_2129 connect _WIRE_8[2], _T_2130 node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2132 = mux(_WIRE_8[0], _T_2131, UInt<1>(0h0)) node _T_2133 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2134 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2135 = or(_T_2132, _T_2133) node _T_2136 = or(_T_2135, _T_2134) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2136 node _T_2137 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2138 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2139 = and(_T_2137, _T_2138) node _T_2140 = or(UInt<1>(0h0), _T_2139) node _T_2141 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2142 = cvt(_T_2141) node _T_2143 = and(_T_2142, asSInt(UInt<14>(0h2000))) node _T_2144 = asSInt(_T_2143) node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0))) node _T_2146 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2147 = cvt(_T_2146) node _T_2148 = and(_T_2147, asSInt(UInt<13>(0h1000))) node _T_2149 = asSInt(_T_2148) node _T_2150 = eq(_T_2149, asSInt(UInt<1>(0h0))) node _T_2151 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2152 = cvt(_T_2151) node _T_2153 = and(_T_2152, asSInt(UInt<17>(0h10000))) node _T_2154 = asSInt(_T_2153) node _T_2155 = eq(_T_2154, asSInt(UInt<1>(0h0))) node _T_2156 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2157 = cvt(_T_2156) node _T_2158 = and(_T_2157, asSInt(UInt<18>(0h2f000))) node _T_2159 = asSInt(_T_2158) node _T_2160 = eq(_T_2159, asSInt(UInt<1>(0h0))) node _T_2161 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2162 = cvt(_T_2161) node _T_2163 = and(_T_2162, asSInt(UInt<17>(0h10000))) node _T_2164 = asSInt(_T_2163) node _T_2165 = eq(_T_2164, asSInt(UInt<1>(0h0))) node _T_2166 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2167 = cvt(_T_2166) node _T_2168 = and(_T_2167, asSInt(UInt<13>(0h1000))) node _T_2169 = asSInt(_T_2168) node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0))) node _T_2171 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2172 = cvt(_T_2171) node _T_2173 = and(_T_2172, asSInt(UInt<17>(0h10000))) node _T_2174 = asSInt(_T_2173) node _T_2175 = eq(_T_2174, asSInt(UInt<1>(0h0))) node _T_2176 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2177 = cvt(_T_2176) node _T_2178 = and(_T_2177, asSInt(UInt<27>(0h4000000))) node _T_2179 = asSInt(_T_2178) node _T_2180 = eq(_T_2179, asSInt(UInt<1>(0h0))) node _T_2181 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2182 = cvt(_T_2181) node _T_2183 = and(_T_2182, asSInt(UInt<13>(0h1000))) node _T_2184 = asSInt(_T_2183) node _T_2185 = eq(_T_2184, asSInt(UInt<1>(0h0))) node _T_2186 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2187 = cvt(_T_2186) node _T_2188 = and(_T_2187, asSInt(UInt<29>(0h10000000))) node _T_2189 = asSInt(_T_2188) node _T_2190 = eq(_T_2189, asSInt(UInt<1>(0h0))) node _T_2191 = or(_T_2145, _T_2150) node _T_2192 = or(_T_2191, _T_2155) node _T_2193 = or(_T_2192, _T_2160) node _T_2194 = or(_T_2193, _T_2165) node _T_2195 = or(_T_2194, _T_2170) node _T_2196 = or(_T_2195, _T_2175) node _T_2197 = or(_T_2196, _T_2180) node _T_2198 = or(_T_2197, _T_2185) node _T_2199 = or(_T_2198, _T_2190) node _T_2200 = and(_T_2140, _T_2199) node _T_2201 = or(UInt<1>(0h0), _T_2200) node _T_2202 = and(_WIRE_9, _T_2201) node _T_2203 = asUInt(reset) node _T_2204 = eq(_T_2203, UInt<1>(0h0)) when _T_2204 : node _T_2205 = eq(_T_2202, UInt<1>(0h0)) when _T_2205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2202, UInt<1>(0h1), "") : assert_151 node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : node _T_2208 = eq(source_ok_2, UInt<1>(0h0)) when _T_2208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2209 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_153 node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2216 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2217 = asUInt(reset) node _T_2218 = eq(_T_2217, UInt<1>(0h0)) when _T_2218 : node _T_2219 = eq(_T_2216, UInt<1>(0h0)) when _T_2219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2216, UInt<1>(0h1), "") : assert_155 node _T_2220 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2220 : node _T_2221 = asUInt(reset) node _T_2222 = eq(_T_2221, UInt<1>(0h0)) when _T_2222 : node _T_2223 = eq(address_ok_1, UInt<1>(0h0)) when _T_2223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(source_ok_2, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2230 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_159 node _T_2234 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2235 = asUInt(reset) node _T_2236 = eq(_T_2235, UInt<1>(0h0)) when _T_2236 : node _T_2237 = eq(_T_2234, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2234, UInt<1>(0h1), "") : assert_160 node _T_2238 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2238 : node _T_2239 = asUInt(reset) node _T_2240 = eq(_T_2239, UInt<1>(0h0)) when _T_2240 : node _T_2241 = eq(address_ok_1, UInt<1>(0h0)) when _T_2241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(source_ok_2, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2248 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_164 node _T_2252 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2252 : node _T_2253 = asUInt(reset) node _T_2254 = eq(_T_2253, UInt<1>(0h0)) when _T_2254 : node _T_2255 = eq(address_ok_1, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2256 = asUInt(reset) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) when _T_2257 : node _T_2258 = eq(source_ok_2, UInt<1>(0h0)) when _T_2258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2262 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_168 node _T_2266 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(_T_2266, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2266, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2273 = eq(a_first, UInt<1>(0h0)) node _T_2274 = and(io.in.a.valid, _T_2273) when _T_2274 : node _T_2275 = eq(io.in.a.bits.opcode, opcode) node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : node _T_2278 = eq(_T_2275, UInt<1>(0h0)) when _T_2278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2275, UInt<1>(0h1), "") : assert_171 node _T_2279 = eq(io.in.a.bits.param, param) node _T_2280 = asUInt(reset) node _T_2281 = eq(_T_2280, UInt<1>(0h0)) when _T_2281 : node _T_2282 = eq(_T_2279, UInt<1>(0h0)) when _T_2282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2279, UInt<1>(0h1), "") : assert_172 node _T_2283 = eq(io.in.a.bits.size, size) node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(_T_2283, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2283, UInt<1>(0h1), "") : assert_173 node _T_2287 = eq(io.in.a.bits.source, source) node _T_2288 = asUInt(reset) node _T_2289 = eq(_T_2288, UInt<1>(0h0)) when _T_2289 : node _T_2290 = eq(_T_2287, UInt<1>(0h0)) when _T_2290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2287, UInt<1>(0h1), "") : assert_174 node _T_2291 = eq(io.in.a.bits.address, address) node _T_2292 = asUInt(reset) node _T_2293 = eq(_T_2292, UInt<1>(0h0)) when _T_2293 : node _T_2294 = eq(_T_2291, UInt<1>(0h0)) when _T_2294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2291, UInt<1>(0h1), "") : assert_175 node _T_2295 = and(io.in.a.ready, io.in.a.valid) node _T_2296 = and(_T_2295, a_first) when _T_2296 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2297 = eq(d_first, UInt<1>(0h0)) node _T_2298 = and(io.in.d.valid, _T_2297) when _T_2298 : node _T_2299 = eq(io.in.d.bits.opcode, opcode_1) node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : node _T_2302 = eq(_T_2299, UInt<1>(0h0)) when _T_2302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2299, UInt<1>(0h1), "") : assert_176 node _T_2303 = eq(io.in.d.bits.param, param_1) node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(_T_2303, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2303, UInt<1>(0h1), "") : assert_177 node _T_2307 = eq(io.in.d.bits.size, size_1) node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : node _T_2310 = eq(_T_2307, UInt<1>(0h0)) when _T_2310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2307, UInt<1>(0h1), "") : assert_178 node _T_2311 = eq(io.in.d.bits.source, source_1) node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : node _T_2314 = eq(_T_2311, UInt<1>(0h0)) when _T_2314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2311, UInt<1>(0h1), "") : assert_179 node _T_2315 = eq(io.in.d.bits.sink, sink) node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : node _T_2318 = eq(_T_2315, UInt<1>(0h0)) when _T_2318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2315, UInt<1>(0h1), "") : assert_180 node _T_2319 = eq(io.in.d.bits.denied, denied) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_181 node _T_2323 = and(io.in.d.ready, io.in.d.valid) node _T_2324 = and(_T_2323, d_first) when _T_2324 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2325 = eq(b_first, UInt<1>(0h0)) node _T_2326 = and(io.in.b.valid, _T_2325) when _T_2326 : node _T_2327 = eq(io.in.b.bits.opcode, opcode_2) node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : node _T_2330 = eq(_T_2327, UInt<1>(0h0)) when _T_2330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2327, UInt<1>(0h1), "") : assert_182 node _T_2331 = eq(io.in.b.bits.param, param_2) node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(_T_2331, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2331, UInt<1>(0h1), "") : assert_183 node _T_2335 = eq(io.in.b.bits.size, size_2) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_184 node _T_2339 = eq(io.in.b.bits.source, source_2) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_185 node _T_2343 = eq(io.in.b.bits.address, address_1) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_186 node _T_2347 = and(io.in.b.ready, io.in.b.valid) node _T_2348 = and(_T_2347, b_first) when _T_2348 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2349 = eq(c_first, UInt<1>(0h0)) node _T_2350 = and(io.in.c.valid, _T_2349) when _T_2350 : node _T_2351 = eq(io.in.c.bits.opcode, opcode_3) node _T_2352 = asUInt(reset) node _T_2353 = eq(_T_2352, UInt<1>(0h0)) when _T_2353 : node _T_2354 = eq(_T_2351, UInt<1>(0h0)) when _T_2354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2351, UInt<1>(0h1), "") : assert_187 node _T_2355 = eq(io.in.c.bits.param, param_3) node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(_T_2355, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2355, UInt<1>(0h1), "") : assert_188 node _T_2359 = eq(io.in.c.bits.size, size_3) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(_T_2359, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2359, UInt<1>(0h1), "") : assert_189 node _T_2363 = eq(io.in.c.bits.source, source_3) node _T_2364 = asUInt(reset) node _T_2365 = eq(_T_2364, UInt<1>(0h0)) when _T_2365 : node _T_2366 = eq(_T_2363, UInt<1>(0h0)) when _T_2366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2363, UInt<1>(0h1), "") : assert_190 node _T_2367 = eq(io.in.c.bits.address, address_2) node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(_T_2367, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2367, UInt<1>(0h1), "") : assert_191 node _T_2371 = and(io.in.c.ready, io.in.c.valid) node _T_2372 = and(_T_2371, c_first) when _T_2372 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes : UInt<24>, clock, reset, UInt<24>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<3> connect a_set, UInt<3>(0h0) wire a_set_wo_ready : UInt<3> connect a_set_wo_ready, UInt<3>(0h0) wire a_opcodes_set : UInt<12> connect a_opcodes_set, UInt<12>(0h0) wire a_sizes_set : UInt<24> connect a_sizes_set, UInt<24>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2373 = and(io.in.a.valid, a_first_1) node _T_2374 = and(_T_2373, UInt<1>(0h1)) when _T_2374 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2375 = and(io.in.a.ready, io.in.a.valid) node _T_2376 = and(_T_2375, a_first_1) node _T_2377 = and(_T_2376, UInt<1>(0h1)) when _T_2377 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2378 = dshr(inflight, io.in.a.bits.source) node _T_2379 = bits(_T_2378, 0, 0) node _T_2380 = eq(_T_2379, UInt<1>(0h0)) node _T_2381 = asUInt(reset) node _T_2382 = eq(_T_2381, UInt<1>(0h0)) when _T_2382 : node _T_2383 = eq(_T_2380, UInt<1>(0h0)) when _T_2383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2380, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<3> connect d_clr, UInt<3>(0h0) wire d_clr_wo_ready : UInt<3> connect d_clr_wo_ready, UInt<3>(0h0) wire d_opcodes_clr : UInt<12> connect d_opcodes_clr, UInt<12>(0h0) wire d_sizes_clr : UInt<24> connect d_sizes_clr, UInt<24>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2384 = and(io.in.d.valid, d_first_1) node _T_2385 = and(_T_2384, UInt<1>(0h1)) node _T_2386 = eq(d_release_ack, UInt<1>(0h0)) node _T_2387 = and(_T_2385, _T_2386) when _T_2387 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2388 = and(io.in.d.ready, io.in.d.valid) node _T_2389 = and(_T_2388, d_first_1) node _T_2390 = and(_T_2389, UInt<1>(0h1)) node _T_2391 = eq(d_release_ack, UInt<1>(0h0)) node _T_2392 = and(_T_2390, _T_2391) when _T_2392 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2393 = and(io.in.d.valid, d_first_1) node _T_2394 = and(_T_2393, UInt<1>(0h1)) node _T_2395 = eq(d_release_ack, UInt<1>(0h0)) node _T_2396 = and(_T_2394, _T_2395) when _T_2396 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2397 = dshr(inflight, io.in.d.bits.source) node _T_2398 = bits(_T_2397, 0, 0) node _T_2399 = or(_T_2398, same_cycle_resp) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2403 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2404 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2405 = or(_T_2403, _T_2404) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_194 node _T_2409 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_195 else : node _T_2413 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2414 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2415 = or(_T_2413, _T_2414) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_196 node _T_2419 = eq(io.in.d.bits.size, a_size_lookup) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_197 node _T_2423 = and(io.in.d.valid, d_first_1) node _T_2424 = and(_T_2423, a_first_1) node _T_2425 = and(_T_2424, io.in.a.valid) node _T_2426 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2427 = and(_T_2425, _T_2426) node _T_2428 = eq(d_release_ack, UInt<1>(0h0)) node _T_2429 = and(_T_2427, _T_2428) when _T_2429 : node _T_2430 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2431 = or(_T_2430, io.in.a.ready) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_198 node _T_2435 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2436 = orr(a_set_wo_ready) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) node _T_2438 = or(_T_2435, _T_2437) node _T_2439 = asUInt(reset) node _T_2440 = eq(_T_2439, UInt<1>(0h0)) when _T_2440 : node _T_2441 = eq(_T_2438, UInt<1>(0h0)) when _T_2441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2438, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_2 node _T_2442 = orr(inflight) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) node _T_2444 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2445 = or(_T_2443, _T_2444) node _T_2446 = lt(watchdog, plusarg_reader.out) node _T_2447 = or(_T_2445, _T_2446) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2451 = and(io.in.a.ready, io.in.a.valid) node _T_2452 = and(io.in.d.ready, io.in.d.valid) node _T_2453 = or(_T_2451, _T_2452) when _T_2453 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes_1 : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes_1 : UInt<24>, clock, reset, UInt<24>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<3> connect c_set, UInt<3>(0h0) wire c_set_wo_ready : UInt<3> connect c_set_wo_ready, UInt<3>(0h0) wire c_opcodes_set : UInt<12> connect c_opcodes_set, UInt<12>(0h0) wire c_sizes_set : UInt<24> connect c_sizes_set, UInt<24>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2454 = and(io.in.c.valid, c_first_1) node _T_2455 = bits(io.in.c.bits.opcode, 2, 2) node _T_2456 = bits(io.in.c.bits.opcode, 1, 1) node _T_2457 = and(_T_2455, _T_2456) node _T_2458 = and(_T_2454, _T_2457) when _T_2458 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2459 = and(io.in.c.ready, io.in.c.valid) node _T_2460 = and(_T_2459, c_first_1) node _T_2461 = bits(io.in.c.bits.opcode, 2, 2) node _T_2462 = bits(io.in.c.bits.opcode, 1, 1) node _T_2463 = and(_T_2461, _T_2462) node _T_2464 = and(_T_2460, _T_2463) when _T_2464 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2465 = dshr(inflight_1, io.in.c.bits.source) node _T_2466 = bits(_T_2465, 0, 0) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<3> connect d_clr_1, UInt<3>(0h0) wire d_clr_wo_ready_1 : UInt<3> connect d_clr_wo_ready_1, UInt<3>(0h0) wire d_opcodes_clr_1 : UInt<12> connect d_opcodes_clr_1, UInt<12>(0h0) wire d_sizes_clr_1 : UInt<24> connect d_sizes_clr_1, UInt<24>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2471 = and(io.in.d.valid, d_first_2) node _T_2472 = and(_T_2471, UInt<1>(0h1)) node _T_2473 = and(_T_2472, d_release_ack_1) when _T_2473 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2474 = and(io.in.d.ready, io.in.d.valid) node _T_2475 = and(_T_2474, d_first_2) node _T_2476 = and(_T_2475, UInt<1>(0h1)) node _T_2477 = and(_T_2476, d_release_ack_1) when _T_2477 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2478 = and(io.in.d.valid, d_first_2) node _T_2479 = and(_T_2478, UInt<1>(0h1)) node _T_2480 = and(_T_2479, d_release_ack_1) when _T_2480 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2481 = dshr(inflight_1, io.in.d.bits.source) node _T_2482 = bits(_T_2481, 0, 0) node _T_2483 = or(_T_2482, same_cycle_resp_1) node _T_2484 = asUInt(reset) node _T_2485 = eq(_T_2484, UInt<1>(0h0)) when _T_2485 : node _T_2486 = eq(_T_2483, UInt<1>(0h0)) when _T_2486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2483, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2487 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2488 = asUInt(reset) node _T_2489 = eq(_T_2488, UInt<1>(0h0)) when _T_2489 : node _T_2490 = eq(_T_2487, UInt<1>(0h0)) when _T_2490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2487, UInt<1>(0h1), "") : assert_203 else : node _T_2491 = eq(io.in.d.bits.size, c_size_lookup) node _T_2492 = asUInt(reset) node _T_2493 = eq(_T_2492, UInt<1>(0h0)) when _T_2493 : node _T_2494 = eq(_T_2491, UInt<1>(0h0)) when _T_2494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2491, UInt<1>(0h1), "") : assert_204 node _T_2495 = and(io.in.d.valid, d_first_2) node _T_2496 = and(_T_2495, c_first_1) node _T_2497 = and(_T_2496, io.in.c.valid) node _T_2498 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2499 = and(_T_2497, _T_2498) node _T_2500 = and(_T_2499, d_release_ack_1) node _T_2501 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2502 = and(_T_2500, _T_2501) when _T_2502 : node _T_2503 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2504 = or(_T_2503, io.in.c.ready) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_205 node _T_2508 = orr(c_set_wo_ready) when _T_2508 : node _T_2509 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_3 node _T_2513 = orr(inflight_1) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) node _T_2515 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2516 = or(_T_2514, _T_2515) node _T_2517 = lt(watchdog_1, plusarg_reader_1.out) node _T_2518 = or(_T_2516, _T_2517) node _T_2519 = asUInt(reset) node _T_2520 = eq(_T_2519, UInt<1>(0h0)) when _T_2520 : node _T_2521 = eq(_T_2518, UInt<1>(0h0)) when _T_2521 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2518, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2522 = and(io.in.c.ready, io.in.c.valid) node _T_2523 = and(io.in.d.ready, io.in.d.valid) node _T_2524 = or(_T_2522, _T_2523) when _T_2524 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2525 = and(io.in.d.ready, io.in.d.valid) node _T_2526 = and(_T_2525, d_first_3) node _T_2527 = bits(io.in.d.bits.opcode, 2, 2) node _T_2528 = bits(io.in.d.bits.opcode, 1, 1) node _T_2529 = eq(_T_2528, UInt<1>(0h0)) node _T_2530 = and(_T_2527, _T_2529) node _T_2531 = and(_T_2526, _T_2530) when _T_2531 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2532 = dshr(inflight_2, io.in.d.bits.sink) node _T_2533 = bits(_T_2532, 0, 0) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) node _T_2535 = asUInt(reset) node _T_2536 = eq(_T_2535, UInt<1>(0h0)) when _T_2536 : node _T_2537 = eq(_T_2534, UInt<1>(0h0)) when _T_2537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2534, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2538 = and(io.in.e.ready, io.in.e.valid) node _T_2539 = and(_T_2538, UInt<1>(0h1)) node _T_2540 = and(_T_2539, UInt<1>(0h1)) when _T_2540 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2541 = or(d_set, inflight_2) node _T_2542 = dshr(_T_2541, io.in.e.bits.sink) node _T_2543 = bits(_T_2542, 0, 0) node _T_2544 = asUInt(reset) node _T_2545 = eq(_T_2544, UInt<1>(0h0)) when _T_2545 : node _T_2546 = eq(_T_2543, UInt<1>(0h0)) when _T_2546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2543, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [1:0] io_in_b_bits_source = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _legal_source_T_5 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1 = 2'h0; // @[Mux.scala:30:73] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_1 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73] wire _legal_source_T_4 = 1'h0; // @[Mux.scala:30:73] wire _legal_source_T_6 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35] wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_20 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46] wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_22 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_23 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_24 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_24; // @[OneHot.scala:58:35] assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _GEN_25 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module TLDebugModuleInnerAsync : output auto : { flip dmiXing_in : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}, dmInner_sb2tlOpt_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, flip dmInner_custom_in : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>}, flip dmInner_tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip debug_clock : Clock, flip debug_reset : Reset, flip tl_clock : Clock, flip tl_reset : Reset, flip dmactive : UInt<1>, flip innerCtrl : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[8], hrmask : UInt<1>[8]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip debugUnavail : UInt<1>[8], hgDebugInt : UInt<1>[8], flip hartIsInReset : UInt<1>[8]} input rf_reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst dmInner of TLDebugModuleInner connect dmInner.clock, childClock connect dmInner.reset, childReset inst dmiXing of TLAsyncCrossingSink_a9d32s1k1z2u connect dmiXing.clock, childClock connect dmiXing.reset, childReset connect dmInner.auto.dmi_in, dmiXing.auto.out connect dmInner.auto.tl_in, auto.dmInner_tl_in connect dmInner.auto.custom_in, auto.dmInner_custom_in connect dmInner.auto.sb2tlOpt_out.d, auto.dmInner_sb2tlOpt_out.d connect auto.dmInner_sb2tlOpt_out.a.bits, dmInner.auto.sb2tlOpt_out.a.bits connect auto.dmInner_sb2tlOpt_out.a.valid, dmInner.auto.sb2tlOpt_out.a.valid connect dmInner.auto.sb2tlOpt_out.a.ready, auto.dmInner_sb2tlOpt_out.a.ready connect dmiXing.auto.in, auto.dmiXing_in connect childClock, io.debug_clock connect childReset, io.debug_reset inst dmactive_synced_dmactive_synced_dmactiveSync of AsyncResetSynchronizerShiftReg_w1_d3_i0_34 connect dmactive_synced_dmactive_synced_dmactiveSync.clock, childClock connect dmactive_synced_dmactive_synced_dmactiveSync.reset, childReset connect dmactive_synced_dmactive_synced_dmactiveSync.io.d, io.dmactive wire dmactive_synced : UInt<1> connect dmactive_synced, dmactive_synced_dmactive_synced_dmactiveSync.io.q connect dmInner.clock, io.debug_clock connect dmInner.reset, io.debug_reset connect dmInner.io.tl_clock, io.tl_clock connect dmInner.io.tl_reset, io.tl_reset connect dmInner.io.dmactive, dmactive_synced inst dmactive_synced_dmInner_io_innerCtrl_sink of AsyncQueueSink_DebugInternalBundle connect dmactive_synced_dmInner_io_innerCtrl_sink.clock, childClock connect dmactive_synced_dmInner_io_innerCtrl_sink.reset, childReset connect dmactive_synced_dmInner_io_innerCtrl_sink.io.async, io.innerCtrl connect dmInner.io.innerCtrl, dmactive_synced_dmInner_io_innerCtrl_sink.io.deq connect dmInner.io.debugUnavail[0], io.debugUnavail[0] connect dmInner.io.debugUnavail[1], io.debugUnavail[1] connect dmInner.io.debugUnavail[2], io.debugUnavail[2] connect dmInner.io.debugUnavail[3], io.debugUnavail[3] connect dmInner.io.debugUnavail[4], io.debugUnavail[4] connect dmInner.io.debugUnavail[5], io.debugUnavail[5] connect dmInner.io.debugUnavail[6], io.debugUnavail[6] connect dmInner.io.debugUnavail[7], io.debugUnavail[7] connect io.hgDebugInt, dmInner.io.hgDebugInt connect dmInner.io.hartIsInReset[0], io.hartIsInReset[0] connect dmInner.io.hartIsInReset[1], io.hartIsInReset[1] connect dmInner.io.hartIsInReset[2], io.hartIsInReset[2] connect dmInner.io.hartIsInReset[3], io.hartIsInReset[3] connect dmInner.io.hartIsInReset[4], io.hartIsInReset[4] connect dmInner.io.hartIsInReset[5], io.hartIsInReset[5] connect dmInner.io.hartIsInReset[6], io.hartIsInReset[6] connect dmInner.io.hartIsInReset[7], io.hartIsInReset[7]

module TLDebugModuleInnerAsync( // @[Debug.scala:1871:9] input [2:0] auto_dmiXing_in_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmiXing_in_a_mem_0_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmiXing_in_a_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_ridx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_widx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmiXing_in_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmiXing_in_d_mem_0_size, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_mem_0_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmiXing_in_d_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_ridx, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_widx, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_dmiXing_in_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmiXing_in_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmInner_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmInner_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmInner_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_dmInner_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_dmInner_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_dmInner_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_dmInner_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmInner_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmInner_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmInner_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmInner_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_dmInner_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_dmInner_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_debug_clock, // @[Debug.scala:1877:16] input io_debug_reset, // @[Debug.scala:1877:16] input io_tl_clock, // @[Debug.scala:1877:16] input io_tl_reset, // @[Debug.scala:1877:16] input io_dmactive, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_resumereq, // @[Debug.scala:1877:16] input [9:0] io_innerCtrl_mem_0_hartsel, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_ackhavereset, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hasel, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_0, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_1, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_2, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_3, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_4, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_5, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_6, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hamask_7, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_0, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_1, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_2, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_3, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_4, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_5, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_6, // @[Debug.scala:1877:16] input io_innerCtrl_mem_0_hrmask_7, // @[Debug.scala:1877:16] output io_innerCtrl_ridx, // @[Debug.scala:1877:16] input io_innerCtrl_widx, // @[Debug.scala:1877:16] output io_innerCtrl_safe_ridx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_widx_valid, // @[Debug.scala:1877:16] input io_innerCtrl_safe_source_reset_n, // @[Debug.scala:1877:16] output io_innerCtrl_safe_sink_reset_n, // @[Debug.scala:1877:16] output io_hgDebugInt_0, // @[Debug.scala:1877:16] output io_hgDebugInt_1, // @[Debug.scala:1877:16] output io_hgDebugInt_2, // @[Debug.scala:1877:16] output io_hgDebugInt_3, // @[Debug.scala:1877:16] output io_hgDebugInt_4, // @[Debug.scala:1877:16] output io_hgDebugInt_5, // @[Debug.scala:1877:16] output io_hgDebugInt_6, // @[Debug.scala:1877:16] output io_hgDebugInt_7, // @[Debug.scala:1877:16] input io_hartIsInReset_0, // @[Debug.scala:1877:16] input io_hartIsInReset_1, // @[Debug.scala:1877:16] input io_hartIsInReset_2, // @[Debug.scala:1877:16] input io_hartIsInReset_3, // @[Debug.scala:1877:16] input io_hartIsInReset_4, // @[Debug.scala:1877:16] input io_hartIsInReset_5, // @[Debug.scala:1877:16] input io_hartIsInReset_6, // @[Debug.scala:1877:16] input io_hartIsInReset_7, // @[Debug.scala:1877:16] input rf_reset // @[Debug.scala:1904:22] ); wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[AsyncQueue.scala:211:22] wire [9:0] _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_1; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_2; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_3; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_4; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_5; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_6; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_7; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_1; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_2; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_3; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_4; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_5; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_6; // @[AsyncQueue.scala:211:22] wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_7; // @[AsyncQueue.scala:211:22] wire _dmiXing_auto_out_a_valid; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_opcode; // @[Debug.scala:1858:27] wire [2:0] _dmiXing_auto_out_a_bits_param; // @[Debug.scala:1858:27] wire [1:0] _dmiXing_auto_out_a_bits_size; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_source; // @[Debug.scala:1858:27] wire [8:0] _dmiXing_auto_out_a_bits_address; // @[Debug.scala:1858:27] wire [3:0] _dmiXing_auto_out_a_bits_mask; // @[Debug.scala:1858:27] wire [31:0] _dmiXing_auto_out_a_bits_data; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_a_bits_corrupt; // @[Debug.scala:1858:27] wire _dmiXing_auto_out_d_ready; // @[Debug.scala:1858:27] wire _dmInner_auto_dmi_in_a_ready; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_valid; // @[Debug.scala:1857:27] wire [2:0] _dmInner_auto_dmi_in_d_bits_opcode; // @[Debug.scala:1857:27] wire [1:0] _dmInner_auto_dmi_in_d_bits_size; // @[Debug.scala:1857:27] wire _dmInner_auto_dmi_in_d_bits_source; // @[Debug.scala:1857:27] wire [31:0] _dmInner_auto_dmi_in_d_bits_data; // @[Debug.scala:1857:27] wire [2:0] auto_dmiXing_in_a_mem_0_opcode_0 = auto_dmiXing_in_a_mem_0_opcode; // @[Debug.scala:1871:9] wire [8:0] auto_dmiXing_in_a_mem_0_address_0 = auto_dmiXing_in_a_mem_0_address; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_a_mem_0_data_0 = auto_dmiXing_in_a_mem_0_data; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_widx_0 = auto_dmiXing_in_a_widx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_widx_valid_0 = auto_dmiXing_in_a_safe_widx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_source_reset_n_0 = auto_dmiXing_in_a_safe_source_reset_n; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_ridx_0 = auto_dmiXing_in_d_ridx; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_ridx_valid_0 = auto_dmiXing_in_d_safe_ridx_valid; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_sink_reset_n_0 = auto_dmiXing_in_d_safe_sink_reset_n; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_ready_0 = auto_dmInner_sb2tlOpt_out_a_ready; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_valid_0 = auto_dmInner_sb2tlOpt_out_d_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode_0 = auto_dmInner_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param_0 = auto_dmInner_sb2tlOpt_out_d_bits_param; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size_0 = auto_dmInner_sb2tlOpt_out_d_bits_size; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_d_bits_sink_0 = auto_dmInner_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_denied_0 = auto_dmInner_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data_0 = auto_dmInner_sb2tlOpt_out_d_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0 = auto_dmInner_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_valid_0 = auto_dmInner_tl_in_a_valid; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_opcode_0 = auto_dmInner_tl_in_a_bits_opcode; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_a_bits_param_0 = auto_dmInner_tl_in_a_bits_param; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_a_bits_size_0 = auto_dmInner_tl_in_a_bits_size; // @[Debug.scala:1871:9] wire [10:0] auto_dmInner_tl_in_a_bits_source_0 = auto_dmInner_tl_in_a_bits_source; // @[Debug.scala:1871:9] wire [11:0] auto_dmInner_tl_in_a_bits_address_0 = auto_dmInner_tl_in_a_bits_address; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_tl_in_a_bits_mask_0 = auto_dmInner_tl_in_a_bits_mask; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_a_bits_data_0 = auto_dmInner_tl_in_a_bits_data; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_bits_corrupt_0 = auto_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_ready_0 = auto_dmInner_tl_in_d_ready; // @[Debug.scala:1871:9] wire io_debug_clock_0 = io_debug_clock; // @[Debug.scala:1871:9] wire io_debug_reset_0 = io_debug_reset; // @[Debug.scala:1871:9] wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:1871:9] wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:1871:9] wire io_dmactive_0 = io_dmactive; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_resumereq_0 = io_innerCtrl_mem_0_resumereq; // @[Debug.scala:1871:9] wire [9:0] io_innerCtrl_mem_0_hartsel_0 = io_innerCtrl_mem_0_hartsel; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_ackhavereset_0 = io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hasel_0 = io_innerCtrl_mem_0_hasel; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_0_0 = io_innerCtrl_mem_0_hamask_0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_1_0 = io_innerCtrl_mem_0_hamask_1; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_2_0 = io_innerCtrl_mem_0_hamask_2; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_3_0 = io_innerCtrl_mem_0_hamask_3; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_4_0 = io_innerCtrl_mem_0_hamask_4; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_5_0 = io_innerCtrl_mem_0_hamask_5; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_6_0 = io_innerCtrl_mem_0_hamask_6; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hamask_7_0 = io_innerCtrl_mem_0_hamask_7; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_0_0 = io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_1_0 = io_innerCtrl_mem_0_hrmask_1; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_2_0 = io_innerCtrl_mem_0_hrmask_2; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_3_0 = io_innerCtrl_mem_0_hrmask_3; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_4_0 = io_innerCtrl_mem_0_hrmask_4; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_5_0 = io_innerCtrl_mem_0_hrmask_5; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_6_0 = io_innerCtrl_mem_0_hrmask_6; // @[Debug.scala:1871:9] wire io_innerCtrl_mem_0_hrmask_7_0 = io_innerCtrl_mem_0_hrmask_7; // @[Debug.scala:1871:9] wire io_innerCtrl_widx_0 = io_innerCtrl_widx; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_widx_valid_0 = io_innerCtrl_safe_widx_valid; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_source_reset_n_0 = io_innerCtrl_safe_source_reset_n; // @[Debug.scala:1871:9] wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:1871:9] wire io_hartIsInReset_1_0 = io_hartIsInReset_1; // @[Debug.scala:1871:9] wire io_hartIsInReset_2_0 = io_hartIsInReset_2; // @[Debug.scala:1871:9] wire io_hartIsInReset_3_0 = io_hartIsInReset_3; // @[Debug.scala:1871:9] wire io_hartIsInReset_4_0 = io_hartIsInReset_4; // @[Debug.scala:1871:9] wire io_hartIsInReset_5_0 = io_hartIsInReset_5; // @[Debug.scala:1871:9] wire io_hartIsInReset_6_0 = io_hartIsInReset_6; // @[Debug.scala:1871:9] wire io_hartIsInReset_7_0 = io_hartIsInReset_7; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_b_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_c_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_mem_0_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_ridx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_widx = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_e_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_addr = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_ready = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_custom_in_valid = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_1 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_2 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_3 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_4 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_5 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_6 = 1'h0; // @[Debug.scala:1871:9] wire io_debugUnavail_7 = 1'h0; // @[Debug.scala:1871:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire auto_dmInner_sb2tlOpt_out_a_bits_mask = 1'h1; // @[AsyncQueue.scala:211:22] wire [31:0] auto_dmiXing_in_b_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [31:0] auto_dmiXing_in_c_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9] wire [3:0] auto_dmiXing_in_b_mem_0_mask = 4'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_b_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [8:0] auto_dmiXing_in_c_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_b_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_c_mem_0_size = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_param = 2'h0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_param = 2'h0; // @[Debug.scala:1871:9] wire [3:0] auto_dmiXing_in_a_mem_0_mask = 4'hF; // @[Debug.scala:1858:27, :1871:9] wire [1:0] auto_dmiXing_in_a_mem_0_size = 2'h2; // @[Debug.scala:1858:27, :1871:9] wire [2:0] auto_dmiXing_in_a_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_b_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_c_mem_0_param = 3'h0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:1871:9] wire childClock = io_debug_clock_0; // @[Debug.scala:1871:9] wire childReset = io_debug_reset_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] wire auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] wire [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] wire [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] wire [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] wire auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] wire [2:0] auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] wire [1:0] auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] wire [10:0] auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] wire [63:0] auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] wire auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] wire io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] wire io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_0_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_1_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_2_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_3_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_4_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_5_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_6_0; // @[Debug.scala:1871:9] wire io_hgDebugInt_7_0; // @[Debug.scala:1871:9] wire dmactive_synced; // @[ShiftReg.scala:48:24] TLDebugModuleInner dmInner ( // @[Debug.scala:1857:27] .clock (io_debug_clock_0), // @[Debug.scala:1871:9] .reset (io_debug_reset_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_ready (auto_dmInner_sb2tlOpt_out_a_ready_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_a_valid (auto_dmInner_sb2tlOpt_out_a_valid_0), .auto_sb2tlOpt_out_a_bits_opcode (auto_dmInner_sb2tlOpt_out_a_bits_opcode_0), .auto_sb2tlOpt_out_a_bits_size (auto_dmInner_sb2tlOpt_out_a_bits_size_0), .auto_sb2tlOpt_out_a_bits_address (auto_dmInner_sb2tlOpt_out_a_bits_address_0), .auto_sb2tlOpt_out_a_bits_data (auto_dmInner_sb2tlOpt_out_a_bits_data_0), .auto_sb2tlOpt_out_d_ready (auto_dmInner_sb2tlOpt_out_d_ready_0), .auto_sb2tlOpt_out_d_valid (auto_dmInner_sb2tlOpt_out_d_valid_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_opcode (auto_dmInner_sb2tlOpt_out_d_bits_opcode_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_param (auto_dmInner_sb2tlOpt_out_d_bits_param_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_size (auto_dmInner_sb2tlOpt_out_d_bits_size_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_sink (auto_dmInner_sb2tlOpt_out_d_bits_sink_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_denied (auto_dmInner_sb2tlOpt_out_d_bits_denied_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_data (auto_dmInner_sb2tlOpt_out_d_bits_data_0), // @[Debug.scala:1871:9] .auto_sb2tlOpt_out_d_bits_corrupt (auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_a_ready (auto_dmInner_tl_in_a_ready_0), .auto_tl_in_a_valid (auto_dmInner_tl_in_a_valid_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_opcode (auto_dmInner_tl_in_a_bits_opcode_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_param (auto_dmInner_tl_in_a_bits_param_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_size (auto_dmInner_tl_in_a_bits_size_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_source (auto_dmInner_tl_in_a_bits_source_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_address (auto_dmInner_tl_in_a_bits_address_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_mask (auto_dmInner_tl_in_a_bits_mask_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_data (auto_dmInner_tl_in_a_bits_data_0), // @[Debug.scala:1871:9] .auto_tl_in_a_bits_corrupt (auto_dmInner_tl_in_a_bits_corrupt_0), // @[Debug.scala:1871:9] .auto_tl_in_d_ready (auto_dmInner_tl_in_d_ready_0), // @[Debug.scala:1871:9] .auto_tl_in_d_valid (auto_dmInner_tl_in_d_valid_0), .auto_tl_in_d_bits_opcode (auto_dmInner_tl_in_d_bits_opcode_0), .auto_tl_in_d_bits_size (auto_dmInner_tl_in_d_bits_size_0), .auto_tl_in_d_bits_source (auto_dmInner_tl_in_d_bits_source_0), .auto_tl_in_d_bits_data (auto_dmInner_tl_in_d_bits_data_0), .auto_dmi_in_a_ready (_dmInner_auto_dmi_in_a_ready), .auto_dmi_in_a_valid (_dmiXing_auto_out_a_valid), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_param (_dmiXing_auto_out_a_bits_param), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_size (_dmiXing_auto_out_a_bits_size), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_source (_dmiXing_auto_out_a_bits_source), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_address (_dmiXing_auto_out_a_bits_address), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_mask (_dmiXing_auto_out_a_bits_mask), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_data (_dmiXing_auto_out_a_bits_data), // @[Debug.scala:1858:27] .auto_dmi_in_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), // @[Debug.scala:1858:27] .auto_dmi_in_d_ready (_dmiXing_auto_out_d_ready), // @[Debug.scala:1858:27] .auto_dmi_in_d_valid (_dmInner_auto_dmi_in_d_valid), .auto_dmi_in_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), .auto_dmi_in_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), .auto_dmi_in_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), .auto_dmi_in_d_bits_data (_dmInner_auto_dmi_in_d_bits_data), .io_dmactive (dmactive_synced), // @[ShiftReg.scala:48:24] .io_innerCtrl_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_1), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_2), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_3), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_4 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_4), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_5 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_5), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_6 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_6), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hamask_7 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_7), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_1), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_2), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_3), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_4 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_4), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_5 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_5), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_6 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_6), // @[AsyncQueue.scala:211:22] .io_innerCtrl_bits_hrmask_7 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_7), // @[AsyncQueue.scala:211:22] .io_hgDebugInt_0 (io_hgDebugInt_0_0), .io_hgDebugInt_1 (io_hgDebugInt_1_0), .io_hgDebugInt_2 (io_hgDebugInt_2_0), .io_hgDebugInt_3 (io_hgDebugInt_3_0), .io_hgDebugInt_4 (io_hgDebugInt_4_0), .io_hgDebugInt_5 (io_hgDebugInt_5_0), .io_hgDebugInt_6 (io_hgDebugInt_6_0), .io_hgDebugInt_7 (io_hgDebugInt_7_0), .io_hartIsInReset_0 (io_hartIsInReset_0_0), // @[Debug.scala:1871:9] .io_hartIsInReset_1 (io_hartIsInReset_1_0), // @[Debug.scala:1871:9] .io_hartIsInReset_2 (io_hartIsInReset_2_0), // @[Debug.scala:1871:9] .io_hartIsInReset_3 (io_hartIsInReset_3_0), // @[Debug.scala:1871:9] .io_hartIsInReset_4 (io_hartIsInReset_4_0), // @[Debug.scala:1871:9] .io_hartIsInReset_5 (io_hartIsInReset_5_0), // @[Debug.scala:1871:9] .io_hartIsInReset_6 (io_hartIsInReset_6_0), // @[Debug.scala:1871:9] .io_hartIsInReset_7 (io_hartIsInReset_7_0), // @[Debug.scala:1871:9] .io_tl_clock (io_tl_clock_0), // @[Debug.scala:1871:9] .io_tl_reset (io_tl_reset_0) // @[Debug.scala:1871:9] ); // @[Debug.scala:1857:27] TLAsyncCrossingSink_a9d32s1k1z2u dmiXing ( // @[Debug.scala:1858:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_mem_0_opcode (auto_dmiXing_in_a_mem_0_opcode_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_address (auto_dmiXing_in_a_mem_0_address_0), // @[Debug.scala:1871:9] .auto_in_a_mem_0_data (auto_dmiXing_in_a_mem_0_data_0), // @[Debug.scala:1871:9] .auto_in_a_ridx (auto_dmiXing_in_a_ridx_0), .auto_in_a_widx (auto_dmiXing_in_a_widx_0), // @[Debug.scala:1871:9] .auto_in_a_safe_ridx_valid (auto_dmiXing_in_a_safe_ridx_valid_0), .auto_in_a_safe_widx_valid (auto_dmiXing_in_a_safe_widx_valid_0), // @[Debug.scala:1871:9] .auto_in_a_safe_source_reset_n (auto_dmiXing_in_a_safe_source_reset_n_0), // @[Debug.scala:1871:9] .auto_in_a_safe_sink_reset_n (auto_dmiXing_in_a_safe_sink_reset_n_0), .auto_in_d_mem_0_opcode (auto_dmiXing_in_d_mem_0_opcode_0), .auto_in_d_mem_0_size (auto_dmiXing_in_d_mem_0_size_0), .auto_in_d_mem_0_source (auto_dmiXing_in_d_mem_0_source_0), .auto_in_d_mem_0_data (auto_dmiXing_in_d_mem_0_data_0), .auto_in_d_ridx (auto_dmiXing_in_d_ridx_0), // @[Debug.scala:1871:9] .auto_in_d_widx (auto_dmiXing_in_d_widx_0), .auto_in_d_safe_ridx_valid (auto_dmiXing_in_d_safe_ridx_valid_0), // @[Debug.scala:1871:9] .auto_in_d_safe_widx_valid (auto_dmiXing_in_d_safe_widx_valid_0), .auto_in_d_safe_source_reset_n (auto_dmiXing_in_d_safe_source_reset_n_0), .auto_in_d_safe_sink_reset_n (auto_dmiXing_in_d_safe_sink_reset_n_0), // @[Debug.scala:1871:9] .auto_out_a_ready (_dmInner_auto_dmi_in_a_ready), // @[Debug.scala:1857:27] .auto_out_a_valid (_dmiXing_auto_out_a_valid), .auto_out_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), .auto_out_a_bits_param (_dmiXing_auto_out_a_bits_param), .auto_out_a_bits_size (_dmiXing_auto_out_a_bits_size), .auto_out_a_bits_source (_dmiXing_auto_out_a_bits_source), .auto_out_a_bits_address (_dmiXing_auto_out_a_bits_address), .auto_out_a_bits_mask (_dmiXing_auto_out_a_bits_mask), .auto_out_a_bits_data (_dmiXing_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), .auto_out_d_ready (_dmiXing_auto_out_d_ready), .auto_out_d_valid (_dmInner_auto_dmi_in_d_valid), // @[Debug.scala:1857:27] .auto_out_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), // @[Debug.scala:1857:27] .auto_out_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), // @[Debug.scala:1857:27] .auto_out_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), // @[Debug.scala:1857:27] .auto_out_d_bits_data (_dmInner_auto_dmi_in_d_bits_data) // @[Debug.scala:1857:27] ); // @[Debug.scala:1858:27] AsyncResetSynchronizerShiftReg_w1_d3_i0_34 dmactive_synced_dmactive_synced_dmactiveSync ( // @[ShiftReg.scala:45:23] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_d (io_dmactive_0), // @[Debug.scala:1871:9] .io_q (dmactive_synced) ); // @[ShiftReg.scala:45:23] AsyncQueueSink_DebugInternalBundle dmactive_synced_dmInner_io_innerCtrl_sink ( // @[AsyncQueue.scala:211:22] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_deq_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), .io_deq_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), .io_deq_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), .io_deq_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), .io_deq_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), .io_deq_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), .io_deq_bits_hamask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_1), .io_deq_bits_hamask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_2), .io_deq_bits_hamask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_3), .io_deq_bits_hamask_4 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_4), .io_deq_bits_hamask_5 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_5), .io_deq_bits_hamask_6 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_6), .io_deq_bits_hamask_7 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_7), .io_deq_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), .io_deq_bits_hrmask_1 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_1), .io_deq_bits_hrmask_2 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_2), .io_deq_bits_hrmask_3 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_3), .io_deq_bits_hrmask_4 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_4), .io_deq_bits_hrmask_5 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_5), .io_deq_bits_hrmask_6 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_6), .io_deq_bits_hrmask_7 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_7), .io_async_mem_0_resumereq (io_innerCtrl_mem_0_resumereq_0), // @[Debug.scala:1871:9] .io_async_mem_0_hartsel (io_innerCtrl_mem_0_hartsel_0), // @[Debug.scala:1871:9] .io_async_mem_0_ackhavereset (io_innerCtrl_mem_0_ackhavereset_0), // @[Debug.scala:1871:9] .io_async_mem_0_hasel (io_innerCtrl_mem_0_hasel_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_0 (io_innerCtrl_mem_0_hamask_0_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_1 (io_innerCtrl_mem_0_hamask_1_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_2 (io_innerCtrl_mem_0_hamask_2_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_3 (io_innerCtrl_mem_0_hamask_3_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_4 (io_innerCtrl_mem_0_hamask_4_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_5 (io_innerCtrl_mem_0_hamask_5_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_6 (io_innerCtrl_mem_0_hamask_6_0), // @[Debug.scala:1871:9] .io_async_mem_0_hamask_7 (io_innerCtrl_mem_0_hamask_7_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_0 (io_innerCtrl_mem_0_hrmask_0_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_1 (io_innerCtrl_mem_0_hrmask_1_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_2 (io_innerCtrl_mem_0_hrmask_2_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_3 (io_innerCtrl_mem_0_hrmask_3_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_4 (io_innerCtrl_mem_0_hrmask_4_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_5 (io_innerCtrl_mem_0_hrmask_5_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_6 (io_innerCtrl_mem_0_hrmask_6_0), // @[Debug.scala:1871:9] .io_async_mem_0_hrmask_7 (io_innerCtrl_mem_0_hrmask_7_0), // @[Debug.scala:1871:9] .io_async_ridx (io_innerCtrl_ridx_0), .io_async_widx (io_innerCtrl_widx_0), // @[Debug.scala:1871:9] .io_async_safe_ridx_valid (io_innerCtrl_safe_ridx_valid_0), .io_async_safe_widx_valid (io_innerCtrl_safe_widx_valid_0), // @[Debug.scala:1871:9] .io_async_safe_source_reset_n (io_innerCtrl_safe_source_reset_n_0), // @[Debug.scala:1871:9] .io_async_safe_sink_reset_n (io_innerCtrl_safe_sink_reset_n_0) ); // @[AsyncQueue.scala:211:22] assign auto_dmiXing_in_a_ridx = auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_ridx_valid = auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_a_safe_sink_reset_n = auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_opcode = auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_size = auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_source = auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_mem_0_data = auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_widx = auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_widx_valid = auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9] assign auto_dmiXing_in_d_safe_source_reset_n = auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_valid = auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_opcode = auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_size = auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_address = auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_a_bits_data = auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9] assign auto_dmInner_sb2tlOpt_out_d_ready = auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_a_ready = auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_valid = auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_opcode = auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_size = auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_source = auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9] assign auto_dmInner_tl_in_d_bits_data = auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9] assign io_innerCtrl_ridx = io_innerCtrl_ridx_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_ridx_valid = io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9] assign io_innerCtrl_safe_sink_reset_n = io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_0 = io_hgDebugInt_0_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_1 = io_hgDebugInt_1_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_2 = io_hgDebugInt_2_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_3 = io_hgDebugInt_3_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_4 = io_hgDebugInt_4_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_5 = io_hgDebugInt_5_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_6 = io_hgDebugInt_6_0; // @[Debug.scala:1871:9] assign io_hgDebugInt_7 = io_hgDebugInt_7_0; // @[Debug.scala:1871:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_22 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] connect auto.out, nodeOut connect nodeIn, auto.in inst reg of AsyncResetRegVec_w1_i0_22 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] connect reg.io.en, UInt<1>(0h1) node _T = bits(reg.io.q, 0, 0) connect nodeOut.sync[0], _T

module IntSyncCrossingSource_n1x1_22( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset // @[Crossing.scala:41:9] ); wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9] wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:41:9] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] AsyncResetRegVec_w1_i0_22 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset) ); // @[AsyncResetReg.scala:86:21] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a32d256s5k3z4u_2 : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)

module Repeater_TLBundleA_a32d256s5k3z4u_2( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [4:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [255:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [4:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output [255:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [4:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [255:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [4:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [255:0] io_deq_bits_data_0; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [4:0] saved_source; // @[Repeater.scala:21:18] reg [31:0] saved_address; // @[Repeater.scala:21:18] reg [31:0] saved_mask; // @[Repeater.scala:21:18] reg [255:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_52 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<17>(0h10000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = and(_T_207, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = and(_T_206, _T_214) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_215, UInt<1>(0h1), "") : assert_26 node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(is_aligned, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_225 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(io.in.a.bits.mask, mask) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_229, UInt<1>(0h1), "") : assert_30 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_237 = shr(io.in.a.bits.source, 11) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_5) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = and(_T_245, _T_250) node _T_252 = or(UInt<1>(0h0), _T_251) node _T_253 = and(_T_244, _T_252) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_253, UInt<1>(0h1), "") : assert_31 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(is_aligned, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_263 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_263, UInt<1>(0h1), "") : assert_34 node _T_267 = not(mask) node _T_268 = and(io.in.a.bits.mask, _T_267) node _T_269 = eq(_T_268, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_269, UInt<1>(0h1), "") : assert_35 node _T_273 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_277 = shr(io.in.a.bits.source, 11) node _T_278 = eq(_T_277, UInt<1>(0h0)) node _T_279 = leq(UInt<1>(0h0), uncommonBits_6) node _T_280 = and(_T_278, _T_279) node _T_281 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_282 = and(_T_280, _T_281) node _T_283 = and(_T_276, _T_282) node _T_284 = or(UInt<1>(0h0), _T_283) node _T_285 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = and(_T_285, _T_290) node _T_292 = or(UInt<1>(0h0), _T_291) node _T_293 = and(_T_284, _T_292) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_293, UInt<1>(0h1), "") : assert_36 node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(is_aligned, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_303 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(_T_303, UInt<1>(0h0)) when _T_306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_303, UInt<1>(0h1), "") : assert_39 node _T_307 = eq(io.in.a.bits.mask, mask) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_307, UInt<1>(0h1), "") : assert_40 node _T_311 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_311 : node _T_312 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_313 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_315 = shr(io.in.a.bits.source, 11) node _T_316 = eq(_T_315, UInt<1>(0h0)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_7) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_320 = and(_T_318, _T_319) node _T_321 = and(_T_314, _T_320) node _T_322 = or(UInt<1>(0h0), _T_321) node _T_323 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = and(_T_323, _T_328) node _T_330 = or(UInt<1>(0h0), _T_329) node _T_331 = and(_T_322, _T_330) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_331, UInt<1>(0h1), "") : assert_41 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(is_aligned, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_341 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(_T_341, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_341, UInt<1>(0h1), "") : assert_44 node _T_345 = eq(io.in.a.bits.mask, mask) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_345, UInt<1>(0h1), "") : assert_45 node _T_349 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_349 : node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_352 = and(_T_350, _T_351) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_353 = shr(io.in.a.bits.source, 11) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = leq(UInt<1>(0h0), uncommonBits_8) node _T_356 = and(_T_354, _T_355) node _T_357 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_358 = and(_T_356, _T_357) node _T_359 = and(_T_352, _T_358) node _T_360 = or(UInt<1>(0h0), _T_359) node _T_361 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = and(_T_361, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = and(_T_360, _T_368) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_369, UInt<1>(0h1), "") : assert_46 node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(is_aligned, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_379 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_379, UInt<1>(0h1), "") : assert_49 node _T_383 = eq(io.in.a.bits.mask, mask) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_383, UInt<1>(0h1), "") : assert_50 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_387, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_391 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_391, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_395 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_395 : node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_399 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_399, UInt<1>(0h1), "") : assert_54 node _T_403 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_403, UInt<1>(0h1), "") : assert_55 node _T_407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_407, UInt<1>(0h1), "") : assert_56 node _T_411 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_411, UInt<1>(0h1), "") : assert_57 node _T_415 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_415 : node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(sink_ok, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_422 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_422, UInt<1>(0h1), "") : assert_60 node _T_426 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_426, UInt<1>(0h1), "") : assert_61 node _T_430 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_431 = asUInt(reset) node _T_432 = eq(_T_431, UInt<1>(0h0)) when _T_432 : node _T_433 = eq(_T_430, UInt<1>(0h0)) when _T_433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_430, UInt<1>(0h1), "") : assert_62 node _T_434 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_434, UInt<1>(0h1), "") : assert_63 node _T_438 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_439, UInt<1>(0h1), "") : assert_64 node _T_443 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_443 : node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(sink_ok, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_450 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_450, UInt<1>(0h1), "") : assert_67 node _T_454 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_454, UInt<1>(0h1), "") : assert_68 node _T_458 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(_T_458, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_458, UInt<1>(0h1), "") : assert_69 node _T_462 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_463 = or(_T_462, io.in.d.bits.corrupt) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_463, UInt<1>(0h1), "") : assert_70 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_468, UInt<1>(0h1), "") : assert_71 node _T_472 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_472 : node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_476 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_476, UInt<1>(0h1), "") : assert_73 node _T_480 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_480, UInt<1>(0h1), "") : assert_74 node _T_484 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_485, UInt<1>(0h1), "") : assert_75 node _T_489 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_493 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_493, UInt<1>(0h1), "") : assert_77 node _T_497 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_498 = or(_T_497, io.in.d.bits.corrupt) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_498, UInt<1>(0h1), "") : assert_78 node _T_502 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = asUInt(reset) node _T_505 = eq(_T_504, UInt<1>(0h0)) when _T_505 : node _T_506 = eq(_T_503, UInt<1>(0h0)) when _T_506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_503, UInt<1>(0h1), "") : assert_79 node _T_507 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_507 : node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_511 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(_T_511, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_511, UInt<1>(0h1), "") : assert_81 node _T_515 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(_T_515, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_515, UInt<1>(0h1), "") : assert_82 node _T_519 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_520, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_524 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_524, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_528 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_528, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_532 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_532, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_536 = eq(a_first, UInt<1>(0h0)) node _T_537 = and(io.in.a.valid, _T_536) when _T_537 : node _T_538 = eq(io.in.a.bits.opcode, opcode) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_538, UInt<1>(0h1), "") : assert_87 node _T_542 = eq(io.in.a.bits.param, param) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_542, UInt<1>(0h1), "") : assert_88 node _T_546 = eq(io.in.a.bits.size, size) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_546, UInt<1>(0h1), "") : assert_89 node _T_550 = eq(io.in.a.bits.source, source) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_550, UInt<1>(0h1), "") : assert_90 node _T_554 = eq(io.in.a.bits.address, address) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_554, UInt<1>(0h1), "") : assert_91 node _T_558 = and(io.in.a.ready, io.in.a.valid) node _T_559 = and(_T_558, a_first) when _T_559 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_560 = eq(d_first, UInt<1>(0h0)) node _T_561 = and(io.in.d.valid, _T_560) when _T_561 : node _T_562 = eq(io.in.d.bits.opcode, opcode_1) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_562, UInt<1>(0h1), "") : assert_92 node _T_566 = eq(io.in.d.bits.param, param_1) node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(_T_566, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_566, UInt<1>(0h1), "") : assert_93 node _T_570 = eq(io.in.d.bits.size, size_1) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_570, UInt<1>(0h1), "") : assert_94 node _T_574 = eq(io.in.d.bits.source, source_1) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_574, UInt<1>(0h1), "") : assert_95 node _T_578 = eq(io.in.d.bits.sink, sink) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_578, UInt<1>(0h1), "") : assert_96 node _T_582 = eq(io.in.d.bits.denied, denied) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_582, UInt<1>(0h1), "") : assert_97 node _T_586 = and(io.in.d.ready, io.in.d.valid) node _T_587 = and(_T_586, d_first) when _T_587 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_588 = and(io.in.a.valid, a_first_1) node _T_589 = and(_T_588, UInt<1>(0h1)) when _T_589 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_590 = and(io.in.a.ready, io.in.a.valid) node _T_591 = and(_T_590, a_first_1) node _T_592 = and(_T_591, UInt<1>(0h1)) when _T_592 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_593 = dshr(inflight, io.in.a.bits.source) node _T_594 = bits(_T_593, 0, 0) node _T_595 = eq(_T_594, UInt<1>(0h0)) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_595, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_599 = and(io.in.d.valid, d_first_1) node _T_600 = and(_T_599, UInt<1>(0h1)) node _T_601 = eq(d_release_ack, UInt<1>(0h0)) node _T_602 = and(_T_600, _T_601) when _T_602 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_603 = and(io.in.d.ready, io.in.d.valid) node _T_604 = and(_T_603, d_first_1) node _T_605 = and(_T_604, UInt<1>(0h1)) node _T_606 = eq(d_release_ack, UInt<1>(0h0)) node _T_607 = and(_T_605, _T_606) when _T_607 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_608 = and(io.in.d.valid, d_first_1) node _T_609 = and(_T_608, UInt<1>(0h1)) node _T_610 = eq(d_release_ack, UInt<1>(0h0)) node _T_611 = and(_T_609, _T_610) when _T_611 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_612 = dshr(inflight, io.in.d.bits.source) node _T_613 = bits(_T_612, 0, 0) node _T_614 = or(_T_613, same_cycle_resp) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_614, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_618 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_619 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_620 = or(_T_618, _T_619) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_620, UInt<1>(0h1), "") : assert_100 node _T_624 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_624, UInt<1>(0h1), "") : assert_101 else : node _T_628 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_629 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_630 = or(_T_628, _T_629) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_630, UInt<1>(0h1), "") : assert_102 node _T_634 = eq(io.in.d.bits.size, a_size_lookup) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_634, UInt<1>(0h1), "") : assert_103 node _T_638 = and(io.in.d.valid, d_first_1) node _T_639 = and(_T_638, a_first_1) node _T_640 = and(_T_639, io.in.a.valid) node _T_641 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_642 = and(_T_640, _T_641) node _T_643 = eq(d_release_ack, UInt<1>(0h0)) node _T_644 = and(_T_642, _T_643) when _T_644 : node _T_645 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_646 = or(_T_645, io.in.a.ready) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_646, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_105 node _T_650 = orr(inflight) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_653 = or(_T_651, _T_652) node _T_654 = lt(watchdog, plusarg_reader.out) node _T_655 = or(_T_653, _T_654) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_655, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_659 = and(io.in.a.ready, io.in.a.valid) node _T_660 = and(io.in.d.ready, io.in.d.valid) node _T_661 = or(_T_659, _T_660) when _T_661 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_662 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<17>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_663 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_664 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_665 = and(_T_663, _T_664) node _T_666 = and(_T_662, _T_665) when _T_666 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_667 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_668 = and(_T_667, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_669 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_673 = dshr(inflight_1, _WIRE_15.bits.source) node _T_674 = bits(_T_673, 0, 0) node _T_675 = eq(_T_674, UInt<1>(0h0)) node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(_T_675, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_675, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_679 = and(io.in.d.valid, d_first_2) node _T_680 = and(_T_679, UInt<1>(0h1)) node _T_681 = and(_T_680, d_release_ack_1) when _T_681 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_682 = and(io.in.d.ready, io.in.d.valid) node _T_683 = and(_T_682, d_first_2) node _T_684 = and(_T_683, UInt<1>(0h1)) node _T_685 = and(_T_684, d_release_ack_1) when _T_685 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_686 = and(io.in.d.valid, d_first_2) node _T_687 = and(_T_686, UInt<1>(0h1)) node _T_688 = and(_T_687, d_release_ack_1) when _T_688 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_689 = dshr(inflight_1, io.in.d.bits.source) node _T_690 = bits(_T_689, 0, 0) node _T_691 = or(_T_690, same_cycle_resp_1) node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(_T_691, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_691, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_695 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_696 = asUInt(reset) node _T_697 = eq(_T_696, UInt<1>(0h0)) when _T_697 : node _T_698 = eq(_T_695, UInt<1>(0h0)) when _T_698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_695, UInt<1>(0h1), "") : assert_108 else : node _T_699 = eq(io.in.d.bits.size, c_size_lookup) node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(_T_699, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_699, UInt<1>(0h1), "") : assert_109 node _T_703 = and(io.in.d.valid, d_first_2) node _T_704 = and(_T_703, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_705 = and(_T_704, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_706 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_707 = and(_T_705, _T_706) node _T_708 = and(_T_707, d_release_ack_1) node _T_709 = eq(c_probe_ack, UInt<1>(0h0)) node _T_710 = and(_T_708, _T_709) when _T_710 : node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_712 = or(_T_711, _WIRE_23.ready) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_106 node _T_716 = orr(inflight_1) node _T_717 = eq(_T_716, UInt<1>(0h0)) node _T_718 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_719 = or(_T_717, _T_718) node _T_720 = lt(watchdog_1, plusarg_reader_1.out) node _T_721 = or(_T_719, _T_720) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_721, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_725 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_726 = and(io.in.d.ready, io.in.d.valid) node _T_727 = or(_T_725, _T_726) when _T_727 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_52( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] reg [31:0] watchdog; // @[Monitor.scala:709:27]

Generate the Verilog code corresponding to this FIRRTL code module PE_444 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_188 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_444( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_188 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BootROMClockSinkDomain : output auto : { flip bootrom_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst bootrom of TLROM connect bootrom.clock, childClock connect bootrom.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect bootrom.auto.in, auto.bootrom_in connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset

module BootROMClockSinkDomain( // @[ClockDomain.scala:14:9] output auto_bootrom_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bootrom_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bootrom_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bootrom_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_bootrom_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_bootrom_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [16:0] auto_bootrom_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bootrom_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_bootrom_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bootrom_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bootrom_in_d_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bootrom_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_bootrom_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bootrom_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); TLROM bootrom ( // @[BootROM.scala:86:17] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_a_ready (auto_bootrom_in_a_ready), .auto_in_a_valid (auto_bootrom_in_a_valid), .auto_in_a_bits_opcode (auto_bootrom_in_a_bits_opcode), .auto_in_a_bits_param (auto_bootrom_in_a_bits_param), .auto_in_a_bits_size (auto_bootrom_in_a_bits_size), .auto_in_a_bits_source (auto_bootrom_in_a_bits_source), .auto_in_a_bits_address (auto_bootrom_in_a_bits_address), .auto_in_a_bits_mask (auto_bootrom_in_a_bits_mask), .auto_in_a_bits_corrupt (auto_bootrom_in_a_bits_corrupt), .auto_in_d_ready (auto_bootrom_in_d_ready), .auto_in_d_valid (auto_bootrom_in_d_valid), .auto_in_d_bits_size (auto_bootrom_in_d_bits_size), .auto_in_d_bits_source (auto_bootrom_in_d_bits_source), .auto_in_d_bits_data (auto_bootrom_in_d_bits_data) ); // @[BootROM.scala:86:17] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_222 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_222( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_49 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_49 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module INToRecFN_i1_e8_s24_49(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_49 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_42 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h2)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<2>(0h3)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h2)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = and(_T_16, _T_24) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_25, UInt<1>(0h1), "") : assert_1 node _T_29 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_29 : node _T_30 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_31 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_32 = and(_T_30, _T_31) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_33 = shr(io.in.a.bits.source, 2) node _T_34 = eq(_T_33, UInt<1>(0h0)) node _T_35 = leq(UInt<1>(0h0), uncommonBits_1) node _T_36 = and(_T_34, _T_35) node _T_37 = leq(uncommonBits_1, UInt<2>(0h2)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_40 = or(_T_38, _T_39) node _T_41 = and(_T_32, _T_40) node _T_42 = or(UInt<1>(0h0), _T_41) node _T_43 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_44 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<14>(0h2000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<13>(0h1000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<18>(0h2f000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<27>(0h4000000))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_48, _T_53) node _T_85 = or(_T_84, _T_58) node _T_86 = or(_T_85, _T_63) node _T_87 = or(_T_86, _T_68) node _T_88 = or(_T_87, _T_73) node _T_89 = or(_T_88, _T_78) node _T_90 = or(_T_89, _T_83) node _T_91 = and(_T_43, _T_90) node _T_92 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_95 = cvt(_T_94) node _T_96 = and(_T_95, asSInt(UInt<17>(0h10000))) node _T_97 = asSInt(_T_96) node _T_98 = eq(_T_97, asSInt(UInt<1>(0h0))) node _T_99 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_100 = cvt(_T_99) node _T_101 = and(_T_100, asSInt(UInt<29>(0h10000000))) node _T_102 = asSInt(_T_101) node _T_103 = eq(_T_102, asSInt(UInt<1>(0h0))) node _T_104 = or(_T_98, _T_103) node _T_105 = and(_T_93, _T_104) node _T_106 = or(UInt<1>(0h0), _T_91) node _T_107 = or(_T_106, _T_105) node _T_108 = and(_T_42, _T_107) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_108, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_2) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_2, UInt<2>(0h2)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.a.bits.source, UInt<2>(0h3)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_117 connect _WIRE[1], _T_118 node _T_119 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_120 = mux(_WIRE[0], _T_119, UInt<1>(0h0)) node _T_121 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_122 = or(_T_120, _T_121) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_122 node _T_123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_125 = and(_T_123, _T_124) node _T_126 = or(UInt<1>(0h0), _T_125) node _T_127 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<14>(0h2000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<13>(0h1000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<17>(0h10000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<18>(0h2f000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<17>(0h10000))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<17>(0h10000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<27>(0h4000000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<29>(0h10000000))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = or(_T_131, _T_136) node _T_178 = or(_T_177, _T_141) node _T_179 = or(_T_178, _T_146) node _T_180 = or(_T_179, _T_151) node _T_181 = or(_T_180, _T_156) node _T_182 = or(_T_181, _T_161) node _T_183 = or(_T_182, _T_166) node _T_184 = or(_T_183, _T_171) node _T_185 = or(_T_184, _T_176) node _T_186 = and(_T_126, _T_185) node _T_187 = or(UInt<1>(0h0), _T_186) node _T_188 = and(_WIRE_1, _T_187) node _T_189 = asUInt(reset) node _T_190 = eq(_T_189, UInt<1>(0h0)) when _T_190 : node _T_191 = eq(_T_188, UInt<1>(0h0)) when _T_191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_188, UInt<1>(0h1), "") : assert_3 node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(source_ok, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_195 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(_T_195, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_195, UInt<1>(0h1), "") : assert_5 node _T_199 = asUInt(reset) node _T_200 = eq(_T_199, UInt<1>(0h0)) when _T_200 : node _T_201 = eq(is_aligned, UInt<1>(0h0)) when _T_201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_202 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_202, UInt<1>(0h1), "") : assert_7 node _T_206 = not(io.in.a.bits.mask) node _T_207 = eq(_T_206, UInt<1>(0h0)) node _T_208 = asUInt(reset) node _T_209 = eq(_T_208, UInt<1>(0h0)) when _T_209 : node _T_210 = eq(_T_207, UInt<1>(0h0)) when _T_210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_207, UInt<1>(0h1), "") : assert_8 node _T_211 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_211, UInt<1>(0h1), "") : assert_9 node _T_215 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_215 : node _T_216 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_217 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_218 = and(_T_216, _T_217) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_219 = shr(io.in.a.bits.source, 2) node _T_220 = eq(_T_219, UInt<1>(0h0)) node _T_221 = leq(UInt<1>(0h0), uncommonBits_3) node _T_222 = and(_T_220, _T_221) node _T_223 = leq(uncommonBits_3, UInt<2>(0h2)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_226 = or(_T_224, _T_225) node _T_227 = and(_T_218, _T_226) node _T_228 = or(UInt<1>(0h0), _T_227) node _T_229 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_230 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_231 = cvt(_T_230) node _T_232 = and(_T_231, asSInt(UInt<14>(0h2000))) node _T_233 = asSInt(_T_232) node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0))) node _T_235 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_236 = cvt(_T_235) node _T_237 = and(_T_236, asSInt(UInt<13>(0h1000))) node _T_238 = asSInt(_T_237) node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0))) node _T_240 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<17>(0h10000))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<18>(0h2f000))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<17>(0h10000))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_256 = cvt(_T_255) node _T_257 = and(_T_256, asSInt(UInt<13>(0h1000))) node _T_258 = asSInt(_T_257) node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0))) node _T_260 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_261 = cvt(_T_260) node _T_262 = and(_T_261, asSInt(UInt<27>(0h4000000))) node _T_263 = asSInt(_T_262) node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0))) node _T_265 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_266 = cvt(_T_265) node _T_267 = and(_T_266, asSInt(UInt<13>(0h1000))) node _T_268 = asSInt(_T_267) node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0))) node _T_270 = or(_T_234, _T_239) node _T_271 = or(_T_270, _T_244) node _T_272 = or(_T_271, _T_249) node _T_273 = or(_T_272, _T_254) node _T_274 = or(_T_273, _T_259) node _T_275 = or(_T_274, _T_264) node _T_276 = or(_T_275, _T_269) node _T_277 = and(_T_229, _T_276) node _T_278 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_279 = or(UInt<1>(0h0), _T_278) node _T_280 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_281 = cvt(_T_280) node _T_282 = and(_T_281, asSInt(UInt<17>(0h10000))) node _T_283 = asSInt(_T_282) node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_286 = cvt(_T_285) node _T_287 = and(_T_286, asSInt(UInt<29>(0h10000000))) node _T_288 = asSInt(_T_287) node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0))) node _T_290 = or(_T_284, _T_289) node _T_291 = and(_T_279, _T_290) node _T_292 = or(UInt<1>(0h0), _T_277) node _T_293 = or(_T_292, _T_291) node _T_294 = and(_T_228, _T_293) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_294, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_298 = shr(io.in.a.bits.source, 2) node _T_299 = eq(_T_298, UInt<1>(0h0)) node _T_300 = leq(UInt<1>(0h0), uncommonBits_4) node _T_301 = and(_T_299, _T_300) node _T_302 = leq(uncommonBits_4, UInt<2>(0h2)) node _T_303 = and(_T_301, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<2>(0h3)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_303 connect _WIRE_2[1], _T_304 node _T_305 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_306 = mux(_WIRE_2[0], _T_305, UInt<1>(0h0)) node _T_307 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_308 = or(_T_306, _T_307) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_308 node _T_309 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_310 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_311 = and(_T_309, _T_310) node _T_312 = or(UInt<1>(0h0), _T_311) node _T_313 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<14>(0h2000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<18>(0h2f000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<17>(0h10000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_344 = cvt(_T_343) node _T_345 = and(_T_344, asSInt(UInt<17>(0h10000))) node _T_346 = asSInt(_T_345) node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0))) node _T_348 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_349 = cvt(_T_348) node _T_350 = and(_T_349, asSInt(UInt<27>(0h4000000))) node _T_351 = asSInt(_T_350) node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0))) node _T_353 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_359 = cvt(_T_358) node _T_360 = and(_T_359, asSInt(UInt<29>(0h10000000))) node _T_361 = asSInt(_T_360) node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0))) node _T_363 = or(_T_317, _T_322) node _T_364 = or(_T_363, _T_327) node _T_365 = or(_T_364, _T_332) node _T_366 = or(_T_365, _T_337) node _T_367 = or(_T_366, _T_342) node _T_368 = or(_T_367, _T_347) node _T_369 = or(_T_368, _T_352) node _T_370 = or(_T_369, _T_357) node _T_371 = or(_T_370, _T_362) node _T_372 = and(_T_312, _T_371) node _T_373 = or(UInt<1>(0h0), _T_372) node _T_374 = and(_WIRE_3, _T_373) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_374, UInt<1>(0h1), "") : assert_11 node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(source_ok, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_381 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_381, UInt<1>(0h1), "") : assert_13 node _T_385 = asUInt(reset) node _T_386 = eq(_T_385, UInt<1>(0h0)) when _T_386 : node _T_387 = eq(is_aligned, UInt<1>(0h0)) when _T_387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_388 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(_T_388, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_388, UInt<1>(0h1), "") : assert_15 node _T_392 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_392, UInt<1>(0h1), "") : assert_16 node _T_396 = not(io.in.a.bits.mask) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_397, UInt<1>(0h1), "") : assert_17 node _T_401 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_T_401, UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_401, UInt<1>(0h1), "") : assert_18 node _T_405 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_405 : node _T_406 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_407 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_408 = and(_T_406, _T_407) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_5) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_5, UInt<2>(0h2)) node _T_414 = and(_T_412, _T_413) node _T_415 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_416 = or(_T_414, _T_415) node _T_417 = and(_T_408, _T_416) node _T_418 = or(UInt<1>(0h0), _T_417) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_418, UInt<1>(0h1), "") : assert_19 node _T_422 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_423 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_424 = and(_T_422, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = and(_T_425, _T_430) node _T_432 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_433 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_434 = and(_T_432, _T_433) node _T_435 = or(UInt<1>(0h0), _T_434) node _T_436 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<14>(0h2000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_447 = cvt(_T_446) node _T_448 = and(_T_447, asSInt(UInt<18>(0h2f000))) node _T_449 = asSInt(_T_448) node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0))) node _T_451 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<17>(0h10000))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<13>(0h1000))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<17>(0h10000))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<27>(0h4000000))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<29>(0h10000000))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_440, _T_445) node _T_482 = or(_T_481, _T_450) node _T_483 = or(_T_482, _T_455) node _T_484 = or(_T_483, _T_460) node _T_485 = or(_T_484, _T_465) node _T_486 = or(_T_485, _T_470) node _T_487 = or(_T_486, _T_475) node _T_488 = or(_T_487, _T_480) node _T_489 = and(_T_435, _T_488) node _T_490 = or(UInt<1>(0h0), _T_431) node _T_491 = or(_T_490, _T_489) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_491, UInt<1>(0h1), "") : assert_20 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(source_ok, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(is_aligned, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_501 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_501, UInt<1>(0h1), "") : assert_23 node _T_505 = eq(io.in.a.bits.mask, mask) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_505, UInt<1>(0h1), "") : assert_24 node _T_509 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_509, UInt<1>(0h1), "") : assert_25 node _T_513 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_513 : node _T_514 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_515 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_516 = and(_T_514, _T_515) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_517 = shr(io.in.a.bits.source, 2) node _T_518 = eq(_T_517, UInt<1>(0h0)) node _T_519 = leq(UInt<1>(0h0), uncommonBits_6) node _T_520 = and(_T_518, _T_519) node _T_521 = leq(uncommonBits_6, UInt<2>(0h2)) node _T_522 = and(_T_520, _T_521) node _T_523 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_524 = or(_T_522, _T_523) node _T_525 = and(_T_516, _T_524) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_528 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_529 = and(_T_527, _T_528) node _T_530 = or(UInt<1>(0h0), _T_529) node _T_531 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<13>(0h1000))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = and(_T_530, _T_535) node _T_537 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_538 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_539 = and(_T_537, _T_538) node _T_540 = or(UInt<1>(0h0), _T_539) node _T_541 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_542 = cvt(_T_541) node _T_543 = and(_T_542, asSInt(UInt<14>(0h2000))) node _T_544 = asSInt(_T_543) node _T_545 = eq(_T_544, asSInt(UInt<1>(0h0))) node _T_546 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_547 = cvt(_T_546) node _T_548 = and(_T_547, asSInt(UInt<18>(0h2f000))) node _T_549 = asSInt(_T_548) node _T_550 = eq(_T_549, asSInt(UInt<1>(0h0))) node _T_551 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_557 = cvt(_T_556) node _T_558 = and(_T_557, asSInt(UInt<13>(0h1000))) node _T_559 = asSInt(_T_558) node _T_560 = eq(_T_559, asSInt(UInt<1>(0h0))) node _T_561 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<17>(0h10000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_567 = cvt(_T_566) node _T_568 = and(_T_567, asSInt(UInt<27>(0h4000000))) node _T_569 = asSInt(_T_568) node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0))) node _T_571 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<13>(0h1000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<29>(0h10000000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = or(_T_545, _T_550) node _T_582 = or(_T_581, _T_555) node _T_583 = or(_T_582, _T_560) node _T_584 = or(_T_583, _T_565) node _T_585 = or(_T_584, _T_570) node _T_586 = or(_T_585, _T_575) node _T_587 = or(_T_586, _T_580) node _T_588 = and(_T_540, _T_587) node _T_589 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_590 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_591 = cvt(_T_590) node _T_592 = and(_T_591, asSInt(UInt<17>(0h10000))) node _T_593 = asSInt(_T_592) node _T_594 = eq(_T_593, asSInt(UInt<1>(0h0))) node _T_595 = and(_T_589, _T_594) node _T_596 = or(UInt<1>(0h0), _T_536) node _T_597 = or(_T_596, _T_588) node _T_598 = or(_T_597, _T_595) node _T_599 = and(_T_526, _T_598) node _T_600 = asUInt(reset) node _T_601 = eq(_T_600, UInt<1>(0h0)) when _T_601 : node _T_602 = eq(_T_599, UInt<1>(0h0)) when _T_602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_599, UInt<1>(0h1), "") : assert_26 node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(source_ok, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(is_aligned, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_609 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_610 = asUInt(reset) node _T_611 = eq(_T_610, UInt<1>(0h0)) when _T_611 : node _T_612 = eq(_T_609, UInt<1>(0h0)) when _T_612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_609, UInt<1>(0h1), "") : assert_29 node _T_613 = eq(io.in.a.bits.mask, mask) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_613, UInt<1>(0h1), "") : assert_30 node _T_617 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_617 : node _T_618 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_619 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_620 = and(_T_618, _T_619) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_621 = shr(io.in.a.bits.source, 2) node _T_622 = eq(_T_621, UInt<1>(0h0)) node _T_623 = leq(UInt<1>(0h0), uncommonBits_7) node _T_624 = and(_T_622, _T_623) node _T_625 = leq(uncommonBits_7, UInt<2>(0h2)) node _T_626 = and(_T_624, _T_625) node _T_627 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_628 = or(_T_626, _T_627) node _T_629 = and(_T_620, _T_628) node _T_630 = or(UInt<1>(0h0), _T_629) node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_633 = and(_T_631, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = and(_T_634, _T_639) node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_643 = and(_T_641, _T_642) node _T_644 = or(UInt<1>(0h0), _T_643) node _T_645 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<14>(0h2000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<18>(0h2f000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<17>(0h10000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<27>(0h4000000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<13>(0h1000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<29>(0h10000000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = or(_T_649, _T_654) node _T_686 = or(_T_685, _T_659) node _T_687 = or(_T_686, _T_664) node _T_688 = or(_T_687, _T_669) node _T_689 = or(_T_688, _T_674) node _T_690 = or(_T_689, _T_679) node _T_691 = or(_T_690, _T_684) node _T_692 = and(_T_644, _T_691) node _T_693 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_694 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_695 = cvt(_T_694) node _T_696 = and(_T_695, asSInt(UInt<17>(0h10000))) node _T_697 = asSInt(_T_696) node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0))) node _T_699 = and(_T_693, _T_698) node _T_700 = or(UInt<1>(0h0), _T_640) node _T_701 = or(_T_700, _T_692) node _T_702 = or(_T_701, _T_699) node _T_703 = and(_T_630, _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_703, UInt<1>(0h1), "") : assert_31 node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(source_ok, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(is_aligned, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_713 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_713, UInt<1>(0h1), "") : assert_34 node _T_717 = not(mask) node _T_718 = and(io.in.a.bits.mask, _T_717) node _T_719 = eq(_T_718, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_719, UInt<1>(0h1), "") : assert_35 node _T_723 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_723 : node _T_724 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_725 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_726 = and(_T_724, _T_725) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_727 = shr(io.in.a.bits.source, 2) node _T_728 = eq(_T_727, UInt<1>(0h0)) node _T_729 = leq(UInt<1>(0h0), uncommonBits_8) node _T_730 = and(_T_728, _T_729) node _T_731 = leq(uncommonBits_8, UInt<2>(0h2)) node _T_732 = and(_T_730, _T_731) node _T_733 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_734 = or(_T_732, _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<14>(0h2000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<13>(0h1000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<18>(0h2f000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_757 = cvt(_T_756) node _T_758 = and(_T_757, asSInt(UInt<17>(0h10000))) node _T_759 = asSInt(_T_758) node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0))) node _T_761 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_762 = cvt(_T_761) node _T_763 = and(_T_762, asSInt(UInt<13>(0h1000))) node _T_764 = asSInt(_T_763) node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) node _T_766 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<17>(0h10000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_772 = cvt(_T_771) node _T_773 = and(_T_772, asSInt(UInt<27>(0h4000000))) node _T_774 = asSInt(_T_773) node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0))) node _T_776 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<13>(0h1000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<29>(0h10000000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = or(_T_745, _T_750) node _T_787 = or(_T_786, _T_755) node _T_788 = or(_T_787, _T_760) node _T_789 = or(_T_788, _T_765) node _T_790 = or(_T_789, _T_770) node _T_791 = or(_T_790, _T_775) node _T_792 = or(_T_791, _T_780) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_740, _T_793) node _T_795 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_796 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_797 = cvt(_T_796) node _T_798 = and(_T_797, asSInt(UInt<17>(0h10000))) node _T_799 = asSInt(_T_798) node _T_800 = eq(_T_799, asSInt(UInt<1>(0h0))) node _T_801 = and(_T_795, _T_800) node _T_802 = or(UInt<1>(0h0), _T_794) node _T_803 = or(_T_802, _T_801) node _T_804 = and(_T_736, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_804, UInt<1>(0h1), "") : assert_36 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_814 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_814, UInt<1>(0h1), "") : assert_39 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_818, UInt<1>(0h1), "") : assert_40 node _T_822 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_822 : node _T_823 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_824 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<1>(0h0)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_9) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_9, UInt<2>(0h2)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_833 = or(_T_831, _T_832) node _T_834 = and(_T_825, _T_833) node _T_835 = or(UInt<1>(0h0), _T_834) node _T_836 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_837 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _T_839 = or(UInt<1>(0h0), _T_838) node _T_840 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<14>(0h2000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<13>(0h1000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<18>(0h2f000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_856 = cvt(_T_855) node _T_857 = and(_T_856, asSInt(UInt<17>(0h10000))) node _T_858 = asSInt(_T_857) node _T_859 = eq(_T_858, asSInt(UInt<1>(0h0))) node _T_860 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<13>(0h1000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_866 = cvt(_T_865) node _T_867 = and(_T_866, asSInt(UInt<17>(0h10000))) node _T_868 = asSInt(_T_867) node _T_869 = eq(_T_868, asSInt(UInt<1>(0h0))) node _T_870 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_871 = cvt(_T_870) node _T_872 = and(_T_871, asSInt(UInt<27>(0h4000000))) node _T_873 = asSInt(_T_872) node _T_874 = eq(_T_873, asSInt(UInt<1>(0h0))) node _T_875 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_876 = cvt(_T_875) node _T_877 = and(_T_876, asSInt(UInt<13>(0h1000))) node _T_878 = asSInt(_T_877) node _T_879 = eq(_T_878, asSInt(UInt<1>(0h0))) node _T_880 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_881 = cvt(_T_880) node _T_882 = and(_T_881, asSInt(UInt<29>(0h10000000))) node _T_883 = asSInt(_T_882) node _T_884 = eq(_T_883, asSInt(UInt<1>(0h0))) node _T_885 = or(_T_844, _T_849) node _T_886 = or(_T_885, _T_854) node _T_887 = or(_T_886, _T_859) node _T_888 = or(_T_887, _T_864) node _T_889 = or(_T_888, _T_869) node _T_890 = or(_T_889, _T_874) node _T_891 = or(_T_890, _T_879) node _T_892 = or(_T_891, _T_884) node _T_893 = and(_T_839, _T_892) node _T_894 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_895 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_896 = cvt(_T_895) node _T_897 = and(_T_896, asSInt(UInt<17>(0h10000))) node _T_898 = asSInt(_T_897) node _T_899 = eq(_T_898, asSInt(UInt<1>(0h0))) node _T_900 = and(_T_894, _T_899) node _T_901 = or(UInt<1>(0h0), _T_893) node _T_902 = or(_T_901, _T_900) node _T_903 = and(_T_835, _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_903, UInt<1>(0h1), "") : assert_41 node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(source_ok, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(is_aligned, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_913 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_913, UInt<1>(0h1), "") : assert_44 node _T_917 = eq(io.in.a.bits.mask, mask) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_917, UInt<1>(0h1), "") : assert_45 node _T_921 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_921 : node _T_922 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_923 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_924 = and(_T_922, _T_923) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_925 = shr(io.in.a.bits.source, 2) node _T_926 = eq(_T_925, UInt<1>(0h0)) node _T_927 = leq(UInt<1>(0h0), uncommonBits_10) node _T_928 = and(_T_926, _T_927) node _T_929 = leq(uncommonBits_10, UInt<2>(0h2)) node _T_930 = and(_T_928, _T_929) node _T_931 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_932 = or(_T_930, _T_931) node _T_933 = and(_T_924, _T_932) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_936 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_937 = and(_T_935, _T_936) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_940 = cvt(_T_939) node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000))) node _T_942 = asSInt(_T_941) node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0))) node _T_944 = and(_T_938, _T_943) node _T_945 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_947 = cvt(_T_946) node _T_948 = and(_T_947, asSInt(UInt<14>(0h2000))) node _T_949 = asSInt(_T_948) node _T_950 = eq(_T_949, asSInt(UInt<1>(0h0))) node _T_951 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_952 = cvt(_T_951) node _T_953 = and(_T_952, asSInt(UInt<17>(0h10000))) node _T_954 = asSInt(_T_953) node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0))) node _T_956 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_957 = cvt(_T_956) node _T_958 = and(_T_957, asSInt(UInt<18>(0h2f000))) node _T_959 = asSInt(_T_958) node _T_960 = eq(_T_959, asSInt(UInt<1>(0h0))) node _T_961 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_962 = cvt(_T_961) node _T_963 = and(_T_962, asSInt(UInt<17>(0h10000))) node _T_964 = asSInt(_T_963) node _T_965 = eq(_T_964, asSInt(UInt<1>(0h0))) node _T_966 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_967 = cvt(_T_966) node _T_968 = and(_T_967, asSInt(UInt<13>(0h1000))) node _T_969 = asSInt(_T_968) node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0))) node _T_971 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_972 = cvt(_T_971) node _T_973 = and(_T_972, asSInt(UInt<27>(0h4000000))) node _T_974 = asSInt(_T_973) node _T_975 = eq(_T_974, asSInt(UInt<1>(0h0))) node _T_976 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_977 = cvt(_T_976) node _T_978 = and(_T_977, asSInt(UInt<13>(0h1000))) node _T_979 = asSInt(_T_978) node _T_980 = eq(_T_979, asSInt(UInt<1>(0h0))) node _T_981 = or(_T_950, _T_955) node _T_982 = or(_T_981, _T_960) node _T_983 = or(_T_982, _T_965) node _T_984 = or(_T_983, _T_970) node _T_985 = or(_T_984, _T_975) node _T_986 = or(_T_985, _T_980) node _T_987 = and(_T_945, _T_986) node _T_988 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_989 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_990 = and(_T_988, _T_989) node _T_991 = or(UInt<1>(0h0), _T_990) node _T_992 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<29>(0h10000000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = or(_T_996, _T_1001) node _T_1003 = and(_T_991, _T_1002) node _T_1004 = or(UInt<1>(0h0), _T_944) node _T_1005 = or(_T_1004, _T_987) node _T_1006 = or(_T_1005, _T_1003) node _T_1007 = and(_T_934, _T_1006) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_46 node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(source_ok, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(is_aligned, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1017 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_49 node _T_1021 = eq(io.in.a.bits.mask, mask) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_50 node _T_1025 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1029 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.d.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h0)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h2)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = eq(io.in.d.bits.source, UInt<2>(0h3)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_12 connect _source_ok_WIRE_1[1], _source_ok_T_13 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1033 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1033 : node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(source_ok_1, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1037 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_54 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_55 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_56 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_57 node _T_1053 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(source_ok_1, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(sink_ok, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1060 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_60 node _T_1064 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_61 node _T_1068 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_62 node _T_1072 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_63 node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1077 = or(UInt<1>(0h1), _T_1076) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_64 node _T_1081 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1081 : node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(source_ok_1, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(sink_ok, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1088 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_67 node _T_1092 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_68 node _T_1096 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_69 node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1101 = or(_T_1100, io.in.d.bits.corrupt) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_70 node _T_1105 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1106 = or(UInt<1>(0h1), _T_1105) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_71 node _T_1110 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1110 : node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(source_ok_1, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1114 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_73 node _T_1118 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_74 node _T_1122 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1123 = or(UInt<1>(0h1), _T_1122) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_75 node _T_1127 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1127 : node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(source_ok_1, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1131 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_77 node _T_1135 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1136 = or(_T_1135, io.in.d.bits.corrupt) node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(_T_1136, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1136, UInt<1>(0h1), "") : assert_78 node _T_1140 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1141 = or(UInt<1>(0h1), _T_1140) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_79 node _T_1145 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1145 : node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(source_ok_1, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1149 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_81 node _T_1153 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_82 node _T_1157 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1158 = or(UInt<1>(0h1), _T_1157) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1162 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_1166 = shr(io.in.b.bits.source, 2) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) node _T_1168 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1169 = and(_T_1167, _T_1168) node _T_1170 = leq(uncommonBits_11, UInt<2>(0h2)) node _T_1171 = and(_T_1169, _T_1170) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) node _T_1173 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1174 = cvt(_T_1173) node _T_1175 = and(_T_1174, asSInt(UInt<1>(0h0))) node _T_1176 = asSInt(_T_1175) node _T_1177 = eq(_T_1176, asSInt(UInt<1>(0h0))) node _T_1178 = or(_T_1172, _T_1177) node _T_1179 = eq(io.in.b.bits.source, UInt<2>(0h3)) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) node _T_1181 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1182 = cvt(_T_1181) node _T_1183 = and(_T_1182, asSInt(UInt<1>(0h0))) node _T_1184 = asSInt(_T_1183) node _T_1185 = eq(_T_1184, asSInt(UInt<1>(0h0))) node _T_1186 = or(_T_1180, _T_1185) node _T_1187 = and(_T_1178, _T_1186) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T = shr(io.in.b.bits.source, 2) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<2>(0h2)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<2>(0h3)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 node _legal_source_T_7 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_8 = mux(_legal_source_WIRE[1], UInt<2>(0h3), UInt<1>(0h0)) node _legal_source_T_9 = or(_legal_source_T_7, _legal_source_T_8) wire _legal_source_WIRE_1 : UInt<2> connect _legal_source_WIRE_1, _legal_source_T_9 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1191 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1191 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_1192 = shr(io.in.b.bits.source, 2) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) node _T_1194 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = leq(uncommonBits_12, UInt<2>(0h2)) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = eq(io.in.b.bits.source, UInt<2>(0h3)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1197 connect _WIRE_4[1], _T_1198 node _T_1199 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1200 = mux(_WIRE_4[0], _T_1199, UInt<1>(0h0)) node _T_1201 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1202 = or(_T_1200, _T_1201) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1202 node _T_1203 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1204 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1205 = and(_T_1203, _T_1204) node _T_1206 = or(UInt<1>(0h0), _T_1205) node _T_1207 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1208 = cvt(_T_1207) node _T_1209 = and(_T_1208, asSInt(UInt<14>(0h2000))) node _T_1210 = asSInt(_T_1209) node _T_1211 = eq(_T_1210, asSInt(UInt<1>(0h0))) node _T_1212 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1213 = cvt(_T_1212) node _T_1214 = and(_T_1213, asSInt(UInt<13>(0h1000))) node _T_1215 = asSInt(_T_1214) node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1218 = cvt(_T_1217) node _T_1219 = and(_T_1218, asSInt(UInt<17>(0h10000))) node _T_1220 = asSInt(_T_1219) node _T_1221 = eq(_T_1220, asSInt(UInt<1>(0h0))) node _T_1222 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<18>(0h2f000))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1228 = cvt(_T_1227) node _T_1229 = and(_T_1228, asSInt(UInt<17>(0h10000))) node _T_1230 = asSInt(_T_1229) node _T_1231 = eq(_T_1230, asSInt(UInt<1>(0h0))) node _T_1232 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1233 = cvt(_T_1232) node _T_1234 = and(_T_1233, asSInt(UInt<13>(0h1000))) node _T_1235 = asSInt(_T_1234) node _T_1236 = eq(_T_1235, asSInt(UInt<1>(0h0))) node _T_1237 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1238 = cvt(_T_1237) node _T_1239 = and(_T_1238, asSInt(UInt<17>(0h10000))) node _T_1240 = asSInt(_T_1239) node _T_1241 = eq(_T_1240, asSInt(UInt<1>(0h0))) node _T_1242 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1243 = cvt(_T_1242) node _T_1244 = and(_T_1243, asSInt(UInt<27>(0h4000000))) node _T_1245 = asSInt(_T_1244) node _T_1246 = eq(_T_1245, asSInt(UInt<1>(0h0))) node _T_1247 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1248 = cvt(_T_1247) node _T_1249 = and(_T_1248, asSInt(UInt<13>(0h1000))) node _T_1250 = asSInt(_T_1249) node _T_1251 = eq(_T_1250, asSInt(UInt<1>(0h0))) node _T_1252 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1253 = cvt(_T_1252) node _T_1254 = and(_T_1253, asSInt(UInt<29>(0h10000000))) node _T_1255 = asSInt(_T_1254) node _T_1256 = eq(_T_1255, asSInt(UInt<1>(0h0))) node _T_1257 = or(_T_1211, _T_1216) node _T_1258 = or(_T_1257, _T_1221) node _T_1259 = or(_T_1258, _T_1226) node _T_1260 = or(_T_1259, _T_1231) node _T_1261 = or(_T_1260, _T_1236) node _T_1262 = or(_T_1261, _T_1241) node _T_1263 = or(_T_1262, _T_1246) node _T_1264 = or(_T_1263, _T_1251) node _T_1265 = or(_T_1264, _T_1256) node _T_1266 = and(_T_1206, _T_1265) node _T_1267 = or(UInt<1>(0h0), _T_1266) node _T_1268 = and(_WIRE_5, _T_1267) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_86 node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(address_ok, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1275 = asUInt(reset) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) when _T_1276 : node _T_1277 = eq(legal_source, UInt<1>(0h0)) when _T_1277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1281 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_90 node _T_1285 = eq(io.in.b.bits.mask, mask_1) node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(_T_1285, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1285, UInt<1>(0h1), "") : assert_91 node _T_1289 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_92 node _T_1293 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1293 : node _T_1294 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1295 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1296 = and(_T_1294, _T_1295) node _T_1297 = or(UInt<1>(0h0), _T_1296) node _T_1298 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1299 = cvt(_T_1298) node _T_1300 = and(_T_1299, asSInt(UInt<14>(0h2000))) node _T_1301 = asSInt(_T_1300) node _T_1302 = eq(_T_1301, asSInt(UInt<1>(0h0))) node _T_1303 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1304 = cvt(_T_1303) node _T_1305 = and(_T_1304, asSInt(UInt<13>(0h1000))) node _T_1306 = asSInt(_T_1305) node _T_1307 = eq(_T_1306, asSInt(UInt<1>(0h0))) node _T_1308 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1309 = cvt(_T_1308) node _T_1310 = and(_T_1309, asSInt(UInt<17>(0h10000))) node _T_1311 = asSInt(_T_1310) node _T_1312 = eq(_T_1311, asSInt(UInt<1>(0h0))) node _T_1313 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1314 = cvt(_T_1313) node _T_1315 = and(_T_1314, asSInt(UInt<18>(0h2f000))) node _T_1316 = asSInt(_T_1315) node _T_1317 = eq(_T_1316, asSInt(UInt<1>(0h0))) node _T_1318 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1319 = cvt(_T_1318) node _T_1320 = and(_T_1319, asSInt(UInt<17>(0h10000))) node _T_1321 = asSInt(_T_1320) node _T_1322 = eq(_T_1321, asSInt(UInt<1>(0h0))) node _T_1323 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1324 = cvt(_T_1323) node _T_1325 = and(_T_1324, asSInt(UInt<13>(0h1000))) node _T_1326 = asSInt(_T_1325) node _T_1327 = eq(_T_1326, asSInt(UInt<1>(0h0))) node _T_1328 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1329 = cvt(_T_1328) node _T_1330 = and(_T_1329, asSInt(UInt<17>(0h10000))) node _T_1331 = asSInt(_T_1330) node _T_1332 = eq(_T_1331, asSInt(UInt<1>(0h0))) node _T_1333 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1334 = cvt(_T_1333) node _T_1335 = and(_T_1334, asSInt(UInt<27>(0h4000000))) node _T_1336 = asSInt(_T_1335) node _T_1337 = eq(_T_1336, asSInt(UInt<1>(0h0))) node _T_1338 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1339 = cvt(_T_1338) node _T_1340 = and(_T_1339, asSInt(UInt<13>(0h1000))) node _T_1341 = asSInt(_T_1340) node _T_1342 = eq(_T_1341, asSInt(UInt<1>(0h0))) node _T_1343 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1344 = cvt(_T_1343) node _T_1345 = and(_T_1344, asSInt(UInt<29>(0h10000000))) node _T_1346 = asSInt(_T_1345) node _T_1347 = eq(_T_1346, asSInt(UInt<1>(0h0))) node _T_1348 = or(_T_1302, _T_1307) node _T_1349 = or(_T_1348, _T_1312) node _T_1350 = or(_T_1349, _T_1317) node _T_1351 = or(_T_1350, _T_1322) node _T_1352 = or(_T_1351, _T_1327) node _T_1353 = or(_T_1352, _T_1332) node _T_1354 = or(_T_1353, _T_1337) node _T_1355 = or(_T_1354, _T_1342) node _T_1356 = or(_T_1355, _T_1347) node _T_1357 = and(_T_1297, _T_1356) node _T_1358 = or(UInt<1>(0h0), _T_1357) node _T_1359 = and(UInt<1>(0h0), _T_1358) node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(_T_1359, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1359, UInt<1>(0h1), "") : assert_93 node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(address_ok, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(legal_source, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1372 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_97 node _T_1376 = eq(io.in.b.bits.mask, mask_1) node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(_T_1376, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1376, UInt<1>(0h1), "") : assert_98 node _T_1380 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1381 = asUInt(reset) node _T_1382 = eq(_T_1381, UInt<1>(0h0)) when _T_1382 : node _T_1383 = eq(_T_1380, UInt<1>(0h0)) when _T_1383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1380, UInt<1>(0h1), "") : assert_99 node _T_1384 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1384 : node _T_1385 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1386 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1387 = and(_T_1385, _T_1386) node _T_1388 = or(UInt<1>(0h0), _T_1387) node _T_1389 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1390 = cvt(_T_1389) node _T_1391 = and(_T_1390, asSInt(UInt<14>(0h2000))) node _T_1392 = asSInt(_T_1391) node _T_1393 = eq(_T_1392, asSInt(UInt<1>(0h0))) node _T_1394 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1395 = cvt(_T_1394) node _T_1396 = and(_T_1395, asSInt(UInt<13>(0h1000))) node _T_1397 = asSInt(_T_1396) node _T_1398 = eq(_T_1397, asSInt(UInt<1>(0h0))) node _T_1399 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1400 = cvt(_T_1399) node _T_1401 = and(_T_1400, asSInt(UInt<17>(0h10000))) node _T_1402 = asSInt(_T_1401) node _T_1403 = eq(_T_1402, asSInt(UInt<1>(0h0))) node _T_1404 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1405 = cvt(_T_1404) node _T_1406 = and(_T_1405, asSInt(UInt<18>(0h2f000))) node _T_1407 = asSInt(_T_1406) node _T_1408 = eq(_T_1407, asSInt(UInt<1>(0h0))) node _T_1409 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1410 = cvt(_T_1409) node _T_1411 = and(_T_1410, asSInt(UInt<17>(0h10000))) node _T_1412 = asSInt(_T_1411) node _T_1413 = eq(_T_1412, asSInt(UInt<1>(0h0))) node _T_1414 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1415 = cvt(_T_1414) node _T_1416 = and(_T_1415, asSInt(UInt<13>(0h1000))) node _T_1417 = asSInt(_T_1416) node _T_1418 = eq(_T_1417, asSInt(UInt<1>(0h0))) node _T_1419 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1420 = cvt(_T_1419) node _T_1421 = and(_T_1420, asSInt(UInt<17>(0h10000))) node _T_1422 = asSInt(_T_1421) node _T_1423 = eq(_T_1422, asSInt(UInt<1>(0h0))) node _T_1424 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1425 = cvt(_T_1424) node _T_1426 = and(_T_1425, asSInt(UInt<27>(0h4000000))) node _T_1427 = asSInt(_T_1426) node _T_1428 = eq(_T_1427, asSInt(UInt<1>(0h0))) node _T_1429 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1430 = cvt(_T_1429) node _T_1431 = and(_T_1430, asSInt(UInt<13>(0h1000))) node _T_1432 = asSInt(_T_1431) node _T_1433 = eq(_T_1432, asSInt(UInt<1>(0h0))) node _T_1434 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1435 = cvt(_T_1434) node _T_1436 = and(_T_1435, asSInt(UInt<29>(0h10000000))) node _T_1437 = asSInt(_T_1436) node _T_1438 = eq(_T_1437, asSInt(UInt<1>(0h0))) node _T_1439 = or(_T_1393, _T_1398) node _T_1440 = or(_T_1439, _T_1403) node _T_1441 = or(_T_1440, _T_1408) node _T_1442 = or(_T_1441, _T_1413) node _T_1443 = or(_T_1442, _T_1418) node _T_1444 = or(_T_1443, _T_1423) node _T_1445 = or(_T_1444, _T_1428) node _T_1446 = or(_T_1445, _T_1433) node _T_1447 = or(_T_1446, _T_1438) node _T_1448 = and(_T_1388, _T_1447) node _T_1449 = or(UInt<1>(0h0), _T_1448) node _T_1450 = and(UInt<1>(0h0), _T_1449) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_100 node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(address_ok, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(legal_source, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1463 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_104 node _T_1467 = eq(io.in.b.bits.mask, mask_1) node _T_1468 = asUInt(reset) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(_T_1467, UInt<1>(0h0)) when _T_1470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1467, UInt<1>(0h1), "") : assert_105 node _T_1471 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1471 : node _T_1472 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1473 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1474 = and(_T_1472, _T_1473) node _T_1475 = or(UInt<1>(0h0), _T_1474) node _T_1476 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1477 = cvt(_T_1476) node _T_1478 = and(_T_1477, asSInt(UInt<14>(0h2000))) node _T_1479 = asSInt(_T_1478) node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0))) node _T_1481 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1482 = cvt(_T_1481) node _T_1483 = and(_T_1482, asSInt(UInt<13>(0h1000))) node _T_1484 = asSInt(_T_1483) node _T_1485 = eq(_T_1484, asSInt(UInt<1>(0h0))) node _T_1486 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1487 = cvt(_T_1486) node _T_1488 = and(_T_1487, asSInt(UInt<17>(0h10000))) node _T_1489 = asSInt(_T_1488) node _T_1490 = eq(_T_1489, asSInt(UInt<1>(0h0))) node _T_1491 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1492 = cvt(_T_1491) node _T_1493 = and(_T_1492, asSInt(UInt<18>(0h2f000))) node _T_1494 = asSInt(_T_1493) node _T_1495 = eq(_T_1494, asSInt(UInt<1>(0h0))) node _T_1496 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1497 = cvt(_T_1496) node _T_1498 = and(_T_1497, asSInt(UInt<17>(0h10000))) node _T_1499 = asSInt(_T_1498) node _T_1500 = eq(_T_1499, asSInt(UInt<1>(0h0))) node _T_1501 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1502 = cvt(_T_1501) node _T_1503 = and(_T_1502, asSInt(UInt<13>(0h1000))) node _T_1504 = asSInt(_T_1503) node _T_1505 = eq(_T_1504, asSInt(UInt<1>(0h0))) node _T_1506 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1507 = cvt(_T_1506) node _T_1508 = and(_T_1507, asSInt(UInt<17>(0h10000))) node _T_1509 = asSInt(_T_1508) node _T_1510 = eq(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1512 = cvt(_T_1511) node _T_1513 = and(_T_1512, asSInt(UInt<27>(0h4000000))) node _T_1514 = asSInt(_T_1513) node _T_1515 = eq(_T_1514, asSInt(UInt<1>(0h0))) node _T_1516 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1517 = cvt(_T_1516) node _T_1518 = and(_T_1517, asSInt(UInt<13>(0h1000))) node _T_1519 = asSInt(_T_1518) node _T_1520 = eq(_T_1519, asSInt(UInt<1>(0h0))) node _T_1521 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1522 = cvt(_T_1521) node _T_1523 = and(_T_1522, asSInt(UInt<29>(0h10000000))) node _T_1524 = asSInt(_T_1523) node _T_1525 = eq(_T_1524, asSInt(UInt<1>(0h0))) node _T_1526 = or(_T_1480, _T_1485) node _T_1527 = or(_T_1526, _T_1490) node _T_1528 = or(_T_1527, _T_1495) node _T_1529 = or(_T_1528, _T_1500) node _T_1530 = or(_T_1529, _T_1505) node _T_1531 = or(_T_1530, _T_1510) node _T_1532 = or(_T_1531, _T_1515) node _T_1533 = or(_T_1532, _T_1520) node _T_1534 = or(_T_1533, _T_1525) node _T_1535 = and(_T_1475, _T_1534) node _T_1536 = or(UInt<1>(0h0), _T_1535) node _T_1537 = and(UInt<1>(0h0), _T_1536) node _T_1538 = asUInt(reset) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) when _T_1539 : node _T_1540 = eq(_T_1537, UInt<1>(0h0)) when _T_1540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1537, UInt<1>(0h1), "") : assert_106 node _T_1541 = asUInt(reset) node _T_1542 = eq(_T_1541, UInt<1>(0h0)) when _T_1542 : node _T_1543 = eq(address_ok, UInt<1>(0h0)) when _T_1543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(legal_source, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1547 = asUInt(reset) node _T_1548 = eq(_T_1547, UInt<1>(0h0)) when _T_1548 : node _T_1549 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1550 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(_T_1550, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1550, UInt<1>(0h1), "") : assert_110 node _T_1554 = not(mask_1) node _T_1555 = and(io.in.b.bits.mask, _T_1554) node _T_1556 = eq(_T_1555, UInt<1>(0h0)) node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(_T_1556, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1556, UInt<1>(0h1), "") : assert_111 node _T_1560 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1560 : node _T_1561 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1562 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1563 = and(_T_1561, _T_1562) node _T_1564 = or(UInt<1>(0h0), _T_1563) node _T_1565 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1566 = cvt(_T_1565) node _T_1567 = and(_T_1566, asSInt(UInt<14>(0h2000))) node _T_1568 = asSInt(_T_1567) node _T_1569 = eq(_T_1568, asSInt(UInt<1>(0h0))) node _T_1570 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1571 = cvt(_T_1570) node _T_1572 = and(_T_1571, asSInt(UInt<13>(0h1000))) node _T_1573 = asSInt(_T_1572) node _T_1574 = eq(_T_1573, asSInt(UInt<1>(0h0))) node _T_1575 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1576 = cvt(_T_1575) node _T_1577 = and(_T_1576, asSInt(UInt<17>(0h10000))) node _T_1578 = asSInt(_T_1577) node _T_1579 = eq(_T_1578, asSInt(UInt<1>(0h0))) node _T_1580 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1581 = cvt(_T_1580) node _T_1582 = and(_T_1581, asSInt(UInt<18>(0h2f000))) node _T_1583 = asSInt(_T_1582) node _T_1584 = eq(_T_1583, asSInt(UInt<1>(0h0))) node _T_1585 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1586 = cvt(_T_1585) node _T_1587 = and(_T_1586, asSInt(UInt<17>(0h10000))) node _T_1588 = asSInt(_T_1587) node _T_1589 = eq(_T_1588, asSInt(UInt<1>(0h0))) node _T_1590 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1591 = cvt(_T_1590) node _T_1592 = and(_T_1591, asSInt(UInt<13>(0h1000))) node _T_1593 = asSInt(_T_1592) node _T_1594 = eq(_T_1593, asSInt(UInt<1>(0h0))) node _T_1595 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1596 = cvt(_T_1595) node _T_1597 = and(_T_1596, asSInt(UInt<17>(0h10000))) node _T_1598 = asSInt(_T_1597) node _T_1599 = eq(_T_1598, asSInt(UInt<1>(0h0))) node _T_1600 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1601 = cvt(_T_1600) node _T_1602 = and(_T_1601, asSInt(UInt<27>(0h4000000))) node _T_1603 = asSInt(_T_1602) node _T_1604 = eq(_T_1603, asSInt(UInt<1>(0h0))) node _T_1605 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1606 = cvt(_T_1605) node _T_1607 = and(_T_1606, asSInt(UInt<13>(0h1000))) node _T_1608 = asSInt(_T_1607) node _T_1609 = eq(_T_1608, asSInt(UInt<1>(0h0))) node _T_1610 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1611 = cvt(_T_1610) node _T_1612 = and(_T_1611, asSInt(UInt<29>(0h10000000))) node _T_1613 = asSInt(_T_1612) node _T_1614 = eq(_T_1613, asSInt(UInt<1>(0h0))) node _T_1615 = or(_T_1569, _T_1574) node _T_1616 = or(_T_1615, _T_1579) node _T_1617 = or(_T_1616, _T_1584) node _T_1618 = or(_T_1617, _T_1589) node _T_1619 = or(_T_1618, _T_1594) node _T_1620 = or(_T_1619, _T_1599) node _T_1621 = or(_T_1620, _T_1604) node _T_1622 = or(_T_1621, _T_1609) node _T_1623 = or(_T_1622, _T_1614) node _T_1624 = and(_T_1564, _T_1623) node _T_1625 = or(UInt<1>(0h0), _T_1624) node _T_1626 = and(UInt<1>(0h0), _T_1625) node _T_1627 = asUInt(reset) node _T_1628 = eq(_T_1627, UInt<1>(0h0)) when _T_1628 : node _T_1629 = eq(_T_1626, UInt<1>(0h0)) when _T_1629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1626, UInt<1>(0h1), "") : assert_112 node _T_1630 = asUInt(reset) node _T_1631 = eq(_T_1630, UInt<1>(0h0)) when _T_1631 : node _T_1632 = eq(address_ok, UInt<1>(0h0)) when _T_1632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1633 = asUInt(reset) node _T_1634 = eq(_T_1633, UInt<1>(0h0)) when _T_1634 : node _T_1635 = eq(legal_source, UInt<1>(0h0)) when _T_1635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1636 = asUInt(reset) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1639 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(_T_1639, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1639, UInt<1>(0h1), "") : assert_116 node _T_1643 = eq(io.in.b.bits.mask, mask_1) node _T_1644 = asUInt(reset) node _T_1645 = eq(_T_1644, UInt<1>(0h0)) when _T_1645 : node _T_1646 = eq(_T_1643, UInt<1>(0h0)) when _T_1646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1643, UInt<1>(0h1), "") : assert_117 node _T_1647 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1647 : node _T_1648 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1649 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1650 = and(_T_1648, _T_1649) node _T_1651 = or(UInt<1>(0h0), _T_1650) node _T_1652 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1653 = cvt(_T_1652) node _T_1654 = and(_T_1653, asSInt(UInt<14>(0h2000))) node _T_1655 = asSInt(_T_1654) node _T_1656 = eq(_T_1655, asSInt(UInt<1>(0h0))) node _T_1657 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1658 = cvt(_T_1657) node _T_1659 = and(_T_1658, asSInt(UInt<13>(0h1000))) node _T_1660 = asSInt(_T_1659) node _T_1661 = eq(_T_1660, asSInt(UInt<1>(0h0))) node _T_1662 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1663 = cvt(_T_1662) node _T_1664 = and(_T_1663, asSInt(UInt<17>(0h10000))) node _T_1665 = asSInt(_T_1664) node _T_1666 = eq(_T_1665, asSInt(UInt<1>(0h0))) node _T_1667 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1668 = cvt(_T_1667) node _T_1669 = and(_T_1668, asSInt(UInt<18>(0h2f000))) node _T_1670 = asSInt(_T_1669) node _T_1671 = eq(_T_1670, asSInt(UInt<1>(0h0))) node _T_1672 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1673 = cvt(_T_1672) node _T_1674 = and(_T_1673, asSInt(UInt<17>(0h10000))) node _T_1675 = asSInt(_T_1674) node _T_1676 = eq(_T_1675, asSInt(UInt<1>(0h0))) node _T_1677 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1678 = cvt(_T_1677) node _T_1679 = and(_T_1678, asSInt(UInt<13>(0h1000))) node _T_1680 = asSInt(_T_1679) node _T_1681 = eq(_T_1680, asSInt(UInt<1>(0h0))) node _T_1682 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1683 = cvt(_T_1682) node _T_1684 = and(_T_1683, asSInt(UInt<17>(0h10000))) node _T_1685 = asSInt(_T_1684) node _T_1686 = eq(_T_1685, asSInt(UInt<1>(0h0))) node _T_1687 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1688 = cvt(_T_1687) node _T_1689 = and(_T_1688, asSInt(UInt<27>(0h4000000))) node _T_1690 = asSInt(_T_1689) node _T_1691 = eq(_T_1690, asSInt(UInt<1>(0h0))) node _T_1692 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1693 = cvt(_T_1692) node _T_1694 = and(_T_1693, asSInt(UInt<13>(0h1000))) node _T_1695 = asSInt(_T_1694) node _T_1696 = eq(_T_1695, asSInt(UInt<1>(0h0))) node _T_1697 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1698 = cvt(_T_1697) node _T_1699 = and(_T_1698, asSInt(UInt<29>(0h10000000))) node _T_1700 = asSInt(_T_1699) node _T_1701 = eq(_T_1700, asSInt(UInt<1>(0h0))) node _T_1702 = or(_T_1656, _T_1661) node _T_1703 = or(_T_1702, _T_1666) node _T_1704 = or(_T_1703, _T_1671) node _T_1705 = or(_T_1704, _T_1676) node _T_1706 = or(_T_1705, _T_1681) node _T_1707 = or(_T_1706, _T_1686) node _T_1708 = or(_T_1707, _T_1691) node _T_1709 = or(_T_1708, _T_1696) node _T_1710 = or(_T_1709, _T_1701) node _T_1711 = and(_T_1651, _T_1710) node _T_1712 = or(UInt<1>(0h0), _T_1711) node _T_1713 = and(UInt<1>(0h0), _T_1712) node _T_1714 = asUInt(reset) node _T_1715 = eq(_T_1714, UInt<1>(0h0)) when _T_1715 : node _T_1716 = eq(_T_1713, UInt<1>(0h0)) when _T_1716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1713, UInt<1>(0h1), "") : assert_118 node _T_1717 = asUInt(reset) node _T_1718 = eq(_T_1717, UInt<1>(0h0)) when _T_1718 : node _T_1719 = eq(address_ok, UInt<1>(0h0)) when _T_1719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1720 = asUInt(reset) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) when _T_1721 : node _T_1722 = eq(legal_source, UInt<1>(0h0)) when _T_1722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1723 = asUInt(reset) node _T_1724 = eq(_T_1723, UInt<1>(0h0)) when _T_1724 : node _T_1725 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1726 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1727 = asUInt(reset) node _T_1728 = eq(_T_1727, UInt<1>(0h0)) when _T_1728 : node _T_1729 = eq(_T_1726, UInt<1>(0h0)) when _T_1729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1726, UInt<1>(0h1), "") : assert_122 node _T_1730 = eq(io.in.b.bits.mask, mask_1) node _T_1731 = asUInt(reset) node _T_1732 = eq(_T_1731, UInt<1>(0h0)) when _T_1732 : node _T_1733 = eq(_T_1730, UInt<1>(0h0)) when _T_1733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1730, UInt<1>(0h1), "") : assert_123 node _T_1734 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1734 : node _T_1735 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1736 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1737 = and(_T_1735, _T_1736) node _T_1738 = or(UInt<1>(0h0), _T_1737) node _T_1739 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1740 = cvt(_T_1739) node _T_1741 = and(_T_1740, asSInt(UInt<14>(0h2000))) node _T_1742 = asSInt(_T_1741) node _T_1743 = eq(_T_1742, asSInt(UInt<1>(0h0))) node _T_1744 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1745 = cvt(_T_1744) node _T_1746 = and(_T_1745, asSInt(UInt<13>(0h1000))) node _T_1747 = asSInt(_T_1746) node _T_1748 = eq(_T_1747, asSInt(UInt<1>(0h0))) node _T_1749 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1750 = cvt(_T_1749) node _T_1751 = and(_T_1750, asSInt(UInt<17>(0h10000))) node _T_1752 = asSInt(_T_1751) node _T_1753 = eq(_T_1752, asSInt(UInt<1>(0h0))) node _T_1754 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1755 = cvt(_T_1754) node _T_1756 = and(_T_1755, asSInt(UInt<18>(0h2f000))) node _T_1757 = asSInt(_T_1756) node _T_1758 = eq(_T_1757, asSInt(UInt<1>(0h0))) node _T_1759 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1760 = cvt(_T_1759) node _T_1761 = and(_T_1760, asSInt(UInt<17>(0h10000))) node _T_1762 = asSInt(_T_1761) node _T_1763 = eq(_T_1762, asSInt(UInt<1>(0h0))) node _T_1764 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1765 = cvt(_T_1764) node _T_1766 = and(_T_1765, asSInt(UInt<13>(0h1000))) node _T_1767 = asSInt(_T_1766) node _T_1768 = eq(_T_1767, asSInt(UInt<1>(0h0))) node _T_1769 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1770 = cvt(_T_1769) node _T_1771 = and(_T_1770, asSInt(UInt<17>(0h10000))) node _T_1772 = asSInt(_T_1771) node _T_1773 = eq(_T_1772, asSInt(UInt<1>(0h0))) node _T_1774 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1775 = cvt(_T_1774) node _T_1776 = and(_T_1775, asSInt(UInt<27>(0h4000000))) node _T_1777 = asSInt(_T_1776) node _T_1778 = eq(_T_1777, asSInt(UInt<1>(0h0))) node _T_1779 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1780 = cvt(_T_1779) node _T_1781 = and(_T_1780, asSInt(UInt<13>(0h1000))) node _T_1782 = asSInt(_T_1781) node _T_1783 = eq(_T_1782, asSInt(UInt<1>(0h0))) node _T_1784 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1785 = cvt(_T_1784) node _T_1786 = and(_T_1785, asSInt(UInt<29>(0h10000000))) node _T_1787 = asSInt(_T_1786) node _T_1788 = eq(_T_1787, asSInt(UInt<1>(0h0))) node _T_1789 = or(_T_1743, _T_1748) node _T_1790 = or(_T_1789, _T_1753) node _T_1791 = or(_T_1790, _T_1758) node _T_1792 = or(_T_1791, _T_1763) node _T_1793 = or(_T_1792, _T_1768) node _T_1794 = or(_T_1793, _T_1773) node _T_1795 = or(_T_1794, _T_1778) node _T_1796 = or(_T_1795, _T_1783) node _T_1797 = or(_T_1796, _T_1788) node _T_1798 = and(_T_1738, _T_1797) node _T_1799 = or(UInt<1>(0h0), _T_1798) node _T_1800 = and(UInt<1>(0h0), _T_1799) node _T_1801 = asUInt(reset) node _T_1802 = eq(_T_1801, UInt<1>(0h0)) when _T_1802 : node _T_1803 = eq(_T_1800, UInt<1>(0h0)) when _T_1803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1800, UInt<1>(0h1), "") : assert_124 node _T_1804 = asUInt(reset) node _T_1805 = eq(_T_1804, UInt<1>(0h0)) when _T_1805 : node _T_1806 = eq(address_ok, UInt<1>(0h0)) when _T_1806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1807 = asUInt(reset) node _T_1808 = eq(_T_1807, UInt<1>(0h0)) when _T_1808 : node _T_1809 = eq(legal_source, UInt<1>(0h0)) when _T_1809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1813 = eq(io.in.b.bits.mask, mask_1) node _T_1814 = asUInt(reset) node _T_1815 = eq(_T_1814, UInt<1>(0h0)) when _T_1815 : node _T_1816 = eq(_T_1813, UInt<1>(0h0)) when _T_1816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1813, UInt<1>(0h1), "") : assert_128 node _T_1817 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1818 = asUInt(reset) node _T_1819 = eq(_T_1818, UInt<1>(0h0)) when _T_1819 : node _T_1820 = eq(_T_1817, UInt<1>(0h0)) when _T_1820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1817, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1821 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1822 = asUInt(reset) node _T_1823 = eq(_T_1822, UInt<1>(0h0)) when _T_1823 : node _T_1824 = eq(_T_1821, UInt<1>(0h0)) when _T_1824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1821, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_14 = shr(io.in.c.bits.source, 2) node _source_ok_T_15 = eq(_source_ok_T_14, UInt<1>(0h0)) node _source_ok_T_16 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_T_18 = leq(source_ok_uncommonBits_2, UInt<2>(0h2)) node _source_ok_T_19 = and(_source_ok_T_17, _source_ok_T_18) node _source_ok_T_20 = eq(io.in.c.bits.source, UInt<2>(0h3)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_19 connect _source_ok_WIRE_2[1], _source_ok_T_20 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_1825 = shr(io.in.c.bits.source, 2) node _T_1826 = eq(_T_1825, UInt<1>(0h0)) node _T_1827 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1828 = and(_T_1826, _T_1827) node _T_1829 = leq(uncommonBits_13, UInt<2>(0h2)) node _T_1830 = and(_T_1828, _T_1829) node _T_1831 = eq(_T_1830, UInt<1>(0h0)) node _T_1832 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<1>(0h0))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = or(_T_1831, _T_1836) node _T_1838 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_1839 = eq(_T_1838, UInt<1>(0h0)) node _T_1840 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1841 = cvt(_T_1840) node _T_1842 = and(_T_1841, asSInt(UInt<1>(0h0))) node _T_1843 = asSInt(_T_1842) node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0))) node _T_1845 = or(_T_1839, _T_1844) node _T_1846 = and(_T_1837, _T_1845) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_131 node _T_1850 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1850 : node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(address_ok_1, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1854 = asUInt(reset) node _T_1855 = eq(_T_1854, UInt<1>(0h0)) when _T_1855 : node _T_1856 = eq(source_ok_2, UInt<1>(0h0)) when _T_1856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1857 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(_T_1857, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1857, UInt<1>(0h1), "") : assert_134 node _T_1861 = asUInt(reset) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : node _T_1863 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1864 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_136 node _T_1868 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_137 node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1872 : node _T_1873 = asUInt(reset) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) when _T_1874 : node _T_1875 = eq(address_ok_1, UInt<1>(0h0)) when _T_1875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1876 = asUInt(reset) node _T_1877 = eq(_T_1876, UInt<1>(0h0)) when _T_1877 : node _T_1878 = eq(source_ok_2, UInt<1>(0h0)) when _T_1878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1879 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_140 node _T_1883 = asUInt(reset) node _T_1884 = eq(_T_1883, UInt<1>(0h0)) when _T_1884 : node _T_1885 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1886 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1887 = asUInt(reset) node _T_1888 = eq(_T_1887, UInt<1>(0h0)) when _T_1888 : node _T_1889 = eq(_T_1886, UInt<1>(0h0)) when _T_1889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1886, UInt<1>(0h1), "") : assert_142 node _T_1890 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1890 : node _T_1891 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1892 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1893 = and(_T_1891, _T_1892) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_1894 = shr(io.in.c.bits.source, 2) node _T_1895 = eq(_T_1894, UInt<1>(0h0)) node _T_1896 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1897 = and(_T_1895, _T_1896) node _T_1898 = leq(uncommonBits_14, UInt<2>(0h2)) node _T_1899 = and(_T_1897, _T_1898) node _T_1900 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_1901 = or(_T_1899, _T_1900) node _T_1902 = and(_T_1893, _T_1901) node _T_1903 = or(UInt<1>(0h0), _T_1902) node _T_1904 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1905 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1906 = cvt(_T_1905) node _T_1907 = and(_T_1906, asSInt(UInt<14>(0h2000))) node _T_1908 = asSInt(_T_1907) node _T_1909 = eq(_T_1908, asSInt(UInt<1>(0h0))) node _T_1910 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1911 = cvt(_T_1910) node _T_1912 = and(_T_1911, asSInt(UInt<13>(0h1000))) node _T_1913 = asSInt(_T_1912) node _T_1914 = eq(_T_1913, asSInt(UInt<1>(0h0))) node _T_1915 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1916 = cvt(_T_1915) node _T_1917 = and(_T_1916, asSInt(UInt<17>(0h10000))) node _T_1918 = asSInt(_T_1917) node _T_1919 = eq(_T_1918, asSInt(UInt<1>(0h0))) node _T_1920 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1921 = cvt(_T_1920) node _T_1922 = and(_T_1921, asSInt(UInt<18>(0h2f000))) node _T_1923 = asSInt(_T_1922) node _T_1924 = eq(_T_1923, asSInt(UInt<1>(0h0))) node _T_1925 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1926 = cvt(_T_1925) node _T_1927 = and(_T_1926, asSInt(UInt<17>(0h10000))) node _T_1928 = asSInt(_T_1927) node _T_1929 = eq(_T_1928, asSInt(UInt<1>(0h0))) node _T_1930 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1931 = cvt(_T_1930) node _T_1932 = and(_T_1931, asSInt(UInt<13>(0h1000))) node _T_1933 = asSInt(_T_1932) node _T_1934 = eq(_T_1933, asSInt(UInt<1>(0h0))) node _T_1935 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1936 = cvt(_T_1935) node _T_1937 = and(_T_1936, asSInt(UInt<27>(0h4000000))) node _T_1938 = asSInt(_T_1937) node _T_1939 = eq(_T_1938, asSInt(UInt<1>(0h0))) node _T_1940 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1941 = cvt(_T_1940) node _T_1942 = and(_T_1941, asSInt(UInt<13>(0h1000))) node _T_1943 = asSInt(_T_1942) node _T_1944 = eq(_T_1943, asSInt(UInt<1>(0h0))) node _T_1945 = or(_T_1909, _T_1914) node _T_1946 = or(_T_1945, _T_1919) node _T_1947 = or(_T_1946, _T_1924) node _T_1948 = or(_T_1947, _T_1929) node _T_1949 = or(_T_1948, _T_1934) node _T_1950 = or(_T_1949, _T_1939) node _T_1951 = or(_T_1950, _T_1944) node _T_1952 = and(_T_1904, _T_1951) node _T_1953 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1954 = or(UInt<1>(0h0), _T_1953) node _T_1955 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1956 = cvt(_T_1955) node _T_1957 = and(_T_1956, asSInt(UInt<17>(0h10000))) node _T_1958 = asSInt(_T_1957) node _T_1959 = eq(_T_1958, asSInt(UInt<1>(0h0))) node _T_1960 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1961 = cvt(_T_1960) node _T_1962 = and(_T_1961, asSInt(UInt<29>(0h10000000))) node _T_1963 = asSInt(_T_1962) node _T_1964 = eq(_T_1963, asSInt(UInt<1>(0h0))) node _T_1965 = or(_T_1959, _T_1964) node _T_1966 = and(_T_1954, _T_1965) node _T_1967 = or(UInt<1>(0h0), _T_1952) node _T_1968 = or(_T_1967, _T_1966) node _T_1969 = and(_T_1903, _T_1968) node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(_T_1969, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1969, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_1973 = shr(io.in.c.bits.source, 2) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) node _T_1975 = leq(UInt<1>(0h0), uncommonBits_15) node _T_1976 = and(_T_1974, _T_1975) node _T_1977 = leq(uncommonBits_15, UInt<2>(0h2)) node _T_1978 = and(_T_1976, _T_1977) node _T_1979 = eq(io.in.c.bits.source, UInt<2>(0h3)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_1978 connect _WIRE_6[1], _T_1979 node _T_1980 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1981 = mux(_WIRE_6[0], _T_1980, UInt<1>(0h0)) node _T_1982 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1983 = or(_T_1981, _T_1982) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1983 node _T_1984 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1985 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1986 = and(_T_1984, _T_1985) node _T_1987 = or(UInt<1>(0h0), _T_1986) node _T_1988 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1989 = cvt(_T_1988) node _T_1990 = and(_T_1989, asSInt(UInt<14>(0h2000))) node _T_1991 = asSInt(_T_1990) node _T_1992 = eq(_T_1991, asSInt(UInt<1>(0h0))) node _T_1993 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1994 = cvt(_T_1993) node _T_1995 = and(_T_1994, asSInt(UInt<13>(0h1000))) node _T_1996 = asSInt(_T_1995) node _T_1997 = eq(_T_1996, asSInt(UInt<1>(0h0))) node _T_1998 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1999 = cvt(_T_1998) node _T_2000 = and(_T_1999, asSInt(UInt<17>(0h10000))) node _T_2001 = asSInt(_T_2000) node _T_2002 = eq(_T_2001, asSInt(UInt<1>(0h0))) node _T_2003 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2004 = cvt(_T_2003) node _T_2005 = and(_T_2004, asSInt(UInt<18>(0h2f000))) node _T_2006 = asSInt(_T_2005) node _T_2007 = eq(_T_2006, asSInt(UInt<1>(0h0))) node _T_2008 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2009 = cvt(_T_2008) node _T_2010 = and(_T_2009, asSInt(UInt<17>(0h10000))) node _T_2011 = asSInt(_T_2010) node _T_2012 = eq(_T_2011, asSInt(UInt<1>(0h0))) node _T_2013 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2014 = cvt(_T_2013) node _T_2015 = and(_T_2014, asSInt(UInt<13>(0h1000))) node _T_2016 = asSInt(_T_2015) node _T_2017 = eq(_T_2016, asSInt(UInt<1>(0h0))) node _T_2018 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2019 = cvt(_T_2018) node _T_2020 = and(_T_2019, asSInt(UInt<17>(0h10000))) node _T_2021 = asSInt(_T_2020) node _T_2022 = eq(_T_2021, asSInt(UInt<1>(0h0))) node _T_2023 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2024 = cvt(_T_2023) node _T_2025 = and(_T_2024, asSInt(UInt<27>(0h4000000))) node _T_2026 = asSInt(_T_2025) node _T_2027 = eq(_T_2026, asSInt(UInt<1>(0h0))) node _T_2028 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2029 = cvt(_T_2028) node _T_2030 = and(_T_2029, asSInt(UInt<13>(0h1000))) node _T_2031 = asSInt(_T_2030) node _T_2032 = eq(_T_2031, asSInt(UInt<1>(0h0))) node _T_2033 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2034 = cvt(_T_2033) node _T_2035 = and(_T_2034, asSInt(UInt<29>(0h10000000))) node _T_2036 = asSInt(_T_2035) node _T_2037 = eq(_T_2036, asSInt(UInt<1>(0h0))) node _T_2038 = or(_T_1992, _T_1997) node _T_2039 = or(_T_2038, _T_2002) node _T_2040 = or(_T_2039, _T_2007) node _T_2041 = or(_T_2040, _T_2012) node _T_2042 = or(_T_2041, _T_2017) node _T_2043 = or(_T_2042, _T_2022) node _T_2044 = or(_T_2043, _T_2027) node _T_2045 = or(_T_2044, _T_2032) node _T_2046 = or(_T_2045, _T_2037) node _T_2047 = and(_T_1987, _T_2046) node _T_2048 = or(UInt<1>(0h0), _T_2047) node _T_2049 = and(_WIRE_7, _T_2048) node _T_2050 = asUInt(reset) node _T_2051 = eq(_T_2050, UInt<1>(0h0)) when _T_2051 : node _T_2052 = eq(_T_2049, UInt<1>(0h0)) when _T_2052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2049, UInt<1>(0h1), "") : assert_144 node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(source_ok_2, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2056 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2057 = asUInt(reset) node _T_2058 = eq(_T_2057, UInt<1>(0h0)) when _T_2058 : node _T_2059 = eq(_T_2056, UInt<1>(0h0)) when _T_2059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2056, UInt<1>(0h1), "") : assert_146 node _T_2060 = asUInt(reset) node _T_2061 = eq(_T_2060, UInt<1>(0h0)) when _T_2061 : node _T_2062 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2063 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2064 = asUInt(reset) node _T_2065 = eq(_T_2064, UInt<1>(0h0)) when _T_2065 : node _T_2066 = eq(_T_2063, UInt<1>(0h0)) when _T_2066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2063, UInt<1>(0h1), "") : assert_148 node _T_2067 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2068 = asUInt(reset) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) when _T_2069 : node _T_2070 = eq(_T_2067, UInt<1>(0h0)) when _T_2070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2067, UInt<1>(0h1), "") : assert_149 node _T_2071 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2071 : node _T_2072 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2073 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2074 = and(_T_2072, _T_2073) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_2075 = shr(io.in.c.bits.source, 2) node _T_2076 = eq(_T_2075, UInt<1>(0h0)) node _T_2077 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2078 = and(_T_2076, _T_2077) node _T_2079 = leq(uncommonBits_16, UInt<2>(0h2)) node _T_2080 = and(_T_2078, _T_2079) node _T_2081 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_2082 = or(_T_2080, _T_2081) node _T_2083 = and(_T_2074, _T_2082) node _T_2084 = or(UInt<1>(0h0), _T_2083) node _T_2085 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2086 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2087 = cvt(_T_2086) node _T_2088 = and(_T_2087, asSInt(UInt<14>(0h2000))) node _T_2089 = asSInt(_T_2088) node _T_2090 = eq(_T_2089, asSInt(UInt<1>(0h0))) node _T_2091 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2092 = cvt(_T_2091) node _T_2093 = and(_T_2092, asSInt(UInt<13>(0h1000))) node _T_2094 = asSInt(_T_2093) node _T_2095 = eq(_T_2094, asSInt(UInt<1>(0h0))) node _T_2096 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2097 = cvt(_T_2096) node _T_2098 = and(_T_2097, asSInt(UInt<17>(0h10000))) node _T_2099 = asSInt(_T_2098) node _T_2100 = eq(_T_2099, asSInt(UInt<1>(0h0))) node _T_2101 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2102 = cvt(_T_2101) node _T_2103 = and(_T_2102, asSInt(UInt<18>(0h2f000))) node _T_2104 = asSInt(_T_2103) node _T_2105 = eq(_T_2104, asSInt(UInt<1>(0h0))) node _T_2106 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2107 = cvt(_T_2106) node _T_2108 = and(_T_2107, asSInt(UInt<17>(0h10000))) node _T_2109 = asSInt(_T_2108) node _T_2110 = eq(_T_2109, asSInt(UInt<1>(0h0))) node _T_2111 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2112 = cvt(_T_2111) node _T_2113 = and(_T_2112, asSInt(UInt<13>(0h1000))) node _T_2114 = asSInt(_T_2113) node _T_2115 = eq(_T_2114, asSInt(UInt<1>(0h0))) node _T_2116 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2117 = cvt(_T_2116) node _T_2118 = and(_T_2117, asSInt(UInt<27>(0h4000000))) node _T_2119 = asSInt(_T_2118) node _T_2120 = eq(_T_2119, asSInt(UInt<1>(0h0))) node _T_2121 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2122 = cvt(_T_2121) node _T_2123 = and(_T_2122, asSInt(UInt<13>(0h1000))) node _T_2124 = asSInt(_T_2123) node _T_2125 = eq(_T_2124, asSInt(UInt<1>(0h0))) node _T_2126 = or(_T_2090, _T_2095) node _T_2127 = or(_T_2126, _T_2100) node _T_2128 = or(_T_2127, _T_2105) node _T_2129 = or(_T_2128, _T_2110) node _T_2130 = or(_T_2129, _T_2115) node _T_2131 = or(_T_2130, _T_2120) node _T_2132 = or(_T_2131, _T_2125) node _T_2133 = and(_T_2085, _T_2132) node _T_2134 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2135 = or(UInt<1>(0h0), _T_2134) node _T_2136 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2137 = cvt(_T_2136) node _T_2138 = and(_T_2137, asSInt(UInt<17>(0h10000))) node _T_2139 = asSInt(_T_2138) node _T_2140 = eq(_T_2139, asSInt(UInt<1>(0h0))) node _T_2141 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2142 = cvt(_T_2141) node _T_2143 = and(_T_2142, asSInt(UInt<29>(0h10000000))) node _T_2144 = asSInt(_T_2143) node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0))) node _T_2146 = or(_T_2140, _T_2145) node _T_2147 = and(_T_2135, _T_2146) node _T_2148 = or(UInt<1>(0h0), _T_2133) node _T_2149 = or(_T_2148, _T_2147) node _T_2150 = and(_T_2084, _T_2149) node _T_2151 = asUInt(reset) node _T_2152 = eq(_T_2151, UInt<1>(0h0)) when _T_2152 : node _T_2153 = eq(_T_2150, UInt<1>(0h0)) when _T_2153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2150, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_2154 = shr(io.in.c.bits.source, 2) node _T_2155 = eq(_T_2154, UInt<1>(0h0)) node _T_2156 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2157 = and(_T_2155, _T_2156) node _T_2158 = leq(uncommonBits_17, UInt<2>(0h2)) node _T_2159 = and(_T_2157, _T_2158) node _T_2160 = eq(io.in.c.bits.source, UInt<2>(0h3)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2159 connect _WIRE_8[1], _T_2160 node _T_2161 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2162 = mux(_WIRE_8[0], _T_2161, UInt<1>(0h0)) node _T_2163 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2164 = or(_T_2162, _T_2163) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2164 node _T_2165 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2166 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2167 = and(_T_2165, _T_2166) node _T_2168 = or(UInt<1>(0h0), _T_2167) node _T_2169 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2170 = cvt(_T_2169) node _T_2171 = and(_T_2170, asSInt(UInt<14>(0h2000))) node _T_2172 = asSInt(_T_2171) node _T_2173 = eq(_T_2172, asSInt(UInt<1>(0h0))) node _T_2174 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2175 = cvt(_T_2174) node _T_2176 = and(_T_2175, asSInt(UInt<13>(0h1000))) node _T_2177 = asSInt(_T_2176) node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0))) node _T_2179 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2180 = cvt(_T_2179) node _T_2181 = and(_T_2180, asSInt(UInt<17>(0h10000))) node _T_2182 = asSInt(_T_2181) node _T_2183 = eq(_T_2182, asSInt(UInt<1>(0h0))) node _T_2184 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2185 = cvt(_T_2184) node _T_2186 = and(_T_2185, asSInt(UInt<18>(0h2f000))) node _T_2187 = asSInt(_T_2186) node _T_2188 = eq(_T_2187, asSInt(UInt<1>(0h0))) node _T_2189 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2190 = cvt(_T_2189) node _T_2191 = and(_T_2190, asSInt(UInt<17>(0h10000))) node _T_2192 = asSInt(_T_2191) node _T_2193 = eq(_T_2192, asSInt(UInt<1>(0h0))) node _T_2194 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2195 = cvt(_T_2194) node _T_2196 = and(_T_2195, asSInt(UInt<13>(0h1000))) node _T_2197 = asSInt(_T_2196) node _T_2198 = eq(_T_2197, asSInt(UInt<1>(0h0))) node _T_2199 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2200 = cvt(_T_2199) node _T_2201 = and(_T_2200, asSInt(UInt<17>(0h10000))) node _T_2202 = asSInt(_T_2201) node _T_2203 = eq(_T_2202, asSInt(UInt<1>(0h0))) node _T_2204 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2205 = cvt(_T_2204) node _T_2206 = and(_T_2205, asSInt(UInt<27>(0h4000000))) node _T_2207 = asSInt(_T_2206) node _T_2208 = eq(_T_2207, asSInt(UInt<1>(0h0))) node _T_2209 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2210 = cvt(_T_2209) node _T_2211 = and(_T_2210, asSInt(UInt<13>(0h1000))) node _T_2212 = asSInt(_T_2211) node _T_2213 = eq(_T_2212, asSInt(UInt<1>(0h0))) node _T_2214 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2215 = cvt(_T_2214) node _T_2216 = and(_T_2215, asSInt(UInt<29>(0h10000000))) node _T_2217 = asSInt(_T_2216) node _T_2218 = eq(_T_2217, asSInt(UInt<1>(0h0))) node _T_2219 = or(_T_2173, _T_2178) node _T_2220 = or(_T_2219, _T_2183) node _T_2221 = or(_T_2220, _T_2188) node _T_2222 = or(_T_2221, _T_2193) node _T_2223 = or(_T_2222, _T_2198) node _T_2224 = or(_T_2223, _T_2203) node _T_2225 = or(_T_2224, _T_2208) node _T_2226 = or(_T_2225, _T_2213) node _T_2227 = or(_T_2226, _T_2218) node _T_2228 = and(_T_2168, _T_2227) node _T_2229 = or(UInt<1>(0h0), _T_2228) node _T_2230 = and(_WIRE_9, _T_2229) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_151 node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : node _T_2236 = eq(source_ok_2, UInt<1>(0h0)) when _T_2236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2237 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_153 node _T_2241 = asUInt(reset) node _T_2242 = eq(_T_2241, UInt<1>(0h0)) when _T_2242 : node _T_2243 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2244 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(_T_2244, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2244, UInt<1>(0h1), "") : assert_155 node _T_2248 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2248 : node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(address_ok_1, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : node _T_2254 = eq(source_ok_2, UInt<1>(0h0)) when _T_2254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2255 = asUInt(reset) node _T_2256 = eq(_T_2255, UInt<1>(0h0)) when _T_2256 : node _T_2257 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2258 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(_T_2258, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2258, UInt<1>(0h1), "") : assert_159 node _T_2262 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_160 node _T_2266 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2266 : node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(address_ok_1, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(source_ok_2, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2273 = asUInt(reset) node _T_2274 = eq(_T_2273, UInt<1>(0h0)) when _T_2274 : node _T_2275 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2276 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2277 = asUInt(reset) node _T_2278 = eq(_T_2277, UInt<1>(0h0)) when _T_2278 : node _T_2279 = eq(_T_2276, UInt<1>(0h0)) when _T_2279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2276, UInt<1>(0h1), "") : assert_164 node _T_2280 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2280 : node _T_2281 = asUInt(reset) node _T_2282 = eq(_T_2281, UInt<1>(0h0)) when _T_2282 : node _T_2283 = eq(address_ok_1, UInt<1>(0h0)) when _T_2283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(source_ok_2, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2287 = asUInt(reset) node _T_2288 = eq(_T_2287, UInt<1>(0h0)) when _T_2288 : node _T_2289 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2290 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2291 = asUInt(reset) node _T_2292 = eq(_T_2291, UInt<1>(0h0)) when _T_2292 : node _T_2293 = eq(_T_2290, UInt<1>(0h0)) when _T_2293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2290, UInt<1>(0h1), "") : assert_168 node _T_2294 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2295 = asUInt(reset) node _T_2296 = eq(_T_2295, UInt<1>(0h0)) when _T_2296 : node _T_2297 = eq(_T_2294, UInt<1>(0h0)) when _T_2297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2294, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2298 = asUInt(reset) node _T_2299 = eq(_T_2298, UInt<1>(0h0)) when _T_2299 : node _T_2300 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2301 = eq(a_first, UInt<1>(0h0)) node _T_2302 = and(io.in.a.valid, _T_2301) when _T_2302 : node _T_2303 = eq(io.in.a.bits.opcode, opcode) node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(_T_2303, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2303, UInt<1>(0h1), "") : assert_171 node _T_2307 = eq(io.in.a.bits.param, param) node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : node _T_2310 = eq(_T_2307, UInt<1>(0h0)) when _T_2310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2307, UInt<1>(0h1), "") : assert_172 node _T_2311 = eq(io.in.a.bits.size, size) node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : node _T_2314 = eq(_T_2311, UInt<1>(0h0)) when _T_2314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2311, UInt<1>(0h1), "") : assert_173 node _T_2315 = eq(io.in.a.bits.source, source) node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : node _T_2318 = eq(_T_2315, UInt<1>(0h0)) when _T_2318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2315, UInt<1>(0h1), "") : assert_174 node _T_2319 = eq(io.in.a.bits.address, address) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_175 node _T_2323 = and(io.in.a.ready, io.in.a.valid) node _T_2324 = and(_T_2323, a_first) when _T_2324 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2325 = eq(d_first, UInt<1>(0h0)) node _T_2326 = and(io.in.d.valid, _T_2325) when _T_2326 : node _T_2327 = eq(io.in.d.bits.opcode, opcode_1) node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : node _T_2330 = eq(_T_2327, UInt<1>(0h0)) when _T_2330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2327, UInt<1>(0h1), "") : assert_176 node _T_2331 = eq(io.in.d.bits.param, param_1) node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(_T_2331, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2331, UInt<1>(0h1), "") : assert_177 node _T_2335 = eq(io.in.d.bits.size, size_1) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_178 node _T_2339 = eq(io.in.d.bits.source, source_1) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_179 node _T_2343 = eq(io.in.d.bits.sink, sink) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_180 node _T_2347 = eq(io.in.d.bits.denied, denied) node _T_2348 = asUInt(reset) node _T_2349 = eq(_T_2348, UInt<1>(0h0)) when _T_2349 : node _T_2350 = eq(_T_2347, UInt<1>(0h0)) when _T_2350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2347, UInt<1>(0h1), "") : assert_181 node _T_2351 = and(io.in.d.ready, io.in.d.valid) node _T_2352 = and(_T_2351, d_first) when _T_2352 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2353 = eq(b_first, UInt<1>(0h0)) node _T_2354 = and(io.in.b.valid, _T_2353) when _T_2354 : node _T_2355 = eq(io.in.b.bits.opcode, opcode_2) node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(_T_2355, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2355, UInt<1>(0h1), "") : assert_182 node _T_2359 = eq(io.in.b.bits.param, param_2) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(_T_2359, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2359, UInt<1>(0h1), "") : assert_183 node _T_2363 = eq(io.in.b.bits.size, size_2) node _T_2364 = asUInt(reset) node _T_2365 = eq(_T_2364, UInt<1>(0h0)) when _T_2365 : node _T_2366 = eq(_T_2363, UInt<1>(0h0)) when _T_2366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2363, UInt<1>(0h1), "") : assert_184 node _T_2367 = eq(io.in.b.bits.source, source_2) node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(_T_2367, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2367, UInt<1>(0h1), "") : assert_185 node _T_2371 = eq(io.in.b.bits.address, address_1) node _T_2372 = asUInt(reset) node _T_2373 = eq(_T_2372, UInt<1>(0h0)) when _T_2373 : node _T_2374 = eq(_T_2371, UInt<1>(0h0)) when _T_2374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2371, UInt<1>(0h1), "") : assert_186 node _T_2375 = and(io.in.b.ready, io.in.b.valid) node _T_2376 = and(_T_2375, b_first) when _T_2376 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2377 = eq(c_first, UInt<1>(0h0)) node _T_2378 = and(io.in.c.valid, _T_2377) when _T_2378 : node _T_2379 = eq(io.in.c.bits.opcode, opcode_3) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_187 node _T_2383 = eq(io.in.c.bits.param, param_3) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_188 node _T_2387 = eq(io.in.c.bits.size, size_3) node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(_T_2387, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2387, UInt<1>(0h1), "") : assert_189 node _T_2391 = eq(io.in.c.bits.source, source_3) node _T_2392 = asUInt(reset) node _T_2393 = eq(_T_2392, UInt<1>(0h0)) when _T_2393 : node _T_2394 = eq(_T_2391, UInt<1>(0h0)) when _T_2394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2391, UInt<1>(0h1), "") : assert_190 node _T_2395 = eq(io.in.c.bits.address, address_2) node _T_2396 = asUInt(reset) node _T_2397 = eq(_T_2396, UInt<1>(0h0)) when _T_2397 : node _T_2398 = eq(_T_2395, UInt<1>(0h0)) when _T_2398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2395, UInt<1>(0h1), "") : assert_191 node _T_2399 = and(io.in.c.ready, io.in.c.valid) node _T_2400 = and(_T_2399, c_first) when _T_2400 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes : UInt<32>, clock, reset, UInt<32>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<4> connect a_set, UInt<4>(0h0) wire a_set_wo_ready : UInt<4> connect a_set_wo_ready, UInt<4>(0h0) wire a_opcodes_set : UInt<16> connect a_opcodes_set, UInt<16>(0h0) wire a_sizes_set : UInt<32> connect a_sizes_set, UInt<32>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2401 = and(io.in.a.valid, a_first_1) node _T_2402 = and(_T_2401, UInt<1>(0h1)) when _T_2402 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2403 = and(io.in.a.ready, io.in.a.valid) node _T_2404 = and(_T_2403, a_first_1) node _T_2405 = and(_T_2404, UInt<1>(0h1)) when _T_2405 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2406 = dshr(inflight, io.in.a.bits.source) node _T_2407 = bits(_T_2406, 0, 0) node _T_2408 = eq(_T_2407, UInt<1>(0h0)) node _T_2409 = asUInt(reset) node _T_2410 = eq(_T_2409, UInt<1>(0h0)) when _T_2410 : node _T_2411 = eq(_T_2408, UInt<1>(0h0)) when _T_2411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2408, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<4> connect d_clr, UInt<4>(0h0) wire d_clr_wo_ready : UInt<4> connect d_clr_wo_ready, UInt<4>(0h0) wire d_opcodes_clr : UInt<16> connect d_opcodes_clr, UInt<16>(0h0) wire d_sizes_clr : UInt<32> connect d_sizes_clr, UInt<32>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2412 = and(io.in.d.valid, d_first_1) node _T_2413 = and(_T_2412, UInt<1>(0h1)) node _T_2414 = eq(d_release_ack, UInt<1>(0h0)) node _T_2415 = and(_T_2413, _T_2414) when _T_2415 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2416 = and(io.in.d.ready, io.in.d.valid) node _T_2417 = and(_T_2416, d_first_1) node _T_2418 = and(_T_2417, UInt<1>(0h1)) node _T_2419 = eq(d_release_ack, UInt<1>(0h0)) node _T_2420 = and(_T_2418, _T_2419) when _T_2420 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2421 = and(io.in.d.valid, d_first_1) node _T_2422 = and(_T_2421, UInt<1>(0h1)) node _T_2423 = eq(d_release_ack, UInt<1>(0h0)) node _T_2424 = and(_T_2422, _T_2423) when _T_2424 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2425 = dshr(inflight, io.in.d.bits.source) node _T_2426 = bits(_T_2425, 0, 0) node _T_2427 = or(_T_2426, same_cycle_resp) node _T_2428 = asUInt(reset) node _T_2429 = eq(_T_2428, UInt<1>(0h0)) when _T_2429 : node _T_2430 = eq(_T_2427, UInt<1>(0h0)) when _T_2430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2427, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2431 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2432 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2433 = or(_T_2431, _T_2432) node _T_2434 = asUInt(reset) node _T_2435 = eq(_T_2434, UInt<1>(0h0)) when _T_2435 : node _T_2436 = eq(_T_2433, UInt<1>(0h0)) when _T_2436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2433, UInt<1>(0h1), "") : assert_194 node _T_2437 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2438 = asUInt(reset) node _T_2439 = eq(_T_2438, UInt<1>(0h0)) when _T_2439 : node _T_2440 = eq(_T_2437, UInt<1>(0h0)) when _T_2440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2437, UInt<1>(0h1), "") : assert_195 else : node _T_2441 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2442 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2443 = or(_T_2441, _T_2442) node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(_T_2443, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2443, UInt<1>(0h1), "") : assert_196 node _T_2447 = eq(io.in.d.bits.size, a_size_lookup) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_197 node _T_2451 = and(io.in.d.valid, d_first_1) node _T_2452 = and(_T_2451, a_first_1) node _T_2453 = and(_T_2452, io.in.a.valid) node _T_2454 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2455 = and(_T_2453, _T_2454) node _T_2456 = eq(d_release_ack, UInt<1>(0h0)) node _T_2457 = and(_T_2455, _T_2456) when _T_2457 : node _T_2458 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2459 = or(_T_2458, io.in.a.ready) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_198 node _T_2463 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2464 = orr(a_set_wo_ready) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) node _T_2466 = or(_T_2463, _T_2465) node _T_2467 = asUInt(reset) node _T_2468 = eq(_T_2467, UInt<1>(0h0)) when _T_2468 : node _T_2469 = eq(_T_2466, UInt<1>(0h0)) when _T_2469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2466, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_84 node _T_2470 = orr(inflight) node _T_2471 = eq(_T_2470, UInt<1>(0h0)) node _T_2472 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2473 = or(_T_2471, _T_2472) node _T_2474 = lt(watchdog, plusarg_reader.out) node _T_2475 = or(_T_2473, _T_2474) node _T_2476 = asUInt(reset) node _T_2477 = eq(_T_2476, UInt<1>(0h0)) when _T_2477 : node _T_2478 = eq(_T_2475, UInt<1>(0h0)) when _T_2478 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2475, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2479 = and(io.in.a.ready, io.in.a.valid) node _T_2480 = and(io.in.d.ready, io.in.d.valid) node _T_2481 = or(_T_2479, _T_2480) when _T_2481 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes_1 : UInt<32>, clock, reset, UInt<32>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<4> connect c_set, UInt<4>(0h0) wire c_set_wo_ready : UInt<4> connect c_set_wo_ready, UInt<4>(0h0) wire c_opcodes_set : UInt<16> connect c_opcodes_set, UInt<16>(0h0) wire c_sizes_set : UInt<32> connect c_sizes_set, UInt<32>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2482 = and(io.in.c.valid, c_first_1) node _T_2483 = bits(io.in.c.bits.opcode, 2, 2) node _T_2484 = bits(io.in.c.bits.opcode, 1, 1) node _T_2485 = and(_T_2483, _T_2484) node _T_2486 = and(_T_2482, _T_2485) when _T_2486 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2487 = and(io.in.c.ready, io.in.c.valid) node _T_2488 = and(_T_2487, c_first_1) node _T_2489 = bits(io.in.c.bits.opcode, 2, 2) node _T_2490 = bits(io.in.c.bits.opcode, 1, 1) node _T_2491 = and(_T_2489, _T_2490) node _T_2492 = and(_T_2488, _T_2491) when _T_2492 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2493 = dshr(inflight_1, io.in.c.bits.source) node _T_2494 = bits(_T_2493, 0, 0) node _T_2495 = eq(_T_2494, UInt<1>(0h0)) node _T_2496 = asUInt(reset) node _T_2497 = eq(_T_2496, UInt<1>(0h0)) when _T_2497 : node _T_2498 = eq(_T_2495, UInt<1>(0h0)) when _T_2498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2495, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<4> connect d_clr_1, UInt<4>(0h0) wire d_clr_wo_ready_1 : UInt<4> connect d_clr_wo_ready_1, UInt<4>(0h0) wire d_opcodes_clr_1 : UInt<16> connect d_opcodes_clr_1, UInt<16>(0h0) wire d_sizes_clr_1 : UInt<32> connect d_sizes_clr_1, UInt<32>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2499 = and(io.in.d.valid, d_first_2) node _T_2500 = and(_T_2499, UInt<1>(0h1)) node _T_2501 = and(_T_2500, d_release_ack_1) when _T_2501 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2502 = and(io.in.d.ready, io.in.d.valid) node _T_2503 = and(_T_2502, d_first_2) node _T_2504 = and(_T_2503, UInt<1>(0h1)) node _T_2505 = and(_T_2504, d_release_ack_1) when _T_2505 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2506 = and(io.in.d.valid, d_first_2) node _T_2507 = and(_T_2506, UInt<1>(0h1)) node _T_2508 = and(_T_2507, d_release_ack_1) when _T_2508 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2509 = dshr(inflight_1, io.in.d.bits.source) node _T_2510 = bits(_T_2509, 0, 0) node _T_2511 = or(_T_2510, same_cycle_resp_1) node _T_2512 = asUInt(reset) node _T_2513 = eq(_T_2512, UInt<1>(0h0)) when _T_2513 : node _T_2514 = eq(_T_2511, UInt<1>(0h0)) when _T_2514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2511, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2515 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2516 = asUInt(reset) node _T_2517 = eq(_T_2516, UInt<1>(0h0)) when _T_2517 : node _T_2518 = eq(_T_2515, UInt<1>(0h0)) when _T_2518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2515, UInt<1>(0h1), "") : assert_203 else : node _T_2519 = eq(io.in.d.bits.size, c_size_lookup) node _T_2520 = asUInt(reset) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) when _T_2521 : node _T_2522 = eq(_T_2519, UInt<1>(0h0)) when _T_2522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2519, UInt<1>(0h1), "") : assert_204 node _T_2523 = and(io.in.d.valid, d_first_2) node _T_2524 = and(_T_2523, c_first_1) node _T_2525 = and(_T_2524, io.in.c.valid) node _T_2526 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2527 = and(_T_2525, _T_2526) node _T_2528 = and(_T_2527, d_release_ack_1) node _T_2529 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2530 = and(_T_2528, _T_2529) when _T_2530 : node _T_2531 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2532 = or(_T_2531, io.in.c.ready) node _T_2533 = asUInt(reset) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) when _T_2534 : node _T_2535 = eq(_T_2532, UInt<1>(0h0)) when _T_2535 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2532, UInt<1>(0h1), "") : assert_205 node _T_2536 = orr(c_set_wo_ready) when _T_2536 : node _T_2537 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_85 node _T_2541 = orr(inflight_1) node _T_2542 = eq(_T_2541, UInt<1>(0h0)) node _T_2543 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2544 = or(_T_2542, _T_2543) node _T_2545 = lt(watchdog_1, plusarg_reader_1.out) node _T_2546 = or(_T_2544, _T_2545) node _T_2547 = asUInt(reset) node _T_2548 = eq(_T_2547, UInt<1>(0h0)) when _T_2548 : node _T_2549 = eq(_T_2546, UInt<1>(0h0)) when _T_2549 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2546, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2550 = and(io.in.c.ready, io.in.c.valid) node _T_2551 = and(io.in.d.ready, io.in.d.valid) node _T_2552 = or(_T_2550, _T_2551) when _T_2552 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2553 = and(io.in.d.ready, io.in.d.valid) node _T_2554 = and(_T_2553, d_first_3) node _T_2555 = bits(io.in.d.bits.opcode, 2, 2) node _T_2556 = bits(io.in.d.bits.opcode, 1, 1) node _T_2557 = eq(_T_2556, UInt<1>(0h0)) node _T_2558 = and(_T_2555, _T_2557) node _T_2559 = and(_T_2554, _T_2558) when _T_2559 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2560 = dshr(inflight_2, io.in.d.bits.sink) node _T_2561 = bits(_T_2560, 0, 0) node _T_2562 = eq(_T_2561, UInt<1>(0h0)) node _T_2563 = asUInt(reset) node _T_2564 = eq(_T_2563, UInt<1>(0h0)) when _T_2564 : node _T_2565 = eq(_T_2562, UInt<1>(0h0)) when _T_2565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2562, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2566 = and(io.in.e.ready, io.in.e.valid) node _T_2567 = and(_T_2566, UInt<1>(0h1)) node _T_2568 = and(_T_2567, UInt<1>(0h1)) when _T_2568 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2569 = or(d_set, inflight_2) node _T_2570 = dshr(_T_2569, io.in.e.bits.sink) node _T_2571 = bits(_T_2570, 0, 0) node _T_2572 = asUInt(reset) node _T_2573 = eq(_T_2572, UInt<1>(0h0)) when _T_2573 : node _T_2574 = eq(_T_2571, UInt<1>(0h0)) when _T_2574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:134:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2571, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_86 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_87 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_42( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_7 = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T_7 = 1'h0; // @[Mux.scala:30:73] wire _source_ok_T_14 = 1'h0; // @[Parameters.scala:54:10] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = &io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_11 = source_ok_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_12 = _source_ok_T_11; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire _source_ok_T_13 = &io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_13; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [1:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_6 = &io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_4 = legal_source_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_4; // @[Parameters.scala:56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [1:0] _legal_source_T_8 = {2{_legal_source_WIRE_1}}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_9 = _legal_source_T_8; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_9; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [1:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = source_ok_uncommonBits_2 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_19 = _source_ok_T_18; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_19; // @[Parameters.scala:1138:31] wire _source_ok_T_20 = &io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_20; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_13 = _uncommonBits_T_13; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17; // @[Parameters.scala:52:{29,56}] wire _T_2479 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2479; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2479; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2553 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2553; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2550 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2550; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2550; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [3:0] inflight; // @[Monitor.scala:614:27] reg [15:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [31:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] a_set; // @[Monitor.scala:626:34] wire [3:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [15:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [31:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [31:0] _a_size_lookup_T_6 = {24'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [31:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = {2'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_22 = 4'h1 << _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_2405 = _T_2479 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2405 ? _a_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2405 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2405 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2405 ? _a_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2405 ? _a_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [3:0] d_clr; // @[Monitor.scala:664:34] wire [3:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [15:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [31:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2451 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_24 = {2'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_25 = 4'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2451 & ~d_release_ack ? _d_clr_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_2420 = _T_2553 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2420 ? _d_clr_T : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2420 ? _d_opcodes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2420 ? _d_sizes_clr_T_5[31:0] : 32'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [3:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [15:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [31:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [3:0] inflight_1; // @[Monitor.scala:726:35] reg [15:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [31:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_set; // @[Monitor.scala:738:34] wire [3:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [15:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [31:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = _c_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [31:0] _c_size_lookup_T_6 = {24'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [31:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_26 = {2'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_27 = 4'h1 << _GEN_26; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_2492 = _T_2550 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2492 ? _c_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2492 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2492 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2492 ? _c_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2492 ? _c_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [3:0] d_clr_1; // @[Monitor.scala:774:34] wire [3:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [15:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [31:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2523 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2523 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 4'h0; // @[OneHot.scala:58:35] wire _T_2505 = _T_2553 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2505 ? _d_clr_T_1 : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2505 ? _d_opcodes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2505 ? _d_sizes_clr_T_11[31:0] : 32'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [3:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [3:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [15:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [15:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [15:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [31:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [31:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2559 = _T_2553 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_28 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_28; // @[OneHot.scala:58:35] assign d_set = _T_2559 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2568 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_29 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_29; // @[OneHot.scala:58:35] assign e_clr = _T_2568 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_34 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_EntryData_34( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module L2MemHelperLatencyInjection_14 : input clock : Clock input reset : Reset output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} output io : { flip userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip latency_inject_cycles : UInt<64>, flip sfence : UInt<1>, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip status : { valid : UInt<1>, bits : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect auto.master_out, masterNodeOut wire request_input : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}} connect request_input, io.userif.req wire response_output : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}} connect io.userif.resp, response_output reg status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock when io.status.valid : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "[raw_block_reader] setting status.dprv to: %x compare %x\n", io.status.bits.dprv, UInt<2>(0h3)) : printf_1 connect status, io.status.bits inst tlb of DTLB_16 connect tlb.clock, clock connect tlb.reset, reset connect tlb.io.req.valid, request_input.valid connect tlb.io.req.bits.vaddr, request_input.bits.addr connect tlb.io.req.bits.size, request_input.bits.size connect tlb.io.req.bits.cmd, request_input.bits.cmd connect tlb.io.req.bits.passthrough, UInt<1>(0h0) node _tlb_ready_T = eq(tlb.io.resp.miss, UInt<1>(0h0)) node tlb_ready = and(tlb.io.req.ready, _tlb_ready_T) invalidate tlb.io.req.bits.prv invalidate tlb.io.req.bits.v invalidate tlb.io.sfence.bits.hv invalidate tlb.io.sfence.bits.hg connect tlb.io.ptw.customCSRs, io.ptw.customCSRs connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] connect tlb.io.ptw.gstatus, io.ptw.gstatus connect tlb.io.ptw.hstatus, io.ptw.hstatus connect tlb.io.ptw.status, io.ptw.status connect tlb.io.ptw.vsatp, io.ptw.vsatp connect tlb.io.ptw.hgatp, io.ptw.hgatp connect tlb.io.ptw.ptbr, io.ptw.ptbr connect tlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, tlb.io.ptw.req.bits connect io.ptw.req.valid, tlb.io.ptw.req.valid connect tlb.io.ptw.req.ready, io.ptw.req.ready connect tlb.io.ptw.status.uie, status.uie connect tlb.io.ptw.status.sie, status.sie connect tlb.io.ptw.status.hie, status.hie connect tlb.io.ptw.status.mie, status.mie connect tlb.io.ptw.status.upie, status.upie connect tlb.io.ptw.status.spie, status.spie connect tlb.io.ptw.status.ube, status.ube connect tlb.io.ptw.status.mpie, status.mpie connect tlb.io.ptw.status.spp, status.spp connect tlb.io.ptw.status.vs, status.vs connect tlb.io.ptw.status.mpp, status.mpp connect tlb.io.ptw.status.fs, status.fs connect tlb.io.ptw.status.xs, status.xs connect tlb.io.ptw.status.mprv, status.mprv connect tlb.io.ptw.status.sum, status.sum connect tlb.io.ptw.status.mxr, status.mxr connect tlb.io.ptw.status.tvm, status.tvm connect tlb.io.ptw.status.tw, status.tw connect tlb.io.ptw.status.tsr, status.tsr connect tlb.io.ptw.status.zero1, status.zero1 connect tlb.io.ptw.status.sd_rv32, status.sd_rv32 connect tlb.io.ptw.status.uxl, status.uxl connect tlb.io.ptw.status.sxl, status.sxl connect tlb.io.ptw.status.sbe, status.sbe connect tlb.io.ptw.status.mbe, status.mbe connect tlb.io.ptw.status.gva, status.gva connect tlb.io.ptw.status.mpv, status.mpv connect tlb.io.ptw.status.zero2, status.zero2 connect tlb.io.ptw.status.sd, status.sd connect tlb.io.ptw.status.v, status.v connect tlb.io.ptw.status.prv, status.prv connect tlb.io.ptw.status.dv, status.dv connect tlb.io.ptw.status.dprv, status.dprv connect tlb.io.ptw.status.isa, status.isa connect tlb.io.ptw.status.wfi, status.wfi connect tlb.io.ptw.status.cease, status.cease connect tlb.io.ptw.status.debug, status.debug connect tlb.io.sfence.valid, io.sfence connect tlb.io.sfence.bits.rs1, UInt<1>(0h0) connect tlb.io.sfence.bits.rs2, UInt<1>(0h0) connect tlb.io.sfence.bits.addr, UInt<1>(0h0) connect tlb.io.sfence.bits.asid, UInt<1>(0h0) connect tlb.io.kill, UInt<1>(0h0) inst outstanding_req_addr of Queue128_L2InternalTracking_10 connect outstanding_req_addr.clock, clock connect outstanding_req_addr.reset, reset inst tags_for_issue_Q of Queue64_UInt5_10 connect tags_for_issue_Q.clock, clock connect tags_for_issue_Q.reset, reset connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h0) invalidate tags_for_issue_Q.io.enq.bits regreset tags_init_reg : UInt<6>, clock, reset, UInt<6>(0h0) node _T_4 = neq(tags_init_reg, UInt<6>(0h20)) when _T_4 : connect tags_for_issue_Q.io.enq.bits, tags_init_reg connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) when tags_for_issue_Q.io.enq.ready : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "[raw_block_reader] tags_for_issue_Q init with value %d\n", tags_for_issue_Q.io.enq.bits) : printf_3 node _tags_init_reg_T = add(tags_init_reg, UInt<1>(0h1)) node _tags_init_reg_T_1 = tail(_tags_init_reg_T, 1) connect tags_init_reg, _tags_init_reg_T_1 node _addr_mask_check_T = dshl(UInt<64>(0h1), request_input.bits.size) node _addr_mask_check_T_1 = sub(_addr_mask_check_T, UInt<1>(0h1)) node addr_mask_check = tail(_addr_mask_check_T_1, 1) node _assertcheck_T = eq(request_input.valid, UInt<1>(0h0)) node _assertcheck_T_1 = and(request_input.bits.addr, addr_mask_check) node _assertcheck_T_2 = eq(_assertcheck_T_1, UInt<1>(0h0)) node _assertcheck_T_3 = or(_assertcheck_T, _assertcheck_T_2) reg assertcheck : UInt<1>, clock connect assertcheck, _assertcheck_T_3 node _T_9 = eq(assertcheck, UInt<1>(0h0)) when _T_9 : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: access addr must be aligned to write width\n") : printf_5 node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(assertcheck, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed: [raw_block_reader] L2IF: access addr must be aligned to write width\n\n at L2MemHelperLatencyInjection.scala:114 assert(assertcheck,\n") : printf_6 assert(clock, assertcheck, UInt<1>(0h1), "") : assert regreset global_memop_accepted : UInt<64>, clock, reset, UInt<64>(0h0) node _T_17 = and(io.userif.req.ready, io.userif.req.valid) when _T_17 : node _global_memop_accepted_T = add(global_memop_accepted, UInt<1>(0h1)) node _global_memop_accepted_T_1 = tail(_global_memop_accepted_T, 1) connect global_memop_accepted, _global_memop_accepted_T_1 regreset global_memop_sent : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_ackd : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_resp_to_user : UInt<64>, clock, reset, UInt<64>(0h0) node _io_userif_no_memops_inflight_T = eq(global_memop_accepted, global_memop_ackd) connect io.userif.no_memops_inflight, _io_userif_no_memops_inflight_T node _free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _free_outstanding_op_slots_T_1 = tail(_free_outstanding_op_slots_T, 1) node free_outstanding_op_slots = lt(_free_outstanding_op_slots_T_1, UInt<6>(0h20)) node _assert_free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _assert_free_outstanding_op_slots_T_1 = tail(_assert_free_outstanding_op_slots_T, 1) node assert_free_outstanding_op_slots = leq(_assert_free_outstanding_op_slots_T_1, UInt<6>(0h20)) node _T_18 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_18 : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_7 node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: Too many outstanding requests for tag count.\n") : printf_8 node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed: [raw_block_reader] L2IF: Too many outstanding requests for tag count.\n\n at L2MemHelperLatencyInjection.scala:136 assert(assert_free_outstanding_op_slots,\n") : printf_9 assert(clock, assert_free_outstanding_op_slots, UInt<1>(0h1), "") : assert_1 node _T_26 = and(request_input.ready, request_input.valid) when _T_26 : node _global_memop_sent_T = add(global_memop_sent, UInt<1>(0h1)) node _global_memop_sent_T_1 = tail(_global_memop_sent_T, 1) connect global_memop_sent, _global_memop_sent_T_1 regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0) node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1)) node _cur_cycle_T_1 = tail(_cur_cycle_T, 1) connect cur_cycle, _cur_cycle_T_1 inst request_latency_injection_q of LatencyInjectionQueue_28 connect request_latency_injection_q.clock, clock connect request_latency_injection_q.reset, reset connect request_latency_injection_q.io.latency_cycles, io.latency_inject_cycles invalidate request_latency_injection_q.io.enq.bits.corrupt invalidate request_latency_injection_q.io.enq.bits.data invalidate request_latency_injection_q.io.enq.bits.mask invalidate request_latency_injection_q.io.enq.bits.address invalidate request_latency_injection_q.io.enq.bits.source invalidate request_latency_injection_q.io.enq.bits.size invalidate request_latency_injection_q.io.enq.bits.param invalidate request_latency_injection_q.io.enq.bits.opcode node _T_27 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_27 : node _legal_T = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_1 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_2 = and(_legal_T, _legal_T_1) node _legal_T_3 = or(UInt<1>(0h0), _legal_T_2) node _legal_T_4 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_5 = cvt(_legal_T_4) node _legal_T_6 = and(_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _legal_T_7 = asSInt(_legal_T_6) node _legal_T_8 = eq(_legal_T_7, asSInt(UInt<1>(0h0))) node _legal_T_9 = and(_legal_T_3, _legal_T_8) node _legal_T_10 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_11 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_12 = and(_legal_T_10, _legal_T_11) node _legal_T_13 = or(UInt<1>(0h0), _legal_T_12) node _legal_T_14 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_15 = cvt(_legal_T_14) node _legal_T_16 = and(_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _legal_T_17 = asSInt(_legal_T_16) node _legal_T_18 = eq(_legal_T_17, asSInt(UInt<1>(0h0))) node _legal_T_19 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_20 = cvt(_legal_T_19) node _legal_T_21 = and(_legal_T_20, asSInt(UInt<33>(0h98013000))) node _legal_T_22 = asSInt(_legal_T_21) node _legal_T_23 = eq(_legal_T_22, asSInt(UInt<1>(0h0))) node _legal_T_24 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_25 = cvt(_legal_T_24) node _legal_T_26 = and(_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _legal_T_27 = asSInt(_legal_T_26) node _legal_T_28 = eq(_legal_T_27, asSInt(UInt<1>(0h0))) node _legal_T_29 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_30 = cvt(_legal_T_29) node _legal_T_31 = and(_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _legal_T_32 = asSInt(_legal_T_31) node _legal_T_33 = eq(_legal_T_32, asSInt(UInt<1>(0h0))) node _legal_T_34 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_35 = cvt(_legal_T_34) node _legal_T_36 = and(_legal_T_35, asSInt(UInt<33>(0h98000000))) node _legal_T_37 = asSInt(_legal_T_36) node _legal_T_38 = eq(_legal_T_37, asSInt(UInt<1>(0h0))) node _legal_T_39 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_40 = cvt(_legal_T_39) node _legal_T_41 = and(_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _legal_T_42 = asSInt(_legal_T_41) node _legal_T_43 = eq(_legal_T_42, asSInt(UInt<1>(0h0))) node _legal_T_44 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_45 = cvt(_legal_T_44) node _legal_T_46 = and(_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _legal_T_47 = asSInt(_legal_T_46) node _legal_T_48 = eq(_legal_T_47, asSInt(UInt<1>(0h0))) node _legal_T_49 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_50 = cvt(_legal_T_49) node _legal_T_51 = and(_legal_T_50, asSInt(UInt<33>(0h90000000))) node _legal_T_52 = asSInt(_legal_T_51) node _legal_T_53 = eq(_legal_T_52, asSInt(UInt<1>(0h0))) node _legal_T_54 = or(_legal_T_18, _legal_T_23) node _legal_T_55 = or(_legal_T_54, _legal_T_28) node _legal_T_56 = or(_legal_T_55, _legal_T_33) node _legal_T_57 = or(_legal_T_56, _legal_T_38) node _legal_T_58 = or(_legal_T_57, _legal_T_43) node _legal_T_59 = or(_legal_T_58, _legal_T_48) node _legal_T_60 = or(_legal_T_59, _legal_T_53) node _legal_T_61 = and(_legal_T_13, _legal_T_60) node _legal_T_62 = or(UInt<1>(0h0), _legal_T_9) node legal = or(_legal_T_62, _legal_T_61) wire bundle : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle.opcode, UInt<3>(0h4) connect bundle.param, UInt<1>(0h0) connect bundle.size, request_input.bits.size connect bundle.source, tags_for_issue_Q.io.deq.bits connect bundle.address, tlb.io.resp.paddr node _a_mask_sizeOH_T = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T = pad(_a_mask_sizeOH_T, 3) node a_mask_sizeOH_shiftAmount = bits(_a_mask_sizeOH_shiftAmount_T, 2, 0) node _a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount) node _a_mask_sizeOH_T_2 = bits(_a_mask_sizeOH_T_1, 4, 0) node a_mask_sizeOH = or(_a_mask_sizeOH_T_2, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size = bits(a_mask_sizeOH, 4, 4) node a_mask_sub_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_0_2) node a_mask_sub_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit) node _a_mask_sub_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_1_2) node a_mask_sub_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_size = bits(a_mask_sizeOH, 3, 3) node a_mask_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_0_2) node a_mask_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_1_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_1_2) node a_mask_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_2_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_2_2) node a_mask_sub_sub_sub_2_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_3_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_3_2) node a_mask_sub_sub_sub_3_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_3) node a_mask_sub_sub_size = bits(a_mask_sizeOH, 2, 2) node a_mask_sub_sub_bit = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit = eq(a_mask_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_0_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T = and(a_mask_sub_sub_size, a_mask_sub_sub_0_2) node a_mask_sub_sub_0_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T) node a_mask_sub_sub_1_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_1 = and(a_mask_sub_sub_size, a_mask_sub_sub_1_2) node a_mask_sub_sub_1_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T_1) node a_mask_sub_sub_2_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_2 = and(a_mask_sub_sub_size, a_mask_sub_sub_2_2) node a_mask_sub_sub_2_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_2) node a_mask_sub_sub_3_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_3 = and(a_mask_sub_sub_size, a_mask_sub_sub_3_2) node a_mask_sub_sub_3_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_3) node a_mask_sub_sub_4_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_4 = and(a_mask_sub_sub_size, a_mask_sub_sub_4_2) node a_mask_sub_sub_4_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_4) node a_mask_sub_sub_5_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_5 = and(a_mask_sub_sub_size, a_mask_sub_sub_5_2) node a_mask_sub_sub_5_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_5) node a_mask_sub_sub_6_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_6 = and(a_mask_sub_sub_size, a_mask_sub_sub_6_2) node a_mask_sub_sub_6_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_6) node a_mask_sub_sub_7_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_7 = and(a_mask_sub_sub_size, a_mask_sub_sub_7_2) node a_mask_sub_sub_7_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_7) node a_mask_sub_size = bits(a_mask_sizeOH, 1, 1) node a_mask_sub_bit = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit = eq(a_mask_sub_bit, UInt<1>(0h0)) node a_mask_sub_0_2 = and(a_mask_sub_sub_0_2, a_mask_sub_nbit) node _a_mask_sub_acc_T = and(a_mask_sub_size, a_mask_sub_0_2) node a_mask_sub_0_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T) node a_mask_sub_1_2 = and(a_mask_sub_sub_0_2, a_mask_sub_bit) node _a_mask_sub_acc_T_1 = and(a_mask_sub_size, a_mask_sub_1_2) node a_mask_sub_1_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T_1) node a_mask_sub_2_2 = and(a_mask_sub_sub_1_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_2 = and(a_mask_sub_size, a_mask_sub_2_2) node a_mask_sub_2_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_2) node a_mask_sub_3_2 = and(a_mask_sub_sub_1_2, a_mask_sub_bit) node _a_mask_sub_acc_T_3 = and(a_mask_sub_size, a_mask_sub_3_2) node a_mask_sub_3_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_3) node a_mask_sub_4_2 = and(a_mask_sub_sub_2_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_4 = and(a_mask_sub_size, a_mask_sub_4_2) node a_mask_sub_4_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_4) node a_mask_sub_5_2 = and(a_mask_sub_sub_2_2, a_mask_sub_bit) node _a_mask_sub_acc_T_5 = and(a_mask_sub_size, a_mask_sub_5_2) node a_mask_sub_5_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_5) node a_mask_sub_6_2 = and(a_mask_sub_sub_3_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_6 = and(a_mask_sub_size, a_mask_sub_6_2) node a_mask_sub_6_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_6) node a_mask_sub_7_2 = and(a_mask_sub_sub_3_2, a_mask_sub_bit) node _a_mask_sub_acc_T_7 = and(a_mask_sub_size, a_mask_sub_7_2) node a_mask_sub_7_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_7) node a_mask_sub_8_2 = and(a_mask_sub_sub_4_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_8 = and(a_mask_sub_size, a_mask_sub_8_2) node a_mask_sub_8_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_8) node a_mask_sub_9_2 = and(a_mask_sub_sub_4_2, a_mask_sub_bit) node _a_mask_sub_acc_T_9 = and(a_mask_sub_size, a_mask_sub_9_2) node a_mask_sub_9_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_9) node a_mask_sub_10_2 = and(a_mask_sub_sub_5_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_10 = and(a_mask_sub_size, a_mask_sub_10_2) node a_mask_sub_10_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_10) node a_mask_sub_11_2 = and(a_mask_sub_sub_5_2, a_mask_sub_bit) node _a_mask_sub_acc_T_11 = and(a_mask_sub_size, a_mask_sub_11_2) node a_mask_sub_11_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_11) node a_mask_sub_12_2 = and(a_mask_sub_sub_6_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_12 = and(a_mask_sub_size, a_mask_sub_12_2) node a_mask_sub_12_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_12) node a_mask_sub_13_2 = and(a_mask_sub_sub_6_2, a_mask_sub_bit) node _a_mask_sub_acc_T_13 = and(a_mask_sub_size, a_mask_sub_13_2) node a_mask_sub_13_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_13) node a_mask_sub_14_2 = and(a_mask_sub_sub_7_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_14 = and(a_mask_sub_size, a_mask_sub_14_2) node a_mask_sub_14_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_14) node a_mask_sub_15_2 = and(a_mask_sub_sub_7_2, a_mask_sub_bit) node _a_mask_sub_acc_T_15 = and(a_mask_sub_size, a_mask_sub_15_2) node a_mask_sub_15_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_15) node a_mask_size = bits(a_mask_sizeOH, 0, 0) node a_mask_bit = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit = eq(a_mask_bit, UInt<1>(0h0)) node a_mask_eq = and(a_mask_sub_0_2, a_mask_nbit) node _a_mask_acc_T = and(a_mask_size, a_mask_eq) node a_mask_acc = or(a_mask_sub_0_1, _a_mask_acc_T) node a_mask_eq_1 = and(a_mask_sub_0_2, a_mask_bit) node _a_mask_acc_T_1 = and(a_mask_size, a_mask_eq_1) node a_mask_acc_1 = or(a_mask_sub_0_1, _a_mask_acc_T_1) node a_mask_eq_2 = and(a_mask_sub_1_2, a_mask_nbit) node _a_mask_acc_T_2 = and(a_mask_size, a_mask_eq_2) node a_mask_acc_2 = or(a_mask_sub_1_1, _a_mask_acc_T_2) node a_mask_eq_3 = and(a_mask_sub_1_2, a_mask_bit) node _a_mask_acc_T_3 = and(a_mask_size, a_mask_eq_3) node a_mask_acc_3 = or(a_mask_sub_1_1, _a_mask_acc_T_3) node a_mask_eq_4 = and(a_mask_sub_2_2, a_mask_nbit) node _a_mask_acc_T_4 = and(a_mask_size, a_mask_eq_4) node a_mask_acc_4 = or(a_mask_sub_2_1, _a_mask_acc_T_4) node a_mask_eq_5 = and(a_mask_sub_2_2, a_mask_bit) node _a_mask_acc_T_5 = and(a_mask_size, a_mask_eq_5) node a_mask_acc_5 = or(a_mask_sub_2_1, _a_mask_acc_T_5) node a_mask_eq_6 = and(a_mask_sub_3_2, a_mask_nbit) node _a_mask_acc_T_6 = and(a_mask_size, a_mask_eq_6) node a_mask_acc_6 = or(a_mask_sub_3_1, _a_mask_acc_T_6) node a_mask_eq_7 = and(a_mask_sub_3_2, a_mask_bit) node _a_mask_acc_T_7 = and(a_mask_size, a_mask_eq_7) node a_mask_acc_7 = or(a_mask_sub_3_1, _a_mask_acc_T_7) node a_mask_eq_8 = and(a_mask_sub_4_2, a_mask_nbit) node _a_mask_acc_T_8 = and(a_mask_size, a_mask_eq_8) node a_mask_acc_8 = or(a_mask_sub_4_1, _a_mask_acc_T_8) node a_mask_eq_9 = and(a_mask_sub_4_2, a_mask_bit) node _a_mask_acc_T_9 = and(a_mask_size, a_mask_eq_9) node a_mask_acc_9 = or(a_mask_sub_4_1, _a_mask_acc_T_9) node a_mask_eq_10 = and(a_mask_sub_5_2, a_mask_nbit) node _a_mask_acc_T_10 = and(a_mask_size, a_mask_eq_10) node a_mask_acc_10 = or(a_mask_sub_5_1, _a_mask_acc_T_10) node a_mask_eq_11 = and(a_mask_sub_5_2, a_mask_bit) node _a_mask_acc_T_11 = and(a_mask_size, a_mask_eq_11) node a_mask_acc_11 = or(a_mask_sub_5_1, _a_mask_acc_T_11) node a_mask_eq_12 = and(a_mask_sub_6_2, a_mask_nbit) node _a_mask_acc_T_12 = and(a_mask_size, a_mask_eq_12) node a_mask_acc_12 = or(a_mask_sub_6_1, _a_mask_acc_T_12) node a_mask_eq_13 = and(a_mask_sub_6_2, a_mask_bit) node _a_mask_acc_T_13 = and(a_mask_size, a_mask_eq_13) node a_mask_acc_13 = or(a_mask_sub_6_1, _a_mask_acc_T_13) node a_mask_eq_14 = and(a_mask_sub_7_2, a_mask_nbit) node _a_mask_acc_T_14 = and(a_mask_size, a_mask_eq_14) node a_mask_acc_14 = or(a_mask_sub_7_1, _a_mask_acc_T_14) node a_mask_eq_15 = and(a_mask_sub_7_2, a_mask_bit) node _a_mask_acc_T_15 = and(a_mask_size, a_mask_eq_15) node a_mask_acc_15 = or(a_mask_sub_7_1, _a_mask_acc_T_15) node a_mask_eq_16 = and(a_mask_sub_8_2, a_mask_nbit) node _a_mask_acc_T_16 = and(a_mask_size, a_mask_eq_16) node a_mask_acc_16 = or(a_mask_sub_8_1, _a_mask_acc_T_16) node a_mask_eq_17 = and(a_mask_sub_8_2, a_mask_bit) node _a_mask_acc_T_17 = and(a_mask_size, a_mask_eq_17) node a_mask_acc_17 = or(a_mask_sub_8_1, _a_mask_acc_T_17) node a_mask_eq_18 = and(a_mask_sub_9_2, a_mask_nbit) node _a_mask_acc_T_18 = and(a_mask_size, a_mask_eq_18) node a_mask_acc_18 = or(a_mask_sub_9_1, _a_mask_acc_T_18) node a_mask_eq_19 = and(a_mask_sub_9_2, a_mask_bit) node _a_mask_acc_T_19 = and(a_mask_size, a_mask_eq_19) node a_mask_acc_19 = or(a_mask_sub_9_1, _a_mask_acc_T_19) node a_mask_eq_20 = and(a_mask_sub_10_2, a_mask_nbit) node _a_mask_acc_T_20 = and(a_mask_size, a_mask_eq_20) node a_mask_acc_20 = or(a_mask_sub_10_1, _a_mask_acc_T_20) node a_mask_eq_21 = and(a_mask_sub_10_2, a_mask_bit) node _a_mask_acc_T_21 = and(a_mask_size, a_mask_eq_21) node a_mask_acc_21 = or(a_mask_sub_10_1, _a_mask_acc_T_21) node a_mask_eq_22 = and(a_mask_sub_11_2, a_mask_nbit) node _a_mask_acc_T_22 = and(a_mask_size, a_mask_eq_22) node a_mask_acc_22 = or(a_mask_sub_11_1, _a_mask_acc_T_22) node a_mask_eq_23 = and(a_mask_sub_11_2, a_mask_bit) node _a_mask_acc_T_23 = and(a_mask_size, a_mask_eq_23) node a_mask_acc_23 = or(a_mask_sub_11_1, _a_mask_acc_T_23) node a_mask_eq_24 = and(a_mask_sub_12_2, a_mask_nbit) node _a_mask_acc_T_24 = and(a_mask_size, a_mask_eq_24) node a_mask_acc_24 = or(a_mask_sub_12_1, _a_mask_acc_T_24) node a_mask_eq_25 = and(a_mask_sub_12_2, a_mask_bit) node _a_mask_acc_T_25 = and(a_mask_size, a_mask_eq_25) node a_mask_acc_25 = or(a_mask_sub_12_1, _a_mask_acc_T_25) node a_mask_eq_26 = and(a_mask_sub_13_2, a_mask_nbit) node _a_mask_acc_T_26 = and(a_mask_size, a_mask_eq_26) node a_mask_acc_26 = or(a_mask_sub_13_1, _a_mask_acc_T_26) node a_mask_eq_27 = and(a_mask_sub_13_2, a_mask_bit) node _a_mask_acc_T_27 = and(a_mask_size, a_mask_eq_27) node a_mask_acc_27 = or(a_mask_sub_13_1, _a_mask_acc_T_27) node a_mask_eq_28 = and(a_mask_sub_14_2, a_mask_nbit) node _a_mask_acc_T_28 = and(a_mask_size, a_mask_eq_28) node a_mask_acc_28 = or(a_mask_sub_14_1, _a_mask_acc_T_28) node a_mask_eq_29 = and(a_mask_sub_14_2, a_mask_bit) node _a_mask_acc_T_29 = and(a_mask_size, a_mask_eq_29) node a_mask_acc_29 = or(a_mask_sub_14_1, _a_mask_acc_T_29) node a_mask_eq_30 = and(a_mask_sub_15_2, a_mask_nbit) node _a_mask_acc_T_30 = and(a_mask_size, a_mask_eq_30) node a_mask_acc_30 = or(a_mask_sub_15_1, _a_mask_acc_T_30) node a_mask_eq_31 = and(a_mask_sub_15_2, a_mask_bit) node _a_mask_acc_T_31 = and(a_mask_size, a_mask_eq_31) node a_mask_acc_31 = or(a_mask_sub_15_1, _a_mask_acc_T_31) node a_mask_lo_lo_lo_lo = cat(a_mask_acc_1, a_mask_acc) node a_mask_lo_lo_lo_hi = cat(a_mask_acc_3, a_mask_acc_2) node a_mask_lo_lo_lo = cat(a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo) node a_mask_lo_lo_hi_lo = cat(a_mask_acc_5, a_mask_acc_4) node a_mask_lo_lo_hi_hi = cat(a_mask_acc_7, a_mask_acc_6) node a_mask_lo_lo_hi = cat(a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo) node a_mask_lo_lo = cat(a_mask_lo_lo_hi, a_mask_lo_lo_lo) node a_mask_lo_hi_lo_lo = cat(a_mask_acc_9, a_mask_acc_8) node a_mask_lo_hi_lo_hi = cat(a_mask_acc_11, a_mask_acc_10) node a_mask_lo_hi_lo = cat(a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo) node a_mask_lo_hi_hi_lo = cat(a_mask_acc_13, a_mask_acc_12) node a_mask_lo_hi_hi_hi = cat(a_mask_acc_15, a_mask_acc_14) node a_mask_lo_hi_hi = cat(a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo) node a_mask_lo_hi = cat(a_mask_lo_hi_hi, a_mask_lo_hi_lo) node a_mask_lo = cat(a_mask_lo_hi, a_mask_lo_lo) node a_mask_hi_lo_lo_lo = cat(a_mask_acc_17, a_mask_acc_16) node a_mask_hi_lo_lo_hi = cat(a_mask_acc_19, a_mask_acc_18) node a_mask_hi_lo_lo = cat(a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo) node a_mask_hi_lo_hi_lo = cat(a_mask_acc_21, a_mask_acc_20) node a_mask_hi_lo_hi_hi = cat(a_mask_acc_23, a_mask_acc_22) node a_mask_hi_lo_hi = cat(a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo) node a_mask_hi_lo = cat(a_mask_hi_lo_hi, a_mask_hi_lo_lo) node a_mask_hi_hi_lo_lo = cat(a_mask_acc_25, a_mask_acc_24) node a_mask_hi_hi_lo_hi = cat(a_mask_acc_27, a_mask_acc_26) node a_mask_hi_hi_lo = cat(a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo) node a_mask_hi_hi_hi_lo = cat(a_mask_acc_29, a_mask_acc_28) node a_mask_hi_hi_hi_hi = cat(a_mask_acc_31, a_mask_acc_30) node a_mask_hi_hi_hi = cat(a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo) node a_mask_hi_hi = cat(a_mask_hi_hi_hi, a_mask_hi_hi_lo) node a_mask_hi = cat(a_mask_hi_hi, a_mask_hi_lo) node _a_mask_T = cat(a_mask_hi, a_mask_lo) connect bundle.mask, _a_mask_T invalidate bundle.data connect bundle.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle.data connect request_latency_injection_q.io.enq.bits.mask, bundle.mask connect request_latency_injection_q.io.enq.bits.address, bundle.address connect request_latency_injection_q.io.enq.bits.source, bundle.source connect request_latency_injection_q.io.enq.bits.size, bundle.size connect request_latency_injection_q.io.enq.bits.param, bundle.param connect request_latency_injection_q.io.enq.bits.opcode, bundle.opcode else : node _T_28 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_28 : node _T_29 = bits(request_input.bits.addr, 4, 0) node _T_30 = shl(_T_29, 3) node _T_31 = dshl(request_input.bits.data, _T_30) node _legal_T_63 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_64 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_65 = and(_legal_T_63, _legal_T_64) node _legal_T_66 = or(UInt<1>(0h0), _legal_T_65) node _legal_T_67 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_68 = cvt(_legal_T_67) node _legal_T_69 = and(_legal_T_68, asSInt(UInt<33>(0h9a113000))) node _legal_T_70 = asSInt(_legal_T_69) node _legal_T_71 = eq(_legal_T_70, asSInt(UInt<1>(0h0))) node _legal_T_72 = and(_legal_T_66, _legal_T_71) node _legal_T_73 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_74 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_75 = and(_legal_T_73, _legal_T_74) node _legal_T_76 = or(UInt<1>(0h0), _legal_T_75) node _legal_T_77 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_78 = cvt(_legal_T_77) node _legal_T_79 = and(_legal_T_78, asSInt(UInt<33>(0h9a112000))) node _legal_T_80 = asSInt(_legal_T_79) node _legal_T_81 = eq(_legal_T_80, asSInt(UInt<1>(0h0))) node _legal_T_82 = xor(tlb.io.resp.paddr, UInt<21>(0h100000)) node _legal_T_83 = cvt(_legal_T_82) node _legal_T_84 = and(_legal_T_83, asSInt(UInt<33>(0h9a103000))) node _legal_T_85 = asSInt(_legal_T_84) node _legal_T_86 = eq(_legal_T_85, asSInt(UInt<1>(0h0))) node _legal_T_87 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_88 = cvt(_legal_T_87) node _legal_T_89 = and(_legal_T_88, asSInt(UInt<33>(0h9a110000))) node _legal_T_90 = asSInt(_legal_T_89) node _legal_T_91 = eq(_legal_T_90, asSInt(UInt<1>(0h0))) node _legal_T_92 = xor(tlb.io.resp.paddr, UInt<26>(0h2010000)) node _legal_T_93 = cvt(_legal_T_92) node _legal_T_94 = and(_legal_T_93, asSInt(UInt<33>(0h9a113000))) node _legal_T_95 = asSInt(_legal_T_94) node _legal_T_96 = eq(_legal_T_95, asSInt(UInt<1>(0h0))) node _legal_T_97 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_98 = cvt(_legal_T_97) node _legal_T_99 = and(_legal_T_98, asSInt(UInt<33>(0h98000000))) node _legal_T_100 = asSInt(_legal_T_99) node _legal_T_101 = eq(_legal_T_100, asSInt(UInt<1>(0h0))) node _legal_T_102 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_103 = cvt(_legal_T_102) node _legal_T_104 = and(_legal_T_103, asSInt(UInt<33>(0h9a110000))) node _legal_T_105 = asSInt(_legal_T_104) node _legal_T_106 = eq(_legal_T_105, asSInt(UInt<1>(0h0))) node _legal_T_107 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_108 = cvt(_legal_T_107) node _legal_T_109 = and(_legal_T_108, asSInt(UInt<33>(0h9a113000))) node _legal_T_110 = asSInt(_legal_T_109) node _legal_T_111 = eq(_legal_T_110, asSInt(UInt<1>(0h0))) node _legal_T_112 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_113 = cvt(_legal_T_112) node _legal_T_114 = and(_legal_T_113, asSInt(UInt<33>(0h90000000))) node _legal_T_115 = asSInt(_legal_T_114) node _legal_T_116 = eq(_legal_T_115, asSInt(UInt<1>(0h0))) node _legal_T_117 = or(_legal_T_81, _legal_T_86) node _legal_T_118 = or(_legal_T_117, _legal_T_91) node _legal_T_119 = or(_legal_T_118, _legal_T_96) node _legal_T_120 = or(_legal_T_119, _legal_T_101) node _legal_T_121 = or(_legal_T_120, _legal_T_106) node _legal_T_122 = or(_legal_T_121, _legal_T_111) node _legal_T_123 = or(_legal_T_122, _legal_T_116) node _legal_T_124 = and(_legal_T_76, _legal_T_123) node _legal_T_125 = or(UInt<1>(0h0), UInt<1>(0h0)) node _legal_T_126 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_127 = cvt(_legal_T_126) node _legal_T_128 = and(_legal_T_127, asSInt(UInt<33>(0h9a110000))) node _legal_T_129 = asSInt(_legal_T_128) node _legal_T_130 = eq(_legal_T_129, asSInt(UInt<1>(0h0))) node _legal_T_131 = and(_legal_T_125, _legal_T_130) node _legal_T_132 = or(UInt<1>(0h0), _legal_T_72) node _legal_T_133 = or(_legal_T_132, _legal_T_124) node legal_1 = or(_legal_T_133, _legal_T_131) wire bundle_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle_1.opcode, UInt<1>(0h0) connect bundle_1.param, UInt<1>(0h0) connect bundle_1.size, request_input.bits.size connect bundle_1.source, tags_for_issue_Q.io.deq.bits connect bundle_1.address, tlb.io.resp.paddr node _a_mask_sizeOH_T_3 = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T_1 = pad(_a_mask_sizeOH_T_3, 3) node a_mask_sizeOH_shiftAmount_1 = bits(_a_mask_sizeOH_shiftAmount_T_1, 2, 0) node _a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount_1) node _a_mask_sizeOH_T_5 = bits(_a_mask_sizeOH_T_4, 4, 0) node a_mask_sizeOH_1 = or(_a_mask_sizeOH_T_5, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 4, 4) node a_mask_sub_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_3) node a_mask_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 3, 3) node a_mask_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_4 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_4) node a_mask_sub_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_5 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_5) node a_mask_sub_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_6 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_2_2_1) node a_mask_sub_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_6) node a_mask_sub_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_7 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_3_2_1) node a_mask_sub_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_7) node a_mask_sub_sub_size_1 = bits(a_mask_sizeOH_1, 2, 2) node a_mask_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit_1 = eq(a_mask_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_8 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_0_2_1) node a_mask_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_8) node a_mask_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_9 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_1_2_1) node a_mask_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_9) node a_mask_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_10 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_2_2_1) node a_mask_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_10) node a_mask_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_11 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_3_2_1) node a_mask_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_11) node a_mask_sub_sub_4_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_12 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_4_2_1) node a_mask_sub_sub_4_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_12) node a_mask_sub_sub_5_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_13 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_5_2_1) node a_mask_sub_sub_5_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_13) node a_mask_sub_sub_6_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_14 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_6_2_1) node a_mask_sub_sub_6_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_14) node a_mask_sub_sub_7_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_15 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_7_2_1) node a_mask_sub_sub_7_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_15) node a_mask_sub_size_1 = bits(a_mask_sizeOH_1, 1, 1) node a_mask_sub_bit_1 = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit_1 = eq(a_mask_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_0_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_16 = and(a_mask_sub_size_1, a_mask_sub_0_2_1) node a_mask_sub_0_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_16) node a_mask_sub_1_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_17 = and(a_mask_sub_size_1, a_mask_sub_1_2_1) node a_mask_sub_1_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_17) node a_mask_sub_2_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_18 = and(a_mask_sub_size_1, a_mask_sub_2_2_1) node a_mask_sub_2_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_18) node a_mask_sub_3_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_19 = and(a_mask_sub_size_1, a_mask_sub_3_2_1) node a_mask_sub_3_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_19) node a_mask_sub_4_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_20 = and(a_mask_sub_size_1, a_mask_sub_4_2_1) node a_mask_sub_4_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_20) node a_mask_sub_5_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_21 = and(a_mask_sub_size_1, a_mask_sub_5_2_1) node a_mask_sub_5_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_21) node a_mask_sub_6_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_22 = and(a_mask_sub_size_1, a_mask_sub_6_2_1) node a_mask_sub_6_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_22) node a_mask_sub_7_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_23 = and(a_mask_sub_size_1, a_mask_sub_7_2_1) node a_mask_sub_7_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_23) node a_mask_sub_8_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_24 = and(a_mask_sub_size_1, a_mask_sub_8_2_1) node a_mask_sub_8_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_24) node a_mask_sub_9_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_25 = and(a_mask_sub_size_1, a_mask_sub_9_2_1) node a_mask_sub_9_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_25) node a_mask_sub_10_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_26 = and(a_mask_sub_size_1, a_mask_sub_10_2_1) node a_mask_sub_10_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_26) node a_mask_sub_11_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_27 = and(a_mask_sub_size_1, a_mask_sub_11_2_1) node a_mask_sub_11_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_27) node a_mask_sub_12_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_28 = and(a_mask_sub_size_1, a_mask_sub_12_2_1) node a_mask_sub_12_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_28) node a_mask_sub_13_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_29 = and(a_mask_sub_size_1, a_mask_sub_13_2_1) node a_mask_sub_13_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_29) node a_mask_sub_14_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_30 = and(a_mask_sub_size_1, a_mask_sub_14_2_1) node a_mask_sub_14_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_30) node a_mask_sub_15_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_31 = and(a_mask_sub_size_1, a_mask_sub_15_2_1) node a_mask_sub_15_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_31) node a_mask_size_1 = bits(a_mask_sizeOH_1, 0, 0) node a_mask_bit_1 = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit_1 = eq(a_mask_bit_1, UInt<1>(0h0)) node a_mask_eq_32 = and(a_mask_sub_0_2_1, a_mask_nbit_1) node _a_mask_acc_T_32 = and(a_mask_size_1, a_mask_eq_32) node a_mask_acc_32 = or(a_mask_sub_0_1_1, _a_mask_acc_T_32) node a_mask_eq_33 = and(a_mask_sub_0_2_1, a_mask_bit_1) node _a_mask_acc_T_33 = and(a_mask_size_1, a_mask_eq_33) node a_mask_acc_33 = or(a_mask_sub_0_1_1, _a_mask_acc_T_33) node a_mask_eq_34 = and(a_mask_sub_1_2_1, a_mask_nbit_1) node _a_mask_acc_T_34 = and(a_mask_size_1, a_mask_eq_34) node a_mask_acc_34 = or(a_mask_sub_1_1_1, _a_mask_acc_T_34) node a_mask_eq_35 = and(a_mask_sub_1_2_1, a_mask_bit_1) node _a_mask_acc_T_35 = and(a_mask_size_1, a_mask_eq_35) node a_mask_acc_35 = or(a_mask_sub_1_1_1, _a_mask_acc_T_35) node a_mask_eq_36 = and(a_mask_sub_2_2_1, a_mask_nbit_1) node _a_mask_acc_T_36 = and(a_mask_size_1, a_mask_eq_36) node a_mask_acc_36 = or(a_mask_sub_2_1_1, _a_mask_acc_T_36) node a_mask_eq_37 = and(a_mask_sub_2_2_1, a_mask_bit_1) node _a_mask_acc_T_37 = and(a_mask_size_1, a_mask_eq_37) node a_mask_acc_37 = or(a_mask_sub_2_1_1, _a_mask_acc_T_37) node a_mask_eq_38 = and(a_mask_sub_3_2_1, a_mask_nbit_1) node _a_mask_acc_T_38 = and(a_mask_size_1, a_mask_eq_38) node a_mask_acc_38 = or(a_mask_sub_3_1_1, _a_mask_acc_T_38) node a_mask_eq_39 = and(a_mask_sub_3_2_1, a_mask_bit_1) node _a_mask_acc_T_39 = and(a_mask_size_1, a_mask_eq_39) node a_mask_acc_39 = or(a_mask_sub_3_1_1, _a_mask_acc_T_39) node a_mask_eq_40 = and(a_mask_sub_4_2_1, a_mask_nbit_1) node _a_mask_acc_T_40 = and(a_mask_size_1, a_mask_eq_40) node a_mask_acc_40 = or(a_mask_sub_4_1_1, _a_mask_acc_T_40) node a_mask_eq_41 = and(a_mask_sub_4_2_1, a_mask_bit_1) node _a_mask_acc_T_41 = and(a_mask_size_1, a_mask_eq_41) node a_mask_acc_41 = or(a_mask_sub_4_1_1, _a_mask_acc_T_41) node a_mask_eq_42 = and(a_mask_sub_5_2_1, a_mask_nbit_1) node _a_mask_acc_T_42 = and(a_mask_size_1, a_mask_eq_42) node a_mask_acc_42 = or(a_mask_sub_5_1_1, _a_mask_acc_T_42) node a_mask_eq_43 = and(a_mask_sub_5_2_1, a_mask_bit_1) node _a_mask_acc_T_43 = and(a_mask_size_1, a_mask_eq_43) node a_mask_acc_43 = or(a_mask_sub_5_1_1, _a_mask_acc_T_43) node a_mask_eq_44 = and(a_mask_sub_6_2_1, a_mask_nbit_1) node _a_mask_acc_T_44 = and(a_mask_size_1, a_mask_eq_44) node a_mask_acc_44 = or(a_mask_sub_6_1_1, _a_mask_acc_T_44) node a_mask_eq_45 = and(a_mask_sub_6_2_1, a_mask_bit_1) node _a_mask_acc_T_45 = and(a_mask_size_1, a_mask_eq_45) node a_mask_acc_45 = or(a_mask_sub_6_1_1, _a_mask_acc_T_45) node a_mask_eq_46 = and(a_mask_sub_7_2_1, a_mask_nbit_1) node _a_mask_acc_T_46 = and(a_mask_size_1, a_mask_eq_46) node a_mask_acc_46 = or(a_mask_sub_7_1_1, _a_mask_acc_T_46) node a_mask_eq_47 = and(a_mask_sub_7_2_1, a_mask_bit_1) node _a_mask_acc_T_47 = and(a_mask_size_1, a_mask_eq_47) node a_mask_acc_47 = or(a_mask_sub_7_1_1, _a_mask_acc_T_47) node a_mask_eq_48 = and(a_mask_sub_8_2_1, a_mask_nbit_1) node _a_mask_acc_T_48 = and(a_mask_size_1, a_mask_eq_48) node a_mask_acc_48 = or(a_mask_sub_8_1_1, _a_mask_acc_T_48) node a_mask_eq_49 = and(a_mask_sub_8_2_1, a_mask_bit_1) node _a_mask_acc_T_49 = and(a_mask_size_1, a_mask_eq_49) node a_mask_acc_49 = or(a_mask_sub_8_1_1, _a_mask_acc_T_49) node a_mask_eq_50 = and(a_mask_sub_9_2_1, a_mask_nbit_1) node _a_mask_acc_T_50 = and(a_mask_size_1, a_mask_eq_50) node a_mask_acc_50 = or(a_mask_sub_9_1_1, _a_mask_acc_T_50) node a_mask_eq_51 = and(a_mask_sub_9_2_1, a_mask_bit_1) node _a_mask_acc_T_51 = and(a_mask_size_1, a_mask_eq_51) node a_mask_acc_51 = or(a_mask_sub_9_1_1, _a_mask_acc_T_51) node a_mask_eq_52 = and(a_mask_sub_10_2_1, a_mask_nbit_1) node _a_mask_acc_T_52 = and(a_mask_size_1, a_mask_eq_52) node a_mask_acc_52 = or(a_mask_sub_10_1_1, _a_mask_acc_T_52) node a_mask_eq_53 = and(a_mask_sub_10_2_1, a_mask_bit_1) node _a_mask_acc_T_53 = and(a_mask_size_1, a_mask_eq_53) node a_mask_acc_53 = or(a_mask_sub_10_1_1, _a_mask_acc_T_53) node a_mask_eq_54 = and(a_mask_sub_11_2_1, a_mask_nbit_1) node _a_mask_acc_T_54 = and(a_mask_size_1, a_mask_eq_54) node a_mask_acc_54 = or(a_mask_sub_11_1_1, _a_mask_acc_T_54) node a_mask_eq_55 = and(a_mask_sub_11_2_1, a_mask_bit_1) node _a_mask_acc_T_55 = and(a_mask_size_1, a_mask_eq_55) node a_mask_acc_55 = or(a_mask_sub_11_1_1, _a_mask_acc_T_55) node a_mask_eq_56 = and(a_mask_sub_12_2_1, a_mask_nbit_1) node _a_mask_acc_T_56 = and(a_mask_size_1, a_mask_eq_56) node a_mask_acc_56 = or(a_mask_sub_12_1_1, _a_mask_acc_T_56) node a_mask_eq_57 = and(a_mask_sub_12_2_1, a_mask_bit_1) node _a_mask_acc_T_57 = and(a_mask_size_1, a_mask_eq_57) node a_mask_acc_57 = or(a_mask_sub_12_1_1, _a_mask_acc_T_57) node a_mask_eq_58 = and(a_mask_sub_13_2_1, a_mask_nbit_1) node _a_mask_acc_T_58 = and(a_mask_size_1, a_mask_eq_58) node a_mask_acc_58 = or(a_mask_sub_13_1_1, _a_mask_acc_T_58) node a_mask_eq_59 = and(a_mask_sub_13_2_1, a_mask_bit_1) node _a_mask_acc_T_59 = and(a_mask_size_1, a_mask_eq_59) node a_mask_acc_59 = or(a_mask_sub_13_1_1, _a_mask_acc_T_59) node a_mask_eq_60 = and(a_mask_sub_14_2_1, a_mask_nbit_1) node _a_mask_acc_T_60 = and(a_mask_size_1, a_mask_eq_60) node a_mask_acc_60 = or(a_mask_sub_14_1_1, _a_mask_acc_T_60) node a_mask_eq_61 = and(a_mask_sub_14_2_1, a_mask_bit_1) node _a_mask_acc_T_61 = and(a_mask_size_1, a_mask_eq_61) node a_mask_acc_61 = or(a_mask_sub_14_1_1, _a_mask_acc_T_61) node a_mask_eq_62 = and(a_mask_sub_15_2_1, a_mask_nbit_1) node _a_mask_acc_T_62 = and(a_mask_size_1, a_mask_eq_62) node a_mask_acc_62 = or(a_mask_sub_15_1_1, _a_mask_acc_T_62) node a_mask_eq_63 = and(a_mask_sub_15_2_1, a_mask_bit_1) node _a_mask_acc_T_63 = and(a_mask_size_1, a_mask_eq_63) node a_mask_acc_63 = or(a_mask_sub_15_1_1, _a_mask_acc_T_63) node a_mask_lo_lo_lo_lo_1 = cat(a_mask_acc_33, a_mask_acc_32) node a_mask_lo_lo_lo_hi_1 = cat(a_mask_acc_35, a_mask_acc_34) node a_mask_lo_lo_lo_1 = cat(a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1) node a_mask_lo_lo_hi_lo_1 = cat(a_mask_acc_37, a_mask_acc_36) node a_mask_lo_lo_hi_hi_1 = cat(a_mask_acc_39, a_mask_acc_38) node a_mask_lo_lo_hi_1 = cat(a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1) node a_mask_lo_lo_1 = cat(a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1) node a_mask_lo_hi_lo_lo_1 = cat(a_mask_acc_41, a_mask_acc_40) node a_mask_lo_hi_lo_hi_1 = cat(a_mask_acc_43, a_mask_acc_42) node a_mask_lo_hi_lo_1 = cat(a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1) node a_mask_lo_hi_hi_lo_1 = cat(a_mask_acc_45, a_mask_acc_44) node a_mask_lo_hi_hi_hi_1 = cat(a_mask_acc_47, a_mask_acc_46) node a_mask_lo_hi_hi_1 = cat(a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1) node a_mask_lo_hi_1 = cat(a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1) node a_mask_lo_1 = cat(a_mask_lo_hi_1, a_mask_lo_lo_1) node a_mask_hi_lo_lo_lo_1 = cat(a_mask_acc_49, a_mask_acc_48) node a_mask_hi_lo_lo_hi_1 = cat(a_mask_acc_51, a_mask_acc_50) node a_mask_hi_lo_lo_1 = cat(a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1) node a_mask_hi_lo_hi_lo_1 = cat(a_mask_acc_53, a_mask_acc_52) node a_mask_hi_lo_hi_hi_1 = cat(a_mask_acc_55, a_mask_acc_54) node a_mask_hi_lo_hi_1 = cat(a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1) node a_mask_hi_lo_1 = cat(a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1) node a_mask_hi_hi_lo_lo_1 = cat(a_mask_acc_57, a_mask_acc_56) node a_mask_hi_hi_lo_hi_1 = cat(a_mask_acc_59, a_mask_acc_58) node a_mask_hi_hi_lo_1 = cat(a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1) node a_mask_hi_hi_hi_lo_1 = cat(a_mask_acc_61, a_mask_acc_60) node a_mask_hi_hi_hi_hi_1 = cat(a_mask_acc_63, a_mask_acc_62) node a_mask_hi_hi_hi_1 = cat(a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1) node a_mask_hi_hi_1 = cat(a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1) node a_mask_hi_1 = cat(a_mask_hi_hi_1, a_mask_hi_lo_1) node _a_mask_T_1 = cat(a_mask_hi_1, a_mask_lo_1) connect bundle_1.mask, _a_mask_T_1 connect bundle_1.data, _T_31 connect bundle_1.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle_1.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle_1.data connect request_latency_injection_q.io.enq.bits.mask, bundle_1.mask connect request_latency_injection_q.io.enq.bits.address, bundle_1.address connect request_latency_injection_q.io.enq.bits.source, bundle_1.source connect request_latency_injection_q.io.enq.bits.size, bundle_1.size connect request_latency_injection_q.io.enq.bits.param, bundle_1.param connect request_latency_injection_q.io.enq.bits.opcode, bundle_1.opcode else : when request_input.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_10 node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : printf(clock, UInt<1>(0h1), "[raw_block_reader] ERR") : printf_11 node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: ERR\n at L2MemHelperLatencyInjection.scala:178 assert(false.B, \"ERR\")\n") : printf_12 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_2 inst Queue4_L2RespInternal of Queue4_L2RespInternal_338 connect Queue4_L2RespInternal.clock, clock connect Queue4_L2RespInternal.reset, reset inst Queue4_L2RespInternal_1 of Queue4_L2RespInternal_339 connect Queue4_L2RespInternal_1.clock, clock connect Queue4_L2RespInternal_1.reset, reset inst Queue4_L2RespInternal_2 of Queue4_L2RespInternal_340 connect Queue4_L2RespInternal_2.clock, clock connect Queue4_L2RespInternal_2.reset, reset inst Queue4_L2RespInternal_3 of Queue4_L2RespInternal_341 connect Queue4_L2RespInternal_3.clock, clock connect Queue4_L2RespInternal_3.reset, reset inst Queue4_L2RespInternal_4 of Queue4_L2RespInternal_342 connect Queue4_L2RespInternal_4.clock, clock connect Queue4_L2RespInternal_4.reset, reset inst Queue4_L2RespInternal_5 of Queue4_L2RespInternal_343 connect Queue4_L2RespInternal_5.clock, clock connect Queue4_L2RespInternal_5.reset, reset inst Queue4_L2RespInternal_6 of Queue4_L2RespInternal_344 connect Queue4_L2RespInternal_6.clock, clock connect Queue4_L2RespInternal_6.reset, reset inst Queue4_L2RespInternal_7 of Queue4_L2RespInternal_345 connect Queue4_L2RespInternal_7.clock, clock connect Queue4_L2RespInternal_7.reset, reset inst Queue4_L2RespInternal_8 of Queue4_L2RespInternal_346 connect Queue4_L2RespInternal_8.clock, clock connect Queue4_L2RespInternal_8.reset, reset inst Queue4_L2RespInternal_9 of Queue4_L2RespInternal_347 connect Queue4_L2RespInternal_9.clock, clock connect Queue4_L2RespInternal_9.reset, reset inst Queue4_L2RespInternal_10 of Queue4_L2RespInternal_348 connect Queue4_L2RespInternal_10.clock, clock connect Queue4_L2RespInternal_10.reset, reset inst Queue4_L2RespInternal_11 of Queue4_L2RespInternal_349 connect Queue4_L2RespInternal_11.clock, clock connect Queue4_L2RespInternal_11.reset, reset inst Queue4_L2RespInternal_12 of Queue4_L2RespInternal_350 connect Queue4_L2RespInternal_12.clock, clock connect Queue4_L2RespInternal_12.reset, reset inst Queue4_L2RespInternal_13 of Queue4_L2RespInternal_351 connect Queue4_L2RespInternal_13.clock, clock connect Queue4_L2RespInternal_13.reset, reset inst Queue4_L2RespInternal_14 of Queue4_L2RespInternal_352 connect Queue4_L2RespInternal_14.clock, clock connect Queue4_L2RespInternal_14.reset, reset inst Queue4_L2RespInternal_15 of Queue4_L2RespInternal_353 connect Queue4_L2RespInternal_15.clock, clock connect Queue4_L2RespInternal_15.reset, reset inst Queue4_L2RespInternal_16 of Queue4_L2RespInternal_354 connect Queue4_L2RespInternal_16.clock, clock connect Queue4_L2RespInternal_16.reset, reset inst Queue4_L2RespInternal_17 of Queue4_L2RespInternal_355 connect Queue4_L2RespInternal_17.clock, clock connect Queue4_L2RespInternal_17.reset, reset inst Queue4_L2RespInternal_18 of Queue4_L2RespInternal_356 connect Queue4_L2RespInternal_18.clock, clock connect Queue4_L2RespInternal_18.reset, reset inst Queue4_L2RespInternal_19 of Queue4_L2RespInternal_357 connect Queue4_L2RespInternal_19.clock, clock connect Queue4_L2RespInternal_19.reset, reset inst Queue4_L2RespInternal_20 of Queue4_L2RespInternal_358 connect Queue4_L2RespInternal_20.clock, clock connect Queue4_L2RespInternal_20.reset, reset inst Queue4_L2RespInternal_21 of Queue4_L2RespInternal_359 connect Queue4_L2RespInternal_21.clock, clock connect Queue4_L2RespInternal_21.reset, reset inst Queue4_L2RespInternal_22 of Queue4_L2RespInternal_360 connect Queue4_L2RespInternal_22.clock, clock connect Queue4_L2RespInternal_22.reset, reset inst Queue4_L2RespInternal_23 of Queue4_L2RespInternal_361 connect Queue4_L2RespInternal_23.clock, clock connect Queue4_L2RespInternal_23.reset, reset inst Queue4_L2RespInternal_24 of Queue4_L2RespInternal_362 connect Queue4_L2RespInternal_24.clock, clock connect Queue4_L2RespInternal_24.reset, reset inst Queue4_L2RespInternal_25 of Queue4_L2RespInternal_363 connect Queue4_L2RespInternal_25.clock, clock connect Queue4_L2RespInternal_25.reset, reset inst Queue4_L2RespInternal_26 of Queue4_L2RespInternal_364 connect Queue4_L2RespInternal_26.clock, clock connect Queue4_L2RespInternal_26.reset, reset inst Queue4_L2RespInternal_27 of Queue4_L2RespInternal_365 connect Queue4_L2RespInternal_27.clock, clock connect Queue4_L2RespInternal_27.reset, reset inst Queue4_L2RespInternal_28 of Queue4_L2RespInternal_366 connect Queue4_L2RespInternal_28.clock, clock connect Queue4_L2RespInternal_28.reset, reset inst Queue4_L2RespInternal_29 of Queue4_L2RespInternal_367 connect Queue4_L2RespInternal_29.clock, clock connect Queue4_L2RespInternal_29.reset, reset inst Queue4_L2RespInternal_30 of Queue4_L2RespInternal_368 connect Queue4_L2RespInternal_30.clock, clock connect Queue4_L2RespInternal_30.reset, reset inst Queue4_L2RespInternal_31 of Queue4_L2RespInternal_369 connect Queue4_L2RespInternal_31.clock, clock connect Queue4_L2RespInternal_31.reset, reset node _current_request_tag_has_response_space_T = eq(UInt<1>(0h0), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _current_request_tag_has_response_space_T) node _current_request_tag_has_response_space_T_2 = eq(UInt<1>(0h1), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _current_request_tag_has_response_space_T_2) node _current_request_tag_has_response_space_T_4 = eq(UInt<2>(0h2), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _current_request_tag_has_response_space_T_4) node _current_request_tag_has_response_space_T_6 = eq(UInt<2>(0h3), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _current_request_tag_has_response_space_T_6) node _current_request_tag_has_response_space_T_8 = eq(UInt<3>(0h4), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_9 = and(Queue4_L2RespInternal_4.io.enq.ready, _current_request_tag_has_response_space_T_8) node _current_request_tag_has_response_space_T_10 = eq(UInt<3>(0h5), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_11 = and(Queue4_L2RespInternal_5.io.enq.ready, _current_request_tag_has_response_space_T_10) node _current_request_tag_has_response_space_T_12 = eq(UInt<3>(0h6), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_13 = and(Queue4_L2RespInternal_6.io.enq.ready, _current_request_tag_has_response_space_T_12) node _current_request_tag_has_response_space_T_14 = eq(UInt<3>(0h7), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_15 = and(Queue4_L2RespInternal_7.io.enq.ready, _current_request_tag_has_response_space_T_14) node _current_request_tag_has_response_space_T_16 = eq(UInt<4>(0h8), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_17 = and(Queue4_L2RespInternal_8.io.enq.ready, _current_request_tag_has_response_space_T_16) node _current_request_tag_has_response_space_T_18 = eq(UInt<4>(0h9), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_19 = and(Queue4_L2RespInternal_9.io.enq.ready, _current_request_tag_has_response_space_T_18) node _current_request_tag_has_response_space_T_20 = eq(UInt<4>(0ha), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_21 = and(Queue4_L2RespInternal_10.io.enq.ready, _current_request_tag_has_response_space_T_20) node _current_request_tag_has_response_space_T_22 = eq(UInt<4>(0hb), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_23 = and(Queue4_L2RespInternal_11.io.enq.ready, _current_request_tag_has_response_space_T_22) node _current_request_tag_has_response_space_T_24 = eq(UInt<4>(0hc), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_25 = and(Queue4_L2RespInternal_12.io.enq.ready, _current_request_tag_has_response_space_T_24) node _current_request_tag_has_response_space_T_26 = eq(UInt<4>(0hd), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_27 = and(Queue4_L2RespInternal_13.io.enq.ready, _current_request_tag_has_response_space_T_26) node _current_request_tag_has_response_space_T_28 = eq(UInt<4>(0he), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_29 = and(Queue4_L2RespInternal_14.io.enq.ready, _current_request_tag_has_response_space_T_28) node _current_request_tag_has_response_space_T_30 = eq(UInt<4>(0hf), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_31 = and(Queue4_L2RespInternal_15.io.enq.ready, _current_request_tag_has_response_space_T_30) node _current_request_tag_has_response_space_T_32 = eq(UInt<5>(0h10), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_33 = and(Queue4_L2RespInternal_16.io.enq.ready, _current_request_tag_has_response_space_T_32) node _current_request_tag_has_response_space_T_34 = eq(UInt<5>(0h11), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_35 = and(Queue4_L2RespInternal_17.io.enq.ready, _current_request_tag_has_response_space_T_34) node _current_request_tag_has_response_space_T_36 = eq(UInt<5>(0h12), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_37 = and(Queue4_L2RespInternal_18.io.enq.ready, _current_request_tag_has_response_space_T_36) node _current_request_tag_has_response_space_T_38 = eq(UInt<5>(0h13), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_39 = and(Queue4_L2RespInternal_19.io.enq.ready, _current_request_tag_has_response_space_T_38) node _current_request_tag_has_response_space_T_40 = eq(UInt<5>(0h14), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_41 = and(Queue4_L2RespInternal_20.io.enq.ready, _current_request_tag_has_response_space_T_40) node _current_request_tag_has_response_space_T_42 = eq(UInt<5>(0h15), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_43 = and(Queue4_L2RespInternal_21.io.enq.ready, _current_request_tag_has_response_space_T_42) node _current_request_tag_has_response_space_T_44 = eq(UInt<5>(0h16), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_45 = and(Queue4_L2RespInternal_22.io.enq.ready, _current_request_tag_has_response_space_T_44) node _current_request_tag_has_response_space_T_46 = eq(UInt<5>(0h17), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_47 = and(Queue4_L2RespInternal_23.io.enq.ready, _current_request_tag_has_response_space_T_46) node _current_request_tag_has_response_space_T_48 = eq(UInt<5>(0h18), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_49 = and(Queue4_L2RespInternal_24.io.enq.ready, _current_request_tag_has_response_space_T_48) node _current_request_tag_has_response_space_T_50 = eq(UInt<5>(0h19), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_51 = and(Queue4_L2RespInternal_25.io.enq.ready, _current_request_tag_has_response_space_T_50) node _current_request_tag_has_response_space_T_52 = eq(UInt<5>(0h1a), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_53 = and(Queue4_L2RespInternal_26.io.enq.ready, _current_request_tag_has_response_space_T_52) node _current_request_tag_has_response_space_T_54 = eq(UInt<5>(0h1b), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_55 = and(Queue4_L2RespInternal_27.io.enq.ready, _current_request_tag_has_response_space_T_54) node _current_request_tag_has_response_space_T_56 = eq(UInt<5>(0h1c), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_57 = and(Queue4_L2RespInternal_28.io.enq.ready, _current_request_tag_has_response_space_T_56) node _current_request_tag_has_response_space_T_58 = eq(UInt<5>(0h1d), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_59 = and(Queue4_L2RespInternal_29.io.enq.ready, _current_request_tag_has_response_space_T_58) node _current_request_tag_has_response_space_T_60 = eq(UInt<5>(0h1e), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_61 = and(Queue4_L2RespInternal_30.io.enq.ready, _current_request_tag_has_response_space_T_60) node _current_request_tag_has_response_space_T_62 = eq(UInt<5>(0h1f), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_63 = and(Queue4_L2RespInternal_31.io.enq.ready, _current_request_tag_has_response_space_T_62) node _current_request_tag_has_response_space_T_64 = or(_current_request_tag_has_response_space_T_1, _current_request_tag_has_response_space_T_3) node _current_request_tag_has_response_space_T_65 = or(_current_request_tag_has_response_space_T_64, _current_request_tag_has_response_space_T_5) node _current_request_tag_has_response_space_T_66 = or(_current_request_tag_has_response_space_T_65, _current_request_tag_has_response_space_T_7) node _current_request_tag_has_response_space_T_67 = or(_current_request_tag_has_response_space_T_66, _current_request_tag_has_response_space_T_9) node _current_request_tag_has_response_space_T_68 = or(_current_request_tag_has_response_space_T_67, _current_request_tag_has_response_space_T_11) node _current_request_tag_has_response_space_T_69 = or(_current_request_tag_has_response_space_T_68, _current_request_tag_has_response_space_T_13) node _current_request_tag_has_response_space_T_70 = or(_current_request_tag_has_response_space_T_69, _current_request_tag_has_response_space_T_15) node _current_request_tag_has_response_space_T_71 = or(_current_request_tag_has_response_space_T_70, _current_request_tag_has_response_space_T_17) node _current_request_tag_has_response_space_T_72 = or(_current_request_tag_has_response_space_T_71, _current_request_tag_has_response_space_T_19) node _current_request_tag_has_response_space_T_73 = or(_current_request_tag_has_response_space_T_72, _current_request_tag_has_response_space_T_21) node _current_request_tag_has_response_space_T_74 = or(_current_request_tag_has_response_space_T_73, _current_request_tag_has_response_space_T_23) node _current_request_tag_has_response_space_T_75 = or(_current_request_tag_has_response_space_T_74, _current_request_tag_has_response_space_T_25) node _current_request_tag_has_response_space_T_76 = or(_current_request_tag_has_response_space_T_75, _current_request_tag_has_response_space_T_27) node _current_request_tag_has_response_space_T_77 = or(_current_request_tag_has_response_space_T_76, _current_request_tag_has_response_space_T_29) node _current_request_tag_has_response_space_T_78 = or(_current_request_tag_has_response_space_T_77, _current_request_tag_has_response_space_T_31) node _current_request_tag_has_response_space_T_79 = or(_current_request_tag_has_response_space_T_78, _current_request_tag_has_response_space_T_33) node _current_request_tag_has_response_space_T_80 = or(_current_request_tag_has_response_space_T_79, _current_request_tag_has_response_space_T_35) node _current_request_tag_has_response_space_T_81 = or(_current_request_tag_has_response_space_T_80, _current_request_tag_has_response_space_T_37) node _current_request_tag_has_response_space_T_82 = or(_current_request_tag_has_response_space_T_81, _current_request_tag_has_response_space_T_39) node _current_request_tag_has_response_space_T_83 = or(_current_request_tag_has_response_space_T_82, _current_request_tag_has_response_space_T_41) node _current_request_tag_has_response_space_T_84 = or(_current_request_tag_has_response_space_T_83, _current_request_tag_has_response_space_T_43) node _current_request_tag_has_response_space_T_85 = or(_current_request_tag_has_response_space_T_84, _current_request_tag_has_response_space_T_45) node _current_request_tag_has_response_space_T_86 = or(_current_request_tag_has_response_space_T_85, _current_request_tag_has_response_space_T_47) node _current_request_tag_has_response_space_T_87 = or(_current_request_tag_has_response_space_T_86, _current_request_tag_has_response_space_T_49) node _current_request_tag_has_response_space_T_88 = or(_current_request_tag_has_response_space_T_87, _current_request_tag_has_response_space_T_51) node _current_request_tag_has_response_space_T_89 = or(_current_request_tag_has_response_space_T_88, _current_request_tag_has_response_space_T_53) node _current_request_tag_has_response_space_T_90 = or(_current_request_tag_has_response_space_T_89, _current_request_tag_has_response_space_T_55) node _current_request_tag_has_response_space_T_91 = or(_current_request_tag_has_response_space_T_90, _current_request_tag_has_response_space_T_57) node _current_request_tag_has_response_space_T_92 = or(_current_request_tag_has_response_space_T_91, _current_request_tag_has_response_space_T_59) node _current_request_tag_has_response_space_T_93 = or(_current_request_tag_has_response_space_T_92, _current_request_tag_has_response_space_T_61) node current_request_tag_has_response_space = or(_current_request_tag_has_response_space_T_93, _current_request_tag_has_response_space_T_63) node _outstanding_req_addr_io_enq_bits_addrindex_T = and(request_input.bits.addr, UInt<5>(0h1f)) connect outstanding_req_addr.io.enq.bits.addrindex, _outstanding_req_addr_io_enq_bits_addrindex_T connect outstanding_req_addr.io.enq.bits.tag, tags_for_issue_Q.io.deq.bits node _request_latency_injection_q_io_enq_valid_T = and(request_input.valid, tlb_ready) node _request_latency_injection_q_io_enq_valid_T_1 = and(_request_latency_injection_q_io_enq_valid_T, outstanding_req_addr.io.enq.ready) node _request_latency_injection_q_io_enq_valid_T_2 = and(_request_latency_injection_q_io_enq_valid_T_1, free_outstanding_op_slots) node _request_latency_injection_q_io_enq_valid_T_3 = and(_request_latency_injection_q_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _request_latency_injection_q_io_enq_valid_T_4 = and(_request_latency_injection_q_io_enq_valid_T_3, current_request_tag_has_response_space) connect request_latency_injection_q.io.enq.valid, _request_latency_injection_q_io_enq_valid_T_4 node _request_input_ready_T = and(request_latency_injection_q.io.enq.ready, tlb_ready) node _request_input_ready_T_1 = and(_request_input_ready_T, outstanding_req_addr.io.enq.ready) node _request_input_ready_T_2 = and(_request_input_ready_T_1, free_outstanding_op_slots) node _request_input_ready_T_3 = and(_request_input_ready_T_2, tags_for_issue_Q.io.deq.valid) node _request_input_ready_T_4 = and(_request_input_ready_T_3, current_request_tag_has_response_space) connect request_input.ready, _request_input_ready_T_4 node _outstanding_req_addr_io_enq_valid_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _outstanding_req_addr_io_enq_valid_T_1 = and(_outstanding_req_addr_io_enq_valid_T, tlb_ready) node _outstanding_req_addr_io_enq_valid_T_2 = and(_outstanding_req_addr_io_enq_valid_T_1, free_outstanding_op_slots) node _outstanding_req_addr_io_enq_valid_T_3 = and(_outstanding_req_addr_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _outstanding_req_addr_io_enq_valid_T_4 = and(_outstanding_req_addr_io_enq_valid_T_3, current_request_tag_has_response_space) connect outstanding_req_addr.io.enq.valid, _outstanding_req_addr_io_enq_valid_T_4 node _tags_for_issue_Q_io_deq_ready_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_1 = and(_tags_for_issue_Q_io_deq_ready_T, tlb_ready) node _tags_for_issue_Q_io_deq_ready_T_2 = and(_tags_for_issue_Q_io_deq_ready_T_1, outstanding_req_addr.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_3 = and(_tags_for_issue_Q_io_deq_ready_T_2, free_outstanding_op_slots) node _tags_for_issue_Q_io_deq_ready_T_4 = and(_tags_for_issue_Q_io_deq_ready_T_3, current_request_tag_has_response_space) connect tags_for_issue_Q.io.deq.ready, _tags_for_issue_Q_io_deq_ready_T_4 connect masterNodeOut.a.bits, request_latency_injection_q.io.deq.bits connect masterNodeOut.a.valid, request_latency_injection_q.io.deq.valid connect request_latency_injection_q.io.deq.ready, masterNodeOut.a.ready node _T_39 = and(masterNodeOut.a.ready, masterNodeOut.a.valid) when _T_39 : node _T_40 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_40 : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_13 node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_14 node _T_45 = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _T_46 = and(_T_45, tlb_ready) node _T_47 = and(_T_46, outstanding_req_addr.io.enq.ready) node _T_48 = and(_T_47, free_outstanding_op_slots) node _T_49 = and(_T_48, tags_for_issue_Q.io.deq.valid) node _T_50 = and(_T_49, current_request_tag_has_response_space) when _T_50 : node _T_51 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_51 : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _printf_T = asUInt(reset) node _printf_T_1 = eq(_printf_T, UInt<1>(0h0)) when _printf_T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_15 node _T_52 = asUInt(reset) node _T_53 = eq(_T_52, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "") : printf_16 node _printf_T_2 = asUInt(reset) node _printf_T_3 = eq(_printf_T_2, UInt<1>(0h0)) when _printf_T_3 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: req(write) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, data: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, request_input.bits.data, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_17 node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "") : printf_18 inst response_latency_injection_q of LatencyInjectionQueue_29 connect response_latency_injection_q.clock, clock connect response_latency_injection_q.reset, reset connect response_latency_injection_q.io.latency_cycles, io.latency_inject_cycles connect response_latency_injection_q.io.enq, masterNodeOut.d node _selectQready_T = eq(UInt<1>(0h0), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _selectQready_T) node _selectQready_T_2 = eq(UInt<1>(0h1), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _selectQready_T_2) node _selectQready_T_4 = eq(UInt<2>(0h2), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _selectQready_T_4) node _selectQready_T_6 = eq(UInt<2>(0h3), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _selectQready_T_6) node _selectQready_T_8 = eq(UInt<3>(0h4), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_9 = and(Queue4_L2RespInternal_4.io.enq.ready, _selectQready_T_8) node _selectQready_T_10 = eq(UInt<3>(0h5), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_11 = and(Queue4_L2RespInternal_5.io.enq.ready, _selectQready_T_10) node _selectQready_T_12 = eq(UInt<3>(0h6), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_13 = and(Queue4_L2RespInternal_6.io.enq.ready, _selectQready_T_12) node _selectQready_T_14 = eq(UInt<3>(0h7), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_15 = and(Queue4_L2RespInternal_7.io.enq.ready, _selectQready_T_14) node _selectQready_T_16 = eq(UInt<4>(0h8), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_17 = and(Queue4_L2RespInternal_8.io.enq.ready, _selectQready_T_16) node _selectQready_T_18 = eq(UInt<4>(0h9), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_19 = and(Queue4_L2RespInternal_9.io.enq.ready, _selectQready_T_18) node _selectQready_T_20 = eq(UInt<4>(0ha), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_21 = and(Queue4_L2RespInternal_10.io.enq.ready, _selectQready_T_20) node _selectQready_T_22 = eq(UInt<4>(0hb), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_23 = and(Queue4_L2RespInternal_11.io.enq.ready, _selectQready_T_22) node _selectQready_T_24 = eq(UInt<4>(0hc), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_25 = and(Queue4_L2RespInternal_12.io.enq.ready, _selectQready_T_24) node _selectQready_T_26 = eq(UInt<4>(0hd), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_27 = and(Queue4_L2RespInternal_13.io.enq.ready, _selectQready_T_26) node _selectQready_T_28 = eq(UInt<4>(0he), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_29 = and(Queue4_L2RespInternal_14.io.enq.ready, _selectQready_T_28) node _selectQready_T_30 = eq(UInt<4>(0hf), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_31 = and(Queue4_L2RespInternal_15.io.enq.ready, _selectQready_T_30) node _selectQready_T_32 = eq(UInt<5>(0h10), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_33 = and(Queue4_L2RespInternal_16.io.enq.ready, _selectQready_T_32) node _selectQready_T_34 = eq(UInt<5>(0h11), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_35 = and(Queue4_L2RespInternal_17.io.enq.ready, _selectQready_T_34) node _selectQready_T_36 = eq(UInt<5>(0h12), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_37 = and(Queue4_L2RespInternal_18.io.enq.ready, _selectQready_T_36) node _selectQready_T_38 = eq(UInt<5>(0h13), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_39 = and(Queue4_L2RespInternal_19.io.enq.ready, _selectQready_T_38) node _selectQready_T_40 = eq(UInt<5>(0h14), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_41 = and(Queue4_L2RespInternal_20.io.enq.ready, _selectQready_T_40) node _selectQready_T_42 = eq(UInt<5>(0h15), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_43 = and(Queue4_L2RespInternal_21.io.enq.ready, _selectQready_T_42) node _selectQready_T_44 = eq(UInt<5>(0h16), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_45 = and(Queue4_L2RespInternal_22.io.enq.ready, _selectQready_T_44) node _selectQready_T_46 = eq(UInt<5>(0h17), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_47 = and(Queue4_L2RespInternal_23.io.enq.ready, _selectQready_T_46) node _selectQready_T_48 = eq(UInt<5>(0h18), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_49 = and(Queue4_L2RespInternal_24.io.enq.ready, _selectQready_T_48) node _selectQready_T_50 = eq(UInt<5>(0h19), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_51 = and(Queue4_L2RespInternal_25.io.enq.ready, _selectQready_T_50) node _selectQready_T_52 = eq(UInt<5>(0h1a), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_53 = and(Queue4_L2RespInternal_26.io.enq.ready, _selectQready_T_52) node _selectQready_T_54 = eq(UInt<5>(0h1b), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_55 = and(Queue4_L2RespInternal_27.io.enq.ready, _selectQready_T_54) node _selectQready_T_56 = eq(UInt<5>(0h1c), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_57 = and(Queue4_L2RespInternal_28.io.enq.ready, _selectQready_T_56) node _selectQready_T_58 = eq(UInt<5>(0h1d), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_59 = and(Queue4_L2RespInternal_29.io.enq.ready, _selectQready_T_58) node _selectQready_T_60 = eq(UInt<5>(0h1e), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_61 = and(Queue4_L2RespInternal_30.io.enq.ready, _selectQready_T_60) node _selectQready_T_62 = eq(UInt<5>(0h1f), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_63 = and(Queue4_L2RespInternal_31.io.enq.ready, _selectQready_T_62) node _selectQready_T_64 = or(_selectQready_T_1, _selectQready_T_3) node _selectQready_T_65 = or(_selectQready_T_64, _selectQready_T_5) node _selectQready_T_66 = or(_selectQready_T_65, _selectQready_T_7) node _selectQready_T_67 = or(_selectQready_T_66, _selectQready_T_9) node _selectQready_T_68 = or(_selectQready_T_67, _selectQready_T_11) node _selectQready_T_69 = or(_selectQready_T_68, _selectQready_T_13) node _selectQready_T_70 = or(_selectQready_T_69, _selectQready_T_15) node _selectQready_T_71 = or(_selectQready_T_70, _selectQready_T_17) node _selectQready_T_72 = or(_selectQready_T_71, _selectQready_T_19) node _selectQready_T_73 = or(_selectQready_T_72, _selectQready_T_21) node _selectQready_T_74 = or(_selectQready_T_73, _selectQready_T_23) node _selectQready_T_75 = or(_selectQready_T_74, _selectQready_T_25) node _selectQready_T_76 = or(_selectQready_T_75, _selectQready_T_27) node _selectQready_T_77 = or(_selectQready_T_76, _selectQready_T_29) node _selectQready_T_78 = or(_selectQready_T_77, _selectQready_T_31) node _selectQready_T_79 = or(_selectQready_T_78, _selectQready_T_33) node _selectQready_T_80 = or(_selectQready_T_79, _selectQready_T_35) node _selectQready_T_81 = or(_selectQready_T_80, _selectQready_T_37) node _selectQready_T_82 = or(_selectQready_T_81, _selectQready_T_39) node _selectQready_T_83 = or(_selectQready_T_82, _selectQready_T_41) node _selectQready_T_84 = or(_selectQready_T_83, _selectQready_T_43) node _selectQready_T_85 = or(_selectQready_T_84, _selectQready_T_45) node _selectQready_T_86 = or(_selectQready_T_85, _selectQready_T_47) node _selectQready_T_87 = or(_selectQready_T_86, _selectQready_T_49) node _selectQready_T_88 = or(_selectQready_T_87, _selectQready_T_51) node _selectQready_T_89 = or(_selectQready_T_88, _selectQready_T_53) node _selectQready_T_90 = or(_selectQready_T_89, _selectQready_T_55) node _selectQready_T_91 = or(_selectQready_T_90, _selectQready_T_57) node _selectQready_T_92 = or(_selectQready_T_91, _selectQready_T_59) node _selectQready_T_93 = or(_selectQready_T_92, _selectQready_T_61) node selectQready = or(_selectQready_T_93, _selectQready_T_63) node _T_56 = and(selectQready, response_latency_injection_q.io.deq.valid) when _T_56 : connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) connect tags_for_issue_Q.io.enq.bits, response_latency_injection_q.io.deq.bits.source node _T_57 = and(selectQready, response_latency_injection_q.io.deq.valid) node _T_58 = and(_T_57, tags_for_issue_Q.io.enq.valid) when _T_58 : regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_19 node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "[raw_block_reader] tags_for_issue_Q add back tag %d\n", tags_for_issue_Q.io.enq.bits) : printf_20 node _response_latency_injection_q_io_deq_ready_T = and(selectQready, tags_for_issue_Q.io.enq.ready) connect response_latency_injection_q.io.deq.ready, _response_latency_injection_q_io_deq_ready_T node _T_63 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_64 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) connect Queue4_L2RespInternal.io.enq.valid, _T_65 connect Queue4_L2RespInternal.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_66 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_67 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h1)) node _T_68 = and(_T_66, _T_67) connect Queue4_L2RespInternal_1.io.enq.valid, _T_68 connect Queue4_L2RespInternal_1.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_69 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_70 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h2)) node _T_71 = and(_T_69, _T_70) connect Queue4_L2RespInternal_2.io.enq.valid, _T_71 connect Queue4_L2RespInternal_2.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_72 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_73 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h3)) node _T_74 = and(_T_72, _T_73) connect Queue4_L2RespInternal_3.io.enq.valid, _T_74 connect Queue4_L2RespInternal_3.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_75 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_76 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h4)) node _T_77 = and(_T_75, _T_76) connect Queue4_L2RespInternal_4.io.enq.valid, _T_77 connect Queue4_L2RespInternal_4.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_78 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_79 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h5)) node _T_80 = and(_T_78, _T_79) connect Queue4_L2RespInternal_5.io.enq.valid, _T_80 connect Queue4_L2RespInternal_5.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_81 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_82 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h6)) node _T_83 = and(_T_81, _T_82) connect Queue4_L2RespInternal_6.io.enq.valid, _T_83 connect Queue4_L2RespInternal_6.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_84 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_85 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h7)) node _T_86 = and(_T_84, _T_85) connect Queue4_L2RespInternal_7.io.enq.valid, _T_86 connect Queue4_L2RespInternal_7.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_87 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_88 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0h8)) node _T_89 = and(_T_87, _T_88) connect Queue4_L2RespInternal_8.io.enq.valid, _T_89 connect Queue4_L2RespInternal_8.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_90 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_91 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0h9)) node _T_92 = and(_T_90, _T_91) connect Queue4_L2RespInternal_9.io.enq.valid, _T_92 connect Queue4_L2RespInternal_9.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_93 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_94 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0ha)) node _T_95 = and(_T_93, _T_94) connect Queue4_L2RespInternal_10.io.enq.valid, _T_95 connect Queue4_L2RespInternal_10.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_96 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_97 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hb)) node _T_98 = and(_T_96, _T_97) connect Queue4_L2RespInternal_11.io.enq.valid, _T_98 connect Queue4_L2RespInternal_11.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_99 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_100 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) connect Queue4_L2RespInternal_12.io.enq.valid, _T_101 connect Queue4_L2RespInternal_12.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_102 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_103 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hd)) node _T_104 = and(_T_102, _T_103) connect Queue4_L2RespInternal_13.io.enq.valid, _T_104 connect Queue4_L2RespInternal_13.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_105 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_106 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0he)) node _T_107 = and(_T_105, _T_106) connect Queue4_L2RespInternal_14.io.enq.valid, _T_107 connect Queue4_L2RespInternal_14.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_108 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_109 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hf)) node _T_110 = and(_T_108, _T_109) connect Queue4_L2RespInternal_15.io.enq.valid, _T_110 connect Queue4_L2RespInternal_15.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_111 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_112 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h10)) node _T_113 = and(_T_111, _T_112) connect Queue4_L2RespInternal_16.io.enq.valid, _T_113 connect Queue4_L2RespInternal_16.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_114 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_115 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h11)) node _T_116 = and(_T_114, _T_115) connect Queue4_L2RespInternal_17.io.enq.valid, _T_116 connect Queue4_L2RespInternal_17.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_117 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_118 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h12)) node _T_119 = and(_T_117, _T_118) connect Queue4_L2RespInternal_18.io.enq.valid, _T_119 connect Queue4_L2RespInternal_18.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_120 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_121 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h13)) node _T_122 = and(_T_120, _T_121) connect Queue4_L2RespInternal_19.io.enq.valid, _T_122 connect Queue4_L2RespInternal_19.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_123 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_124 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h14)) node _T_125 = and(_T_123, _T_124) connect Queue4_L2RespInternal_20.io.enq.valid, _T_125 connect Queue4_L2RespInternal_20.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_126 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_127 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h15)) node _T_128 = and(_T_126, _T_127) connect Queue4_L2RespInternal_21.io.enq.valid, _T_128 connect Queue4_L2RespInternal_21.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_129 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_130 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h16)) node _T_131 = and(_T_129, _T_130) connect Queue4_L2RespInternal_22.io.enq.valid, _T_131 connect Queue4_L2RespInternal_22.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_132 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_133 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h17)) node _T_134 = and(_T_132, _T_133) connect Queue4_L2RespInternal_23.io.enq.valid, _T_134 connect Queue4_L2RespInternal_23.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_135 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_136 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h18)) node _T_137 = and(_T_135, _T_136) connect Queue4_L2RespInternal_24.io.enq.valid, _T_137 connect Queue4_L2RespInternal_24.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_138 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_139 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h19)) node _T_140 = and(_T_138, _T_139) connect Queue4_L2RespInternal_25.io.enq.valid, _T_140 connect Queue4_L2RespInternal_25.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_141 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_142 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1a)) node _T_143 = and(_T_141, _T_142) connect Queue4_L2RespInternal_26.io.enq.valid, _T_143 connect Queue4_L2RespInternal_26.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_144 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_145 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1b)) node _T_146 = and(_T_144, _T_145) connect Queue4_L2RespInternal_27.io.enq.valid, _T_146 connect Queue4_L2RespInternal_27.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_147 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_148 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1c)) node _T_149 = and(_T_147, _T_148) connect Queue4_L2RespInternal_28.io.enq.valid, _T_149 connect Queue4_L2RespInternal_28.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_150 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_151 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1d)) node _T_152 = and(_T_150, _T_151) connect Queue4_L2RespInternal_29.io.enq.valid, _T_152 connect Queue4_L2RespInternal_29.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_153 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_154 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1e)) node _T_155 = and(_T_153, _T_154) connect Queue4_L2RespInternal_30.io.enq.valid, _T_155 connect Queue4_L2RespInternal_30.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_156 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_157 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1f)) node _T_158 = and(_T_156, _T_157) connect Queue4_L2RespInternal_31.io.enq.valid, _T_158 connect Queue4_L2RespInternal_31.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _queueValid_T = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_1 = and(Queue4_L2RespInternal.io.deq.valid, _queueValid_T) node _queueValid_T_2 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_3 = and(Queue4_L2RespInternal_1.io.deq.valid, _queueValid_T_2) node _queueValid_T_4 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_5 = and(Queue4_L2RespInternal_2.io.deq.valid, _queueValid_T_4) node _queueValid_T_6 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_7 = and(Queue4_L2RespInternal_3.io.deq.valid, _queueValid_T_6) node _queueValid_T_8 = eq(UInt<3>(0h4), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_9 = and(Queue4_L2RespInternal_4.io.deq.valid, _queueValid_T_8) node _queueValid_T_10 = eq(UInt<3>(0h5), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_11 = and(Queue4_L2RespInternal_5.io.deq.valid, _queueValid_T_10) node _queueValid_T_12 = eq(UInt<3>(0h6), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_13 = and(Queue4_L2RespInternal_6.io.deq.valid, _queueValid_T_12) node _queueValid_T_14 = eq(UInt<3>(0h7), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_15 = and(Queue4_L2RespInternal_7.io.deq.valid, _queueValid_T_14) node _queueValid_T_16 = eq(UInt<4>(0h8), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_17 = and(Queue4_L2RespInternal_8.io.deq.valid, _queueValid_T_16) node _queueValid_T_18 = eq(UInt<4>(0h9), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_19 = and(Queue4_L2RespInternal_9.io.deq.valid, _queueValid_T_18) node _queueValid_T_20 = eq(UInt<4>(0ha), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_21 = and(Queue4_L2RespInternal_10.io.deq.valid, _queueValid_T_20) node _queueValid_T_22 = eq(UInt<4>(0hb), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_23 = and(Queue4_L2RespInternal_11.io.deq.valid, _queueValid_T_22) node _queueValid_T_24 = eq(UInt<4>(0hc), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_25 = and(Queue4_L2RespInternal_12.io.deq.valid, _queueValid_T_24) node _queueValid_T_26 = eq(UInt<4>(0hd), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_27 = and(Queue4_L2RespInternal_13.io.deq.valid, _queueValid_T_26) node _queueValid_T_28 = eq(UInt<4>(0he), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_29 = and(Queue4_L2RespInternal_14.io.deq.valid, _queueValid_T_28) node _queueValid_T_30 = eq(UInt<4>(0hf), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_31 = and(Queue4_L2RespInternal_15.io.deq.valid, _queueValid_T_30) node _queueValid_T_32 = eq(UInt<5>(0h10), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_33 = and(Queue4_L2RespInternal_16.io.deq.valid, _queueValid_T_32) node _queueValid_T_34 = eq(UInt<5>(0h11), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_35 = and(Queue4_L2RespInternal_17.io.deq.valid, _queueValid_T_34) node _queueValid_T_36 = eq(UInt<5>(0h12), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_37 = and(Queue4_L2RespInternal_18.io.deq.valid, _queueValid_T_36) node _queueValid_T_38 = eq(UInt<5>(0h13), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_39 = and(Queue4_L2RespInternal_19.io.deq.valid, _queueValid_T_38) node _queueValid_T_40 = eq(UInt<5>(0h14), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_41 = and(Queue4_L2RespInternal_20.io.deq.valid, _queueValid_T_40) node _queueValid_T_42 = eq(UInt<5>(0h15), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_43 = and(Queue4_L2RespInternal_21.io.deq.valid, _queueValid_T_42) node _queueValid_T_44 = eq(UInt<5>(0h16), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_45 = and(Queue4_L2RespInternal_22.io.deq.valid, _queueValid_T_44) node _queueValid_T_46 = eq(UInt<5>(0h17), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_47 = and(Queue4_L2RespInternal_23.io.deq.valid, _queueValid_T_46) node _queueValid_T_48 = eq(UInt<5>(0h18), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_49 = and(Queue4_L2RespInternal_24.io.deq.valid, _queueValid_T_48) node _queueValid_T_50 = eq(UInt<5>(0h19), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_51 = and(Queue4_L2RespInternal_25.io.deq.valid, _queueValid_T_50) node _queueValid_T_52 = eq(UInt<5>(0h1a), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_53 = and(Queue4_L2RespInternal_26.io.deq.valid, _queueValid_T_52) node _queueValid_T_54 = eq(UInt<5>(0h1b), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_55 = and(Queue4_L2RespInternal_27.io.deq.valid, _queueValid_T_54) node _queueValid_T_56 = eq(UInt<5>(0h1c), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_57 = and(Queue4_L2RespInternal_28.io.deq.valid, _queueValid_T_56) node _queueValid_T_58 = eq(UInt<5>(0h1d), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_59 = and(Queue4_L2RespInternal_29.io.deq.valid, _queueValid_T_58) node _queueValid_T_60 = eq(UInt<5>(0h1e), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_61 = and(Queue4_L2RespInternal_30.io.deq.valid, _queueValid_T_60) node _queueValid_T_62 = eq(UInt<5>(0h1f), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_63 = and(Queue4_L2RespInternal_31.io.deq.valid, _queueValid_T_62) node _queueValid_T_64 = or(_queueValid_T_1, _queueValid_T_3) node _queueValid_T_65 = or(_queueValid_T_64, _queueValid_T_5) node _queueValid_T_66 = or(_queueValid_T_65, _queueValid_T_7) node _queueValid_T_67 = or(_queueValid_T_66, _queueValid_T_9) node _queueValid_T_68 = or(_queueValid_T_67, _queueValid_T_11) node _queueValid_T_69 = or(_queueValid_T_68, _queueValid_T_13) node _queueValid_T_70 = or(_queueValid_T_69, _queueValid_T_15) node _queueValid_T_71 = or(_queueValid_T_70, _queueValid_T_17) node _queueValid_T_72 = or(_queueValid_T_71, _queueValid_T_19) node _queueValid_T_73 = or(_queueValid_T_72, _queueValid_T_21) node _queueValid_T_74 = or(_queueValid_T_73, _queueValid_T_23) node _queueValid_T_75 = or(_queueValid_T_74, _queueValid_T_25) node _queueValid_T_76 = or(_queueValid_T_75, _queueValid_T_27) node _queueValid_T_77 = or(_queueValid_T_76, _queueValid_T_29) node _queueValid_T_78 = or(_queueValid_T_77, _queueValid_T_31) node _queueValid_T_79 = or(_queueValid_T_78, _queueValid_T_33) node _queueValid_T_80 = or(_queueValid_T_79, _queueValid_T_35) node _queueValid_T_81 = or(_queueValid_T_80, _queueValid_T_37) node _queueValid_T_82 = or(_queueValid_T_81, _queueValid_T_39) node _queueValid_T_83 = or(_queueValid_T_82, _queueValid_T_41) node _queueValid_T_84 = or(_queueValid_T_83, _queueValid_T_43) node _queueValid_T_85 = or(_queueValid_T_84, _queueValid_T_45) node _queueValid_T_86 = or(_queueValid_T_85, _queueValid_T_47) node _queueValid_T_87 = or(_queueValid_T_86, _queueValid_T_49) node _queueValid_T_88 = or(_queueValid_T_87, _queueValid_T_51) node _queueValid_T_89 = or(_queueValid_T_88, _queueValid_T_53) node _queueValid_T_90 = or(_queueValid_T_89, _queueValid_T_55) node _queueValid_T_91 = or(_queueValid_T_90, _queueValid_T_57) node _queueValid_T_92 = or(_queueValid_T_91, _queueValid_T_59) node _queueValid_T_93 = or(_queueValid_T_92, _queueValid_T_61) node queueValid = or(_queueValid_T_93, _queueValid_T_63) node resultdata_is_current_q = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data : UInt<256> when resultdata_is_current_q : node _resultdata_data_T = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_1 = dshr(Queue4_L2RespInternal.io.deq.bits.data, _resultdata_data_T) connect resultdata_data, _resultdata_data_T_1 else : connect resultdata_data, UInt<1>(0h0) node resultdata_is_current_q_1 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_1 : UInt<256> when resultdata_is_current_q_1 : node _resultdata_data_T_2 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_3 = dshr(Queue4_L2RespInternal_1.io.deq.bits.data, _resultdata_data_T_2) connect resultdata_data_1, _resultdata_data_T_3 else : connect resultdata_data_1, UInt<1>(0h0) node resultdata_is_current_q_2 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_2 : UInt<256> when resultdata_is_current_q_2 : node _resultdata_data_T_4 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_5 = dshr(Queue4_L2RespInternal_2.io.deq.bits.data, _resultdata_data_T_4) connect resultdata_data_2, _resultdata_data_T_5 else : connect resultdata_data_2, UInt<1>(0h0) node resultdata_is_current_q_3 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_3 : UInt<256> when resultdata_is_current_q_3 : node _resultdata_data_T_6 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_7 = dshr(Queue4_L2RespInternal_3.io.deq.bits.data, _resultdata_data_T_6) connect resultdata_data_3, _resultdata_data_T_7 else : connect resultdata_data_3, UInt<1>(0h0) node resultdata_is_current_q_4 = eq(UInt<3>(0h4), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_4 : UInt<256> when resultdata_is_current_q_4 : node _resultdata_data_T_8 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_9 = dshr(Queue4_L2RespInternal_4.io.deq.bits.data, _resultdata_data_T_8) connect resultdata_data_4, _resultdata_data_T_9 else : connect resultdata_data_4, UInt<1>(0h0) node resultdata_is_current_q_5 = eq(UInt<3>(0h5), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_5 : UInt<256> when resultdata_is_current_q_5 : node _resultdata_data_T_10 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_11 = dshr(Queue4_L2RespInternal_5.io.deq.bits.data, _resultdata_data_T_10) connect resultdata_data_5, _resultdata_data_T_11 else : connect resultdata_data_5, UInt<1>(0h0) node resultdata_is_current_q_6 = eq(UInt<3>(0h6), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_6 : UInt<256> when resultdata_is_current_q_6 : node _resultdata_data_T_12 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_13 = dshr(Queue4_L2RespInternal_6.io.deq.bits.data, _resultdata_data_T_12) connect resultdata_data_6, _resultdata_data_T_13 else : connect resultdata_data_6, UInt<1>(0h0) node resultdata_is_current_q_7 = eq(UInt<3>(0h7), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_7 : UInt<256> when resultdata_is_current_q_7 : node _resultdata_data_T_14 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_15 = dshr(Queue4_L2RespInternal_7.io.deq.bits.data, _resultdata_data_T_14) connect resultdata_data_7, _resultdata_data_T_15 else : connect resultdata_data_7, UInt<1>(0h0) node resultdata_is_current_q_8 = eq(UInt<4>(0h8), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_8 : UInt<256> when resultdata_is_current_q_8 : node _resultdata_data_T_16 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_17 = dshr(Queue4_L2RespInternal_8.io.deq.bits.data, _resultdata_data_T_16) connect resultdata_data_8, _resultdata_data_T_17 else : connect resultdata_data_8, UInt<1>(0h0) node resultdata_is_current_q_9 = eq(UInt<4>(0h9), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_9 : UInt<256> when resultdata_is_current_q_9 : node _resultdata_data_T_18 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_19 = dshr(Queue4_L2RespInternal_9.io.deq.bits.data, _resultdata_data_T_18) connect resultdata_data_9, _resultdata_data_T_19 else : connect resultdata_data_9, UInt<1>(0h0) node resultdata_is_current_q_10 = eq(UInt<4>(0ha), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_10 : UInt<256> when resultdata_is_current_q_10 : node _resultdata_data_T_20 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_21 = dshr(Queue4_L2RespInternal_10.io.deq.bits.data, _resultdata_data_T_20) connect resultdata_data_10, _resultdata_data_T_21 else : connect resultdata_data_10, UInt<1>(0h0) node resultdata_is_current_q_11 = eq(UInt<4>(0hb), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_11 : UInt<256> when resultdata_is_current_q_11 : node _resultdata_data_T_22 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_23 = dshr(Queue4_L2RespInternal_11.io.deq.bits.data, _resultdata_data_T_22) connect resultdata_data_11, _resultdata_data_T_23 else : connect resultdata_data_11, UInt<1>(0h0) node resultdata_is_current_q_12 = eq(UInt<4>(0hc), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_12 : UInt<256> when resultdata_is_current_q_12 : node _resultdata_data_T_24 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_25 = dshr(Queue4_L2RespInternal_12.io.deq.bits.data, _resultdata_data_T_24) connect resultdata_data_12, _resultdata_data_T_25 else : connect resultdata_data_12, UInt<1>(0h0) node resultdata_is_current_q_13 = eq(UInt<4>(0hd), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_13 : UInt<256> when resultdata_is_current_q_13 : node _resultdata_data_T_26 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_27 = dshr(Queue4_L2RespInternal_13.io.deq.bits.data, _resultdata_data_T_26) connect resultdata_data_13, _resultdata_data_T_27 else : connect resultdata_data_13, UInt<1>(0h0) node resultdata_is_current_q_14 = eq(UInt<4>(0he), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_14 : UInt<256> when resultdata_is_current_q_14 : node _resultdata_data_T_28 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_29 = dshr(Queue4_L2RespInternal_14.io.deq.bits.data, _resultdata_data_T_28) connect resultdata_data_14, _resultdata_data_T_29 else : connect resultdata_data_14, UInt<1>(0h0) node resultdata_is_current_q_15 = eq(UInt<4>(0hf), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_15 : UInt<256> when resultdata_is_current_q_15 : node _resultdata_data_T_30 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_31 = dshr(Queue4_L2RespInternal_15.io.deq.bits.data, _resultdata_data_T_30) connect resultdata_data_15, _resultdata_data_T_31 else : connect resultdata_data_15, UInt<1>(0h0) node resultdata_is_current_q_16 = eq(UInt<5>(0h10), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_16 : UInt<256> when resultdata_is_current_q_16 : node _resultdata_data_T_32 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_33 = dshr(Queue4_L2RespInternal_16.io.deq.bits.data, _resultdata_data_T_32) connect resultdata_data_16, _resultdata_data_T_33 else : connect resultdata_data_16, UInt<1>(0h0) node resultdata_is_current_q_17 = eq(UInt<5>(0h11), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_17 : UInt<256> when resultdata_is_current_q_17 : node _resultdata_data_T_34 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_35 = dshr(Queue4_L2RespInternal_17.io.deq.bits.data, _resultdata_data_T_34) connect resultdata_data_17, _resultdata_data_T_35 else : connect resultdata_data_17, UInt<1>(0h0) node resultdata_is_current_q_18 = eq(UInt<5>(0h12), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_18 : UInt<256> when resultdata_is_current_q_18 : node _resultdata_data_T_36 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_37 = dshr(Queue4_L2RespInternal_18.io.deq.bits.data, _resultdata_data_T_36) connect resultdata_data_18, _resultdata_data_T_37 else : connect resultdata_data_18, UInt<1>(0h0) node resultdata_is_current_q_19 = eq(UInt<5>(0h13), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_19 : UInt<256> when resultdata_is_current_q_19 : node _resultdata_data_T_38 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_39 = dshr(Queue4_L2RespInternal_19.io.deq.bits.data, _resultdata_data_T_38) connect resultdata_data_19, _resultdata_data_T_39 else : connect resultdata_data_19, UInt<1>(0h0) node resultdata_is_current_q_20 = eq(UInt<5>(0h14), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_20 : UInt<256> when resultdata_is_current_q_20 : node _resultdata_data_T_40 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_41 = dshr(Queue4_L2RespInternal_20.io.deq.bits.data, _resultdata_data_T_40) connect resultdata_data_20, _resultdata_data_T_41 else : connect resultdata_data_20, UInt<1>(0h0) node resultdata_is_current_q_21 = eq(UInt<5>(0h15), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_21 : UInt<256> when resultdata_is_current_q_21 : node _resultdata_data_T_42 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_43 = dshr(Queue4_L2RespInternal_21.io.deq.bits.data, _resultdata_data_T_42) connect resultdata_data_21, _resultdata_data_T_43 else : connect resultdata_data_21, UInt<1>(0h0) node resultdata_is_current_q_22 = eq(UInt<5>(0h16), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_22 : UInt<256> when resultdata_is_current_q_22 : node _resultdata_data_T_44 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_45 = dshr(Queue4_L2RespInternal_22.io.deq.bits.data, _resultdata_data_T_44) connect resultdata_data_22, _resultdata_data_T_45 else : connect resultdata_data_22, UInt<1>(0h0) node resultdata_is_current_q_23 = eq(UInt<5>(0h17), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_23 : UInt<256> when resultdata_is_current_q_23 : node _resultdata_data_T_46 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_47 = dshr(Queue4_L2RespInternal_23.io.deq.bits.data, _resultdata_data_T_46) connect resultdata_data_23, _resultdata_data_T_47 else : connect resultdata_data_23, UInt<1>(0h0) node resultdata_is_current_q_24 = eq(UInt<5>(0h18), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_24 : UInt<256> when resultdata_is_current_q_24 : node _resultdata_data_T_48 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_49 = dshr(Queue4_L2RespInternal_24.io.deq.bits.data, _resultdata_data_T_48) connect resultdata_data_24, _resultdata_data_T_49 else : connect resultdata_data_24, UInt<1>(0h0) node resultdata_is_current_q_25 = eq(UInt<5>(0h19), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_25 : UInt<256> when resultdata_is_current_q_25 : node _resultdata_data_T_50 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_51 = dshr(Queue4_L2RespInternal_25.io.deq.bits.data, _resultdata_data_T_50) connect resultdata_data_25, _resultdata_data_T_51 else : connect resultdata_data_25, UInt<1>(0h0) node resultdata_is_current_q_26 = eq(UInt<5>(0h1a), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_26 : UInt<256> when resultdata_is_current_q_26 : node _resultdata_data_T_52 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_53 = dshr(Queue4_L2RespInternal_26.io.deq.bits.data, _resultdata_data_T_52) connect resultdata_data_26, _resultdata_data_T_53 else : connect resultdata_data_26, UInt<1>(0h0) node resultdata_is_current_q_27 = eq(UInt<5>(0h1b), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_27 : UInt<256> when resultdata_is_current_q_27 : node _resultdata_data_T_54 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_55 = dshr(Queue4_L2RespInternal_27.io.deq.bits.data, _resultdata_data_T_54) connect resultdata_data_27, _resultdata_data_T_55 else : connect resultdata_data_27, UInt<1>(0h0) node resultdata_is_current_q_28 = eq(UInt<5>(0h1c), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_28 : UInt<256> when resultdata_is_current_q_28 : node _resultdata_data_T_56 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_57 = dshr(Queue4_L2RespInternal_28.io.deq.bits.data, _resultdata_data_T_56) connect resultdata_data_28, _resultdata_data_T_57 else : connect resultdata_data_28, UInt<1>(0h0) node resultdata_is_current_q_29 = eq(UInt<5>(0h1d), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_29 : UInt<256> when resultdata_is_current_q_29 : node _resultdata_data_T_58 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_59 = dshr(Queue4_L2RespInternal_29.io.deq.bits.data, _resultdata_data_T_58) connect resultdata_data_29, _resultdata_data_T_59 else : connect resultdata_data_29, UInt<1>(0h0) node resultdata_is_current_q_30 = eq(UInt<5>(0h1e), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_30 : UInt<256> when resultdata_is_current_q_30 : node _resultdata_data_T_60 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_61 = dshr(Queue4_L2RespInternal_30.io.deq.bits.data, _resultdata_data_T_60) connect resultdata_data_30, _resultdata_data_T_61 else : connect resultdata_data_30, UInt<1>(0h0) node resultdata_is_current_q_31 = eq(UInt<5>(0h1f), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_31 : UInt<256> when resultdata_is_current_q_31 : node _resultdata_data_T_62 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_63 = dshr(Queue4_L2RespInternal_31.io.deq.bits.data, _resultdata_data_T_62) connect resultdata_data_31, _resultdata_data_T_63 else : connect resultdata_data_31, UInt<1>(0h0) node _resultdata_T = or(resultdata_data, resultdata_data_1) node _resultdata_T_1 = or(_resultdata_T, resultdata_data_2) node _resultdata_T_2 = or(_resultdata_T_1, resultdata_data_3) node _resultdata_T_3 = or(_resultdata_T_2, resultdata_data_4) node _resultdata_T_4 = or(_resultdata_T_3, resultdata_data_5) node _resultdata_T_5 = or(_resultdata_T_4, resultdata_data_6) node _resultdata_T_6 = or(_resultdata_T_5, resultdata_data_7) node _resultdata_T_7 = or(_resultdata_T_6, resultdata_data_8) node _resultdata_T_8 = or(_resultdata_T_7, resultdata_data_9) node _resultdata_T_9 = or(_resultdata_T_8, resultdata_data_10) node _resultdata_T_10 = or(_resultdata_T_9, resultdata_data_11) node _resultdata_T_11 = or(_resultdata_T_10, resultdata_data_12) node _resultdata_T_12 = or(_resultdata_T_11, resultdata_data_13) node _resultdata_T_13 = or(_resultdata_T_12, resultdata_data_14) node _resultdata_T_14 = or(_resultdata_T_13, resultdata_data_15) node _resultdata_T_15 = or(_resultdata_T_14, resultdata_data_16) node _resultdata_T_16 = or(_resultdata_T_15, resultdata_data_17) node _resultdata_T_17 = or(_resultdata_T_16, resultdata_data_18) node _resultdata_T_18 = or(_resultdata_T_17, resultdata_data_19) node _resultdata_T_19 = or(_resultdata_T_18, resultdata_data_20) node _resultdata_T_20 = or(_resultdata_T_19, resultdata_data_21) node _resultdata_T_21 = or(_resultdata_T_20, resultdata_data_22) node _resultdata_T_22 = or(_resultdata_T_21, resultdata_data_23) node _resultdata_T_23 = or(_resultdata_T_22, resultdata_data_24) node _resultdata_T_24 = or(_resultdata_T_23, resultdata_data_25) node _resultdata_T_25 = or(_resultdata_T_24, resultdata_data_26) node _resultdata_T_26 = or(_resultdata_T_25, resultdata_data_27) node _resultdata_T_27 = or(_resultdata_T_26, resultdata_data_28) node _resultdata_T_28 = or(_resultdata_T_27, resultdata_data_29) node _resultdata_T_29 = or(_resultdata_T_28, resultdata_data_30) node resultdata = or(_resultdata_T_29, resultdata_data_31) connect response_output.bits.data, resultdata node _response_output_valid_T = and(queueValid, outstanding_req_addr.io.deq.valid) connect response_output.valid, _response_output_valid_T node _outstanding_req_addr_io_deq_ready_T = and(queueValid, response_output.ready) connect outstanding_req_addr.io.deq.ready, _outstanding_req_addr_io_deq_ready_T node _T_159 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_160 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) connect Queue4_L2RespInternal.io.deq.ready, _T_161 node _T_162 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_163 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h1)) node _T_164 = and(_T_162, _T_163) connect Queue4_L2RespInternal_1.io.deq.ready, _T_164 node _T_165 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_166 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h2)) node _T_167 = and(_T_165, _T_166) connect Queue4_L2RespInternal_2.io.deq.ready, _T_167 node _T_168 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_169 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h3)) node _T_170 = and(_T_168, _T_169) connect Queue4_L2RespInternal_3.io.deq.ready, _T_170 node _T_171 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_172 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h4)) node _T_173 = and(_T_171, _T_172) connect Queue4_L2RespInternal_4.io.deq.ready, _T_173 node _T_174 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_175 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h5)) node _T_176 = and(_T_174, _T_175) connect Queue4_L2RespInternal_5.io.deq.ready, _T_176 node _T_177 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_178 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h6)) node _T_179 = and(_T_177, _T_178) connect Queue4_L2RespInternal_6.io.deq.ready, _T_179 node _T_180 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_181 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h7)) node _T_182 = and(_T_180, _T_181) connect Queue4_L2RespInternal_7.io.deq.ready, _T_182 node _T_183 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_184 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0h8)) node _T_185 = and(_T_183, _T_184) connect Queue4_L2RespInternal_8.io.deq.ready, _T_185 node _T_186 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_187 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0h9)) node _T_188 = and(_T_186, _T_187) connect Queue4_L2RespInternal_9.io.deq.ready, _T_188 node _T_189 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_190 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0ha)) node _T_191 = and(_T_189, _T_190) connect Queue4_L2RespInternal_10.io.deq.ready, _T_191 node _T_192 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_193 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hb)) node _T_194 = and(_T_192, _T_193) connect Queue4_L2RespInternal_11.io.deq.ready, _T_194 node _T_195 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_196 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hc)) node _T_197 = and(_T_195, _T_196) connect Queue4_L2RespInternal_12.io.deq.ready, _T_197 node _T_198 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_199 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hd)) node _T_200 = and(_T_198, _T_199) connect Queue4_L2RespInternal_13.io.deq.ready, _T_200 node _T_201 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_202 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0he)) node _T_203 = and(_T_201, _T_202) connect Queue4_L2RespInternal_14.io.deq.ready, _T_203 node _T_204 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_205 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hf)) node _T_206 = and(_T_204, _T_205) connect Queue4_L2RespInternal_15.io.deq.ready, _T_206 node _T_207 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_208 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h10)) node _T_209 = and(_T_207, _T_208) connect Queue4_L2RespInternal_16.io.deq.ready, _T_209 node _T_210 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_211 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h11)) node _T_212 = and(_T_210, _T_211) connect Queue4_L2RespInternal_17.io.deq.ready, _T_212 node _T_213 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_214 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h12)) node _T_215 = and(_T_213, _T_214) connect Queue4_L2RespInternal_18.io.deq.ready, _T_215 node _T_216 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_217 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h13)) node _T_218 = and(_T_216, _T_217) connect Queue4_L2RespInternal_19.io.deq.ready, _T_218 node _T_219 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_220 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h14)) node _T_221 = and(_T_219, _T_220) connect Queue4_L2RespInternal_20.io.deq.ready, _T_221 node _T_222 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_223 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h15)) node _T_224 = and(_T_222, _T_223) connect Queue4_L2RespInternal_21.io.deq.ready, _T_224 node _T_225 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_226 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h16)) node _T_227 = and(_T_225, _T_226) connect Queue4_L2RespInternal_22.io.deq.ready, _T_227 node _T_228 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_229 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h17)) node _T_230 = and(_T_228, _T_229) connect Queue4_L2RespInternal_23.io.deq.ready, _T_230 node _T_231 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_232 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h18)) node _T_233 = and(_T_231, _T_232) connect Queue4_L2RespInternal_24.io.deq.ready, _T_233 node _T_234 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_235 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h19)) node _T_236 = and(_T_234, _T_235) connect Queue4_L2RespInternal_25.io.deq.ready, _T_236 node _T_237 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_238 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1a)) node _T_239 = and(_T_237, _T_238) connect Queue4_L2RespInternal_26.io.deq.ready, _T_239 node _T_240 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_241 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1b)) node _T_242 = and(_T_240, _T_241) connect Queue4_L2RespInternal_27.io.deq.ready, _T_242 node _T_243 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_244 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1c)) node _T_245 = and(_T_243, _T_244) connect Queue4_L2RespInternal_28.io.deq.ready, _T_245 node _T_246 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_247 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1d)) node _T_248 = and(_T_246, _T_247) connect Queue4_L2RespInternal_29.io.deq.ready, _T_248 node _T_249 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_250 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1e)) node _T_251 = and(_T_249, _T_250) connect Queue4_L2RespInternal_30.io.deq.ready, _T_251 node _T_252 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_253 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1f)) node _T_254 = and(_T_252, _T_253) connect Queue4_L2RespInternal_31.io.deq.ready, _T_254 node _T_255 = and(masterNodeOut.d.ready, masterNodeOut.d.valid) when _T_255 : node opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) when opdata : regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_21 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n", masterNodeOut.d.bits.data, global_memop_ackd, masterNodeOut.d.bits.source) : printf_22 else : regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_23 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: resp(write) opnum: %d, gettag: %d\n", global_memop_ackd, masterNodeOut.d.bits.source) : printf_24 node _T_264 = and(response_output.ready, response_output.valid) when _T_264 : regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_25 node _T_267 = asUInt(reset) node _T_268 = eq(_T_267, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "[raw_block_reader] L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n", resultdata, global_memop_resp_to_user, outstanding_req_addr.io.deq.bits.tag) : printf_26 node _T_269 = and(response_latency_injection_q.io.deq.ready, response_latency_injection_q.io.deq.valid) when _T_269 : node _global_memop_ackd_T = add(global_memop_ackd, UInt<1>(0h1)) node _global_memop_ackd_T_1 = tail(_global_memop_ackd_T, 1) connect global_memop_ackd, _global_memop_ackd_T_1 node _T_270 = and(response_output.ready, response_output.valid) when _T_270 : node _global_memop_resp_to_user_T = add(global_memop_resp_to_user, UInt<1>(0h1)) node _global_memop_resp_to_user_T_1 = tail(_global_memop_resp_to_user_T, 1) connect global_memop_resp_to_user, _global_memop_resp_to_user_T_1 extmodule plusarg_reader_144 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_145 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module L2MemHelperLatencyInjection_14( // @[L2MemHelperLatencyInjection.scala:29:7] input clock, // @[L2MemHelperLatencyInjection.scala:29:7] input reset, // @[L2MemHelperLatencyInjection.scala:29:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_master_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_master_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [255:0] auto_master_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_master_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [255:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_userif_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [70:0] io_userif_req_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_resp_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [255:0] io_userif_resp_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_no_memops_inflight, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_latency_inject_cycles, // @[L2MemHelperLatencyInjection.scala:33:14] input io_sfence, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [26:0] io_ptw_req_bits_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_bits_bits_need_gpa, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_ptw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_final, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hx, // @[L2MemHelperLatencyInjection.scala:33:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_d, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_g, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_u, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_r, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_level, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_homogeneous, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_is_pte, // @[L2MemHelperLatencyInjection.scala:33:14] input [3:0] io_ptw_ptbr_mode, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_ptbr_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_status_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spvp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_gstatus_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_ptw_gstatus_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_ptw_gstatus_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_uie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_0_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_0_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_1_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_1_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_2_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_2_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_3_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_3_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_4_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_4_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_5_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_5_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_6_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_6_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_7_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_7_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_status_bits_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_status_bits_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_uxl, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd_rv32, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_status_bits_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_xs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_uie // @[L2MemHelperLatencyInjection.scala:33:14] ); wire _response_latency_injection_q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:245:44] wire [4:0] _response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44] wire [255:0] _response_latency_injection_q_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:245:44] wire _Queue4_L2RespInternal_31_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_31_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_31_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_30_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_29_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_28_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_27_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_26_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_25_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_24_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_23_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_22_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_21_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_20_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_19_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_18_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_17_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_16_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_15_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_14_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_13_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_12_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_11_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_10_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_9_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_8_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_7_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_6_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_5_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_4_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_3_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_2_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_1_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _request_latency_injection_q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:151:43] wire _tags_for_issue_Q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:94:32] wire _tags_for_issue_Q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:94:32] wire [4:0] _tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32] wire _outstanding_req_addr_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:91:36] wire _outstanding_req_addr_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_addrindex; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36] wire _tlb_io_req_ready; // @[L2MemHelperLatencyInjection.scala:68:19] wire _tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19] wire [31:0] _tlb_io_resp_paddr; // @[L2MemHelperLatencyInjection.scala:68:19] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_valid_0 = io_userif_req_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [70:0] io_userif_req_bits_addr_0 = io_userif_req_bits_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_ready_0 = io_userif_resp_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_latency_inject_cycles_0 = io_latency_inject_cycles; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_sfence_0 = io_sfence; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[L2MemHelperLatencyInjection.scala:29:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_valid_0 = io_status_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_debug_0 = io_status_bits_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_cease_0 = io_status_bits_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_wfi_0 = io_status_bits_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_status_bits_isa_0 = io_status_bits_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_dprv_0 = io_status_bits_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_dv_0 = io_status_bits_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_prv_0 = io_status_bits_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_v_0 = io_status_bits_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_0 = io_status_bits_sd; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_status_bits_zero2_0 = io_status_bits_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpv_0 = io_status_bits_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_gva_0 = io_status_bits_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mbe_0 = io_status_bits_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sbe_0 = io_status_bits_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_sxl_0 = io_status_bits_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_uxl_0 = io_status_bits_uxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_rv32_0 = io_status_bits_sd_rv32; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_status_bits_zero1_0 = io_status_bits_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tsr_0 = io_status_bits_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tw_0 = io_status_bits_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tvm_0 = io_status_bits_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mxr_0 = io_status_bits_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sum_0 = io_status_bits_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mprv_0 = io_status_bits_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_xs_0 = io_status_bits_xs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_fs_0 = io_status_bits_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_mpp_0 = io_status_bits_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_vs_0 = io_status_bits_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spp_0 = io_status_bits_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpie_0 = io_status_bits_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_ube_0 = io_status_bits_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spie_0 = io_status_bits_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_upie_0 = io_status_bits_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mie_0 = io_status_bits_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_hie_0 = io_status_bits_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sie_0 = io_status_bits_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_uie_0 = io_status_bits_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire _printf_T = reset; // @[annotations.scala:102:49] wire _printf_T_2 = reset; // @[annotations.scala:102:49] wire io_userif_req_bits_cmd = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_ube = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_upie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_hie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_uie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtw = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_hu = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire request_input_bits_cmd = 1'h0; // @[L2MemHelperLatencyInjection.scala:44:27] wire bundle_corrupt = 1'h0; // @[Edges.scala:460:17] wire a_mask_sub_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_T_125 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_131 = 1'h0; // @[Parameters.scala:684:54] wire bundle_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire a_mask_sub_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_acc_T_16 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_17 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_18 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_19 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_20 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_21 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_22 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_23 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_24 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_25 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_26 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_27 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_28 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_29 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_30 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_31 = 1'h0; // @[Misc.scala:215:38] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_valid = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_8_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_9_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_10_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_11_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_12_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_13_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_14_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_15_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_64 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_65 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_66 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_73 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_74 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_75 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_76 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_8_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_9_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_10_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_11_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_12_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_13_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_14_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_15_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc_32 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_33 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_34 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_35 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_36 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_37 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_38 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_39 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_40 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_41 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_42 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_43 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_44 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_45 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_46 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_47 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_48 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_49 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_50 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_51 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_52 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_53 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_54 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_55 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_56 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_57 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_58 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_59 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_60 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_61 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_62 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_63 = 1'h1; // @[Misc.scala:215:29] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] a_mask_lo_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_ptw_status_vs = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] _a_mask_sizeOH_T_2 = 5'h0; // @[OneHot.scala:65:27] wire [4:0] _a_mask_sizeOH_T_5 = 5'h0; // @[OneHot.scala:65:27] wire [2:0] io_userif_req_bits_size = 3'h5; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] request_input_bits_size = 3'h5; // @[L2MemHelperLatencyInjection.scala:44:27] wire [2:0] a_mask_sizeOH_shiftAmount = 3'h5; // @[OneHot.scala:64:49] wire [2:0] a_mask_sizeOH_shiftAmount_1 = 3'h5; // @[OneHot.scala:64:49] wire [255:0] io_userif_req_bits_data = 256'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] request_input_bits_data = 256'h0; // @[L2MemHelperLatencyInjection.scala:44:27] wire [255:0] bundle_data = 256'h0; // @[Edges.scala:460:17] wire [1:0] io_ptw_status_sxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] bundle_mask = 32'hFFFFFFFF; // @[Edges.scala:460:17] wire [31:0] _a_mask_T = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [31:0] bundle_1_mask = 32'hFFFFFFFF; // @[Edges.scala:480:17] wire [31:0] _a_mask_T_1 = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_lo = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_hi = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_lo_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_hi_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [4:0] a_mask_sizeOH = 5'h1; // @[Misc.scala:202:81] wire [4:0] a_mask_sizeOH_1 = 5'h1; // @[Misc.scala:202:81] wire [7:0] _a_mask_sizeOH_T_1 = 8'h20; // @[OneHot.scala:65:12] wire [7:0] _a_mask_sizeOH_T_4 = 8'h20; // @[OneHot.scala:65:12] wire [4:0] _a_mask_sizeOH_T = 5'h5; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T = 5'h5; // @[OneHot.scala:64:31] wire [4:0] _a_mask_sizeOH_T_3 = 5'h5; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T_1 = 5'h5; // @[OneHot.scala:64:31] wire [3:0] bundle_size = 4'h5; // @[Edges.scala:460:17] wire [3:0] bundle_1_size = 4'h5; // @[Edges.scala:480:17] wire [2:0] bundle_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] bundle_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_1_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_opcode = 3'h4; // @[Edges.scala:460:17] wire [70:0] addr_mask_check = 71'h1F; // @[L2MemHelperLatencyInjection.scala:108:64] wire [71:0] _addr_mask_check_T_1 = 72'h1F; // @[L2MemHelperLatencyInjection.scala:108:64] wire [70:0] _addr_mask_check_T = 71'h20; // @[L2MemHelperLatencyInjection.scala:108:36] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire request_input_ready; // @[L2MemHelperLatencyInjection.scala:44:27] wire request_input_valid = io_userif_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [70:0] request_input_bits_addr = io_userif_req_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire response_output_ready = io_userif_resp_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire response_output_valid; // @[L2MemHelperLatencyInjection.scala:53:29] wire [255:0] response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:53:29] wire _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:128:57] wire [2:0] auto_master_out_a_bits_opcode_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_a_bits_param_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_a_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_a_bits_source_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_address_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_mask_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_a_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_bits_corrupt_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_resp_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_no_memops_inflight_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_opcode_0 = masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_param_0 = masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_size_0 = masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_source_0 = masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_mask_0 = masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_data_0 = masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_corrupt_0 = masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_master_out_d_ready_0 = masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire _request_input_ready_T_4; // @[Misc.scala:26:53] assign io_userif_req_ready_0 = request_input_ready; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire _response_output_valid_T; // @[Misc.scala:26:53] assign io_userif_resp_valid_0 = response_output_valid; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire [255:0] resultdata; // @[L2MemHelperLatencyInjection.scala:307:15] assign io_userif_resp_bits_data_0 = response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] reg status_debug; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_cease; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_wfi; // @[L2MemHelperLatencyInjection.scala:62:19] reg [31:0] status_isa; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_dprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_dv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_prv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_v; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd; // @[L2MemHelperLatencyInjection.scala:62:19] reg [22:0] status_zero2; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_gva; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_sxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_uxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd_rv32; // @[L2MemHelperLatencyInjection.scala:62:19] reg [7:0] status_zero1; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tsr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tw; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tvm; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mxr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sum; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_xs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_fs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_mpp; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_vs; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spp; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_ube; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_upie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_hie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_uie; // @[L2MemHelperLatencyInjection.scala:62:19] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _tlb_ready_T = ~_tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19, :74:39] wire tlb_ready = _tlb_io_req_ready & _tlb_ready_T; // @[L2MemHelperLatencyInjection.scala:68:19, :74:{36,39}] reg [5:0] tags_init_reg; // @[L2MemHelperLatencyInjection.scala:98:30] wire _T_4 = tags_init_reg != 6'h20; // @[L2MemHelperLatencyInjection.scala:98:30, :99:23] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] wire [6:0] _tags_init_reg_T = {1'h0, tags_init_reg} + 7'h1; // @[L2MemHelperLatencyInjection.scala:98:30, :104:38] wire [5:0] _tags_init_reg_T_1 = _tags_init_reg_T[5:0]; // @[L2MemHelperLatencyInjection.scala:104:38] wire _assertcheck_T = ~request_input_valid; // @[L2MemHelperLatencyInjection.scala:44:27, :109:30] wire [70:0] _assertcheck_T_1 = request_input_bits_addr & 71'h1F; // @[L2MemHelperLatencyInjection.scala:44:27, :109:81] wire _assertcheck_T_2 = _assertcheck_T_1 == 71'h0; // @[L2MemHelperLatencyInjection.scala:109:{81,100}] wire _assertcheck_T_3 = _assertcheck_T | _assertcheck_T_2; // @[L2MemHelperLatencyInjection.scala:109:{30,52,100}] reg assertcheck; // @[L2MemHelperLatencyInjection.scala:109:28] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] global_memop_accepted; // @[L2MemHelperLatencyInjection.scala:117:38] wire [64:0] _global_memop_accepted_T = {1'h0, global_memop_accepted} + 65'h1; // @[L2MemHelperLatencyInjection.scala:117:38, :119:52] wire [63:0] _global_memop_accepted_T_1 = _global_memop_accepted_T[63:0]; // @[L2MemHelperLatencyInjection.scala:119:52] reg [63:0] global_memop_sent; // @[L2MemHelperLatencyInjection.scala:122:34] reg [63:0] global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:124:34] reg [63:0] global_memop_resp_to_user; // @[L2MemHelperLatencyInjection.scala:126:42] assign _io_userif_no_memops_inflight_T = global_memop_accepted == global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:117:38, :124:34, :128:57] assign io_userif_no_memops_inflight_0 = _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:29:7, :128:57] wire [64:0] _GEN = {1'h0, global_memop_sent}; // @[L2MemHelperLatencyInjection.scala:122:34, :130:54] wire [64:0] _GEN_0 = {1'h0, global_memop_ackd}; // @[L2MemHelperLatencyInjection.scala:124:34, :130:54] wire [64:0] _GEN_1 = _GEN - _GEN_0; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:130:54] assign _free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _assert_free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:131:61] assign _assert_free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54, :131:61] wire [63:0] _free_outstanding_op_slots_T_1 = _free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:130:54] wire free_outstanding_op_slots = _free_outstanding_op_slots_T_1 < 64'h20; // @[L2MemHelperLatencyInjection.scala:130:{54,75}] wire [63:0] _assert_free_outstanding_op_slots_T_1 = _assert_free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:131:61] wire assert_free_outstanding_op_slots = _assert_free_outstanding_op_slots_T_1 < 64'h21; // @[L2MemHelperLatencyInjection.scala:131:{61,82}] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] wire [64:0] _global_memop_sent_T = _GEN + 65'h1; // @[L2MemHelperLatencyInjection.scala:130:54, :140:44] wire [63:0] _global_memop_sent_T_1 = _global_memop_sent_T[63:0]; // @[L2MemHelperLatencyInjection.scala:140:44] reg [63:0] cur_cycle; // @[L2MemHelperLatencyInjection.scala:146:26] wire [64:0] _cur_cycle_T = {1'h0, cur_cycle} + 65'h1; // @[L2MemHelperLatencyInjection.scala:146:26, :147:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[L2MemHelperLatencyInjection.scala:147:26] wire [31:0] _GEN_2 = {_tlb_io_resp_paddr[31:14], _tlb_io_resp_paddr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_4; // @[Parameters.scala:137:31] assign _legal_T_4 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _legal_T_67; // @[Parameters.scala:137:31] assign _legal_T_67 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_62 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [31:0] _legal_T_14; // @[Parameters.scala:137:31] wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_16 = _legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46] wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {_tlb_io_resp_paddr[31:17], _tlb_io_resp_paddr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_19; // @[Parameters.scala:137:31] assign _legal_T_19 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _legal_T_24; // @[Parameters.scala:137:31] assign _legal_T_24 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _legal_T_126; // @[Parameters.scala:137:31] assign _legal_T_126 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_21 = _legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46] wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_26 = _legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46] wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_29; // @[Parameters.scala:137:31] assign _legal_T_29 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_87; // @[Parameters.scala:137:31] assign _legal_T_87 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_31 = _legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46] wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_5 = {_tlb_io_resp_paddr[31:28], _tlb_io_resp_paddr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_34; // @[Parameters.scala:137:31] assign _legal_T_34 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_39; // @[Parameters.scala:137:31] assign _legal_T_39 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_97; // @[Parameters.scala:137:31] assign _legal_T_97 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_102; // @[Parameters.scala:137:31] assign _legal_T_102 = _GEN_5; // @[Parameters.scala:137:31] wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_36 = _legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46] wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_41 = _legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46] wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_6 = {_tlb_io_resp_paddr[31:29], _tlb_io_resp_paddr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_44; // @[Parameters.scala:137:31] assign _legal_T_44 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_107; // @[Parameters.scala:137:31] assign _legal_T_107 = _GEN_6; // @[Parameters.scala:137:31] wire [32:0] _legal_T_45 = {1'h0, _legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_46 = _legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_47 = _legal_T_46; // @[Parameters.scala:137:46] wire _legal_T_48 = _legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_7 = _tlb_io_resp_paddr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _legal_T_49; // @[Parameters.scala:137:31] assign _legal_T_49 = _GEN_7; // @[Parameters.scala:137:31] wire [31:0] _legal_T_112; // @[Parameters.scala:137:31] assign _legal_T_112 = _GEN_7; // @[Parameters.scala:137:31] wire [32:0] _legal_T_50 = {1'h0, _legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_51 = _legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_52 = _legal_T_51; // @[Parameters.scala:137:46] wire _legal_T_53 = _legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_54 = _legal_T_18 | _legal_T_23; // @[Parameters.scala:685:42] wire _legal_T_55 = _legal_T_54 | _legal_T_28; // @[Parameters.scala:685:42] wire _legal_T_56 = _legal_T_55 | _legal_T_33; // @[Parameters.scala:685:42] wire _legal_T_57 = _legal_T_56 | _legal_T_38; // @[Parameters.scala:685:42] wire _legal_T_58 = _legal_T_57 | _legal_T_43; // @[Parameters.scala:685:42] wire _legal_T_59 = _legal_T_58 | _legal_T_48; // @[Parameters.scala:685:42] wire _legal_T_60 = _legal_T_59 | _legal_T_53; // @[Parameters.scala:685:42] wire _legal_T_61 = _legal_T_60; // @[Parameters.scala:684:54, :685:42] wire legal = _legal_T_62 | _legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [4:0] bundle_source; // @[Edges.scala:460:17] wire [31:0] bundle_address; // @[Edges.scala:460:17] wire a_mask_sub_sub_sub_sub_bit = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_bit = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_2_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_3_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_bit = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_bit_1 = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_1_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_2_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_3_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_4_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_5_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_6_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_7_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_bit = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_bit_1 = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_4_2 = a_mask_sub_sub_2_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_5_2 = a_mask_sub_sub_2_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_6_2 = a_mask_sub_sub_3_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_7_2 = a_mask_sub_sub_3_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_8_2 = a_mask_sub_sub_4_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_9_2 = a_mask_sub_sub_4_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_10_2 = a_mask_sub_sub_5_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_11_2 = a_mask_sub_sub_5_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_12_2 = a_mask_sub_sub_6_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_13_2 = a_mask_sub_sub_6_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_14_2 = a_mask_sub_sub_7_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_15_2 = a_mask_sub_sub_7_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_bit = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_bit_1 = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_eq; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_8 = a_mask_sub_4_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_8 = a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_9 = a_mask_sub_4_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_9 = a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_10 = a_mask_sub_5_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_10 = a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_11 = a_mask_sub_5_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_11 = a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_12 = a_mask_sub_6_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_12 = a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_13 = a_mask_sub_6_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_13 = a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_14 = a_mask_sub_7_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_14 = a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_15 = a_mask_sub_7_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_15 = a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_16 = a_mask_sub_8_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_16 = a_mask_eq_16; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_17 = a_mask_sub_8_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_17 = a_mask_eq_17; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_18 = a_mask_sub_9_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_18 = a_mask_eq_18; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_19 = a_mask_sub_9_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_19 = a_mask_eq_19; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_20 = a_mask_sub_10_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_20 = a_mask_eq_20; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_21 = a_mask_sub_10_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_21 = a_mask_eq_21; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_22 = a_mask_sub_11_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_22 = a_mask_eq_22; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_23 = a_mask_sub_11_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_23 = a_mask_eq_23; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_24 = a_mask_sub_12_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_24 = a_mask_eq_24; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_25 = a_mask_sub_12_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_25 = a_mask_eq_25; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_26 = a_mask_sub_13_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_26 = a_mask_eq_26; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_27 = a_mask_sub_13_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_27 = a_mask_eq_27; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_28 = a_mask_sub_14_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_28 = a_mask_eq_28; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_29 = a_mask_sub_14_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_29 = a_mask_eq_29; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_30 = a_mask_sub_15_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_30 = a_mask_eq_30; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_31 = a_mask_sub_15_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_31 = a_mask_eq_31; // @[Misc.scala:214:27, :215:38] wire [510:0] _T_31 = 511'h0 << {503'h0, request_input_bits_addr[4:0], 3'h0}; // @[L2MemHelperLatencyInjection.scala:44:27, :172:{58,86}] wire [32:0] _legal_T_68 = {1'h0, _legal_T_67}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_69 = _legal_T_68 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_70 = _legal_T_69; // @[Parameters.scala:137:46] wire _legal_T_71 = _legal_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_72 = _legal_T_71; // @[Parameters.scala:684:54] wire _legal_T_132 = _legal_T_72; // @[Parameters.scala:684:54, :686:26] wire [31:0] _legal_T_77; // @[Parameters.scala:137:31] wire [32:0] _legal_T_78 = {1'h0, _legal_T_77}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_79 = _legal_T_78 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_80 = _legal_T_79; // @[Parameters.scala:137:46] wire _legal_T_81 = _legal_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_82 = {_tlb_io_resp_paddr[31:21], _tlb_io_resp_paddr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_83 = {1'h0, _legal_T_82}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_84 = _legal_T_83 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_85 = _legal_T_84; // @[Parameters.scala:137:46] wire _legal_T_86 = _legal_T_85 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_88 = {1'h0, _legal_T_87}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_89 = _legal_T_88 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_90 = _legal_T_89; // @[Parameters.scala:137:46] wire _legal_T_91 = _legal_T_90 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_92 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_93 = {1'h0, _legal_T_92}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_94 = _legal_T_93 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_95 = _legal_T_94; // @[Parameters.scala:137:46] wire _legal_T_96 = _legal_T_95 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_98 = {1'h0, _legal_T_97}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_99 = _legal_T_98 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_100 = _legal_T_99; // @[Parameters.scala:137:46] wire _legal_T_101 = _legal_T_100 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_103 = {1'h0, _legal_T_102}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_104 = _legal_T_103 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_105 = _legal_T_104; // @[Parameters.scala:137:46] wire _legal_T_106 = _legal_T_105 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_108 = {1'h0, _legal_T_107}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_109 = _legal_T_108 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_110 = _legal_T_109; // @[Parameters.scala:137:46] wire _legal_T_111 = _legal_T_110 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_113 = {1'h0, _legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_114 = _legal_T_113 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_115 = _legal_T_114; // @[Parameters.scala:137:46] wire _legal_T_116 = _legal_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_117 = _legal_T_81 | _legal_T_86; // @[Parameters.scala:685:42] wire _legal_T_118 = _legal_T_117 | _legal_T_91; // @[Parameters.scala:685:42] wire _legal_T_119 = _legal_T_118 | _legal_T_96; // @[Parameters.scala:685:42] wire _legal_T_120 = _legal_T_119 | _legal_T_101; // @[Parameters.scala:685:42] wire _legal_T_121 = _legal_T_120 | _legal_T_106; // @[Parameters.scala:685:42] wire _legal_T_122 = _legal_T_121 | _legal_T_111; // @[Parameters.scala:685:42] wire _legal_T_123 = _legal_T_122 | _legal_T_116; // @[Parameters.scala:685:42] wire _legal_T_124 = _legal_T_123; // @[Parameters.scala:684:54, :685:42] wire [32:0] _legal_T_127 = {1'h0, _legal_T_126}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_128 = _legal_T_127 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_129 = _legal_T_128; // @[Parameters.scala:137:46] wire _legal_T_130 = _legal_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_133 = _legal_T_132 | _legal_T_124; // @[Parameters.scala:684:54, :686:26] wire legal_1 = _legal_T_133; // @[Parameters.scala:686:26] wire [4:0] bundle_1_source; // @[Edges.scala:480:17] wire [31:0] bundle_1_address; // @[Edges.scala:480:17] wire [255:0] bundle_1_data; // @[Edges.scala:480:17] wire a_mask_sub_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_2_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_3_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_nbit_1 = ~a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_1_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_2_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_3_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_4_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_5_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_6_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_7_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_1_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_2_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_3_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_4_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_5_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_6_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_7_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_8_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_9_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_10_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_11_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_12_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_13_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_14_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_15_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_eq_32 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_32 = a_mask_eq_32; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_33 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_33 = a_mask_eq_33; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_34 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_34 = a_mask_eq_34; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_35 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_35 = a_mask_eq_35; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_36 = a_mask_sub_2_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_36 = a_mask_eq_36; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_37 = a_mask_sub_2_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_37 = a_mask_eq_37; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_38 = a_mask_sub_3_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_38 = a_mask_eq_38; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_39 = a_mask_sub_3_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_39 = a_mask_eq_39; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_40 = a_mask_sub_4_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_40 = a_mask_eq_40; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_41 = a_mask_sub_4_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_41 = a_mask_eq_41; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_42 = a_mask_sub_5_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_42 = a_mask_eq_42; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_43 = a_mask_sub_5_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_43 = a_mask_eq_43; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_44 = a_mask_sub_6_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_44 = a_mask_eq_44; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_45 = a_mask_sub_6_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_45 = a_mask_eq_45; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_46 = a_mask_sub_7_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_46 = a_mask_eq_46; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_47 = a_mask_sub_7_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_47 = a_mask_eq_47; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_48 = a_mask_sub_8_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_48 = a_mask_eq_48; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_49 = a_mask_sub_8_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_49 = a_mask_eq_49; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_50 = a_mask_sub_9_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_50 = a_mask_eq_50; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_51 = a_mask_sub_9_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_51 = a_mask_eq_51; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_52 = a_mask_sub_10_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_52 = a_mask_eq_52; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_53 = a_mask_sub_10_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_53 = a_mask_eq_53; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_54 = a_mask_sub_11_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_54 = a_mask_eq_54; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_55 = a_mask_sub_11_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_55 = a_mask_eq_55; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_56 = a_mask_sub_12_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_56 = a_mask_eq_56; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_57 = a_mask_sub_12_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_57 = a_mask_eq_57; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_58 = a_mask_sub_13_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_58 = a_mask_eq_58; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_59 = a_mask_sub_13_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_59 = a_mask_eq_59; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_60 = a_mask_sub_14_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_60 = a_mask_eq_60; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_61 = a_mask_sub_14_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_61 = a_mask_eq_61; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_62 = a_mask_sub_15_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_62 = a_mask_eq_62; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_63 = a_mask_sub_15_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_63 = a_mask_eq_63; // @[Misc.scala:214:27, :215:38] assign bundle_1_data = _T_31[255:0]; // @[Edges.scala:480:17, :489:15] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] wire _current_request_tag_has_response_space_T = _tags_for_issue_Q_io_deq_bits == 5'h0; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_1 = _Queue4_L2RespInternal_io_enq_ready & _current_request_tag_has_response_space_T; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_2 = _tags_for_issue_Q_io_deq_bits == 5'h1; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _current_request_tag_has_response_space_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_4 = _tags_for_issue_Q_io_deq_bits == 5'h2; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _current_request_tag_has_response_space_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_6 = _tags_for_issue_Q_io_deq_bits == 5'h3; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _current_request_tag_has_response_space_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_8 = _tags_for_issue_Q_io_deq_bits == 5'h4; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _current_request_tag_has_response_space_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_10 = _tags_for_issue_Q_io_deq_bits == 5'h5; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _current_request_tag_has_response_space_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_12 = _tags_for_issue_Q_io_deq_bits == 5'h6; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _current_request_tag_has_response_space_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_14 = _tags_for_issue_Q_io_deq_bits == 5'h7; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _current_request_tag_has_response_space_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_16 = _tags_for_issue_Q_io_deq_bits == 5'h8; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _current_request_tag_has_response_space_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_18 = _tags_for_issue_Q_io_deq_bits == 5'h9; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _current_request_tag_has_response_space_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_20 = _tags_for_issue_Q_io_deq_bits == 5'hA; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _current_request_tag_has_response_space_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_22 = _tags_for_issue_Q_io_deq_bits == 5'hB; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _current_request_tag_has_response_space_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_24 = _tags_for_issue_Q_io_deq_bits == 5'hC; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _current_request_tag_has_response_space_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_26 = _tags_for_issue_Q_io_deq_bits == 5'hD; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _current_request_tag_has_response_space_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_28 = _tags_for_issue_Q_io_deq_bits == 5'hE; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _current_request_tag_has_response_space_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_30 = _tags_for_issue_Q_io_deq_bits == 5'hF; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _current_request_tag_has_response_space_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_32 = _tags_for_issue_Q_io_deq_bits == 5'h10; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _current_request_tag_has_response_space_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_34 = _tags_for_issue_Q_io_deq_bits == 5'h11; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _current_request_tag_has_response_space_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_36 = _tags_for_issue_Q_io_deq_bits == 5'h12; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _current_request_tag_has_response_space_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_38 = _tags_for_issue_Q_io_deq_bits == 5'h13; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _current_request_tag_has_response_space_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_40 = _tags_for_issue_Q_io_deq_bits == 5'h14; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _current_request_tag_has_response_space_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_42 = _tags_for_issue_Q_io_deq_bits == 5'h15; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _current_request_tag_has_response_space_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_44 = _tags_for_issue_Q_io_deq_bits == 5'h16; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _current_request_tag_has_response_space_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_46 = _tags_for_issue_Q_io_deq_bits == 5'h17; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _current_request_tag_has_response_space_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_48 = _tags_for_issue_Q_io_deq_bits == 5'h18; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _current_request_tag_has_response_space_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_50 = _tags_for_issue_Q_io_deq_bits == 5'h19; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _current_request_tag_has_response_space_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_52 = _tags_for_issue_Q_io_deq_bits == 5'h1A; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _current_request_tag_has_response_space_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_54 = _tags_for_issue_Q_io_deq_bits == 5'h1B; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _current_request_tag_has_response_space_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_56 = _tags_for_issue_Q_io_deq_bits == 5'h1C; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _current_request_tag_has_response_space_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_58 = _tags_for_issue_Q_io_deq_bits == 5'h1D; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _current_request_tag_has_response_space_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_60 = _tags_for_issue_Q_io_deq_bits == 5'h1E; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _current_request_tag_has_response_space_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_62 = &_tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _current_request_tag_has_response_space_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_64 = _current_request_tag_has_response_space_T_1 | _current_request_tag_has_response_space_T_3; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_65 = _current_request_tag_has_response_space_T_64 | _current_request_tag_has_response_space_T_5; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_66 = _current_request_tag_has_response_space_T_65 | _current_request_tag_has_response_space_T_7; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_67 = _current_request_tag_has_response_space_T_66 | _current_request_tag_has_response_space_T_9; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_68 = _current_request_tag_has_response_space_T_67 | _current_request_tag_has_response_space_T_11; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_69 = _current_request_tag_has_response_space_T_68 | _current_request_tag_has_response_space_T_13; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_70 = _current_request_tag_has_response_space_T_69 | _current_request_tag_has_response_space_T_15; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_71 = _current_request_tag_has_response_space_T_70 | _current_request_tag_has_response_space_T_17; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_72 = _current_request_tag_has_response_space_T_71 | _current_request_tag_has_response_space_T_19; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_73 = _current_request_tag_has_response_space_T_72 | _current_request_tag_has_response_space_T_21; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_74 = _current_request_tag_has_response_space_T_73 | _current_request_tag_has_response_space_T_23; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_75 = _current_request_tag_has_response_space_T_74 | _current_request_tag_has_response_space_T_25; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_76 = _current_request_tag_has_response_space_T_75 | _current_request_tag_has_response_space_T_27; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_77 = _current_request_tag_has_response_space_T_76 | _current_request_tag_has_response_space_T_29; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_78 = _current_request_tag_has_response_space_T_77 | _current_request_tag_has_response_space_T_31; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_79 = _current_request_tag_has_response_space_T_78 | _current_request_tag_has_response_space_T_33; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_80 = _current_request_tag_has_response_space_T_79 | _current_request_tag_has_response_space_T_35; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_81 = _current_request_tag_has_response_space_T_80 | _current_request_tag_has_response_space_T_37; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_82 = _current_request_tag_has_response_space_T_81 | _current_request_tag_has_response_space_T_39; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_83 = _current_request_tag_has_response_space_T_82 | _current_request_tag_has_response_space_T_41; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_84 = _current_request_tag_has_response_space_T_83 | _current_request_tag_has_response_space_T_43; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_85 = _current_request_tag_has_response_space_T_84 | _current_request_tag_has_response_space_T_45; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_86 = _current_request_tag_has_response_space_T_85 | _current_request_tag_has_response_space_T_47; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_87 = _current_request_tag_has_response_space_T_86 | _current_request_tag_has_response_space_T_49; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_88 = _current_request_tag_has_response_space_T_87 | _current_request_tag_has_response_space_T_51; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_89 = _current_request_tag_has_response_space_T_88 | _current_request_tag_has_response_space_T_53; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_90 = _current_request_tag_has_response_space_T_89 | _current_request_tag_has_response_space_T_55; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_91 = _current_request_tag_has_response_space_T_90 | _current_request_tag_has_response_space_T_57; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_92 = _current_request_tag_has_response_space_T_91 | _current_request_tag_has_response_space_T_59; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_93 = _current_request_tag_has_response_space_T_92 | _current_request_tag_has_response_space_T_61; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire current_request_tag_has_response_space = _current_request_tag_has_response_space_T_93 | _current_request_tag_has_response_space_T_63; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire [70:0] _outstanding_req_addr_io_enq_bits_addrindex_T = {66'h0, request_input_bits_addr[4:0]}; // @[L2MemHelperLatencyInjection.scala:44:27, :200:73] wire _request_latency_injection_q_io_enq_valid_T = request_input_valid & tlb_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_1 = _request_latency_injection_q_io_enq_valid_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_2 = _request_latency_injection_q_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_3 = _request_latency_injection_q_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_4 = _request_latency_injection_q_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _request_input_ready_T = _request_latency_injection_q_io_enq_ready & tlb_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_1 = _request_input_ready_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_2 = _request_input_ready_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_input_ready_T_3 = _request_input_ready_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] assign _request_input_ready_T_4 = _request_input_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] assign request_input_ready = _request_input_ready_T_4; // @[Misc.scala:26:53] wire _T_45 = request_input_valid & _request_latency_injection_q_io_enq_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T; // @[Misc.scala:26:53] assign _outstanding_req_addr_io_enq_valid_T = _T_45; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T; // @[Misc.scala:26:53] assign _tags_for_issue_Q_io_deq_ready_T = _T_45; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_1 = _outstanding_req_addr_io_enq_valid_T & tlb_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_2 = _outstanding_req_addr_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_3 = _outstanding_req_addr_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_4 = _outstanding_req_addr_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_1 = _tags_for_issue_Q_io_deq_ready_T & tlb_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_2 = _tags_for_issue_Q_io_deq_ready_T_1 & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_3 = _tags_for_issue_Q_io_deq_ready_T_2 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_4 = _tags_for_issue_Q_io_deq_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:26:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:26:33, :27:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:27:38] wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49] wire _printf_T_3 = ~_printf_T_2; // @[annotations.scala:102:49] wire _selectQready_T = _response_latency_injection_q_io_deq_bits_source == 5'h0; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_1 = _Queue4_L2RespInternal_io_enq_ready & _selectQready_T; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_2 = _response_latency_injection_q_io_deq_bits_source == 5'h1; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _selectQready_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_4 = _response_latency_injection_q_io_deq_bits_source == 5'h2; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _selectQready_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_6 = _response_latency_injection_q_io_deq_bits_source == 5'h3; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _selectQready_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_8 = _response_latency_injection_q_io_deq_bits_source == 5'h4; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _selectQready_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_10 = _response_latency_injection_q_io_deq_bits_source == 5'h5; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _selectQready_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_12 = _response_latency_injection_q_io_deq_bits_source == 5'h6; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _selectQready_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_14 = _response_latency_injection_q_io_deq_bits_source == 5'h7; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _selectQready_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_16 = _response_latency_injection_q_io_deq_bits_source == 5'h8; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _selectQready_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_18 = _response_latency_injection_q_io_deq_bits_source == 5'h9; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _selectQready_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_20 = _response_latency_injection_q_io_deq_bits_source == 5'hA; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _selectQready_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_22 = _response_latency_injection_q_io_deq_bits_source == 5'hB; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _selectQready_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_24 = _response_latency_injection_q_io_deq_bits_source == 5'hC; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _selectQready_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_26 = _response_latency_injection_q_io_deq_bits_source == 5'hD; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _selectQready_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_28 = _response_latency_injection_q_io_deq_bits_source == 5'hE; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _selectQready_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_30 = _response_latency_injection_q_io_deq_bits_source == 5'hF; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _selectQready_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_32 = _response_latency_injection_q_io_deq_bits_source == 5'h10; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _selectQready_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_34 = _response_latency_injection_q_io_deq_bits_source == 5'h11; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _selectQready_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_36 = _response_latency_injection_q_io_deq_bits_source == 5'h12; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _selectQready_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_38 = _response_latency_injection_q_io_deq_bits_source == 5'h13; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _selectQready_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_40 = _response_latency_injection_q_io_deq_bits_source == 5'h14; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _selectQready_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_42 = _response_latency_injection_q_io_deq_bits_source == 5'h15; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _selectQready_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_44 = _response_latency_injection_q_io_deq_bits_source == 5'h16; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _selectQready_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_46 = _response_latency_injection_q_io_deq_bits_source == 5'h17; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _selectQready_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_48 = _response_latency_injection_q_io_deq_bits_source == 5'h18; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _selectQready_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_50 = _response_latency_injection_q_io_deq_bits_source == 5'h19; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _selectQready_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_52 = _response_latency_injection_q_io_deq_bits_source == 5'h1A; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _selectQready_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_54 = _response_latency_injection_q_io_deq_bits_source == 5'h1B; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _selectQready_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_56 = _response_latency_injection_q_io_deq_bits_source == 5'h1C; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _selectQready_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_58 = _response_latency_injection_q_io_deq_bits_source == 5'h1D; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _selectQready_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_60 = _response_latency_injection_q_io_deq_bits_source == 5'h1E; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _selectQready_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_62 = &_response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _selectQready_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_64 = _selectQready_T_1 | _selectQready_T_3; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_65 = _selectQready_T_64 | _selectQready_T_5; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_66 = _selectQready_T_65 | _selectQready_T_7; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_67 = _selectQready_T_66 | _selectQready_T_9; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_68 = _selectQready_T_67 | _selectQready_T_11; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_69 = _selectQready_T_68 | _selectQready_T_13; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_70 = _selectQready_T_69 | _selectQready_T_15; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_71 = _selectQready_T_70 | _selectQready_T_17; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_72 = _selectQready_T_71 | _selectQready_T_19; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_73 = _selectQready_T_72 | _selectQready_T_21; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_74 = _selectQready_T_73 | _selectQready_T_23; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_75 = _selectQready_T_74 | _selectQready_T_25; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_76 = _selectQready_T_75 | _selectQready_T_27; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_77 = _selectQready_T_76 | _selectQready_T_29; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_78 = _selectQready_T_77 | _selectQready_T_31; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_79 = _selectQready_T_78 | _selectQready_T_33; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_80 = _selectQready_T_79 | _selectQready_T_35; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_81 = _selectQready_T_80 | _selectQready_T_37; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_82 = _selectQready_T_81 | _selectQready_T_39; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_83 = _selectQready_T_82 | _selectQready_T_41; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_84 = _selectQready_T_83 | _selectQready_T_43; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_85 = _selectQready_T_84 | _selectQready_T_45; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_86 = _selectQready_T_85 | _selectQready_T_47; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_87 = _selectQready_T_86 | _selectQready_T_49; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_88 = _selectQready_T_87 | _selectQready_T_51; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_89 = _selectQready_T_88 | _selectQready_T_53; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_90 = _selectQready_T_89 | _selectQready_T_55; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_91 = _selectQready_T_90 | _selectQready_T_57; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_92 = _selectQready_T_91 | _selectQready_T_59; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_93 = _selectQready_T_92 | _selectQready_T_61; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire selectQready = _selectQready_T_93 | _selectQready_T_63; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _T_57 = selectQready & _response_latency_injection_q_io_deq_valid; // @[Misc.scala:26:53] wire tags_for_issue_Q_io_enq_valid = _T_57 | _T_4; // @[Misc.scala:26:53] wire [4:0] tags_for_issue_Q_io_enq_bits = _T_57 ? _response_latency_injection_q_io_deq_bits_source : tags_init_reg[4:0]; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] wire _response_latency_injection_q_io_deq_ready_T = selectQready & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_156 = _response_latency_injection_q_io_deq_valid & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_160 = _outstanding_req_addr_io_deq_bits_tag == 5'h0; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T = _T_160; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q = _T_160; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_1 = _Queue4_L2RespInternal_io_deq_valid & _queueValid_T; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_163 = _outstanding_req_addr_io_deq_bits_tag == 5'h1; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_2 = _T_163; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_1; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_1 = _T_163; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_3 = _Queue4_L2RespInternal_1_io_deq_valid & _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_166 = _outstanding_req_addr_io_deq_bits_tag == 5'h2; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_4 = _T_166; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_2; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_2 = _T_166; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_5 = _Queue4_L2RespInternal_2_io_deq_valid & _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_169 = _outstanding_req_addr_io_deq_bits_tag == 5'h3; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_6 = _T_169; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_3; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_3 = _T_169; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_7 = _Queue4_L2RespInternal_3_io_deq_valid & _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_172 = _outstanding_req_addr_io_deq_bits_tag == 5'h4; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_8 = _T_172; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_4; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_4 = _T_172; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_9 = _Queue4_L2RespInternal_4_io_deq_valid & _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_175 = _outstanding_req_addr_io_deq_bits_tag == 5'h5; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_10 = _T_175; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_5; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_5 = _T_175; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_11 = _Queue4_L2RespInternal_5_io_deq_valid & _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_178 = _outstanding_req_addr_io_deq_bits_tag == 5'h6; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_12 = _T_178; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_6; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_6 = _T_178; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_13 = _Queue4_L2RespInternal_6_io_deq_valid & _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_181 = _outstanding_req_addr_io_deq_bits_tag == 5'h7; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_14 = _T_181; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_7; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_7 = _T_181; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_15 = _Queue4_L2RespInternal_7_io_deq_valid & _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_184 = _outstanding_req_addr_io_deq_bits_tag == 5'h8; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_16 = _T_184; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_8; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_8 = _T_184; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_17 = _Queue4_L2RespInternal_8_io_deq_valid & _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_187 = _outstanding_req_addr_io_deq_bits_tag == 5'h9; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_18 = _T_187; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_9; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_9 = _T_187; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_19 = _Queue4_L2RespInternal_9_io_deq_valid & _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_190 = _outstanding_req_addr_io_deq_bits_tag == 5'hA; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_20 = _T_190; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_10; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_10 = _T_190; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_21 = _Queue4_L2RespInternal_10_io_deq_valid & _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_193 = _outstanding_req_addr_io_deq_bits_tag == 5'hB; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_22 = _T_193; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_11; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_11 = _T_193; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_23 = _Queue4_L2RespInternal_11_io_deq_valid & _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_196 = _outstanding_req_addr_io_deq_bits_tag == 5'hC; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_24 = _T_196; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_12; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_12 = _T_196; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_25 = _Queue4_L2RespInternal_12_io_deq_valid & _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_199 = _outstanding_req_addr_io_deq_bits_tag == 5'hD; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_26 = _T_199; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_13; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_13 = _T_199; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_27 = _Queue4_L2RespInternal_13_io_deq_valid & _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_202 = _outstanding_req_addr_io_deq_bits_tag == 5'hE; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_28 = _T_202; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_14; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_14 = _T_202; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_29 = _Queue4_L2RespInternal_14_io_deq_valid & _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_205 = _outstanding_req_addr_io_deq_bits_tag == 5'hF; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_30 = _T_205; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_15; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_15 = _T_205; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_31 = _Queue4_L2RespInternal_15_io_deq_valid & _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_208 = _outstanding_req_addr_io_deq_bits_tag == 5'h10; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_32 = _T_208; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_16; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_16 = _T_208; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_33 = _Queue4_L2RespInternal_16_io_deq_valid & _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_211 = _outstanding_req_addr_io_deq_bits_tag == 5'h11; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_34 = _T_211; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_17; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_17 = _T_211; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_35 = _Queue4_L2RespInternal_17_io_deq_valid & _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_214 = _outstanding_req_addr_io_deq_bits_tag == 5'h12; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_36 = _T_214; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_18; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_18 = _T_214; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_37 = _Queue4_L2RespInternal_18_io_deq_valid & _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_217 = _outstanding_req_addr_io_deq_bits_tag == 5'h13; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_38 = _T_217; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_19; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_19 = _T_217; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_39 = _Queue4_L2RespInternal_19_io_deq_valid & _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_220 = _outstanding_req_addr_io_deq_bits_tag == 5'h14; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_40 = _T_220; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_20; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_20 = _T_220; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_41 = _Queue4_L2RespInternal_20_io_deq_valid & _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_223 = _outstanding_req_addr_io_deq_bits_tag == 5'h15; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_42 = _T_223; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_21; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_21 = _T_223; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_43 = _Queue4_L2RespInternal_21_io_deq_valid & _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_226 = _outstanding_req_addr_io_deq_bits_tag == 5'h16; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_44 = _T_226; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_22; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_22 = _T_226; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_45 = _Queue4_L2RespInternal_22_io_deq_valid & _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_229 = _outstanding_req_addr_io_deq_bits_tag == 5'h17; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_46 = _T_229; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_23; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_23 = _T_229; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_47 = _Queue4_L2RespInternal_23_io_deq_valid & _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_232 = _outstanding_req_addr_io_deq_bits_tag == 5'h18; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_48 = _T_232; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_24; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_24 = _T_232; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_49 = _Queue4_L2RespInternal_24_io_deq_valid & _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_235 = _outstanding_req_addr_io_deq_bits_tag == 5'h19; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_50 = _T_235; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_25; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_25 = _T_235; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_51 = _Queue4_L2RespInternal_25_io_deq_valid & _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_238 = _outstanding_req_addr_io_deq_bits_tag == 5'h1A; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_52 = _T_238; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_26; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_26 = _T_238; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_53 = _Queue4_L2RespInternal_26_io_deq_valid & _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_241 = _outstanding_req_addr_io_deq_bits_tag == 5'h1B; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_54 = _T_241; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_27; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_27 = _T_241; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_55 = _Queue4_L2RespInternal_27_io_deq_valid & _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_244 = _outstanding_req_addr_io_deq_bits_tag == 5'h1C; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_56 = _T_244; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_28; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_28 = _T_244; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_57 = _Queue4_L2RespInternal_28_io_deq_valid & _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_247 = _outstanding_req_addr_io_deq_bits_tag == 5'h1D; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_58 = _T_247; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_29; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_29 = _T_247; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_59 = _Queue4_L2RespInternal_29_io_deq_valid & _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_250 = _outstanding_req_addr_io_deq_bits_tag == 5'h1E; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_60 = _T_250; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_30; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_30 = _T_250; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_61 = _Queue4_L2RespInternal_30_io_deq_valid & _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_62 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_63 = _Queue4_L2RespInternal_31_io_deq_valid & _queueValid_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_64 = _queueValid_T_1 | _queueValid_T_3; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_65 = _queueValid_T_64 | _queueValid_T_5; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_66 = _queueValid_T_65 | _queueValid_T_7; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_67 = _queueValid_T_66 | _queueValid_T_9; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_68 = _queueValid_T_67 | _queueValid_T_11; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_69 = _queueValid_T_68 | _queueValid_T_13; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_70 = _queueValid_T_69 | _queueValid_T_15; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_71 = _queueValid_T_70 | _queueValid_T_17; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_72 = _queueValid_T_71 | _queueValid_T_19; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_73 = _queueValid_T_72 | _queueValid_T_21; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_74 = _queueValid_T_73 | _queueValid_T_23; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_75 = _queueValid_T_74 | _queueValid_T_25; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_76 = _queueValid_T_75 | _queueValid_T_27; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_77 = _queueValid_T_76 | _queueValid_T_29; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_78 = _queueValid_T_77 | _queueValid_T_31; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_79 = _queueValid_T_78 | _queueValid_T_33; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_80 = _queueValid_T_79 | _queueValid_T_35; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_81 = _queueValid_T_80 | _queueValid_T_37; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_82 = _queueValid_T_81 | _queueValid_T_39; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_83 = _queueValid_T_82 | _queueValid_T_41; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_84 = _queueValid_T_83 | _queueValid_T_43; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_85 = _queueValid_T_84 | _queueValid_T_45; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_86 = _queueValid_T_85 | _queueValid_T_47; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_87 = _queueValid_T_86 | _queueValid_T_49; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_88 = _queueValid_T_87 | _queueValid_T_51; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_89 = _queueValid_T_88 | _queueValid_T_53; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_90 = _queueValid_T_89 | _queueValid_T_55; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_91 = _queueValid_T_90 | _queueValid_T_57; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_92 = _queueValid_T_91 | _queueValid_T_59; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_93 = _queueValid_T_92 | _queueValid_T_61; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire queueValid = _queueValid_T_93 | _queueValid_T_63; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire [255:0] resultdata_data; // @[L2MemHelperLatencyInjection.scala:300:20] wire [7:0] _GEN_8 = {_outstanding_req_addr_io_deq_bits_addrindex, 3'h0}; // @[L2MemHelperLatencyInjection.scala:91:36, :302:78] wire [7:0] _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_2 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_4 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_6 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_8 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_10 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_12 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_14 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_16 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_18 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_20 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_22 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_24 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_26 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_28 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_30 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_32 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_34 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_36 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_38 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_40 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_42 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_44 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_46 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_48 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_50 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_52 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_54 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_56 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_58 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_60 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_62 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [255:0] _resultdata_data_T_1 = _Queue4_L2RespInternal_io_deq_bits_data >> _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data = resultdata_is_current_q ? _resultdata_data_T_1 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_3 = _Queue4_L2RespInternal_1_io_deq_bits_data >> _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_1 = resultdata_is_current_q_1 ? _resultdata_data_T_3 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_5 = _Queue4_L2RespInternal_2_io_deq_bits_data >> _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_2 = resultdata_is_current_q_2 ? _resultdata_data_T_5 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_7 = _Queue4_L2RespInternal_3_io_deq_bits_data >> _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_3 = resultdata_is_current_q_3 ? _resultdata_data_T_7 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_9 = _Queue4_L2RespInternal_4_io_deq_bits_data >> _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_4 = resultdata_is_current_q_4 ? _resultdata_data_T_9 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_11 = _Queue4_L2RespInternal_5_io_deq_bits_data >> _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_5 = resultdata_is_current_q_5 ? _resultdata_data_T_11 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_13 = _Queue4_L2RespInternal_6_io_deq_bits_data >> _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_6 = resultdata_is_current_q_6 ? _resultdata_data_T_13 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_15 = _Queue4_L2RespInternal_7_io_deq_bits_data >> _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_7 = resultdata_is_current_q_7 ? _resultdata_data_T_15 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_17 = _Queue4_L2RespInternal_8_io_deq_bits_data >> _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_8 = resultdata_is_current_q_8 ? _resultdata_data_T_17 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_19 = _Queue4_L2RespInternal_9_io_deq_bits_data >> _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_9 = resultdata_is_current_q_9 ? _resultdata_data_T_19 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_21 = _Queue4_L2RespInternal_10_io_deq_bits_data >> _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_10 = resultdata_is_current_q_10 ? _resultdata_data_T_21 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_23 = _Queue4_L2RespInternal_11_io_deq_bits_data >> _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_11 = resultdata_is_current_q_11 ? _resultdata_data_T_23 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_25 = _Queue4_L2RespInternal_12_io_deq_bits_data >> _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_12 = resultdata_is_current_q_12 ? _resultdata_data_T_25 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_27 = _Queue4_L2RespInternal_13_io_deq_bits_data >> _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_13 = resultdata_is_current_q_13 ? _resultdata_data_T_27 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_29 = _Queue4_L2RespInternal_14_io_deq_bits_data >> _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_14 = resultdata_is_current_q_14 ? _resultdata_data_T_29 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_31 = _Queue4_L2RespInternal_15_io_deq_bits_data >> _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_15 = resultdata_is_current_q_15 ? _resultdata_data_T_31 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_33 = _Queue4_L2RespInternal_16_io_deq_bits_data >> _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_16 = resultdata_is_current_q_16 ? _resultdata_data_T_33 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_35 = _Queue4_L2RespInternal_17_io_deq_bits_data >> _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_17 = resultdata_is_current_q_17 ? _resultdata_data_T_35 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_37 = _Queue4_L2RespInternal_18_io_deq_bits_data >> _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_18 = resultdata_is_current_q_18 ? _resultdata_data_T_37 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_39 = _Queue4_L2RespInternal_19_io_deq_bits_data >> _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_19 = resultdata_is_current_q_19 ? _resultdata_data_T_39 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_41 = _Queue4_L2RespInternal_20_io_deq_bits_data >> _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_20 = resultdata_is_current_q_20 ? _resultdata_data_T_41 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_43 = _Queue4_L2RespInternal_21_io_deq_bits_data >> _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_21 = resultdata_is_current_q_21 ? _resultdata_data_T_43 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_45 = _Queue4_L2RespInternal_22_io_deq_bits_data >> _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_22 = resultdata_is_current_q_22 ? _resultdata_data_T_45 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_47 = _Queue4_L2RespInternal_23_io_deq_bits_data >> _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_23 = resultdata_is_current_q_23 ? _resultdata_data_T_47 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_49 = _Queue4_L2RespInternal_24_io_deq_bits_data >> _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_24 = resultdata_is_current_q_24 ? _resultdata_data_T_49 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_51 = _Queue4_L2RespInternal_25_io_deq_bits_data >> _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_25 = resultdata_is_current_q_25 ? _resultdata_data_T_51 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_53 = _Queue4_L2RespInternal_26_io_deq_bits_data >> _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_26 = resultdata_is_current_q_26 ? _resultdata_data_T_53 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_55 = _Queue4_L2RespInternal_27_io_deq_bits_data >> _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_27 = resultdata_is_current_q_27 ? _resultdata_data_T_55 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_57 = _Queue4_L2RespInternal_28_io_deq_bits_data >> _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_28 = resultdata_is_current_q_28 ? _resultdata_data_T_57 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_59 = _Queue4_L2RespInternal_29_io_deq_bits_data >> _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_29 = resultdata_is_current_q_29 ? _resultdata_data_T_59 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_61 = _Queue4_L2RespInternal_30_io_deq_bits_data >> _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_30 = resultdata_is_current_q_30 ? _resultdata_data_T_61 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire resultdata_is_current_q_31 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27, :299:31] wire [255:0] resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_63 = _Queue4_L2RespInternal_31_io_deq_bits_data >> _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_31 = resultdata_is_current_q_31 ? _resultdata_data_T_63 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] _resultdata_T = resultdata_data | resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_1 = _resultdata_T | resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_2 = _resultdata_T_1 | resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_3 = _resultdata_T_2 | resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_4 = _resultdata_T_3 | resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_5 = _resultdata_T_4 | resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_6 = _resultdata_T_5 | resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_7 = _resultdata_T_6 | resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_8 = _resultdata_T_7 | resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_9 = _resultdata_T_8 | resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_10 = _resultdata_T_9 | resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_11 = _resultdata_T_10 | resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_12 = _resultdata_T_11 | resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_13 = _resultdata_T_12 | resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_14 = _resultdata_T_13 | resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_15 = _resultdata_T_14 | resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_16 = _resultdata_T_15 | resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_17 = _resultdata_T_16 | resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_18 = _resultdata_T_17 | resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_19 = _resultdata_T_18 | resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_20 = _resultdata_T_19 | resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_21 = _resultdata_T_20 | resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_22 = _resultdata_T_21 | resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_23 = _resultdata_T_22 | resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_24 = _resultdata_T_23 | resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_25 = _resultdata_T_24 | resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_26 = _resultdata_T_25 | resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_27 = _resultdata_T_26 | resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_28 = _resultdata_T_27 | resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_29 = _resultdata_T_28 | resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign resultdata = _resultdata_T_29 | resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign response_output_bits_data = resultdata; // @[L2MemHelperLatencyInjection.scala:53:29, :307:15] assign _response_output_valid_T = queueValid & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] assign response_output_valid = _response_output_valid_T; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_deq_ready_T = queueValid & response_output_ready; // @[Misc.scala:26:53] wire _T_252 = response_output_ready & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] wire opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] wire _T_270 = response_output_ready & response_output_valid; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38]

Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e8_s24_i8_3 : input clock : Clock input reset : Reset output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<8>, intExceptionFlags : UInt<3>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node magGeOne = bits(rawIn.sExp, 8, 8) node posExp = bits(rawIn.sExp, 7, 0) node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0)) node _magJustBelowOne_T_1 = andr(posExp) node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1) node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _shiftedSig_T = bits(rawIn.sig, 22, 0) node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T) node _shiftedSig_T_2 = bits(rawIn.sExp, 2, 0) node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0)) node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3) node _alignedSig_T = shr(shiftedSig, 22) node _alignedSig_T_1 = bits(shiftedSig, 21, 0) node _alignedSig_T_2 = orr(_alignedSig_T_1) node alignedSig = cat(_alignedSig_T, _alignedSig_T_2) node _unroundedInt_T = shr(alignedSig, 2) node unroundedInt = or(UInt<8>(0h0), _unroundedInt_T) node _common_inexact_T = bits(alignedSig, 1, 0) node _common_inexact_T_1 = orr(_common_inexact_T) node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0)) node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2) node _roundIncr_near_even_T = bits(alignedSig, 2, 1) node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T) node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2) node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3) node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4) node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6) node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7) node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8) node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1) node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T) node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne) node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even) node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag) node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1) node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd) node _roundIncr_T_4 = and(rawIn.sign, common_inexact) node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4) node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5) node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0)) node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact) node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8) node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9) node _complUnroundedInt_T = not(unroundedInt) node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt) node _roundedInt_T = xor(roundIncr, rawIn.sign) node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1)) node _roundedInt_T_2 = tail(_roundedInt_T_1, 1) node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt) node _roundedInt_T_4 = and(roundingMode_odd, common_inexact) node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4) node magGeOne_atOverflowEdge = eq(posExp, UInt<3>(0h7)) node _roundCarryBut2_T = bits(unroundedInt, 5, 0) node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T) node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr) node _common_overflow_T = geq(posExp, UInt<4>(0h8)) node _common_overflow_T_1 = bits(unroundedInt, 6, 0) node _common_overflow_T_2 = orr(_common_overflow_T_1) node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr) node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3) node _common_overflow_T_5 = eq(posExp, UInt<3>(0h6)) node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2) node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6) node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7) node _common_overflow_T_9 = bits(unroundedInt, 6, 6) node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9) node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2) node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11) node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12) node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13) node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0)) node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign) node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr) node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17) node invalidExc = or(rawIn.isNaN, rawIn.isInf) node _overflow_T = eq(invalidExc, UInt<1>(0h0)) node overflow = and(_overflow_T, common_overflow) node _inexact_T = eq(invalidExc, UInt<1>(0h0)) node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0)) node _inexact_T_2 = and(_inexact_T, _inexact_T_1) node inexact = and(_inexact_T_2, common_inexact) node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0)) node excSign = and(_excSign_T, rawIn.sign) node _excOut_T = eq(io.signedOut, excSign) node _excOut_T_1 = mux(_excOut_T, UInt<8>(0h80), UInt<1>(0h0)) node _excOut_T_2 = eq(excSign, UInt<1>(0h0)) node _excOut_T_3 = mux(_excOut_T_2, UInt<7>(0h7f), UInt<1>(0h0)) node excOut = or(_excOut_T_1, _excOut_T_3) node _io_out_T = or(invalidExc, common_overflow) node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt) connect io.out, _io_out_T_1 node _io_intExceptionFlags_T = cat(invalidExc, overflow) node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact) connect io.intExceptionFlags, _io_intExceptionFlags_T_1

module RecFNToIN_e8_s24_i8_3( // @[RecFNToIN.scala:46:7] input clock, // @[RecFNToIN.scala:46:7] input reset, // @[RecFNToIN.scala:46:7] input [32:0] io_in, // @[RecFNToIN.scala:49:16] output [7:0] io_out, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7] wire roundingMode_minMag = 1'h0; // @[RecFNToIN.scala:68:53] wire roundingMode_min = 1'h0; // @[RecFNToIN.scala:69:53] wire roundingMode_max = 1'h0; // @[RecFNToIN.scala:70:53] wire roundingMode_near_maxMag = 1'h0; // @[RecFNToIN.scala:71:53] wire roundingMode_odd = 1'h0; // @[RecFNToIN.scala:72:53] wire _roundIncr_T_1 = 1'h0; // @[RecFNToIN.scala:99:35] wire _roundIncr_T_3 = 1'h0; // @[RecFNToIN.scala:100:28] wire _roundIncr_T_5 = 1'h0; // @[RecFNToIN.scala:100:49] wire _roundIncr_T_9 = 1'h0; // @[RecFNToIN.scala:102:27] wire _roundedInt_T_4 = 1'h0; // @[RecFNToIN.scala:108:31] wire _common_overflow_T_15 = 1'h0; // @[RecFNToIN.scala:128:13] wire _common_overflow_T_16 = 1'h0; // @[RecFNToIN.scala:128:27] wire _common_overflow_T_17 = 1'h0; // @[RecFNToIN.scala:128:41] wire io_signedOut = 1'h1; // @[RecFNToIN.scala:46:7] wire roundingMode_near_even = 1'h1; // @[RecFNToIN.scala:67:53] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToIN.scala:46:7] wire [7:0] _io_out_T_1; // @[RecFNToIN.scala:145:18] wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52] wire [7:0] io_out_0; // @[RecFNToIN.scala:46:7] wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire magGeOne = rawIn_sExp[8]; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] posExp = rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27] wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47] wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}] wire [22:0] _shiftedSig_T = rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}] wire [2:0] _shiftedSig_T_2 = rawIn_sExp[2:0]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 3'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27] wire [30:0] shiftedSig = {7'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16] wire [8:0] _alignedSig_T = shiftedSig[30:22]; // @[RecFNToIN.scala:83:49, :89:20] wire [21:0] _alignedSig_T_1 = shiftedSig[21:0]; // @[RecFNToIN.scala:83:49, :89:51] wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}] wire [9:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}] wire [7:0] _unroundedInt_T = alignedSig[9:2]; // @[RecFNToIN.scala:89:38, :90:52] wire [7:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}] wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50] wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64] wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39] wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}] wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}] wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39] wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}] wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}] wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}] wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}] wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}] wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}] wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26] wire _roundIncr_T = roundIncr_near_even; // @[RecFNToIN.scala:94:78, :98:35] wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56] wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}] wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}] wire _roundIncr_T_2 = _roundIncr_T; // @[RecFNToIN.scala:98:{35,61}] wire _roundIncr_T_6 = _roundIncr_T_2; // @[RecFNToIN.scala:98:61, :99:61] wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23] wire roundIncr = _roundIncr_T_6; // @[RecFNToIN.scala:99:61, :101:46] wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}] wire [7:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45] wire [7:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23] wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 9'h1; // @[RecFNToIN.scala:103:32, :106:31] wire [7:0] _roundedInt_T_2 = _roundedInt_T_1[7:0]; // @[RecFNToIN.scala:106:31] wire [7:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31] wire [7:0] roundedInt = _roundedInt_T_3; // @[RecFNToIN.scala:105:12, :108:11] wire magGeOne_atOverflowEdge = posExp == 8'h7; // @[RecFNToIN.scala:62:28, :110:43] wire [5:0] _roundCarryBut2_T = unroundedInt[5:0]; // @[RecFNToIN.scala:90:40, :113:38] wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}] wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}] wire _common_overflow_T = |(posExp[7:3]); // @[RecFNToIN.scala:62:28, :116:21] wire [6:0] _common_overflow_T_1 = unroundedInt[6:0]; // @[RecFNToIN.scala:90:40, :120:42] wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}] wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}] wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64] wire _common_overflow_T_5 = posExp == 8'h6; // @[RecFNToIN.scala:62:28, :122:38] wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}] wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60] wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_13 = _common_overflow_T_8; // @[RecFNToIN.scala:117:20, :118:24] wire _common_overflow_T_9 = unroundedInt[6]; // @[RecFNToIN.scala:90:40, :126:42] wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42] wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57] wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20] wire common_overflow = magGeOne & _common_overflow_T_14; // @[RecFNToIN.scala:61:30, :115:12, :116:36] wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20] wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}] wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20] wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35] wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}] wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}] wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _excOut_T = excSign; // @[RecFNToIN.scala:137:32, :139:27] wire [7:0] _excOut_T_1 = {_excOut_T, 7'h0}; // @[RecFNToIN.scala:139:{12,27}] wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13] wire [6:0] _excOut_T_3 = {7{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}] wire [7:0] excOut = {_excOut_T_1[7], _excOut_T_1[6:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12] wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30] assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}] assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18] wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40] assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}] assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52] assign io_out = io_out_0; // @[RecFNToIN.scala:46:7] assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_18 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}} wire _in_flight_WIRE : UInt<1>[8] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = or(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_16 = or(_T_15, UInt<1>(0h0)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_21 = or(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_21, UInt<1>(0h1), "") : assert_4 node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_28 = and(_T_26, _T_27) node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_32 = and(_T_30, _T_31) node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) node _T_40 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_41 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_42 = and(_T_40, _T_41) node _T_43 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_69 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_70 = and(_T_68, _T_69) node _T_71 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_74 = and(_T_72, _T_73) node _T_75 = or(_T_32, _T_39) node _T_76 = or(_T_75, _T_46) node _T_77 = or(_T_76, _T_53) node _T_78 = or(_T_77, _T_60) node _T_79 = or(_T_78, _T_67) node _T_80 = or(_T_79, _T_74) node _T_81 = or(_T_25, _T_80) node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(_T_81, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_81, UInt<1>(0h1), "") : assert_5 node _T_85 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_87 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_88 = and(_T_86, _T_87) node _T_89 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_90 = and(_T_88, _T_89) node _T_91 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_94 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_97 = and(_T_95, _T_96) node _T_98 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_101 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_102 = and(_T_100, _T_101) node _T_103 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_104 = and(_T_102, _T_103) node _T_105 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_108 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_109 = and(_T_107, _T_108) node _T_110 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_111 = and(_T_109, _T_110) node _T_112 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_115 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_116 = and(_T_114, _T_115) node _T_117 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_118 = and(_T_116, _T_117) node _T_119 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_122 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _T_124 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_125 = and(_T_123, _T_124) node _T_126 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_129 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_134 = and(_T_132, _T_133) node _T_135 = or(_T_92, _T_99) node _T_136 = or(_T_135, _T_106) node _T_137 = or(_T_136, _T_113) node _T_138 = or(_T_137, _T_120) node _T_139 = or(_T_138, _T_127) node _T_140 = or(_T_139, _T_134) node _T_141 = or(_T_85, _T_140) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_141, UInt<1>(0h1), "") : assert_6 node _T_145 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_146 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_147 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_148 = and(_T_146, _T_147) node _T_149 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_150 = and(_T_148, _T_149) node _T_151 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_152 = and(_T_150, _T_151) node _T_153 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_154 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_157 = and(_T_155, _T_156) node _T_158 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_161 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_168 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_169 = and(_T_167, _T_168) node _T_170 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_175 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_180 = and(_T_178, _T_179) node _T_181 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_182 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_187 = and(_T_185, _T_186) node _T_188 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_189 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_194 = and(_T_192, _T_193) node _T_195 = or(_T_152, _T_159) node _T_196 = or(_T_195, _T_166) node _T_197 = or(_T_196, _T_173) node _T_198 = or(_T_197, _T_180) node _T_199 = or(_T_198, _T_187) node _T_200 = or(_T_199, _T_194) node _T_201 = or(_T_145, _T_200) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_201, UInt<1>(0h1), "") : assert_7 node _T_205 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_206 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_207 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_208 = and(_T_206, _T_207) node _T_209 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_212 = and(_T_210, _T_211) node _T_213 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_214 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_215 = and(_T_213, _T_214) node _T_216 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_219 = and(_T_217, _T_218) node _T_220 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_221 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_226 = and(_T_224, _T_225) node _T_227 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_228 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_229 = and(_T_227, _T_228) node _T_230 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_233 = and(_T_231, _T_232) node _T_234 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_235 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_236 = and(_T_234, _T_235) node _T_237 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_240 = and(_T_238, _T_239) node _T_241 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_242 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_243 = and(_T_241, _T_242) node _T_244 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_247 = and(_T_245, _T_246) node _T_248 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_249 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_254 = and(_T_252, _T_253) node _T_255 = or(_T_212, _T_219) node _T_256 = or(_T_255, _T_226) node _T_257 = or(_T_256, _T_233) node _T_258 = or(_T_257, _T_240) node _T_259 = or(_T_258, _T_247) node _T_260 = or(_T_259, _T_254) node _T_261 = or(_T_205, _T_260) node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_T_261, UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_261, UInt<1>(0h1), "") : assert_8

module NoCMonitor_18( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s1k3z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_40 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k3z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k3z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLBuffer_a32d64s1k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready = 1'h1; // @[Decoupled.scala:362:21] wire nodeIn_d_ready = 1'h1; // @[Decoupled.scala:362:21] wire [63:0] auto_in_a_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] nodeIn_a_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [7:0] auto_in_a_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [7:0] nodeIn_a_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire auto_in_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire [3:0] auto_in_a_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeIn_a_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_opcode = 3'h4; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_opcode = 3'h4; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_40 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s1k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s1k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_85 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_137 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_85( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_137 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_246 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_502 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_246( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_502 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_31 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut

module MulFullRawFN_31( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_162 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_418 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_162( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_418 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_9 : input clock : Clock input reset : Reset output io : { flip inR : { bits : UInt<32>}, flip inD : { bits : UInt<32>}, outL : { bits : UInt<32>}, outU : { bits : UInt<32>}, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : { bits : UInt<32>}, clock when io.en : connect reg.bits, _reg_T_1.bits connect io.outU, reg connect io.outL, reg

module PE_9( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [31:0] io_inR_bits, // @[Transposer.scala:101:16] input [31:0] io_inD_bits, // @[Transposer.scala:101:16] output [31:0] io_outL_bits, // @[Transposer.scala:101:16] output [31:0] io_outU_bits, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [31:0] io_inR_bits_0 = io_inR_bits; // @[Transposer.scala:100:9] wire [31:0] io_inD_bits_0 = io_inD_bits; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [31:0] io_outL_bits_0; // @[Transposer.scala:100:9] wire [31:0] io_outU_bits_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [31:0] _reg_T_1_bits = _reg_T ? io_inR_bits_0 : io_inD_bits_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [31:0] reg_bits; // @[Transposer.scala:110:24] assign io_outL_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] assign io_outU_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_bits <= _reg_T_1_bits; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL_bits = io_outL_bits_0; // @[Transposer.scala:100:9] assign io_outU_bits = io_outU_bits_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_77 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg

module PE_77( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BufferBRAM_2 : input clock : Clock input reset : Reset output io : { read : { flip en : UInt<1>, flip addr : UInt<10>, data : UInt<11>}, write : { flip en : UInt<1>, flip addr : UInt<10>, flip data : UInt<11>}} cmem ram : UInt<11> [600] regreset wen : UInt<1>, clock, reset, UInt<1>(0h0) connect wen, io.write.en reg waddr : UInt, clock connect waddr, io.write.addr reg wdata : UInt, clock connect wdata, io.write.data when wen : node _T = or(waddr, UInt<10>(0h0)) node _T_1 = bits(_T, 9, 0) write mport MPORT = ram[_T_1], clock connect MPORT, wdata read mport rread_data_MPORT = ram[io.read.addr], clock reg rread_data : UInt<11>, clock when io.read.en : connect rread_data, rread_data_MPORT node _rbypass_T = eq(io.read.addr, waddr) node _rbypass_T_1 = and(_rbypass_T, wen) reg rbypass : UInt<1>, clock when io.read.en : connect rbypass, _rbypass_T_1 reg rbypass_data : UInt, clock when io.read.en : connect rbypass_data, wdata node _io_read_data_T = mux(rbypass, rbypass_data, rread_data) connect io.read.data, _io_read_data_T

module BufferBRAM_2( // @[Buffer.scala:10:7] input clock, // @[Buffer.scala:10:7] input reset, // @[Buffer.scala:10:7] input io_read_en, // @[Buffer.scala:12:14] input [9:0] io_read_addr, // @[Buffer.scala:12:14] output [10:0] io_read_data, // @[Buffer.scala:12:14] input io_write_en, // @[Buffer.scala:12:14] input [9:0] io_write_addr, // @[Buffer.scala:12:14] input [10:0] io_write_data // @[Buffer.scala:12:14] ); wire [10:0] _ram_ext_R0_data; // @[Buffer.scala:27:16] wire io_read_en_0 = io_read_en; // @[Buffer.scala:10:7] wire [9:0] io_read_addr_0 = io_read_addr; // @[Buffer.scala:10:7] wire io_write_en_0 = io_write_en; // @[Buffer.scala:10:7] wire [9:0] io_write_addr_0 = io_write_addr; // @[Buffer.scala:10:7] wire [10:0] io_write_data_0 = io_write_data; // @[Buffer.scala:10:7] wire [10:0] _io_read_data_T; // @[Buffer.scala:39:22] wire [10:0] io_read_data_0; // @[Buffer.scala:10:7] reg wen; // @[Buffer.scala:29:20] reg [9:0] waddr; // @[Buffer.scala:30:22] reg [10:0] wdata; // @[Buffer.scala:31:22] reg [10:0] rread_data; // @[Buffer.scala:35:29] wire _rbypass_T = io_read_addr_0 == waddr; // @[Buffer.scala:10:7, :30:22, :36:40] wire _rbypass_T_1 = _rbypass_T & wen; // @[Buffer.scala:29:20, :36:{40,50}] reg rbypass; // @[Buffer.scala:36:26] reg [10:0] rbypass_data; // @[Buffer.scala:37:31] assign _io_read_data_T = rbypass ? rbypass_data : rread_data; // @[Buffer.scala:35:29, :36:26, :37:31, :39:22] assign io_read_data_0 = _io_read_data_T; // @[Buffer.scala:10:7, :39:22] always @(posedge clock) begin // @[Buffer.scala:10:7] if (reset) // @[Buffer.scala:10:7] wen <= 1'h0; // @[Buffer.scala:29:20] else // @[Buffer.scala:10:7] wen <= io_write_en_0; // @[Buffer.scala:10:7, :29:20] waddr <= io_write_addr_0; // @[Buffer.scala:10:7, :30:22] wdata <= io_write_data_0; // @[Buffer.scala:10:7, :31:22] if (io_read_en_0) begin // @[Buffer.scala:10:7] rread_data <= _ram_ext_R0_data; // @[Buffer.scala:27:16, :35:29] rbypass <= _rbypass_T_1; // @[Buffer.scala:36:{26,50}] rbypass_data <= wdata; // @[Buffer.scala:31:22, :37:31] end always @(posedge) ram_600x11 ram_ext ( // @[Buffer.scala:27:16] .R0_addr (io_read_addr_0), // @[Buffer.scala:10:7] .R0_en (1'h1), // @[Buffer.scala:10:7] .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (waddr), // @[Buffer.scala:30:22] .W0_en (wen), // @[Buffer.scala:29:20] .W0_clk (clock), .W0_data (wdata) // @[Buffer.scala:31:22] ); // @[Buffer.scala:27:16] assign io_read_data = io_read_data_0; // @[Buffer.scala:10:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_100 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_100 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RoundRawFNToRecFN_e8_s24_100( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_100 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_42 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_377 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_378 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_379 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_380 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T

module AsyncResetSynchronizerShiftReg_w4_d3_i0_42( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_377 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_378 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_379 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_380 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget1 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_11 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in node _hasData_opdata_T = bits(anonIn.a.bits.opcode, 2, 2) node hasData = eq(_hasData_opdata_T, UInt<1>(0h0)) node _limit_T = dshl(UInt<3>(0h7), anonIn.a.bits.size) node _limit_T_1 = bits(_limit_T, 2, 0) node _limit_T_2 = not(_limit_T_1) node limit = shr(_limit_T_2, 0) regreset count : UInt<3>, clock, reset, UInt<3>(0h0) node first = eq(count, UInt<1>(0h0)) node _last_T = eq(count, limit) node _last_T_1 = eq(hasData, UInt<1>(0h0)) node last = or(_last_T, _last_T_1) node _enable_T = xor(count, UInt<1>(0h0)) node _enable_T_1 = and(_enable_T, limit) node _enable_T_2 = orr(_enable_T_1) node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) node _enable_T_3 = xor(count, UInt<1>(0h1)) node _enable_T_4 = and(_enable_T_3, limit) node _enable_T_5 = orr(_enable_T_4) node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) node _enable_T_6 = xor(count, UInt<2>(0h2)) node _enable_T_7 = and(_enable_T_6, limit) node _enable_T_8 = orr(_enable_T_7) node enable_2 = eq(_enable_T_8, UInt<1>(0h0)) node _enable_T_9 = xor(count, UInt<2>(0h3)) node _enable_T_10 = and(_enable_T_9, limit) node _enable_T_11 = orr(_enable_T_10) node enable_3 = eq(_enable_T_11, UInt<1>(0h0)) node _enable_T_12 = xor(count, UInt<3>(0h4)) node _enable_T_13 = and(_enable_T_12, limit) node _enable_T_14 = orr(_enable_T_13) node enable_4 = eq(_enable_T_14, UInt<1>(0h0)) node _enable_T_15 = xor(count, UInt<3>(0h5)) node _enable_T_16 = and(_enable_T_15, limit) node _enable_T_17 = orr(_enable_T_16) node enable_5 = eq(_enable_T_17, UInt<1>(0h0)) node _enable_T_18 = xor(count, UInt<3>(0h6)) node _enable_T_19 = and(_enable_T_18, limit) node _enable_T_20 = orr(_enable_T_19) node enable_6 = eq(_enable_T_20, UInt<1>(0h0)) node _enable_T_21 = xor(count, UInt<3>(0h7)) node _enable_T_22 = and(_enable_T_21, limit) node _enable_T_23 = orr(_enable_T_22) node enable_7 = eq(_enable_T_23, UInt<1>(0h0)) regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) node corrupt_out = or(anonIn.a.bits.corrupt, corrupt_reg) node _T = and(anonIn.a.ready, anonIn.a.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 connect corrupt_reg, corrupt_out when last : connect count, UInt<1>(0h0) connect corrupt_reg, UInt<1>(0h0) node _anonIn_a_ready_T = eq(last, UInt<1>(0h0)) node _anonIn_a_ready_T_1 = or(anonOut.a.ready, _anonIn_a_ready_T) connect anonIn.a.ready, _anonIn_a_ready_T_1 node _anonOut_a_valid_T = and(anonIn.a.valid, last) connect anonOut.a.valid, _anonOut_a_valid_T connect anonOut.a.bits, anonIn.a.bits regreset anonOut_a_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonOut_a_bits_data_masked_enable_T = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_0 = or(enable_0, _anonOut_a_bits_data_masked_enable_T) node _anonOut_a_bits_data_masked_enable_T_1 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_1 = or(enable_1, _anonOut_a_bits_data_masked_enable_T_1) node _anonOut_a_bits_data_masked_enable_T_2 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_2 = or(enable_2, _anonOut_a_bits_data_masked_enable_T_2) node _anonOut_a_bits_data_masked_enable_T_3 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_3 = or(enable_3, _anonOut_a_bits_data_masked_enable_T_3) node _anonOut_a_bits_data_masked_enable_T_4 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_4 = or(enable_4, _anonOut_a_bits_data_masked_enable_T_4) node _anonOut_a_bits_data_masked_enable_T_5 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_5 = or(enable_5, _anonOut_a_bits_data_masked_enable_T_5) node _anonOut_a_bits_data_masked_enable_T_6 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_6 = or(enable_6, _anonOut_a_bits_data_masked_enable_T_6) node _anonOut_a_bits_data_masked_enable_T_7 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_7 = or(enable_7, _anonOut_a_bits_data_masked_enable_T_7) wire anonOut_a_bits_data_odata_0 : UInt connect anonOut_a_bits_data_odata_0, anonIn.a.bits.data wire anonOut_a_bits_data_odata_1 : UInt connect anonOut_a_bits_data_odata_1, anonIn.a.bits.data wire anonOut_a_bits_data_odata_2 : UInt connect anonOut_a_bits_data_odata_2, anonIn.a.bits.data wire anonOut_a_bits_data_odata_3 : UInt connect anonOut_a_bits_data_odata_3, anonIn.a.bits.data wire anonOut_a_bits_data_odata_4 : UInt connect anonOut_a_bits_data_odata_4, anonIn.a.bits.data wire anonOut_a_bits_data_odata_5 : UInt connect anonOut_a_bits_data_odata_5, anonIn.a.bits.data wire anonOut_a_bits_data_odata_6 : UInt connect anonOut_a_bits_data_odata_6, anonIn.a.bits.data wire anonOut_a_bits_data_odata_7 : UInt connect anonOut_a_bits_data_odata_7, anonIn.a.bits.data reg anonOut_a_bits_data_rdata : UInt<8>[7], clock node anonOut_a_bits_data_mdata_0 = mux(anonOut_a_bits_data_masked_enable_0, anonOut_a_bits_data_odata_0, anonOut_a_bits_data_rdata[0]) node anonOut_a_bits_data_mdata_1 = mux(anonOut_a_bits_data_masked_enable_1, anonOut_a_bits_data_odata_1, anonOut_a_bits_data_rdata[1]) node anonOut_a_bits_data_mdata_2 = mux(anonOut_a_bits_data_masked_enable_2, anonOut_a_bits_data_odata_2, anonOut_a_bits_data_rdata[2]) node anonOut_a_bits_data_mdata_3 = mux(anonOut_a_bits_data_masked_enable_3, anonOut_a_bits_data_odata_3, anonOut_a_bits_data_rdata[3]) node anonOut_a_bits_data_mdata_4 = mux(anonOut_a_bits_data_masked_enable_4, anonOut_a_bits_data_odata_4, anonOut_a_bits_data_rdata[4]) node anonOut_a_bits_data_mdata_5 = mux(anonOut_a_bits_data_masked_enable_5, anonOut_a_bits_data_odata_5, anonOut_a_bits_data_rdata[5]) node anonOut_a_bits_data_mdata_6 = mux(anonOut_a_bits_data_masked_enable_6, anonOut_a_bits_data_odata_6, anonOut_a_bits_data_rdata[6]) node anonOut_a_bits_data_mdata_7 = mux(anonOut_a_bits_data_masked_enable_7, anonOut_a_bits_data_odata_7, anonIn.a.bits.data) node _anonOut_a_bits_data_T = and(anonIn.a.ready, anonIn.a.valid) node _anonOut_a_bits_data_T_1 = eq(last, UInt<1>(0h0)) node _anonOut_a_bits_data_T_2 = and(_anonOut_a_bits_data_T, _anonOut_a_bits_data_T_1) when _anonOut_a_bits_data_T_2 : connect anonOut_a_bits_data_rdata_written_once, UInt<1>(0h1) connect anonOut_a_bits_data_rdata[0], anonOut_a_bits_data_mdata_0 connect anonOut_a_bits_data_rdata[1], anonOut_a_bits_data_mdata_1 connect anonOut_a_bits_data_rdata[2], anonOut_a_bits_data_mdata_2 connect anonOut_a_bits_data_rdata[3], anonOut_a_bits_data_mdata_3 connect anonOut_a_bits_data_rdata[4], anonOut_a_bits_data_mdata_4 connect anonOut_a_bits_data_rdata[5], anonOut_a_bits_data_mdata_5 connect anonOut_a_bits_data_rdata[6], anonOut_a_bits_data_mdata_6 node anonOut_a_bits_data_lo_lo = cat(anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0) node anonOut_a_bits_data_lo_hi = cat(anonOut_a_bits_data_mdata_3, anonOut_a_bits_data_mdata_2) node anonOut_a_bits_data_lo = cat(anonOut_a_bits_data_lo_hi, anonOut_a_bits_data_lo_lo) node anonOut_a_bits_data_hi_lo = cat(anonOut_a_bits_data_mdata_5, anonOut_a_bits_data_mdata_4) node anonOut_a_bits_data_hi_hi = cat(anonOut_a_bits_data_mdata_7, anonOut_a_bits_data_mdata_6) node anonOut_a_bits_data_hi = cat(anonOut_a_bits_data_hi_hi, anonOut_a_bits_data_hi_lo) node _anonOut_a_bits_data_T_3 = cat(anonOut_a_bits_data_hi, anonOut_a_bits_data_lo) connect anonOut.a.bits.data, _anonOut_a_bits_data_T_3 connect anonOut.a.bits.corrupt, corrupt_out node _anonOut_a_bits_mask_sizeOH_T = or(anonOut.a.bits.size, UInt<3>(0h0)) node anonOut_a_bits_mask_sizeOH_shiftAmount = bits(_anonOut_a_bits_mask_sizeOH_T, 1, 0) node _anonOut_a_bits_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), anonOut_a_bits_mask_sizeOH_shiftAmount) node _anonOut_a_bits_mask_sizeOH_T_2 = bits(_anonOut_a_bits_mask_sizeOH_T_1, 2, 0) node anonOut_a_bits_mask_sizeOH = or(_anonOut_a_bits_mask_sizeOH_T_2, UInt<1>(0h1)) node anonOut_a_bits_mask_sub_sub_sub_0_1 = geq(anonOut.a.bits.size, UInt<2>(0h3)) node anonOut_a_bits_mask_sub_sub_size = bits(anonOut_a_bits_mask_sizeOH, 2, 2) node anonOut_a_bits_mask_sub_sub_bit = bits(anonOut.a.bits.address, 2, 2) node anonOut_a_bits_mask_sub_sub_nbit = eq(anonOut_a_bits_mask_sub_sub_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_sub_sub_0_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_nbit) node _anonOut_a_bits_mask_sub_sub_acc_T = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_0_2) node anonOut_a_bits_mask_sub_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T) node anonOut_a_bits_mask_sub_sub_1_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_bit) node _anonOut_a_bits_mask_sub_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_1_2) node anonOut_a_bits_mask_sub_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T_1) node anonOut_a_bits_mask_sub_size = bits(anonOut_a_bits_mask_sizeOH, 1, 1) node anonOut_a_bits_mask_sub_bit = bits(anonOut.a.bits.address, 1, 1) node anonOut_a_bits_mask_sub_nbit = eq(anonOut_a_bits_mask_sub_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_sub_0_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_nbit) node _anonOut_a_bits_mask_sub_acc_T = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_0_2) node anonOut_a_bits_mask_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T) node anonOut_a_bits_mask_sub_1_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_bit) node _anonOut_a_bits_mask_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_1_2) node anonOut_a_bits_mask_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T_1) node anonOut_a_bits_mask_sub_2_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_nbit) node _anonOut_a_bits_mask_sub_acc_T_2 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_2_2) node anonOut_a_bits_mask_sub_2_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_2) node anonOut_a_bits_mask_sub_3_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_bit) node _anonOut_a_bits_mask_sub_acc_T_3 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_3_2) node anonOut_a_bits_mask_sub_3_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_3) node anonOut_a_bits_mask_size = bits(anonOut_a_bits_mask_sizeOH, 0, 0) node anonOut_a_bits_mask_bit = bits(anonOut.a.bits.address, 0, 0) node anonOut_a_bits_mask_nbit = eq(anonOut_a_bits_mask_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_eq = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq) node anonOut_a_bits_mask_acc = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T) node anonOut_a_bits_mask_eq_1 = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_1 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_1) node anonOut_a_bits_mask_acc_1 = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T_1) node anonOut_a_bits_mask_eq_2 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_2 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_2) node anonOut_a_bits_mask_acc_2 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_2) node anonOut_a_bits_mask_eq_3 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_3 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_3) node anonOut_a_bits_mask_acc_3 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_3) node anonOut_a_bits_mask_eq_4 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_4 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_4) node anonOut_a_bits_mask_acc_4 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_4) node anonOut_a_bits_mask_eq_5 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_5 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_5) node anonOut_a_bits_mask_acc_5 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_5) node anonOut_a_bits_mask_eq_6 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_6 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_6) node anonOut_a_bits_mask_acc_6 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_6) node anonOut_a_bits_mask_eq_7 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_7 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_7) node anonOut_a_bits_mask_acc_7 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_7) node anonOut_a_bits_mask_lo_lo = cat(anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc) node anonOut_a_bits_mask_lo_hi = cat(anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2) node anonOut_a_bits_mask_lo = cat(anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo) node anonOut_a_bits_mask_hi_lo = cat(anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4) node anonOut_a_bits_mask_hi_hi = cat(anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6) node anonOut_a_bits_mask_hi = cat(anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo) node _anonOut_a_bits_mask_T = cat(anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo) regreset anonOut_a_bits_mask_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonOut_a_bits_mask_masked_enable_T = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_0 = or(enable_0, _anonOut_a_bits_mask_masked_enable_T) node _anonOut_a_bits_mask_masked_enable_T_1 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_1 = or(enable_1, _anonOut_a_bits_mask_masked_enable_T_1) node _anonOut_a_bits_mask_masked_enable_T_2 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_2 = or(enable_2, _anonOut_a_bits_mask_masked_enable_T_2) node _anonOut_a_bits_mask_masked_enable_T_3 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_3 = or(enable_3, _anonOut_a_bits_mask_masked_enable_T_3) node _anonOut_a_bits_mask_masked_enable_T_4 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_4 = or(enable_4, _anonOut_a_bits_mask_masked_enable_T_4) node _anonOut_a_bits_mask_masked_enable_T_5 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_5 = or(enable_5, _anonOut_a_bits_mask_masked_enable_T_5) node _anonOut_a_bits_mask_masked_enable_T_6 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_6 = or(enable_6, _anonOut_a_bits_mask_masked_enable_T_6) node _anonOut_a_bits_mask_masked_enable_T_7 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_7 = or(enable_7, _anonOut_a_bits_mask_masked_enable_T_7) wire anonOut_a_bits_mask_odata_0 : UInt connect anonOut_a_bits_mask_odata_0, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_1 : UInt connect anonOut_a_bits_mask_odata_1, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_2 : UInt connect anonOut_a_bits_mask_odata_2, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_3 : UInt connect anonOut_a_bits_mask_odata_3, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_4 : UInt connect anonOut_a_bits_mask_odata_4, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_5 : UInt connect anonOut_a_bits_mask_odata_5, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_6 : UInt connect anonOut_a_bits_mask_odata_6, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_7 : UInt connect anonOut_a_bits_mask_odata_7, anonIn.a.bits.mask reg anonOut_a_bits_mask_rdata : UInt<1>[7], clock node anonOut_a_bits_mask_mdata_0 = mux(anonOut_a_bits_mask_masked_enable_0, anonOut_a_bits_mask_odata_0, anonOut_a_bits_mask_rdata[0]) node anonOut_a_bits_mask_mdata_1 = mux(anonOut_a_bits_mask_masked_enable_1, anonOut_a_bits_mask_odata_1, anonOut_a_bits_mask_rdata[1]) node anonOut_a_bits_mask_mdata_2 = mux(anonOut_a_bits_mask_masked_enable_2, anonOut_a_bits_mask_odata_2, anonOut_a_bits_mask_rdata[2]) node anonOut_a_bits_mask_mdata_3 = mux(anonOut_a_bits_mask_masked_enable_3, anonOut_a_bits_mask_odata_3, anonOut_a_bits_mask_rdata[3]) node anonOut_a_bits_mask_mdata_4 = mux(anonOut_a_bits_mask_masked_enable_4, anonOut_a_bits_mask_odata_4, anonOut_a_bits_mask_rdata[4]) node anonOut_a_bits_mask_mdata_5 = mux(anonOut_a_bits_mask_masked_enable_5, anonOut_a_bits_mask_odata_5, anonOut_a_bits_mask_rdata[5]) node anonOut_a_bits_mask_mdata_6 = mux(anonOut_a_bits_mask_masked_enable_6, anonOut_a_bits_mask_odata_6, anonOut_a_bits_mask_rdata[6]) node anonOut_a_bits_mask_mdata_7 = mux(anonOut_a_bits_mask_masked_enable_7, anonOut_a_bits_mask_odata_7, anonIn.a.bits.mask) node _anonOut_a_bits_mask_T_1 = and(anonIn.a.ready, anonIn.a.valid) node _anonOut_a_bits_mask_T_2 = eq(last, UInt<1>(0h0)) node _anonOut_a_bits_mask_T_3 = and(_anonOut_a_bits_mask_T_1, _anonOut_a_bits_mask_T_2) when _anonOut_a_bits_mask_T_3 : connect anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h1) connect anonOut_a_bits_mask_rdata[0], anonOut_a_bits_mask_mdata_0 connect anonOut_a_bits_mask_rdata[1], anonOut_a_bits_mask_mdata_1 connect anonOut_a_bits_mask_rdata[2], anonOut_a_bits_mask_mdata_2 connect anonOut_a_bits_mask_rdata[3], anonOut_a_bits_mask_mdata_3 connect anonOut_a_bits_mask_rdata[4], anonOut_a_bits_mask_mdata_4 connect anonOut_a_bits_mask_rdata[5], anonOut_a_bits_mask_mdata_5 connect anonOut_a_bits_mask_rdata[6], anonOut_a_bits_mask_mdata_6 node anonOut_a_bits_mask_lo_lo_1 = cat(anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0) node anonOut_a_bits_mask_lo_hi_1 = cat(anonOut_a_bits_mask_mdata_3, anonOut_a_bits_mask_mdata_2) node anonOut_a_bits_mask_lo_1 = cat(anonOut_a_bits_mask_lo_hi_1, anonOut_a_bits_mask_lo_lo_1) node anonOut_a_bits_mask_hi_lo_1 = cat(anonOut_a_bits_mask_mdata_5, anonOut_a_bits_mask_mdata_4) node anonOut_a_bits_mask_hi_hi_1 = cat(anonOut_a_bits_mask_mdata_7, anonOut_a_bits_mask_mdata_6) node anonOut_a_bits_mask_hi_1 = cat(anonOut_a_bits_mask_hi_hi_1, anonOut_a_bits_mask_hi_lo_1) node _anonOut_a_bits_mask_T_4 = cat(anonOut_a_bits_mask_hi_1, anonOut_a_bits_mask_lo_1) node _anonOut_a_bits_mask_T_5 = not(UInt<8>(0h0)) node _anonOut_a_bits_mask_T_6 = mux(hasData, _anonOut_a_bits_mask_T_4, _anonOut_a_bits_mask_T_5) node _anonOut_a_bits_mask_T_7 = and(_anonOut_a_bits_mask_T, _anonOut_a_bits_mask_T_6) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T_7 wire repeat : UInt<1> inst repeated_repeater of Repeater_TLBundleD_a32d64s1k3z4u connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat connect repeated_repeater.io.enq, anonOut.d wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect cated.bits, repeated_repeater.io.deq.bits connect cated.valid, repeated_repeater.io.deq.valid connect repeated_repeater.io.deq.ready, cated.ready node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 63, 8) node _cated_bits_data_T_1 = bits(anonOut.d.bits.data, 7, 0) node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) connect cated.bits.data, _cated_bits_data_T_2 node repeat_hasData = bits(cated.bits.opcode, 0, 0) node _repeat_limit_T = dshl(UInt<3>(0h7), cated.bits.size) node _repeat_limit_T_1 = bits(_repeat_limit_T, 2, 0) node _repeat_limit_T_2 = not(_repeat_limit_T_1) node repeat_limit = shr(_repeat_limit_T_2, 0) regreset repeat_count : UInt<3>, clock, reset, UInt<3>(0h0) node repeat_first = eq(repeat_count, UInt<1>(0h0)) node _repeat_last_T = eq(repeat_count, repeat_limit) node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) node repeat_last = or(_repeat_last_T, _repeat_last_T_1) node _repeat_T = and(anonIn.d.ready, anonIn.d.valid) when _repeat_T : node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) node _repeat_count_T_1 = tail(_repeat_count_T, 1) connect repeat_count, _repeat_count_T_1 when repeat_last : connect repeat_count, UInt<1>(0h0) reg repeat_sel_sel_sources : UInt<3>[1], clock node repeat_sel_sel_a_sel = bits(anonIn.a.bits.address, 2, 0) node _repeat_sel_sel_T = and(anonIn.a.ready, anonIn.a.valid) when _repeat_sel_sel_T : connect repeat_sel_sel_sources[0], repeat_sel_sel_a_sel node _repeat_sel_sel_bypass_T = eq(anonIn.a.bits.source, UInt<0>(0h0)) node repeat_sel_sel_bypass = and(anonIn.a.valid, _repeat_sel_sel_bypass_T) reg repeat_sel_hold_r : UInt<3>, clock when repeat_first : connect repeat_sel_hold_r, repeat_sel_sel_sources[0] node repeat_sel_hold = mux(repeat_first, repeat_sel_sel_sources[0], repeat_sel_hold_r) node _repeat_sel_T = not(repeat_limit) node repeat_sel = and(repeat_sel_hold, _repeat_sel_T) node repeat_index = or(repeat_sel, repeat_count) connect anonIn.d.bits.corrupt, cated.bits.corrupt connect anonIn.d.bits.data, cated.bits.data connect anonIn.d.bits.denied, cated.bits.denied connect anonIn.d.bits.sink, cated.bits.sink connect anonIn.d.bits.source, cated.bits.source connect anonIn.d.bits.size, cated.bits.size connect anonIn.d.bits.param, cated.bits.param connect anonIn.d.bits.opcode, cated.bits.opcode connect anonIn.d.valid, cated.valid connect cated.ready, anonIn.d.ready node _repeat_anonIn_d_bits_data_mux_T = bits(cated.bits.data, 7, 0) node _repeat_anonIn_d_bits_data_mux_T_1 = bits(cated.bits.data, 15, 8) node _repeat_anonIn_d_bits_data_mux_T_2 = bits(cated.bits.data, 23, 16) node _repeat_anonIn_d_bits_data_mux_T_3 = bits(cated.bits.data, 31, 24) node _repeat_anonIn_d_bits_data_mux_T_4 = bits(cated.bits.data, 39, 32) node _repeat_anonIn_d_bits_data_mux_T_5 = bits(cated.bits.data, 47, 40) node _repeat_anonIn_d_bits_data_mux_T_6 = bits(cated.bits.data, 55, 48) node _repeat_anonIn_d_bits_data_mux_T_7 = bits(cated.bits.data, 63, 56) wire repeat_anonIn_d_bits_data_mux : UInt<8>[8] connect repeat_anonIn_d_bits_data_mux[0], _repeat_anonIn_d_bits_data_mux_T connect repeat_anonIn_d_bits_data_mux[1], _repeat_anonIn_d_bits_data_mux_T_1 connect repeat_anonIn_d_bits_data_mux[2], _repeat_anonIn_d_bits_data_mux_T_2 connect repeat_anonIn_d_bits_data_mux[3], _repeat_anonIn_d_bits_data_mux_T_3 connect repeat_anonIn_d_bits_data_mux[4], _repeat_anonIn_d_bits_data_mux_T_4 connect repeat_anonIn_d_bits_data_mux[5], _repeat_anonIn_d_bits_data_mux_T_5 connect repeat_anonIn_d_bits_data_mux[6], _repeat_anonIn_d_bits_data_mux_T_6 connect repeat_anonIn_d_bits_data_mux[7], _repeat_anonIn_d_bits_data_mux_T_7 connect anonIn.d.bits.data, repeat_anonIn_d_bits_data_mux[repeat_index] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) connect repeat, _repeat_T_1 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<8>(0h0) connect _WIRE.bits.mask, UInt<1>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLWidthWidget1( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [63:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [7:0] _anonOut_a_bits_mask_T_5 = 8'hFF; // @[WidthWidget.scala:85:119] wire auto_anon_in_a_bits_mask = 1'h1; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_mask = 1'h1; // @[MixedNode.scala:551:17] wire anonOut_a_bits_mask_odata_0 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_1 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_2 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_3 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_4 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_5 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_6 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_odata_7 = 1'h1; // @[WidthWidget.scala:65:47] wire anonOut_a_bits_mask_mdata_7 = 1'h1; // @[WidthWidget.scala:68:88] wire _repeat_sel_sel_bypass_T = 1'h1; // @[WidthWidget.scala:200:53] wire [2:0] auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] anonOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire cated_bits_source = 1'h0; // @[WidthWidget.scala:161:25] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] wire _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire repeat_sel_sel_bypass = anonIn_a_valid; // @[WidthWidget.scala:200:33] assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] anonOut_a_bits_data_odata_0 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_1 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_2 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_3 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_4 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_5 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_6 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_data_odata_7 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire cated_ready = anonIn_d_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_sink; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] wire cated_bits_denied; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_a_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] _anonOut_a_bits_mask_sizeOH_T = anonOut_a_bits_size; // @[Misc.scala:202:34] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] wire _hasData_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [17:0] _limit_T = 18'h7 << anonIn_a_bits_size; // @[package.scala:243:71] wire [2:0] _limit_T_1 = _limit_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire [2:0] limit = _limit_T_2; // @[package.scala:243:46] reg [2:0] count; // @[WidthWidget.scala:40:27] wire [2:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = count == 3'h0; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire [2:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_3 = {count[2:1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_6 = {count[2], count[1:0] ^ 2'h2}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}] wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_9 = {count[2], ~(count[1:0])}; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}] wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_12 = count ^ 3'h4; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_13 = _enable_T_12 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_14 = |_enable_T_13; // @[WidthWidget.scala:43:{63,72}] wire enable_4 = ~_enable_T_14; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_15 = count ^ 3'h5; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_16 = _enable_T_15 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_17 = |_enable_T_16; // @[WidthWidget.scala:43:{63,72}] wire enable_5 = ~_enable_T_17; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_18 = count ^ 3'h6; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_19 = _enable_T_18 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_20 = |_enable_T_19; // @[WidthWidget.scala:43:{63,72}] wire enable_6 = ~_enable_T_20; // @[WidthWidget.scala:43:{47,72}] wire [2:0] _enable_T_21 = ~count; // @[WidthWidget.scala:40:27, :43:56] wire [2:0] _enable_T_22 = _enable_T_21 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_23 = |_enable_T_22; // @[WidthWidget.scala:43:{63,72}] wire enable_7 = ~_enable_T_23; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonOut_a_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _T = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35] wire _anonOut_a_bits_data_T; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_data_T = _T; // @[Decoupled.scala:51:35] wire _anonOut_a_bits_mask_T_1; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_mask_T_1 = _T; // @[Decoupled.scala:51:35] wire _repeat_sel_sel_T; // @[Decoupled.scala:51:35] assign _repeat_sel_sel_T = _T; // @[Decoupled.scala:51:35] wire [3:0] _count_T = {1'h0, count} + 4'h1; // @[WidthWidget.scala:40:27, :50:24] wire [2:0] _count_T_1 = _count_T[2:0]; // @[WidthWidget.scala:50:24] wire _anonIn_a_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonIn_a_ready_T_1 = anonOut_a_ready | _anonIn_a_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonIn_a_ready = _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonOut_a_valid_T = anonIn_a_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonOut_a_valid = _anonOut_a_valid_T; // @[WidthWidget.scala:77:29] reg anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonOut_a_bits_data_masked_enable_T = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_0 = enable_0 | _anonOut_a_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_1 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_1 = enable_1 | _anonOut_a_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_2 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_2 = enable_2 | _anonOut_a_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_3 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_3 = enable_3 | _anonOut_a_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_4 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_4 = enable_4 | _anonOut_a_bits_data_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_5 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_5 = enable_5 | _anonOut_a_bits_data_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_6 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_6 = enable_6 | _anonOut_a_bits_data_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_7 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_7 = enable_7 | _anonOut_a_bits_data_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [7:0] anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:66:24] reg [7:0] anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:66:24] wire [7:0] anonOut_a_bits_data_mdata_0 = anonOut_a_bits_data_masked_enable_0 ? anonOut_a_bits_data_odata_0 : anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_1 = anonOut_a_bits_data_masked_enable_1 ? anonOut_a_bits_data_odata_1 : anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_2 = anonOut_a_bits_data_masked_enable_2 ? anonOut_a_bits_data_odata_2 : anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_3 = anonOut_a_bits_data_masked_enable_3 ? anonOut_a_bits_data_odata_3 : anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_4 = anonOut_a_bits_data_masked_enable_4 ? anonOut_a_bits_data_odata_4 : anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_5 = anonOut_a_bits_data_masked_enable_5 ? anonOut_a_bits_data_odata_5 : anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_6 = anonOut_a_bits_data_masked_enable_6 ? anonOut_a_bits_data_odata_6 : anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_data_mdata_7 = anonOut_a_bits_data_masked_enable_7 ? anonOut_a_bits_data_odata_7 : anonIn_a_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonOut_a_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonOut_a_bits_data_T_2 = _anonOut_a_bits_data_T & _anonOut_a_bits_data_T_1; // @[Decoupled.scala:51:35] wire [15:0] anonOut_a_bits_data_lo_lo = {anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [15:0] anonOut_a_bits_data_lo_hi = {anonOut_a_bits_data_mdata_3, anonOut_a_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] wire [31:0] anonOut_a_bits_data_lo = {anonOut_a_bits_data_lo_hi, anonOut_a_bits_data_lo_lo}; // @[WidthWidget.scala:73:12] wire [15:0] anonOut_a_bits_data_hi_lo = {anonOut_a_bits_data_mdata_5, anonOut_a_bits_data_mdata_4}; // @[WidthWidget.scala:68:88, :73:12] wire [15:0] anonOut_a_bits_data_hi_hi = {anonOut_a_bits_data_mdata_7, anonOut_a_bits_data_mdata_6}; // @[WidthWidget.scala:68:88, :73:12] wire [31:0] anonOut_a_bits_data_hi = {anonOut_a_bits_data_hi_hi, anonOut_a_bits_data_hi_lo}; // @[WidthWidget.scala:73:12] assign _anonOut_a_bits_data_T_3 = {anonOut_a_bits_data_hi, anonOut_a_bits_data_lo}; // @[WidthWidget.scala:73:12] assign anonOut_a_bits_data = _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12] wire [1:0] anonOut_a_bits_mask_sizeOH_shiftAmount = _anonOut_a_bits_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _anonOut_a_bits_mask_sizeOH_T_1 = 4'h1 << anonOut_a_bits_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _anonOut_a_bits_mask_sizeOH_T_2 = _anonOut_a_bits_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] anonOut_a_bits_mask_sizeOH = {_anonOut_a_bits_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire anonOut_a_bits_mask_sub_sub_sub_0_1 = anonOut_a_bits_size > 4'h2; // @[Misc.scala:206:21] wire anonOut_a_bits_mask_sub_sub_size = anonOut_a_bits_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_sub_bit = anonOut_a_bits_address[2]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_sub_1_2 = anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire anonOut_a_bits_mask_sub_sub_nbit = ~anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_sub_0_2 = anonOut_a_bits_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_sub_acc_T = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_0_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _anonOut_a_bits_mask_sub_sub_acc_T_1 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_1_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire anonOut_a_bits_mask_sub_size = anonOut_a_bits_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_bit = anonOut_a_bits_address[1]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_nbit = ~anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_0_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_0_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_1_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_1 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_1_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_2_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_2 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_2_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_3_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_3 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_3_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_size = anonOut_a_bits_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_bit = anonOut_a_bits_address[0]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_nbit = ~anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_eq = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_1 = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_1 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_1 = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_2 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_2 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_2 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_3 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_3 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_3 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_4 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_4 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_4 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_5 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_5 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_5 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_6 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_6 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_6 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_7 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_7 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_7 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] anonOut_a_bits_mask_lo_lo = {anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_lo_hi = {anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_lo = {anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] anonOut_a_bits_mask_hi_lo = {anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_hi_hi = {anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_hi = {anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] _anonOut_a_bits_mask_T = {anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo}; // @[Misc.scala:222:10] reg anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonOut_a_bits_mask_masked_enable_T = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_0 = enable_0 | _anonOut_a_bits_mask_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_1 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_1 = enable_1 | _anonOut_a_bits_mask_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_2 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_2 = enable_2 | _anonOut_a_bits_mask_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_3 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_3 = enable_3 | _anonOut_a_bits_mask_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_4 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_4 = enable_4 | _anonOut_a_bits_mask_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_5 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_5 = enable_5 | _anonOut_a_bits_mask_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_6 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_6 = enable_6 | _anonOut_a_bits_mask_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_7 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_7 = enable_7 | _anonOut_a_bits_mask_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}] reg anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_1; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_2; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_3; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_4; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_5; // @[WidthWidget.scala:66:24] reg anonOut_a_bits_mask_rdata_6; // @[WidthWidget.scala:66:24] wire anonOut_a_bits_mask_mdata_0 = anonOut_a_bits_mask_masked_enable_0 | anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_1 = anonOut_a_bits_mask_masked_enable_1 | anonOut_a_bits_mask_rdata_1; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_2 = anonOut_a_bits_mask_masked_enable_2 | anonOut_a_bits_mask_rdata_2; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_3 = anonOut_a_bits_mask_masked_enable_3 | anonOut_a_bits_mask_rdata_3; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_4 = anonOut_a_bits_mask_masked_enable_4 | anonOut_a_bits_mask_rdata_4; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_5 = anonOut_a_bits_mask_masked_enable_5 | anonOut_a_bits_mask_rdata_5; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire anonOut_a_bits_mask_mdata_6 = anonOut_a_bits_mask_masked_enable_6 | anonOut_a_bits_mask_rdata_6; // @[WidthWidget.scala:63:42, :66:24, :68:88] wire _anonOut_a_bits_mask_T_2 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonOut_a_bits_mask_T_3 = _anonOut_a_bits_mask_T_1 & _anonOut_a_bits_mask_T_2; // @[Decoupled.scala:51:35] wire [1:0] anonOut_a_bits_mask_lo_lo_1 = {anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [1:0] anonOut_a_bits_mask_lo_hi_1 = {anonOut_a_bits_mask_mdata_3, anonOut_a_bits_mask_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] wire [3:0] anonOut_a_bits_mask_lo_1 = {anonOut_a_bits_mask_lo_hi_1, anonOut_a_bits_mask_lo_lo_1}; // @[WidthWidget.scala:73:12] wire [1:0] anonOut_a_bits_mask_hi_lo_1 = {anonOut_a_bits_mask_mdata_5, anonOut_a_bits_mask_mdata_4}; // @[WidthWidget.scala:68:88, :73:12] wire [1:0] anonOut_a_bits_mask_hi_hi_1 = {1'h1, anonOut_a_bits_mask_mdata_6}; // @[WidthWidget.scala:68:88, :73:12] wire [3:0] anonOut_a_bits_mask_hi_1 = {anonOut_a_bits_mask_hi_hi_1, anonOut_a_bits_mask_hi_lo_1}; // @[WidthWidget.scala:73:12] wire [7:0] _anonOut_a_bits_mask_T_4 = {anonOut_a_bits_mask_hi_1, anonOut_a_bits_mask_lo_1}; // @[WidthWidget.scala:73:12] wire [7:0] _anonOut_a_bits_mask_T_6 = hasData ? _anonOut_a_bits_mask_T_4 : 8'hFF; // @[WidthWidget.scala:73:12, :85:93] assign _anonOut_a_bits_mask_T_7 = _anonOut_a_bits_mask_T & _anonOut_a_bits_mask_T_6; // @[Misc.scala:222:10] assign anonOut_a_bits_mask = _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonIn_d_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_sink = cated_bits_sink; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_denied = cated_bits_denied; // @[WidthWidget.scala:161:25] wire [63:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonIn_d_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [63:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [55:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[63:8]; // @[Repeater.scala:36:26] wire [7:0] _cated_bits_data_T_1 = anonOut_d_bits_data[7:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire repeat_hasData = cated_bits_opcode[0]; // @[WidthWidget.scala:161:25] wire [17:0] _repeat_limit_T = 18'h7 << cated_bits_size; // @[package.scala:243:71] wire [2:0] _repeat_limit_T_1 = _repeat_limit_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire [2:0] repeat_limit = _repeat_limit_T_2; // @[package.scala:243:46] reg [2:0] repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = repeat_count == 3'h0; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35] wire [3:0] _repeat_count_T = {1'h0, repeat_count} + 4'h1; // @[WidthWidget.scala:105:26, :110:24] wire [2:0] _repeat_count_T_1 = _repeat_count_T[2:0]; // @[WidthWidget.scala:110:24] reg [2:0] repeat_sel_sel_sources_0; // @[WidthWidget.scala:187:27] wire [2:0] repeat_sel_sel_a_sel = anonIn_a_bits_address[2:0]; // @[WidthWidget.scala:188:38] reg [2:0] repeat_sel_hold_r; // @[WidthWidget.scala:121:47] wire [2:0] repeat_sel_hold = repeat_first ? repeat_sel_sel_sources_0 : repeat_sel_hold_r; // @[WidthWidget.scala:106:25, :121:{25,47}, :187:27] wire [2:0] _repeat_sel_T = ~repeat_limit; // @[WidthWidget.scala:103:47, :122:18] wire [2:0] repeat_sel = repeat_sel_hold & _repeat_sel_T; // @[WidthWidget.scala:121:25, :122:{16,18}] wire [2:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :122:16, :126:24] wire [7:0] _repeat_anonIn_d_bits_data_mux_T = cated_bits_data[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_0 = _repeat_anonIn_d_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_1 = cated_bits_data[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_1 = _repeat_anonIn_d_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_2 = cated_bits_data[23:16]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_2 = _repeat_anonIn_d_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_3 = cated_bits_data[31:24]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_3 = _repeat_anonIn_d_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_4 = cated_bits_data[39:32]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_4 = _repeat_anonIn_d_bits_data_mux_T_4; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_5 = cated_bits_data[47:40]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_5 = _repeat_anonIn_d_bits_data_mux_T_5; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_6 = cated_bits_data[55:48]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_6 = _repeat_anonIn_d_bits_data_mux_T_6; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonIn_d_bits_data_mux_T_7 = cated_bits_data[63:56]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonIn_d_bits_data_mux_7 = _repeat_anonIn_d_bits_data_mux_T_7; // @[WidthWidget.scala:128:{43,55}] wire [7:0][7:0] _GEN = {{repeat_anonIn_d_bits_data_mux_7}, {repeat_anonIn_d_bits_data_mux_6}, {repeat_anonIn_d_bits_data_mux_5}, {repeat_anonIn_d_bits_data_mux_4}, {repeat_anonIn_d_bits_data_mux_3}, {repeat_anonIn_d_bits_data_mux_2}, {repeat_anonIn_d_bits_data_mux_1}, {repeat_anonIn_d_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30] assign anonIn_d_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] count <= 3'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonOut_a_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] anonOut_a_bits_mask_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] repeat_count <= 3'h0; // @[WidthWidget.scala:105:26] end else begin // @[WidthWidget.scala:27:9] if (_T) begin // @[Decoupled.scala:51:35] count <= last ? 3'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23] end anonOut_a_bits_data_rdata_written_once <= _anonOut_a_bits_data_T_2 | anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] anonOut_a_bits_mask_rdata_written_once <= _anonOut_a_bits_mask_T_3 | anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= repeat_last ? 3'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] end if (_anonOut_a_bits_data_T_2) begin // @[WidthWidget.scala:69:23] anonOut_a_bits_data_rdata_0 <= anonOut_a_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_1 <= anonOut_a_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_2 <= anonOut_a_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_3 <= anonOut_a_bits_data_mdata_3; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_4 <= anonOut_a_bits_data_mdata_4; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_5 <= anonOut_a_bits_data_mdata_5; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_data_rdata_6 <= anonOut_a_bits_data_mdata_6; // @[WidthWidget.scala:66:24, :68:88] end if (_anonOut_a_bits_mask_T_3) begin // @[WidthWidget.scala:69:23] anonOut_a_bits_mask_rdata_0 <= anonOut_a_bits_mask_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_1 <= anonOut_a_bits_mask_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_2 <= anonOut_a_bits_mask_mdata_2; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_3 <= anonOut_a_bits_mask_mdata_3; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_4 <= anonOut_a_bits_mask_mdata_4; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_5 <= anonOut_a_bits_mask_mdata_5; // @[WidthWidget.scala:66:24, :68:88] anonOut_a_bits_mask_rdata_6 <= anonOut_a_bits_mask_mdata_6; // @[WidthWidget.scala:66:24, :68:88] end if (_repeat_sel_sel_T) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_0 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (repeat_first) // @[WidthWidget.scala:106:25] repeat_sel_hold_r <= repeat_sel_sel_sources_0; // @[WidthWidget.scala:121:47, :187:27] always @(posedge) TLMonitor_11 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleD_a32d64s1k3z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonOut_d_ready), .io_enq_valid (anonOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (anonOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (anonOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (anonOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_sink (anonOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (anonOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (anonOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (anonOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_sink (cated_bits_sink), .io_deq_bits_denied (cated_bits_denied), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_54 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_108 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_109 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_110 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 1 parameter FORMAT = "uart_tx=%d" parameter WIDTH = 32 extmodule plusarg_reader_111 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "uart_tx_printf=%d" parameter WIDTH = 32

module TLMonitor_54( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_6 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}} wire _in_flight_WIRE : UInt<1>[10] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) connect _in_flight_WIRE[8], UInt<1>(0h0) connect _in_flight_WIRE[9], UInt<1>(0h0) regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_33 = and(_T_31, _T_32) node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_40 = and(_T_38, _T_39) node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_49 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_66 = and(_T_64, _T_65) node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_71 = and(_T_69, _T_70) node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_73 = and(_T_71, _T_72) node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_75 = and(_T_73, _T_74) node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_78 = and(_T_76, _T_77) node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(_T_12, _T_19) node _T_91 = or(_T_90, _T_26) node _T_92 = or(_T_91, _T_33) node _T_93 = or(_T_92, _T_40) node _T_94 = or(_T_93, _T_47) node _T_95 = or(_T_94, _T_54) node _T_96 = or(_T_95, _T_61) node _T_97 = or(_T_96, _T_68) node _T_98 = or(_T_97, _T_75) node _T_99 = or(_T_98, _T_82) node _T_100 = or(_T_99, _T_89) node _T_101 = or(_T_5, _T_100) node _T_102 = asUInt(reset) node _T_103 = eq(_T_102, UInt<1>(0h0)) when _T_103 : node _T_104 = eq(_T_101, UInt<1>(0h0)) when _T_104 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_101, UInt<1>(0h1), "") : assert_1 node _T_105 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_107 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_112 = and(_T_110, _T_111) node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_114 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_121 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_122 = and(_T_120, _T_121) node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_128 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_135 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_136 = and(_T_134, _T_135) node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_142 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_145 = and(_T_143, _T_144) node _T_146 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_149 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_150 = and(_T_148, _T_149) node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_152 = and(_T_150, _T_151) node _T_153 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_156 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_157 = and(_T_155, _T_156) node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_163 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_170 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_177 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_180 = and(_T_178, _T_179) node _T_181 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_184 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_187 = and(_T_185, _T_186) node _T_188 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = or(_T_112, _T_119) node _T_191 = or(_T_190, _T_126) node _T_192 = or(_T_191, _T_133) node _T_193 = or(_T_192, _T_140) node _T_194 = or(_T_193, _T_147) node _T_195 = or(_T_194, _T_154) node _T_196 = or(_T_195, _T_161) node _T_197 = or(_T_196, _T_168) node _T_198 = or(_T_197, _T_175) node _T_199 = or(_T_198, _T_182) node _T_200 = or(_T_199, _T_189) node _T_201 = or(_T_105, _T_200) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_201, UInt<1>(0h1), "") : assert_2 node _T_205 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_206 = or(_T_205, UInt<1>(0h0)) node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_T_206, UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_206, UInt<1>(0h1), "") : assert_3 node _T_210 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_211 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_212 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_213 = and(_T_211, _T_212) node _T_214 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_215 = and(_T_213, _T_214) node _T_216 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_219 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_220 = and(_T_218, _T_219) node _T_221 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_226 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_229 = and(_T_227, _T_228) node _T_230 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_233 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_236 = and(_T_234, _T_235) node _T_237 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_240 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _T_242 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_243 = and(_T_241, _T_242) node _T_244 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_247 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_248 = and(_T_246, _T_247) node _T_249 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_254 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_255 = and(_T_253, _T_254) node _T_256 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_257 = and(_T_255, _T_256) node _T_258 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_261 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_268 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_269 = and(_T_267, _T_268) node _T_270 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_271 = and(_T_269, _T_270) node _T_272 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_273 = and(_T_271, _T_272) node _T_274 = or(_T_217, _T_224) node _T_275 = or(_T_274, _T_231) node _T_276 = or(_T_275, _T_238) node _T_277 = or(_T_276, _T_245) node _T_278 = or(_T_277, _T_252) node _T_279 = or(_T_278, _T_259) node _T_280 = or(_T_279, _T_266) node _T_281 = or(_T_280, _T_273) node _T_282 = or(_T_210, _T_281) node _T_283 = asUInt(reset) node _T_284 = eq(_T_283, UInt<1>(0h0)) when _T_284 : node _T_285 = eq(_T_282, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_282, UInt<1>(0h1), "") : assert_4 node _T_286 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_287 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_288 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_289 = and(_T_287, _T_288) node _T_290 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_291 = and(_T_289, _T_290) node _T_292 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_295 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_302 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_303 = and(_T_301, _T_302) node _T_304 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_305 = and(_T_303, _T_304) node _T_306 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_309 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_310 = and(_T_308, _T_309) node _T_311 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_312 = and(_T_310, _T_311) node _T_313 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_316 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_317 = and(_T_315, _T_316) node _T_318 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_323 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_328 = and(_T_326, _T_327) node _T_329 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_330 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_331 = and(_T_329, _T_330) node _T_332 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_335 = and(_T_333, _T_334) node _T_336 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_337 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_338 = and(_T_336, _T_337) node _T_339 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_340 = and(_T_338, _T_339) node _T_341 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_342 = and(_T_340, _T_341) node _T_343 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_344 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_345 = and(_T_343, _T_344) node _T_346 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_349 = and(_T_347, _T_348) node _T_350 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_351 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_354 = and(_T_352, _T_353) node _T_355 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_356 = and(_T_354, _T_355) node _T_357 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_358 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_359 = and(_T_357, _T_358) node _T_360 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_361 = and(_T_359, _T_360) node _T_362 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_363 = and(_T_361, _T_362) node _T_364 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_365 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_366 = and(_T_364, _T_365) node _T_367 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_368 = and(_T_366, _T_367) node _T_369 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(_T_293, _T_300) node _T_372 = or(_T_371, _T_307) node _T_373 = or(_T_372, _T_314) node _T_374 = or(_T_373, _T_321) node _T_375 = or(_T_374, _T_328) node _T_376 = or(_T_375, _T_335) node _T_377 = or(_T_376, _T_342) node _T_378 = or(_T_377, _T_349) node _T_379 = or(_T_378, _T_356) node _T_380 = or(_T_379, _T_363) node _T_381 = or(_T_380, _T_370) node _T_382 = or(_T_286, _T_381) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_382, UInt<1>(0h1), "") : assert_5 node _T_386 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_387 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_388 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_389 = and(_T_387, _T_388) node _T_390 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_391 = and(_T_389, _T_390) node _T_392 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_395 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_398 = and(_T_396, _T_397) node _T_399 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_400 = and(_T_398, _T_399) node _T_401 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_402 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_405 = and(_T_403, _T_404) node _T_406 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_409 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_414 = and(_T_412, _T_413) node _T_415 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_416 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_421 = and(_T_419, _T_420) node _T_422 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_423 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_428 = and(_T_426, _T_427) node _T_429 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_430 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_435 = and(_T_433, _T_434) node _T_436 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_437 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_440 = and(_T_438, _T_439) node _T_441 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_442 = and(_T_440, _T_441) node _T_443 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_444 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_445 = and(_T_443, _T_444) node _T_446 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_447 = and(_T_445, _T_446) node _T_448 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_449 = and(_T_447, _T_448) node _T_450 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_451 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_452 = and(_T_450, _T_451) node _T_453 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_454 = and(_T_452, _T_453) node _T_455 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_456 = and(_T_454, _T_455) node _T_457 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_458 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_461 = and(_T_459, _T_460) node _T_462 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_463 = and(_T_461, _T_462) node _T_464 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_465 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_466 = and(_T_464, _T_465) node _T_467 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_470 = and(_T_468, _T_469) node _T_471 = or(_T_393, _T_400) node _T_472 = or(_T_471, _T_407) node _T_473 = or(_T_472, _T_414) node _T_474 = or(_T_473, _T_421) node _T_475 = or(_T_474, _T_428) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_442) node _T_478 = or(_T_477, _T_449) node _T_479 = or(_T_478, _T_456) node _T_480 = or(_T_479, _T_463) node _T_481 = or(_T_480, _T_470) node _T_482 = or(_T_386, _T_481) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_482, UInt<1>(0h1), "") : assert_6 node _T_486 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_487 = or(_T_486, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_487, UInt<1>(0h1), "") : assert_7 node _T_491 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_492 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_493 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_496 = and(_T_494, _T_495) node _T_497 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_498 = and(_T_496, _T_497) node _T_499 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_500 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_503 = and(_T_501, _T_502) node _T_504 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_505 = and(_T_503, _T_504) node _T_506 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_507 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_510 = and(_T_508, _T_509) node _T_511 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_512 = and(_T_510, _T_511) node _T_513 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_514 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_517 = and(_T_515, _T_516) node _T_518 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_519 = and(_T_517, _T_518) node _T_520 = or(_T_498, _T_505) node _T_521 = or(_T_520, _T_512) node _T_522 = or(_T_521, _T_519) node _T_523 = or(_T_491, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_523, UInt<1>(0h1), "") : assert_8 node _T_527 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_528 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_529 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_530 = and(_T_528, _T_529) node _T_531 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_532 = and(_T_530, _T_531) node _T_533 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_534 = and(_T_532, _T_533) node _T_535 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_536 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_539 = and(_T_537, _T_538) node _T_540 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_541 = and(_T_539, _T_540) node _T_542 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_543 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _T_547 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_548 = and(_T_546, _T_547) node _T_549 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_550 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_553 = and(_T_551, _T_552) node _T_554 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) node _T_556 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_557 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_558 = and(_T_556, _T_557) node _T_559 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_560 = and(_T_558, _T_559) node _T_561 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_562 = and(_T_560, _T_561) node _T_563 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_564 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_565 = and(_T_563, _T_564) node _T_566 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_567 = and(_T_565, _T_566) node _T_568 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_571 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_572 = and(_T_570, _T_571) node _T_573 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_574 = and(_T_572, _T_573) node _T_575 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_576 = and(_T_574, _T_575) node _T_577 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_578 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_579 = and(_T_577, _T_578) node _T_580 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_581 = and(_T_579, _T_580) node _T_582 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_583 = and(_T_581, _T_582) node _T_584 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_585 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_588 = and(_T_586, _T_587) node _T_589 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_590 = and(_T_588, _T_589) node _T_591 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_592 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_593 = and(_T_591, _T_592) node _T_594 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_595 = and(_T_593, _T_594) node _T_596 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_597 = and(_T_595, _T_596) node _T_598 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_599 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_600 = and(_T_598, _T_599) node _T_601 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_602 = and(_T_600, _T_601) node _T_603 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_604 = and(_T_602, _T_603) node _T_605 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_606 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_609 = and(_T_607, _T_608) node _T_610 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_611 = and(_T_609, _T_610) node _T_612 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_613 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_614 = and(_T_612, _T_613) node _T_615 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_616 = and(_T_614, _T_615) node _T_617 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_620 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_621 = and(_T_619, _T_620) node _T_622 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_623 = and(_T_621, _T_622) node _T_624 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_625 = and(_T_623, _T_624) node _T_626 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_627 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_628 = and(_T_626, _T_627) node _T_629 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_630 = and(_T_628, _T_629) node _T_631 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_632 = and(_T_630, _T_631) node _T_633 = or(_T_534, _T_541) node _T_634 = or(_T_633, _T_548) node _T_635 = or(_T_634, _T_555) node _T_636 = or(_T_635, _T_562) node _T_637 = or(_T_636, _T_569) node _T_638 = or(_T_637, _T_576) node _T_639 = or(_T_638, _T_583) node _T_640 = or(_T_639, _T_590) node _T_641 = or(_T_640, _T_597) node _T_642 = or(_T_641, _T_604) node _T_643 = or(_T_642, _T_611) node _T_644 = or(_T_643, _T_618) node _T_645 = or(_T_644, _T_625) node _T_646 = or(_T_645, _T_632) node _T_647 = or(_T_527, _T_646) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_9 assert(clock, _T_647, UInt<1>(0h1), "") : assert_9 node _T_651 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9)) node _T_652 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_653 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_654 = and(_T_652, _T_653) node _T_655 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_656 = and(_T_654, _T_655) node _T_657 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_658 = and(_T_656, _T_657) node _T_659 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_660 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_661 = and(_T_659, _T_660) node _T_662 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_663 = and(_T_661, _T_662) node _T_664 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_665 = and(_T_663, _T_664) node _T_666 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_667 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_668 = and(_T_666, _T_667) node _T_669 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_670 = and(_T_668, _T_669) node _T_671 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_672 = and(_T_670, _T_671) node _T_673 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_674 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_675 = and(_T_673, _T_674) node _T_676 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_677 = and(_T_675, _T_676) node _T_678 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_679 = and(_T_677, _T_678) node _T_680 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_681 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_682 = and(_T_680, _T_681) node _T_683 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_684 = and(_T_682, _T_683) node _T_685 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_686 = and(_T_684, _T_685) node _T_687 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_688 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_689 = and(_T_687, _T_688) node _T_690 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_691 = and(_T_689, _T_690) node _T_692 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_693 = and(_T_691, _T_692) node _T_694 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_695 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_696 = and(_T_694, _T_695) node _T_697 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_698 = and(_T_696, _T_697) node _T_699 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_700 = and(_T_698, _T_699) node _T_701 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_702 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_703 = and(_T_701, _T_702) node _T_704 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_705 = and(_T_703, _T_704) node _T_706 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_707 = and(_T_705, _T_706) node _T_708 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_709 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_710 = and(_T_708, _T_709) node _T_711 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_714 = and(_T_712, _T_713) node _T_715 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_716 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_717 = and(_T_715, _T_716) node _T_718 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_719 = and(_T_717, _T_718) node _T_720 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_721 = and(_T_719, _T_720) node _T_722 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_723 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_726 = and(_T_724, _T_725) node _T_727 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_728 = and(_T_726, _T_727) node _T_729 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_730 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_731 = and(_T_729, _T_730) node _T_732 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_733 = and(_T_731, _T_732) node _T_734 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_735 = and(_T_733, _T_734) node _T_736 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_737 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_738 = and(_T_736, _T_737) node _T_739 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_740 = and(_T_738, _T_739) node _T_741 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_742 = and(_T_740, _T_741) node _T_743 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_744 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_745 = and(_T_743, _T_744) node _T_746 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_751 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_756 = and(_T_754, _T_755) node _T_757 = or(_T_658, _T_665) node _T_758 = or(_T_757, _T_672) node _T_759 = or(_T_758, _T_679) node _T_760 = or(_T_759, _T_686) node _T_761 = or(_T_760, _T_693) node _T_762 = or(_T_761, _T_700) node _T_763 = or(_T_762, _T_707) node _T_764 = or(_T_763, _T_714) node _T_765 = or(_T_764, _T_721) node _T_766 = or(_T_765, _T_728) node _T_767 = or(_T_766, _T_735) node _T_768 = or(_T_767, _T_742) node _T_769 = or(_T_768, _T_749) node _T_770 = or(_T_769, _T_756) node _T_771 = or(_T_651, _T_770) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_10 assert(clock, _T_771, UInt<1>(0h1), "") : assert_10

module NoCMonitor_6( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h2; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h6; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to this FIRRTL code module TestHarness : input clock : Clock input reset : UInt<1> output io : { success : UInt<1>} wire harnessBinderClock : Clock wire harnessBinderReset : Reset wire success : UInt<1> connect success, UInt<1>(0h0) connect io.success, success inst chiptop0 of ChipTop inst uart_sim_0_uartno0 of UARTAdapter connect uart_sim_0_uartno0.clock, harnessBinderClock connect uart_sim_0_uartno0.reset, harnessBinderReset connect uart_sim_0_uartno0.io.uart.txd, chiptop0.uart_0.txd connect chiptop0.uart_0.rxd, uart_sim_0_uartno0.io.uart.rxd inst simdram of SimDRAM connect simdram.clock, chiptop0.axi4_mem_0.clock node _simdram_io_reset_T = asAsyncReset(harnessBinderReset) connect simdram.reset, _simdram_io_reset_T connect chiptop0.axi4_mem_0.bits.r.bits.last, simdram.axi.r.bits.last connect chiptop0.axi4_mem_0.bits.r.bits.resp, simdram.axi.r.bits.resp connect chiptop0.axi4_mem_0.bits.r.bits.data, simdram.axi.r.bits.data connect chiptop0.axi4_mem_0.bits.r.bits.id, simdram.axi.r.bits.id connect chiptop0.axi4_mem_0.bits.r.valid, simdram.axi.r.valid connect simdram.axi.r.ready, chiptop0.axi4_mem_0.bits.r.ready connect simdram.axi.ar.bits.qos, chiptop0.axi4_mem_0.bits.ar.bits.qos connect simdram.axi.ar.bits.prot, chiptop0.axi4_mem_0.bits.ar.bits.prot connect simdram.axi.ar.bits.cache, chiptop0.axi4_mem_0.bits.ar.bits.cache connect simdram.axi.ar.bits.lock, chiptop0.axi4_mem_0.bits.ar.bits.lock connect simdram.axi.ar.bits.burst, chiptop0.axi4_mem_0.bits.ar.bits.burst connect simdram.axi.ar.bits.size, chiptop0.axi4_mem_0.bits.ar.bits.size connect simdram.axi.ar.bits.len, chiptop0.axi4_mem_0.bits.ar.bits.len connect simdram.axi.ar.bits.addr, chiptop0.axi4_mem_0.bits.ar.bits.addr connect simdram.axi.ar.bits.id, chiptop0.axi4_mem_0.bits.ar.bits.id connect simdram.axi.ar.valid, chiptop0.axi4_mem_0.bits.ar.valid connect chiptop0.axi4_mem_0.bits.ar.ready, simdram.axi.ar.ready connect chiptop0.axi4_mem_0.bits.b.bits.resp, simdram.axi.b.bits.resp connect chiptop0.axi4_mem_0.bits.b.bits.id, simdram.axi.b.bits.id connect chiptop0.axi4_mem_0.bits.b.valid, simdram.axi.b.valid connect simdram.axi.b.ready, chiptop0.axi4_mem_0.bits.b.ready connect simdram.axi.w.bits.last, chiptop0.axi4_mem_0.bits.w.bits.last connect simdram.axi.w.bits.strb, chiptop0.axi4_mem_0.bits.w.bits.strb connect simdram.axi.w.bits.data, chiptop0.axi4_mem_0.bits.w.bits.data connect simdram.axi.w.valid, chiptop0.axi4_mem_0.bits.w.valid connect chiptop0.axi4_mem_0.bits.w.ready, simdram.axi.w.ready connect simdram.axi.aw.bits.qos, chiptop0.axi4_mem_0.bits.aw.bits.qos connect simdram.axi.aw.bits.prot, chiptop0.axi4_mem_0.bits.aw.bits.prot connect simdram.axi.aw.bits.cache, chiptop0.axi4_mem_0.bits.aw.bits.cache connect simdram.axi.aw.bits.lock, chiptop0.axi4_mem_0.bits.aw.bits.lock connect simdram.axi.aw.bits.burst, chiptop0.axi4_mem_0.bits.aw.bits.burst connect simdram.axi.aw.bits.size, chiptop0.axi4_mem_0.bits.aw.bits.size connect simdram.axi.aw.bits.len, chiptop0.axi4_mem_0.bits.aw.bits.len connect simdram.axi.aw.bits.addr, chiptop0.axi4_mem_0.bits.aw.bits.addr connect simdram.axi.aw.bits.id, chiptop0.axi4_mem_0.bits.aw.bits.id connect simdram.axi.aw.valid, chiptop0.axi4_mem_0.bits.aw.valid connect chiptop0.axi4_mem_0.bits.aw.ready, simdram.axi.aw.ready inst simdram_1 of SimDRAM_1 connect simdram_1.clock, chiptop0.axi4_mem_1.clock node _simdram_io_reset_T_1 = asAsyncReset(harnessBinderReset) connect simdram_1.reset, _simdram_io_reset_T_1 connect chiptop0.axi4_mem_1.bits.r.bits.last, simdram_1.axi.r.bits.last connect chiptop0.axi4_mem_1.bits.r.bits.resp, simdram_1.axi.r.bits.resp connect chiptop0.axi4_mem_1.bits.r.bits.data, simdram_1.axi.r.bits.data connect chiptop0.axi4_mem_1.bits.r.bits.id, simdram_1.axi.r.bits.id connect chiptop0.axi4_mem_1.bits.r.valid, simdram_1.axi.r.valid connect simdram_1.axi.r.ready, chiptop0.axi4_mem_1.bits.r.ready connect simdram_1.axi.ar.bits.qos, chiptop0.axi4_mem_1.bits.ar.bits.qos connect simdram_1.axi.ar.bits.prot, chiptop0.axi4_mem_1.bits.ar.bits.prot connect simdram_1.axi.ar.bits.cache, chiptop0.axi4_mem_1.bits.ar.bits.cache connect simdram_1.axi.ar.bits.lock, chiptop0.axi4_mem_1.bits.ar.bits.lock connect simdram_1.axi.ar.bits.burst, chiptop0.axi4_mem_1.bits.ar.bits.burst connect simdram_1.axi.ar.bits.size, chiptop0.axi4_mem_1.bits.ar.bits.size connect simdram_1.axi.ar.bits.len, chiptop0.axi4_mem_1.bits.ar.bits.len connect simdram_1.axi.ar.bits.addr, chiptop0.axi4_mem_1.bits.ar.bits.addr connect simdram_1.axi.ar.bits.id, chiptop0.axi4_mem_1.bits.ar.bits.id connect simdram_1.axi.ar.valid, chiptop0.axi4_mem_1.bits.ar.valid connect chiptop0.axi4_mem_1.bits.ar.ready, simdram_1.axi.ar.ready connect chiptop0.axi4_mem_1.bits.b.bits.resp, simdram_1.axi.b.bits.resp connect chiptop0.axi4_mem_1.bits.b.bits.id, simdram_1.axi.b.bits.id connect chiptop0.axi4_mem_1.bits.b.valid, simdram_1.axi.b.valid connect simdram_1.axi.b.ready, chiptop0.axi4_mem_1.bits.b.ready connect simdram_1.axi.w.bits.last, chiptop0.axi4_mem_1.bits.w.bits.last connect simdram_1.axi.w.bits.strb, chiptop0.axi4_mem_1.bits.w.bits.strb connect simdram_1.axi.w.bits.data, chiptop0.axi4_mem_1.bits.w.bits.data connect simdram_1.axi.w.valid, chiptop0.axi4_mem_1.bits.w.valid connect chiptop0.axi4_mem_1.bits.w.ready, simdram_1.axi.w.ready connect simdram_1.axi.aw.bits.qos, chiptop0.axi4_mem_1.bits.aw.bits.qos connect simdram_1.axi.aw.bits.prot, chiptop0.axi4_mem_1.bits.aw.bits.prot connect simdram_1.axi.aw.bits.cache, chiptop0.axi4_mem_1.bits.aw.bits.cache connect simdram_1.axi.aw.bits.lock, chiptop0.axi4_mem_1.bits.aw.bits.lock connect simdram_1.axi.aw.bits.burst, chiptop0.axi4_mem_1.bits.aw.bits.burst connect simdram_1.axi.aw.bits.size, chiptop0.axi4_mem_1.bits.aw.bits.size connect simdram_1.axi.aw.bits.len, chiptop0.axi4_mem_1.bits.aw.bits.len connect simdram_1.axi.aw.bits.addr, chiptop0.axi4_mem_1.bits.aw.bits.addr connect simdram_1.axi.aw.bits.id, chiptop0.axi4_mem_1.bits.aw.bits.id connect simdram_1.axi.aw.valid, chiptop0.axi4_mem_1.bits.aw.valid connect chiptop0.axi4_mem_1.bits.aw.ready, simdram_1.axi.aw.ready inst simdram_2 of SimDRAM_2 connect simdram_2.clock, chiptop0.axi4_mem_2.clock node _simdram_io_reset_T_2 = asAsyncReset(harnessBinderReset) connect simdram_2.reset, _simdram_io_reset_T_2 connect chiptop0.axi4_mem_2.bits.r.bits.last, simdram_2.axi.r.bits.last connect chiptop0.axi4_mem_2.bits.r.bits.resp, simdram_2.axi.r.bits.resp connect chiptop0.axi4_mem_2.bits.r.bits.data, simdram_2.axi.r.bits.data connect chiptop0.axi4_mem_2.bits.r.bits.id, simdram_2.axi.r.bits.id connect chiptop0.axi4_mem_2.bits.r.valid, simdram_2.axi.r.valid connect simdram_2.axi.r.ready, chiptop0.axi4_mem_2.bits.r.ready connect simdram_2.axi.ar.bits.qos, chiptop0.axi4_mem_2.bits.ar.bits.qos connect simdram_2.axi.ar.bits.prot, chiptop0.axi4_mem_2.bits.ar.bits.prot connect simdram_2.axi.ar.bits.cache, chiptop0.axi4_mem_2.bits.ar.bits.cache connect simdram_2.axi.ar.bits.lock, chiptop0.axi4_mem_2.bits.ar.bits.lock connect simdram_2.axi.ar.bits.burst, chiptop0.axi4_mem_2.bits.ar.bits.burst connect simdram_2.axi.ar.bits.size, chiptop0.axi4_mem_2.bits.ar.bits.size connect simdram_2.axi.ar.bits.len, chiptop0.axi4_mem_2.bits.ar.bits.len connect simdram_2.axi.ar.bits.addr, chiptop0.axi4_mem_2.bits.ar.bits.addr connect simdram_2.axi.ar.bits.id, chiptop0.axi4_mem_2.bits.ar.bits.id connect simdram_2.axi.ar.valid, chiptop0.axi4_mem_2.bits.ar.valid connect chiptop0.axi4_mem_2.bits.ar.ready, simdram_2.axi.ar.ready connect chiptop0.axi4_mem_2.bits.b.bits.resp, simdram_2.axi.b.bits.resp connect chiptop0.axi4_mem_2.bits.b.bits.id, simdram_2.axi.b.bits.id connect chiptop0.axi4_mem_2.bits.b.valid, simdram_2.axi.b.valid connect simdram_2.axi.b.ready, chiptop0.axi4_mem_2.bits.b.ready connect simdram_2.axi.w.bits.last, chiptop0.axi4_mem_2.bits.w.bits.last connect simdram_2.axi.w.bits.strb, chiptop0.axi4_mem_2.bits.w.bits.strb connect simdram_2.axi.w.bits.data, chiptop0.axi4_mem_2.bits.w.bits.data connect simdram_2.axi.w.valid, chiptop0.axi4_mem_2.bits.w.valid connect chiptop0.axi4_mem_2.bits.w.ready, simdram_2.axi.w.ready connect simdram_2.axi.aw.bits.qos, chiptop0.axi4_mem_2.bits.aw.bits.qos connect simdram_2.axi.aw.bits.prot, chiptop0.axi4_mem_2.bits.aw.bits.prot connect simdram_2.axi.aw.bits.cache, chiptop0.axi4_mem_2.bits.aw.bits.cache connect simdram_2.axi.aw.bits.lock, chiptop0.axi4_mem_2.bits.aw.bits.lock connect simdram_2.axi.aw.bits.burst, chiptop0.axi4_mem_2.bits.aw.bits.burst connect simdram_2.axi.aw.bits.size, chiptop0.axi4_mem_2.bits.aw.bits.size connect simdram_2.axi.aw.bits.len, chiptop0.axi4_mem_2.bits.aw.bits.len connect simdram_2.axi.aw.bits.addr, chiptop0.axi4_mem_2.bits.aw.bits.addr connect simdram_2.axi.aw.bits.id, chiptop0.axi4_mem_2.bits.aw.bits.id connect simdram_2.axi.aw.valid, chiptop0.axi4_mem_2.bits.aw.valid connect chiptop0.axi4_mem_2.bits.aw.ready, simdram_2.axi.aw.ready inst simdram_3 of SimDRAM_3 connect simdram_3.clock, chiptop0.axi4_mem_3.clock node _simdram_io_reset_T_3 = asAsyncReset(harnessBinderReset) connect simdram_3.reset, _simdram_io_reset_T_3 connect chiptop0.axi4_mem_3.bits.r.bits.last, simdram_3.axi.r.bits.last connect chiptop0.axi4_mem_3.bits.r.bits.resp, simdram_3.axi.r.bits.resp connect chiptop0.axi4_mem_3.bits.r.bits.data, simdram_3.axi.r.bits.data connect chiptop0.axi4_mem_3.bits.r.bits.id, simdram_3.axi.r.bits.id connect chiptop0.axi4_mem_3.bits.r.valid, simdram_3.axi.r.valid connect simdram_3.axi.r.ready, chiptop0.axi4_mem_3.bits.r.ready connect simdram_3.axi.ar.bits.qos, chiptop0.axi4_mem_3.bits.ar.bits.qos connect simdram_3.axi.ar.bits.prot, chiptop0.axi4_mem_3.bits.ar.bits.prot connect simdram_3.axi.ar.bits.cache, chiptop0.axi4_mem_3.bits.ar.bits.cache connect simdram_3.axi.ar.bits.lock, chiptop0.axi4_mem_3.bits.ar.bits.lock connect simdram_3.axi.ar.bits.burst, chiptop0.axi4_mem_3.bits.ar.bits.burst connect simdram_3.axi.ar.bits.size, chiptop0.axi4_mem_3.bits.ar.bits.size connect simdram_3.axi.ar.bits.len, chiptop0.axi4_mem_3.bits.ar.bits.len connect simdram_3.axi.ar.bits.addr, chiptop0.axi4_mem_3.bits.ar.bits.addr connect simdram_3.axi.ar.bits.id, chiptop0.axi4_mem_3.bits.ar.bits.id connect simdram_3.axi.ar.valid, chiptop0.axi4_mem_3.bits.ar.valid connect chiptop0.axi4_mem_3.bits.ar.ready, simdram_3.axi.ar.ready connect chiptop0.axi4_mem_3.bits.b.bits.resp, simdram_3.axi.b.bits.resp connect chiptop0.axi4_mem_3.bits.b.bits.id, simdram_3.axi.b.bits.id connect chiptop0.axi4_mem_3.bits.b.valid, simdram_3.axi.b.valid connect simdram_3.axi.b.ready, chiptop0.axi4_mem_3.bits.b.ready connect simdram_3.axi.w.bits.last, chiptop0.axi4_mem_3.bits.w.bits.last connect simdram_3.axi.w.bits.strb, chiptop0.axi4_mem_3.bits.w.bits.strb connect simdram_3.axi.w.bits.data, chiptop0.axi4_mem_3.bits.w.bits.data connect simdram_3.axi.w.valid, chiptop0.axi4_mem_3.bits.w.valid connect chiptop0.axi4_mem_3.bits.w.ready, simdram_3.axi.w.ready connect simdram_3.axi.aw.bits.qos, chiptop0.axi4_mem_3.bits.aw.bits.qos connect simdram_3.axi.aw.bits.prot, chiptop0.axi4_mem_3.bits.aw.bits.prot connect simdram_3.axi.aw.bits.cache, chiptop0.axi4_mem_3.bits.aw.bits.cache connect simdram_3.axi.aw.bits.lock, chiptop0.axi4_mem_3.bits.aw.bits.lock connect simdram_3.axi.aw.bits.burst, chiptop0.axi4_mem_3.bits.aw.bits.burst connect simdram_3.axi.aw.bits.size, chiptop0.axi4_mem_3.bits.aw.bits.size connect simdram_3.axi.aw.bits.len, chiptop0.axi4_mem_3.bits.aw.bits.len connect simdram_3.axi.aw.bits.addr, chiptop0.axi4_mem_3.bits.aw.bits.addr connect simdram_3.axi.aw.bits.id, chiptop0.axi4_mem_3.bits.aw.bits.id connect simdram_3.axi.aw.valid, chiptop0.axi4_mem_3.bits.aw.valid connect chiptop0.axi4_mem_3.bits.aw.ready, simdram_3.axi.aw.ready inst plusarg_reader of plusarg_reader_215 connect chiptop0.custom_boot, plusarg_reader.out wire dtm_success : UInt<1> connect dtm_success, UInt<1>(0h0) when dtm_success : connect success, UInt<1>(0h1) wire jtag_wire : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}} connect jtag_wire.TDO.data, chiptop0.jtag.TDO connect jtag_wire.TDO.driven, UInt<1>(0h1) connect chiptop0.jtag.TCK, jtag_wire.TCK connect chiptop0.jtag.TMS, jtag_wire.TMS connect chiptop0.jtag.TDI, jtag_wire.TDI inst jtag of SimJTAG node _T = asUInt(harnessBinderReset) node _T_1 = asUInt(harnessBinderReset) node _T_2 = not(_T_1) connect jtag_wire.TCK, jtag.jtag.TCK connect jtag_wire.TMS, jtag.jtag.TMS connect jtag_wire.TDI, jtag.jtag.TDI connect jtag.jtag.TDO.driven, jtag_wire.TDO.driven connect jtag.jtag.TDO.data, jtag_wire.TDO.data connect jtag.clock, harnessBinderClock connect jtag.reset, _T inst plusarg_reader_1 of plusarg_reader_216 connect jtag.enable, plusarg_reader_1.out connect jtag.init_done, _T_2 node _dtm_success_T = eq(jtag.exit, UInt<1>(0h1)) connect dtm_success, _dtm_success_T node _T_3 = lt(jtag.exit, UInt<2>(0h2)) node _T_4 = dshr(jtag.exit, UInt<1>(0h1)) node _T_5 = asUInt(harnessBinderReset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_3, UInt<1>(0h0)) when _T_7 : printf(harnessBinderClock, UInt<1>(0h1), "Assertion failed: *** FAILED *** (exit code = %d)\n\n at Periphery.scala:236 assert(io.exit < 2.U, \"*** FAILED *** (exit code = %%%%d)\\n\", io.exit >> 1.U)\n", _T_4) : printf assert(harnessBinderClock, _T_3, UInt<1>(0h1), "") : assert wire chiptop0_clock_uncore_clock : Clock connect chiptop0.clock_uncore, chiptop0_clock_uncore_clock node _chiptop0_reset_io_T = asAsyncReset(reset) connect chiptop0.reset_io, _chiptop0_reset_io_T connect chiptop0.serial_tl_0.clock_in, harnessBinderClock inst ram of SerialRAM connect ram.clock, harnessBinderClock connect ram.reset, harnessBinderReset connect ram.io.ser.in, chiptop0.serial_tl_0.out connect chiptop0.serial_tl_0.in, ram.io.ser.out inst success_exit_sim of SimTSI connect success_exit_sim.clock, harnessBinderClock connect success_exit_sim.reset, harnessBinderReset connect success_exit_sim.tsi.out.bits, ram.io.tsi.out.bits connect success_exit_sim.tsi.out.valid, ram.io.tsi.out.valid connect ram.io.tsi.out.ready, success_exit_sim.tsi.out.ready connect ram.io.tsi.in.bits, success_exit_sim.tsi.in.bits connect ram.io.tsi.in.valid, success_exit_sim.tsi.in.valid connect success_exit_sim.tsi.in.ready, ram.io.tsi.in.ready node success_1 = eq(success_exit_sim.exit, UInt<1>(0h1)) node success_error = geq(success_exit_sim.exit, UInt<2>(0h2)) node _success_T = eq(success_error, UInt<1>(0h0)) node _success_T_1 = dshr(success_exit_sim.exit, UInt<1>(0h1)) node _success_T_2 = asUInt(harnessBinderReset) node _success_T_3 = eq(_success_T_2, UInt<1>(0h0)) when _success_T_3 : node _success_T_4 = eq(_success_T, UInt<1>(0h0)) when _success_T_4 : printf(harnessBinderClock, UInt<1>(0h1), "Assertion failed: *** FAILED *** (exit code = %d)\n\n at SimTSI.scala:21 assert(!error, \"*** FAILED *** (exit code = %%%%d)\\n\", exit >> 1.U)\n", _success_T_1) : success_printf assert(harnessBinderClock, _success_T, UInt<1>(0h1), "") : success_assert when success_1 : connect success, UInt<1>(0h1) wire harnessBinderClk : Clock connect harnessBinderClock, harnessBinderClk inst harnessBinderReset_catcher of ResetCatchAndSync_d3_4 connect harnessBinderReset_catcher.clock, harnessBinderClk connect harnessBinderReset_catcher.reset, reset wire _harnessBinderReset_catcher_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>} connect _harnessBinderReset_catcher_io_psd_WIRE.test_mode_reset, UInt<1>(0h0) connect _harnessBinderReset_catcher_io_psd_WIRE.test_mode, UInt<1>(0h0) wire _harnessBinderReset_catcher_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>} connect _harnessBinderReset_catcher_io_psd_WIRE_1, _harnessBinderReset_catcher_io_psd_WIRE connect harnessBinderReset_catcher.io.psd, _harnessBinderReset_catcher_io_psd_WIRE_1 connect harnessBinderReset, harnessBinderReset_catcher.io.sync_reset inst source of ClockSourceAtFreqMHz connect source.power, UInt<1>(0h1) connect source.gate, UInt<1>(0h0) connect chiptop0_clock_uncore_clock, source.clk inst source_1 of ClockSourceAtFreqMHz_1 connect source_1.power, UInt<1>(0h1) connect source_1.gate, UInt<1>(0h0) connect harnessBinderClk, source_1.clk

module TestHarness( // @[TestHarness.scala:19:7] input clock, // @[TestHarness.scala:19:7] input reset, // @[TestHarness.scala:19:7] output io_success // @[TestHarness.scala:20:14] ); wire _success_exit_sim_tsi_in_valid; // @[SimTSI.scala:12:23] wire [31:0] _success_exit_sim_tsi_in_bits; // @[SimTSI.scala:12:23] wire _success_exit_sim_tsi_out_ready; // @[SimTSI.scala:12:23] wire [31:0] _success_exit_sim_exit; // @[SimTSI.scala:12:23] wire _ram_io_ser_in_ready; // @[HarnessBinders.scala:253:27] wire _ram_io_ser_out_valid; // @[HarnessBinders.scala:253:27] wire [31:0] _ram_io_ser_out_bits_phit; // @[HarnessBinders.scala:253:27] wire _ram_io_tsi_in_ready; // @[HarnessBinders.scala:253:27] wire _ram_io_tsi_out_valid; // @[HarnessBinders.scala:253:27] wire [31:0] _ram_io_tsi_out_bits; // @[HarnessBinders.scala:253:27] wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _jtag_exit; // @[HarnessBinders.scala:184:22] wire _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _simdram_3_axi_aw_ready; // @[HarnessBinders.scala:123:21] wire _simdram_3_axi_w_ready; // @[HarnessBinders.scala:123:21] wire _simdram_3_axi_b_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_3_axi_b_bits_id; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_3_axi_b_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_3_axi_ar_ready; // @[HarnessBinders.scala:123:21] wire _simdram_3_axi_r_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_3_axi_r_bits_id; // @[HarnessBinders.scala:123:21] wire [63:0] _simdram_3_axi_r_bits_data; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_3_axi_r_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_3_axi_r_bits_last; // @[HarnessBinders.scala:123:21] wire _simdram_2_axi_aw_ready; // @[HarnessBinders.scala:123:21] wire _simdram_2_axi_w_ready; // @[HarnessBinders.scala:123:21] wire _simdram_2_axi_b_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_2_axi_b_bits_id; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_2_axi_b_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_2_axi_ar_ready; // @[HarnessBinders.scala:123:21] wire _simdram_2_axi_r_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_2_axi_r_bits_id; // @[HarnessBinders.scala:123:21] wire [63:0] _simdram_2_axi_r_bits_data; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_2_axi_r_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_2_axi_r_bits_last; // @[HarnessBinders.scala:123:21] wire _simdram_1_axi_aw_ready; // @[HarnessBinders.scala:123:21] wire _simdram_1_axi_w_ready; // @[HarnessBinders.scala:123:21] wire _simdram_1_axi_b_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_1_axi_b_bits_id; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_1_axi_b_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_1_axi_ar_ready; // @[HarnessBinders.scala:123:21] wire _simdram_1_axi_r_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_1_axi_r_bits_id; // @[HarnessBinders.scala:123:21] wire [63:0] _simdram_1_axi_r_bits_data; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_1_axi_r_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_1_axi_r_bits_last; // @[HarnessBinders.scala:123:21] wire _simdram_axi_aw_ready; // @[HarnessBinders.scala:123:21] wire _simdram_axi_w_ready; // @[HarnessBinders.scala:123:21] wire _simdram_axi_b_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_axi_b_bits_id; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_axi_b_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_axi_ar_ready; // @[HarnessBinders.scala:123:21] wire _simdram_axi_r_valid; // @[HarnessBinders.scala:123:21] wire [6:0] _simdram_axi_r_bits_id; // @[HarnessBinders.scala:123:21] wire [63:0] _simdram_axi_r_bits_data; // @[HarnessBinders.scala:123:21] wire [1:0] _simdram_axi_r_bits_resp; // @[HarnessBinders.scala:123:21] wire _simdram_axi_r_bits_last; // @[HarnessBinders.scala:123:21] wire _uart_sim_0_uartno0_io_uart_rxd; // @[SimUART.scala:76:28] wire _chiptop0_uart_0_txd; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_clock; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_aw_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_0_bits_aw_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_0_bits_aw_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_0_bits_aw_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_0_bits_aw_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_0_bits_aw_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_aw_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_aw_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_0_bits_aw_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_aw_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_w_valid; // @[HasHarnessInstantiators.scala:87:40] wire [63:0] _chiptop0_axi4_mem_0_bits_w_bits_data; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_0_bits_w_bits_strb; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_w_bits_last; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_b_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_ar_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_0_bits_ar_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_0_bits_ar_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_0_bits_ar_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_0_bits_ar_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_0_bits_ar_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_ar_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_ar_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_0_bits_ar_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_0_bits_ar_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_0_bits_r_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_clock; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_aw_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_1_bits_aw_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_1_bits_aw_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_1_bits_aw_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_1_bits_aw_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_1_bits_aw_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_aw_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_1_bits_aw_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_1_bits_aw_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_1_bits_aw_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_w_valid; // @[HasHarnessInstantiators.scala:87:40] wire [63:0] _chiptop0_axi4_mem_1_bits_w_bits_data; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_1_bits_w_bits_strb; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_w_bits_last; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_b_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_ar_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_1_bits_ar_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_1_bits_ar_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_1_bits_ar_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_1_bits_ar_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_1_bits_ar_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_ar_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_1_bits_ar_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_1_bits_ar_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_1_bits_ar_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_1_bits_r_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_clock; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_aw_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_2_bits_aw_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_2_bits_aw_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_2_bits_aw_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_2_bits_aw_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_2_bits_aw_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_aw_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_2_bits_aw_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_2_bits_aw_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_2_bits_aw_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_w_valid; // @[HasHarnessInstantiators.scala:87:40] wire [63:0] _chiptop0_axi4_mem_2_bits_w_bits_data; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_2_bits_w_bits_strb; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_w_bits_last; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_b_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_ar_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_2_bits_ar_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_2_bits_ar_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_2_bits_ar_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_2_bits_ar_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_2_bits_ar_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_ar_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_2_bits_ar_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_2_bits_ar_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_2_bits_ar_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_2_bits_r_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_clock; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_aw_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_3_bits_aw_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_3_bits_aw_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_3_bits_aw_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_3_bits_aw_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_3_bits_aw_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_aw_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_3_bits_aw_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_3_bits_aw_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_3_bits_aw_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_w_valid; // @[HasHarnessInstantiators.scala:87:40] wire [63:0] _chiptop0_axi4_mem_3_bits_w_bits_data; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_3_bits_w_bits_strb; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_w_bits_last; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_b_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_ar_valid; // @[HasHarnessInstantiators.scala:87:40] wire [6:0] _chiptop0_axi4_mem_3_bits_ar_bits_id; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_axi4_mem_3_bits_ar_bits_addr; // @[HasHarnessInstantiators.scala:87:40] wire [7:0] _chiptop0_axi4_mem_3_bits_ar_bits_len; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_3_bits_ar_bits_size; // @[HasHarnessInstantiators.scala:87:40] wire [1:0] _chiptop0_axi4_mem_3_bits_ar_bits_burst; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_ar_bits_lock; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_3_bits_ar_bits_cache; // @[HasHarnessInstantiators.scala:87:40] wire [2:0] _chiptop0_axi4_mem_3_bits_ar_bits_prot; // @[HasHarnessInstantiators.scala:87:40] wire [3:0] _chiptop0_axi4_mem_3_bits_ar_bits_qos; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_axi4_mem_3_bits_r_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_serial_tl_0_in_ready; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_serial_tl_0_out_valid; // @[HasHarnessInstantiators.scala:87:40] wire [31:0] _chiptop0_serial_tl_0_out_bits_phit; // @[HasHarnessInstantiators.scala:87:40] wire _chiptop0_reset_io_T = reset; // @[HarnessBinders.scala:325:34] wire _harnessBinderReset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63] wire _harnessBinderReset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63] wire _harnessBinderReset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50] wire _harnessBinderReset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50] wire success; // @[TestHarness.scala:23:25] wire jtag_wire_TDO_driven = 1'h1; // @[Periphery.scala:236:11] wire io_success_0; // @[TestHarness.scala:19:7] wire harnessBinderClk; // @[HarnessClocks.scala:28:23] wire harnessBinderClock; // @[HasHarnessInstantiators.scala:57:32] wire harnessBinderReset; // @[HasHarnessInstantiators.scala:58:32] wire _simdram_io_reset_T = harnessBinderReset; // @[HasHarnessInstantiators.scala:58:32] wire _simdram_io_reset_T_1 = harnessBinderReset; // @[HasHarnessInstantiators.scala:58:32] wire _simdram_io_reset_T_2 = harnessBinderReset; // @[HasHarnessInstantiators.scala:58:32] wire _simdram_io_reset_T_3 = harnessBinderReset; // @[HasHarnessInstantiators.scala:58:32] wire _success_T_2 = harnessBinderReset; // @[SimTSI.scala:21:11] assign io_success_0 = success; // @[TestHarness.scala:19:7, :23:25] wire _dtm_success_T; // @[Periphery.scala:235:26] wire dtm_success; // @[HarnessBinders.scala:176:31] wire jtag_wire_TDO_data; // @[HarnessBinders.scala:178:25] wire jtag_wire_TCK; // @[HarnessBinders.scala:178:25] wire jtag_wire_TMS; // @[HarnessBinders.scala:178:25] wire jtag_wire_TDI; // @[HarnessBinders.scala:178:25] assign _dtm_success_T = _jtag_exit == 32'h1; // @[Periphery.scala:235:26] assign dtm_success = _dtm_success_T; // @[Periphery.scala:235:26] wire chiptop0_clock_uncore_clock; // @[HarnessClocks.scala:28:23] wire success_1 = _success_exit_sim_exit == 32'h1; // @[SimTSI.scala:12:23, :19:24] wire success_error = |(_success_exit_sim_exit[31:1]); // @[SimTSI.scala:12:23, :20:22] wire _success_T = ~success_error; // @[SimTSI.scala:20:22, :21:12] wire [31:0] _success_T_1 = {1'h0, _success_exit_sim_exit[31:1]}; // @[SimTSI.scala:12:23, :20:22, :21:62] wire _success_T_3 = ~_success_T_2; // @[SimTSI.scala:21:11] wire _success_T_4 = ~_success_T; // @[SimTSI.scala:21:{11,12}]

Generate the Verilog code corresponding to this FIRRTL code module TLXbar_pbus_out_i1_o2_a29d64s10k1z3u : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_20 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<10>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<10>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<10>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 9, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<13>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<13>(0h0) connect _WIRE_30.bits.source, UInt<10>(0h0) connect _WIRE_30.bits.size, UInt<3>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<29>(0h0) connect _WIRE_32.bits.source, UInt<10>(0h0) connect _WIRE_32.bits.size, UInt<3>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<13>(0h0) connect _WIRE_34.bits.source, UInt<10>(0h0) connect _WIRE_34.bits.size, UInt<3>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<29>(0h0) connect _WIRE_36.bits.source, UInt<10>(0h0) connect _WIRE_36.bits.size, UInt<3>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.ready, UInt<1>(0h1) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<13>(0h0) connect _WIRE_38.bits.source, UInt<10>(0h0) connect _WIRE_38.bits.size, UInt<3>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.ready, UInt<1>(0h1) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<29>(0h0) connect _WIRE_48.bits.source, UInt<10>(0h0) connect _WIRE_48.bits.size, UInt<3>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<29>(0h0) connect _WIRE_50.bits.source, UInt<10>(0h0) connect _WIRE_50.bits.size, UInt<3>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<29>(0h0) connect _WIRE_52.bits.source, UInt<10>(0h0) connect _WIRE_52.bits.size, UInt<3>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<29>(0h0) connect _WIRE_54.bits.source, UInt<10>(0h0) connect _WIRE_54.bits.size, UInt<3>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<29>(0h0) connect _WIRE_56.bits.source, UInt<10>(0h0) connect _WIRE_56.bits.size, UInt<3>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<29>(0h0) connect _WIRE_58.bits.source, UInt<10>(0h0) connect _WIRE_58.bits.size, UInt<3>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<29>(0h0) connect _WIRE_60.bits.source, UInt<10>(0h0) connect _WIRE_60.bits.size, UInt<3>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<29>(0h0) connect _WIRE_62.bits.source, UInt<10>(0h0) connect _WIRE_62.bits.size, UInt<3>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<29>(0h0) connect _addressC_WIRE.bits.source, UInt<10>(0h0) connect _addressC_WIRE.bits.size, UInt<3>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<30>(0h10000000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<29>(0h10000000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<30>(0h10000000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<29>(0h0) connect _requestBOI_WIRE.bits.source, UInt<10>(0h0) connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<10>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 9, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 10) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<10>(0h3ff)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<29>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<10>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<10>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 9, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 10) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<10>(0h3ff)) node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<10>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 9, 0) node _requestDOI_T = shr(out[0].d.bits.source, 10) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<10>(0h3ff)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<10>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 9, 0) node _requestDOI_T_5 = shr(out[1].d.bits.source, 10) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<10>(0h3ff)) node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<29>(0h0) connect _beatsBO_WIRE.bits.source, UInt<10>(0h0) connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<29>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<10>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<29>(0h0) connect _beatsCI_WIRE.bits.source, UInt<10>(0h0) connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<29>(0h0) connect _portsBIO_WIRE.bits.source, UInt<10>(0h0) connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.address, UInt<29>(0h0) connect _portsBIO_WIRE_2.bits.source, UInt<10>(0h0) connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<29>(0h0) connect _portsCOI_WIRE.bits.source, UInt<10>(0h0) connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_2 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect out[0].d.ready, portsDIO_filtered[0].ready wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect out[1].d.ready, portsDIO_filtered_1[0].ready wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_2 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 connect out[0].a, portsAOI_filtered[0] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.address, UInt<29>(0h0) connect _WIRE_72.bits.source, UInt<10>(0h0) connect _WIRE_72.bits.size, UInt<3>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_74.bits.sink, UInt<1>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect out[1].a, portsAOI_filtered[1] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.address, UInt<29>(0h0) connect _WIRE_76.bits.source, UInt<10>(0h0) connect _WIRE_76.bits.size, UInt<3>(0h0) connect _WIRE_76.bits.param, UInt<3>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_78.bits.sink, UInt<1>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<64>(0h0) connect _WIRE_80.bits.mask, UInt<8>(0h0) connect _WIRE_80.bits.address, UInt<29>(0h0) connect _WIRE_80.bits.source, UInt<10>(0h0) connect _WIRE_80.bits.size, UInt<3>(0h0) connect _WIRE_80.bits.param, UInt<2>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.mask invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, in[0].d.ready) node _readys_T = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsDIO_filtered[0].valid) node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<64> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<1> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<10> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<3> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) extmodule plusarg_reader_42 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_43 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLXbar_pbus_out_i1_o2_a29d64s10k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [12:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire [9:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [9:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] x1_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] in_0_d_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_WIRE_param = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_19 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_in_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_d_bits_sink = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_denied = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _out_1_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_WIRE_sink = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_denied = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_7 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_10 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_11 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_6 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [28:0] _addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _requestCIO_T = 29'h0; // @[Parameters.scala:137:31] wire [28:0] _requestCIO_T_5 = 29'h0; // @[Parameters.scala:137:31] wire [28:0] _requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _requestBOI_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _requestBOI_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _beatsBO_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _beatsBO_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] _beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] _portsBIO_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] _portsBIO_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] portsBIO_filtered_1_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] _portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] portsCOI_filtered_1_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [9:0] _addressC_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _addressC_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _requestBOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _requestBOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _requestBOI_uncommonBits_T = 10'h0; // @[Parameters.scala:52:29] wire [9:0] requestBOI_uncommonBits = 10'h0; // @[Parameters.scala:52:56] wire [9:0] _requestBOI_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _requestBOI_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _requestBOI_uncommonBits_T_1 = 10'h0; // @[Parameters.scala:52:29] wire [9:0] requestBOI_uncommonBits_1 = 10'h0; // @[Parameters.scala:52:56] wire [9:0] _beatsBO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _beatsBO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _beatsBO_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _beatsBO_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] _beatsCI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _beatsCI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _portsBIO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _portsBIO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] portsBIO_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] _portsBIO_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] _portsBIO_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] portsBIO_filtered_1_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] _portsCOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _portsCOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] portsCOI_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] portsCOI_filtered_1_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [29:0] _requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] _requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_6 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] _requestCIO_T_7 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _requestCIO_T_8 = 30'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [9:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [12:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [9:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [12:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [9:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [28:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [9:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [9:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [9:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [9:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [28:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [28:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [28:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [9:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [9:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [9:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [9:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [9:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [28:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address[12:0]; // @[Xbar.scala:216:19, :222:41] wire [29:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] _requestAIO_T_2 = _requestAIO_T_1 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [28:0] _requestAIO_T_5 = in_0_a_bits_address ^ 29'h10000000; // @[Xbar.scala:159:18] wire [29:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [29:0] _requestAIO_T_7 = _requestAIO_T_6 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [9:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [9:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]

Generate the Verilog code corresponding to this FIRRTL code module PE_422 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_166 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_422( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_166 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s6k1z3u_1 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_80 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a28d64s6k1z3u_1 connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a28d64s6k1z3u_1 connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLBuffer_a28d64s6k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [5:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_80 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s6k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s6k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (2'h0), // @[Decoupled.scala:362:21] .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (1'h0), // @[Decoupled.scala:362:21] .io_enq_bits_denied (1'h0), // @[Decoupled.scala:362:21] .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (1'h0), // @[Decoupled.scala:362:21] .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_34 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h13)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h13)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_86 = shr(io.in.a.bits.source, 5) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<5>(0h13)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_152 = shr(io.in.a.bits.source, 5) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<5>(0h13)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_199 = shr(io.in.a.bits.source, 5) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<5>(0h13)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_240 = shr(io.in.a.bits.source, 5) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<5>(0h13)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_283 = shr(io.in.a.bits.source, 5) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<5>(0h13)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_321 = shr(io.in.a.bits.source, 5) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<5>(0h13)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_359 = shr(io.in.a.bits.source, 5) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<5>(0h13)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0) regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<20> connect a_set, UInt<20>(0h0) wire a_set_wo_ready : UInt<20> connect a_set_wo_ready, UInt<20>(0h0) wire a_opcodes_set : UInt<80> connect a_opcodes_set, UInt<80>(0h0) wire a_sizes_set : UInt<80> connect a_sizes_set, UInt<80>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<20> connect d_clr, UInt<20>(0h0) wire d_clr_wo_ready : UInt<20> connect d_clr_wo_ready, UInt<20>(0h0) wire d_opcodes_clr : UInt<80> connect d_opcodes_clr, UInt<80>(0h0) wire d_sizes_clr : UInt<80> connect d_sizes_clr, UInt<80>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_68 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0) regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<20> connect c_set, UInt<20>(0h0) wire c_set_wo_ready : UInt<20> connect c_set_wo_ready, UInt<20>(0h0) wire c_opcodes_set : UInt<80> connect c_opcodes_set, UInt<80>(0h0) wire c_sizes_set : UInt<80> connect c_sizes_set, UInt<80>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<20> connect d_clr_1, UInt<20>(0h0) wire d_clr_wo_ready_1 : UInt<20> connect d_clr_wo_ready_1, UInt<20>(0h0) wire d_opcodes_clr_1 : UInt<80> connect d_opcodes_clr_1, UInt<80>(0h0) wire d_sizes_clr_1 : UInt<80> connect d_sizes_clr_1, UInt<80>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_69 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_34( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34] wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34] wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34] wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [19:0] inflight; // @[Monitor.scala:614:27] reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [19:0] a_set; // @[Monitor.scala:626:34] wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [79:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [19:0] d_clr; // @[Monitor.scala:664:34] wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [19:0] inflight_1; // @[Monitor.scala:726:35] wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [19:0] d_clr_1; // @[Monitor.scala:774:34] wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_31 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_31 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module INToRecFN_i1_e8_s24_31(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_31 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_133 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_389 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_133( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_389 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMasterACDToNoC_10 : input clock : Clock input reset : Reset output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst a of TLAToNoC_10 connect a.clock, clock connect a.reset, reset inst c of TLCToNoC_10 connect c.clock, clock connect c.reset, reset inst d of TLDFromNoC_10 connect d.clock, clock connect d.reset, reset connect a.io.protocol, io.tilelink.a connect c.io.protocol, io.tilelink.c connect io.tilelink.d.bits, d.io.protocol.bits connect io.tilelink.d.valid, d.io.protocol.valid connect d.io.protocol.ready, io.tilelink.d.ready connect io.flits.a.bits, a.io.flit.bits connect io.flits.a.valid, a.io.flit.valid connect a.io.flit.ready, io.flits.a.ready connect io.flits.c.bits, c.io.flit.bits connect io.flits.c.valid, c.io.flit.valid connect c.io.flit.ready, io.flits.c.ready connect d.io.flit, io.flits.d

module TLMasterACDToNoC_10( // @[Tilelink.scala:72:7] input clock, // @[Tilelink.scala:72:7] input reset, // @[Tilelink.scala:72:7] output io_tilelink_a_ready, // @[Tilelink.scala:79:14] input io_tilelink_a_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:79:14] input [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:79:14] input [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:79:14] input [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:79:14] output io_tilelink_c_ready, // @[Tilelink.scala:79:14] input io_tilelink_c_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:79:14] input [6:0] io_tilelink_c_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:79:14] input [127:0] io_tilelink_c_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:79:14] input io_tilelink_d_ready, // @[Tilelink.scala:79:14] output io_tilelink_d_valid, // @[Tilelink.scala:79:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:79:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:79:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:79:14] output [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:79:14] output [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:79:14] output [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:79:14] input io_flits_a_ready, // @[Tilelink.scala:79:14] output io_flits_a_valid, // @[Tilelink.scala:79:14] output io_flits_a_bits_head, // @[Tilelink.scala:79:14] output io_flits_a_bits_tail, // @[Tilelink.scala:79:14] output [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:79:14] input io_flits_c_ready, // @[Tilelink.scala:79:14] output io_flits_c_valid, // @[Tilelink.scala:79:14] output io_flits_c_bits_head, // @[Tilelink.scala:79:14] output io_flits_c_bits_tail, // @[Tilelink.scala:79:14] output [144:0] io_flits_c_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:79:14] output io_flits_d_ready, // @[Tilelink.scala:79:14] input io_flits_d_valid, // @[Tilelink.scala:79:14] input io_flits_d_bits_head, // @[Tilelink.scala:79:14] input io_flits_d_bits_tail, // @[Tilelink.scala:79:14] input [144:0] io_flits_d_bits_payload // @[Tilelink.scala:79:14] ); wire [128:0] _c_io_flit_bits_payload; // @[Tilelink.scala:89:17] TLAToNoC_10 a ( // @[Tilelink.scala:88:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:88:17] TLCToNoC_10 c ( // @[Tilelink.scala:89:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:89:17] TLDFromNoC_1 d ( // @[Tilelink.scala:90:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[128:0]) // @[Tilelink.scala:97:14] ); // @[Tilelink.scala:90:17] assign io_flits_c_bits_payload = {16'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:72:7, :89:17, :96:14] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OutputUnit_1 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[6], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[6], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[6], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[6], out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}} reg states : { `5` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}, `4` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}, `3` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}, `2` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}, `1` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}, `0` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, clock connect io.channel_status[0].occupied, states.`0`.occupied connect io.channel_status[0].flow, states.`0`.flow connect io.channel_status[1].occupied, states.`1`.occupied connect io.channel_status[1].flow, states.`1`.flow connect io.channel_status[2].occupied, states.`2`.occupied connect io.channel_status[2].flow, states.`2`.flow connect io.channel_status[3].occupied, states.`3`.occupied connect io.channel_status[3].flow, states.`3`.flow connect io.channel_status[4].occupied, states.`4`.occupied connect io.channel_status[4].flow, states.`4`.flow connect io.channel_status[5].occupied, states.`5`.occupied connect io.channel_status[5].flow, states.`5`.flow connect io.out.flit, io.in node _T = bits(io.out.vc_free, 0, 0) when _T : node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(states.`0`.occupied, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf assert(clock, states.`0`.occupied, UInt<1>(0h1), "") : assert connect states.`0`.occupied, UInt<1>(0h0) node _T_4 = bits(io.out.vc_free, 1, 1) when _T_4 : node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(states.`1`.occupied, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_1 assert(clock, states.`1`.occupied, UInt<1>(0h1), "") : assert_1 connect states.`1`.occupied, UInt<1>(0h0) node _T_8 = bits(io.out.vc_free, 2, 2) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : node _T_11 = eq(states.`2`.occupied, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_2 assert(clock, states.`2`.occupied, UInt<1>(0h1), "") : assert_2 connect states.`2`.occupied, UInt<1>(0h0) node _T_12 = bits(io.out.vc_free, 3, 3) when _T_12 : node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(states.`3`.occupied, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_3 assert(clock, states.`3`.occupied, UInt<1>(0h1), "") : assert_3 connect states.`3`.occupied, UInt<1>(0h0) node _T_16 = bits(io.out.vc_free, 4, 4) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(states.`4`.occupied, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_4 assert(clock, states.`4`.occupied, UInt<1>(0h1), "") : assert_4 connect states.`4`.occupied, UInt<1>(0h0) node _T_20 = bits(io.out.vc_free, 5, 5) when _T_20 : node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(states.`5`.occupied, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_5 assert(clock, states.`5`.occupied, UInt<1>(0h1), "") : assert_5 connect states.`5`.occupied, UInt<1>(0h0) when io.allocs[0].alloc : connect states.`0`.occupied, UInt<1>(0h1) connect states.`0`.flow, io.allocs[0].flow when io.allocs[1].alloc : connect states.`1`.occupied, UInt<1>(0h1) connect states.`1`.flow, io.allocs[1].flow when io.allocs[2].alloc : connect states.`2`.occupied, UInt<1>(0h1) connect states.`2`.flow, io.allocs[2].flow when io.allocs[3].alloc : connect states.`3`.occupied, UInt<1>(0h1) connect states.`3`.flow, io.allocs[3].flow when io.allocs[4].alloc : connect states.`4`.occupied, UInt<1>(0h1) connect states.`4`.flow, io.allocs[4].flow when io.allocs[5].alloc : connect states.`5`.occupied, UInt<1>(0h1) connect states.`5`.flow, io.allocs[5].flow node _io_credit_available_0_T = neq(states.`0`.c, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_credit_available_1_T = neq(states.`1`.c, UInt<1>(0h0)) connect io.credit_available[1], _io_credit_available_1_T node _io_credit_available_2_T = neq(states.`2`.c, UInt<1>(0h0)) connect io.credit_available[2], _io_credit_available_2_T node _io_credit_available_3_T = neq(states.`3`.c, UInt<1>(0h0)) connect io.credit_available[3], _io_credit_available_3_T node _io_credit_available_4_T = neq(states.`4`.c, UInt<1>(0h0)) connect io.credit_available[4], _io_credit_available_4_T node _io_credit_available_5_T = neq(states.`5`.c, UInt<1>(0h0)) connect io.credit_available[5], _io_credit_available_5_T node free = bits(io.out.credit_return, 0, 0) node _states_0_c_T = add(states.`0`.c, free) node _states_0_c_T_1 = sub(_states_0_c_T, io.credit_alloc[0].alloc) node _states_0_c_T_2 = tail(_states_0_c_T_1, 1) connect states.`0`.c, _states_0_c_T_2 node free_1 = bits(io.out.credit_return, 1, 1) node _states_1_c_T = add(states.`1`.c, free_1) node _states_1_c_T_1 = sub(_states_1_c_T, io.credit_alloc[1].alloc) node _states_1_c_T_2 = tail(_states_1_c_T_1, 1) connect states.`1`.c, _states_1_c_T_2 node free_2 = bits(io.out.credit_return, 2, 2) node _states_2_c_T = add(states.`2`.c, free_2) node _states_2_c_T_1 = sub(_states_2_c_T, io.credit_alloc[2].alloc) node _states_2_c_T_2 = tail(_states_2_c_T_1, 1) connect states.`2`.c, _states_2_c_T_2 node free_3 = bits(io.out.credit_return, 3, 3) node _states_3_c_T = add(states.`3`.c, free_3) node _states_3_c_T_1 = sub(_states_3_c_T, io.credit_alloc[3].alloc) node _states_3_c_T_2 = tail(_states_3_c_T_1, 1) connect states.`3`.c, _states_3_c_T_2 node free_4 = bits(io.out.credit_return, 4, 4) node _states_4_c_T = add(states.`4`.c, free_4) node _states_4_c_T_1 = sub(_states_4_c_T, io.credit_alloc[4].alloc) node _states_4_c_T_2 = tail(_states_4_c_T_1, 1) connect states.`4`.c, _states_4_c_T_2 node free_5 = bits(io.out.credit_return, 5, 5) node _states_5_c_T = add(states.`5`.c, free_5) node _states_5_c_T_1 = sub(_states_5_c_T, io.credit_alloc[5].alloc) node _states_5_c_T_2 = tail(_states_5_c_T_1, 1) connect states.`5`.c, _states_5_c_T_2 node _T_24 = asUInt(reset) when _T_24 : connect states.`0`.occupied, UInt<1>(0h0) connect states.`1`.occupied, UInt<1>(0h0) connect states.`2`.occupied, UInt<1>(0h0) connect states.`3`.occupied, UInt<1>(0h0) connect states.`4`.occupied, UInt<1>(0h0) connect states.`5`.occupied, UInt<1>(0h0) connect states.`0`.c, UInt<3>(0h4) connect states.`1`.c, UInt<3>(0h4) connect states.`2`.c, UInt<3>(0h4) connect states.`3`.c, UInt<3>(0h4) connect states.`4`.c, UInt<3>(0h4) connect states.`5`.c, UInt<3>(0h4)

module OutputUnit_1( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [72:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_0, // @[OutputUnit.scala:58:14] output io_credit_available_1, // @[OutputUnit.scala:58:14] output io_credit_available_2, // @[OutputUnit.scala:58:14] output io_credit_available_3, // @[OutputUnit.scala:58:14] output io_credit_available_4, // @[OutputUnit.scala:58:14] output io_credit_available_5, // @[OutputUnit.scala:58:14] output io_channel_status_0_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_1_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_2_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_3_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_4_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_5_occupied, // @[OutputUnit.scala:58:14] input io_allocs_0_alloc, // @[OutputUnit.scala:58:14] input io_allocs_1_alloc, // @[OutputUnit.scala:58:14] input io_allocs_2_alloc, // @[OutputUnit.scala:58:14] input io_allocs_3_alloc, // @[OutputUnit.scala:58:14] input io_allocs_4_alloc, // @[OutputUnit.scala:58:14] input io_allocs_5_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_0_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_1_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_2_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_3_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_4_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_5_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [72:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [5:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [5:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_5_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_5_c; // @[OutputUnit.scala:66:19] reg states_4_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_4_c; // @[OutputUnit.scala:66:19] reg states_3_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_3_c; // @[OutputUnit.scala:66:19] reg states_2_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_2_c; // @[OutputUnit.scala:66:19] reg states_1_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_1_c; // @[OutputUnit.scala:66:19] reg states_0_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_0_c; // @[OutputUnit.scala:66:19]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_170 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_191 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_170( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_191 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w55 : input clock : Clock input reset : Reset output io : { flip d : UInt<55>, q : UInt<55>, flip en : UInt<1>} reg cdc_reg : UInt<55>, clock when io.en : connect cdc_reg, io.d connect io.q, cdc_reg

module ClockCrossingReg_w55( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [54:0] io_d, // @[SynchronizerReg.scala:195:14] output [54:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [54:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [54:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [54:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_123 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_123 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module RoundRawFNToRecFN_e8_s24_123( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_123 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_106 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_106( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_347 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_91 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_347( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_91 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[12] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 node _source_ok_T_32 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[2]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[3]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[4]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[5]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[6]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[7]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[8]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[9]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[10]) node source_ok = or(_source_ok_T_41, _source_ok_WIRE[11]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = and(_T_11, _T_24) node _T_121 = and(_T_120, _T_37) node _T_122 = and(_T_121, _T_50) node _T_123 = and(_T_122, _T_63) node _T_124 = and(_T_123, _T_71) node _T_125 = and(_T_124, _T_79) node _T_126 = and(_T_125, _T_87) node _T_127 = and(_T_126, _T_95) node _T_128 = and(_T_127, _T_103) node _T_129 = and(_T_128, _T_111) node _T_130 = and(_T_129, _T_119) node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(_T_130, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_130, UInt<1>(0h1), "") : assert_1 node _T_134 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_134 : node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_136 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_139 = shr(io.in.a.bits.source, 2) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = leq(UInt<1>(0h0), uncommonBits_4) node _T_142 = and(_T_140, _T_141) node _T_143 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_144 = and(_T_142, _T_143) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_145 = shr(io.in.a.bits.source, 2) node _T_146 = eq(_T_145, UInt<1>(0h1)) node _T_147 = leq(UInt<1>(0h0), uncommonBits_5) node _T_148 = and(_T_146, _T_147) node _T_149 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_150 = and(_T_148, _T_149) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_151 = shr(io.in.a.bits.source, 2) node _T_152 = eq(_T_151, UInt<2>(0h2)) node _T_153 = leq(UInt<1>(0h0), uncommonBits_6) node _T_154 = and(_T_152, _T_153) node _T_155 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_156 = and(_T_154, _T_155) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_157 = shr(io.in.a.bits.source, 2) node _T_158 = eq(_T_157, UInt<2>(0h3)) node _T_159 = leq(UInt<1>(0h0), uncommonBits_7) node _T_160 = and(_T_158, _T_159) node _T_161 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_166 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_167 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_169 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_170 = or(_T_138, _T_144) node _T_171 = or(_T_170, _T_150) node _T_172 = or(_T_171, _T_156) node _T_173 = or(_T_172, _T_162) node _T_174 = or(_T_173, _T_163) node _T_175 = or(_T_174, _T_164) node _T_176 = or(_T_175, _T_165) node _T_177 = or(_T_176, _T_166) node _T_178 = or(_T_177, _T_167) node _T_179 = or(_T_178, _T_168) node _T_180 = or(_T_179, _T_169) node _T_181 = and(_T_137, _T_180) node _T_182 = or(UInt<1>(0h0), _T_181) node _T_183 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_184 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<13>(0h1000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = and(_T_183, _T_188) node _T_190 = or(UInt<1>(0h0), _T_189) node _T_191 = and(_T_182, _T_190) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_191, UInt<1>(0h1), "") : assert_2 node _T_195 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_196 = shr(io.in.a.bits.source, 2) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = leq(UInt<1>(0h0), uncommonBits_8) node _T_199 = and(_T_197, _T_198) node _T_200 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_201 = and(_T_199, _T_200) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_202 = shr(io.in.a.bits.source, 2) node _T_203 = eq(_T_202, UInt<1>(0h1)) node _T_204 = leq(UInt<1>(0h0), uncommonBits_9) node _T_205 = and(_T_203, _T_204) node _T_206 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_207 = and(_T_205, _T_206) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_208 = shr(io.in.a.bits.source, 2) node _T_209 = eq(_T_208, UInt<2>(0h2)) node _T_210 = leq(UInt<1>(0h0), uncommonBits_10) node _T_211 = and(_T_209, _T_210) node _T_212 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_213 = and(_T_211, _T_212) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_214 = shr(io.in.a.bits.source, 2) node _T_215 = eq(_T_214, UInt<2>(0h3)) node _T_216 = leq(UInt<1>(0h0), uncommonBits_11) node _T_217 = and(_T_215, _T_216) node _T_218 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_219 = and(_T_217, _T_218) node _T_220 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_221 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_222 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_223 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_225 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_226 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[12] connect _WIRE[0], _T_195 connect _WIRE[1], _T_201 connect _WIRE[2], _T_207 connect _WIRE[3], _T_213 connect _WIRE[4], _T_219 connect _WIRE[5], _T_220 connect _WIRE[6], _T_221 connect _WIRE[7], _T_222 connect _WIRE[8], _T_223 connect _WIRE[9], _T_224 connect _WIRE[10], _T_225 connect _WIRE[11], _T_226 node _T_227 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_228 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_229 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_230 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_231 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_232 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_233 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_234 = mux(_WIRE[5], _T_227, UInt<1>(0h0)) node _T_235 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_236 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_237 = mux(_WIRE[8], _T_228, UInt<1>(0h0)) node _T_238 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_239 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_240 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = or(_T_229, _T_230) node _T_242 = or(_T_241, _T_231) node _T_243 = or(_T_242, _T_232) node _T_244 = or(_T_243, _T_233) node _T_245 = or(_T_244, _T_234) node _T_246 = or(_T_245, _T_235) node _T_247 = or(_T_246, _T_236) node _T_248 = or(_T_247, _T_237) node _T_249 = or(_T_248, _T_238) node _T_250 = or(_T_249, _T_239) node _T_251 = or(_T_250, _T_240) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_251 node _T_252 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_253 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_254 = and(_T_252, _T_253) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<13>(0h1000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = and(_T_255, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = and(_WIRE_1, _T_262) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_263, UInt<1>(0h1), "") : assert_3 node _T_267 = asUInt(reset) node _T_268 = eq(_T_267, UInt<1>(0h0)) when _T_268 : node _T_269 = eq(source_ok, UInt<1>(0h0)) when _T_269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_270 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_270, UInt<1>(0h1), "") : assert_5 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(is_aligned, UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_277 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_277, UInt<1>(0h1), "") : assert_7 node _T_281 = not(io.in.a.bits.mask) node _T_282 = eq(_T_281, UInt<1>(0h0)) node _T_283 = asUInt(reset) node _T_284 = eq(_T_283, UInt<1>(0h0)) when _T_284 : node _T_285 = eq(_T_282, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_282, UInt<1>(0h1), "") : assert_8 node _T_286 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_287 = asUInt(reset) node _T_288 = eq(_T_287, UInt<1>(0h0)) when _T_288 : node _T_289 = eq(_T_286, UInt<1>(0h0)) when _T_289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_286, UInt<1>(0h1), "") : assert_9 node _T_290 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_290 : node _T_291 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_292 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_295 = shr(io.in.a.bits.source, 2) node _T_296 = eq(_T_295, UInt<1>(0h0)) node _T_297 = leq(UInt<1>(0h0), uncommonBits_12) node _T_298 = and(_T_296, _T_297) node _T_299 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_300 = and(_T_298, _T_299) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<1>(0h1)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_13) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<2>(0h2)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_14) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<2>(0h3)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_15) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_321 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_322 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_323 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_324 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_325 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_326 = or(_T_294, _T_300) node _T_327 = or(_T_326, _T_306) node _T_328 = or(_T_327, _T_312) node _T_329 = or(_T_328, _T_318) node _T_330 = or(_T_329, _T_319) node _T_331 = or(_T_330, _T_320) node _T_332 = or(_T_331, _T_321) node _T_333 = or(_T_332, _T_322) node _T_334 = or(_T_333, _T_323) node _T_335 = or(_T_334, _T_324) node _T_336 = or(_T_335, _T_325) node _T_337 = and(_T_293, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<13>(0h1000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = and(_T_339, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = and(_T_338, _T_346) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_347, UInt<1>(0h1), "") : assert_10 node _T_351 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_352 = shr(io.in.a.bits.source, 2) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = leq(UInt<1>(0h0), uncommonBits_16) node _T_355 = and(_T_353, _T_354) node _T_356 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_357 = and(_T_355, _T_356) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_358 = shr(io.in.a.bits.source, 2) node _T_359 = eq(_T_358, UInt<1>(0h1)) node _T_360 = leq(UInt<1>(0h0), uncommonBits_17) node _T_361 = and(_T_359, _T_360) node _T_362 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_363 = and(_T_361, _T_362) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_364 = shr(io.in.a.bits.source, 2) node _T_365 = eq(_T_364, UInt<2>(0h2)) node _T_366 = leq(UInt<1>(0h0), uncommonBits_18) node _T_367 = and(_T_365, _T_366) node _T_368 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_369 = and(_T_367, _T_368) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_370 = shr(io.in.a.bits.source, 2) node _T_371 = eq(_T_370, UInt<2>(0h3)) node _T_372 = leq(UInt<1>(0h0), uncommonBits_19) node _T_373 = and(_T_371, _T_372) node _T_374 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_375 = and(_T_373, _T_374) node _T_376 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_377 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_378 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_379 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_380 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_381 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_382 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[12] connect _WIRE_2[0], _T_351 connect _WIRE_2[1], _T_357 connect _WIRE_2[2], _T_363 connect _WIRE_2[3], _T_369 connect _WIRE_2[4], _T_375 connect _WIRE_2[5], _T_376 connect _WIRE_2[6], _T_377 connect _WIRE_2[7], _T_378 connect _WIRE_2[8], _T_379 connect _WIRE_2[9], _T_380 connect _WIRE_2[10], _T_381 connect _WIRE_2[11], _T_382 node _T_383 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_384 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_385 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_387 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_388 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_389 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_390 = mux(_WIRE_2[5], _T_383, UInt<1>(0h0)) node _T_391 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_392 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_393 = mux(_WIRE_2[8], _T_384, UInt<1>(0h0)) node _T_394 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_395 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_396 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_397 = or(_T_385, _T_386) node _T_398 = or(_T_397, _T_387) node _T_399 = or(_T_398, _T_388) node _T_400 = or(_T_399, _T_389) node _T_401 = or(_T_400, _T_390) node _T_402 = or(_T_401, _T_391) node _T_403 = or(_T_402, _T_392) node _T_404 = or(_T_403, _T_393) node _T_405 = or(_T_404, _T_394) node _T_406 = or(_T_405, _T_395) node _T_407 = or(_T_406, _T_396) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_407 node _T_408 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_409 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_410 = and(_T_408, _T_409) node _T_411 = or(UInt<1>(0h0), _T_410) node _T_412 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_413 = cvt(_T_412) node _T_414 = and(_T_413, asSInt(UInt<13>(0h1000))) node _T_415 = asSInt(_T_414) node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0))) node _T_417 = and(_T_411, _T_416) node _T_418 = or(UInt<1>(0h0), _T_417) node _T_419 = and(_WIRE_3, _T_418) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_419, UInt<1>(0h1), "") : assert_11 node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(source_ok, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_426 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_426, UInt<1>(0h1), "") : assert_13 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(is_aligned, UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_433 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_433, UInt<1>(0h1), "") : assert_15 node _T_437 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_437, UInt<1>(0h1), "") : assert_16 node _T_441 = not(io.in.a.bits.mask) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_442, UInt<1>(0h1), "") : assert_17 node _T_446 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_446, UInt<1>(0h1), "") : assert_18 node _T_450 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_450 : node _T_451 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_452 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_453 = and(_T_451, _T_452) node _T_454 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_455 = shr(io.in.a.bits.source, 2) node _T_456 = eq(_T_455, UInt<1>(0h0)) node _T_457 = leq(UInt<1>(0h0), uncommonBits_20) node _T_458 = and(_T_456, _T_457) node _T_459 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_460 = and(_T_458, _T_459) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_461 = shr(io.in.a.bits.source, 2) node _T_462 = eq(_T_461, UInt<1>(0h1)) node _T_463 = leq(UInt<1>(0h0), uncommonBits_21) node _T_464 = and(_T_462, _T_463) node _T_465 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_466 = and(_T_464, _T_465) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_467 = shr(io.in.a.bits.source, 2) node _T_468 = eq(_T_467, UInt<2>(0h2)) node _T_469 = leq(UInt<1>(0h0), uncommonBits_22) node _T_470 = and(_T_468, _T_469) node _T_471 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_472 = and(_T_470, _T_471) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_473 = shr(io.in.a.bits.source, 2) node _T_474 = eq(_T_473, UInt<2>(0h3)) node _T_475 = leq(UInt<1>(0h0), uncommonBits_23) node _T_476 = and(_T_474, _T_475) node _T_477 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_480 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_483 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_484 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_485 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_486 = or(_T_454, _T_460) node _T_487 = or(_T_486, _T_466) node _T_488 = or(_T_487, _T_472) node _T_489 = or(_T_488, _T_478) node _T_490 = or(_T_489, _T_479) node _T_491 = or(_T_490, _T_480) node _T_492 = or(_T_491, _T_481) node _T_493 = or(_T_492, _T_482) node _T_494 = or(_T_493, _T_483) node _T_495 = or(_T_494, _T_484) node _T_496 = or(_T_495, _T_485) node _T_497 = and(_T_453, _T_496) node _T_498 = or(UInt<1>(0h0), _T_497) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_498, UInt<1>(0h1), "") : assert_19 node _T_502 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_503 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_504 = and(_T_502, _T_503) node _T_505 = or(UInt<1>(0h0), _T_504) node _T_506 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<13>(0h1000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = and(_T_505, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_512, UInt<1>(0h1), "") : assert_20 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_522, UInt<1>(0h1), "") : assert_23 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_526, UInt<1>(0h1), "") : assert_24 node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_530, UInt<1>(0h1), "") : assert_25 node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_534 : node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_539 = shr(io.in.a.bits.source, 2) node _T_540 = eq(_T_539, UInt<1>(0h0)) node _T_541 = leq(UInt<1>(0h0), uncommonBits_24) node _T_542 = and(_T_540, _T_541) node _T_543 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_544 = and(_T_542, _T_543) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_545 = shr(io.in.a.bits.source, 2) node _T_546 = eq(_T_545, UInt<1>(0h1)) node _T_547 = leq(UInt<1>(0h0), uncommonBits_25) node _T_548 = and(_T_546, _T_547) node _T_549 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_550 = and(_T_548, _T_549) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_551 = shr(io.in.a.bits.source, 2) node _T_552 = eq(_T_551, UInt<2>(0h2)) node _T_553 = leq(UInt<1>(0h0), uncommonBits_26) node _T_554 = and(_T_552, _T_553) node _T_555 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_556 = and(_T_554, _T_555) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_557 = shr(io.in.a.bits.source, 2) node _T_558 = eq(_T_557, UInt<2>(0h3)) node _T_559 = leq(UInt<1>(0h0), uncommonBits_27) node _T_560 = and(_T_558, _T_559) node _T_561 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_562 = and(_T_560, _T_561) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_569 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_570 = or(_T_538, _T_544) node _T_571 = or(_T_570, _T_550) node _T_572 = or(_T_571, _T_556) node _T_573 = or(_T_572, _T_562) node _T_574 = or(_T_573, _T_563) node _T_575 = or(_T_574, _T_564) node _T_576 = or(_T_575, _T_565) node _T_577 = or(_T_576, _T_566) node _T_578 = or(_T_577, _T_567) node _T_579 = or(_T_578, _T_568) node _T_580 = or(_T_579, _T_569) node _T_581 = and(_T_537, _T_580) node _T_582 = or(UInt<1>(0h0), _T_581) node _T_583 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_584 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_585 = and(_T_583, _T_584) node _T_586 = or(UInt<1>(0h0), _T_585) node _T_587 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_588 = cvt(_T_587) node _T_589 = and(_T_588, asSInt(UInt<13>(0h1000))) node _T_590 = asSInt(_T_589) node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0))) node _T_592 = and(_T_586, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = and(_T_582, _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_594, UInt<1>(0h1), "") : assert_26 node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(source_ok, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_601 = asUInt(reset) node _T_602 = eq(_T_601, UInt<1>(0h0)) when _T_602 : node _T_603 = eq(is_aligned, UInt<1>(0h0)) when _T_603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_604 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_604, UInt<1>(0h1), "") : assert_29 node _T_608 = eq(io.in.a.bits.mask, mask) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_608, UInt<1>(0h1), "") : assert_30 node _T_612 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_612 : node _T_613 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_614 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_615 = and(_T_613, _T_614) node _T_616 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_617 = shr(io.in.a.bits.source, 2) node _T_618 = eq(_T_617, UInt<1>(0h0)) node _T_619 = leq(UInt<1>(0h0), uncommonBits_28) node _T_620 = and(_T_618, _T_619) node _T_621 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_622 = and(_T_620, _T_621) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_623 = shr(io.in.a.bits.source, 2) node _T_624 = eq(_T_623, UInt<1>(0h1)) node _T_625 = leq(UInt<1>(0h0), uncommonBits_29) node _T_626 = and(_T_624, _T_625) node _T_627 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_629 = shr(io.in.a.bits.source, 2) node _T_630 = eq(_T_629, UInt<2>(0h2)) node _T_631 = leq(UInt<1>(0h0), uncommonBits_30) node _T_632 = and(_T_630, _T_631) node _T_633 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_634 = and(_T_632, _T_633) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_635 = shr(io.in.a.bits.source, 2) node _T_636 = eq(_T_635, UInt<2>(0h3)) node _T_637 = leq(UInt<1>(0h0), uncommonBits_31) node _T_638 = and(_T_636, _T_637) node _T_639 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_640 = and(_T_638, _T_639) node _T_641 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_642 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_643 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_616, _T_622) node _T_649 = or(_T_648, _T_628) node _T_650 = or(_T_649, _T_634) node _T_651 = or(_T_650, _T_640) node _T_652 = or(_T_651, _T_641) node _T_653 = or(_T_652, _T_642) node _T_654 = or(_T_653, _T_643) node _T_655 = or(_T_654, _T_644) node _T_656 = or(_T_655, _T_645) node _T_657 = or(_T_656, _T_646) node _T_658 = or(_T_657, _T_647) node _T_659 = and(_T_615, _T_658) node _T_660 = or(UInt<1>(0h0), _T_659) node _T_661 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_662 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_663 = and(_T_661, _T_662) node _T_664 = or(UInt<1>(0h0), _T_663) node _T_665 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<13>(0h1000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = and(_T_664, _T_669) node _T_671 = or(UInt<1>(0h0), _T_670) node _T_672 = and(_T_660, _T_671) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_672, UInt<1>(0h1), "") : assert_31 node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(source_ok, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(is_aligned, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_682 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_T_682, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_682, UInt<1>(0h1), "") : assert_34 node _T_686 = not(mask) node _T_687 = and(io.in.a.bits.mask, _T_686) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_688, UInt<1>(0h1), "") : assert_35 node _T_692 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_692 : node _T_693 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_694 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_695 = and(_T_693, _T_694) node _T_696 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<1>(0h0)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_32) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_703 = shr(io.in.a.bits.source, 2) node _T_704 = eq(_T_703, UInt<1>(0h1)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_33) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_708 = and(_T_706, _T_707) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_709 = shr(io.in.a.bits.source, 2) node _T_710 = eq(_T_709, UInt<2>(0h2)) node _T_711 = leq(UInt<1>(0h0), uncommonBits_34) node _T_712 = and(_T_710, _T_711) node _T_713 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_714 = and(_T_712, _T_713) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_715 = shr(io.in.a.bits.source, 2) node _T_716 = eq(_T_715, UInt<2>(0h3)) node _T_717 = leq(UInt<1>(0h0), uncommonBits_35) node _T_718 = and(_T_716, _T_717) node _T_719 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_720 = and(_T_718, _T_719) node _T_721 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_722 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_725 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_726 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_727 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_728 = or(_T_696, _T_702) node _T_729 = or(_T_728, _T_708) node _T_730 = or(_T_729, _T_714) node _T_731 = or(_T_730, _T_720) node _T_732 = or(_T_731, _T_721) node _T_733 = or(_T_732, _T_722) node _T_734 = or(_T_733, _T_723) node _T_735 = or(_T_734, _T_724) node _T_736 = or(_T_735, _T_725) node _T_737 = or(_T_736, _T_726) node _T_738 = or(_T_737, _T_727) node _T_739 = and(_T_695, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_742 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_743 = cvt(_T_742) node _T_744 = and(_T_743, asSInt(UInt<13>(0h1000))) node _T_745 = asSInt(_T_744) node _T_746 = eq(_T_745, asSInt(UInt<1>(0h0))) node _T_747 = and(_T_741, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = and(_T_740, _T_748) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_749, UInt<1>(0h1), "") : assert_36 node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(source_ok, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(is_aligned, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_759 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_759, UInt<1>(0h1), "") : assert_39 node _T_763 = eq(io.in.a.bits.mask, mask) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_763, UInt<1>(0h1), "") : assert_40 node _T_767 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_767 : node _T_768 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_769 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_770 = and(_T_768, _T_769) node _T_771 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<1>(0h0)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_36) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<1>(0h1)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_37) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_784 = shr(io.in.a.bits.source, 2) node _T_785 = eq(_T_784, UInt<2>(0h2)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_38) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_789 = and(_T_787, _T_788) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_790 = shr(io.in.a.bits.source, 2) node _T_791 = eq(_T_790, UInt<2>(0h3)) node _T_792 = leq(UInt<1>(0h0), uncommonBits_39) node _T_793 = and(_T_791, _T_792) node _T_794 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_802 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_803 = or(_T_771, _T_777) node _T_804 = or(_T_803, _T_783) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_795) node _T_807 = or(_T_806, _T_796) node _T_808 = or(_T_807, _T_797) node _T_809 = or(_T_808, _T_798) node _T_810 = or(_T_809, _T_799) node _T_811 = or(_T_810, _T_800) node _T_812 = or(_T_811, _T_801) node _T_813 = or(_T_812, _T_802) node _T_814 = and(_T_770, _T_813) node _T_815 = or(UInt<1>(0h0), _T_814) node _T_816 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_817 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_818 = cvt(_T_817) node _T_819 = and(_T_818, asSInt(UInt<13>(0h1000))) node _T_820 = asSInt(_T_819) node _T_821 = eq(_T_820, asSInt(UInt<1>(0h0))) node _T_822 = and(_T_816, _T_821) node _T_823 = or(UInt<1>(0h0), _T_822) node _T_824 = and(_T_815, _T_823) node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(_T_824, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_824, UInt<1>(0h1), "") : assert_41 node _T_828 = asUInt(reset) node _T_829 = eq(_T_828, UInt<1>(0h0)) when _T_829 : node _T_830 = eq(source_ok, UInt<1>(0h0)) when _T_830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(is_aligned, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_834 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_834, UInt<1>(0h1), "") : assert_44 node _T_838 = eq(io.in.a.bits.mask, mask) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_838, UInt<1>(0h1), "") : assert_45 node _T_842 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_842 : node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_847 = shr(io.in.a.bits.source, 2) node _T_848 = eq(_T_847, UInt<1>(0h0)) node _T_849 = leq(UInt<1>(0h0), uncommonBits_40) node _T_850 = and(_T_848, _T_849) node _T_851 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<1>(0h1)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_41) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<2>(0h2)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_42) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_865 = shr(io.in.a.bits.source, 2) node _T_866 = eq(_T_865, UInt<2>(0h3)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_43) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_870 = and(_T_868, _T_869) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_873 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_874 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_875 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_876 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_878 = or(_T_846, _T_852) node _T_879 = or(_T_878, _T_858) node _T_880 = or(_T_879, _T_864) node _T_881 = or(_T_880, _T_870) node _T_882 = or(_T_881, _T_871) node _T_883 = or(_T_882, _T_872) node _T_884 = or(_T_883, _T_873) node _T_885 = or(_T_884, _T_874) node _T_886 = or(_T_885, _T_875) node _T_887 = or(_T_886, _T_876) node _T_888 = or(_T_887, _T_877) node _T_889 = and(_T_845, _T_888) node _T_890 = or(UInt<1>(0h0), _T_889) node _T_891 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_892 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), _T_897) node _T_899 = and(_T_890, _T_898) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_899, UInt<1>(0h1), "") : assert_46 node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(source_ok, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(is_aligned, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_909 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(_T_909, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_909, UInt<1>(0h1), "") : assert_49 node _T_913 = eq(io.in.a.bits.mask, mask) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_913, UInt<1>(0h1), "") : assert_50 node _T_917 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_917, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_921 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_921, UInt<1>(0h1), "") : assert_52 node _source_ok_T_42 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h0)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<1>(0h1)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h2)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<2>(0h3)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_68 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[12] connect _source_ok_WIRE_1[0], _source_ok_T_42 connect _source_ok_WIRE_1[1], _source_ok_T_48 connect _source_ok_WIRE_1[2], _source_ok_T_54 connect _source_ok_WIRE_1[3], _source_ok_T_60 connect _source_ok_WIRE_1[4], _source_ok_T_66 connect _source_ok_WIRE_1[5], _source_ok_T_67 connect _source_ok_WIRE_1[6], _source_ok_T_68 connect _source_ok_WIRE_1[7], _source_ok_T_69 connect _source_ok_WIRE_1[8], _source_ok_T_70 connect _source_ok_WIRE_1[9], _source_ok_T_71 connect _source_ok_WIRE_1[10], _source_ok_T_72 connect _source_ok_WIRE_1[11], _source_ok_T_73 node _source_ok_T_74 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[2]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[3]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[4]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[5]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[6]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[7]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[8]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[9]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[10]) node source_ok_1 = or(_source_ok_T_83, _source_ok_WIRE_1[11]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_925 : node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(source_ok_1, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_929 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_929, UInt<1>(0h1), "") : assert_54 node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_933, UInt<1>(0h1), "") : assert_55 node _T_937 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_937, UInt<1>(0h1), "") : assert_56 node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_941, UInt<1>(0h1), "") : assert_57 node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_945 : node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok_1, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(sink_ok, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_952 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_952, UInt<1>(0h1), "") : assert_60 node _T_956 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_956, UInt<1>(0h1), "") : assert_61 node _T_960 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_960, UInt<1>(0h1), "") : assert_62 node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_964, UInt<1>(0h1), "") : assert_63 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_969, UInt<1>(0h1), "") : assert_64 node _T_973 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(sink_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_980 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_980, UInt<1>(0h1), "") : assert_67 node _T_984 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_984, UInt<1>(0h1), "") : assert_68 node _T_988 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_988, UInt<1>(0h1), "") : assert_69 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(_T_992, io.in.d.bits.corrupt) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_993, UInt<1>(0h1), "") : assert_70 node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_998 = or(UInt<1>(0h0), _T_997) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_998, UInt<1>(0h1), "") : assert_71 node _T_1002 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_73 node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_74 node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1015 = or(UInt<1>(0h0), _T_1014) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_75 node _T_1019 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1019 : node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(source_ok_1, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1023 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_77 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = or(_T_1027, io.in.d.bits.corrupt) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_78 node _T_1032 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1033 = or(UInt<1>(0h0), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_79 node _T_1037 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1037 : node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(source_ok_1, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_81 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_82 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1054 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1058 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1062 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1066 = eq(a_first, UInt<1>(0h0)) node _T_1067 = and(io.in.a.valid, _T_1066) when _T_1067 : node _T_1068 = eq(io.in.a.bits.opcode, opcode) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_87 node _T_1072 = eq(io.in.a.bits.param, param) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_88 node _T_1076 = eq(io.in.a.bits.size, size) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_89 node _T_1080 = eq(io.in.a.bits.source, source) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_90 node _T_1084 = eq(io.in.a.bits.address, address) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_91 node _T_1088 = and(io.in.a.ready, io.in.a.valid) node _T_1089 = and(_T_1088, a_first) when _T_1089 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1090 = eq(d_first, UInt<1>(0h0)) node _T_1091 = and(io.in.d.valid, _T_1090) when _T_1091 : node _T_1092 = eq(io.in.d.bits.opcode, opcode_1) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_92 node _T_1096 = eq(io.in.d.bits.param, param_1) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_93 node _T_1100 = eq(io.in.d.bits.size, size_1) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_94 node _T_1104 = eq(io.in.d.bits.source, source_1) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_95 node _T_1108 = eq(io.in.d.bits.sink, sink) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_96 node _T_1112 = eq(io.in.d.bits.denied, denied) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_97 node _T_1116 = and(io.in.d.ready, io.in.d.valid) node _T_1117 = and(_T_1116, d_first) when _T_1117 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1118 = and(io.in.a.valid, a_first_1) node _T_1119 = and(_T_1118, UInt<1>(0h1)) when _T_1119 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1120 = and(io.in.a.ready, io.in.a.valid) node _T_1121 = and(_T_1120, a_first_1) node _T_1122 = and(_T_1121, UInt<1>(0h1)) when _T_1122 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1123 = dshr(inflight, io.in.a.bits.source) node _T_1124 = bits(_T_1123, 0, 0) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1129 = and(io.in.d.valid, d_first_1) node _T_1130 = and(_T_1129, UInt<1>(0h1)) node _T_1131 = eq(d_release_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1133 = and(io.in.d.ready, io.in.d.valid) node _T_1134 = and(_T_1133, d_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) node _T_1136 = eq(d_release_ack, UInt<1>(0h0)) node _T_1137 = and(_T_1135, _T_1136) when _T_1137 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1138 = and(io.in.d.valid, d_first_1) node _T_1139 = and(_T_1138, UInt<1>(0h1)) node _T_1140 = eq(d_release_ack, UInt<1>(0h0)) node _T_1141 = and(_T_1139, _T_1140) when _T_1141 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1142 = dshr(inflight, io.in.d.bits.source) node _T_1143 = bits(_T_1142, 0, 0) node _T_1144 = or(_T_1143, same_cycle_resp) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1148 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1149 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1150 = or(_T_1148, _T_1149) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_100 node _T_1154 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_101 else : node _T_1158 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1159 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1160 = or(_T_1158, _T_1159) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_102 node _T_1164 = eq(io.in.d.bits.size, a_size_lookup) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_103 node _T_1168 = and(io.in.d.valid, d_first_1) node _T_1169 = and(_T_1168, a_first_1) node _T_1170 = and(_T_1169, io.in.a.valid) node _T_1171 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1172 = and(_T_1170, _T_1171) node _T_1173 = eq(d_release_ack, UInt<1>(0h0)) node _T_1174 = and(_T_1172, _T_1173) when _T_1174 : node _T_1175 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1176 = or(_T_1175, io.in.a.ready) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_52 node _T_1180 = orr(inflight) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) node _T_1182 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1183 = or(_T_1181, _T_1182) node _T_1184 = lt(watchdog, plusarg_reader.out) node _T_1185 = or(_T_1183, _T_1184) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1189 = and(io.in.a.ready, io.in.a.valid) node _T_1190 = and(io.in.d.ready, io.in.d.valid) node _T_1191 = or(_T_1189, _T_1190) when _T_1191 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1192 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1193 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1194 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = and(_T_1192, _T_1195) when _T_1196 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1197 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1198 = and(_T_1197, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1199 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1200 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = and(_T_1198, _T_1201) when _T_1202 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1203 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1209 = and(io.in.d.valid, d_first_2) node _T_1210 = and(_T_1209, UInt<1>(0h1)) node _T_1211 = and(_T_1210, d_release_ack_1) when _T_1211 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1212 = and(io.in.d.ready, io.in.d.valid) node _T_1213 = and(_T_1212, d_first_2) node _T_1214 = and(_T_1213, UInt<1>(0h1)) node _T_1215 = and(_T_1214, d_release_ack_1) when _T_1215 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1216 = and(io.in.d.valid, d_first_2) node _T_1217 = and(_T_1216, UInt<1>(0h1)) node _T_1218 = and(_T_1217, d_release_ack_1) when _T_1218 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1219 = dshr(inflight_1, io.in.d.bits.source) node _T_1220 = bits(_T_1219, 0, 0) node _T_1221 = or(_T_1220, same_cycle_resp_1) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1225 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_108 else : node _T_1229 = eq(io.in.d.bits.size, c_size_lookup) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_109 node _T_1233 = and(io.in.d.valid, d_first_2) node _T_1234 = and(_T_1233, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1235 = and(_T_1234, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1236 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1237 = and(_T_1235, _T_1236) node _T_1238 = and(_T_1237, d_release_ack_1) node _T_1239 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1240 = and(_T_1238, _T_1239) when _T_1240 : node _T_1241 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1242 = or(_T_1241, _WIRE_27.ready) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_53 node _T_1246 = orr(inflight_1) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) node _T_1248 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1249 = or(_T_1247, _T_1248) node _T_1250 = lt(watchdog_1, plusarg_reader_1.out) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1255 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1256 = and(io.in.d.ready, io.in.d.valid) node _T_1257 = or(_T_1255, _T_1256) when _T_1257 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_26( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_41 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_61 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_44 = _source_ok_T_43 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire _source_ok_T_67 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire _source_ok_T_68 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire _source_ok_T_69 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_83 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _T_1189 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1189; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1189; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1257 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1257; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1122 = _T_1189 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1122 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1122 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1122 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1122 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1122 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1168 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1168 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1137 = _T_1257 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1137 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1137 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1137 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1233 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1233 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1215 = _T_1257 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1215 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1215 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1215 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_12 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] connect auto.out, nodeOut connect nodeIn, auto.in inst reg of AsyncResetRegVec_w1_i0_12 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] connect reg.io.en, UInt<1>(0h1) node _T = bits(reg.io.q, 0, 0) connect nodeOut.sync[0], _T

module IntSyncCrossingSource_n1x1_12( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_12 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_205 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_205( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module Router_12 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[4], sa_stall : UInt[4]}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_12 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_1.flit.bits.egress_id invalidate ingressNodesIn_1.flit.bits.payload invalidate ingressNodesIn_1.flit.bits.tail invalidate ingressNodesIn_1.flit.bits.head invalidate ingressNodesIn_1.flit.valid invalidate ingressNodesIn_1.flit.ready wire ingressNodesIn_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_2.flit.bits.egress_id invalidate ingressNodesIn_2.flit.bits.payload invalidate ingressNodesIn_2.flit.bits.tail invalidate ingressNodesIn_2.flit.bits.head invalidate ingressNodesIn_2.flit.valid invalidate ingressNodesIn_2.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut_1.flit.bits.ingress_id invalidate egressNodesOut_1.flit.bits.payload invalidate egressNodesOut_1.flit.bits.tail invalidate egressNodesOut_1.flit.bits.head invalidate egressNodesOut_1.flit.valid invalidate egressNodesOut_1.flit.ready wire debugNodeOut : { va_stall : UInt[4], sa_stall : UInt[4]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.sa_stall[3] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] invalidate debugNodeOut.va_stall[3] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in_0 connect ingressNodesIn_1, auto.ingress_nodes_in_1 connect ingressNodesIn_2, auto.ingress_nodes_in_2 connect auto.egress_nodes_out_0, egressNodesOut connect auto.egress_nodes_out_1, egressNodesOut_1 connect auto.debug_out, debugNodeOut inst input_unit_0_from_29 of InputUnit_12 connect input_unit_0_from_29.clock, clock connect input_unit_0_from_29.reset, reset inst ingress_unit_1_from_21 of IngressUnit_31 connect ingress_unit_1_from_21.clock, clock connect ingress_unit_1_from_21.reset, reset inst ingress_unit_2_from_22 of IngressUnit_32 connect ingress_unit_2_from_22.clock, clock connect ingress_unit_2_from_22.reset, reset inst ingress_unit_3_from_23 of IngressUnit_33 connect ingress_unit_3_from_23.clock, clock connect ingress_unit_3_from_23.reset, reset inst output_unit_0_to_29 of OutputUnit_12 connect output_unit_0_to_29.clock, clock connect output_unit_0_to_29.reset, reset inst egress_unit_1_to_14 of EgressUnit_29 connect egress_unit_1_to_14.clock, clock connect egress_unit_1_to_14.reset, reset inst egress_unit_2_to_15 of EgressUnit_30 connect egress_unit_2_to_15.clock, clock connect egress_unit_2_to_15.reset, reset inst switch of Switch_12 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_12 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_12 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_12 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid) node _fires_count_T_4 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_5 = bits(_fires_count_T_4, 1, 0) node _fires_count_T_6 = add(_fires_count_T_2, _fires_count_T_3) node _fires_count_T_7 = bits(_fires_count_T_6, 1, 0) node _fires_count_T_8 = add(_fires_count_T_5, _fires_count_T_7) node _fires_count_T_9 = bits(_fires_count_T_8, 2, 0) wire fires_count : UInt connect fires_count, _fires_count_T_9 connect input_unit_0_from_29.io.in, destNodesIn connect ingress_unit_1_from_21.io.in, ingressNodesIn.flit connect ingress_unit_2_from_22.io.in, ingressNodesIn_1.flit connect ingress_unit_3_from_23.io.in, ingressNodesIn_2.flit connect output_unit_0_to_29.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_29.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_29.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_14.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_14.io.out.valid connect egress_unit_1_to_14.io.out.ready, egressNodesOut.flit.ready connect egressNodesOut_1.flit.bits, egress_unit_2_to_15.io.out.bits connect egressNodesOut_1.flit.valid, egress_unit_2_to_15.io.out.valid connect egress_unit_2_to_15.io.out.ready, egressNodesOut_1.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_29.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_21.io.router_req connect route_computer.io.req.`2`, ingress_unit_2_from_22.io.router_req connect route_computer.io.req.`3`, ingress_unit_3_from_23.io.router_req connect input_unit_0_from_29.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_21.io.router_resp, route_computer.io.resp.`1` connect ingress_unit_2_from_22.io.router_resp, route_computer.io.resp.`2` connect ingress_unit_3_from_23.io.router_resp, route_computer.io.resp.`3` connect vc_allocator.io.req.`0`, input_unit_0_from_29.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_21.io.vcalloc_req connect vc_allocator.io.req.`2`, ingress_unit_2_from_22.io.vcalloc_req connect vc_allocator.io.req.`3`, ingress_unit_3_from_23.io.vcalloc_req connect input_unit_0_from_29.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_21.io.vcalloc_resp, vc_allocator.io.resp.`1` connect ingress_unit_2_from_22.io.vcalloc_resp, vc_allocator.io.resp.`2` connect ingress_unit_3_from_23.io.vcalloc_resp, vc_allocator.io.resp.`3` connect output_unit_0_to_29.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_14.io.allocs, vc_allocator.io.out_allocs.`1` connect egress_unit_2_to_15.io.allocs, vc_allocator.io.out_allocs.`2` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_29.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_29.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_29.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_29.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_29.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_29.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_29.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_29.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_29.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_29.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_29.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_29.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_29.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_29.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_29.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_29.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_29.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_29.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_29.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_29.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_29.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_29.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_29.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_29.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_29.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_29.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_29.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_29.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_29.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_29.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_29.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_29.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_29.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_29.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_29.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_29.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_29.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_29.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_29.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_29.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_29.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_14.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_14.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_14.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_14.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_14.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_14.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_15.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_15.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_15.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_15.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_15.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_15.io.channel_status[0].occupied connect input_unit_0_from_29.io.out_credit_available.`0`[0], output_unit_0_to_29.io.credit_available[0] connect input_unit_0_from_29.io.out_credit_available.`0`[1], output_unit_0_to_29.io.credit_available[1] connect input_unit_0_from_29.io.out_credit_available.`0`[2], output_unit_0_to_29.io.credit_available[2] connect input_unit_0_from_29.io.out_credit_available.`0`[3], output_unit_0_to_29.io.credit_available[3] connect input_unit_0_from_29.io.out_credit_available.`0`[4], output_unit_0_to_29.io.credit_available[4] connect input_unit_0_from_29.io.out_credit_available.`0`[5], output_unit_0_to_29.io.credit_available[5] connect input_unit_0_from_29.io.out_credit_available.`0`[6], output_unit_0_to_29.io.credit_available[6] connect input_unit_0_from_29.io.out_credit_available.`0`[7], output_unit_0_to_29.io.credit_available[7] connect input_unit_0_from_29.io.out_credit_available.`1`[0], egress_unit_1_to_14.io.credit_available[0] connect input_unit_0_from_29.io.out_credit_available.`2`[0], egress_unit_2_to_15.io.credit_available[0] connect ingress_unit_1_from_21.io.out_credit_available.`0`[0], output_unit_0_to_29.io.credit_available[0] connect ingress_unit_1_from_21.io.out_credit_available.`0`[1], output_unit_0_to_29.io.credit_available[1] connect ingress_unit_1_from_21.io.out_credit_available.`0`[2], output_unit_0_to_29.io.credit_available[2] connect ingress_unit_1_from_21.io.out_credit_available.`0`[3], output_unit_0_to_29.io.credit_available[3] connect ingress_unit_1_from_21.io.out_credit_available.`0`[4], output_unit_0_to_29.io.credit_available[4] connect ingress_unit_1_from_21.io.out_credit_available.`0`[5], output_unit_0_to_29.io.credit_available[5] connect ingress_unit_1_from_21.io.out_credit_available.`0`[6], output_unit_0_to_29.io.credit_available[6] connect ingress_unit_1_from_21.io.out_credit_available.`0`[7], output_unit_0_to_29.io.credit_available[7] connect ingress_unit_1_from_21.io.out_credit_available.`1`[0], egress_unit_1_to_14.io.credit_available[0] connect ingress_unit_1_from_21.io.out_credit_available.`2`[0], egress_unit_2_to_15.io.credit_available[0] connect ingress_unit_2_from_22.io.out_credit_available.`0`[0], output_unit_0_to_29.io.credit_available[0] connect ingress_unit_2_from_22.io.out_credit_available.`0`[1], output_unit_0_to_29.io.credit_available[1] connect ingress_unit_2_from_22.io.out_credit_available.`0`[2], output_unit_0_to_29.io.credit_available[2] connect ingress_unit_2_from_22.io.out_credit_available.`0`[3], output_unit_0_to_29.io.credit_available[3] connect ingress_unit_2_from_22.io.out_credit_available.`0`[4], output_unit_0_to_29.io.credit_available[4] connect ingress_unit_2_from_22.io.out_credit_available.`0`[5], output_unit_0_to_29.io.credit_available[5] connect ingress_unit_2_from_22.io.out_credit_available.`0`[6], output_unit_0_to_29.io.credit_available[6] connect ingress_unit_2_from_22.io.out_credit_available.`0`[7], output_unit_0_to_29.io.credit_available[7] connect ingress_unit_2_from_22.io.out_credit_available.`1`[0], egress_unit_1_to_14.io.credit_available[0] connect ingress_unit_2_from_22.io.out_credit_available.`2`[0], egress_unit_2_to_15.io.credit_available[0] connect ingress_unit_3_from_23.io.out_credit_available.`0`[0], output_unit_0_to_29.io.credit_available[0] connect ingress_unit_3_from_23.io.out_credit_available.`0`[1], output_unit_0_to_29.io.credit_available[1] connect ingress_unit_3_from_23.io.out_credit_available.`0`[2], output_unit_0_to_29.io.credit_available[2] connect ingress_unit_3_from_23.io.out_credit_available.`0`[3], output_unit_0_to_29.io.credit_available[3] connect ingress_unit_3_from_23.io.out_credit_available.`0`[4], output_unit_0_to_29.io.credit_available[4] connect ingress_unit_3_from_23.io.out_credit_available.`0`[5], output_unit_0_to_29.io.credit_available[5] connect ingress_unit_3_from_23.io.out_credit_available.`0`[6], output_unit_0_to_29.io.credit_available[6] connect ingress_unit_3_from_23.io.out_credit_available.`0`[7], output_unit_0_to_29.io.credit_available[7] connect ingress_unit_3_from_23.io.out_credit_available.`1`[0], egress_unit_1_to_14.io.credit_available[0] connect ingress_unit_3_from_23.io.out_credit_available.`2`[0], egress_unit_2_to_15.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_29.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_21.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_22.io.salloc_req[0] connect switch_allocator.io.req.`3`[0], ingress_unit_3_from_23.io.salloc_req[0] connect output_unit_0_to_29.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_29.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_29.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_29.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_29.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_29.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_29.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_29.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_29.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_29.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_0_to_29.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail connect output_unit_0_to_29.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc connect output_unit_0_to_29.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail connect output_unit_0_to_29.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc connect output_unit_0_to_29.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail connect output_unit_0_to_29.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc connect egress_unit_1_to_14.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_14.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect egress_unit_2_to_15.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect egress_unit_2_to_15.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_29.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_21.io.out[0] connect switch.io.in.`2`[0], ingress_unit_2_from_22.io.out[0] connect switch.io.in.`3`[0], ingress_unit_3_from_23.io.out[0] connect output_unit_0_to_29.io.in, switch.io.out.`0` connect egress_unit_1_to_14.io.in, switch.io.out.`1` connect egress_unit_2_to_15.io.in, switch.io.out.`2` reg REG : { `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`0`[0].`3`[0], REG.`0`[0].`3`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`1`[0].`3`[0], REG.`1`[0].`3`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect switch.io.sel.`2`[0].`3`[0], REG.`2`[0].`3`[0] connect input_unit_0_from_29.io.block, UInt<1>(0h0) connect ingress_unit_1_from_21.io.block, UInt<1>(0h0) connect ingress_unit_2_from_22.io.block, UInt<1>(0h0) connect ingress_unit_3_from_23.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_29.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_21.io.debug.va_stall connect debugNodeOut.va_stall[2], ingress_unit_2_from_22.io.debug.va_stall connect debugNodeOut.va_stall[3], ingress_unit_3_from_23.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_29.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_21.io.debug.sa_stall connect debugNodeOut.sa_stall[2], ingress_unit_2_from_22.io.debug.sa_stall connect debugNodeOut.sa_stall[3], ingress_unit_3_from_23.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_30 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 29 13 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i21 13 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d i22 13 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20 node _T_29 = and(ingressNodesIn_2.flit.ready, ingressNodesIn_2.flit.valid) regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, _T_29) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, _T_29) connect fired_3, _fired_T_3 node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_32 = tail(_T_31, 1) node _T_33 = eq(debug_sample, _T_32) node _T_34 = and(_T_30, _T_33) node _T_35 = and(_T_34, fired_3) when _T_35 : node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "nocsample %d i23 13 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, _T_29 node _T_38 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, _T_38) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, _T_38) connect fired_4, _fired_T_4 node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_41 = tail(_T_40, 1) node _T_42 = eq(debug_sample, _T_41) node _T_43 = and(_T_39, _T_42) node _T_44 = and(_T_43, fired_4) when _T_44 : node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : printf(clock, UInt<1>(0h1), "nocsample %d 13 e14 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, _T_38 node _T_47 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid) regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_10 = add(util_ctr_5, _T_47) node _util_ctr_T_11 = tail(_util_ctr_T_10, 1) connect util_ctr_5, _util_ctr_T_11 node _fired_T_5 = or(fired_5, _T_47) connect fired_5, _fired_T_5 node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_50 = tail(_T_49, 1) node _T_51 = eq(debug_sample, _T_50) node _T_52 = and(_T_48, _T_51) node _T_53 = and(_T_52, fired_5) when _T_53 : node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "nocsample %d 13 e15 %d\n", debug_tsc, util_ctr_5) : printf_5 connect fired_5, _T_47

module Router_12( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [5:0] auto_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_2_to_15_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_2_to_15_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_2_to_15_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_1_to_14_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_14_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_14_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_29_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_29_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _ingress_unit_3_from_23_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_3_from_23_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_23_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_23_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_23_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_23_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_23_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_23_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_3_from_23_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_2_from_22_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_22_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_22_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_22_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_1_from_21_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_21_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_21_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_21_io_in_ready; // @[Router.scala:116:13] wire _input_unit_0_from_29_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_29_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_29_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_29_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_29_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_29_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_29_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_29_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_29_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_21_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_22_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_23_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg REG_2_0_3_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_3_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_3_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_63 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_129 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_130 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_20 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_20( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter : input clock : Clock input reset : Reset output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlNodeIn.d.bits.corrupt invalidate tlNodeIn.d.bits.data invalidate tlNodeIn.d.bits.denied invalidate tlNodeIn.d.bits.sink invalidate tlNodeIn.d.bits.source invalidate tlNodeIn.d.bits.size invalidate tlNodeIn.d.bits.param invalidate tlNodeIn.d.bits.opcode invalidate tlNodeIn.d.valid invalidate tlNodeIn.d.ready invalidate tlNodeIn.a.bits.corrupt invalidate tlNodeIn.a.bits.data invalidate tlNodeIn.a.bits.mask invalidate tlNodeIn.a.bits.address invalidate tlNodeIn.a.bits.source invalidate tlNodeIn.a.bits.size invalidate tlNodeIn.a.bits.param invalidate tlNodeIn.a.bits.opcode invalidate tlNodeIn.a.valid invalidate tlNodeIn.a.ready inst monitor of TLMonitor_67 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, tlNodeIn.d.valid connect monitor.io.in.d.ready, tlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, tlNodeIn.a.valid connect monitor.io.in.a.ready, tlNodeIn.a.ready wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeOut.member.allClocks_uncore.reset invalidate clockNodeOut.member.allClocks_uncore.clock wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeIn.member.allClocks_uncore.reset invalidate clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut, clockNodeIn connect tlNodeIn, auto.tl_in connect auto.clock_out, clockNodeOut connect clockNodeIn, auto.clock_in wire tile_async_resets : Reset[1] node _tile_async_resets_0_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[0], _tile_async_resets_0_T inst r_tile_resets_0 of AsyncResetRegVec_w1_i0_6 connect r_tile_resets_0.clock, clock connect r_tile_resets_0.reset, tile_async_resets[0] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(tlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, tlNodeIn.a.bits.data connect in.bits.mask, tlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect r_tile_resets_0.io.en, out_f_woready connect r_tile_resets_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(r_tile_resets_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, tlNodeIn.a.valid connect tlNodeIn.a.ready, in.ready connect tlNodeIn.d.valid, out.valid connect out.ready, tlNodeIn.d.ready wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect tlNodeIn_d_bits_d.param, UInt<1>(0h0) connect tlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect tlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate tlNodeIn_d_bits_d.data connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode connect tlNodeIn.d.bits.data, out.bits.data node _tlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset extmodule plusarg_reader_140 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_141 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] wire [11:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33] wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_WIRE_1_0 = 1'h0; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_T_3 = 1'h0; // @[MuxLiteral.scala:49:10] wire _out_out_bits_data_T_4 = 1'h0; // @[RegisterRouter.scala:87:24] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25] wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [11:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] wire [11:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_67 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i0_6 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15] .clock (clock), .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileResetSetter.scala:33:15] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_41 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_41( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLDFromNoC_10 : input clock : Clock input reset : Reset output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, ingress_id : UInt}}} wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1) reg const_reg : UInt<16>, clock node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg) node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0)) node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T) node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready) connect io.flit.ready, _io_flit_ready_T_2 node _protocol_valid_T = eq(is_const, UInt<1>(0h0)) node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail) node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid) connect protocol.valid, _protocol_valid_T_2 wire _protocol_bits_denied_WIRE : UInt<1> connect _protocol_bits_denied_WIRE, const connect protocol.bits.denied, _protocol_bits_denied_WIRE node _T = shr(const, 1) wire _protocol_bits_sink_WIRE : UInt<1> connect _protocol_bits_sink_WIRE, _T connect protocol.bits.sink, _protocol_bits_sink_WIRE node _T_1 = shr(_T, 1) wire _protocol_bits_echo_WIRE : { } wire _protocol_bits_echo_WIRE_1 : UInt<0> connect _protocol_bits_echo_WIRE_1, _T_1 connect protocol.bits.echo, _protocol_bits_echo_WIRE node _T_2 = shr(_T_1, 0) wire _protocol_bits_user_WIRE : { } wire _protocol_bits_user_WIRE_1 : UInt<0> connect _protocol_bits_user_WIRE_1, _T_2 connect protocol.bits.user, _protocol_bits_user_WIRE node _T_3 = shr(_T_2, 0) wire _protocol_bits_source_WIRE : UInt<6> connect _protocol_bits_source_WIRE, _T_3 connect protocol.bits.source, _protocol_bits_source_WIRE node _T_4 = shr(_T_3, 6) wire _protocol_bits_size_WIRE : UInt<3> connect _protocol_bits_size_WIRE, _T_4 connect protocol.bits.size, _protocol_bits_size_WIRE node _T_5 = shr(_T_4, 3) wire _protocol_bits_param_WIRE : UInt<2> connect _protocol_bits_param_WIRE, _T_5 connect protocol.bits.param, _protocol_bits_param_WIRE node _T_6 = shr(_T_5, 2) wire _protocol_bits_opcode_WIRE : UInt<3> connect _protocol_bits_opcode_WIRE, _T_6 connect protocol.bits.opcode, _protocol_bits_opcode_WIRE node _T_7 = shr(_T_6, 3) wire _protocol_bits_corrupt_WIRE : UInt<1> connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE node _T_8 = shr(io.flit.bits.payload, 1) wire _protocol_bits_data_WIRE : UInt<64> connect _protocol_bits_data_WIRE, _T_8 connect protocol.bits.data, _protocol_bits_data_WIRE node _T_9 = shr(_T_8, 64) node _T_10 = and(io.flit.ready, io.flit.valid) node _T_11 = and(_T_10, io.flit.bits.head) when _T_11 : connect is_const, UInt<1>(0h0) connect const_reg, io.flit.bits.payload node _T_12 = and(io.flit.ready, io.flit.valid) node _T_13 = and(_T_12, io.flit.bits.tail) when _T_13 : connect is_const, UInt<1>(0h1) connect io.protocol, protocol node _io_protocol_bits_source_T = bits(protocol.bits.source, 3, 0) connect io.protocol.bits.source, _io_protocol_bits_source_T

module TLDFromNoC_10( // @[TilelinkAdapters.scala:185:7] input clock, // @[TilelinkAdapters.scala:185:7] input reset, // @[TilelinkAdapters.scala:185:7] input io_protocol_ready, // @[TilelinkAdapters.scala:56:14] output io_protocol_valid, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14] output [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14] output [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_sink, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_denied, // @[TilelinkAdapters.scala:56:14] output [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14] output io_flit_ready, // @[TilelinkAdapters.scala:56:14] input io_flit_valid, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14] input [64:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14] ); reg is_const; // @[TilelinkAdapters.scala:68:25] reg [15:0] const_reg; // @[TilelinkAdapters.scala:69:22] wire [15:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[15:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18] wire io_flit_ready_0 = is_const & ~io_flit_bits_tail | io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}] wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35] wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:185:7] if (reset) // @[TilelinkAdapters.scala:185:7] is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :185:7] else // @[TilelinkAdapters.scala:185:7] is_const <= _GEN & io_flit_bits_tail | ~_GEN_0 & is_const; // @[Decoupled.scala:51:35] if (_GEN_0) // @[TilelinkAdapters.scala:84:22] const_reg <= io_flit_bits_payload[15:0]; // @[TilelinkAdapters.scala:56:14, :69:22] always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_95 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_95( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ZstdCompressorLitRotBuf_2 : input clock : Clock input reset : Reset output io : { flip memwrites_in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>}}, consumer : { flip user_consumed_bytes : UInt<6>, available_output_bytes : UInt<6>, output_valid : UInt<1>, flip output_ready : UInt<1>, output_data : UInt<256>, output_last_chunk : UInt<1>}} inst incoming_writes_Q of Queue4_WriterBundle_12 connect incoming_writes_Q.clock, clock connect incoming_writes_Q.reset, reset connect incoming_writes_Q.io.enq, io.memwrites_in node _T = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid) when _T : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "[lit-rot-buf] dat: 0x%x, bytes: 0x%x, EOM: %d\n", incoming_writes_Q.io.deq.bits.data, incoming_writes_Q.io.deq.bits.validbytes, incoming_writes_Q.io.deq.bits.end_of_message) : printf_1 regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0) inst Queue10_UInt8 of Queue10_UInt8_96 connect Queue10_UInt8.clock, clock connect Queue10_UInt8.reset, reset inst Queue10_UInt8_1 of Queue10_UInt8_97 connect Queue10_UInt8_1.clock, clock connect Queue10_UInt8_1.reset, reset inst Queue10_UInt8_2 of Queue10_UInt8_98 connect Queue10_UInt8_2.clock, clock connect Queue10_UInt8_2.reset, reset inst Queue10_UInt8_3 of Queue10_UInt8_99 connect Queue10_UInt8_3.clock, clock connect Queue10_UInt8_3.reset, reset inst Queue10_UInt8_4 of Queue10_UInt8_100 connect Queue10_UInt8_4.clock, clock connect Queue10_UInt8_4.reset, reset inst Queue10_UInt8_5 of Queue10_UInt8_101 connect Queue10_UInt8_5.clock, clock connect Queue10_UInt8_5.reset, reset inst Queue10_UInt8_6 of Queue10_UInt8_102 connect Queue10_UInt8_6.clock, clock connect Queue10_UInt8_6.reset, reset inst Queue10_UInt8_7 of Queue10_UInt8_103 connect Queue10_UInt8_7.clock, clock connect Queue10_UInt8_7.reset, reset inst Queue10_UInt8_8 of Queue10_UInt8_104 connect Queue10_UInt8_8.clock, clock connect Queue10_UInt8_8.reset, reset inst Queue10_UInt8_9 of Queue10_UInt8_105 connect Queue10_UInt8_9.clock, clock connect Queue10_UInt8_9.reset, reset inst Queue10_UInt8_10 of Queue10_UInt8_106 connect Queue10_UInt8_10.clock, clock connect Queue10_UInt8_10.reset, reset inst Queue10_UInt8_11 of Queue10_UInt8_107 connect Queue10_UInt8_11.clock, clock connect Queue10_UInt8_11.reset, reset inst Queue10_UInt8_12 of Queue10_UInt8_108 connect Queue10_UInt8_12.clock, clock connect Queue10_UInt8_12.reset, reset inst Queue10_UInt8_13 of Queue10_UInt8_109 connect Queue10_UInt8_13.clock, clock connect Queue10_UInt8_13.reset, reset inst Queue10_UInt8_14 of Queue10_UInt8_110 connect Queue10_UInt8_14.clock, clock connect Queue10_UInt8_14.reset, reset inst Queue10_UInt8_15 of Queue10_UInt8_111 connect Queue10_UInt8_15.clock, clock connect Queue10_UInt8_15.reset, reset inst Queue10_UInt8_16 of Queue10_UInt8_112 connect Queue10_UInt8_16.clock, clock connect Queue10_UInt8_16.reset, reset inst Queue10_UInt8_17 of Queue10_UInt8_113 connect Queue10_UInt8_17.clock, clock connect Queue10_UInt8_17.reset, reset inst Queue10_UInt8_18 of Queue10_UInt8_114 connect Queue10_UInt8_18.clock, clock connect Queue10_UInt8_18.reset, reset inst Queue10_UInt8_19 of Queue10_UInt8_115 connect Queue10_UInt8_19.clock, clock connect Queue10_UInt8_19.reset, reset inst Queue10_UInt8_20 of Queue10_UInt8_116 connect Queue10_UInt8_20.clock, clock connect Queue10_UInt8_20.reset, reset inst Queue10_UInt8_21 of Queue10_UInt8_117 connect Queue10_UInt8_21.clock, clock connect Queue10_UInt8_21.reset, reset inst Queue10_UInt8_22 of Queue10_UInt8_118 connect Queue10_UInt8_22.clock, clock connect Queue10_UInt8_22.reset, reset inst Queue10_UInt8_23 of Queue10_UInt8_119 connect Queue10_UInt8_23.clock, clock connect Queue10_UInt8_23.reset, reset inst Queue10_UInt8_24 of Queue10_UInt8_120 connect Queue10_UInt8_24.clock, clock connect Queue10_UInt8_24.reset, reset inst Queue10_UInt8_25 of Queue10_UInt8_121 connect Queue10_UInt8_25.clock, clock connect Queue10_UInt8_25.reset, reset inst Queue10_UInt8_26 of Queue10_UInt8_122 connect Queue10_UInt8_26.clock, clock connect Queue10_UInt8_26.reset, reset inst Queue10_UInt8_27 of Queue10_UInt8_123 connect Queue10_UInt8_27.clock, clock connect Queue10_UInt8_27.reset, reset inst Queue10_UInt8_28 of Queue10_UInt8_124 connect Queue10_UInt8_28.clock, clock connect Queue10_UInt8_28.reset, reset inst Queue10_UInt8_29 of Queue10_UInt8_125 connect Queue10_UInt8_29.clock, clock connect Queue10_UInt8_29.reset, reset inst Queue10_UInt8_30 of Queue10_UInt8_126 connect Queue10_UInt8_30.clock, clock connect Queue10_UInt8_30.reset, reset inst Queue10_UInt8_31 of Queue10_UInt8_127 connect Queue10_UInt8_31.clock, clock connect Queue10_UInt8_31.reset, reset connect Queue10_UInt8.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_1.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_2.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_3.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_4.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_5.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_6.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_7.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_8.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_9.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_10.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_11.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_12.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_13.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_14.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_15.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_16.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_17.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_18.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_19.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_20.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_21.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_22.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_23.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_24.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_25.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_26.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_27.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_28.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_29.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_30.io.enq.bits, UInt<1>(0h0) connect Queue10_UInt8_31.io.enq.bits, UInt<1>(0h0) node _idx_T = add(write_start_index, UInt<1>(0h0)) node idx = rem(_idx_T, UInt<6>(0h20)) node _T_5 = eq(UInt<1>(0h0), idx) when _T_5 : node _T_6 = shl(UInt<1>(0h0), 3) node _T_7 = dshr(incoming_writes_Q.io.deq.bits.data, _T_6) connect Queue10_UInt8.io.enq.bits, _T_7 node _T_8 = eq(UInt<1>(0h1), idx) when _T_8 : node _T_9 = shl(UInt<1>(0h0), 3) node _T_10 = dshr(incoming_writes_Q.io.deq.bits.data, _T_9) connect Queue10_UInt8_1.io.enq.bits, _T_10 node _T_11 = eq(UInt<2>(0h2), idx) when _T_11 : node _T_12 = shl(UInt<1>(0h0), 3) node _T_13 = dshr(incoming_writes_Q.io.deq.bits.data, _T_12) connect Queue10_UInt8_2.io.enq.bits, _T_13 node _T_14 = eq(UInt<2>(0h3), idx) when _T_14 : node _T_15 = shl(UInt<1>(0h0), 3) node _T_16 = dshr(incoming_writes_Q.io.deq.bits.data, _T_15) connect Queue10_UInt8_3.io.enq.bits, _T_16 node _T_17 = eq(UInt<3>(0h4), idx) when _T_17 : node _T_18 = shl(UInt<1>(0h0), 3) node _T_19 = dshr(incoming_writes_Q.io.deq.bits.data, _T_18) connect Queue10_UInt8_4.io.enq.bits, _T_19 node _T_20 = eq(UInt<3>(0h5), idx) when _T_20 : node _T_21 = shl(UInt<1>(0h0), 3) node _T_22 = dshr(incoming_writes_Q.io.deq.bits.data, _T_21) connect Queue10_UInt8_5.io.enq.bits, _T_22 node _T_23 = eq(UInt<3>(0h6), idx) when _T_23 : node _T_24 = shl(UInt<1>(0h0), 3) node _T_25 = dshr(incoming_writes_Q.io.deq.bits.data, _T_24) connect Queue10_UInt8_6.io.enq.bits, _T_25 node _T_26 = eq(UInt<3>(0h7), idx) when _T_26 : node _T_27 = shl(UInt<1>(0h0), 3) node _T_28 = dshr(incoming_writes_Q.io.deq.bits.data, _T_27) connect Queue10_UInt8_7.io.enq.bits, _T_28 node _T_29 = eq(UInt<4>(0h8), idx) when _T_29 : node _T_30 = shl(UInt<1>(0h0), 3) node _T_31 = dshr(incoming_writes_Q.io.deq.bits.data, _T_30) connect Queue10_UInt8_8.io.enq.bits, _T_31 node _T_32 = eq(UInt<4>(0h9), idx) when _T_32 : node _T_33 = shl(UInt<1>(0h0), 3) node _T_34 = dshr(incoming_writes_Q.io.deq.bits.data, _T_33) connect Queue10_UInt8_9.io.enq.bits, _T_34 node _T_35 = eq(UInt<4>(0ha), idx) when _T_35 : node _T_36 = shl(UInt<1>(0h0), 3) node _T_37 = dshr(incoming_writes_Q.io.deq.bits.data, _T_36) connect Queue10_UInt8_10.io.enq.bits, _T_37 node _T_38 = eq(UInt<4>(0hb), idx) when _T_38 : node _T_39 = shl(UInt<1>(0h0), 3) node _T_40 = dshr(incoming_writes_Q.io.deq.bits.data, _T_39) connect Queue10_UInt8_11.io.enq.bits, _T_40 node _T_41 = eq(UInt<4>(0hc), idx) when _T_41 : node _T_42 = shl(UInt<1>(0h0), 3) node _T_43 = dshr(incoming_writes_Q.io.deq.bits.data, _T_42) connect Queue10_UInt8_12.io.enq.bits, _T_43 node _T_44 = eq(UInt<4>(0hd), idx) when _T_44 : node _T_45 = shl(UInt<1>(0h0), 3) node _T_46 = dshr(incoming_writes_Q.io.deq.bits.data, _T_45) connect Queue10_UInt8_13.io.enq.bits, _T_46 node _T_47 = eq(UInt<4>(0he), idx) when _T_47 : node _T_48 = shl(UInt<1>(0h0), 3) node _T_49 = dshr(incoming_writes_Q.io.deq.bits.data, _T_48) connect Queue10_UInt8_14.io.enq.bits, _T_49 node _T_50 = eq(UInt<4>(0hf), idx) when _T_50 : node _T_51 = shl(UInt<1>(0h0), 3) node _T_52 = dshr(incoming_writes_Q.io.deq.bits.data, _T_51) connect Queue10_UInt8_15.io.enq.bits, _T_52 node _T_53 = eq(UInt<5>(0h10), idx) when _T_53 : node _T_54 = shl(UInt<1>(0h0), 3) node _T_55 = dshr(incoming_writes_Q.io.deq.bits.data, _T_54) connect Queue10_UInt8_16.io.enq.bits, _T_55 node _T_56 = eq(UInt<5>(0h11), idx) when _T_56 : node _T_57 = shl(UInt<1>(0h0), 3) node _T_58 = dshr(incoming_writes_Q.io.deq.bits.data, _T_57) connect Queue10_UInt8_17.io.enq.bits, _T_58 node _T_59 = eq(UInt<5>(0h12), idx) when _T_59 : node _T_60 = shl(UInt<1>(0h0), 3) node _T_61 = dshr(incoming_writes_Q.io.deq.bits.data, _T_60) connect Queue10_UInt8_18.io.enq.bits, _T_61 node _T_62 = eq(UInt<5>(0h13), idx) when _T_62 : node _T_63 = shl(UInt<1>(0h0), 3) node _T_64 = dshr(incoming_writes_Q.io.deq.bits.data, _T_63) connect Queue10_UInt8_19.io.enq.bits, _T_64 node _T_65 = eq(UInt<5>(0h14), idx) when _T_65 : node _T_66 = shl(UInt<1>(0h0), 3) node _T_67 = dshr(incoming_writes_Q.io.deq.bits.data, _T_66) connect Queue10_UInt8_20.io.enq.bits, _T_67 node _T_68 = eq(UInt<5>(0h15), idx) when _T_68 : node _T_69 = shl(UInt<1>(0h0), 3) node _T_70 = dshr(incoming_writes_Q.io.deq.bits.data, _T_69) connect Queue10_UInt8_21.io.enq.bits, _T_70 node _T_71 = eq(UInt<5>(0h16), idx) when _T_71 : node _T_72 = shl(UInt<1>(0h0), 3) node _T_73 = dshr(incoming_writes_Q.io.deq.bits.data, _T_72) connect Queue10_UInt8_22.io.enq.bits, _T_73 node _T_74 = eq(UInt<5>(0h17), idx) when _T_74 : node _T_75 = shl(UInt<1>(0h0), 3) node _T_76 = dshr(incoming_writes_Q.io.deq.bits.data, _T_75) connect Queue10_UInt8_23.io.enq.bits, _T_76 node _T_77 = eq(UInt<5>(0h18), idx) when _T_77 : node _T_78 = shl(UInt<1>(0h0), 3) node _T_79 = dshr(incoming_writes_Q.io.deq.bits.data, _T_78) connect Queue10_UInt8_24.io.enq.bits, _T_79 node _T_80 = eq(UInt<5>(0h19), idx) when _T_80 : node _T_81 = shl(UInt<1>(0h0), 3) node _T_82 = dshr(incoming_writes_Q.io.deq.bits.data, _T_81) connect Queue10_UInt8_25.io.enq.bits, _T_82 node _T_83 = eq(UInt<5>(0h1a), idx) when _T_83 : node _T_84 = shl(UInt<1>(0h0), 3) node _T_85 = dshr(incoming_writes_Q.io.deq.bits.data, _T_84) connect Queue10_UInt8_26.io.enq.bits, _T_85 node _T_86 = eq(UInt<5>(0h1b), idx) when _T_86 : node _T_87 = shl(UInt<1>(0h0), 3) node _T_88 = dshr(incoming_writes_Q.io.deq.bits.data, _T_87) connect Queue10_UInt8_27.io.enq.bits, _T_88 node _T_89 = eq(UInt<5>(0h1c), idx) when _T_89 : node _T_90 = shl(UInt<1>(0h0), 3) node _T_91 = dshr(incoming_writes_Q.io.deq.bits.data, _T_90) connect Queue10_UInt8_28.io.enq.bits, _T_91 node _T_92 = eq(UInt<5>(0h1d), idx) when _T_92 : node _T_93 = shl(UInt<1>(0h0), 3) node _T_94 = dshr(incoming_writes_Q.io.deq.bits.data, _T_93) connect Queue10_UInt8_29.io.enq.bits, _T_94 node _T_95 = eq(UInt<5>(0h1e), idx) when _T_95 : node _T_96 = shl(UInt<1>(0h0), 3) node _T_97 = dshr(incoming_writes_Q.io.deq.bits.data, _T_96) connect Queue10_UInt8_30.io.enq.bits, _T_97 node _T_98 = eq(UInt<5>(0h1f), idx) when _T_98 : node _T_99 = shl(UInt<1>(0h0), 3) node _T_100 = dshr(incoming_writes_Q.io.deq.bits.data, _T_99) connect Queue10_UInt8_31.io.enq.bits, _T_100 node _idx_T_1 = add(write_start_index, UInt<1>(0h1)) node idx_1 = rem(_idx_T_1, UInt<6>(0h20)) node _T_101 = eq(UInt<1>(0h0), idx_1) when _T_101 : node _T_102 = shl(UInt<1>(0h1), 3) node _T_103 = dshr(incoming_writes_Q.io.deq.bits.data, _T_102) connect Queue10_UInt8.io.enq.bits, _T_103 node _T_104 = eq(UInt<1>(0h1), idx_1) when _T_104 : node _T_105 = shl(UInt<1>(0h1), 3) node _T_106 = dshr(incoming_writes_Q.io.deq.bits.data, _T_105) connect Queue10_UInt8_1.io.enq.bits, _T_106 node _T_107 = eq(UInt<2>(0h2), idx_1) when _T_107 : node _T_108 = shl(UInt<1>(0h1), 3) node _T_109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_108) connect Queue10_UInt8_2.io.enq.bits, _T_109 node _T_110 = eq(UInt<2>(0h3), idx_1) when _T_110 : node _T_111 = shl(UInt<1>(0h1), 3) node _T_112 = dshr(incoming_writes_Q.io.deq.bits.data, _T_111) connect Queue10_UInt8_3.io.enq.bits, _T_112 node _T_113 = eq(UInt<3>(0h4), idx_1) when _T_113 : node _T_114 = shl(UInt<1>(0h1), 3) node _T_115 = dshr(incoming_writes_Q.io.deq.bits.data, _T_114) connect Queue10_UInt8_4.io.enq.bits, _T_115 node _T_116 = eq(UInt<3>(0h5), idx_1) when _T_116 : node _T_117 = shl(UInt<1>(0h1), 3) node _T_118 = dshr(incoming_writes_Q.io.deq.bits.data, _T_117) connect Queue10_UInt8_5.io.enq.bits, _T_118 node _T_119 = eq(UInt<3>(0h6), idx_1) when _T_119 : node _T_120 = shl(UInt<1>(0h1), 3) node _T_121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_120) connect Queue10_UInt8_6.io.enq.bits, _T_121 node _T_122 = eq(UInt<3>(0h7), idx_1) when _T_122 : node _T_123 = shl(UInt<1>(0h1), 3) node _T_124 = dshr(incoming_writes_Q.io.deq.bits.data, _T_123) connect Queue10_UInt8_7.io.enq.bits, _T_124 node _T_125 = eq(UInt<4>(0h8), idx_1) when _T_125 : node _T_126 = shl(UInt<1>(0h1), 3) node _T_127 = dshr(incoming_writes_Q.io.deq.bits.data, _T_126) connect Queue10_UInt8_8.io.enq.bits, _T_127 node _T_128 = eq(UInt<4>(0h9), idx_1) when _T_128 : node _T_129 = shl(UInt<1>(0h1), 3) node _T_130 = dshr(incoming_writes_Q.io.deq.bits.data, _T_129) connect Queue10_UInt8_9.io.enq.bits, _T_130 node _T_131 = eq(UInt<4>(0ha), idx_1) when _T_131 : node _T_132 = shl(UInt<1>(0h1), 3) node _T_133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_132) connect Queue10_UInt8_10.io.enq.bits, _T_133 node _T_134 = eq(UInt<4>(0hb), idx_1) when _T_134 : node _T_135 = shl(UInt<1>(0h1), 3) node _T_136 = dshr(incoming_writes_Q.io.deq.bits.data, _T_135) connect Queue10_UInt8_11.io.enq.bits, _T_136 node _T_137 = eq(UInt<4>(0hc), idx_1) when _T_137 : node _T_138 = shl(UInt<1>(0h1), 3) node _T_139 = dshr(incoming_writes_Q.io.deq.bits.data, _T_138) connect Queue10_UInt8_12.io.enq.bits, _T_139 node _T_140 = eq(UInt<4>(0hd), idx_1) when _T_140 : node _T_141 = shl(UInt<1>(0h1), 3) node _T_142 = dshr(incoming_writes_Q.io.deq.bits.data, _T_141) connect Queue10_UInt8_13.io.enq.bits, _T_142 node _T_143 = eq(UInt<4>(0he), idx_1) when _T_143 : node _T_144 = shl(UInt<1>(0h1), 3) node _T_145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_144) connect Queue10_UInt8_14.io.enq.bits, _T_145 node _T_146 = eq(UInt<4>(0hf), idx_1) when _T_146 : node _T_147 = shl(UInt<1>(0h1), 3) node _T_148 = dshr(incoming_writes_Q.io.deq.bits.data, _T_147) connect Queue10_UInt8_15.io.enq.bits, _T_148 node _T_149 = eq(UInt<5>(0h10), idx_1) when _T_149 : node _T_150 = shl(UInt<1>(0h1), 3) node _T_151 = dshr(incoming_writes_Q.io.deq.bits.data, _T_150) connect Queue10_UInt8_16.io.enq.bits, _T_151 node _T_152 = eq(UInt<5>(0h11), idx_1) when _T_152 : node _T_153 = shl(UInt<1>(0h1), 3) node _T_154 = dshr(incoming_writes_Q.io.deq.bits.data, _T_153) connect Queue10_UInt8_17.io.enq.bits, _T_154 node _T_155 = eq(UInt<5>(0h12), idx_1) when _T_155 : node _T_156 = shl(UInt<1>(0h1), 3) node _T_157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_156) connect Queue10_UInt8_18.io.enq.bits, _T_157 node _T_158 = eq(UInt<5>(0h13), idx_1) when _T_158 : node _T_159 = shl(UInt<1>(0h1), 3) node _T_160 = dshr(incoming_writes_Q.io.deq.bits.data, _T_159) connect Queue10_UInt8_19.io.enq.bits, _T_160 node _T_161 = eq(UInt<5>(0h14), idx_1) when _T_161 : node _T_162 = shl(UInt<1>(0h1), 3) node _T_163 = dshr(incoming_writes_Q.io.deq.bits.data, _T_162) connect Queue10_UInt8_20.io.enq.bits, _T_163 node _T_164 = eq(UInt<5>(0h15), idx_1) when _T_164 : node _T_165 = shl(UInt<1>(0h1), 3) node _T_166 = dshr(incoming_writes_Q.io.deq.bits.data, _T_165) connect Queue10_UInt8_21.io.enq.bits, _T_166 node _T_167 = eq(UInt<5>(0h16), idx_1) when _T_167 : node _T_168 = shl(UInt<1>(0h1), 3) node _T_169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_168) connect Queue10_UInt8_22.io.enq.bits, _T_169 node _T_170 = eq(UInt<5>(0h17), idx_1) when _T_170 : node _T_171 = shl(UInt<1>(0h1), 3) node _T_172 = dshr(incoming_writes_Q.io.deq.bits.data, _T_171) connect Queue10_UInt8_23.io.enq.bits, _T_172 node _T_173 = eq(UInt<5>(0h18), idx_1) when _T_173 : node _T_174 = shl(UInt<1>(0h1), 3) node _T_175 = dshr(incoming_writes_Q.io.deq.bits.data, _T_174) connect Queue10_UInt8_24.io.enq.bits, _T_175 node _T_176 = eq(UInt<5>(0h19), idx_1) when _T_176 : node _T_177 = shl(UInt<1>(0h1), 3) node _T_178 = dshr(incoming_writes_Q.io.deq.bits.data, _T_177) connect Queue10_UInt8_25.io.enq.bits, _T_178 node _T_179 = eq(UInt<5>(0h1a), idx_1) when _T_179 : node _T_180 = shl(UInt<1>(0h1), 3) node _T_181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_180) connect Queue10_UInt8_26.io.enq.bits, _T_181 node _T_182 = eq(UInt<5>(0h1b), idx_1) when _T_182 : node _T_183 = shl(UInt<1>(0h1), 3) node _T_184 = dshr(incoming_writes_Q.io.deq.bits.data, _T_183) connect Queue10_UInt8_27.io.enq.bits, _T_184 node _T_185 = eq(UInt<5>(0h1c), idx_1) when _T_185 : node _T_186 = shl(UInt<1>(0h1), 3) node _T_187 = dshr(incoming_writes_Q.io.deq.bits.data, _T_186) connect Queue10_UInt8_28.io.enq.bits, _T_187 node _T_188 = eq(UInt<5>(0h1d), idx_1) when _T_188 : node _T_189 = shl(UInt<1>(0h1), 3) node _T_190 = dshr(incoming_writes_Q.io.deq.bits.data, _T_189) connect Queue10_UInt8_29.io.enq.bits, _T_190 node _T_191 = eq(UInt<5>(0h1e), idx_1) when _T_191 : node _T_192 = shl(UInt<1>(0h1), 3) node _T_193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_192) connect Queue10_UInt8_30.io.enq.bits, _T_193 node _T_194 = eq(UInt<5>(0h1f), idx_1) when _T_194 : node _T_195 = shl(UInt<1>(0h1), 3) node _T_196 = dshr(incoming_writes_Q.io.deq.bits.data, _T_195) connect Queue10_UInt8_31.io.enq.bits, _T_196 node _idx_T_2 = add(write_start_index, UInt<2>(0h2)) node idx_2 = rem(_idx_T_2, UInt<6>(0h20)) node _T_197 = eq(UInt<1>(0h0), idx_2) when _T_197 : node _T_198 = shl(UInt<2>(0h2), 3) node _T_199 = dshr(incoming_writes_Q.io.deq.bits.data, _T_198) connect Queue10_UInt8.io.enq.bits, _T_199 node _T_200 = eq(UInt<1>(0h1), idx_2) when _T_200 : node _T_201 = shl(UInt<2>(0h2), 3) node _T_202 = dshr(incoming_writes_Q.io.deq.bits.data, _T_201) connect Queue10_UInt8_1.io.enq.bits, _T_202 node _T_203 = eq(UInt<2>(0h2), idx_2) when _T_203 : node _T_204 = shl(UInt<2>(0h2), 3) node _T_205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_204) connect Queue10_UInt8_2.io.enq.bits, _T_205 node _T_206 = eq(UInt<2>(0h3), idx_2) when _T_206 : node _T_207 = shl(UInt<2>(0h2), 3) node _T_208 = dshr(incoming_writes_Q.io.deq.bits.data, _T_207) connect Queue10_UInt8_3.io.enq.bits, _T_208 node _T_209 = eq(UInt<3>(0h4), idx_2) when _T_209 : node _T_210 = shl(UInt<2>(0h2), 3) node _T_211 = dshr(incoming_writes_Q.io.deq.bits.data, _T_210) connect Queue10_UInt8_4.io.enq.bits, _T_211 node _T_212 = eq(UInt<3>(0h5), idx_2) when _T_212 : node _T_213 = shl(UInt<2>(0h2), 3) node _T_214 = dshr(incoming_writes_Q.io.deq.bits.data, _T_213) connect Queue10_UInt8_5.io.enq.bits, _T_214 node _T_215 = eq(UInt<3>(0h6), idx_2) when _T_215 : node _T_216 = shl(UInt<2>(0h2), 3) node _T_217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_216) connect Queue10_UInt8_6.io.enq.bits, _T_217 node _T_218 = eq(UInt<3>(0h7), idx_2) when _T_218 : node _T_219 = shl(UInt<2>(0h2), 3) node _T_220 = dshr(incoming_writes_Q.io.deq.bits.data, _T_219) connect Queue10_UInt8_7.io.enq.bits, _T_220 node _T_221 = eq(UInt<4>(0h8), idx_2) when _T_221 : node _T_222 = shl(UInt<2>(0h2), 3) node _T_223 = dshr(incoming_writes_Q.io.deq.bits.data, _T_222) connect Queue10_UInt8_8.io.enq.bits, _T_223 node _T_224 = eq(UInt<4>(0h9), idx_2) when _T_224 : node _T_225 = shl(UInt<2>(0h2), 3) node _T_226 = dshr(incoming_writes_Q.io.deq.bits.data, _T_225) connect Queue10_UInt8_9.io.enq.bits, _T_226 node _T_227 = eq(UInt<4>(0ha), idx_2) when _T_227 : node _T_228 = shl(UInt<2>(0h2), 3) node _T_229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_228) connect Queue10_UInt8_10.io.enq.bits, _T_229 node _T_230 = eq(UInt<4>(0hb), idx_2) when _T_230 : node _T_231 = shl(UInt<2>(0h2), 3) node _T_232 = dshr(incoming_writes_Q.io.deq.bits.data, _T_231) connect Queue10_UInt8_11.io.enq.bits, _T_232 node _T_233 = eq(UInt<4>(0hc), idx_2) when _T_233 : node _T_234 = shl(UInt<2>(0h2), 3) node _T_235 = dshr(incoming_writes_Q.io.deq.bits.data, _T_234) connect Queue10_UInt8_12.io.enq.bits, _T_235 node _T_236 = eq(UInt<4>(0hd), idx_2) when _T_236 : node _T_237 = shl(UInt<2>(0h2), 3) node _T_238 = dshr(incoming_writes_Q.io.deq.bits.data, _T_237) connect Queue10_UInt8_13.io.enq.bits, _T_238 node _T_239 = eq(UInt<4>(0he), idx_2) when _T_239 : node _T_240 = shl(UInt<2>(0h2), 3) node _T_241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_240) connect Queue10_UInt8_14.io.enq.bits, _T_241 node _T_242 = eq(UInt<4>(0hf), idx_2) when _T_242 : node _T_243 = shl(UInt<2>(0h2), 3) node _T_244 = dshr(incoming_writes_Q.io.deq.bits.data, _T_243) connect Queue10_UInt8_15.io.enq.bits, _T_244 node _T_245 = eq(UInt<5>(0h10), idx_2) when _T_245 : node _T_246 = shl(UInt<2>(0h2), 3) node _T_247 = dshr(incoming_writes_Q.io.deq.bits.data, _T_246) connect Queue10_UInt8_16.io.enq.bits, _T_247 node _T_248 = eq(UInt<5>(0h11), idx_2) when _T_248 : node _T_249 = shl(UInt<2>(0h2), 3) node _T_250 = dshr(incoming_writes_Q.io.deq.bits.data, _T_249) connect Queue10_UInt8_17.io.enq.bits, _T_250 node _T_251 = eq(UInt<5>(0h12), idx_2) when _T_251 : node _T_252 = shl(UInt<2>(0h2), 3) node _T_253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_252) connect Queue10_UInt8_18.io.enq.bits, _T_253 node _T_254 = eq(UInt<5>(0h13), idx_2) when _T_254 : node _T_255 = shl(UInt<2>(0h2), 3) node _T_256 = dshr(incoming_writes_Q.io.deq.bits.data, _T_255) connect Queue10_UInt8_19.io.enq.bits, _T_256 node _T_257 = eq(UInt<5>(0h14), idx_2) when _T_257 : node _T_258 = shl(UInt<2>(0h2), 3) node _T_259 = dshr(incoming_writes_Q.io.deq.bits.data, _T_258) connect Queue10_UInt8_20.io.enq.bits, _T_259 node _T_260 = eq(UInt<5>(0h15), idx_2) when _T_260 : node _T_261 = shl(UInt<2>(0h2), 3) node _T_262 = dshr(incoming_writes_Q.io.deq.bits.data, _T_261) connect Queue10_UInt8_21.io.enq.bits, _T_262 node _T_263 = eq(UInt<5>(0h16), idx_2) when _T_263 : node _T_264 = shl(UInt<2>(0h2), 3) node _T_265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_264) connect Queue10_UInt8_22.io.enq.bits, _T_265 node _T_266 = eq(UInt<5>(0h17), idx_2) when _T_266 : node _T_267 = shl(UInt<2>(0h2), 3) node _T_268 = dshr(incoming_writes_Q.io.deq.bits.data, _T_267) connect Queue10_UInt8_23.io.enq.bits, _T_268 node _T_269 = eq(UInt<5>(0h18), idx_2) when _T_269 : node _T_270 = shl(UInt<2>(0h2), 3) node _T_271 = dshr(incoming_writes_Q.io.deq.bits.data, _T_270) connect Queue10_UInt8_24.io.enq.bits, _T_271 node _T_272 = eq(UInt<5>(0h19), idx_2) when _T_272 : node _T_273 = shl(UInt<2>(0h2), 3) node _T_274 = dshr(incoming_writes_Q.io.deq.bits.data, _T_273) connect Queue10_UInt8_25.io.enq.bits, _T_274 node _T_275 = eq(UInt<5>(0h1a), idx_2) when _T_275 : node _T_276 = shl(UInt<2>(0h2), 3) node _T_277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_276) connect Queue10_UInt8_26.io.enq.bits, _T_277 node _T_278 = eq(UInt<5>(0h1b), idx_2) when _T_278 : node _T_279 = shl(UInt<2>(0h2), 3) node _T_280 = dshr(incoming_writes_Q.io.deq.bits.data, _T_279) connect Queue10_UInt8_27.io.enq.bits, _T_280 node _T_281 = eq(UInt<5>(0h1c), idx_2) when _T_281 : node _T_282 = shl(UInt<2>(0h2), 3) node _T_283 = dshr(incoming_writes_Q.io.deq.bits.data, _T_282) connect Queue10_UInt8_28.io.enq.bits, _T_283 node _T_284 = eq(UInt<5>(0h1d), idx_2) when _T_284 : node _T_285 = shl(UInt<2>(0h2), 3) node _T_286 = dshr(incoming_writes_Q.io.deq.bits.data, _T_285) connect Queue10_UInt8_29.io.enq.bits, _T_286 node _T_287 = eq(UInt<5>(0h1e), idx_2) when _T_287 : node _T_288 = shl(UInt<2>(0h2), 3) node _T_289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_288) connect Queue10_UInt8_30.io.enq.bits, _T_289 node _T_290 = eq(UInt<5>(0h1f), idx_2) when _T_290 : node _T_291 = shl(UInt<2>(0h2), 3) node _T_292 = dshr(incoming_writes_Q.io.deq.bits.data, _T_291) connect Queue10_UInt8_31.io.enq.bits, _T_292 node _idx_T_3 = add(write_start_index, UInt<2>(0h3)) node idx_3 = rem(_idx_T_3, UInt<6>(0h20)) node _T_293 = eq(UInt<1>(0h0), idx_3) when _T_293 : node _T_294 = shl(UInt<2>(0h3), 3) node _T_295 = dshr(incoming_writes_Q.io.deq.bits.data, _T_294) connect Queue10_UInt8.io.enq.bits, _T_295 node _T_296 = eq(UInt<1>(0h1), idx_3) when _T_296 : node _T_297 = shl(UInt<2>(0h3), 3) node _T_298 = dshr(incoming_writes_Q.io.deq.bits.data, _T_297) connect Queue10_UInt8_1.io.enq.bits, _T_298 node _T_299 = eq(UInt<2>(0h2), idx_3) when _T_299 : node _T_300 = shl(UInt<2>(0h3), 3) node _T_301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_300) connect Queue10_UInt8_2.io.enq.bits, _T_301 node _T_302 = eq(UInt<2>(0h3), idx_3) when _T_302 : node _T_303 = shl(UInt<2>(0h3), 3) node _T_304 = dshr(incoming_writes_Q.io.deq.bits.data, _T_303) connect Queue10_UInt8_3.io.enq.bits, _T_304 node _T_305 = eq(UInt<3>(0h4), idx_3) when _T_305 : node _T_306 = shl(UInt<2>(0h3), 3) node _T_307 = dshr(incoming_writes_Q.io.deq.bits.data, _T_306) connect Queue10_UInt8_4.io.enq.bits, _T_307 node _T_308 = eq(UInt<3>(0h5), idx_3) when _T_308 : node _T_309 = shl(UInt<2>(0h3), 3) node _T_310 = dshr(incoming_writes_Q.io.deq.bits.data, _T_309) connect Queue10_UInt8_5.io.enq.bits, _T_310 node _T_311 = eq(UInt<3>(0h6), idx_3) when _T_311 : node _T_312 = shl(UInt<2>(0h3), 3) node _T_313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_312) connect Queue10_UInt8_6.io.enq.bits, _T_313 node _T_314 = eq(UInt<3>(0h7), idx_3) when _T_314 : node _T_315 = shl(UInt<2>(0h3), 3) node _T_316 = dshr(incoming_writes_Q.io.deq.bits.data, _T_315) connect Queue10_UInt8_7.io.enq.bits, _T_316 node _T_317 = eq(UInt<4>(0h8), idx_3) when _T_317 : node _T_318 = shl(UInt<2>(0h3), 3) node _T_319 = dshr(incoming_writes_Q.io.deq.bits.data, _T_318) connect Queue10_UInt8_8.io.enq.bits, _T_319 node _T_320 = eq(UInt<4>(0h9), idx_3) when _T_320 : node _T_321 = shl(UInt<2>(0h3), 3) node _T_322 = dshr(incoming_writes_Q.io.deq.bits.data, _T_321) connect Queue10_UInt8_9.io.enq.bits, _T_322 node _T_323 = eq(UInt<4>(0ha), idx_3) when _T_323 : node _T_324 = shl(UInt<2>(0h3), 3) node _T_325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_324) connect Queue10_UInt8_10.io.enq.bits, _T_325 node _T_326 = eq(UInt<4>(0hb), idx_3) when _T_326 : node _T_327 = shl(UInt<2>(0h3), 3) node _T_328 = dshr(incoming_writes_Q.io.deq.bits.data, _T_327) connect Queue10_UInt8_11.io.enq.bits, _T_328 node _T_329 = eq(UInt<4>(0hc), idx_3) when _T_329 : node _T_330 = shl(UInt<2>(0h3), 3) node _T_331 = dshr(incoming_writes_Q.io.deq.bits.data, _T_330) connect Queue10_UInt8_12.io.enq.bits, _T_331 node _T_332 = eq(UInt<4>(0hd), idx_3) when _T_332 : node _T_333 = shl(UInt<2>(0h3), 3) node _T_334 = dshr(incoming_writes_Q.io.deq.bits.data, _T_333) connect Queue10_UInt8_13.io.enq.bits, _T_334 node _T_335 = eq(UInt<4>(0he), idx_3) when _T_335 : node _T_336 = shl(UInt<2>(0h3), 3) node _T_337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_336) connect Queue10_UInt8_14.io.enq.bits, _T_337 node _T_338 = eq(UInt<4>(0hf), idx_3) when _T_338 : node _T_339 = shl(UInt<2>(0h3), 3) node _T_340 = dshr(incoming_writes_Q.io.deq.bits.data, _T_339) connect Queue10_UInt8_15.io.enq.bits, _T_340 node _T_341 = eq(UInt<5>(0h10), idx_3) when _T_341 : node _T_342 = shl(UInt<2>(0h3), 3) node _T_343 = dshr(incoming_writes_Q.io.deq.bits.data, _T_342) connect Queue10_UInt8_16.io.enq.bits, _T_343 node _T_344 = eq(UInt<5>(0h11), idx_3) when _T_344 : node _T_345 = shl(UInt<2>(0h3), 3) node _T_346 = dshr(incoming_writes_Q.io.deq.bits.data, _T_345) connect Queue10_UInt8_17.io.enq.bits, _T_346 node _T_347 = eq(UInt<5>(0h12), idx_3) when _T_347 : node _T_348 = shl(UInt<2>(0h3), 3) node _T_349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_348) connect Queue10_UInt8_18.io.enq.bits, _T_349 node _T_350 = eq(UInt<5>(0h13), idx_3) when _T_350 : node _T_351 = shl(UInt<2>(0h3), 3) node _T_352 = dshr(incoming_writes_Q.io.deq.bits.data, _T_351) connect Queue10_UInt8_19.io.enq.bits, _T_352 node _T_353 = eq(UInt<5>(0h14), idx_3) when _T_353 : node _T_354 = shl(UInt<2>(0h3), 3) node _T_355 = dshr(incoming_writes_Q.io.deq.bits.data, _T_354) connect Queue10_UInt8_20.io.enq.bits, _T_355 node _T_356 = eq(UInt<5>(0h15), idx_3) when _T_356 : node _T_357 = shl(UInt<2>(0h3), 3) node _T_358 = dshr(incoming_writes_Q.io.deq.bits.data, _T_357) connect Queue10_UInt8_21.io.enq.bits, _T_358 node _T_359 = eq(UInt<5>(0h16), idx_3) when _T_359 : node _T_360 = shl(UInt<2>(0h3), 3) node _T_361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_360) connect Queue10_UInt8_22.io.enq.bits, _T_361 node _T_362 = eq(UInt<5>(0h17), idx_3) when _T_362 : node _T_363 = shl(UInt<2>(0h3), 3) node _T_364 = dshr(incoming_writes_Q.io.deq.bits.data, _T_363) connect Queue10_UInt8_23.io.enq.bits, _T_364 node _T_365 = eq(UInt<5>(0h18), idx_3) when _T_365 : node _T_366 = shl(UInt<2>(0h3), 3) node _T_367 = dshr(incoming_writes_Q.io.deq.bits.data, _T_366) connect Queue10_UInt8_24.io.enq.bits, _T_367 node _T_368 = eq(UInt<5>(0h19), idx_3) when _T_368 : node _T_369 = shl(UInt<2>(0h3), 3) node _T_370 = dshr(incoming_writes_Q.io.deq.bits.data, _T_369) connect Queue10_UInt8_25.io.enq.bits, _T_370 node _T_371 = eq(UInt<5>(0h1a), idx_3) when _T_371 : node _T_372 = shl(UInt<2>(0h3), 3) node _T_373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_372) connect Queue10_UInt8_26.io.enq.bits, _T_373 node _T_374 = eq(UInt<5>(0h1b), idx_3) when _T_374 : node _T_375 = shl(UInt<2>(0h3), 3) node _T_376 = dshr(incoming_writes_Q.io.deq.bits.data, _T_375) connect Queue10_UInt8_27.io.enq.bits, _T_376 node _T_377 = eq(UInt<5>(0h1c), idx_3) when _T_377 : node _T_378 = shl(UInt<2>(0h3), 3) node _T_379 = dshr(incoming_writes_Q.io.deq.bits.data, _T_378) connect Queue10_UInt8_28.io.enq.bits, _T_379 node _T_380 = eq(UInt<5>(0h1d), idx_3) when _T_380 : node _T_381 = shl(UInt<2>(0h3), 3) node _T_382 = dshr(incoming_writes_Q.io.deq.bits.data, _T_381) connect Queue10_UInt8_29.io.enq.bits, _T_382 node _T_383 = eq(UInt<5>(0h1e), idx_3) when _T_383 : node _T_384 = shl(UInt<2>(0h3), 3) node _T_385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_384) connect Queue10_UInt8_30.io.enq.bits, _T_385 node _T_386 = eq(UInt<5>(0h1f), idx_3) when _T_386 : node _T_387 = shl(UInt<2>(0h3), 3) node _T_388 = dshr(incoming_writes_Q.io.deq.bits.data, _T_387) connect Queue10_UInt8_31.io.enq.bits, _T_388 node _idx_T_4 = add(write_start_index, UInt<3>(0h4)) node idx_4 = rem(_idx_T_4, UInt<6>(0h20)) node _T_389 = eq(UInt<1>(0h0), idx_4) when _T_389 : node _T_390 = shl(UInt<3>(0h4), 3) node _T_391 = dshr(incoming_writes_Q.io.deq.bits.data, _T_390) connect Queue10_UInt8.io.enq.bits, _T_391 node _T_392 = eq(UInt<1>(0h1), idx_4) when _T_392 : node _T_393 = shl(UInt<3>(0h4), 3) node _T_394 = dshr(incoming_writes_Q.io.deq.bits.data, _T_393) connect Queue10_UInt8_1.io.enq.bits, _T_394 node _T_395 = eq(UInt<2>(0h2), idx_4) when _T_395 : node _T_396 = shl(UInt<3>(0h4), 3) node _T_397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_396) connect Queue10_UInt8_2.io.enq.bits, _T_397 node _T_398 = eq(UInt<2>(0h3), idx_4) when _T_398 : node _T_399 = shl(UInt<3>(0h4), 3) node _T_400 = dshr(incoming_writes_Q.io.deq.bits.data, _T_399) connect Queue10_UInt8_3.io.enq.bits, _T_400 node _T_401 = eq(UInt<3>(0h4), idx_4) when _T_401 : node _T_402 = shl(UInt<3>(0h4), 3) node _T_403 = dshr(incoming_writes_Q.io.deq.bits.data, _T_402) connect Queue10_UInt8_4.io.enq.bits, _T_403 node _T_404 = eq(UInt<3>(0h5), idx_4) when _T_404 : node _T_405 = shl(UInt<3>(0h4), 3) node _T_406 = dshr(incoming_writes_Q.io.deq.bits.data, _T_405) connect Queue10_UInt8_5.io.enq.bits, _T_406 node _T_407 = eq(UInt<3>(0h6), idx_4) when _T_407 : node _T_408 = shl(UInt<3>(0h4), 3) node _T_409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_408) connect Queue10_UInt8_6.io.enq.bits, _T_409 node _T_410 = eq(UInt<3>(0h7), idx_4) when _T_410 : node _T_411 = shl(UInt<3>(0h4), 3) node _T_412 = dshr(incoming_writes_Q.io.deq.bits.data, _T_411) connect Queue10_UInt8_7.io.enq.bits, _T_412 node _T_413 = eq(UInt<4>(0h8), idx_4) when _T_413 : node _T_414 = shl(UInt<3>(0h4), 3) node _T_415 = dshr(incoming_writes_Q.io.deq.bits.data, _T_414) connect Queue10_UInt8_8.io.enq.bits, _T_415 node _T_416 = eq(UInt<4>(0h9), idx_4) when _T_416 : node _T_417 = shl(UInt<3>(0h4), 3) node _T_418 = dshr(incoming_writes_Q.io.deq.bits.data, _T_417) connect Queue10_UInt8_9.io.enq.bits, _T_418 node _T_419 = eq(UInt<4>(0ha), idx_4) when _T_419 : node _T_420 = shl(UInt<3>(0h4), 3) node _T_421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_420) connect Queue10_UInt8_10.io.enq.bits, _T_421 node _T_422 = eq(UInt<4>(0hb), idx_4) when _T_422 : node _T_423 = shl(UInt<3>(0h4), 3) node _T_424 = dshr(incoming_writes_Q.io.deq.bits.data, _T_423) connect Queue10_UInt8_11.io.enq.bits, _T_424 node _T_425 = eq(UInt<4>(0hc), idx_4) when _T_425 : node _T_426 = shl(UInt<3>(0h4), 3) node _T_427 = dshr(incoming_writes_Q.io.deq.bits.data, _T_426) connect Queue10_UInt8_12.io.enq.bits, _T_427 node _T_428 = eq(UInt<4>(0hd), idx_4) when _T_428 : node _T_429 = shl(UInt<3>(0h4), 3) node _T_430 = dshr(incoming_writes_Q.io.deq.bits.data, _T_429) connect Queue10_UInt8_13.io.enq.bits, _T_430 node _T_431 = eq(UInt<4>(0he), idx_4) when _T_431 : node _T_432 = shl(UInt<3>(0h4), 3) node _T_433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_432) connect Queue10_UInt8_14.io.enq.bits, _T_433 node _T_434 = eq(UInt<4>(0hf), idx_4) when _T_434 : node _T_435 = shl(UInt<3>(0h4), 3) node _T_436 = dshr(incoming_writes_Q.io.deq.bits.data, _T_435) connect Queue10_UInt8_15.io.enq.bits, _T_436 node _T_437 = eq(UInt<5>(0h10), idx_4) when _T_437 : node _T_438 = shl(UInt<3>(0h4), 3) node _T_439 = dshr(incoming_writes_Q.io.deq.bits.data, _T_438) connect Queue10_UInt8_16.io.enq.bits, _T_439 node _T_440 = eq(UInt<5>(0h11), idx_4) when _T_440 : node _T_441 = shl(UInt<3>(0h4), 3) node _T_442 = dshr(incoming_writes_Q.io.deq.bits.data, _T_441) connect Queue10_UInt8_17.io.enq.bits, _T_442 node _T_443 = eq(UInt<5>(0h12), idx_4) when _T_443 : node _T_444 = shl(UInt<3>(0h4), 3) node _T_445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_444) connect Queue10_UInt8_18.io.enq.bits, _T_445 node _T_446 = eq(UInt<5>(0h13), idx_4) when _T_446 : node _T_447 = shl(UInt<3>(0h4), 3) node _T_448 = dshr(incoming_writes_Q.io.deq.bits.data, _T_447) connect Queue10_UInt8_19.io.enq.bits, _T_448 node _T_449 = eq(UInt<5>(0h14), idx_4) when _T_449 : node _T_450 = shl(UInt<3>(0h4), 3) node _T_451 = dshr(incoming_writes_Q.io.deq.bits.data, _T_450) connect Queue10_UInt8_20.io.enq.bits, _T_451 node _T_452 = eq(UInt<5>(0h15), idx_4) when _T_452 : node _T_453 = shl(UInt<3>(0h4), 3) node _T_454 = dshr(incoming_writes_Q.io.deq.bits.data, _T_453) connect Queue10_UInt8_21.io.enq.bits, _T_454 node _T_455 = eq(UInt<5>(0h16), idx_4) when _T_455 : node _T_456 = shl(UInt<3>(0h4), 3) node _T_457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_456) connect Queue10_UInt8_22.io.enq.bits, _T_457 node _T_458 = eq(UInt<5>(0h17), idx_4) when _T_458 : node _T_459 = shl(UInt<3>(0h4), 3) node _T_460 = dshr(incoming_writes_Q.io.deq.bits.data, _T_459) connect Queue10_UInt8_23.io.enq.bits, _T_460 node _T_461 = eq(UInt<5>(0h18), idx_4) when _T_461 : node _T_462 = shl(UInt<3>(0h4), 3) node _T_463 = dshr(incoming_writes_Q.io.deq.bits.data, _T_462) connect Queue10_UInt8_24.io.enq.bits, _T_463 node _T_464 = eq(UInt<5>(0h19), idx_4) when _T_464 : node _T_465 = shl(UInt<3>(0h4), 3) node _T_466 = dshr(incoming_writes_Q.io.deq.bits.data, _T_465) connect Queue10_UInt8_25.io.enq.bits, _T_466 node _T_467 = eq(UInt<5>(0h1a), idx_4) when _T_467 : node _T_468 = shl(UInt<3>(0h4), 3) node _T_469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_468) connect Queue10_UInt8_26.io.enq.bits, _T_469 node _T_470 = eq(UInt<5>(0h1b), idx_4) when _T_470 : node _T_471 = shl(UInt<3>(0h4), 3) node _T_472 = dshr(incoming_writes_Q.io.deq.bits.data, _T_471) connect Queue10_UInt8_27.io.enq.bits, _T_472 node _T_473 = eq(UInt<5>(0h1c), idx_4) when _T_473 : node _T_474 = shl(UInt<3>(0h4), 3) node _T_475 = dshr(incoming_writes_Q.io.deq.bits.data, _T_474) connect Queue10_UInt8_28.io.enq.bits, _T_475 node _T_476 = eq(UInt<5>(0h1d), idx_4) when _T_476 : node _T_477 = shl(UInt<3>(0h4), 3) node _T_478 = dshr(incoming_writes_Q.io.deq.bits.data, _T_477) connect Queue10_UInt8_29.io.enq.bits, _T_478 node _T_479 = eq(UInt<5>(0h1e), idx_4) when _T_479 : node _T_480 = shl(UInt<3>(0h4), 3) node _T_481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_480) connect Queue10_UInt8_30.io.enq.bits, _T_481 node _T_482 = eq(UInt<5>(0h1f), idx_4) when _T_482 : node _T_483 = shl(UInt<3>(0h4), 3) node _T_484 = dshr(incoming_writes_Q.io.deq.bits.data, _T_483) connect Queue10_UInt8_31.io.enq.bits, _T_484 node _idx_T_5 = add(write_start_index, UInt<3>(0h5)) node idx_5 = rem(_idx_T_5, UInt<6>(0h20)) node _T_485 = eq(UInt<1>(0h0), idx_5) when _T_485 : node _T_486 = shl(UInt<3>(0h5), 3) node _T_487 = dshr(incoming_writes_Q.io.deq.bits.data, _T_486) connect Queue10_UInt8.io.enq.bits, _T_487 node _T_488 = eq(UInt<1>(0h1), idx_5) when _T_488 : node _T_489 = shl(UInt<3>(0h5), 3) node _T_490 = dshr(incoming_writes_Q.io.deq.bits.data, _T_489) connect Queue10_UInt8_1.io.enq.bits, _T_490 node _T_491 = eq(UInt<2>(0h2), idx_5) when _T_491 : node _T_492 = shl(UInt<3>(0h5), 3) node _T_493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_492) connect Queue10_UInt8_2.io.enq.bits, _T_493 node _T_494 = eq(UInt<2>(0h3), idx_5) when _T_494 : node _T_495 = shl(UInt<3>(0h5), 3) node _T_496 = dshr(incoming_writes_Q.io.deq.bits.data, _T_495) connect Queue10_UInt8_3.io.enq.bits, _T_496 node _T_497 = eq(UInt<3>(0h4), idx_5) when _T_497 : node _T_498 = shl(UInt<3>(0h5), 3) node _T_499 = dshr(incoming_writes_Q.io.deq.bits.data, _T_498) connect Queue10_UInt8_4.io.enq.bits, _T_499 node _T_500 = eq(UInt<3>(0h5), idx_5) when _T_500 : node _T_501 = shl(UInt<3>(0h5), 3) node _T_502 = dshr(incoming_writes_Q.io.deq.bits.data, _T_501) connect Queue10_UInt8_5.io.enq.bits, _T_502 node _T_503 = eq(UInt<3>(0h6), idx_5) when _T_503 : node _T_504 = shl(UInt<3>(0h5), 3) node _T_505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_504) connect Queue10_UInt8_6.io.enq.bits, _T_505 node _T_506 = eq(UInt<3>(0h7), idx_5) when _T_506 : node _T_507 = shl(UInt<3>(0h5), 3) node _T_508 = dshr(incoming_writes_Q.io.deq.bits.data, _T_507) connect Queue10_UInt8_7.io.enq.bits, _T_508 node _T_509 = eq(UInt<4>(0h8), idx_5) when _T_509 : node _T_510 = shl(UInt<3>(0h5), 3) node _T_511 = dshr(incoming_writes_Q.io.deq.bits.data, _T_510) connect Queue10_UInt8_8.io.enq.bits, _T_511 node _T_512 = eq(UInt<4>(0h9), idx_5) when _T_512 : node _T_513 = shl(UInt<3>(0h5), 3) node _T_514 = dshr(incoming_writes_Q.io.deq.bits.data, _T_513) connect Queue10_UInt8_9.io.enq.bits, _T_514 node _T_515 = eq(UInt<4>(0ha), idx_5) when _T_515 : node _T_516 = shl(UInt<3>(0h5), 3) node _T_517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_516) connect Queue10_UInt8_10.io.enq.bits, _T_517 node _T_518 = eq(UInt<4>(0hb), idx_5) when _T_518 : node _T_519 = shl(UInt<3>(0h5), 3) node _T_520 = dshr(incoming_writes_Q.io.deq.bits.data, _T_519) connect Queue10_UInt8_11.io.enq.bits, _T_520 node _T_521 = eq(UInt<4>(0hc), idx_5) when _T_521 : node _T_522 = shl(UInt<3>(0h5), 3) node _T_523 = dshr(incoming_writes_Q.io.deq.bits.data, _T_522) connect Queue10_UInt8_12.io.enq.bits, _T_523 node _T_524 = eq(UInt<4>(0hd), idx_5) when _T_524 : node _T_525 = shl(UInt<3>(0h5), 3) node _T_526 = dshr(incoming_writes_Q.io.deq.bits.data, _T_525) connect Queue10_UInt8_13.io.enq.bits, _T_526 node _T_527 = eq(UInt<4>(0he), idx_5) when _T_527 : node _T_528 = shl(UInt<3>(0h5), 3) node _T_529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_528) connect Queue10_UInt8_14.io.enq.bits, _T_529 node _T_530 = eq(UInt<4>(0hf), idx_5) when _T_530 : node _T_531 = shl(UInt<3>(0h5), 3) node _T_532 = dshr(incoming_writes_Q.io.deq.bits.data, _T_531) connect Queue10_UInt8_15.io.enq.bits, _T_532 node _T_533 = eq(UInt<5>(0h10), idx_5) when _T_533 : node _T_534 = shl(UInt<3>(0h5), 3) node _T_535 = dshr(incoming_writes_Q.io.deq.bits.data, _T_534) connect Queue10_UInt8_16.io.enq.bits, _T_535 node _T_536 = eq(UInt<5>(0h11), idx_5) when _T_536 : node _T_537 = shl(UInt<3>(0h5), 3) node _T_538 = dshr(incoming_writes_Q.io.deq.bits.data, _T_537) connect Queue10_UInt8_17.io.enq.bits, _T_538 node _T_539 = eq(UInt<5>(0h12), idx_5) when _T_539 : node _T_540 = shl(UInt<3>(0h5), 3) node _T_541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_540) connect Queue10_UInt8_18.io.enq.bits, _T_541 node _T_542 = eq(UInt<5>(0h13), idx_5) when _T_542 : node _T_543 = shl(UInt<3>(0h5), 3) node _T_544 = dshr(incoming_writes_Q.io.deq.bits.data, _T_543) connect Queue10_UInt8_19.io.enq.bits, _T_544 node _T_545 = eq(UInt<5>(0h14), idx_5) when _T_545 : node _T_546 = shl(UInt<3>(0h5), 3) node _T_547 = dshr(incoming_writes_Q.io.deq.bits.data, _T_546) connect Queue10_UInt8_20.io.enq.bits, _T_547 node _T_548 = eq(UInt<5>(0h15), idx_5) when _T_548 : node _T_549 = shl(UInt<3>(0h5), 3) node _T_550 = dshr(incoming_writes_Q.io.deq.bits.data, _T_549) connect Queue10_UInt8_21.io.enq.bits, _T_550 node _T_551 = eq(UInt<5>(0h16), idx_5) when _T_551 : node _T_552 = shl(UInt<3>(0h5), 3) node _T_553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_552) connect Queue10_UInt8_22.io.enq.bits, _T_553 node _T_554 = eq(UInt<5>(0h17), idx_5) when _T_554 : node _T_555 = shl(UInt<3>(0h5), 3) node _T_556 = dshr(incoming_writes_Q.io.deq.bits.data, _T_555) connect Queue10_UInt8_23.io.enq.bits, _T_556 node _T_557 = eq(UInt<5>(0h18), idx_5) when _T_557 : node _T_558 = shl(UInt<3>(0h5), 3) node _T_559 = dshr(incoming_writes_Q.io.deq.bits.data, _T_558) connect Queue10_UInt8_24.io.enq.bits, _T_559 node _T_560 = eq(UInt<5>(0h19), idx_5) when _T_560 : node _T_561 = shl(UInt<3>(0h5), 3) node _T_562 = dshr(incoming_writes_Q.io.deq.bits.data, _T_561) connect Queue10_UInt8_25.io.enq.bits, _T_562 node _T_563 = eq(UInt<5>(0h1a), idx_5) when _T_563 : node _T_564 = shl(UInt<3>(0h5), 3) node _T_565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_564) connect Queue10_UInt8_26.io.enq.bits, _T_565 node _T_566 = eq(UInt<5>(0h1b), idx_5) when _T_566 : node _T_567 = shl(UInt<3>(0h5), 3) node _T_568 = dshr(incoming_writes_Q.io.deq.bits.data, _T_567) connect Queue10_UInt8_27.io.enq.bits, _T_568 node _T_569 = eq(UInt<5>(0h1c), idx_5) when _T_569 : node _T_570 = shl(UInt<3>(0h5), 3) node _T_571 = dshr(incoming_writes_Q.io.deq.bits.data, _T_570) connect Queue10_UInt8_28.io.enq.bits, _T_571 node _T_572 = eq(UInt<5>(0h1d), idx_5) when _T_572 : node _T_573 = shl(UInt<3>(0h5), 3) node _T_574 = dshr(incoming_writes_Q.io.deq.bits.data, _T_573) connect Queue10_UInt8_29.io.enq.bits, _T_574 node _T_575 = eq(UInt<5>(0h1e), idx_5) when _T_575 : node _T_576 = shl(UInt<3>(0h5), 3) node _T_577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_576) connect Queue10_UInt8_30.io.enq.bits, _T_577 node _T_578 = eq(UInt<5>(0h1f), idx_5) when _T_578 : node _T_579 = shl(UInt<3>(0h5), 3) node _T_580 = dshr(incoming_writes_Q.io.deq.bits.data, _T_579) connect Queue10_UInt8_31.io.enq.bits, _T_580 node _idx_T_6 = add(write_start_index, UInt<3>(0h6)) node idx_6 = rem(_idx_T_6, UInt<6>(0h20)) node _T_581 = eq(UInt<1>(0h0), idx_6) when _T_581 : node _T_582 = shl(UInt<3>(0h6), 3) node _T_583 = dshr(incoming_writes_Q.io.deq.bits.data, _T_582) connect Queue10_UInt8.io.enq.bits, _T_583 node _T_584 = eq(UInt<1>(0h1), idx_6) when _T_584 : node _T_585 = shl(UInt<3>(0h6), 3) node _T_586 = dshr(incoming_writes_Q.io.deq.bits.data, _T_585) connect Queue10_UInt8_1.io.enq.bits, _T_586 node _T_587 = eq(UInt<2>(0h2), idx_6) when _T_587 : node _T_588 = shl(UInt<3>(0h6), 3) node _T_589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_588) connect Queue10_UInt8_2.io.enq.bits, _T_589 node _T_590 = eq(UInt<2>(0h3), idx_6) when _T_590 : node _T_591 = shl(UInt<3>(0h6), 3) node _T_592 = dshr(incoming_writes_Q.io.deq.bits.data, _T_591) connect Queue10_UInt8_3.io.enq.bits, _T_592 node _T_593 = eq(UInt<3>(0h4), idx_6) when _T_593 : node _T_594 = shl(UInt<3>(0h6), 3) node _T_595 = dshr(incoming_writes_Q.io.deq.bits.data, _T_594) connect Queue10_UInt8_4.io.enq.bits, _T_595 node _T_596 = eq(UInt<3>(0h5), idx_6) when _T_596 : node _T_597 = shl(UInt<3>(0h6), 3) node _T_598 = dshr(incoming_writes_Q.io.deq.bits.data, _T_597) connect Queue10_UInt8_5.io.enq.bits, _T_598 node _T_599 = eq(UInt<3>(0h6), idx_6) when _T_599 : node _T_600 = shl(UInt<3>(0h6), 3) node _T_601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_600) connect Queue10_UInt8_6.io.enq.bits, _T_601 node _T_602 = eq(UInt<3>(0h7), idx_6) when _T_602 : node _T_603 = shl(UInt<3>(0h6), 3) node _T_604 = dshr(incoming_writes_Q.io.deq.bits.data, _T_603) connect Queue10_UInt8_7.io.enq.bits, _T_604 node _T_605 = eq(UInt<4>(0h8), idx_6) when _T_605 : node _T_606 = shl(UInt<3>(0h6), 3) node _T_607 = dshr(incoming_writes_Q.io.deq.bits.data, _T_606) connect Queue10_UInt8_8.io.enq.bits, _T_607 node _T_608 = eq(UInt<4>(0h9), idx_6) when _T_608 : node _T_609 = shl(UInt<3>(0h6), 3) node _T_610 = dshr(incoming_writes_Q.io.deq.bits.data, _T_609) connect Queue10_UInt8_9.io.enq.bits, _T_610 node _T_611 = eq(UInt<4>(0ha), idx_6) when _T_611 : node _T_612 = shl(UInt<3>(0h6), 3) node _T_613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_612) connect Queue10_UInt8_10.io.enq.bits, _T_613 node _T_614 = eq(UInt<4>(0hb), idx_6) when _T_614 : node _T_615 = shl(UInt<3>(0h6), 3) node _T_616 = dshr(incoming_writes_Q.io.deq.bits.data, _T_615) connect Queue10_UInt8_11.io.enq.bits, _T_616 node _T_617 = eq(UInt<4>(0hc), idx_6) when _T_617 : node _T_618 = shl(UInt<3>(0h6), 3) node _T_619 = dshr(incoming_writes_Q.io.deq.bits.data, _T_618) connect Queue10_UInt8_12.io.enq.bits, _T_619 node _T_620 = eq(UInt<4>(0hd), idx_6) when _T_620 : node _T_621 = shl(UInt<3>(0h6), 3) node _T_622 = dshr(incoming_writes_Q.io.deq.bits.data, _T_621) connect Queue10_UInt8_13.io.enq.bits, _T_622 node _T_623 = eq(UInt<4>(0he), idx_6) when _T_623 : node _T_624 = shl(UInt<3>(0h6), 3) node _T_625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_624) connect Queue10_UInt8_14.io.enq.bits, _T_625 node _T_626 = eq(UInt<4>(0hf), idx_6) when _T_626 : node _T_627 = shl(UInt<3>(0h6), 3) node _T_628 = dshr(incoming_writes_Q.io.deq.bits.data, _T_627) connect Queue10_UInt8_15.io.enq.bits, _T_628 node _T_629 = eq(UInt<5>(0h10), idx_6) when _T_629 : node _T_630 = shl(UInt<3>(0h6), 3) node _T_631 = dshr(incoming_writes_Q.io.deq.bits.data, _T_630) connect Queue10_UInt8_16.io.enq.bits, _T_631 node _T_632 = eq(UInt<5>(0h11), idx_6) when _T_632 : node _T_633 = shl(UInt<3>(0h6), 3) node _T_634 = dshr(incoming_writes_Q.io.deq.bits.data, _T_633) connect Queue10_UInt8_17.io.enq.bits, _T_634 node _T_635 = eq(UInt<5>(0h12), idx_6) when _T_635 : node _T_636 = shl(UInt<3>(0h6), 3) node _T_637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_636) connect Queue10_UInt8_18.io.enq.bits, _T_637 node _T_638 = eq(UInt<5>(0h13), idx_6) when _T_638 : node _T_639 = shl(UInt<3>(0h6), 3) node _T_640 = dshr(incoming_writes_Q.io.deq.bits.data, _T_639) connect Queue10_UInt8_19.io.enq.bits, _T_640 node _T_641 = eq(UInt<5>(0h14), idx_6) when _T_641 : node _T_642 = shl(UInt<3>(0h6), 3) node _T_643 = dshr(incoming_writes_Q.io.deq.bits.data, _T_642) connect Queue10_UInt8_20.io.enq.bits, _T_643 node _T_644 = eq(UInt<5>(0h15), idx_6) when _T_644 : node _T_645 = shl(UInt<3>(0h6), 3) node _T_646 = dshr(incoming_writes_Q.io.deq.bits.data, _T_645) connect Queue10_UInt8_21.io.enq.bits, _T_646 node _T_647 = eq(UInt<5>(0h16), idx_6) when _T_647 : node _T_648 = shl(UInt<3>(0h6), 3) node _T_649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_648) connect Queue10_UInt8_22.io.enq.bits, _T_649 node _T_650 = eq(UInt<5>(0h17), idx_6) when _T_650 : node _T_651 = shl(UInt<3>(0h6), 3) node _T_652 = dshr(incoming_writes_Q.io.deq.bits.data, _T_651) connect Queue10_UInt8_23.io.enq.bits, _T_652 node _T_653 = eq(UInt<5>(0h18), idx_6) when _T_653 : node _T_654 = shl(UInt<3>(0h6), 3) node _T_655 = dshr(incoming_writes_Q.io.deq.bits.data, _T_654) connect Queue10_UInt8_24.io.enq.bits, _T_655 node _T_656 = eq(UInt<5>(0h19), idx_6) when _T_656 : node _T_657 = shl(UInt<3>(0h6), 3) node _T_658 = dshr(incoming_writes_Q.io.deq.bits.data, _T_657) connect Queue10_UInt8_25.io.enq.bits, _T_658 node _T_659 = eq(UInt<5>(0h1a), idx_6) when _T_659 : node _T_660 = shl(UInt<3>(0h6), 3) node _T_661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_660) connect Queue10_UInt8_26.io.enq.bits, _T_661 node _T_662 = eq(UInt<5>(0h1b), idx_6) when _T_662 : node _T_663 = shl(UInt<3>(0h6), 3) node _T_664 = dshr(incoming_writes_Q.io.deq.bits.data, _T_663) connect Queue10_UInt8_27.io.enq.bits, _T_664 node _T_665 = eq(UInt<5>(0h1c), idx_6) when _T_665 : node _T_666 = shl(UInt<3>(0h6), 3) node _T_667 = dshr(incoming_writes_Q.io.deq.bits.data, _T_666) connect Queue10_UInt8_28.io.enq.bits, _T_667 node _T_668 = eq(UInt<5>(0h1d), idx_6) when _T_668 : node _T_669 = shl(UInt<3>(0h6), 3) node _T_670 = dshr(incoming_writes_Q.io.deq.bits.data, _T_669) connect Queue10_UInt8_29.io.enq.bits, _T_670 node _T_671 = eq(UInt<5>(0h1e), idx_6) when _T_671 : node _T_672 = shl(UInt<3>(0h6), 3) node _T_673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_672) connect Queue10_UInt8_30.io.enq.bits, _T_673 node _T_674 = eq(UInt<5>(0h1f), idx_6) when _T_674 : node _T_675 = shl(UInt<3>(0h6), 3) node _T_676 = dshr(incoming_writes_Q.io.deq.bits.data, _T_675) connect Queue10_UInt8_31.io.enq.bits, _T_676 node _idx_T_7 = add(write_start_index, UInt<3>(0h7)) node idx_7 = rem(_idx_T_7, UInt<6>(0h20)) node _T_677 = eq(UInt<1>(0h0), idx_7) when _T_677 : node _T_678 = shl(UInt<3>(0h7), 3) node _T_679 = dshr(incoming_writes_Q.io.deq.bits.data, _T_678) connect Queue10_UInt8.io.enq.bits, _T_679 node _T_680 = eq(UInt<1>(0h1), idx_7) when _T_680 : node _T_681 = shl(UInt<3>(0h7), 3) node _T_682 = dshr(incoming_writes_Q.io.deq.bits.data, _T_681) connect Queue10_UInt8_1.io.enq.bits, _T_682 node _T_683 = eq(UInt<2>(0h2), idx_7) when _T_683 : node _T_684 = shl(UInt<3>(0h7), 3) node _T_685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_684) connect Queue10_UInt8_2.io.enq.bits, _T_685 node _T_686 = eq(UInt<2>(0h3), idx_7) when _T_686 : node _T_687 = shl(UInt<3>(0h7), 3) node _T_688 = dshr(incoming_writes_Q.io.deq.bits.data, _T_687) connect Queue10_UInt8_3.io.enq.bits, _T_688 node _T_689 = eq(UInt<3>(0h4), idx_7) when _T_689 : node _T_690 = shl(UInt<3>(0h7), 3) node _T_691 = dshr(incoming_writes_Q.io.deq.bits.data, _T_690) connect Queue10_UInt8_4.io.enq.bits, _T_691 node _T_692 = eq(UInt<3>(0h5), idx_7) when _T_692 : node _T_693 = shl(UInt<3>(0h7), 3) node _T_694 = dshr(incoming_writes_Q.io.deq.bits.data, _T_693) connect Queue10_UInt8_5.io.enq.bits, _T_694 node _T_695 = eq(UInt<3>(0h6), idx_7) when _T_695 : node _T_696 = shl(UInt<3>(0h7), 3) node _T_697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_696) connect Queue10_UInt8_6.io.enq.bits, _T_697 node _T_698 = eq(UInt<3>(0h7), idx_7) when _T_698 : node _T_699 = shl(UInt<3>(0h7), 3) node _T_700 = dshr(incoming_writes_Q.io.deq.bits.data, _T_699) connect Queue10_UInt8_7.io.enq.bits, _T_700 node _T_701 = eq(UInt<4>(0h8), idx_7) when _T_701 : node _T_702 = shl(UInt<3>(0h7), 3) node _T_703 = dshr(incoming_writes_Q.io.deq.bits.data, _T_702) connect Queue10_UInt8_8.io.enq.bits, _T_703 node _T_704 = eq(UInt<4>(0h9), idx_7) when _T_704 : node _T_705 = shl(UInt<3>(0h7), 3) node _T_706 = dshr(incoming_writes_Q.io.deq.bits.data, _T_705) connect Queue10_UInt8_9.io.enq.bits, _T_706 node _T_707 = eq(UInt<4>(0ha), idx_7) when _T_707 : node _T_708 = shl(UInt<3>(0h7), 3) node _T_709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_708) connect Queue10_UInt8_10.io.enq.bits, _T_709 node _T_710 = eq(UInt<4>(0hb), idx_7) when _T_710 : node _T_711 = shl(UInt<3>(0h7), 3) node _T_712 = dshr(incoming_writes_Q.io.deq.bits.data, _T_711) connect Queue10_UInt8_11.io.enq.bits, _T_712 node _T_713 = eq(UInt<4>(0hc), idx_7) when _T_713 : node _T_714 = shl(UInt<3>(0h7), 3) node _T_715 = dshr(incoming_writes_Q.io.deq.bits.data, _T_714) connect Queue10_UInt8_12.io.enq.bits, _T_715 node _T_716 = eq(UInt<4>(0hd), idx_7) when _T_716 : node _T_717 = shl(UInt<3>(0h7), 3) node _T_718 = dshr(incoming_writes_Q.io.deq.bits.data, _T_717) connect Queue10_UInt8_13.io.enq.bits, _T_718 node _T_719 = eq(UInt<4>(0he), idx_7) when _T_719 : node _T_720 = shl(UInt<3>(0h7), 3) node _T_721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_720) connect Queue10_UInt8_14.io.enq.bits, _T_721 node _T_722 = eq(UInt<4>(0hf), idx_7) when _T_722 : node _T_723 = shl(UInt<3>(0h7), 3) node _T_724 = dshr(incoming_writes_Q.io.deq.bits.data, _T_723) connect Queue10_UInt8_15.io.enq.bits, _T_724 node _T_725 = eq(UInt<5>(0h10), idx_7) when _T_725 : node _T_726 = shl(UInt<3>(0h7), 3) node _T_727 = dshr(incoming_writes_Q.io.deq.bits.data, _T_726) connect Queue10_UInt8_16.io.enq.bits, _T_727 node _T_728 = eq(UInt<5>(0h11), idx_7) when _T_728 : node _T_729 = shl(UInt<3>(0h7), 3) node _T_730 = dshr(incoming_writes_Q.io.deq.bits.data, _T_729) connect Queue10_UInt8_17.io.enq.bits, _T_730 node _T_731 = eq(UInt<5>(0h12), idx_7) when _T_731 : node _T_732 = shl(UInt<3>(0h7), 3) node _T_733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_732) connect Queue10_UInt8_18.io.enq.bits, _T_733 node _T_734 = eq(UInt<5>(0h13), idx_7) when _T_734 : node _T_735 = shl(UInt<3>(0h7), 3) node _T_736 = dshr(incoming_writes_Q.io.deq.bits.data, _T_735) connect Queue10_UInt8_19.io.enq.bits, _T_736 node _T_737 = eq(UInt<5>(0h14), idx_7) when _T_737 : node _T_738 = shl(UInt<3>(0h7), 3) node _T_739 = dshr(incoming_writes_Q.io.deq.bits.data, _T_738) connect Queue10_UInt8_20.io.enq.bits, _T_739 node _T_740 = eq(UInt<5>(0h15), idx_7) when _T_740 : node _T_741 = shl(UInt<3>(0h7), 3) node _T_742 = dshr(incoming_writes_Q.io.deq.bits.data, _T_741) connect Queue10_UInt8_21.io.enq.bits, _T_742 node _T_743 = eq(UInt<5>(0h16), idx_7) when _T_743 : node _T_744 = shl(UInt<3>(0h7), 3) node _T_745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_744) connect Queue10_UInt8_22.io.enq.bits, _T_745 node _T_746 = eq(UInt<5>(0h17), idx_7) when _T_746 : node _T_747 = shl(UInt<3>(0h7), 3) node _T_748 = dshr(incoming_writes_Q.io.deq.bits.data, _T_747) connect Queue10_UInt8_23.io.enq.bits, _T_748 node _T_749 = eq(UInt<5>(0h18), idx_7) when _T_749 : node _T_750 = shl(UInt<3>(0h7), 3) node _T_751 = dshr(incoming_writes_Q.io.deq.bits.data, _T_750) connect Queue10_UInt8_24.io.enq.bits, _T_751 node _T_752 = eq(UInt<5>(0h19), idx_7) when _T_752 : node _T_753 = shl(UInt<3>(0h7), 3) node _T_754 = dshr(incoming_writes_Q.io.deq.bits.data, _T_753) connect Queue10_UInt8_25.io.enq.bits, _T_754 node _T_755 = eq(UInt<5>(0h1a), idx_7) when _T_755 : node _T_756 = shl(UInt<3>(0h7), 3) node _T_757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_756) connect Queue10_UInt8_26.io.enq.bits, _T_757 node _T_758 = eq(UInt<5>(0h1b), idx_7) when _T_758 : node _T_759 = shl(UInt<3>(0h7), 3) node _T_760 = dshr(incoming_writes_Q.io.deq.bits.data, _T_759) connect Queue10_UInt8_27.io.enq.bits, _T_760 node _T_761 = eq(UInt<5>(0h1c), idx_7) when _T_761 : node _T_762 = shl(UInt<3>(0h7), 3) node _T_763 = dshr(incoming_writes_Q.io.deq.bits.data, _T_762) connect Queue10_UInt8_28.io.enq.bits, _T_763 node _T_764 = eq(UInt<5>(0h1d), idx_7) when _T_764 : node _T_765 = shl(UInt<3>(0h7), 3) node _T_766 = dshr(incoming_writes_Q.io.deq.bits.data, _T_765) connect Queue10_UInt8_29.io.enq.bits, _T_766 node _T_767 = eq(UInt<5>(0h1e), idx_7) when _T_767 : node _T_768 = shl(UInt<3>(0h7), 3) node _T_769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_768) connect Queue10_UInt8_30.io.enq.bits, _T_769 node _T_770 = eq(UInt<5>(0h1f), idx_7) when _T_770 : node _T_771 = shl(UInt<3>(0h7), 3) node _T_772 = dshr(incoming_writes_Q.io.deq.bits.data, _T_771) connect Queue10_UInt8_31.io.enq.bits, _T_772 node _idx_T_8 = add(write_start_index, UInt<4>(0h8)) node idx_8 = rem(_idx_T_8, UInt<6>(0h20)) node _T_773 = eq(UInt<1>(0h0), idx_8) when _T_773 : node _T_774 = shl(UInt<4>(0h8), 3) node _T_775 = dshr(incoming_writes_Q.io.deq.bits.data, _T_774) connect Queue10_UInt8.io.enq.bits, _T_775 node _T_776 = eq(UInt<1>(0h1), idx_8) when _T_776 : node _T_777 = shl(UInt<4>(0h8), 3) node _T_778 = dshr(incoming_writes_Q.io.deq.bits.data, _T_777) connect Queue10_UInt8_1.io.enq.bits, _T_778 node _T_779 = eq(UInt<2>(0h2), idx_8) when _T_779 : node _T_780 = shl(UInt<4>(0h8), 3) node _T_781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_780) connect Queue10_UInt8_2.io.enq.bits, _T_781 node _T_782 = eq(UInt<2>(0h3), idx_8) when _T_782 : node _T_783 = shl(UInt<4>(0h8), 3) node _T_784 = dshr(incoming_writes_Q.io.deq.bits.data, _T_783) connect Queue10_UInt8_3.io.enq.bits, _T_784 node _T_785 = eq(UInt<3>(0h4), idx_8) when _T_785 : node _T_786 = shl(UInt<4>(0h8), 3) node _T_787 = dshr(incoming_writes_Q.io.deq.bits.data, _T_786) connect Queue10_UInt8_4.io.enq.bits, _T_787 node _T_788 = eq(UInt<3>(0h5), idx_8) when _T_788 : node _T_789 = shl(UInt<4>(0h8), 3) node _T_790 = dshr(incoming_writes_Q.io.deq.bits.data, _T_789) connect Queue10_UInt8_5.io.enq.bits, _T_790 node _T_791 = eq(UInt<3>(0h6), idx_8) when _T_791 : node _T_792 = shl(UInt<4>(0h8), 3) node _T_793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_792) connect Queue10_UInt8_6.io.enq.bits, _T_793 node _T_794 = eq(UInt<3>(0h7), idx_8) when _T_794 : node _T_795 = shl(UInt<4>(0h8), 3) node _T_796 = dshr(incoming_writes_Q.io.deq.bits.data, _T_795) connect Queue10_UInt8_7.io.enq.bits, _T_796 node _T_797 = eq(UInt<4>(0h8), idx_8) when _T_797 : node _T_798 = shl(UInt<4>(0h8), 3) node _T_799 = dshr(incoming_writes_Q.io.deq.bits.data, _T_798) connect Queue10_UInt8_8.io.enq.bits, _T_799 node _T_800 = eq(UInt<4>(0h9), idx_8) when _T_800 : node _T_801 = shl(UInt<4>(0h8), 3) node _T_802 = dshr(incoming_writes_Q.io.deq.bits.data, _T_801) connect Queue10_UInt8_9.io.enq.bits, _T_802 node _T_803 = eq(UInt<4>(0ha), idx_8) when _T_803 : node _T_804 = shl(UInt<4>(0h8), 3) node _T_805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_804) connect Queue10_UInt8_10.io.enq.bits, _T_805 node _T_806 = eq(UInt<4>(0hb), idx_8) when _T_806 : node _T_807 = shl(UInt<4>(0h8), 3) node _T_808 = dshr(incoming_writes_Q.io.deq.bits.data, _T_807) connect Queue10_UInt8_11.io.enq.bits, _T_808 node _T_809 = eq(UInt<4>(0hc), idx_8) when _T_809 : node _T_810 = shl(UInt<4>(0h8), 3) node _T_811 = dshr(incoming_writes_Q.io.deq.bits.data, _T_810) connect Queue10_UInt8_12.io.enq.bits, _T_811 node _T_812 = eq(UInt<4>(0hd), idx_8) when _T_812 : node _T_813 = shl(UInt<4>(0h8), 3) node _T_814 = dshr(incoming_writes_Q.io.deq.bits.data, _T_813) connect Queue10_UInt8_13.io.enq.bits, _T_814 node _T_815 = eq(UInt<4>(0he), idx_8) when _T_815 : node _T_816 = shl(UInt<4>(0h8), 3) node _T_817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_816) connect Queue10_UInt8_14.io.enq.bits, _T_817 node _T_818 = eq(UInt<4>(0hf), idx_8) when _T_818 : node _T_819 = shl(UInt<4>(0h8), 3) node _T_820 = dshr(incoming_writes_Q.io.deq.bits.data, _T_819) connect Queue10_UInt8_15.io.enq.bits, _T_820 node _T_821 = eq(UInt<5>(0h10), idx_8) when _T_821 : node _T_822 = shl(UInt<4>(0h8), 3) node _T_823 = dshr(incoming_writes_Q.io.deq.bits.data, _T_822) connect Queue10_UInt8_16.io.enq.bits, _T_823 node _T_824 = eq(UInt<5>(0h11), idx_8) when _T_824 : node _T_825 = shl(UInt<4>(0h8), 3) node _T_826 = dshr(incoming_writes_Q.io.deq.bits.data, _T_825) connect Queue10_UInt8_17.io.enq.bits, _T_826 node _T_827 = eq(UInt<5>(0h12), idx_8) when _T_827 : node _T_828 = shl(UInt<4>(0h8), 3) node _T_829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_828) connect Queue10_UInt8_18.io.enq.bits, _T_829 node _T_830 = eq(UInt<5>(0h13), idx_8) when _T_830 : node _T_831 = shl(UInt<4>(0h8), 3) node _T_832 = dshr(incoming_writes_Q.io.deq.bits.data, _T_831) connect Queue10_UInt8_19.io.enq.bits, _T_832 node _T_833 = eq(UInt<5>(0h14), idx_8) when _T_833 : node _T_834 = shl(UInt<4>(0h8), 3) node _T_835 = dshr(incoming_writes_Q.io.deq.bits.data, _T_834) connect Queue10_UInt8_20.io.enq.bits, _T_835 node _T_836 = eq(UInt<5>(0h15), idx_8) when _T_836 : node _T_837 = shl(UInt<4>(0h8), 3) node _T_838 = dshr(incoming_writes_Q.io.deq.bits.data, _T_837) connect Queue10_UInt8_21.io.enq.bits, _T_838 node _T_839 = eq(UInt<5>(0h16), idx_8) when _T_839 : node _T_840 = shl(UInt<4>(0h8), 3) node _T_841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_840) connect Queue10_UInt8_22.io.enq.bits, _T_841 node _T_842 = eq(UInt<5>(0h17), idx_8) when _T_842 : node _T_843 = shl(UInt<4>(0h8), 3) node _T_844 = dshr(incoming_writes_Q.io.deq.bits.data, _T_843) connect Queue10_UInt8_23.io.enq.bits, _T_844 node _T_845 = eq(UInt<5>(0h18), idx_8) when _T_845 : node _T_846 = shl(UInt<4>(0h8), 3) node _T_847 = dshr(incoming_writes_Q.io.deq.bits.data, _T_846) connect Queue10_UInt8_24.io.enq.bits, _T_847 node _T_848 = eq(UInt<5>(0h19), idx_8) when _T_848 : node _T_849 = shl(UInt<4>(0h8), 3) node _T_850 = dshr(incoming_writes_Q.io.deq.bits.data, _T_849) connect Queue10_UInt8_25.io.enq.bits, _T_850 node _T_851 = eq(UInt<5>(0h1a), idx_8) when _T_851 : node _T_852 = shl(UInt<4>(0h8), 3) node _T_853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_852) connect Queue10_UInt8_26.io.enq.bits, _T_853 node _T_854 = eq(UInt<5>(0h1b), idx_8) when _T_854 : node _T_855 = shl(UInt<4>(0h8), 3) node _T_856 = dshr(incoming_writes_Q.io.deq.bits.data, _T_855) connect Queue10_UInt8_27.io.enq.bits, _T_856 node _T_857 = eq(UInt<5>(0h1c), idx_8) when _T_857 : node _T_858 = shl(UInt<4>(0h8), 3) node _T_859 = dshr(incoming_writes_Q.io.deq.bits.data, _T_858) connect Queue10_UInt8_28.io.enq.bits, _T_859 node _T_860 = eq(UInt<5>(0h1d), idx_8) when _T_860 : node _T_861 = shl(UInt<4>(0h8), 3) node _T_862 = dshr(incoming_writes_Q.io.deq.bits.data, _T_861) connect Queue10_UInt8_29.io.enq.bits, _T_862 node _T_863 = eq(UInt<5>(0h1e), idx_8) when _T_863 : node _T_864 = shl(UInt<4>(0h8), 3) node _T_865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_864) connect Queue10_UInt8_30.io.enq.bits, _T_865 node _T_866 = eq(UInt<5>(0h1f), idx_8) when _T_866 : node _T_867 = shl(UInt<4>(0h8), 3) node _T_868 = dshr(incoming_writes_Q.io.deq.bits.data, _T_867) connect Queue10_UInt8_31.io.enq.bits, _T_868 node _idx_T_9 = add(write_start_index, UInt<4>(0h9)) node idx_9 = rem(_idx_T_9, UInt<6>(0h20)) node _T_869 = eq(UInt<1>(0h0), idx_9) when _T_869 : node _T_870 = shl(UInt<4>(0h9), 3) node _T_871 = dshr(incoming_writes_Q.io.deq.bits.data, _T_870) connect Queue10_UInt8.io.enq.bits, _T_871 node _T_872 = eq(UInt<1>(0h1), idx_9) when _T_872 : node _T_873 = shl(UInt<4>(0h9), 3) node _T_874 = dshr(incoming_writes_Q.io.deq.bits.data, _T_873) connect Queue10_UInt8_1.io.enq.bits, _T_874 node _T_875 = eq(UInt<2>(0h2), idx_9) when _T_875 : node _T_876 = shl(UInt<4>(0h9), 3) node _T_877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_876) connect Queue10_UInt8_2.io.enq.bits, _T_877 node _T_878 = eq(UInt<2>(0h3), idx_9) when _T_878 : node _T_879 = shl(UInt<4>(0h9), 3) node _T_880 = dshr(incoming_writes_Q.io.deq.bits.data, _T_879) connect Queue10_UInt8_3.io.enq.bits, _T_880 node _T_881 = eq(UInt<3>(0h4), idx_9) when _T_881 : node _T_882 = shl(UInt<4>(0h9), 3) node _T_883 = dshr(incoming_writes_Q.io.deq.bits.data, _T_882) connect Queue10_UInt8_4.io.enq.bits, _T_883 node _T_884 = eq(UInt<3>(0h5), idx_9) when _T_884 : node _T_885 = shl(UInt<4>(0h9), 3) node _T_886 = dshr(incoming_writes_Q.io.deq.bits.data, _T_885) connect Queue10_UInt8_5.io.enq.bits, _T_886 node _T_887 = eq(UInt<3>(0h6), idx_9) when _T_887 : node _T_888 = shl(UInt<4>(0h9), 3) node _T_889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_888) connect Queue10_UInt8_6.io.enq.bits, _T_889 node _T_890 = eq(UInt<3>(0h7), idx_9) when _T_890 : node _T_891 = shl(UInt<4>(0h9), 3) node _T_892 = dshr(incoming_writes_Q.io.deq.bits.data, _T_891) connect Queue10_UInt8_7.io.enq.bits, _T_892 node _T_893 = eq(UInt<4>(0h8), idx_9) when _T_893 : node _T_894 = shl(UInt<4>(0h9), 3) node _T_895 = dshr(incoming_writes_Q.io.deq.bits.data, _T_894) connect Queue10_UInt8_8.io.enq.bits, _T_895 node _T_896 = eq(UInt<4>(0h9), idx_9) when _T_896 : node _T_897 = shl(UInt<4>(0h9), 3) node _T_898 = dshr(incoming_writes_Q.io.deq.bits.data, _T_897) connect Queue10_UInt8_9.io.enq.bits, _T_898 node _T_899 = eq(UInt<4>(0ha), idx_9) when _T_899 : node _T_900 = shl(UInt<4>(0h9), 3) node _T_901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_900) connect Queue10_UInt8_10.io.enq.bits, _T_901 node _T_902 = eq(UInt<4>(0hb), idx_9) when _T_902 : node _T_903 = shl(UInt<4>(0h9), 3) node _T_904 = dshr(incoming_writes_Q.io.deq.bits.data, _T_903) connect Queue10_UInt8_11.io.enq.bits, _T_904 node _T_905 = eq(UInt<4>(0hc), idx_9) when _T_905 : node _T_906 = shl(UInt<4>(0h9), 3) node _T_907 = dshr(incoming_writes_Q.io.deq.bits.data, _T_906) connect Queue10_UInt8_12.io.enq.bits, _T_907 node _T_908 = eq(UInt<4>(0hd), idx_9) when _T_908 : node _T_909 = shl(UInt<4>(0h9), 3) node _T_910 = dshr(incoming_writes_Q.io.deq.bits.data, _T_909) connect Queue10_UInt8_13.io.enq.bits, _T_910 node _T_911 = eq(UInt<4>(0he), idx_9) when _T_911 : node _T_912 = shl(UInt<4>(0h9), 3) node _T_913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_912) connect Queue10_UInt8_14.io.enq.bits, _T_913 node _T_914 = eq(UInt<4>(0hf), idx_9) when _T_914 : node _T_915 = shl(UInt<4>(0h9), 3) node _T_916 = dshr(incoming_writes_Q.io.deq.bits.data, _T_915) connect Queue10_UInt8_15.io.enq.bits, _T_916 node _T_917 = eq(UInt<5>(0h10), idx_9) when _T_917 : node _T_918 = shl(UInt<4>(0h9), 3) node _T_919 = dshr(incoming_writes_Q.io.deq.bits.data, _T_918) connect Queue10_UInt8_16.io.enq.bits, _T_919 node _T_920 = eq(UInt<5>(0h11), idx_9) when _T_920 : node _T_921 = shl(UInt<4>(0h9), 3) node _T_922 = dshr(incoming_writes_Q.io.deq.bits.data, _T_921) connect Queue10_UInt8_17.io.enq.bits, _T_922 node _T_923 = eq(UInt<5>(0h12), idx_9) when _T_923 : node _T_924 = shl(UInt<4>(0h9), 3) node _T_925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_924) connect Queue10_UInt8_18.io.enq.bits, _T_925 node _T_926 = eq(UInt<5>(0h13), idx_9) when _T_926 : node _T_927 = shl(UInt<4>(0h9), 3) node _T_928 = dshr(incoming_writes_Q.io.deq.bits.data, _T_927) connect Queue10_UInt8_19.io.enq.bits, _T_928 node _T_929 = eq(UInt<5>(0h14), idx_9) when _T_929 : node _T_930 = shl(UInt<4>(0h9), 3) node _T_931 = dshr(incoming_writes_Q.io.deq.bits.data, _T_930) connect Queue10_UInt8_20.io.enq.bits, _T_931 node _T_932 = eq(UInt<5>(0h15), idx_9) when _T_932 : node _T_933 = shl(UInt<4>(0h9), 3) node _T_934 = dshr(incoming_writes_Q.io.deq.bits.data, _T_933) connect Queue10_UInt8_21.io.enq.bits, _T_934 node _T_935 = eq(UInt<5>(0h16), idx_9) when _T_935 : node _T_936 = shl(UInt<4>(0h9), 3) node _T_937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_936) connect Queue10_UInt8_22.io.enq.bits, _T_937 node _T_938 = eq(UInt<5>(0h17), idx_9) when _T_938 : node _T_939 = shl(UInt<4>(0h9), 3) node _T_940 = dshr(incoming_writes_Q.io.deq.bits.data, _T_939) connect Queue10_UInt8_23.io.enq.bits, _T_940 node _T_941 = eq(UInt<5>(0h18), idx_9) when _T_941 : node _T_942 = shl(UInt<4>(0h9), 3) node _T_943 = dshr(incoming_writes_Q.io.deq.bits.data, _T_942) connect Queue10_UInt8_24.io.enq.bits, _T_943 node _T_944 = eq(UInt<5>(0h19), idx_9) when _T_944 : node _T_945 = shl(UInt<4>(0h9), 3) node _T_946 = dshr(incoming_writes_Q.io.deq.bits.data, _T_945) connect Queue10_UInt8_25.io.enq.bits, _T_946 node _T_947 = eq(UInt<5>(0h1a), idx_9) when _T_947 : node _T_948 = shl(UInt<4>(0h9), 3) node _T_949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_948) connect Queue10_UInt8_26.io.enq.bits, _T_949 node _T_950 = eq(UInt<5>(0h1b), idx_9) when _T_950 : node _T_951 = shl(UInt<4>(0h9), 3) node _T_952 = dshr(incoming_writes_Q.io.deq.bits.data, _T_951) connect Queue10_UInt8_27.io.enq.bits, _T_952 node _T_953 = eq(UInt<5>(0h1c), idx_9) when _T_953 : node _T_954 = shl(UInt<4>(0h9), 3) node _T_955 = dshr(incoming_writes_Q.io.deq.bits.data, _T_954) connect Queue10_UInt8_28.io.enq.bits, _T_955 node _T_956 = eq(UInt<5>(0h1d), idx_9) when _T_956 : node _T_957 = shl(UInt<4>(0h9), 3) node _T_958 = dshr(incoming_writes_Q.io.deq.bits.data, _T_957) connect Queue10_UInt8_29.io.enq.bits, _T_958 node _T_959 = eq(UInt<5>(0h1e), idx_9) when _T_959 : node _T_960 = shl(UInt<4>(0h9), 3) node _T_961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_960) connect Queue10_UInt8_30.io.enq.bits, _T_961 node _T_962 = eq(UInt<5>(0h1f), idx_9) when _T_962 : node _T_963 = shl(UInt<4>(0h9), 3) node _T_964 = dshr(incoming_writes_Q.io.deq.bits.data, _T_963) connect Queue10_UInt8_31.io.enq.bits, _T_964 node _idx_T_10 = add(write_start_index, UInt<4>(0ha)) node idx_10 = rem(_idx_T_10, UInt<6>(0h20)) node _T_965 = eq(UInt<1>(0h0), idx_10) when _T_965 : node _T_966 = shl(UInt<4>(0ha), 3) node _T_967 = dshr(incoming_writes_Q.io.deq.bits.data, _T_966) connect Queue10_UInt8.io.enq.bits, _T_967 node _T_968 = eq(UInt<1>(0h1), idx_10) when _T_968 : node _T_969 = shl(UInt<4>(0ha), 3) node _T_970 = dshr(incoming_writes_Q.io.deq.bits.data, _T_969) connect Queue10_UInt8_1.io.enq.bits, _T_970 node _T_971 = eq(UInt<2>(0h2), idx_10) when _T_971 : node _T_972 = shl(UInt<4>(0ha), 3) node _T_973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_972) connect Queue10_UInt8_2.io.enq.bits, _T_973 node _T_974 = eq(UInt<2>(0h3), idx_10) when _T_974 : node _T_975 = shl(UInt<4>(0ha), 3) node _T_976 = dshr(incoming_writes_Q.io.deq.bits.data, _T_975) connect Queue10_UInt8_3.io.enq.bits, _T_976 node _T_977 = eq(UInt<3>(0h4), idx_10) when _T_977 : node _T_978 = shl(UInt<4>(0ha), 3) node _T_979 = dshr(incoming_writes_Q.io.deq.bits.data, _T_978) connect Queue10_UInt8_4.io.enq.bits, _T_979 node _T_980 = eq(UInt<3>(0h5), idx_10) when _T_980 : node _T_981 = shl(UInt<4>(0ha), 3) node _T_982 = dshr(incoming_writes_Q.io.deq.bits.data, _T_981) connect Queue10_UInt8_5.io.enq.bits, _T_982 node _T_983 = eq(UInt<3>(0h6), idx_10) when _T_983 : node _T_984 = shl(UInt<4>(0ha), 3) node _T_985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_984) connect Queue10_UInt8_6.io.enq.bits, _T_985 node _T_986 = eq(UInt<3>(0h7), idx_10) when _T_986 : node _T_987 = shl(UInt<4>(0ha), 3) node _T_988 = dshr(incoming_writes_Q.io.deq.bits.data, _T_987) connect Queue10_UInt8_7.io.enq.bits, _T_988 node _T_989 = eq(UInt<4>(0h8), idx_10) when _T_989 : node _T_990 = shl(UInt<4>(0ha), 3) node _T_991 = dshr(incoming_writes_Q.io.deq.bits.data, _T_990) connect Queue10_UInt8_8.io.enq.bits, _T_991 node _T_992 = eq(UInt<4>(0h9), idx_10) when _T_992 : node _T_993 = shl(UInt<4>(0ha), 3) node _T_994 = dshr(incoming_writes_Q.io.deq.bits.data, _T_993) connect Queue10_UInt8_9.io.enq.bits, _T_994 node _T_995 = eq(UInt<4>(0ha), idx_10) when _T_995 : node _T_996 = shl(UInt<4>(0ha), 3) node _T_997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_996) connect Queue10_UInt8_10.io.enq.bits, _T_997 node _T_998 = eq(UInt<4>(0hb), idx_10) when _T_998 : node _T_999 = shl(UInt<4>(0ha), 3) node _T_1000 = dshr(incoming_writes_Q.io.deq.bits.data, _T_999) connect Queue10_UInt8_11.io.enq.bits, _T_1000 node _T_1001 = eq(UInt<4>(0hc), idx_10) when _T_1001 : node _T_1002 = shl(UInt<4>(0ha), 3) node _T_1003 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1002) connect Queue10_UInt8_12.io.enq.bits, _T_1003 node _T_1004 = eq(UInt<4>(0hd), idx_10) when _T_1004 : node _T_1005 = shl(UInt<4>(0ha), 3) node _T_1006 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1005) connect Queue10_UInt8_13.io.enq.bits, _T_1006 node _T_1007 = eq(UInt<4>(0he), idx_10) when _T_1007 : node _T_1008 = shl(UInt<4>(0ha), 3) node _T_1009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1008) connect Queue10_UInt8_14.io.enq.bits, _T_1009 node _T_1010 = eq(UInt<4>(0hf), idx_10) when _T_1010 : node _T_1011 = shl(UInt<4>(0ha), 3) node _T_1012 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1011) connect Queue10_UInt8_15.io.enq.bits, _T_1012 node _T_1013 = eq(UInt<5>(0h10), idx_10) when _T_1013 : node _T_1014 = shl(UInt<4>(0ha), 3) node _T_1015 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1014) connect Queue10_UInt8_16.io.enq.bits, _T_1015 node _T_1016 = eq(UInt<5>(0h11), idx_10) when _T_1016 : node _T_1017 = shl(UInt<4>(0ha), 3) node _T_1018 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1017) connect Queue10_UInt8_17.io.enq.bits, _T_1018 node _T_1019 = eq(UInt<5>(0h12), idx_10) when _T_1019 : node _T_1020 = shl(UInt<4>(0ha), 3) node _T_1021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1020) connect Queue10_UInt8_18.io.enq.bits, _T_1021 node _T_1022 = eq(UInt<5>(0h13), idx_10) when _T_1022 : node _T_1023 = shl(UInt<4>(0ha), 3) node _T_1024 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1023) connect Queue10_UInt8_19.io.enq.bits, _T_1024 node _T_1025 = eq(UInt<5>(0h14), idx_10) when _T_1025 : node _T_1026 = shl(UInt<4>(0ha), 3) node _T_1027 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1026) connect Queue10_UInt8_20.io.enq.bits, _T_1027 node _T_1028 = eq(UInt<5>(0h15), idx_10) when _T_1028 : node _T_1029 = shl(UInt<4>(0ha), 3) node _T_1030 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1029) connect Queue10_UInt8_21.io.enq.bits, _T_1030 node _T_1031 = eq(UInt<5>(0h16), idx_10) when _T_1031 : node _T_1032 = shl(UInt<4>(0ha), 3) node _T_1033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1032) connect Queue10_UInt8_22.io.enq.bits, _T_1033 node _T_1034 = eq(UInt<5>(0h17), idx_10) when _T_1034 : node _T_1035 = shl(UInt<4>(0ha), 3) node _T_1036 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1035) connect Queue10_UInt8_23.io.enq.bits, _T_1036 node _T_1037 = eq(UInt<5>(0h18), idx_10) when _T_1037 : node _T_1038 = shl(UInt<4>(0ha), 3) node _T_1039 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1038) connect Queue10_UInt8_24.io.enq.bits, _T_1039 node _T_1040 = eq(UInt<5>(0h19), idx_10) when _T_1040 : node _T_1041 = shl(UInt<4>(0ha), 3) node _T_1042 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1041) connect Queue10_UInt8_25.io.enq.bits, _T_1042 node _T_1043 = eq(UInt<5>(0h1a), idx_10) when _T_1043 : node _T_1044 = shl(UInt<4>(0ha), 3) node _T_1045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1044) connect Queue10_UInt8_26.io.enq.bits, _T_1045 node _T_1046 = eq(UInt<5>(0h1b), idx_10) when _T_1046 : node _T_1047 = shl(UInt<4>(0ha), 3) node _T_1048 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1047) connect Queue10_UInt8_27.io.enq.bits, _T_1048 node _T_1049 = eq(UInt<5>(0h1c), idx_10) when _T_1049 : node _T_1050 = shl(UInt<4>(0ha), 3) node _T_1051 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1050) connect Queue10_UInt8_28.io.enq.bits, _T_1051 node _T_1052 = eq(UInt<5>(0h1d), idx_10) when _T_1052 : node _T_1053 = shl(UInt<4>(0ha), 3) node _T_1054 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1053) connect Queue10_UInt8_29.io.enq.bits, _T_1054 node _T_1055 = eq(UInt<5>(0h1e), idx_10) when _T_1055 : node _T_1056 = shl(UInt<4>(0ha), 3) node _T_1057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1056) connect Queue10_UInt8_30.io.enq.bits, _T_1057 node _T_1058 = eq(UInt<5>(0h1f), idx_10) when _T_1058 : node _T_1059 = shl(UInt<4>(0ha), 3) node _T_1060 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1059) connect Queue10_UInt8_31.io.enq.bits, _T_1060 node _idx_T_11 = add(write_start_index, UInt<4>(0hb)) node idx_11 = rem(_idx_T_11, UInt<6>(0h20)) node _T_1061 = eq(UInt<1>(0h0), idx_11) when _T_1061 : node _T_1062 = shl(UInt<4>(0hb), 3) node _T_1063 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1062) connect Queue10_UInt8.io.enq.bits, _T_1063 node _T_1064 = eq(UInt<1>(0h1), idx_11) when _T_1064 : node _T_1065 = shl(UInt<4>(0hb), 3) node _T_1066 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1065) connect Queue10_UInt8_1.io.enq.bits, _T_1066 node _T_1067 = eq(UInt<2>(0h2), idx_11) when _T_1067 : node _T_1068 = shl(UInt<4>(0hb), 3) node _T_1069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1068) connect Queue10_UInt8_2.io.enq.bits, _T_1069 node _T_1070 = eq(UInt<2>(0h3), idx_11) when _T_1070 : node _T_1071 = shl(UInt<4>(0hb), 3) node _T_1072 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1071) connect Queue10_UInt8_3.io.enq.bits, _T_1072 node _T_1073 = eq(UInt<3>(0h4), idx_11) when _T_1073 : node _T_1074 = shl(UInt<4>(0hb), 3) node _T_1075 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1074) connect Queue10_UInt8_4.io.enq.bits, _T_1075 node _T_1076 = eq(UInt<3>(0h5), idx_11) when _T_1076 : node _T_1077 = shl(UInt<4>(0hb), 3) node _T_1078 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1077) connect Queue10_UInt8_5.io.enq.bits, _T_1078 node _T_1079 = eq(UInt<3>(0h6), idx_11) when _T_1079 : node _T_1080 = shl(UInt<4>(0hb), 3) node _T_1081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1080) connect Queue10_UInt8_6.io.enq.bits, _T_1081 node _T_1082 = eq(UInt<3>(0h7), idx_11) when _T_1082 : node _T_1083 = shl(UInt<4>(0hb), 3) node _T_1084 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1083) connect Queue10_UInt8_7.io.enq.bits, _T_1084 node _T_1085 = eq(UInt<4>(0h8), idx_11) when _T_1085 : node _T_1086 = shl(UInt<4>(0hb), 3) node _T_1087 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1086) connect Queue10_UInt8_8.io.enq.bits, _T_1087 node _T_1088 = eq(UInt<4>(0h9), idx_11) when _T_1088 : node _T_1089 = shl(UInt<4>(0hb), 3) node _T_1090 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1089) connect Queue10_UInt8_9.io.enq.bits, _T_1090 node _T_1091 = eq(UInt<4>(0ha), idx_11) when _T_1091 : node _T_1092 = shl(UInt<4>(0hb), 3) node _T_1093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1092) connect Queue10_UInt8_10.io.enq.bits, _T_1093 node _T_1094 = eq(UInt<4>(0hb), idx_11) when _T_1094 : node _T_1095 = shl(UInt<4>(0hb), 3) node _T_1096 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1095) connect Queue10_UInt8_11.io.enq.bits, _T_1096 node _T_1097 = eq(UInt<4>(0hc), idx_11) when _T_1097 : node _T_1098 = shl(UInt<4>(0hb), 3) node _T_1099 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1098) connect Queue10_UInt8_12.io.enq.bits, _T_1099 node _T_1100 = eq(UInt<4>(0hd), idx_11) when _T_1100 : node _T_1101 = shl(UInt<4>(0hb), 3) node _T_1102 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1101) connect Queue10_UInt8_13.io.enq.bits, _T_1102 node _T_1103 = eq(UInt<4>(0he), idx_11) when _T_1103 : node _T_1104 = shl(UInt<4>(0hb), 3) node _T_1105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1104) connect Queue10_UInt8_14.io.enq.bits, _T_1105 node _T_1106 = eq(UInt<4>(0hf), idx_11) when _T_1106 : node _T_1107 = shl(UInt<4>(0hb), 3) node _T_1108 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1107) connect Queue10_UInt8_15.io.enq.bits, _T_1108 node _T_1109 = eq(UInt<5>(0h10), idx_11) when _T_1109 : node _T_1110 = shl(UInt<4>(0hb), 3) node _T_1111 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1110) connect Queue10_UInt8_16.io.enq.bits, _T_1111 node _T_1112 = eq(UInt<5>(0h11), idx_11) when _T_1112 : node _T_1113 = shl(UInt<4>(0hb), 3) node _T_1114 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1113) connect Queue10_UInt8_17.io.enq.bits, _T_1114 node _T_1115 = eq(UInt<5>(0h12), idx_11) when _T_1115 : node _T_1116 = shl(UInt<4>(0hb), 3) node _T_1117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1116) connect Queue10_UInt8_18.io.enq.bits, _T_1117 node _T_1118 = eq(UInt<5>(0h13), idx_11) when _T_1118 : node _T_1119 = shl(UInt<4>(0hb), 3) node _T_1120 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1119) connect Queue10_UInt8_19.io.enq.bits, _T_1120 node _T_1121 = eq(UInt<5>(0h14), idx_11) when _T_1121 : node _T_1122 = shl(UInt<4>(0hb), 3) node _T_1123 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1122) connect Queue10_UInt8_20.io.enq.bits, _T_1123 node _T_1124 = eq(UInt<5>(0h15), idx_11) when _T_1124 : node _T_1125 = shl(UInt<4>(0hb), 3) node _T_1126 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1125) connect Queue10_UInt8_21.io.enq.bits, _T_1126 node _T_1127 = eq(UInt<5>(0h16), idx_11) when _T_1127 : node _T_1128 = shl(UInt<4>(0hb), 3) node _T_1129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1128) connect Queue10_UInt8_22.io.enq.bits, _T_1129 node _T_1130 = eq(UInt<5>(0h17), idx_11) when _T_1130 : node _T_1131 = shl(UInt<4>(0hb), 3) node _T_1132 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1131) connect Queue10_UInt8_23.io.enq.bits, _T_1132 node _T_1133 = eq(UInt<5>(0h18), idx_11) when _T_1133 : node _T_1134 = shl(UInt<4>(0hb), 3) node _T_1135 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1134) connect Queue10_UInt8_24.io.enq.bits, _T_1135 node _T_1136 = eq(UInt<5>(0h19), idx_11) when _T_1136 : node _T_1137 = shl(UInt<4>(0hb), 3) node _T_1138 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1137) connect Queue10_UInt8_25.io.enq.bits, _T_1138 node _T_1139 = eq(UInt<5>(0h1a), idx_11) when _T_1139 : node _T_1140 = shl(UInt<4>(0hb), 3) node _T_1141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1140) connect Queue10_UInt8_26.io.enq.bits, _T_1141 node _T_1142 = eq(UInt<5>(0h1b), idx_11) when _T_1142 : node _T_1143 = shl(UInt<4>(0hb), 3) node _T_1144 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1143) connect Queue10_UInt8_27.io.enq.bits, _T_1144 node _T_1145 = eq(UInt<5>(0h1c), idx_11) when _T_1145 : node _T_1146 = shl(UInt<4>(0hb), 3) node _T_1147 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1146) connect Queue10_UInt8_28.io.enq.bits, _T_1147 node _T_1148 = eq(UInt<5>(0h1d), idx_11) when _T_1148 : node _T_1149 = shl(UInt<4>(0hb), 3) node _T_1150 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1149) connect Queue10_UInt8_29.io.enq.bits, _T_1150 node _T_1151 = eq(UInt<5>(0h1e), idx_11) when _T_1151 : node _T_1152 = shl(UInt<4>(0hb), 3) node _T_1153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1152) connect Queue10_UInt8_30.io.enq.bits, _T_1153 node _T_1154 = eq(UInt<5>(0h1f), idx_11) when _T_1154 : node _T_1155 = shl(UInt<4>(0hb), 3) node _T_1156 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1155) connect Queue10_UInt8_31.io.enq.bits, _T_1156 node _idx_T_12 = add(write_start_index, UInt<4>(0hc)) node idx_12 = rem(_idx_T_12, UInt<6>(0h20)) node _T_1157 = eq(UInt<1>(0h0), idx_12) when _T_1157 : node _T_1158 = shl(UInt<4>(0hc), 3) node _T_1159 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1158) connect Queue10_UInt8.io.enq.bits, _T_1159 node _T_1160 = eq(UInt<1>(0h1), idx_12) when _T_1160 : node _T_1161 = shl(UInt<4>(0hc), 3) node _T_1162 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1161) connect Queue10_UInt8_1.io.enq.bits, _T_1162 node _T_1163 = eq(UInt<2>(0h2), idx_12) when _T_1163 : node _T_1164 = shl(UInt<4>(0hc), 3) node _T_1165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1164) connect Queue10_UInt8_2.io.enq.bits, _T_1165 node _T_1166 = eq(UInt<2>(0h3), idx_12) when _T_1166 : node _T_1167 = shl(UInt<4>(0hc), 3) node _T_1168 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1167) connect Queue10_UInt8_3.io.enq.bits, _T_1168 node _T_1169 = eq(UInt<3>(0h4), idx_12) when _T_1169 : node _T_1170 = shl(UInt<4>(0hc), 3) node _T_1171 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1170) connect Queue10_UInt8_4.io.enq.bits, _T_1171 node _T_1172 = eq(UInt<3>(0h5), idx_12) when _T_1172 : node _T_1173 = shl(UInt<4>(0hc), 3) node _T_1174 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1173) connect Queue10_UInt8_5.io.enq.bits, _T_1174 node _T_1175 = eq(UInt<3>(0h6), idx_12) when _T_1175 : node _T_1176 = shl(UInt<4>(0hc), 3) node _T_1177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1176) connect Queue10_UInt8_6.io.enq.bits, _T_1177 node _T_1178 = eq(UInt<3>(0h7), idx_12) when _T_1178 : node _T_1179 = shl(UInt<4>(0hc), 3) node _T_1180 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1179) connect Queue10_UInt8_7.io.enq.bits, _T_1180 node _T_1181 = eq(UInt<4>(0h8), idx_12) when _T_1181 : node _T_1182 = shl(UInt<4>(0hc), 3) node _T_1183 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1182) connect Queue10_UInt8_8.io.enq.bits, _T_1183 node _T_1184 = eq(UInt<4>(0h9), idx_12) when _T_1184 : node _T_1185 = shl(UInt<4>(0hc), 3) node _T_1186 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1185) connect Queue10_UInt8_9.io.enq.bits, _T_1186 node _T_1187 = eq(UInt<4>(0ha), idx_12) when _T_1187 : node _T_1188 = shl(UInt<4>(0hc), 3) node _T_1189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1188) connect Queue10_UInt8_10.io.enq.bits, _T_1189 node _T_1190 = eq(UInt<4>(0hb), idx_12) when _T_1190 : node _T_1191 = shl(UInt<4>(0hc), 3) node _T_1192 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1191) connect Queue10_UInt8_11.io.enq.bits, _T_1192 node _T_1193 = eq(UInt<4>(0hc), idx_12) when _T_1193 : node _T_1194 = shl(UInt<4>(0hc), 3) node _T_1195 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1194) connect Queue10_UInt8_12.io.enq.bits, _T_1195 node _T_1196 = eq(UInt<4>(0hd), idx_12) when _T_1196 : node _T_1197 = shl(UInt<4>(0hc), 3) node _T_1198 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1197) connect Queue10_UInt8_13.io.enq.bits, _T_1198 node _T_1199 = eq(UInt<4>(0he), idx_12) when _T_1199 : node _T_1200 = shl(UInt<4>(0hc), 3) node _T_1201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1200) connect Queue10_UInt8_14.io.enq.bits, _T_1201 node _T_1202 = eq(UInt<4>(0hf), idx_12) when _T_1202 : node _T_1203 = shl(UInt<4>(0hc), 3) node _T_1204 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1203) connect Queue10_UInt8_15.io.enq.bits, _T_1204 node _T_1205 = eq(UInt<5>(0h10), idx_12) when _T_1205 : node _T_1206 = shl(UInt<4>(0hc), 3) node _T_1207 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1206) connect Queue10_UInt8_16.io.enq.bits, _T_1207 node _T_1208 = eq(UInt<5>(0h11), idx_12) when _T_1208 : node _T_1209 = shl(UInt<4>(0hc), 3) node _T_1210 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1209) connect Queue10_UInt8_17.io.enq.bits, _T_1210 node _T_1211 = eq(UInt<5>(0h12), idx_12) when _T_1211 : node _T_1212 = shl(UInt<4>(0hc), 3) node _T_1213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1212) connect Queue10_UInt8_18.io.enq.bits, _T_1213 node _T_1214 = eq(UInt<5>(0h13), idx_12) when _T_1214 : node _T_1215 = shl(UInt<4>(0hc), 3) node _T_1216 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1215) connect Queue10_UInt8_19.io.enq.bits, _T_1216 node _T_1217 = eq(UInt<5>(0h14), idx_12) when _T_1217 : node _T_1218 = shl(UInt<4>(0hc), 3) node _T_1219 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1218) connect Queue10_UInt8_20.io.enq.bits, _T_1219 node _T_1220 = eq(UInt<5>(0h15), idx_12) when _T_1220 : node _T_1221 = shl(UInt<4>(0hc), 3) node _T_1222 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1221) connect Queue10_UInt8_21.io.enq.bits, _T_1222 node _T_1223 = eq(UInt<5>(0h16), idx_12) when _T_1223 : node _T_1224 = shl(UInt<4>(0hc), 3) node _T_1225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1224) connect Queue10_UInt8_22.io.enq.bits, _T_1225 node _T_1226 = eq(UInt<5>(0h17), idx_12) when _T_1226 : node _T_1227 = shl(UInt<4>(0hc), 3) node _T_1228 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1227) connect Queue10_UInt8_23.io.enq.bits, _T_1228 node _T_1229 = eq(UInt<5>(0h18), idx_12) when _T_1229 : node _T_1230 = shl(UInt<4>(0hc), 3) node _T_1231 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1230) connect Queue10_UInt8_24.io.enq.bits, _T_1231 node _T_1232 = eq(UInt<5>(0h19), idx_12) when _T_1232 : node _T_1233 = shl(UInt<4>(0hc), 3) node _T_1234 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1233) connect Queue10_UInt8_25.io.enq.bits, _T_1234 node _T_1235 = eq(UInt<5>(0h1a), idx_12) when _T_1235 : node _T_1236 = shl(UInt<4>(0hc), 3) node _T_1237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1236) connect Queue10_UInt8_26.io.enq.bits, _T_1237 node _T_1238 = eq(UInt<5>(0h1b), idx_12) when _T_1238 : node _T_1239 = shl(UInt<4>(0hc), 3) node _T_1240 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1239) connect Queue10_UInt8_27.io.enq.bits, _T_1240 node _T_1241 = eq(UInt<5>(0h1c), idx_12) when _T_1241 : node _T_1242 = shl(UInt<4>(0hc), 3) node _T_1243 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1242) connect Queue10_UInt8_28.io.enq.bits, _T_1243 node _T_1244 = eq(UInt<5>(0h1d), idx_12) when _T_1244 : node _T_1245 = shl(UInt<4>(0hc), 3) node _T_1246 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1245) connect Queue10_UInt8_29.io.enq.bits, _T_1246 node _T_1247 = eq(UInt<5>(0h1e), idx_12) when _T_1247 : node _T_1248 = shl(UInt<4>(0hc), 3) node _T_1249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1248) connect Queue10_UInt8_30.io.enq.bits, _T_1249 node _T_1250 = eq(UInt<5>(0h1f), idx_12) when _T_1250 : node _T_1251 = shl(UInt<4>(0hc), 3) node _T_1252 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1251) connect Queue10_UInt8_31.io.enq.bits, _T_1252 node _idx_T_13 = add(write_start_index, UInt<4>(0hd)) node idx_13 = rem(_idx_T_13, UInt<6>(0h20)) node _T_1253 = eq(UInt<1>(0h0), idx_13) when _T_1253 : node _T_1254 = shl(UInt<4>(0hd), 3) node _T_1255 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1254) connect Queue10_UInt8.io.enq.bits, _T_1255 node _T_1256 = eq(UInt<1>(0h1), idx_13) when _T_1256 : node _T_1257 = shl(UInt<4>(0hd), 3) node _T_1258 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1257) connect Queue10_UInt8_1.io.enq.bits, _T_1258 node _T_1259 = eq(UInt<2>(0h2), idx_13) when _T_1259 : node _T_1260 = shl(UInt<4>(0hd), 3) node _T_1261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1260) connect Queue10_UInt8_2.io.enq.bits, _T_1261 node _T_1262 = eq(UInt<2>(0h3), idx_13) when _T_1262 : node _T_1263 = shl(UInt<4>(0hd), 3) node _T_1264 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1263) connect Queue10_UInt8_3.io.enq.bits, _T_1264 node _T_1265 = eq(UInt<3>(0h4), idx_13) when _T_1265 : node _T_1266 = shl(UInt<4>(0hd), 3) node _T_1267 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1266) connect Queue10_UInt8_4.io.enq.bits, _T_1267 node _T_1268 = eq(UInt<3>(0h5), idx_13) when _T_1268 : node _T_1269 = shl(UInt<4>(0hd), 3) node _T_1270 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1269) connect Queue10_UInt8_5.io.enq.bits, _T_1270 node _T_1271 = eq(UInt<3>(0h6), idx_13) when _T_1271 : node _T_1272 = shl(UInt<4>(0hd), 3) node _T_1273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1272) connect Queue10_UInt8_6.io.enq.bits, _T_1273 node _T_1274 = eq(UInt<3>(0h7), idx_13) when _T_1274 : node _T_1275 = shl(UInt<4>(0hd), 3) node _T_1276 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1275) connect Queue10_UInt8_7.io.enq.bits, _T_1276 node _T_1277 = eq(UInt<4>(0h8), idx_13) when _T_1277 : node _T_1278 = shl(UInt<4>(0hd), 3) node _T_1279 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1278) connect Queue10_UInt8_8.io.enq.bits, _T_1279 node _T_1280 = eq(UInt<4>(0h9), idx_13) when _T_1280 : node _T_1281 = shl(UInt<4>(0hd), 3) node _T_1282 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1281) connect Queue10_UInt8_9.io.enq.bits, _T_1282 node _T_1283 = eq(UInt<4>(0ha), idx_13) when _T_1283 : node _T_1284 = shl(UInt<4>(0hd), 3) node _T_1285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1284) connect Queue10_UInt8_10.io.enq.bits, _T_1285 node _T_1286 = eq(UInt<4>(0hb), idx_13) when _T_1286 : node _T_1287 = shl(UInt<4>(0hd), 3) node _T_1288 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1287) connect Queue10_UInt8_11.io.enq.bits, _T_1288 node _T_1289 = eq(UInt<4>(0hc), idx_13) when _T_1289 : node _T_1290 = shl(UInt<4>(0hd), 3) node _T_1291 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1290) connect Queue10_UInt8_12.io.enq.bits, _T_1291 node _T_1292 = eq(UInt<4>(0hd), idx_13) when _T_1292 : node _T_1293 = shl(UInt<4>(0hd), 3) node _T_1294 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1293) connect Queue10_UInt8_13.io.enq.bits, _T_1294 node _T_1295 = eq(UInt<4>(0he), idx_13) when _T_1295 : node _T_1296 = shl(UInt<4>(0hd), 3) node _T_1297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1296) connect Queue10_UInt8_14.io.enq.bits, _T_1297 node _T_1298 = eq(UInt<4>(0hf), idx_13) when _T_1298 : node _T_1299 = shl(UInt<4>(0hd), 3) node _T_1300 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1299) connect Queue10_UInt8_15.io.enq.bits, _T_1300 node _T_1301 = eq(UInt<5>(0h10), idx_13) when _T_1301 : node _T_1302 = shl(UInt<4>(0hd), 3) node _T_1303 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1302) connect Queue10_UInt8_16.io.enq.bits, _T_1303 node _T_1304 = eq(UInt<5>(0h11), idx_13) when _T_1304 : node _T_1305 = shl(UInt<4>(0hd), 3) node _T_1306 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1305) connect Queue10_UInt8_17.io.enq.bits, _T_1306 node _T_1307 = eq(UInt<5>(0h12), idx_13) when _T_1307 : node _T_1308 = shl(UInt<4>(0hd), 3) node _T_1309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1308) connect Queue10_UInt8_18.io.enq.bits, _T_1309 node _T_1310 = eq(UInt<5>(0h13), idx_13) when _T_1310 : node _T_1311 = shl(UInt<4>(0hd), 3) node _T_1312 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1311) connect Queue10_UInt8_19.io.enq.bits, _T_1312 node _T_1313 = eq(UInt<5>(0h14), idx_13) when _T_1313 : node _T_1314 = shl(UInt<4>(0hd), 3) node _T_1315 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1314) connect Queue10_UInt8_20.io.enq.bits, _T_1315 node _T_1316 = eq(UInt<5>(0h15), idx_13) when _T_1316 : node _T_1317 = shl(UInt<4>(0hd), 3) node _T_1318 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1317) connect Queue10_UInt8_21.io.enq.bits, _T_1318 node _T_1319 = eq(UInt<5>(0h16), idx_13) when _T_1319 : node _T_1320 = shl(UInt<4>(0hd), 3) node _T_1321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1320) connect Queue10_UInt8_22.io.enq.bits, _T_1321 node _T_1322 = eq(UInt<5>(0h17), idx_13) when _T_1322 : node _T_1323 = shl(UInt<4>(0hd), 3) node _T_1324 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1323) connect Queue10_UInt8_23.io.enq.bits, _T_1324 node _T_1325 = eq(UInt<5>(0h18), idx_13) when _T_1325 : node _T_1326 = shl(UInt<4>(0hd), 3) node _T_1327 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1326) connect Queue10_UInt8_24.io.enq.bits, _T_1327 node _T_1328 = eq(UInt<5>(0h19), idx_13) when _T_1328 : node _T_1329 = shl(UInt<4>(0hd), 3) node _T_1330 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1329) connect Queue10_UInt8_25.io.enq.bits, _T_1330 node _T_1331 = eq(UInt<5>(0h1a), idx_13) when _T_1331 : node _T_1332 = shl(UInt<4>(0hd), 3) node _T_1333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1332) connect Queue10_UInt8_26.io.enq.bits, _T_1333 node _T_1334 = eq(UInt<5>(0h1b), idx_13) when _T_1334 : node _T_1335 = shl(UInt<4>(0hd), 3) node _T_1336 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1335) connect Queue10_UInt8_27.io.enq.bits, _T_1336 node _T_1337 = eq(UInt<5>(0h1c), idx_13) when _T_1337 : node _T_1338 = shl(UInt<4>(0hd), 3) node _T_1339 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1338) connect Queue10_UInt8_28.io.enq.bits, _T_1339 node _T_1340 = eq(UInt<5>(0h1d), idx_13) when _T_1340 : node _T_1341 = shl(UInt<4>(0hd), 3) node _T_1342 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1341) connect Queue10_UInt8_29.io.enq.bits, _T_1342 node _T_1343 = eq(UInt<5>(0h1e), idx_13) when _T_1343 : node _T_1344 = shl(UInt<4>(0hd), 3) node _T_1345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1344) connect Queue10_UInt8_30.io.enq.bits, _T_1345 node _T_1346 = eq(UInt<5>(0h1f), idx_13) when _T_1346 : node _T_1347 = shl(UInt<4>(0hd), 3) node _T_1348 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1347) connect Queue10_UInt8_31.io.enq.bits, _T_1348 node _idx_T_14 = add(write_start_index, UInt<4>(0he)) node idx_14 = rem(_idx_T_14, UInt<6>(0h20)) node _T_1349 = eq(UInt<1>(0h0), idx_14) when _T_1349 : node _T_1350 = shl(UInt<4>(0he), 3) node _T_1351 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1350) connect Queue10_UInt8.io.enq.bits, _T_1351 node _T_1352 = eq(UInt<1>(0h1), idx_14) when _T_1352 : node _T_1353 = shl(UInt<4>(0he), 3) node _T_1354 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1353) connect Queue10_UInt8_1.io.enq.bits, _T_1354 node _T_1355 = eq(UInt<2>(0h2), idx_14) when _T_1355 : node _T_1356 = shl(UInt<4>(0he), 3) node _T_1357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1356) connect Queue10_UInt8_2.io.enq.bits, _T_1357 node _T_1358 = eq(UInt<2>(0h3), idx_14) when _T_1358 : node _T_1359 = shl(UInt<4>(0he), 3) node _T_1360 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1359) connect Queue10_UInt8_3.io.enq.bits, _T_1360 node _T_1361 = eq(UInt<3>(0h4), idx_14) when _T_1361 : node _T_1362 = shl(UInt<4>(0he), 3) node _T_1363 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1362) connect Queue10_UInt8_4.io.enq.bits, _T_1363 node _T_1364 = eq(UInt<3>(0h5), idx_14) when _T_1364 : node _T_1365 = shl(UInt<4>(0he), 3) node _T_1366 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1365) connect Queue10_UInt8_5.io.enq.bits, _T_1366 node _T_1367 = eq(UInt<3>(0h6), idx_14) when _T_1367 : node _T_1368 = shl(UInt<4>(0he), 3) node _T_1369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1368) connect Queue10_UInt8_6.io.enq.bits, _T_1369 node _T_1370 = eq(UInt<3>(0h7), idx_14) when _T_1370 : node _T_1371 = shl(UInt<4>(0he), 3) node _T_1372 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1371) connect Queue10_UInt8_7.io.enq.bits, _T_1372 node _T_1373 = eq(UInt<4>(0h8), idx_14) when _T_1373 : node _T_1374 = shl(UInt<4>(0he), 3) node _T_1375 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1374) connect Queue10_UInt8_8.io.enq.bits, _T_1375 node _T_1376 = eq(UInt<4>(0h9), idx_14) when _T_1376 : node _T_1377 = shl(UInt<4>(0he), 3) node _T_1378 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1377) connect Queue10_UInt8_9.io.enq.bits, _T_1378 node _T_1379 = eq(UInt<4>(0ha), idx_14) when _T_1379 : node _T_1380 = shl(UInt<4>(0he), 3) node _T_1381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1380) connect Queue10_UInt8_10.io.enq.bits, _T_1381 node _T_1382 = eq(UInt<4>(0hb), idx_14) when _T_1382 : node _T_1383 = shl(UInt<4>(0he), 3) node _T_1384 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1383) connect Queue10_UInt8_11.io.enq.bits, _T_1384 node _T_1385 = eq(UInt<4>(0hc), idx_14) when _T_1385 : node _T_1386 = shl(UInt<4>(0he), 3) node _T_1387 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1386) connect Queue10_UInt8_12.io.enq.bits, _T_1387 node _T_1388 = eq(UInt<4>(0hd), idx_14) when _T_1388 : node _T_1389 = shl(UInt<4>(0he), 3) node _T_1390 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1389) connect Queue10_UInt8_13.io.enq.bits, _T_1390 node _T_1391 = eq(UInt<4>(0he), idx_14) when _T_1391 : node _T_1392 = shl(UInt<4>(0he), 3) node _T_1393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1392) connect Queue10_UInt8_14.io.enq.bits, _T_1393 node _T_1394 = eq(UInt<4>(0hf), idx_14) when _T_1394 : node _T_1395 = shl(UInt<4>(0he), 3) node _T_1396 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1395) connect Queue10_UInt8_15.io.enq.bits, _T_1396 node _T_1397 = eq(UInt<5>(0h10), idx_14) when _T_1397 : node _T_1398 = shl(UInt<4>(0he), 3) node _T_1399 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1398) connect Queue10_UInt8_16.io.enq.bits, _T_1399 node _T_1400 = eq(UInt<5>(0h11), idx_14) when _T_1400 : node _T_1401 = shl(UInt<4>(0he), 3) node _T_1402 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1401) connect Queue10_UInt8_17.io.enq.bits, _T_1402 node _T_1403 = eq(UInt<5>(0h12), idx_14) when _T_1403 : node _T_1404 = shl(UInt<4>(0he), 3) node _T_1405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1404) connect Queue10_UInt8_18.io.enq.bits, _T_1405 node _T_1406 = eq(UInt<5>(0h13), idx_14) when _T_1406 : node _T_1407 = shl(UInt<4>(0he), 3) node _T_1408 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1407) connect Queue10_UInt8_19.io.enq.bits, _T_1408 node _T_1409 = eq(UInt<5>(0h14), idx_14) when _T_1409 : node _T_1410 = shl(UInt<4>(0he), 3) node _T_1411 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1410) connect Queue10_UInt8_20.io.enq.bits, _T_1411 node _T_1412 = eq(UInt<5>(0h15), idx_14) when _T_1412 : node _T_1413 = shl(UInt<4>(0he), 3) node _T_1414 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1413) connect Queue10_UInt8_21.io.enq.bits, _T_1414 node _T_1415 = eq(UInt<5>(0h16), idx_14) when _T_1415 : node _T_1416 = shl(UInt<4>(0he), 3) node _T_1417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1416) connect Queue10_UInt8_22.io.enq.bits, _T_1417 node _T_1418 = eq(UInt<5>(0h17), idx_14) when _T_1418 : node _T_1419 = shl(UInt<4>(0he), 3) node _T_1420 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1419) connect Queue10_UInt8_23.io.enq.bits, _T_1420 node _T_1421 = eq(UInt<5>(0h18), idx_14) when _T_1421 : node _T_1422 = shl(UInt<4>(0he), 3) node _T_1423 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1422) connect Queue10_UInt8_24.io.enq.bits, _T_1423 node _T_1424 = eq(UInt<5>(0h19), idx_14) when _T_1424 : node _T_1425 = shl(UInt<4>(0he), 3) node _T_1426 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1425) connect Queue10_UInt8_25.io.enq.bits, _T_1426 node _T_1427 = eq(UInt<5>(0h1a), idx_14) when _T_1427 : node _T_1428 = shl(UInt<4>(0he), 3) node _T_1429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1428) connect Queue10_UInt8_26.io.enq.bits, _T_1429 node _T_1430 = eq(UInt<5>(0h1b), idx_14) when _T_1430 : node _T_1431 = shl(UInt<4>(0he), 3) node _T_1432 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1431) connect Queue10_UInt8_27.io.enq.bits, _T_1432 node _T_1433 = eq(UInt<5>(0h1c), idx_14) when _T_1433 : node _T_1434 = shl(UInt<4>(0he), 3) node _T_1435 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1434) connect Queue10_UInt8_28.io.enq.bits, _T_1435 node _T_1436 = eq(UInt<5>(0h1d), idx_14) when _T_1436 : node _T_1437 = shl(UInt<4>(0he), 3) node _T_1438 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1437) connect Queue10_UInt8_29.io.enq.bits, _T_1438 node _T_1439 = eq(UInt<5>(0h1e), idx_14) when _T_1439 : node _T_1440 = shl(UInt<4>(0he), 3) node _T_1441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1440) connect Queue10_UInt8_30.io.enq.bits, _T_1441 node _T_1442 = eq(UInt<5>(0h1f), idx_14) when _T_1442 : node _T_1443 = shl(UInt<4>(0he), 3) node _T_1444 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1443) connect Queue10_UInt8_31.io.enq.bits, _T_1444 node _idx_T_15 = add(write_start_index, UInt<4>(0hf)) node idx_15 = rem(_idx_T_15, UInt<6>(0h20)) node _T_1445 = eq(UInt<1>(0h0), idx_15) when _T_1445 : node _T_1446 = shl(UInt<4>(0hf), 3) node _T_1447 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1446) connect Queue10_UInt8.io.enq.bits, _T_1447 node _T_1448 = eq(UInt<1>(0h1), idx_15) when _T_1448 : node _T_1449 = shl(UInt<4>(0hf), 3) node _T_1450 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1449) connect Queue10_UInt8_1.io.enq.bits, _T_1450 node _T_1451 = eq(UInt<2>(0h2), idx_15) when _T_1451 : node _T_1452 = shl(UInt<4>(0hf), 3) node _T_1453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1452) connect Queue10_UInt8_2.io.enq.bits, _T_1453 node _T_1454 = eq(UInt<2>(0h3), idx_15) when _T_1454 : node _T_1455 = shl(UInt<4>(0hf), 3) node _T_1456 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1455) connect Queue10_UInt8_3.io.enq.bits, _T_1456 node _T_1457 = eq(UInt<3>(0h4), idx_15) when _T_1457 : node _T_1458 = shl(UInt<4>(0hf), 3) node _T_1459 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1458) connect Queue10_UInt8_4.io.enq.bits, _T_1459 node _T_1460 = eq(UInt<3>(0h5), idx_15) when _T_1460 : node _T_1461 = shl(UInt<4>(0hf), 3) node _T_1462 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1461) connect Queue10_UInt8_5.io.enq.bits, _T_1462 node _T_1463 = eq(UInt<3>(0h6), idx_15) when _T_1463 : node _T_1464 = shl(UInt<4>(0hf), 3) node _T_1465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1464) connect Queue10_UInt8_6.io.enq.bits, _T_1465 node _T_1466 = eq(UInt<3>(0h7), idx_15) when _T_1466 : node _T_1467 = shl(UInt<4>(0hf), 3) node _T_1468 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1467) connect Queue10_UInt8_7.io.enq.bits, _T_1468 node _T_1469 = eq(UInt<4>(0h8), idx_15) when _T_1469 : node _T_1470 = shl(UInt<4>(0hf), 3) node _T_1471 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1470) connect Queue10_UInt8_8.io.enq.bits, _T_1471 node _T_1472 = eq(UInt<4>(0h9), idx_15) when _T_1472 : node _T_1473 = shl(UInt<4>(0hf), 3) node _T_1474 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1473) connect Queue10_UInt8_9.io.enq.bits, _T_1474 node _T_1475 = eq(UInt<4>(0ha), idx_15) when _T_1475 : node _T_1476 = shl(UInt<4>(0hf), 3) node _T_1477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1476) connect Queue10_UInt8_10.io.enq.bits, _T_1477 node _T_1478 = eq(UInt<4>(0hb), idx_15) when _T_1478 : node _T_1479 = shl(UInt<4>(0hf), 3) node _T_1480 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1479) connect Queue10_UInt8_11.io.enq.bits, _T_1480 node _T_1481 = eq(UInt<4>(0hc), idx_15) when _T_1481 : node _T_1482 = shl(UInt<4>(0hf), 3) node _T_1483 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1482) connect Queue10_UInt8_12.io.enq.bits, _T_1483 node _T_1484 = eq(UInt<4>(0hd), idx_15) when _T_1484 : node _T_1485 = shl(UInt<4>(0hf), 3) node _T_1486 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1485) connect Queue10_UInt8_13.io.enq.bits, _T_1486 node _T_1487 = eq(UInt<4>(0he), idx_15) when _T_1487 : node _T_1488 = shl(UInt<4>(0hf), 3) node _T_1489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1488) connect Queue10_UInt8_14.io.enq.bits, _T_1489 node _T_1490 = eq(UInt<4>(0hf), idx_15) when _T_1490 : node _T_1491 = shl(UInt<4>(0hf), 3) node _T_1492 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1491) connect Queue10_UInt8_15.io.enq.bits, _T_1492 node _T_1493 = eq(UInt<5>(0h10), idx_15) when _T_1493 : node _T_1494 = shl(UInt<4>(0hf), 3) node _T_1495 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1494) connect Queue10_UInt8_16.io.enq.bits, _T_1495 node _T_1496 = eq(UInt<5>(0h11), idx_15) when _T_1496 : node _T_1497 = shl(UInt<4>(0hf), 3) node _T_1498 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1497) connect Queue10_UInt8_17.io.enq.bits, _T_1498 node _T_1499 = eq(UInt<5>(0h12), idx_15) when _T_1499 : node _T_1500 = shl(UInt<4>(0hf), 3) node _T_1501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1500) connect Queue10_UInt8_18.io.enq.bits, _T_1501 node _T_1502 = eq(UInt<5>(0h13), idx_15) when _T_1502 : node _T_1503 = shl(UInt<4>(0hf), 3) node _T_1504 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1503) connect Queue10_UInt8_19.io.enq.bits, _T_1504 node _T_1505 = eq(UInt<5>(0h14), idx_15) when _T_1505 : node _T_1506 = shl(UInt<4>(0hf), 3) node _T_1507 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1506) connect Queue10_UInt8_20.io.enq.bits, _T_1507 node _T_1508 = eq(UInt<5>(0h15), idx_15) when _T_1508 : node _T_1509 = shl(UInt<4>(0hf), 3) node _T_1510 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1509) connect Queue10_UInt8_21.io.enq.bits, _T_1510 node _T_1511 = eq(UInt<5>(0h16), idx_15) when _T_1511 : node _T_1512 = shl(UInt<4>(0hf), 3) node _T_1513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1512) connect Queue10_UInt8_22.io.enq.bits, _T_1513 node _T_1514 = eq(UInt<5>(0h17), idx_15) when _T_1514 : node _T_1515 = shl(UInt<4>(0hf), 3) node _T_1516 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1515) connect Queue10_UInt8_23.io.enq.bits, _T_1516 node _T_1517 = eq(UInt<5>(0h18), idx_15) when _T_1517 : node _T_1518 = shl(UInt<4>(0hf), 3) node _T_1519 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1518) connect Queue10_UInt8_24.io.enq.bits, _T_1519 node _T_1520 = eq(UInt<5>(0h19), idx_15) when _T_1520 : node _T_1521 = shl(UInt<4>(0hf), 3) node _T_1522 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1521) connect Queue10_UInt8_25.io.enq.bits, _T_1522 node _T_1523 = eq(UInt<5>(0h1a), idx_15) when _T_1523 : node _T_1524 = shl(UInt<4>(0hf), 3) node _T_1525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1524) connect Queue10_UInt8_26.io.enq.bits, _T_1525 node _T_1526 = eq(UInt<5>(0h1b), idx_15) when _T_1526 : node _T_1527 = shl(UInt<4>(0hf), 3) node _T_1528 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1527) connect Queue10_UInt8_27.io.enq.bits, _T_1528 node _T_1529 = eq(UInt<5>(0h1c), idx_15) when _T_1529 : node _T_1530 = shl(UInt<4>(0hf), 3) node _T_1531 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1530) connect Queue10_UInt8_28.io.enq.bits, _T_1531 node _T_1532 = eq(UInt<5>(0h1d), idx_15) when _T_1532 : node _T_1533 = shl(UInt<4>(0hf), 3) node _T_1534 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1533) connect Queue10_UInt8_29.io.enq.bits, _T_1534 node _T_1535 = eq(UInt<5>(0h1e), idx_15) when _T_1535 : node _T_1536 = shl(UInt<4>(0hf), 3) node _T_1537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1536) connect Queue10_UInt8_30.io.enq.bits, _T_1537 node _T_1538 = eq(UInt<5>(0h1f), idx_15) when _T_1538 : node _T_1539 = shl(UInt<4>(0hf), 3) node _T_1540 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1539) connect Queue10_UInt8_31.io.enq.bits, _T_1540 node _idx_T_16 = add(write_start_index, UInt<5>(0h10)) node idx_16 = rem(_idx_T_16, UInt<6>(0h20)) node _T_1541 = eq(UInt<1>(0h0), idx_16) when _T_1541 : node _T_1542 = shl(UInt<5>(0h10), 3) node _T_1543 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1542) connect Queue10_UInt8.io.enq.bits, _T_1543 node _T_1544 = eq(UInt<1>(0h1), idx_16) when _T_1544 : node _T_1545 = shl(UInt<5>(0h10), 3) node _T_1546 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1545) connect Queue10_UInt8_1.io.enq.bits, _T_1546 node _T_1547 = eq(UInt<2>(0h2), idx_16) when _T_1547 : node _T_1548 = shl(UInt<5>(0h10), 3) node _T_1549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1548) connect Queue10_UInt8_2.io.enq.bits, _T_1549 node _T_1550 = eq(UInt<2>(0h3), idx_16) when _T_1550 : node _T_1551 = shl(UInt<5>(0h10), 3) node _T_1552 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1551) connect Queue10_UInt8_3.io.enq.bits, _T_1552 node _T_1553 = eq(UInt<3>(0h4), idx_16) when _T_1553 : node _T_1554 = shl(UInt<5>(0h10), 3) node _T_1555 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1554) connect Queue10_UInt8_4.io.enq.bits, _T_1555 node _T_1556 = eq(UInt<3>(0h5), idx_16) when _T_1556 : node _T_1557 = shl(UInt<5>(0h10), 3) node _T_1558 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1557) connect Queue10_UInt8_5.io.enq.bits, _T_1558 node _T_1559 = eq(UInt<3>(0h6), idx_16) when _T_1559 : node _T_1560 = shl(UInt<5>(0h10), 3) node _T_1561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1560) connect Queue10_UInt8_6.io.enq.bits, _T_1561 node _T_1562 = eq(UInt<3>(0h7), idx_16) when _T_1562 : node _T_1563 = shl(UInt<5>(0h10), 3) node _T_1564 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1563) connect Queue10_UInt8_7.io.enq.bits, _T_1564 node _T_1565 = eq(UInt<4>(0h8), idx_16) when _T_1565 : node _T_1566 = shl(UInt<5>(0h10), 3) node _T_1567 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1566) connect Queue10_UInt8_8.io.enq.bits, _T_1567 node _T_1568 = eq(UInt<4>(0h9), idx_16) when _T_1568 : node _T_1569 = shl(UInt<5>(0h10), 3) node _T_1570 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1569) connect Queue10_UInt8_9.io.enq.bits, _T_1570 node _T_1571 = eq(UInt<4>(0ha), idx_16) when _T_1571 : node _T_1572 = shl(UInt<5>(0h10), 3) node _T_1573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1572) connect Queue10_UInt8_10.io.enq.bits, _T_1573 node _T_1574 = eq(UInt<4>(0hb), idx_16) when _T_1574 : node _T_1575 = shl(UInt<5>(0h10), 3) node _T_1576 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1575) connect Queue10_UInt8_11.io.enq.bits, _T_1576 node _T_1577 = eq(UInt<4>(0hc), idx_16) when _T_1577 : node _T_1578 = shl(UInt<5>(0h10), 3) node _T_1579 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1578) connect Queue10_UInt8_12.io.enq.bits, _T_1579 node _T_1580 = eq(UInt<4>(0hd), idx_16) when _T_1580 : node _T_1581 = shl(UInt<5>(0h10), 3) node _T_1582 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1581) connect Queue10_UInt8_13.io.enq.bits, _T_1582 node _T_1583 = eq(UInt<4>(0he), idx_16) when _T_1583 : node _T_1584 = shl(UInt<5>(0h10), 3) node _T_1585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1584) connect Queue10_UInt8_14.io.enq.bits, _T_1585 node _T_1586 = eq(UInt<4>(0hf), idx_16) when _T_1586 : node _T_1587 = shl(UInt<5>(0h10), 3) node _T_1588 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1587) connect Queue10_UInt8_15.io.enq.bits, _T_1588 node _T_1589 = eq(UInt<5>(0h10), idx_16) when _T_1589 : node _T_1590 = shl(UInt<5>(0h10), 3) node _T_1591 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1590) connect Queue10_UInt8_16.io.enq.bits, _T_1591 node _T_1592 = eq(UInt<5>(0h11), idx_16) when _T_1592 : node _T_1593 = shl(UInt<5>(0h10), 3) node _T_1594 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1593) connect Queue10_UInt8_17.io.enq.bits, _T_1594 node _T_1595 = eq(UInt<5>(0h12), idx_16) when _T_1595 : node _T_1596 = shl(UInt<5>(0h10), 3) node _T_1597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1596) connect Queue10_UInt8_18.io.enq.bits, _T_1597 node _T_1598 = eq(UInt<5>(0h13), idx_16) when _T_1598 : node _T_1599 = shl(UInt<5>(0h10), 3) node _T_1600 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1599) connect Queue10_UInt8_19.io.enq.bits, _T_1600 node _T_1601 = eq(UInt<5>(0h14), idx_16) when _T_1601 : node _T_1602 = shl(UInt<5>(0h10), 3) node _T_1603 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1602) connect Queue10_UInt8_20.io.enq.bits, _T_1603 node _T_1604 = eq(UInt<5>(0h15), idx_16) when _T_1604 : node _T_1605 = shl(UInt<5>(0h10), 3) node _T_1606 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1605) connect Queue10_UInt8_21.io.enq.bits, _T_1606 node _T_1607 = eq(UInt<5>(0h16), idx_16) when _T_1607 : node _T_1608 = shl(UInt<5>(0h10), 3) node _T_1609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1608) connect Queue10_UInt8_22.io.enq.bits, _T_1609 node _T_1610 = eq(UInt<5>(0h17), idx_16) when _T_1610 : node _T_1611 = shl(UInt<5>(0h10), 3) node _T_1612 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1611) connect Queue10_UInt8_23.io.enq.bits, _T_1612 node _T_1613 = eq(UInt<5>(0h18), idx_16) when _T_1613 : node _T_1614 = shl(UInt<5>(0h10), 3) node _T_1615 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1614) connect Queue10_UInt8_24.io.enq.bits, _T_1615 node _T_1616 = eq(UInt<5>(0h19), idx_16) when _T_1616 : node _T_1617 = shl(UInt<5>(0h10), 3) node _T_1618 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1617) connect Queue10_UInt8_25.io.enq.bits, _T_1618 node _T_1619 = eq(UInt<5>(0h1a), idx_16) when _T_1619 : node _T_1620 = shl(UInt<5>(0h10), 3) node _T_1621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1620) connect Queue10_UInt8_26.io.enq.bits, _T_1621 node _T_1622 = eq(UInt<5>(0h1b), idx_16) when _T_1622 : node _T_1623 = shl(UInt<5>(0h10), 3) node _T_1624 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1623) connect Queue10_UInt8_27.io.enq.bits, _T_1624 node _T_1625 = eq(UInt<5>(0h1c), idx_16) when _T_1625 : node _T_1626 = shl(UInt<5>(0h10), 3) node _T_1627 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1626) connect Queue10_UInt8_28.io.enq.bits, _T_1627 node _T_1628 = eq(UInt<5>(0h1d), idx_16) when _T_1628 : node _T_1629 = shl(UInt<5>(0h10), 3) node _T_1630 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1629) connect Queue10_UInt8_29.io.enq.bits, _T_1630 node _T_1631 = eq(UInt<5>(0h1e), idx_16) when _T_1631 : node _T_1632 = shl(UInt<5>(0h10), 3) node _T_1633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1632) connect Queue10_UInt8_30.io.enq.bits, _T_1633 node _T_1634 = eq(UInt<5>(0h1f), idx_16) when _T_1634 : node _T_1635 = shl(UInt<5>(0h10), 3) node _T_1636 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1635) connect Queue10_UInt8_31.io.enq.bits, _T_1636 node _idx_T_17 = add(write_start_index, UInt<5>(0h11)) node idx_17 = rem(_idx_T_17, UInt<6>(0h20)) node _T_1637 = eq(UInt<1>(0h0), idx_17) when _T_1637 : node _T_1638 = shl(UInt<5>(0h11), 3) node _T_1639 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1638) connect Queue10_UInt8.io.enq.bits, _T_1639 node _T_1640 = eq(UInt<1>(0h1), idx_17) when _T_1640 : node _T_1641 = shl(UInt<5>(0h11), 3) node _T_1642 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1641) connect Queue10_UInt8_1.io.enq.bits, _T_1642 node _T_1643 = eq(UInt<2>(0h2), idx_17) when _T_1643 : node _T_1644 = shl(UInt<5>(0h11), 3) node _T_1645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1644) connect Queue10_UInt8_2.io.enq.bits, _T_1645 node _T_1646 = eq(UInt<2>(0h3), idx_17) when _T_1646 : node _T_1647 = shl(UInt<5>(0h11), 3) node _T_1648 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1647) connect Queue10_UInt8_3.io.enq.bits, _T_1648 node _T_1649 = eq(UInt<3>(0h4), idx_17) when _T_1649 : node _T_1650 = shl(UInt<5>(0h11), 3) node _T_1651 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1650) connect Queue10_UInt8_4.io.enq.bits, _T_1651 node _T_1652 = eq(UInt<3>(0h5), idx_17) when _T_1652 : node _T_1653 = shl(UInt<5>(0h11), 3) node _T_1654 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1653) connect Queue10_UInt8_5.io.enq.bits, _T_1654 node _T_1655 = eq(UInt<3>(0h6), idx_17) when _T_1655 : node _T_1656 = shl(UInt<5>(0h11), 3) node _T_1657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1656) connect Queue10_UInt8_6.io.enq.bits, _T_1657 node _T_1658 = eq(UInt<3>(0h7), idx_17) when _T_1658 : node _T_1659 = shl(UInt<5>(0h11), 3) node _T_1660 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1659) connect Queue10_UInt8_7.io.enq.bits, _T_1660 node _T_1661 = eq(UInt<4>(0h8), idx_17) when _T_1661 : node _T_1662 = shl(UInt<5>(0h11), 3) node _T_1663 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1662) connect Queue10_UInt8_8.io.enq.bits, _T_1663 node _T_1664 = eq(UInt<4>(0h9), idx_17) when _T_1664 : node _T_1665 = shl(UInt<5>(0h11), 3) node _T_1666 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1665) connect Queue10_UInt8_9.io.enq.bits, _T_1666 node _T_1667 = eq(UInt<4>(0ha), idx_17) when _T_1667 : node _T_1668 = shl(UInt<5>(0h11), 3) node _T_1669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1668) connect Queue10_UInt8_10.io.enq.bits, _T_1669 node _T_1670 = eq(UInt<4>(0hb), idx_17) when _T_1670 : node _T_1671 = shl(UInt<5>(0h11), 3) node _T_1672 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1671) connect Queue10_UInt8_11.io.enq.bits, _T_1672 node _T_1673 = eq(UInt<4>(0hc), idx_17) when _T_1673 : node _T_1674 = shl(UInt<5>(0h11), 3) node _T_1675 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1674) connect Queue10_UInt8_12.io.enq.bits, _T_1675 node _T_1676 = eq(UInt<4>(0hd), idx_17) when _T_1676 : node _T_1677 = shl(UInt<5>(0h11), 3) node _T_1678 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1677) connect Queue10_UInt8_13.io.enq.bits, _T_1678 node _T_1679 = eq(UInt<4>(0he), idx_17) when _T_1679 : node _T_1680 = shl(UInt<5>(0h11), 3) node _T_1681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1680) connect Queue10_UInt8_14.io.enq.bits, _T_1681 node _T_1682 = eq(UInt<4>(0hf), idx_17) when _T_1682 : node _T_1683 = shl(UInt<5>(0h11), 3) node _T_1684 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1683) connect Queue10_UInt8_15.io.enq.bits, _T_1684 node _T_1685 = eq(UInt<5>(0h10), idx_17) when _T_1685 : node _T_1686 = shl(UInt<5>(0h11), 3) node _T_1687 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1686) connect Queue10_UInt8_16.io.enq.bits, _T_1687 node _T_1688 = eq(UInt<5>(0h11), idx_17) when _T_1688 : node _T_1689 = shl(UInt<5>(0h11), 3) node _T_1690 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1689) connect Queue10_UInt8_17.io.enq.bits, _T_1690 node _T_1691 = eq(UInt<5>(0h12), idx_17) when _T_1691 : node _T_1692 = shl(UInt<5>(0h11), 3) node _T_1693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1692) connect Queue10_UInt8_18.io.enq.bits, _T_1693 node _T_1694 = eq(UInt<5>(0h13), idx_17) when _T_1694 : node _T_1695 = shl(UInt<5>(0h11), 3) node _T_1696 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1695) connect Queue10_UInt8_19.io.enq.bits, _T_1696 node _T_1697 = eq(UInt<5>(0h14), idx_17) when _T_1697 : node _T_1698 = shl(UInt<5>(0h11), 3) node _T_1699 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1698) connect Queue10_UInt8_20.io.enq.bits, _T_1699 node _T_1700 = eq(UInt<5>(0h15), idx_17) when _T_1700 : node _T_1701 = shl(UInt<5>(0h11), 3) node _T_1702 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1701) connect Queue10_UInt8_21.io.enq.bits, _T_1702 node _T_1703 = eq(UInt<5>(0h16), idx_17) when _T_1703 : node _T_1704 = shl(UInt<5>(0h11), 3) node _T_1705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1704) connect Queue10_UInt8_22.io.enq.bits, _T_1705 node _T_1706 = eq(UInt<5>(0h17), idx_17) when _T_1706 : node _T_1707 = shl(UInt<5>(0h11), 3) node _T_1708 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1707) connect Queue10_UInt8_23.io.enq.bits, _T_1708 node _T_1709 = eq(UInt<5>(0h18), idx_17) when _T_1709 : node _T_1710 = shl(UInt<5>(0h11), 3) node _T_1711 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1710) connect Queue10_UInt8_24.io.enq.bits, _T_1711 node _T_1712 = eq(UInt<5>(0h19), idx_17) when _T_1712 : node _T_1713 = shl(UInt<5>(0h11), 3) node _T_1714 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1713) connect Queue10_UInt8_25.io.enq.bits, _T_1714 node _T_1715 = eq(UInt<5>(0h1a), idx_17) when _T_1715 : node _T_1716 = shl(UInt<5>(0h11), 3) node _T_1717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1716) connect Queue10_UInt8_26.io.enq.bits, _T_1717 node _T_1718 = eq(UInt<5>(0h1b), idx_17) when _T_1718 : node _T_1719 = shl(UInt<5>(0h11), 3) node _T_1720 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1719) connect Queue10_UInt8_27.io.enq.bits, _T_1720 node _T_1721 = eq(UInt<5>(0h1c), idx_17) when _T_1721 : node _T_1722 = shl(UInt<5>(0h11), 3) node _T_1723 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1722) connect Queue10_UInt8_28.io.enq.bits, _T_1723 node _T_1724 = eq(UInt<5>(0h1d), idx_17) when _T_1724 : node _T_1725 = shl(UInt<5>(0h11), 3) node _T_1726 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1725) connect Queue10_UInt8_29.io.enq.bits, _T_1726 node _T_1727 = eq(UInt<5>(0h1e), idx_17) when _T_1727 : node _T_1728 = shl(UInt<5>(0h11), 3) node _T_1729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1728) connect Queue10_UInt8_30.io.enq.bits, _T_1729 node _T_1730 = eq(UInt<5>(0h1f), idx_17) when _T_1730 : node _T_1731 = shl(UInt<5>(0h11), 3) node _T_1732 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1731) connect Queue10_UInt8_31.io.enq.bits, _T_1732 node _idx_T_18 = add(write_start_index, UInt<5>(0h12)) node idx_18 = rem(_idx_T_18, UInt<6>(0h20)) node _T_1733 = eq(UInt<1>(0h0), idx_18) when _T_1733 : node _T_1734 = shl(UInt<5>(0h12), 3) node _T_1735 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1734) connect Queue10_UInt8.io.enq.bits, _T_1735 node _T_1736 = eq(UInt<1>(0h1), idx_18) when _T_1736 : node _T_1737 = shl(UInt<5>(0h12), 3) node _T_1738 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1737) connect Queue10_UInt8_1.io.enq.bits, _T_1738 node _T_1739 = eq(UInt<2>(0h2), idx_18) when _T_1739 : node _T_1740 = shl(UInt<5>(0h12), 3) node _T_1741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1740) connect Queue10_UInt8_2.io.enq.bits, _T_1741 node _T_1742 = eq(UInt<2>(0h3), idx_18) when _T_1742 : node _T_1743 = shl(UInt<5>(0h12), 3) node _T_1744 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1743) connect Queue10_UInt8_3.io.enq.bits, _T_1744 node _T_1745 = eq(UInt<3>(0h4), idx_18) when _T_1745 : node _T_1746 = shl(UInt<5>(0h12), 3) node _T_1747 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1746) connect Queue10_UInt8_4.io.enq.bits, _T_1747 node _T_1748 = eq(UInt<3>(0h5), idx_18) when _T_1748 : node _T_1749 = shl(UInt<5>(0h12), 3) node _T_1750 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1749) connect Queue10_UInt8_5.io.enq.bits, _T_1750 node _T_1751 = eq(UInt<3>(0h6), idx_18) when _T_1751 : node _T_1752 = shl(UInt<5>(0h12), 3) node _T_1753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1752) connect Queue10_UInt8_6.io.enq.bits, _T_1753 node _T_1754 = eq(UInt<3>(0h7), idx_18) when _T_1754 : node _T_1755 = shl(UInt<5>(0h12), 3) node _T_1756 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1755) connect Queue10_UInt8_7.io.enq.bits, _T_1756 node _T_1757 = eq(UInt<4>(0h8), idx_18) when _T_1757 : node _T_1758 = shl(UInt<5>(0h12), 3) node _T_1759 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1758) connect Queue10_UInt8_8.io.enq.bits, _T_1759 node _T_1760 = eq(UInt<4>(0h9), idx_18) when _T_1760 : node _T_1761 = shl(UInt<5>(0h12), 3) node _T_1762 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1761) connect Queue10_UInt8_9.io.enq.bits, _T_1762 node _T_1763 = eq(UInt<4>(0ha), idx_18) when _T_1763 : node _T_1764 = shl(UInt<5>(0h12), 3) node _T_1765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1764) connect Queue10_UInt8_10.io.enq.bits, _T_1765 node _T_1766 = eq(UInt<4>(0hb), idx_18) when _T_1766 : node _T_1767 = shl(UInt<5>(0h12), 3) node _T_1768 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1767) connect Queue10_UInt8_11.io.enq.bits, _T_1768 node _T_1769 = eq(UInt<4>(0hc), idx_18) when _T_1769 : node _T_1770 = shl(UInt<5>(0h12), 3) node _T_1771 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1770) connect Queue10_UInt8_12.io.enq.bits, _T_1771 node _T_1772 = eq(UInt<4>(0hd), idx_18) when _T_1772 : node _T_1773 = shl(UInt<5>(0h12), 3) node _T_1774 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1773) connect Queue10_UInt8_13.io.enq.bits, _T_1774 node _T_1775 = eq(UInt<4>(0he), idx_18) when _T_1775 : node _T_1776 = shl(UInt<5>(0h12), 3) node _T_1777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1776) connect Queue10_UInt8_14.io.enq.bits, _T_1777 node _T_1778 = eq(UInt<4>(0hf), idx_18) when _T_1778 : node _T_1779 = shl(UInt<5>(0h12), 3) node _T_1780 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1779) connect Queue10_UInt8_15.io.enq.bits, _T_1780 node _T_1781 = eq(UInt<5>(0h10), idx_18) when _T_1781 : node _T_1782 = shl(UInt<5>(0h12), 3) node _T_1783 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1782) connect Queue10_UInt8_16.io.enq.bits, _T_1783 node _T_1784 = eq(UInt<5>(0h11), idx_18) when _T_1784 : node _T_1785 = shl(UInt<5>(0h12), 3) node _T_1786 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1785) connect Queue10_UInt8_17.io.enq.bits, _T_1786 node _T_1787 = eq(UInt<5>(0h12), idx_18) when _T_1787 : node _T_1788 = shl(UInt<5>(0h12), 3) node _T_1789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1788) connect Queue10_UInt8_18.io.enq.bits, _T_1789 node _T_1790 = eq(UInt<5>(0h13), idx_18) when _T_1790 : node _T_1791 = shl(UInt<5>(0h12), 3) node _T_1792 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1791) connect Queue10_UInt8_19.io.enq.bits, _T_1792 node _T_1793 = eq(UInt<5>(0h14), idx_18) when _T_1793 : node _T_1794 = shl(UInt<5>(0h12), 3) node _T_1795 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1794) connect Queue10_UInt8_20.io.enq.bits, _T_1795 node _T_1796 = eq(UInt<5>(0h15), idx_18) when _T_1796 : node _T_1797 = shl(UInt<5>(0h12), 3) node _T_1798 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1797) connect Queue10_UInt8_21.io.enq.bits, _T_1798 node _T_1799 = eq(UInt<5>(0h16), idx_18) when _T_1799 : node _T_1800 = shl(UInt<5>(0h12), 3) node _T_1801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1800) connect Queue10_UInt8_22.io.enq.bits, _T_1801 node _T_1802 = eq(UInt<5>(0h17), idx_18) when _T_1802 : node _T_1803 = shl(UInt<5>(0h12), 3) node _T_1804 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1803) connect Queue10_UInt8_23.io.enq.bits, _T_1804 node _T_1805 = eq(UInt<5>(0h18), idx_18) when _T_1805 : node _T_1806 = shl(UInt<5>(0h12), 3) node _T_1807 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1806) connect Queue10_UInt8_24.io.enq.bits, _T_1807 node _T_1808 = eq(UInt<5>(0h19), idx_18) when _T_1808 : node _T_1809 = shl(UInt<5>(0h12), 3) node _T_1810 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1809) connect Queue10_UInt8_25.io.enq.bits, _T_1810 node _T_1811 = eq(UInt<5>(0h1a), idx_18) when _T_1811 : node _T_1812 = shl(UInt<5>(0h12), 3) node _T_1813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1812) connect Queue10_UInt8_26.io.enq.bits, _T_1813 node _T_1814 = eq(UInt<5>(0h1b), idx_18) when _T_1814 : node _T_1815 = shl(UInt<5>(0h12), 3) node _T_1816 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1815) connect Queue10_UInt8_27.io.enq.bits, _T_1816 node _T_1817 = eq(UInt<5>(0h1c), idx_18) when _T_1817 : node _T_1818 = shl(UInt<5>(0h12), 3) node _T_1819 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1818) connect Queue10_UInt8_28.io.enq.bits, _T_1819 node _T_1820 = eq(UInt<5>(0h1d), idx_18) when _T_1820 : node _T_1821 = shl(UInt<5>(0h12), 3) node _T_1822 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1821) connect Queue10_UInt8_29.io.enq.bits, _T_1822 node _T_1823 = eq(UInt<5>(0h1e), idx_18) when _T_1823 : node _T_1824 = shl(UInt<5>(0h12), 3) node _T_1825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1824) connect Queue10_UInt8_30.io.enq.bits, _T_1825 node _T_1826 = eq(UInt<5>(0h1f), idx_18) when _T_1826 : node _T_1827 = shl(UInt<5>(0h12), 3) node _T_1828 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1827) connect Queue10_UInt8_31.io.enq.bits, _T_1828 node _idx_T_19 = add(write_start_index, UInt<5>(0h13)) node idx_19 = rem(_idx_T_19, UInt<6>(0h20)) node _T_1829 = eq(UInt<1>(0h0), idx_19) when _T_1829 : node _T_1830 = shl(UInt<5>(0h13), 3) node _T_1831 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1830) connect Queue10_UInt8.io.enq.bits, _T_1831 node _T_1832 = eq(UInt<1>(0h1), idx_19) when _T_1832 : node _T_1833 = shl(UInt<5>(0h13), 3) node _T_1834 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1833) connect Queue10_UInt8_1.io.enq.bits, _T_1834 node _T_1835 = eq(UInt<2>(0h2), idx_19) when _T_1835 : node _T_1836 = shl(UInt<5>(0h13), 3) node _T_1837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1836) connect Queue10_UInt8_2.io.enq.bits, _T_1837 node _T_1838 = eq(UInt<2>(0h3), idx_19) when _T_1838 : node _T_1839 = shl(UInt<5>(0h13), 3) node _T_1840 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1839) connect Queue10_UInt8_3.io.enq.bits, _T_1840 node _T_1841 = eq(UInt<3>(0h4), idx_19) when _T_1841 : node _T_1842 = shl(UInt<5>(0h13), 3) node _T_1843 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1842) connect Queue10_UInt8_4.io.enq.bits, _T_1843 node _T_1844 = eq(UInt<3>(0h5), idx_19) when _T_1844 : node _T_1845 = shl(UInt<5>(0h13), 3) node _T_1846 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1845) connect Queue10_UInt8_5.io.enq.bits, _T_1846 node _T_1847 = eq(UInt<3>(0h6), idx_19) when _T_1847 : node _T_1848 = shl(UInt<5>(0h13), 3) node _T_1849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1848) connect Queue10_UInt8_6.io.enq.bits, _T_1849 node _T_1850 = eq(UInt<3>(0h7), idx_19) when _T_1850 : node _T_1851 = shl(UInt<5>(0h13), 3) node _T_1852 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1851) connect Queue10_UInt8_7.io.enq.bits, _T_1852 node _T_1853 = eq(UInt<4>(0h8), idx_19) when _T_1853 : node _T_1854 = shl(UInt<5>(0h13), 3) node _T_1855 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1854) connect Queue10_UInt8_8.io.enq.bits, _T_1855 node _T_1856 = eq(UInt<4>(0h9), idx_19) when _T_1856 : node _T_1857 = shl(UInt<5>(0h13), 3) node _T_1858 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1857) connect Queue10_UInt8_9.io.enq.bits, _T_1858 node _T_1859 = eq(UInt<4>(0ha), idx_19) when _T_1859 : node _T_1860 = shl(UInt<5>(0h13), 3) node _T_1861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1860) connect Queue10_UInt8_10.io.enq.bits, _T_1861 node _T_1862 = eq(UInt<4>(0hb), idx_19) when _T_1862 : node _T_1863 = shl(UInt<5>(0h13), 3) node _T_1864 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1863) connect Queue10_UInt8_11.io.enq.bits, _T_1864 node _T_1865 = eq(UInt<4>(0hc), idx_19) when _T_1865 : node _T_1866 = shl(UInt<5>(0h13), 3) node _T_1867 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1866) connect Queue10_UInt8_12.io.enq.bits, _T_1867 node _T_1868 = eq(UInt<4>(0hd), idx_19) when _T_1868 : node _T_1869 = shl(UInt<5>(0h13), 3) node _T_1870 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1869) connect Queue10_UInt8_13.io.enq.bits, _T_1870 node _T_1871 = eq(UInt<4>(0he), idx_19) when _T_1871 : node _T_1872 = shl(UInt<5>(0h13), 3) node _T_1873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1872) connect Queue10_UInt8_14.io.enq.bits, _T_1873 node _T_1874 = eq(UInt<4>(0hf), idx_19) when _T_1874 : node _T_1875 = shl(UInt<5>(0h13), 3) node _T_1876 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1875) connect Queue10_UInt8_15.io.enq.bits, _T_1876 node _T_1877 = eq(UInt<5>(0h10), idx_19) when _T_1877 : node _T_1878 = shl(UInt<5>(0h13), 3) node _T_1879 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1878) connect Queue10_UInt8_16.io.enq.bits, _T_1879 node _T_1880 = eq(UInt<5>(0h11), idx_19) when _T_1880 : node _T_1881 = shl(UInt<5>(0h13), 3) node _T_1882 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1881) connect Queue10_UInt8_17.io.enq.bits, _T_1882 node _T_1883 = eq(UInt<5>(0h12), idx_19) when _T_1883 : node _T_1884 = shl(UInt<5>(0h13), 3) node _T_1885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1884) connect Queue10_UInt8_18.io.enq.bits, _T_1885 node _T_1886 = eq(UInt<5>(0h13), idx_19) when _T_1886 : node _T_1887 = shl(UInt<5>(0h13), 3) node _T_1888 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1887) connect Queue10_UInt8_19.io.enq.bits, _T_1888 node _T_1889 = eq(UInt<5>(0h14), idx_19) when _T_1889 : node _T_1890 = shl(UInt<5>(0h13), 3) node _T_1891 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1890) connect Queue10_UInt8_20.io.enq.bits, _T_1891 node _T_1892 = eq(UInt<5>(0h15), idx_19) when _T_1892 : node _T_1893 = shl(UInt<5>(0h13), 3) node _T_1894 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1893) connect Queue10_UInt8_21.io.enq.bits, _T_1894 node _T_1895 = eq(UInt<5>(0h16), idx_19) when _T_1895 : node _T_1896 = shl(UInt<5>(0h13), 3) node _T_1897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1896) connect Queue10_UInt8_22.io.enq.bits, _T_1897 node _T_1898 = eq(UInt<5>(0h17), idx_19) when _T_1898 : node _T_1899 = shl(UInt<5>(0h13), 3) node _T_1900 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1899) connect Queue10_UInt8_23.io.enq.bits, _T_1900 node _T_1901 = eq(UInt<5>(0h18), idx_19) when _T_1901 : node _T_1902 = shl(UInt<5>(0h13), 3) node _T_1903 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1902) connect Queue10_UInt8_24.io.enq.bits, _T_1903 node _T_1904 = eq(UInt<5>(0h19), idx_19) when _T_1904 : node _T_1905 = shl(UInt<5>(0h13), 3) node _T_1906 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1905) connect Queue10_UInt8_25.io.enq.bits, _T_1906 node _T_1907 = eq(UInt<5>(0h1a), idx_19) when _T_1907 : node _T_1908 = shl(UInt<5>(0h13), 3) node _T_1909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1908) connect Queue10_UInt8_26.io.enq.bits, _T_1909 node _T_1910 = eq(UInt<5>(0h1b), idx_19) when _T_1910 : node _T_1911 = shl(UInt<5>(0h13), 3) node _T_1912 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1911) connect Queue10_UInt8_27.io.enq.bits, _T_1912 node _T_1913 = eq(UInt<5>(0h1c), idx_19) when _T_1913 : node _T_1914 = shl(UInt<5>(0h13), 3) node _T_1915 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1914) connect Queue10_UInt8_28.io.enq.bits, _T_1915 node _T_1916 = eq(UInt<5>(0h1d), idx_19) when _T_1916 : node _T_1917 = shl(UInt<5>(0h13), 3) node _T_1918 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1917) connect Queue10_UInt8_29.io.enq.bits, _T_1918 node _T_1919 = eq(UInt<5>(0h1e), idx_19) when _T_1919 : node _T_1920 = shl(UInt<5>(0h13), 3) node _T_1921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1920) connect Queue10_UInt8_30.io.enq.bits, _T_1921 node _T_1922 = eq(UInt<5>(0h1f), idx_19) when _T_1922 : node _T_1923 = shl(UInt<5>(0h13), 3) node _T_1924 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1923) connect Queue10_UInt8_31.io.enq.bits, _T_1924 node _idx_T_20 = add(write_start_index, UInt<5>(0h14)) node idx_20 = rem(_idx_T_20, UInt<6>(0h20)) node _T_1925 = eq(UInt<1>(0h0), idx_20) when _T_1925 : node _T_1926 = shl(UInt<5>(0h14), 3) node _T_1927 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1926) connect Queue10_UInt8.io.enq.bits, _T_1927 node _T_1928 = eq(UInt<1>(0h1), idx_20) when _T_1928 : node _T_1929 = shl(UInt<5>(0h14), 3) node _T_1930 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1929) connect Queue10_UInt8_1.io.enq.bits, _T_1930 node _T_1931 = eq(UInt<2>(0h2), idx_20) when _T_1931 : node _T_1932 = shl(UInt<5>(0h14), 3) node _T_1933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1932) connect Queue10_UInt8_2.io.enq.bits, _T_1933 node _T_1934 = eq(UInt<2>(0h3), idx_20) when _T_1934 : node _T_1935 = shl(UInt<5>(0h14), 3) node _T_1936 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1935) connect Queue10_UInt8_3.io.enq.bits, _T_1936 node _T_1937 = eq(UInt<3>(0h4), idx_20) when _T_1937 : node _T_1938 = shl(UInt<5>(0h14), 3) node _T_1939 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1938) connect Queue10_UInt8_4.io.enq.bits, _T_1939 node _T_1940 = eq(UInt<3>(0h5), idx_20) when _T_1940 : node _T_1941 = shl(UInt<5>(0h14), 3) node _T_1942 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1941) connect Queue10_UInt8_5.io.enq.bits, _T_1942 node _T_1943 = eq(UInt<3>(0h6), idx_20) when _T_1943 : node _T_1944 = shl(UInt<5>(0h14), 3) node _T_1945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1944) connect Queue10_UInt8_6.io.enq.bits, _T_1945 node _T_1946 = eq(UInt<3>(0h7), idx_20) when _T_1946 : node _T_1947 = shl(UInt<5>(0h14), 3) node _T_1948 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1947) connect Queue10_UInt8_7.io.enq.bits, _T_1948 node _T_1949 = eq(UInt<4>(0h8), idx_20) when _T_1949 : node _T_1950 = shl(UInt<5>(0h14), 3) node _T_1951 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1950) connect Queue10_UInt8_8.io.enq.bits, _T_1951 node _T_1952 = eq(UInt<4>(0h9), idx_20) when _T_1952 : node _T_1953 = shl(UInt<5>(0h14), 3) node _T_1954 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1953) connect Queue10_UInt8_9.io.enq.bits, _T_1954 node _T_1955 = eq(UInt<4>(0ha), idx_20) when _T_1955 : node _T_1956 = shl(UInt<5>(0h14), 3) node _T_1957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1956) connect Queue10_UInt8_10.io.enq.bits, _T_1957 node _T_1958 = eq(UInt<4>(0hb), idx_20) when _T_1958 : node _T_1959 = shl(UInt<5>(0h14), 3) node _T_1960 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1959) connect Queue10_UInt8_11.io.enq.bits, _T_1960 node _T_1961 = eq(UInt<4>(0hc), idx_20) when _T_1961 : node _T_1962 = shl(UInt<5>(0h14), 3) node _T_1963 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1962) connect Queue10_UInt8_12.io.enq.bits, _T_1963 node _T_1964 = eq(UInt<4>(0hd), idx_20) when _T_1964 : node _T_1965 = shl(UInt<5>(0h14), 3) node _T_1966 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1965) connect Queue10_UInt8_13.io.enq.bits, _T_1966 node _T_1967 = eq(UInt<4>(0he), idx_20) when _T_1967 : node _T_1968 = shl(UInt<5>(0h14), 3) node _T_1969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1968) connect Queue10_UInt8_14.io.enq.bits, _T_1969 node _T_1970 = eq(UInt<4>(0hf), idx_20) when _T_1970 : node _T_1971 = shl(UInt<5>(0h14), 3) node _T_1972 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1971) connect Queue10_UInt8_15.io.enq.bits, _T_1972 node _T_1973 = eq(UInt<5>(0h10), idx_20) when _T_1973 : node _T_1974 = shl(UInt<5>(0h14), 3) node _T_1975 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1974) connect Queue10_UInt8_16.io.enq.bits, _T_1975 node _T_1976 = eq(UInt<5>(0h11), idx_20) when _T_1976 : node _T_1977 = shl(UInt<5>(0h14), 3) node _T_1978 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1977) connect Queue10_UInt8_17.io.enq.bits, _T_1978 node _T_1979 = eq(UInt<5>(0h12), idx_20) when _T_1979 : node _T_1980 = shl(UInt<5>(0h14), 3) node _T_1981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1980) connect Queue10_UInt8_18.io.enq.bits, _T_1981 node _T_1982 = eq(UInt<5>(0h13), idx_20) when _T_1982 : node _T_1983 = shl(UInt<5>(0h14), 3) node _T_1984 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1983) connect Queue10_UInt8_19.io.enq.bits, _T_1984 node _T_1985 = eq(UInt<5>(0h14), idx_20) when _T_1985 : node _T_1986 = shl(UInt<5>(0h14), 3) node _T_1987 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1986) connect Queue10_UInt8_20.io.enq.bits, _T_1987 node _T_1988 = eq(UInt<5>(0h15), idx_20) when _T_1988 : node _T_1989 = shl(UInt<5>(0h14), 3) node _T_1990 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1989) connect Queue10_UInt8_21.io.enq.bits, _T_1990 node _T_1991 = eq(UInt<5>(0h16), idx_20) when _T_1991 : node _T_1992 = shl(UInt<5>(0h14), 3) node _T_1993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1992) connect Queue10_UInt8_22.io.enq.bits, _T_1993 node _T_1994 = eq(UInt<5>(0h17), idx_20) when _T_1994 : node _T_1995 = shl(UInt<5>(0h14), 3) node _T_1996 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1995) connect Queue10_UInt8_23.io.enq.bits, _T_1996 node _T_1997 = eq(UInt<5>(0h18), idx_20) when _T_1997 : node _T_1998 = shl(UInt<5>(0h14), 3) node _T_1999 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1998) connect Queue10_UInt8_24.io.enq.bits, _T_1999 node _T_2000 = eq(UInt<5>(0h19), idx_20) when _T_2000 : node _T_2001 = shl(UInt<5>(0h14), 3) node _T_2002 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2001) connect Queue10_UInt8_25.io.enq.bits, _T_2002 node _T_2003 = eq(UInt<5>(0h1a), idx_20) when _T_2003 : node _T_2004 = shl(UInt<5>(0h14), 3) node _T_2005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2004) connect Queue10_UInt8_26.io.enq.bits, _T_2005 node _T_2006 = eq(UInt<5>(0h1b), idx_20) when _T_2006 : node _T_2007 = shl(UInt<5>(0h14), 3) node _T_2008 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2007) connect Queue10_UInt8_27.io.enq.bits, _T_2008 node _T_2009 = eq(UInt<5>(0h1c), idx_20) when _T_2009 : node _T_2010 = shl(UInt<5>(0h14), 3) node _T_2011 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2010) connect Queue10_UInt8_28.io.enq.bits, _T_2011 node _T_2012 = eq(UInt<5>(0h1d), idx_20) when _T_2012 : node _T_2013 = shl(UInt<5>(0h14), 3) node _T_2014 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2013) connect Queue10_UInt8_29.io.enq.bits, _T_2014 node _T_2015 = eq(UInt<5>(0h1e), idx_20) when _T_2015 : node _T_2016 = shl(UInt<5>(0h14), 3) node _T_2017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2016) connect Queue10_UInt8_30.io.enq.bits, _T_2017 node _T_2018 = eq(UInt<5>(0h1f), idx_20) when _T_2018 : node _T_2019 = shl(UInt<5>(0h14), 3) node _T_2020 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2019) connect Queue10_UInt8_31.io.enq.bits, _T_2020 node _idx_T_21 = add(write_start_index, UInt<5>(0h15)) node idx_21 = rem(_idx_T_21, UInt<6>(0h20)) node _T_2021 = eq(UInt<1>(0h0), idx_21) when _T_2021 : node _T_2022 = shl(UInt<5>(0h15), 3) node _T_2023 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2022) connect Queue10_UInt8.io.enq.bits, _T_2023 node _T_2024 = eq(UInt<1>(0h1), idx_21) when _T_2024 : node _T_2025 = shl(UInt<5>(0h15), 3) node _T_2026 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2025) connect Queue10_UInt8_1.io.enq.bits, _T_2026 node _T_2027 = eq(UInt<2>(0h2), idx_21) when _T_2027 : node _T_2028 = shl(UInt<5>(0h15), 3) node _T_2029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2028) connect Queue10_UInt8_2.io.enq.bits, _T_2029 node _T_2030 = eq(UInt<2>(0h3), idx_21) when _T_2030 : node _T_2031 = shl(UInt<5>(0h15), 3) node _T_2032 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2031) connect Queue10_UInt8_3.io.enq.bits, _T_2032 node _T_2033 = eq(UInt<3>(0h4), idx_21) when _T_2033 : node _T_2034 = shl(UInt<5>(0h15), 3) node _T_2035 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2034) connect Queue10_UInt8_4.io.enq.bits, _T_2035 node _T_2036 = eq(UInt<3>(0h5), idx_21) when _T_2036 : node _T_2037 = shl(UInt<5>(0h15), 3) node _T_2038 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2037) connect Queue10_UInt8_5.io.enq.bits, _T_2038 node _T_2039 = eq(UInt<3>(0h6), idx_21) when _T_2039 : node _T_2040 = shl(UInt<5>(0h15), 3) node _T_2041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2040) connect Queue10_UInt8_6.io.enq.bits, _T_2041 node _T_2042 = eq(UInt<3>(0h7), idx_21) when _T_2042 : node _T_2043 = shl(UInt<5>(0h15), 3) node _T_2044 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2043) connect Queue10_UInt8_7.io.enq.bits, _T_2044 node _T_2045 = eq(UInt<4>(0h8), idx_21) when _T_2045 : node _T_2046 = shl(UInt<5>(0h15), 3) node _T_2047 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2046) connect Queue10_UInt8_8.io.enq.bits, _T_2047 node _T_2048 = eq(UInt<4>(0h9), idx_21) when _T_2048 : node _T_2049 = shl(UInt<5>(0h15), 3) node _T_2050 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2049) connect Queue10_UInt8_9.io.enq.bits, _T_2050 node _T_2051 = eq(UInt<4>(0ha), idx_21) when _T_2051 : node _T_2052 = shl(UInt<5>(0h15), 3) node _T_2053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2052) connect Queue10_UInt8_10.io.enq.bits, _T_2053 node _T_2054 = eq(UInt<4>(0hb), idx_21) when _T_2054 : node _T_2055 = shl(UInt<5>(0h15), 3) node _T_2056 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2055) connect Queue10_UInt8_11.io.enq.bits, _T_2056 node _T_2057 = eq(UInt<4>(0hc), idx_21) when _T_2057 : node _T_2058 = shl(UInt<5>(0h15), 3) node _T_2059 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2058) connect Queue10_UInt8_12.io.enq.bits, _T_2059 node _T_2060 = eq(UInt<4>(0hd), idx_21) when _T_2060 : node _T_2061 = shl(UInt<5>(0h15), 3) node _T_2062 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2061) connect Queue10_UInt8_13.io.enq.bits, _T_2062 node _T_2063 = eq(UInt<4>(0he), idx_21) when _T_2063 : node _T_2064 = shl(UInt<5>(0h15), 3) node _T_2065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2064) connect Queue10_UInt8_14.io.enq.bits, _T_2065 node _T_2066 = eq(UInt<4>(0hf), idx_21) when _T_2066 : node _T_2067 = shl(UInt<5>(0h15), 3) node _T_2068 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2067) connect Queue10_UInt8_15.io.enq.bits, _T_2068 node _T_2069 = eq(UInt<5>(0h10), idx_21) when _T_2069 : node _T_2070 = shl(UInt<5>(0h15), 3) node _T_2071 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2070) connect Queue10_UInt8_16.io.enq.bits, _T_2071 node _T_2072 = eq(UInt<5>(0h11), idx_21) when _T_2072 : node _T_2073 = shl(UInt<5>(0h15), 3) node _T_2074 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2073) connect Queue10_UInt8_17.io.enq.bits, _T_2074 node _T_2075 = eq(UInt<5>(0h12), idx_21) when _T_2075 : node _T_2076 = shl(UInt<5>(0h15), 3) node _T_2077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2076) connect Queue10_UInt8_18.io.enq.bits, _T_2077 node _T_2078 = eq(UInt<5>(0h13), idx_21) when _T_2078 : node _T_2079 = shl(UInt<5>(0h15), 3) node _T_2080 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2079) connect Queue10_UInt8_19.io.enq.bits, _T_2080 node _T_2081 = eq(UInt<5>(0h14), idx_21) when _T_2081 : node _T_2082 = shl(UInt<5>(0h15), 3) node _T_2083 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2082) connect Queue10_UInt8_20.io.enq.bits, _T_2083 node _T_2084 = eq(UInt<5>(0h15), idx_21) when _T_2084 : node _T_2085 = shl(UInt<5>(0h15), 3) node _T_2086 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2085) connect Queue10_UInt8_21.io.enq.bits, _T_2086 node _T_2087 = eq(UInt<5>(0h16), idx_21) when _T_2087 : node _T_2088 = shl(UInt<5>(0h15), 3) node _T_2089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2088) connect Queue10_UInt8_22.io.enq.bits, _T_2089 node _T_2090 = eq(UInt<5>(0h17), idx_21) when _T_2090 : node _T_2091 = shl(UInt<5>(0h15), 3) node _T_2092 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2091) connect Queue10_UInt8_23.io.enq.bits, _T_2092 node _T_2093 = eq(UInt<5>(0h18), idx_21) when _T_2093 : node _T_2094 = shl(UInt<5>(0h15), 3) node _T_2095 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2094) connect Queue10_UInt8_24.io.enq.bits, _T_2095 node _T_2096 = eq(UInt<5>(0h19), idx_21) when _T_2096 : node _T_2097 = shl(UInt<5>(0h15), 3) node _T_2098 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2097) connect Queue10_UInt8_25.io.enq.bits, _T_2098 node _T_2099 = eq(UInt<5>(0h1a), idx_21) when _T_2099 : node _T_2100 = shl(UInt<5>(0h15), 3) node _T_2101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2100) connect Queue10_UInt8_26.io.enq.bits, _T_2101 node _T_2102 = eq(UInt<5>(0h1b), idx_21) when _T_2102 : node _T_2103 = shl(UInt<5>(0h15), 3) node _T_2104 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2103) connect Queue10_UInt8_27.io.enq.bits, _T_2104 node _T_2105 = eq(UInt<5>(0h1c), idx_21) when _T_2105 : node _T_2106 = shl(UInt<5>(0h15), 3) node _T_2107 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2106) connect Queue10_UInt8_28.io.enq.bits, _T_2107 node _T_2108 = eq(UInt<5>(0h1d), idx_21) when _T_2108 : node _T_2109 = shl(UInt<5>(0h15), 3) node _T_2110 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2109) connect Queue10_UInt8_29.io.enq.bits, _T_2110 node _T_2111 = eq(UInt<5>(0h1e), idx_21) when _T_2111 : node _T_2112 = shl(UInt<5>(0h15), 3) node _T_2113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2112) connect Queue10_UInt8_30.io.enq.bits, _T_2113 node _T_2114 = eq(UInt<5>(0h1f), idx_21) when _T_2114 : node _T_2115 = shl(UInt<5>(0h15), 3) node _T_2116 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2115) connect Queue10_UInt8_31.io.enq.bits, _T_2116 node _idx_T_22 = add(write_start_index, UInt<5>(0h16)) node idx_22 = rem(_idx_T_22, UInt<6>(0h20)) node _T_2117 = eq(UInt<1>(0h0), idx_22) when _T_2117 : node _T_2118 = shl(UInt<5>(0h16), 3) node _T_2119 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2118) connect Queue10_UInt8.io.enq.bits, _T_2119 node _T_2120 = eq(UInt<1>(0h1), idx_22) when _T_2120 : node _T_2121 = shl(UInt<5>(0h16), 3) node _T_2122 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2121) connect Queue10_UInt8_1.io.enq.bits, _T_2122 node _T_2123 = eq(UInt<2>(0h2), idx_22) when _T_2123 : node _T_2124 = shl(UInt<5>(0h16), 3) node _T_2125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2124) connect Queue10_UInt8_2.io.enq.bits, _T_2125 node _T_2126 = eq(UInt<2>(0h3), idx_22) when _T_2126 : node _T_2127 = shl(UInt<5>(0h16), 3) node _T_2128 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2127) connect Queue10_UInt8_3.io.enq.bits, _T_2128 node _T_2129 = eq(UInt<3>(0h4), idx_22) when _T_2129 : node _T_2130 = shl(UInt<5>(0h16), 3) node _T_2131 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2130) connect Queue10_UInt8_4.io.enq.bits, _T_2131 node _T_2132 = eq(UInt<3>(0h5), idx_22) when _T_2132 : node _T_2133 = shl(UInt<5>(0h16), 3) node _T_2134 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2133) connect Queue10_UInt8_5.io.enq.bits, _T_2134 node _T_2135 = eq(UInt<3>(0h6), idx_22) when _T_2135 : node _T_2136 = shl(UInt<5>(0h16), 3) node _T_2137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2136) connect Queue10_UInt8_6.io.enq.bits, _T_2137 node _T_2138 = eq(UInt<3>(0h7), idx_22) when _T_2138 : node _T_2139 = shl(UInt<5>(0h16), 3) node _T_2140 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2139) connect Queue10_UInt8_7.io.enq.bits, _T_2140 node _T_2141 = eq(UInt<4>(0h8), idx_22) when _T_2141 : node _T_2142 = shl(UInt<5>(0h16), 3) node _T_2143 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2142) connect Queue10_UInt8_8.io.enq.bits, _T_2143 node _T_2144 = eq(UInt<4>(0h9), idx_22) when _T_2144 : node _T_2145 = shl(UInt<5>(0h16), 3) node _T_2146 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2145) connect Queue10_UInt8_9.io.enq.bits, _T_2146 node _T_2147 = eq(UInt<4>(0ha), idx_22) when _T_2147 : node _T_2148 = shl(UInt<5>(0h16), 3) node _T_2149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2148) connect Queue10_UInt8_10.io.enq.bits, _T_2149 node _T_2150 = eq(UInt<4>(0hb), idx_22) when _T_2150 : node _T_2151 = shl(UInt<5>(0h16), 3) node _T_2152 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2151) connect Queue10_UInt8_11.io.enq.bits, _T_2152 node _T_2153 = eq(UInt<4>(0hc), idx_22) when _T_2153 : node _T_2154 = shl(UInt<5>(0h16), 3) node _T_2155 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2154) connect Queue10_UInt8_12.io.enq.bits, _T_2155 node _T_2156 = eq(UInt<4>(0hd), idx_22) when _T_2156 : node _T_2157 = shl(UInt<5>(0h16), 3) node _T_2158 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2157) connect Queue10_UInt8_13.io.enq.bits, _T_2158 node _T_2159 = eq(UInt<4>(0he), idx_22) when _T_2159 : node _T_2160 = shl(UInt<5>(0h16), 3) node _T_2161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2160) connect Queue10_UInt8_14.io.enq.bits, _T_2161 node _T_2162 = eq(UInt<4>(0hf), idx_22) when _T_2162 : node _T_2163 = shl(UInt<5>(0h16), 3) node _T_2164 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2163) connect Queue10_UInt8_15.io.enq.bits, _T_2164 node _T_2165 = eq(UInt<5>(0h10), idx_22) when _T_2165 : node _T_2166 = shl(UInt<5>(0h16), 3) node _T_2167 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2166) connect Queue10_UInt8_16.io.enq.bits, _T_2167 node _T_2168 = eq(UInt<5>(0h11), idx_22) when _T_2168 : node _T_2169 = shl(UInt<5>(0h16), 3) node _T_2170 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2169) connect Queue10_UInt8_17.io.enq.bits, _T_2170 node _T_2171 = eq(UInt<5>(0h12), idx_22) when _T_2171 : node _T_2172 = shl(UInt<5>(0h16), 3) node _T_2173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2172) connect Queue10_UInt8_18.io.enq.bits, _T_2173 node _T_2174 = eq(UInt<5>(0h13), idx_22) when _T_2174 : node _T_2175 = shl(UInt<5>(0h16), 3) node _T_2176 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2175) connect Queue10_UInt8_19.io.enq.bits, _T_2176 node _T_2177 = eq(UInt<5>(0h14), idx_22) when _T_2177 : node _T_2178 = shl(UInt<5>(0h16), 3) node _T_2179 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2178) connect Queue10_UInt8_20.io.enq.bits, _T_2179 node _T_2180 = eq(UInt<5>(0h15), idx_22) when _T_2180 : node _T_2181 = shl(UInt<5>(0h16), 3) node _T_2182 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2181) connect Queue10_UInt8_21.io.enq.bits, _T_2182 node _T_2183 = eq(UInt<5>(0h16), idx_22) when _T_2183 : node _T_2184 = shl(UInt<5>(0h16), 3) node _T_2185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2184) connect Queue10_UInt8_22.io.enq.bits, _T_2185 node _T_2186 = eq(UInt<5>(0h17), idx_22) when _T_2186 : node _T_2187 = shl(UInt<5>(0h16), 3) node _T_2188 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2187) connect Queue10_UInt8_23.io.enq.bits, _T_2188 node _T_2189 = eq(UInt<5>(0h18), idx_22) when _T_2189 : node _T_2190 = shl(UInt<5>(0h16), 3) node _T_2191 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2190) connect Queue10_UInt8_24.io.enq.bits, _T_2191 node _T_2192 = eq(UInt<5>(0h19), idx_22) when _T_2192 : node _T_2193 = shl(UInt<5>(0h16), 3) node _T_2194 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2193) connect Queue10_UInt8_25.io.enq.bits, _T_2194 node _T_2195 = eq(UInt<5>(0h1a), idx_22) when _T_2195 : node _T_2196 = shl(UInt<5>(0h16), 3) node _T_2197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2196) connect Queue10_UInt8_26.io.enq.bits, _T_2197 node _T_2198 = eq(UInt<5>(0h1b), idx_22) when _T_2198 : node _T_2199 = shl(UInt<5>(0h16), 3) node _T_2200 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2199) connect Queue10_UInt8_27.io.enq.bits, _T_2200 node _T_2201 = eq(UInt<5>(0h1c), idx_22) when _T_2201 : node _T_2202 = shl(UInt<5>(0h16), 3) node _T_2203 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2202) connect Queue10_UInt8_28.io.enq.bits, _T_2203 node _T_2204 = eq(UInt<5>(0h1d), idx_22) when _T_2204 : node _T_2205 = shl(UInt<5>(0h16), 3) node _T_2206 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2205) connect Queue10_UInt8_29.io.enq.bits, _T_2206 node _T_2207 = eq(UInt<5>(0h1e), idx_22) when _T_2207 : node _T_2208 = shl(UInt<5>(0h16), 3) node _T_2209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2208) connect Queue10_UInt8_30.io.enq.bits, _T_2209 node _T_2210 = eq(UInt<5>(0h1f), idx_22) when _T_2210 : node _T_2211 = shl(UInt<5>(0h16), 3) node _T_2212 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2211) connect Queue10_UInt8_31.io.enq.bits, _T_2212 node _idx_T_23 = add(write_start_index, UInt<5>(0h17)) node idx_23 = rem(_idx_T_23, UInt<6>(0h20)) node _T_2213 = eq(UInt<1>(0h0), idx_23) when _T_2213 : node _T_2214 = shl(UInt<5>(0h17), 3) node _T_2215 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2214) connect Queue10_UInt8.io.enq.bits, _T_2215 node _T_2216 = eq(UInt<1>(0h1), idx_23) when _T_2216 : node _T_2217 = shl(UInt<5>(0h17), 3) node _T_2218 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2217) connect Queue10_UInt8_1.io.enq.bits, _T_2218 node _T_2219 = eq(UInt<2>(0h2), idx_23) when _T_2219 : node _T_2220 = shl(UInt<5>(0h17), 3) node _T_2221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2220) connect Queue10_UInt8_2.io.enq.bits, _T_2221 node _T_2222 = eq(UInt<2>(0h3), idx_23) when _T_2222 : node _T_2223 = shl(UInt<5>(0h17), 3) node _T_2224 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2223) connect Queue10_UInt8_3.io.enq.bits, _T_2224 node _T_2225 = eq(UInt<3>(0h4), idx_23) when _T_2225 : node _T_2226 = shl(UInt<5>(0h17), 3) node _T_2227 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2226) connect Queue10_UInt8_4.io.enq.bits, _T_2227 node _T_2228 = eq(UInt<3>(0h5), idx_23) when _T_2228 : node _T_2229 = shl(UInt<5>(0h17), 3) node _T_2230 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2229) connect Queue10_UInt8_5.io.enq.bits, _T_2230 node _T_2231 = eq(UInt<3>(0h6), idx_23) when _T_2231 : node _T_2232 = shl(UInt<5>(0h17), 3) node _T_2233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2232) connect Queue10_UInt8_6.io.enq.bits, _T_2233 node _T_2234 = eq(UInt<3>(0h7), idx_23) when _T_2234 : node _T_2235 = shl(UInt<5>(0h17), 3) node _T_2236 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2235) connect Queue10_UInt8_7.io.enq.bits, _T_2236 node _T_2237 = eq(UInt<4>(0h8), idx_23) when _T_2237 : node _T_2238 = shl(UInt<5>(0h17), 3) node _T_2239 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2238) connect Queue10_UInt8_8.io.enq.bits, _T_2239 node _T_2240 = eq(UInt<4>(0h9), idx_23) when _T_2240 : node _T_2241 = shl(UInt<5>(0h17), 3) node _T_2242 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2241) connect Queue10_UInt8_9.io.enq.bits, _T_2242 node _T_2243 = eq(UInt<4>(0ha), idx_23) when _T_2243 : node _T_2244 = shl(UInt<5>(0h17), 3) node _T_2245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2244) connect Queue10_UInt8_10.io.enq.bits, _T_2245 node _T_2246 = eq(UInt<4>(0hb), idx_23) when _T_2246 : node _T_2247 = shl(UInt<5>(0h17), 3) node _T_2248 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2247) connect Queue10_UInt8_11.io.enq.bits, _T_2248 node _T_2249 = eq(UInt<4>(0hc), idx_23) when _T_2249 : node _T_2250 = shl(UInt<5>(0h17), 3) node _T_2251 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2250) connect Queue10_UInt8_12.io.enq.bits, _T_2251 node _T_2252 = eq(UInt<4>(0hd), idx_23) when _T_2252 : node _T_2253 = shl(UInt<5>(0h17), 3) node _T_2254 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2253) connect Queue10_UInt8_13.io.enq.bits, _T_2254 node _T_2255 = eq(UInt<4>(0he), idx_23) when _T_2255 : node _T_2256 = shl(UInt<5>(0h17), 3) node _T_2257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2256) connect Queue10_UInt8_14.io.enq.bits, _T_2257 node _T_2258 = eq(UInt<4>(0hf), idx_23) when _T_2258 : node _T_2259 = shl(UInt<5>(0h17), 3) node _T_2260 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2259) connect Queue10_UInt8_15.io.enq.bits, _T_2260 node _T_2261 = eq(UInt<5>(0h10), idx_23) when _T_2261 : node _T_2262 = shl(UInt<5>(0h17), 3) node _T_2263 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2262) connect Queue10_UInt8_16.io.enq.bits, _T_2263 node _T_2264 = eq(UInt<5>(0h11), idx_23) when _T_2264 : node _T_2265 = shl(UInt<5>(0h17), 3) node _T_2266 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2265) connect Queue10_UInt8_17.io.enq.bits, _T_2266 node _T_2267 = eq(UInt<5>(0h12), idx_23) when _T_2267 : node _T_2268 = shl(UInt<5>(0h17), 3) node _T_2269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2268) connect Queue10_UInt8_18.io.enq.bits, _T_2269 node _T_2270 = eq(UInt<5>(0h13), idx_23) when _T_2270 : node _T_2271 = shl(UInt<5>(0h17), 3) node _T_2272 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2271) connect Queue10_UInt8_19.io.enq.bits, _T_2272 node _T_2273 = eq(UInt<5>(0h14), idx_23) when _T_2273 : node _T_2274 = shl(UInt<5>(0h17), 3) node _T_2275 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2274) connect Queue10_UInt8_20.io.enq.bits, _T_2275 node _T_2276 = eq(UInt<5>(0h15), idx_23) when _T_2276 : node _T_2277 = shl(UInt<5>(0h17), 3) node _T_2278 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2277) connect Queue10_UInt8_21.io.enq.bits, _T_2278 node _T_2279 = eq(UInt<5>(0h16), idx_23) when _T_2279 : node _T_2280 = shl(UInt<5>(0h17), 3) node _T_2281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2280) connect Queue10_UInt8_22.io.enq.bits, _T_2281 node _T_2282 = eq(UInt<5>(0h17), idx_23) when _T_2282 : node _T_2283 = shl(UInt<5>(0h17), 3) node _T_2284 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2283) connect Queue10_UInt8_23.io.enq.bits, _T_2284 node _T_2285 = eq(UInt<5>(0h18), idx_23) when _T_2285 : node _T_2286 = shl(UInt<5>(0h17), 3) node _T_2287 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2286) connect Queue10_UInt8_24.io.enq.bits, _T_2287 node _T_2288 = eq(UInt<5>(0h19), idx_23) when _T_2288 : node _T_2289 = shl(UInt<5>(0h17), 3) node _T_2290 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2289) connect Queue10_UInt8_25.io.enq.bits, _T_2290 node _T_2291 = eq(UInt<5>(0h1a), idx_23) when _T_2291 : node _T_2292 = shl(UInt<5>(0h17), 3) node _T_2293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2292) connect Queue10_UInt8_26.io.enq.bits, _T_2293 node _T_2294 = eq(UInt<5>(0h1b), idx_23) when _T_2294 : node _T_2295 = shl(UInt<5>(0h17), 3) node _T_2296 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2295) connect Queue10_UInt8_27.io.enq.bits, _T_2296 node _T_2297 = eq(UInt<5>(0h1c), idx_23) when _T_2297 : node _T_2298 = shl(UInt<5>(0h17), 3) node _T_2299 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2298) connect Queue10_UInt8_28.io.enq.bits, _T_2299 node _T_2300 = eq(UInt<5>(0h1d), idx_23) when _T_2300 : node _T_2301 = shl(UInt<5>(0h17), 3) node _T_2302 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2301) connect Queue10_UInt8_29.io.enq.bits, _T_2302 node _T_2303 = eq(UInt<5>(0h1e), idx_23) when _T_2303 : node _T_2304 = shl(UInt<5>(0h17), 3) node _T_2305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2304) connect Queue10_UInt8_30.io.enq.bits, _T_2305 node _T_2306 = eq(UInt<5>(0h1f), idx_23) when _T_2306 : node _T_2307 = shl(UInt<5>(0h17), 3) node _T_2308 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2307) connect Queue10_UInt8_31.io.enq.bits, _T_2308 node _idx_T_24 = add(write_start_index, UInt<5>(0h18)) node idx_24 = rem(_idx_T_24, UInt<6>(0h20)) node _T_2309 = eq(UInt<1>(0h0), idx_24) when _T_2309 : node _T_2310 = shl(UInt<5>(0h18), 3) node _T_2311 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2310) connect Queue10_UInt8.io.enq.bits, _T_2311 node _T_2312 = eq(UInt<1>(0h1), idx_24) when _T_2312 : node _T_2313 = shl(UInt<5>(0h18), 3) node _T_2314 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2313) connect Queue10_UInt8_1.io.enq.bits, _T_2314 node _T_2315 = eq(UInt<2>(0h2), idx_24) when _T_2315 : node _T_2316 = shl(UInt<5>(0h18), 3) node _T_2317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2316) connect Queue10_UInt8_2.io.enq.bits, _T_2317 node _T_2318 = eq(UInt<2>(0h3), idx_24) when _T_2318 : node _T_2319 = shl(UInt<5>(0h18), 3) node _T_2320 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2319) connect Queue10_UInt8_3.io.enq.bits, _T_2320 node _T_2321 = eq(UInt<3>(0h4), idx_24) when _T_2321 : node _T_2322 = shl(UInt<5>(0h18), 3) node _T_2323 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2322) connect Queue10_UInt8_4.io.enq.bits, _T_2323 node _T_2324 = eq(UInt<3>(0h5), idx_24) when _T_2324 : node _T_2325 = shl(UInt<5>(0h18), 3) node _T_2326 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2325) connect Queue10_UInt8_5.io.enq.bits, _T_2326 node _T_2327 = eq(UInt<3>(0h6), idx_24) when _T_2327 : node _T_2328 = shl(UInt<5>(0h18), 3) node _T_2329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2328) connect Queue10_UInt8_6.io.enq.bits, _T_2329 node _T_2330 = eq(UInt<3>(0h7), idx_24) when _T_2330 : node _T_2331 = shl(UInt<5>(0h18), 3) node _T_2332 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2331) connect Queue10_UInt8_7.io.enq.bits, _T_2332 node _T_2333 = eq(UInt<4>(0h8), idx_24) when _T_2333 : node _T_2334 = shl(UInt<5>(0h18), 3) node _T_2335 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2334) connect Queue10_UInt8_8.io.enq.bits, _T_2335 node _T_2336 = eq(UInt<4>(0h9), idx_24) when _T_2336 : node _T_2337 = shl(UInt<5>(0h18), 3) node _T_2338 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2337) connect Queue10_UInt8_9.io.enq.bits, _T_2338 node _T_2339 = eq(UInt<4>(0ha), idx_24) when _T_2339 : node _T_2340 = shl(UInt<5>(0h18), 3) node _T_2341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2340) connect Queue10_UInt8_10.io.enq.bits, _T_2341 node _T_2342 = eq(UInt<4>(0hb), idx_24) when _T_2342 : node _T_2343 = shl(UInt<5>(0h18), 3) node _T_2344 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2343) connect Queue10_UInt8_11.io.enq.bits, _T_2344 node _T_2345 = eq(UInt<4>(0hc), idx_24) when _T_2345 : node _T_2346 = shl(UInt<5>(0h18), 3) node _T_2347 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2346) connect Queue10_UInt8_12.io.enq.bits, _T_2347 node _T_2348 = eq(UInt<4>(0hd), idx_24) when _T_2348 : node _T_2349 = shl(UInt<5>(0h18), 3) node _T_2350 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2349) connect Queue10_UInt8_13.io.enq.bits, _T_2350 node _T_2351 = eq(UInt<4>(0he), idx_24) when _T_2351 : node _T_2352 = shl(UInt<5>(0h18), 3) node _T_2353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2352) connect Queue10_UInt8_14.io.enq.bits, _T_2353 node _T_2354 = eq(UInt<4>(0hf), idx_24) when _T_2354 : node _T_2355 = shl(UInt<5>(0h18), 3) node _T_2356 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2355) connect Queue10_UInt8_15.io.enq.bits, _T_2356 node _T_2357 = eq(UInt<5>(0h10), idx_24) when _T_2357 : node _T_2358 = shl(UInt<5>(0h18), 3) node _T_2359 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2358) connect Queue10_UInt8_16.io.enq.bits, _T_2359 node _T_2360 = eq(UInt<5>(0h11), idx_24) when _T_2360 : node _T_2361 = shl(UInt<5>(0h18), 3) node _T_2362 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2361) connect Queue10_UInt8_17.io.enq.bits, _T_2362 node _T_2363 = eq(UInt<5>(0h12), idx_24) when _T_2363 : node _T_2364 = shl(UInt<5>(0h18), 3) node _T_2365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2364) connect Queue10_UInt8_18.io.enq.bits, _T_2365 node _T_2366 = eq(UInt<5>(0h13), idx_24) when _T_2366 : node _T_2367 = shl(UInt<5>(0h18), 3) node _T_2368 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2367) connect Queue10_UInt8_19.io.enq.bits, _T_2368 node _T_2369 = eq(UInt<5>(0h14), idx_24) when _T_2369 : node _T_2370 = shl(UInt<5>(0h18), 3) node _T_2371 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2370) connect Queue10_UInt8_20.io.enq.bits, _T_2371 node _T_2372 = eq(UInt<5>(0h15), idx_24) when _T_2372 : node _T_2373 = shl(UInt<5>(0h18), 3) node _T_2374 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2373) connect Queue10_UInt8_21.io.enq.bits, _T_2374 node _T_2375 = eq(UInt<5>(0h16), idx_24) when _T_2375 : node _T_2376 = shl(UInt<5>(0h18), 3) node _T_2377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2376) connect Queue10_UInt8_22.io.enq.bits, _T_2377 node _T_2378 = eq(UInt<5>(0h17), idx_24) when _T_2378 : node _T_2379 = shl(UInt<5>(0h18), 3) node _T_2380 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2379) connect Queue10_UInt8_23.io.enq.bits, _T_2380 node _T_2381 = eq(UInt<5>(0h18), idx_24) when _T_2381 : node _T_2382 = shl(UInt<5>(0h18), 3) node _T_2383 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2382) connect Queue10_UInt8_24.io.enq.bits, _T_2383 node _T_2384 = eq(UInt<5>(0h19), idx_24) when _T_2384 : node _T_2385 = shl(UInt<5>(0h18), 3) node _T_2386 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2385) connect Queue10_UInt8_25.io.enq.bits, _T_2386 node _T_2387 = eq(UInt<5>(0h1a), idx_24) when _T_2387 : node _T_2388 = shl(UInt<5>(0h18), 3) node _T_2389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2388) connect Queue10_UInt8_26.io.enq.bits, _T_2389 node _T_2390 = eq(UInt<5>(0h1b), idx_24) when _T_2390 : node _T_2391 = shl(UInt<5>(0h18), 3) node _T_2392 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2391) connect Queue10_UInt8_27.io.enq.bits, _T_2392 node _T_2393 = eq(UInt<5>(0h1c), idx_24) when _T_2393 : node _T_2394 = shl(UInt<5>(0h18), 3) node _T_2395 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2394) connect Queue10_UInt8_28.io.enq.bits, _T_2395 node _T_2396 = eq(UInt<5>(0h1d), idx_24) when _T_2396 : node _T_2397 = shl(UInt<5>(0h18), 3) node _T_2398 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2397) connect Queue10_UInt8_29.io.enq.bits, _T_2398 node _T_2399 = eq(UInt<5>(0h1e), idx_24) when _T_2399 : node _T_2400 = shl(UInt<5>(0h18), 3) node _T_2401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2400) connect Queue10_UInt8_30.io.enq.bits, _T_2401 node _T_2402 = eq(UInt<5>(0h1f), idx_24) when _T_2402 : node _T_2403 = shl(UInt<5>(0h18), 3) node _T_2404 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2403) connect Queue10_UInt8_31.io.enq.bits, _T_2404 node _idx_T_25 = add(write_start_index, UInt<5>(0h19)) node idx_25 = rem(_idx_T_25, UInt<6>(0h20)) node _T_2405 = eq(UInt<1>(0h0), idx_25) when _T_2405 : node _T_2406 = shl(UInt<5>(0h19), 3) node _T_2407 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2406) connect Queue10_UInt8.io.enq.bits, _T_2407 node _T_2408 = eq(UInt<1>(0h1), idx_25) when _T_2408 : node _T_2409 = shl(UInt<5>(0h19), 3) node _T_2410 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2409) connect Queue10_UInt8_1.io.enq.bits, _T_2410 node _T_2411 = eq(UInt<2>(0h2), idx_25) when _T_2411 : node _T_2412 = shl(UInt<5>(0h19), 3) node _T_2413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2412) connect Queue10_UInt8_2.io.enq.bits, _T_2413 node _T_2414 = eq(UInt<2>(0h3), idx_25) when _T_2414 : node _T_2415 = shl(UInt<5>(0h19), 3) node _T_2416 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2415) connect Queue10_UInt8_3.io.enq.bits, _T_2416 node _T_2417 = eq(UInt<3>(0h4), idx_25) when _T_2417 : node _T_2418 = shl(UInt<5>(0h19), 3) node _T_2419 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2418) connect Queue10_UInt8_4.io.enq.bits, _T_2419 node _T_2420 = eq(UInt<3>(0h5), idx_25) when _T_2420 : node _T_2421 = shl(UInt<5>(0h19), 3) node _T_2422 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2421) connect Queue10_UInt8_5.io.enq.bits, _T_2422 node _T_2423 = eq(UInt<3>(0h6), idx_25) when _T_2423 : node _T_2424 = shl(UInt<5>(0h19), 3) node _T_2425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2424) connect Queue10_UInt8_6.io.enq.bits, _T_2425 node _T_2426 = eq(UInt<3>(0h7), idx_25) when _T_2426 : node _T_2427 = shl(UInt<5>(0h19), 3) node _T_2428 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2427) connect Queue10_UInt8_7.io.enq.bits, _T_2428 node _T_2429 = eq(UInt<4>(0h8), idx_25) when _T_2429 : node _T_2430 = shl(UInt<5>(0h19), 3) node _T_2431 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2430) connect Queue10_UInt8_8.io.enq.bits, _T_2431 node _T_2432 = eq(UInt<4>(0h9), idx_25) when _T_2432 : node _T_2433 = shl(UInt<5>(0h19), 3) node _T_2434 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2433) connect Queue10_UInt8_9.io.enq.bits, _T_2434 node _T_2435 = eq(UInt<4>(0ha), idx_25) when _T_2435 : node _T_2436 = shl(UInt<5>(0h19), 3) node _T_2437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2436) connect Queue10_UInt8_10.io.enq.bits, _T_2437 node _T_2438 = eq(UInt<4>(0hb), idx_25) when _T_2438 : node _T_2439 = shl(UInt<5>(0h19), 3) node _T_2440 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2439) connect Queue10_UInt8_11.io.enq.bits, _T_2440 node _T_2441 = eq(UInt<4>(0hc), idx_25) when _T_2441 : node _T_2442 = shl(UInt<5>(0h19), 3) node _T_2443 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2442) connect Queue10_UInt8_12.io.enq.bits, _T_2443 node _T_2444 = eq(UInt<4>(0hd), idx_25) when _T_2444 : node _T_2445 = shl(UInt<5>(0h19), 3) node _T_2446 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2445) connect Queue10_UInt8_13.io.enq.bits, _T_2446 node _T_2447 = eq(UInt<4>(0he), idx_25) when _T_2447 : node _T_2448 = shl(UInt<5>(0h19), 3) node _T_2449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2448) connect Queue10_UInt8_14.io.enq.bits, _T_2449 node _T_2450 = eq(UInt<4>(0hf), idx_25) when _T_2450 : node _T_2451 = shl(UInt<5>(0h19), 3) node _T_2452 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2451) connect Queue10_UInt8_15.io.enq.bits, _T_2452 node _T_2453 = eq(UInt<5>(0h10), idx_25) when _T_2453 : node _T_2454 = shl(UInt<5>(0h19), 3) node _T_2455 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2454) connect Queue10_UInt8_16.io.enq.bits, _T_2455 node _T_2456 = eq(UInt<5>(0h11), idx_25) when _T_2456 : node _T_2457 = shl(UInt<5>(0h19), 3) node _T_2458 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2457) connect Queue10_UInt8_17.io.enq.bits, _T_2458 node _T_2459 = eq(UInt<5>(0h12), idx_25) when _T_2459 : node _T_2460 = shl(UInt<5>(0h19), 3) node _T_2461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2460) connect Queue10_UInt8_18.io.enq.bits, _T_2461 node _T_2462 = eq(UInt<5>(0h13), idx_25) when _T_2462 : node _T_2463 = shl(UInt<5>(0h19), 3) node _T_2464 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2463) connect Queue10_UInt8_19.io.enq.bits, _T_2464 node _T_2465 = eq(UInt<5>(0h14), idx_25) when _T_2465 : node _T_2466 = shl(UInt<5>(0h19), 3) node _T_2467 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2466) connect Queue10_UInt8_20.io.enq.bits, _T_2467 node _T_2468 = eq(UInt<5>(0h15), idx_25) when _T_2468 : node _T_2469 = shl(UInt<5>(0h19), 3) node _T_2470 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2469) connect Queue10_UInt8_21.io.enq.bits, _T_2470 node _T_2471 = eq(UInt<5>(0h16), idx_25) when _T_2471 : node _T_2472 = shl(UInt<5>(0h19), 3) node _T_2473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2472) connect Queue10_UInt8_22.io.enq.bits, _T_2473 node _T_2474 = eq(UInt<5>(0h17), idx_25) when _T_2474 : node _T_2475 = shl(UInt<5>(0h19), 3) node _T_2476 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2475) connect Queue10_UInt8_23.io.enq.bits, _T_2476 node _T_2477 = eq(UInt<5>(0h18), idx_25) when _T_2477 : node _T_2478 = shl(UInt<5>(0h19), 3) node _T_2479 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2478) connect Queue10_UInt8_24.io.enq.bits, _T_2479 node _T_2480 = eq(UInt<5>(0h19), idx_25) when _T_2480 : node _T_2481 = shl(UInt<5>(0h19), 3) node _T_2482 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2481) connect Queue10_UInt8_25.io.enq.bits, _T_2482 node _T_2483 = eq(UInt<5>(0h1a), idx_25) when _T_2483 : node _T_2484 = shl(UInt<5>(0h19), 3) node _T_2485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2484) connect Queue10_UInt8_26.io.enq.bits, _T_2485 node _T_2486 = eq(UInt<5>(0h1b), idx_25) when _T_2486 : node _T_2487 = shl(UInt<5>(0h19), 3) node _T_2488 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2487) connect Queue10_UInt8_27.io.enq.bits, _T_2488 node _T_2489 = eq(UInt<5>(0h1c), idx_25) when _T_2489 : node _T_2490 = shl(UInt<5>(0h19), 3) node _T_2491 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2490) connect Queue10_UInt8_28.io.enq.bits, _T_2491 node _T_2492 = eq(UInt<5>(0h1d), idx_25) when _T_2492 : node _T_2493 = shl(UInt<5>(0h19), 3) node _T_2494 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2493) connect Queue10_UInt8_29.io.enq.bits, _T_2494 node _T_2495 = eq(UInt<5>(0h1e), idx_25) when _T_2495 : node _T_2496 = shl(UInt<5>(0h19), 3) node _T_2497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2496) connect Queue10_UInt8_30.io.enq.bits, _T_2497 node _T_2498 = eq(UInt<5>(0h1f), idx_25) when _T_2498 : node _T_2499 = shl(UInt<5>(0h19), 3) node _T_2500 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2499) connect Queue10_UInt8_31.io.enq.bits, _T_2500 node _idx_T_26 = add(write_start_index, UInt<5>(0h1a)) node idx_26 = rem(_idx_T_26, UInt<6>(0h20)) node _T_2501 = eq(UInt<1>(0h0), idx_26) when _T_2501 : node _T_2502 = shl(UInt<5>(0h1a), 3) node _T_2503 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2502) connect Queue10_UInt8.io.enq.bits, _T_2503 node _T_2504 = eq(UInt<1>(0h1), idx_26) when _T_2504 : node _T_2505 = shl(UInt<5>(0h1a), 3) node _T_2506 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2505) connect Queue10_UInt8_1.io.enq.bits, _T_2506 node _T_2507 = eq(UInt<2>(0h2), idx_26) when _T_2507 : node _T_2508 = shl(UInt<5>(0h1a), 3) node _T_2509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2508) connect Queue10_UInt8_2.io.enq.bits, _T_2509 node _T_2510 = eq(UInt<2>(0h3), idx_26) when _T_2510 : node _T_2511 = shl(UInt<5>(0h1a), 3) node _T_2512 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2511) connect Queue10_UInt8_3.io.enq.bits, _T_2512 node _T_2513 = eq(UInt<3>(0h4), idx_26) when _T_2513 : node _T_2514 = shl(UInt<5>(0h1a), 3) node _T_2515 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2514) connect Queue10_UInt8_4.io.enq.bits, _T_2515 node _T_2516 = eq(UInt<3>(0h5), idx_26) when _T_2516 : node _T_2517 = shl(UInt<5>(0h1a), 3) node _T_2518 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2517) connect Queue10_UInt8_5.io.enq.bits, _T_2518 node _T_2519 = eq(UInt<3>(0h6), idx_26) when _T_2519 : node _T_2520 = shl(UInt<5>(0h1a), 3) node _T_2521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2520) connect Queue10_UInt8_6.io.enq.bits, _T_2521 node _T_2522 = eq(UInt<3>(0h7), idx_26) when _T_2522 : node _T_2523 = shl(UInt<5>(0h1a), 3) node _T_2524 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2523) connect Queue10_UInt8_7.io.enq.bits, _T_2524 node _T_2525 = eq(UInt<4>(0h8), idx_26) when _T_2525 : node _T_2526 = shl(UInt<5>(0h1a), 3) node _T_2527 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2526) connect Queue10_UInt8_8.io.enq.bits, _T_2527 node _T_2528 = eq(UInt<4>(0h9), idx_26) when _T_2528 : node _T_2529 = shl(UInt<5>(0h1a), 3) node _T_2530 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2529) connect Queue10_UInt8_9.io.enq.bits, _T_2530 node _T_2531 = eq(UInt<4>(0ha), idx_26) when _T_2531 : node _T_2532 = shl(UInt<5>(0h1a), 3) node _T_2533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2532) connect Queue10_UInt8_10.io.enq.bits, _T_2533 node _T_2534 = eq(UInt<4>(0hb), idx_26) when _T_2534 : node _T_2535 = shl(UInt<5>(0h1a), 3) node _T_2536 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2535) connect Queue10_UInt8_11.io.enq.bits, _T_2536 node _T_2537 = eq(UInt<4>(0hc), idx_26) when _T_2537 : node _T_2538 = shl(UInt<5>(0h1a), 3) node _T_2539 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2538) connect Queue10_UInt8_12.io.enq.bits, _T_2539 node _T_2540 = eq(UInt<4>(0hd), idx_26) when _T_2540 : node _T_2541 = shl(UInt<5>(0h1a), 3) node _T_2542 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2541) connect Queue10_UInt8_13.io.enq.bits, _T_2542 node _T_2543 = eq(UInt<4>(0he), idx_26) when _T_2543 : node _T_2544 = shl(UInt<5>(0h1a), 3) node _T_2545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2544) connect Queue10_UInt8_14.io.enq.bits, _T_2545 node _T_2546 = eq(UInt<4>(0hf), idx_26) when _T_2546 : node _T_2547 = shl(UInt<5>(0h1a), 3) node _T_2548 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2547) connect Queue10_UInt8_15.io.enq.bits, _T_2548 node _T_2549 = eq(UInt<5>(0h10), idx_26) when _T_2549 : node _T_2550 = shl(UInt<5>(0h1a), 3) node _T_2551 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2550) connect Queue10_UInt8_16.io.enq.bits, _T_2551 node _T_2552 = eq(UInt<5>(0h11), idx_26) when _T_2552 : node _T_2553 = shl(UInt<5>(0h1a), 3) node _T_2554 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2553) connect Queue10_UInt8_17.io.enq.bits, _T_2554 node _T_2555 = eq(UInt<5>(0h12), idx_26) when _T_2555 : node _T_2556 = shl(UInt<5>(0h1a), 3) node _T_2557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2556) connect Queue10_UInt8_18.io.enq.bits, _T_2557 node _T_2558 = eq(UInt<5>(0h13), idx_26) when _T_2558 : node _T_2559 = shl(UInt<5>(0h1a), 3) node _T_2560 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2559) connect Queue10_UInt8_19.io.enq.bits, _T_2560 node _T_2561 = eq(UInt<5>(0h14), idx_26) when _T_2561 : node _T_2562 = shl(UInt<5>(0h1a), 3) node _T_2563 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2562) connect Queue10_UInt8_20.io.enq.bits, _T_2563 node _T_2564 = eq(UInt<5>(0h15), idx_26) when _T_2564 : node _T_2565 = shl(UInt<5>(0h1a), 3) node _T_2566 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2565) connect Queue10_UInt8_21.io.enq.bits, _T_2566 node _T_2567 = eq(UInt<5>(0h16), idx_26) when _T_2567 : node _T_2568 = shl(UInt<5>(0h1a), 3) node _T_2569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2568) connect Queue10_UInt8_22.io.enq.bits, _T_2569 node _T_2570 = eq(UInt<5>(0h17), idx_26) when _T_2570 : node _T_2571 = shl(UInt<5>(0h1a), 3) node _T_2572 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2571) connect Queue10_UInt8_23.io.enq.bits, _T_2572 node _T_2573 = eq(UInt<5>(0h18), idx_26) when _T_2573 : node _T_2574 = shl(UInt<5>(0h1a), 3) node _T_2575 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2574) connect Queue10_UInt8_24.io.enq.bits, _T_2575 node _T_2576 = eq(UInt<5>(0h19), idx_26) when _T_2576 : node _T_2577 = shl(UInt<5>(0h1a), 3) node _T_2578 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2577) connect Queue10_UInt8_25.io.enq.bits, _T_2578 node _T_2579 = eq(UInt<5>(0h1a), idx_26) when _T_2579 : node _T_2580 = shl(UInt<5>(0h1a), 3) node _T_2581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2580) connect Queue10_UInt8_26.io.enq.bits, _T_2581 node _T_2582 = eq(UInt<5>(0h1b), idx_26) when _T_2582 : node _T_2583 = shl(UInt<5>(0h1a), 3) node _T_2584 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2583) connect Queue10_UInt8_27.io.enq.bits, _T_2584 node _T_2585 = eq(UInt<5>(0h1c), idx_26) when _T_2585 : node _T_2586 = shl(UInt<5>(0h1a), 3) node _T_2587 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2586) connect Queue10_UInt8_28.io.enq.bits, _T_2587 node _T_2588 = eq(UInt<5>(0h1d), idx_26) when _T_2588 : node _T_2589 = shl(UInt<5>(0h1a), 3) node _T_2590 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2589) connect Queue10_UInt8_29.io.enq.bits, _T_2590 node _T_2591 = eq(UInt<5>(0h1e), idx_26) when _T_2591 : node _T_2592 = shl(UInt<5>(0h1a), 3) node _T_2593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2592) connect Queue10_UInt8_30.io.enq.bits, _T_2593 node _T_2594 = eq(UInt<5>(0h1f), idx_26) when _T_2594 : node _T_2595 = shl(UInt<5>(0h1a), 3) node _T_2596 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2595) connect Queue10_UInt8_31.io.enq.bits, _T_2596 node _idx_T_27 = add(write_start_index, UInt<5>(0h1b)) node idx_27 = rem(_idx_T_27, UInt<6>(0h20)) node _T_2597 = eq(UInt<1>(0h0), idx_27) when _T_2597 : node _T_2598 = shl(UInt<5>(0h1b), 3) node _T_2599 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2598) connect Queue10_UInt8.io.enq.bits, _T_2599 node _T_2600 = eq(UInt<1>(0h1), idx_27) when _T_2600 : node _T_2601 = shl(UInt<5>(0h1b), 3) node _T_2602 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2601) connect Queue10_UInt8_1.io.enq.bits, _T_2602 node _T_2603 = eq(UInt<2>(0h2), idx_27) when _T_2603 : node _T_2604 = shl(UInt<5>(0h1b), 3) node _T_2605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2604) connect Queue10_UInt8_2.io.enq.bits, _T_2605 node _T_2606 = eq(UInt<2>(0h3), idx_27) when _T_2606 : node _T_2607 = shl(UInt<5>(0h1b), 3) node _T_2608 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2607) connect Queue10_UInt8_3.io.enq.bits, _T_2608 node _T_2609 = eq(UInt<3>(0h4), idx_27) when _T_2609 : node _T_2610 = shl(UInt<5>(0h1b), 3) node _T_2611 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2610) connect Queue10_UInt8_4.io.enq.bits, _T_2611 node _T_2612 = eq(UInt<3>(0h5), idx_27) when _T_2612 : node _T_2613 = shl(UInt<5>(0h1b), 3) node _T_2614 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2613) connect Queue10_UInt8_5.io.enq.bits, _T_2614 node _T_2615 = eq(UInt<3>(0h6), idx_27) when _T_2615 : node _T_2616 = shl(UInt<5>(0h1b), 3) node _T_2617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2616) connect Queue10_UInt8_6.io.enq.bits, _T_2617 node _T_2618 = eq(UInt<3>(0h7), idx_27) when _T_2618 : node _T_2619 = shl(UInt<5>(0h1b), 3) node _T_2620 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2619) connect Queue10_UInt8_7.io.enq.bits, _T_2620 node _T_2621 = eq(UInt<4>(0h8), idx_27) when _T_2621 : node _T_2622 = shl(UInt<5>(0h1b), 3) node _T_2623 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2622) connect Queue10_UInt8_8.io.enq.bits, _T_2623 node _T_2624 = eq(UInt<4>(0h9), idx_27) when _T_2624 : node _T_2625 = shl(UInt<5>(0h1b), 3) node _T_2626 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2625) connect Queue10_UInt8_9.io.enq.bits, _T_2626 node _T_2627 = eq(UInt<4>(0ha), idx_27) when _T_2627 : node _T_2628 = shl(UInt<5>(0h1b), 3) node _T_2629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2628) connect Queue10_UInt8_10.io.enq.bits, _T_2629 node _T_2630 = eq(UInt<4>(0hb), idx_27) when _T_2630 : node _T_2631 = shl(UInt<5>(0h1b), 3) node _T_2632 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2631) connect Queue10_UInt8_11.io.enq.bits, _T_2632 node _T_2633 = eq(UInt<4>(0hc), idx_27) when _T_2633 : node _T_2634 = shl(UInt<5>(0h1b), 3) node _T_2635 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2634) connect Queue10_UInt8_12.io.enq.bits, _T_2635 node _T_2636 = eq(UInt<4>(0hd), idx_27) when _T_2636 : node _T_2637 = shl(UInt<5>(0h1b), 3) node _T_2638 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2637) connect Queue10_UInt8_13.io.enq.bits, _T_2638 node _T_2639 = eq(UInt<4>(0he), idx_27) when _T_2639 : node _T_2640 = shl(UInt<5>(0h1b), 3) node _T_2641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2640) connect Queue10_UInt8_14.io.enq.bits, _T_2641 node _T_2642 = eq(UInt<4>(0hf), idx_27) when _T_2642 : node _T_2643 = shl(UInt<5>(0h1b), 3) node _T_2644 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2643) connect Queue10_UInt8_15.io.enq.bits, _T_2644 node _T_2645 = eq(UInt<5>(0h10), idx_27) when _T_2645 : node _T_2646 = shl(UInt<5>(0h1b), 3) node _T_2647 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2646) connect Queue10_UInt8_16.io.enq.bits, _T_2647 node _T_2648 = eq(UInt<5>(0h11), idx_27) when _T_2648 : node _T_2649 = shl(UInt<5>(0h1b), 3) node _T_2650 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2649) connect Queue10_UInt8_17.io.enq.bits, _T_2650 node _T_2651 = eq(UInt<5>(0h12), idx_27) when _T_2651 : node _T_2652 = shl(UInt<5>(0h1b), 3) node _T_2653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2652) connect Queue10_UInt8_18.io.enq.bits, _T_2653 node _T_2654 = eq(UInt<5>(0h13), idx_27) when _T_2654 : node _T_2655 = shl(UInt<5>(0h1b), 3) node _T_2656 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2655) connect Queue10_UInt8_19.io.enq.bits, _T_2656 node _T_2657 = eq(UInt<5>(0h14), idx_27) when _T_2657 : node _T_2658 = shl(UInt<5>(0h1b), 3) node _T_2659 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2658) connect Queue10_UInt8_20.io.enq.bits, _T_2659 node _T_2660 = eq(UInt<5>(0h15), idx_27) when _T_2660 : node _T_2661 = shl(UInt<5>(0h1b), 3) node _T_2662 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2661) connect Queue10_UInt8_21.io.enq.bits, _T_2662 node _T_2663 = eq(UInt<5>(0h16), idx_27) when _T_2663 : node _T_2664 = shl(UInt<5>(0h1b), 3) node _T_2665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2664) connect Queue10_UInt8_22.io.enq.bits, _T_2665 node _T_2666 = eq(UInt<5>(0h17), idx_27) when _T_2666 : node _T_2667 = shl(UInt<5>(0h1b), 3) node _T_2668 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2667) connect Queue10_UInt8_23.io.enq.bits, _T_2668 node _T_2669 = eq(UInt<5>(0h18), idx_27) when _T_2669 : node _T_2670 = shl(UInt<5>(0h1b), 3) node _T_2671 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2670) connect Queue10_UInt8_24.io.enq.bits, _T_2671 node _T_2672 = eq(UInt<5>(0h19), idx_27) when _T_2672 : node _T_2673 = shl(UInt<5>(0h1b), 3) node _T_2674 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2673) connect Queue10_UInt8_25.io.enq.bits, _T_2674 node _T_2675 = eq(UInt<5>(0h1a), idx_27) when _T_2675 : node _T_2676 = shl(UInt<5>(0h1b), 3) node _T_2677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2676) connect Queue10_UInt8_26.io.enq.bits, _T_2677 node _T_2678 = eq(UInt<5>(0h1b), idx_27) when _T_2678 : node _T_2679 = shl(UInt<5>(0h1b), 3) node _T_2680 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2679) connect Queue10_UInt8_27.io.enq.bits, _T_2680 node _T_2681 = eq(UInt<5>(0h1c), idx_27) when _T_2681 : node _T_2682 = shl(UInt<5>(0h1b), 3) node _T_2683 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2682) connect Queue10_UInt8_28.io.enq.bits, _T_2683 node _T_2684 = eq(UInt<5>(0h1d), idx_27) when _T_2684 : node _T_2685 = shl(UInt<5>(0h1b), 3) node _T_2686 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2685) connect Queue10_UInt8_29.io.enq.bits, _T_2686 node _T_2687 = eq(UInt<5>(0h1e), idx_27) when _T_2687 : node _T_2688 = shl(UInt<5>(0h1b), 3) node _T_2689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2688) connect Queue10_UInt8_30.io.enq.bits, _T_2689 node _T_2690 = eq(UInt<5>(0h1f), idx_27) when _T_2690 : node _T_2691 = shl(UInt<5>(0h1b), 3) node _T_2692 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2691) connect Queue10_UInt8_31.io.enq.bits, _T_2692 node _idx_T_28 = add(write_start_index, UInt<5>(0h1c)) node idx_28 = rem(_idx_T_28, UInt<6>(0h20)) node _T_2693 = eq(UInt<1>(0h0), idx_28) when _T_2693 : node _T_2694 = shl(UInt<5>(0h1c), 3) node _T_2695 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2694) connect Queue10_UInt8.io.enq.bits, _T_2695 node _T_2696 = eq(UInt<1>(0h1), idx_28) when _T_2696 : node _T_2697 = shl(UInt<5>(0h1c), 3) node _T_2698 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2697) connect Queue10_UInt8_1.io.enq.bits, _T_2698 node _T_2699 = eq(UInt<2>(0h2), idx_28) when _T_2699 : node _T_2700 = shl(UInt<5>(0h1c), 3) node _T_2701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2700) connect Queue10_UInt8_2.io.enq.bits, _T_2701 node _T_2702 = eq(UInt<2>(0h3), idx_28) when _T_2702 : node _T_2703 = shl(UInt<5>(0h1c), 3) node _T_2704 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2703) connect Queue10_UInt8_3.io.enq.bits, _T_2704 node _T_2705 = eq(UInt<3>(0h4), idx_28) when _T_2705 : node _T_2706 = shl(UInt<5>(0h1c), 3) node _T_2707 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2706) connect Queue10_UInt8_4.io.enq.bits, _T_2707 node _T_2708 = eq(UInt<3>(0h5), idx_28) when _T_2708 : node _T_2709 = shl(UInt<5>(0h1c), 3) node _T_2710 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2709) connect Queue10_UInt8_5.io.enq.bits, _T_2710 node _T_2711 = eq(UInt<3>(0h6), idx_28) when _T_2711 : node _T_2712 = shl(UInt<5>(0h1c), 3) node _T_2713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2712) connect Queue10_UInt8_6.io.enq.bits, _T_2713 node _T_2714 = eq(UInt<3>(0h7), idx_28) when _T_2714 : node _T_2715 = shl(UInt<5>(0h1c), 3) node _T_2716 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2715) connect Queue10_UInt8_7.io.enq.bits, _T_2716 node _T_2717 = eq(UInt<4>(0h8), idx_28) when _T_2717 : node _T_2718 = shl(UInt<5>(0h1c), 3) node _T_2719 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2718) connect Queue10_UInt8_8.io.enq.bits, _T_2719 node _T_2720 = eq(UInt<4>(0h9), idx_28) when _T_2720 : node _T_2721 = shl(UInt<5>(0h1c), 3) node _T_2722 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2721) connect Queue10_UInt8_9.io.enq.bits, _T_2722 node _T_2723 = eq(UInt<4>(0ha), idx_28) when _T_2723 : node _T_2724 = shl(UInt<5>(0h1c), 3) node _T_2725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2724) connect Queue10_UInt8_10.io.enq.bits, _T_2725 node _T_2726 = eq(UInt<4>(0hb), idx_28) when _T_2726 : node _T_2727 = shl(UInt<5>(0h1c), 3) node _T_2728 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2727) connect Queue10_UInt8_11.io.enq.bits, _T_2728 node _T_2729 = eq(UInt<4>(0hc), idx_28) when _T_2729 : node _T_2730 = shl(UInt<5>(0h1c), 3) node _T_2731 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2730) connect Queue10_UInt8_12.io.enq.bits, _T_2731 node _T_2732 = eq(UInt<4>(0hd), idx_28) when _T_2732 : node _T_2733 = shl(UInt<5>(0h1c), 3) node _T_2734 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2733) connect Queue10_UInt8_13.io.enq.bits, _T_2734 node _T_2735 = eq(UInt<4>(0he), idx_28) when _T_2735 : node _T_2736 = shl(UInt<5>(0h1c), 3) node _T_2737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2736) connect Queue10_UInt8_14.io.enq.bits, _T_2737 node _T_2738 = eq(UInt<4>(0hf), idx_28) when _T_2738 : node _T_2739 = shl(UInt<5>(0h1c), 3) node _T_2740 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2739) connect Queue10_UInt8_15.io.enq.bits, _T_2740 node _T_2741 = eq(UInt<5>(0h10), idx_28) when _T_2741 : node _T_2742 = shl(UInt<5>(0h1c), 3) node _T_2743 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2742) connect Queue10_UInt8_16.io.enq.bits, _T_2743 node _T_2744 = eq(UInt<5>(0h11), idx_28) when _T_2744 : node _T_2745 = shl(UInt<5>(0h1c), 3) node _T_2746 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2745) connect Queue10_UInt8_17.io.enq.bits, _T_2746 node _T_2747 = eq(UInt<5>(0h12), idx_28) when _T_2747 : node _T_2748 = shl(UInt<5>(0h1c), 3) node _T_2749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2748) connect Queue10_UInt8_18.io.enq.bits, _T_2749 node _T_2750 = eq(UInt<5>(0h13), idx_28) when _T_2750 : node _T_2751 = shl(UInt<5>(0h1c), 3) node _T_2752 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2751) connect Queue10_UInt8_19.io.enq.bits, _T_2752 node _T_2753 = eq(UInt<5>(0h14), idx_28) when _T_2753 : node _T_2754 = shl(UInt<5>(0h1c), 3) node _T_2755 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2754) connect Queue10_UInt8_20.io.enq.bits, _T_2755 node _T_2756 = eq(UInt<5>(0h15), idx_28) when _T_2756 : node _T_2757 = shl(UInt<5>(0h1c), 3) node _T_2758 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2757) connect Queue10_UInt8_21.io.enq.bits, _T_2758 node _T_2759 = eq(UInt<5>(0h16), idx_28) when _T_2759 : node _T_2760 = shl(UInt<5>(0h1c), 3) node _T_2761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2760) connect Queue10_UInt8_22.io.enq.bits, _T_2761 node _T_2762 = eq(UInt<5>(0h17), idx_28) when _T_2762 : node _T_2763 = shl(UInt<5>(0h1c), 3) node _T_2764 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2763) connect Queue10_UInt8_23.io.enq.bits, _T_2764 node _T_2765 = eq(UInt<5>(0h18), idx_28) when _T_2765 : node _T_2766 = shl(UInt<5>(0h1c), 3) node _T_2767 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2766) connect Queue10_UInt8_24.io.enq.bits, _T_2767 node _T_2768 = eq(UInt<5>(0h19), idx_28) when _T_2768 : node _T_2769 = shl(UInt<5>(0h1c), 3) node _T_2770 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2769) connect Queue10_UInt8_25.io.enq.bits, _T_2770 node _T_2771 = eq(UInt<5>(0h1a), idx_28) when _T_2771 : node _T_2772 = shl(UInt<5>(0h1c), 3) node _T_2773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2772) connect Queue10_UInt8_26.io.enq.bits, _T_2773 node _T_2774 = eq(UInt<5>(0h1b), idx_28) when _T_2774 : node _T_2775 = shl(UInt<5>(0h1c), 3) node _T_2776 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2775) connect Queue10_UInt8_27.io.enq.bits, _T_2776 node _T_2777 = eq(UInt<5>(0h1c), idx_28) when _T_2777 : node _T_2778 = shl(UInt<5>(0h1c), 3) node _T_2779 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2778) connect Queue10_UInt8_28.io.enq.bits, _T_2779 node _T_2780 = eq(UInt<5>(0h1d), idx_28) when _T_2780 : node _T_2781 = shl(UInt<5>(0h1c), 3) node _T_2782 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2781) connect Queue10_UInt8_29.io.enq.bits, _T_2782 node _T_2783 = eq(UInt<5>(0h1e), idx_28) when _T_2783 : node _T_2784 = shl(UInt<5>(0h1c), 3) node _T_2785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2784) connect Queue10_UInt8_30.io.enq.bits, _T_2785 node _T_2786 = eq(UInt<5>(0h1f), idx_28) when _T_2786 : node _T_2787 = shl(UInt<5>(0h1c), 3) node _T_2788 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2787) connect Queue10_UInt8_31.io.enq.bits, _T_2788 node _idx_T_29 = add(write_start_index, UInt<5>(0h1d)) node idx_29 = rem(_idx_T_29, UInt<6>(0h20)) node _T_2789 = eq(UInt<1>(0h0), idx_29) when _T_2789 : node _T_2790 = shl(UInt<5>(0h1d), 3) node _T_2791 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2790) connect Queue10_UInt8.io.enq.bits, _T_2791 node _T_2792 = eq(UInt<1>(0h1), idx_29) when _T_2792 : node _T_2793 = shl(UInt<5>(0h1d), 3) node _T_2794 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2793) connect Queue10_UInt8_1.io.enq.bits, _T_2794 node _T_2795 = eq(UInt<2>(0h2), idx_29) when _T_2795 : node _T_2796 = shl(UInt<5>(0h1d), 3) node _T_2797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2796) connect Queue10_UInt8_2.io.enq.bits, _T_2797 node _T_2798 = eq(UInt<2>(0h3), idx_29) when _T_2798 : node _T_2799 = shl(UInt<5>(0h1d), 3) node _T_2800 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2799) connect Queue10_UInt8_3.io.enq.bits, _T_2800 node _T_2801 = eq(UInt<3>(0h4), idx_29) when _T_2801 : node _T_2802 = shl(UInt<5>(0h1d), 3) node _T_2803 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2802) connect Queue10_UInt8_4.io.enq.bits, _T_2803 node _T_2804 = eq(UInt<3>(0h5), idx_29) when _T_2804 : node _T_2805 = shl(UInt<5>(0h1d), 3) node _T_2806 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2805) connect Queue10_UInt8_5.io.enq.bits, _T_2806 node _T_2807 = eq(UInt<3>(0h6), idx_29) when _T_2807 : node _T_2808 = shl(UInt<5>(0h1d), 3) node _T_2809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2808) connect Queue10_UInt8_6.io.enq.bits, _T_2809 node _T_2810 = eq(UInt<3>(0h7), idx_29) when _T_2810 : node _T_2811 = shl(UInt<5>(0h1d), 3) node _T_2812 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2811) connect Queue10_UInt8_7.io.enq.bits, _T_2812 node _T_2813 = eq(UInt<4>(0h8), idx_29) when _T_2813 : node _T_2814 = shl(UInt<5>(0h1d), 3) node _T_2815 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2814) connect Queue10_UInt8_8.io.enq.bits, _T_2815 node _T_2816 = eq(UInt<4>(0h9), idx_29) when _T_2816 : node _T_2817 = shl(UInt<5>(0h1d), 3) node _T_2818 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2817) connect Queue10_UInt8_9.io.enq.bits, _T_2818 node _T_2819 = eq(UInt<4>(0ha), idx_29) when _T_2819 : node _T_2820 = shl(UInt<5>(0h1d), 3) node _T_2821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2820) connect Queue10_UInt8_10.io.enq.bits, _T_2821 node _T_2822 = eq(UInt<4>(0hb), idx_29) when _T_2822 : node _T_2823 = shl(UInt<5>(0h1d), 3) node _T_2824 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2823) connect Queue10_UInt8_11.io.enq.bits, _T_2824 node _T_2825 = eq(UInt<4>(0hc), idx_29) when _T_2825 : node _T_2826 = shl(UInt<5>(0h1d), 3) node _T_2827 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2826) connect Queue10_UInt8_12.io.enq.bits, _T_2827 node _T_2828 = eq(UInt<4>(0hd), idx_29) when _T_2828 : node _T_2829 = shl(UInt<5>(0h1d), 3) node _T_2830 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2829) connect Queue10_UInt8_13.io.enq.bits, _T_2830 node _T_2831 = eq(UInt<4>(0he), idx_29) when _T_2831 : node _T_2832 = shl(UInt<5>(0h1d), 3) node _T_2833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2832) connect Queue10_UInt8_14.io.enq.bits, _T_2833 node _T_2834 = eq(UInt<4>(0hf), idx_29) when _T_2834 : node _T_2835 = shl(UInt<5>(0h1d), 3) node _T_2836 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2835) connect Queue10_UInt8_15.io.enq.bits, _T_2836 node _T_2837 = eq(UInt<5>(0h10), idx_29) when _T_2837 : node _T_2838 = shl(UInt<5>(0h1d), 3) node _T_2839 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2838) connect Queue10_UInt8_16.io.enq.bits, _T_2839 node _T_2840 = eq(UInt<5>(0h11), idx_29) when _T_2840 : node _T_2841 = shl(UInt<5>(0h1d), 3) node _T_2842 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2841) connect Queue10_UInt8_17.io.enq.bits, _T_2842 node _T_2843 = eq(UInt<5>(0h12), idx_29) when _T_2843 : node _T_2844 = shl(UInt<5>(0h1d), 3) node _T_2845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2844) connect Queue10_UInt8_18.io.enq.bits, _T_2845 node _T_2846 = eq(UInt<5>(0h13), idx_29) when _T_2846 : node _T_2847 = shl(UInt<5>(0h1d), 3) node _T_2848 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2847) connect Queue10_UInt8_19.io.enq.bits, _T_2848 node _T_2849 = eq(UInt<5>(0h14), idx_29) when _T_2849 : node _T_2850 = shl(UInt<5>(0h1d), 3) node _T_2851 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2850) connect Queue10_UInt8_20.io.enq.bits, _T_2851 node _T_2852 = eq(UInt<5>(0h15), idx_29) when _T_2852 : node _T_2853 = shl(UInt<5>(0h1d), 3) node _T_2854 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2853) connect Queue10_UInt8_21.io.enq.bits, _T_2854 node _T_2855 = eq(UInt<5>(0h16), idx_29) when _T_2855 : node _T_2856 = shl(UInt<5>(0h1d), 3) node _T_2857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2856) connect Queue10_UInt8_22.io.enq.bits, _T_2857 node _T_2858 = eq(UInt<5>(0h17), idx_29) when _T_2858 : node _T_2859 = shl(UInt<5>(0h1d), 3) node _T_2860 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2859) connect Queue10_UInt8_23.io.enq.bits, _T_2860 node _T_2861 = eq(UInt<5>(0h18), idx_29) when _T_2861 : node _T_2862 = shl(UInt<5>(0h1d), 3) node _T_2863 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2862) connect Queue10_UInt8_24.io.enq.bits, _T_2863 node _T_2864 = eq(UInt<5>(0h19), idx_29) when _T_2864 : node _T_2865 = shl(UInt<5>(0h1d), 3) node _T_2866 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2865) connect Queue10_UInt8_25.io.enq.bits, _T_2866 node _T_2867 = eq(UInt<5>(0h1a), idx_29) when _T_2867 : node _T_2868 = shl(UInt<5>(0h1d), 3) node _T_2869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2868) connect Queue10_UInt8_26.io.enq.bits, _T_2869 node _T_2870 = eq(UInt<5>(0h1b), idx_29) when _T_2870 : node _T_2871 = shl(UInt<5>(0h1d), 3) node _T_2872 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2871) connect Queue10_UInt8_27.io.enq.bits, _T_2872 node _T_2873 = eq(UInt<5>(0h1c), idx_29) when _T_2873 : node _T_2874 = shl(UInt<5>(0h1d), 3) node _T_2875 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2874) connect Queue10_UInt8_28.io.enq.bits, _T_2875 node _T_2876 = eq(UInt<5>(0h1d), idx_29) when _T_2876 : node _T_2877 = shl(UInt<5>(0h1d), 3) node _T_2878 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2877) connect Queue10_UInt8_29.io.enq.bits, _T_2878 node _T_2879 = eq(UInt<5>(0h1e), idx_29) when _T_2879 : node _T_2880 = shl(UInt<5>(0h1d), 3) node _T_2881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2880) connect Queue10_UInt8_30.io.enq.bits, _T_2881 node _T_2882 = eq(UInt<5>(0h1f), idx_29) when _T_2882 : node _T_2883 = shl(UInt<5>(0h1d), 3) node _T_2884 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2883) connect Queue10_UInt8_31.io.enq.bits, _T_2884 node _idx_T_30 = add(write_start_index, UInt<5>(0h1e)) node idx_30 = rem(_idx_T_30, UInt<6>(0h20)) node _T_2885 = eq(UInt<1>(0h0), idx_30) when _T_2885 : node _T_2886 = shl(UInt<5>(0h1e), 3) node _T_2887 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2886) connect Queue10_UInt8.io.enq.bits, _T_2887 node _T_2888 = eq(UInt<1>(0h1), idx_30) when _T_2888 : node _T_2889 = shl(UInt<5>(0h1e), 3) node _T_2890 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2889) connect Queue10_UInt8_1.io.enq.bits, _T_2890 node _T_2891 = eq(UInt<2>(0h2), idx_30) when _T_2891 : node _T_2892 = shl(UInt<5>(0h1e), 3) node _T_2893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2892) connect Queue10_UInt8_2.io.enq.bits, _T_2893 node _T_2894 = eq(UInt<2>(0h3), idx_30) when _T_2894 : node _T_2895 = shl(UInt<5>(0h1e), 3) node _T_2896 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2895) connect Queue10_UInt8_3.io.enq.bits, _T_2896 node _T_2897 = eq(UInt<3>(0h4), idx_30) when _T_2897 : node _T_2898 = shl(UInt<5>(0h1e), 3) node _T_2899 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2898) connect Queue10_UInt8_4.io.enq.bits, _T_2899 node _T_2900 = eq(UInt<3>(0h5), idx_30) when _T_2900 : node _T_2901 = shl(UInt<5>(0h1e), 3) node _T_2902 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2901) connect Queue10_UInt8_5.io.enq.bits, _T_2902 node _T_2903 = eq(UInt<3>(0h6), idx_30) when _T_2903 : node _T_2904 = shl(UInt<5>(0h1e), 3) node _T_2905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2904) connect Queue10_UInt8_6.io.enq.bits, _T_2905 node _T_2906 = eq(UInt<3>(0h7), idx_30) when _T_2906 : node _T_2907 = shl(UInt<5>(0h1e), 3) node _T_2908 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2907) connect Queue10_UInt8_7.io.enq.bits, _T_2908 node _T_2909 = eq(UInt<4>(0h8), idx_30) when _T_2909 : node _T_2910 = shl(UInt<5>(0h1e), 3) node _T_2911 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2910) connect Queue10_UInt8_8.io.enq.bits, _T_2911 node _T_2912 = eq(UInt<4>(0h9), idx_30) when _T_2912 : node _T_2913 = shl(UInt<5>(0h1e), 3) node _T_2914 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2913) connect Queue10_UInt8_9.io.enq.bits, _T_2914 node _T_2915 = eq(UInt<4>(0ha), idx_30) when _T_2915 : node _T_2916 = shl(UInt<5>(0h1e), 3) node _T_2917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2916) connect Queue10_UInt8_10.io.enq.bits, _T_2917 node _T_2918 = eq(UInt<4>(0hb), idx_30) when _T_2918 : node _T_2919 = shl(UInt<5>(0h1e), 3) node _T_2920 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2919) connect Queue10_UInt8_11.io.enq.bits, _T_2920 node _T_2921 = eq(UInt<4>(0hc), idx_30) when _T_2921 : node _T_2922 = shl(UInt<5>(0h1e), 3) node _T_2923 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2922) connect Queue10_UInt8_12.io.enq.bits, _T_2923 node _T_2924 = eq(UInt<4>(0hd), idx_30) when _T_2924 : node _T_2925 = shl(UInt<5>(0h1e), 3) node _T_2926 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2925) connect Queue10_UInt8_13.io.enq.bits, _T_2926 node _T_2927 = eq(UInt<4>(0he), idx_30) when _T_2927 : node _T_2928 = shl(UInt<5>(0h1e), 3) node _T_2929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2928) connect Queue10_UInt8_14.io.enq.bits, _T_2929 node _T_2930 = eq(UInt<4>(0hf), idx_30) when _T_2930 : node _T_2931 = shl(UInt<5>(0h1e), 3) node _T_2932 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2931) connect Queue10_UInt8_15.io.enq.bits, _T_2932 node _T_2933 = eq(UInt<5>(0h10), idx_30) when _T_2933 : node _T_2934 = shl(UInt<5>(0h1e), 3) node _T_2935 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2934) connect Queue10_UInt8_16.io.enq.bits, _T_2935 node _T_2936 = eq(UInt<5>(0h11), idx_30) when _T_2936 : node _T_2937 = shl(UInt<5>(0h1e), 3) node _T_2938 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2937) connect Queue10_UInt8_17.io.enq.bits, _T_2938 node _T_2939 = eq(UInt<5>(0h12), idx_30) when _T_2939 : node _T_2940 = shl(UInt<5>(0h1e), 3) node _T_2941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2940) connect Queue10_UInt8_18.io.enq.bits, _T_2941 node _T_2942 = eq(UInt<5>(0h13), idx_30) when _T_2942 : node _T_2943 = shl(UInt<5>(0h1e), 3) node _T_2944 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2943) connect Queue10_UInt8_19.io.enq.bits, _T_2944 node _T_2945 = eq(UInt<5>(0h14), idx_30) when _T_2945 : node _T_2946 = shl(UInt<5>(0h1e), 3) node _T_2947 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2946) connect Queue10_UInt8_20.io.enq.bits, _T_2947 node _T_2948 = eq(UInt<5>(0h15), idx_30) when _T_2948 : node _T_2949 = shl(UInt<5>(0h1e), 3) node _T_2950 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2949) connect Queue10_UInt8_21.io.enq.bits, _T_2950 node _T_2951 = eq(UInt<5>(0h16), idx_30) when _T_2951 : node _T_2952 = shl(UInt<5>(0h1e), 3) node _T_2953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2952) connect Queue10_UInt8_22.io.enq.bits, _T_2953 node _T_2954 = eq(UInt<5>(0h17), idx_30) when _T_2954 : node _T_2955 = shl(UInt<5>(0h1e), 3) node _T_2956 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2955) connect Queue10_UInt8_23.io.enq.bits, _T_2956 node _T_2957 = eq(UInt<5>(0h18), idx_30) when _T_2957 : node _T_2958 = shl(UInt<5>(0h1e), 3) node _T_2959 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2958) connect Queue10_UInt8_24.io.enq.bits, _T_2959 node _T_2960 = eq(UInt<5>(0h19), idx_30) when _T_2960 : node _T_2961 = shl(UInt<5>(0h1e), 3) node _T_2962 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2961) connect Queue10_UInt8_25.io.enq.bits, _T_2962 node _T_2963 = eq(UInt<5>(0h1a), idx_30) when _T_2963 : node _T_2964 = shl(UInt<5>(0h1e), 3) node _T_2965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2964) connect Queue10_UInt8_26.io.enq.bits, _T_2965 node _T_2966 = eq(UInt<5>(0h1b), idx_30) when _T_2966 : node _T_2967 = shl(UInt<5>(0h1e), 3) node _T_2968 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2967) connect Queue10_UInt8_27.io.enq.bits, _T_2968 node _T_2969 = eq(UInt<5>(0h1c), idx_30) when _T_2969 : node _T_2970 = shl(UInt<5>(0h1e), 3) node _T_2971 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2970) connect Queue10_UInt8_28.io.enq.bits, _T_2971 node _T_2972 = eq(UInt<5>(0h1d), idx_30) when _T_2972 : node _T_2973 = shl(UInt<5>(0h1e), 3) node _T_2974 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2973) connect Queue10_UInt8_29.io.enq.bits, _T_2974 node _T_2975 = eq(UInt<5>(0h1e), idx_30) when _T_2975 : node _T_2976 = shl(UInt<5>(0h1e), 3) node _T_2977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2976) connect Queue10_UInt8_30.io.enq.bits, _T_2977 node _T_2978 = eq(UInt<5>(0h1f), idx_30) when _T_2978 : node _T_2979 = shl(UInt<5>(0h1e), 3) node _T_2980 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2979) connect Queue10_UInt8_31.io.enq.bits, _T_2980 node _idx_T_31 = add(write_start_index, UInt<5>(0h1f)) node idx_31 = rem(_idx_T_31, UInt<6>(0h20)) node _T_2981 = eq(UInt<1>(0h0), idx_31) when _T_2981 : node _T_2982 = shl(UInt<5>(0h1f), 3) node _T_2983 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2982) connect Queue10_UInt8.io.enq.bits, _T_2983 node _T_2984 = eq(UInt<1>(0h1), idx_31) when _T_2984 : node _T_2985 = shl(UInt<5>(0h1f), 3) node _T_2986 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2985) connect Queue10_UInt8_1.io.enq.bits, _T_2986 node _T_2987 = eq(UInt<2>(0h2), idx_31) when _T_2987 : node _T_2988 = shl(UInt<5>(0h1f), 3) node _T_2989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2988) connect Queue10_UInt8_2.io.enq.bits, _T_2989 node _T_2990 = eq(UInt<2>(0h3), idx_31) when _T_2990 : node _T_2991 = shl(UInt<5>(0h1f), 3) node _T_2992 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2991) connect Queue10_UInt8_3.io.enq.bits, _T_2992 node _T_2993 = eq(UInt<3>(0h4), idx_31) when _T_2993 : node _T_2994 = shl(UInt<5>(0h1f), 3) node _T_2995 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2994) connect Queue10_UInt8_4.io.enq.bits, _T_2995 node _T_2996 = eq(UInt<3>(0h5), idx_31) when _T_2996 : node _T_2997 = shl(UInt<5>(0h1f), 3) node _T_2998 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2997) connect Queue10_UInt8_5.io.enq.bits, _T_2998 node _T_2999 = eq(UInt<3>(0h6), idx_31) when _T_2999 : node _T_3000 = shl(UInt<5>(0h1f), 3) node _T_3001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3000) connect Queue10_UInt8_6.io.enq.bits, _T_3001 node _T_3002 = eq(UInt<3>(0h7), idx_31) when _T_3002 : node _T_3003 = shl(UInt<5>(0h1f), 3) node _T_3004 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3003) connect Queue10_UInt8_7.io.enq.bits, _T_3004 node _T_3005 = eq(UInt<4>(0h8), idx_31) when _T_3005 : node _T_3006 = shl(UInt<5>(0h1f), 3) node _T_3007 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3006) connect Queue10_UInt8_8.io.enq.bits, _T_3007 node _T_3008 = eq(UInt<4>(0h9), idx_31) when _T_3008 : node _T_3009 = shl(UInt<5>(0h1f), 3) node _T_3010 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3009) connect Queue10_UInt8_9.io.enq.bits, _T_3010 node _T_3011 = eq(UInt<4>(0ha), idx_31) when _T_3011 : node _T_3012 = shl(UInt<5>(0h1f), 3) node _T_3013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3012) connect Queue10_UInt8_10.io.enq.bits, _T_3013 node _T_3014 = eq(UInt<4>(0hb), idx_31) when _T_3014 : node _T_3015 = shl(UInt<5>(0h1f), 3) node _T_3016 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3015) connect Queue10_UInt8_11.io.enq.bits, _T_3016 node _T_3017 = eq(UInt<4>(0hc), idx_31) when _T_3017 : node _T_3018 = shl(UInt<5>(0h1f), 3) node _T_3019 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3018) connect Queue10_UInt8_12.io.enq.bits, _T_3019 node _T_3020 = eq(UInt<4>(0hd), idx_31) when _T_3020 : node _T_3021 = shl(UInt<5>(0h1f), 3) node _T_3022 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3021) connect Queue10_UInt8_13.io.enq.bits, _T_3022 node _T_3023 = eq(UInt<4>(0he), idx_31) when _T_3023 : node _T_3024 = shl(UInt<5>(0h1f), 3) node _T_3025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3024) connect Queue10_UInt8_14.io.enq.bits, _T_3025 node _T_3026 = eq(UInt<4>(0hf), idx_31) when _T_3026 : node _T_3027 = shl(UInt<5>(0h1f), 3) node _T_3028 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3027) connect Queue10_UInt8_15.io.enq.bits, _T_3028 node _T_3029 = eq(UInt<5>(0h10), idx_31) when _T_3029 : node _T_3030 = shl(UInt<5>(0h1f), 3) node _T_3031 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3030) connect Queue10_UInt8_16.io.enq.bits, _T_3031 node _T_3032 = eq(UInt<5>(0h11), idx_31) when _T_3032 : node _T_3033 = shl(UInt<5>(0h1f), 3) node _T_3034 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3033) connect Queue10_UInt8_17.io.enq.bits, _T_3034 node _T_3035 = eq(UInt<5>(0h12), idx_31) when _T_3035 : node _T_3036 = shl(UInt<5>(0h1f), 3) node _T_3037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3036) connect Queue10_UInt8_18.io.enq.bits, _T_3037 node _T_3038 = eq(UInt<5>(0h13), idx_31) when _T_3038 : node _T_3039 = shl(UInt<5>(0h1f), 3) node _T_3040 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3039) connect Queue10_UInt8_19.io.enq.bits, _T_3040 node _T_3041 = eq(UInt<5>(0h14), idx_31) when _T_3041 : node _T_3042 = shl(UInt<5>(0h1f), 3) node _T_3043 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3042) connect Queue10_UInt8_20.io.enq.bits, _T_3043 node _T_3044 = eq(UInt<5>(0h15), idx_31) when _T_3044 : node _T_3045 = shl(UInt<5>(0h1f), 3) node _T_3046 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3045) connect Queue10_UInt8_21.io.enq.bits, _T_3046 node _T_3047 = eq(UInt<5>(0h16), idx_31) when _T_3047 : node _T_3048 = shl(UInt<5>(0h1f), 3) node _T_3049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3048) connect Queue10_UInt8_22.io.enq.bits, _T_3049 node _T_3050 = eq(UInt<5>(0h17), idx_31) when _T_3050 : node _T_3051 = shl(UInt<5>(0h1f), 3) node _T_3052 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3051) connect Queue10_UInt8_23.io.enq.bits, _T_3052 node _T_3053 = eq(UInt<5>(0h18), idx_31) when _T_3053 : node _T_3054 = shl(UInt<5>(0h1f), 3) node _T_3055 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3054) connect Queue10_UInt8_24.io.enq.bits, _T_3055 node _T_3056 = eq(UInt<5>(0h19), idx_31) when _T_3056 : node _T_3057 = shl(UInt<5>(0h1f), 3) node _T_3058 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3057) connect Queue10_UInt8_25.io.enq.bits, _T_3058 node _T_3059 = eq(UInt<5>(0h1a), idx_31) when _T_3059 : node _T_3060 = shl(UInt<5>(0h1f), 3) node _T_3061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3060) connect Queue10_UInt8_26.io.enq.bits, _T_3061 node _T_3062 = eq(UInt<5>(0h1b), idx_31) when _T_3062 : node _T_3063 = shl(UInt<5>(0h1f), 3) node _T_3064 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3063) connect Queue10_UInt8_27.io.enq.bits, _T_3064 node _T_3065 = eq(UInt<5>(0h1c), idx_31) when _T_3065 : node _T_3066 = shl(UInt<5>(0h1f), 3) node _T_3067 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3066) connect Queue10_UInt8_28.io.enq.bits, _T_3067 node _T_3068 = eq(UInt<5>(0h1d), idx_31) when _T_3068 : node _T_3069 = shl(UInt<5>(0h1f), 3) node _T_3070 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3069) connect Queue10_UInt8_29.io.enq.bits, _T_3070 node _T_3071 = eq(UInt<5>(0h1e), idx_31) when _T_3071 : node _T_3072 = shl(UInt<5>(0h1f), 3) node _T_3073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3072) connect Queue10_UInt8_30.io.enq.bits, _T_3073 node _T_3074 = eq(UInt<5>(0h1f), idx_31) when _T_3074 : node _T_3075 = shl(UInt<5>(0h1f), 3) node _T_3076 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3075) connect Queue10_UInt8_31.io.enq.bits, _T_3076 node wrap_len_index_wide = add(write_start_index, incoming_writes_Q.io.deq.bits.validbytes) node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20)) node wrapped = geq(wrap_len_index_wide, UInt<6>(0h20)) node _all_queues_ready_T = and(Queue10_UInt8.io.enq.ready, Queue10_UInt8_1.io.enq.ready) node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue10_UInt8_2.io.enq.ready) node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue10_UInt8_3.io.enq.ready) node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue10_UInt8_4.io.enq.ready) node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue10_UInt8_5.io.enq.ready) node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue10_UInt8_6.io.enq.ready) node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue10_UInt8_7.io.enq.ready) node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue10_UInt8_8.io.enq.ready) node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue10_UInt8_9.io.enq.ready) node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue10_UInt8_10.io.enq.ready) node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue10_UInt8_11.io.enq.ready) node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue10_UInt8_12.io.enq.ready) node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue10_UInt8_13.io.enq.ready) node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue10_UInt8_14.io.enq.ready) node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue10_UInt8_15.io.enq.ready) node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue10_UInt8_16.io.enq.ready) node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue10_UInt8_17.io.enq.ready) node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue10_UInt8_18.io.enq.ready) node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue10_UInt8_19.io.enq.ready) node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue10_UInt8_20.io.enq.ready) node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue10_UInt8_21.io.enq.ready) node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue10_UInt8_22.io.enq.ready) node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue10_UInt8_23.io.enq.ready) node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue10_UInt8_24.io.enq.ready) node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue10_UInt8_25.io.enq.ready) node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue10_UInt8_26.io.enq.ready) node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue10_UInt8_27.io.enq.ready) node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue10_UInt8_28.io.enq.ready) node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue10_UInt8_29.io.enq.ready) node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue10_UInt8_30.io.enq.ready) node all_queues_ready = and(_all_queues_ready_T_29, Queue10_UInt8_31.io.enq.ready) connect incoming_writes_Q.io.deq.ready, all_queues_ready node _T_3077 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) when _T_3077 : connect write_start_index, wrap_len_index_end node _use_this_queue_T = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_1 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_2 = or(_use_this_queue_T, _use_this_queue_T_1) node _use_this_queue_T_3 = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_4 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_5 = and(_use_this_queue_T_3, _use_this_queue_T_4) node use_this_queue = mux(wrapped, _use_this_queue_T_2, _use_this_queue_T_5) node _T_3078 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3079 = and(_T_3078, use_this_queue) connect Queue10_UInt8.io.enq.valid, _T_3079 node _use_this_queue_T_6 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_7 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_8 = or(_use_this_queue_T_6, _use_this_queue_T_7) node _use_this_queue_T_9 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_10 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_11 = and(_use_this_queue_T_9, _use_this_queue_T_10) node use_this_queue_1 = mux(wrapped, _use_this_queue_T_8, _use_this_queue_T_11) node _T_3080 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3081 = and(_T_3080, use_this_queue_1) connect Queue10_UInt8_1.io.enq.valid, _T_3081 node _use_this_queue_T_12 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_13 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_14 = or(_use_this_queue_T_12, _use_this_queue_T_13) node _use_this_queue_T_15 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_16 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_17 = and(_use_this_queue_T_15, _use_this_queue_T_16) node use_this_queue_2 = mux(wrapped, _use_this_queue_T_14, _use_this_queue_T_17) node _T_3082 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3083 = and(_T_3082, use_this_queue_2) connect Queue10_UInt8_2.io.enq.valid, _T_3083 node _use_this_queue_T_18 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_19 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_20 = or(_use_this_queue_T_18, _use_this_queue_T_19) node _use_this_queue_T_21 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_22 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_23 = and(_use_this_queue_T_21, _use_this_queue_T_22) node use_this_queue_3 = mux(wrapped, _use_this_queue_T_20, _use_this_queue_T_23) node _T_3084 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3085 = and(_T_3084, use_this_queue_3) connect Queue10_UInt8_3.io.enq.valid, _T_3085 node _use_this_queue_T_24 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_25 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_26 = or(_use_this_queue_T_24, _use_this_queue_T_25) node _use_this_queue_T_27 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_28 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_29 = and(_use_this_queue_T_27, _use_this_queue_T_28) node use_this_queue_4 = mux(wrapped, _use_this_queue_T_26, _use_this_queue_T_29) node _T_3086 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3087 = and(_T_3086, use_this_queue_4) connect Queue10_UInt8_4.io.enq.valid, _T_3087 node _use_this_queue_T_30 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_31 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31) node _use_this_queue_T_33 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_34 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_35 = and(_use_this_queue_T_33, _use_this_queue_T_34) node use_this_queue_5 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_35) node _T_3088 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3089 = and(_T_3088, use_this_queue_5) connect Queue10_UInt8_5.io.enq.valid, _T_3089 node _use_this_queue_T_36 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_37 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_38 = or(_use_this_queue_T_36, _use_this_queue_T_37) node _use_this_queue_T_39 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_40 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_41 = and(_use_this_queue_T_39, _use_this_queue_T_40) node use_this_queue_6 = mux(wrapped, _use_this_queue_T_38, _use_this_queue_T_41) node _T_3090 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3091 = and(_T_3090, use_this_queue_6) connect Queue10_UInt8_6.io.enq.valid, _T_3091 node _use_this_queue_T_42 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_43 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_44 = or(_use_this_queue_T_42, _use_this_queue_T_43) node _use_this_queue_T_45 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_46 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_47 = and(_use_this_queue_T_45, _use_this_queue_T_46) node use_this_queue_7 = mux(wrapped, _use_this_queue_T_44, _use_this_queue_T_47) node _T_3092 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3093 = and(_T_3092, use_this_queue_7) connect Queue10_UInt8_7.io.enq.valid, _T_3093 node _use_this_queue_T_48 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_49 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_50 = or(_use_this_queue_T_48, _use_this_queue_T_49) node _use_this_queue_T_51 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_52 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_53 = and(_use_this_queue_T_51, _use_this_queue_T_52) node use_this_queue_8 = mux(wrapped, _use_this_queue_T_50, _use_this_queue_T_53) node _T_3094 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3095 = and(_T_3094, use_this_queue_8) connect Queue10_UInt8_8.io.enq.valid, _T_3095 node _use_this_queue_T_54 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_55 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_56 = or(_use_this_queue_T_54, _use_this_queue_T_55) node _use_this_queue_T_57 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_58 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_59 = and(_use_this_queue_T_57, _use_this_queue_T_58) node use_this_queue_9 = mux(wrapped, _use_this_queue_T_56, _use_this_queue_T_59) node _T_3096 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3097 = and(_T_3096, use_this_queue_9) connect Queue10_UInt8_9.io.enq.valid, _T_3097 node _use_this_queue_T_60 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_61 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_62 = or(_use_this_queue_T_60, _use_this_queue_T_61) node _use_this_queue_T_63 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_64 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_65 = and(_use_this_queue_T_63, _use_this_queue_T_64) node use_this_queue_10 = mux(wrapped, _use_this_queue_T_62, _use_this_queue_T_65) node _T_3098 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3099 = and(_T_3098, use_this_queue_10) connect Queue10_UInt8_10.io.enq.valid, _T_3099 node _use_this_queue_T_66 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_67 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_68 = or(_use_this_queue_T_66, _use_this_queue_T_67) node _use_this_queue_T_69 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_70 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_71 = and(_use_this_queue_T_69, _use_this_queue_T_70) node use_this_queue_11 = mux(wrapped, _use_this_queue_T_68, _use_this_queue_T_71) node _T_3100 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3101 = and(_T_3100, use_this_queue_11) connect Queue10_UInt8_11.io.enq.valid, _T_3101 node _use_this_queue_T_72 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_73 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73) node _use_this_queue_T_75 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_76 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_77 = and(_use_this_queue_T_75, _use_this_queue_T_76) node use_this_queue_12 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_77) node _T_3102 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3103 = and(_T_3102, use_this_queue_12) connect Queue10_UInt8_12.io.enq.valid, _T_3103 node _use_this_queue_T_78 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_79 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_80 = or(_use_this_queue_T_78, _use_this_queue_T_79) node _use_this_queue_T_81 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_82 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_83 = and(_use_this_queue_T_81, _use_this_queue_T_82) node use_this_queue_13 = mux(wrapped, _use_this_queue_T_80, _use_this_queue_T_83) node _T_3104 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3105 = and(_T_3104, use_this_queue_13) connect Queue10_UInt8_13.io.enq.valid, _T_3105 node _use_this_queue_T_84 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_85 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_86 = or(_use_this_queue_T_84, _use_this_queue_T_85) node _use_this_queue_T_87 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_88 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_89 = and(_use_this_queue_T_87, _use_this_queue_T_88) node use_this_queue_14 = mux(wrapped, _use_this_queue_T_86, _use_this_queue_T_89) node _T_3106 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3107 = and(_T_3106, use_this_queue_14) connect Queue10_UInt8_14.io.enq.valid, _T_3107 node _use_this_queue_T_90 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_91 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_92 = or(_use_this_queue_T_90, _use_this_queue_T_91) node _use_this_queue_T_93 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_94 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_95 = and(_use_this_queue_T_93, _use_this_queue_T_94) node use_this_queue_15 = mux(wrapped, _use_this_queue_T_92, _use_this_queue_T_95) node _T_3108 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3109 = and(_T_3108, use_this_queue_15) connect Queue10_UInt8_15.io.enq.valid, _T_3109 node _use_this_queue_T_96 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_97 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_98 = or(_use_this_queue_T_96, _use_this_queue_T_97) node _use_this_queue_T_99 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_100 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_101 = and(_use_this_queue_T_99, _use_this_queue_T_100) node use_this_queue_16 = mux(wrapped, _use_this_queue_T_98, _use_this_queue_T_101) node _T_3110 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3111 = and(_T_3110, use_this_queue_16) connect Queue10_UInt8_16.io.enq.valid, _T_3111 node _use_this_queue_T_102 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_103 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_104 = or(_use_this_queue_T_102, _use_this_queue_T_103) node _use_this_queue_T_105 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_106 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_107 = and(_use_this_queue_T_105, _use_this_queue_T_106) node use_this_queue_17 = mux(wrapped, _use_this_queue_T_104, _use_this_queue_T_107) node _T_3112 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3113 = and(_T_3112, use_this_queue_17) connect Queue10_UInt8_17.io.enq.valid, _T_3113 node _use_this_queue_T_108 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_109 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_110 = or(_use_this_queue_T_108, _use_this_queue_T_109) node _use_this_queue_T_111 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_112 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_113 = and(_use_this_queue_T_111, _use_this_queue_T_112) node use_this_queue_18 = mux(wrapped, _use_this_queue_T_110, _use_this_queue_T_113) node _T_3114 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3115 = and(_T_3114, use_this_queue_18) connect Queue10_UInt8_18.io.enq.valid, _T_3115 node _use_this_queue_T_114 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_115 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115) node _use_this_queue_T_117 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_118 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_119 = and(_use_this_queue_T_117, _use_this_queue_T_118) node use_this_queue_19 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_119) node _T_3116 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3117 = and(_T_3116, use_this_queue_19) connect Queue10_UInt8_19.io.enq.valid, _T_3117 node _use_this_queue_T_120 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_121 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_122 = or(_use_this_queue_T_120, _use_this_queue_T_121) node _use_this_queue_T_123 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_124 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_125 = and(_use_this_queue_T_123, _use_this_queue_T_124) node use_this_queue_20 = mux(wrapped, _use_this_queue_T_122, _use_this_queue_T_125) node _T_3118 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3119 = and(_T_3118, use_this_queue_20) connect Queue10_UInt8_20.io.enq.valid, _T_3119 node _use_this_queue_T_126 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_127 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_128 = or(_use_this_queue_T_126, _use_this_queue_T_127) node _use_this_queue_T_129 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_130 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_131 = and(_use_this_queue_T_129, _use_this_queue_T_130) node use_this_queue_21 = mux(wrapped, _use_this_queue_T_128, _use_this_queue_T_131) node _T_3120 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3121 = and(_T_3120, use_this_queue_21) connect Queue10_UInt8_21.io.enq.valid, _T_3121 node _use_this_queue_T_132 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_133 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_134 = or(_use_this_queue_T_132, _use_this_queue_T_133) node _use_this_queue_T_135 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_136 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_137 = and(_use_this_queue_T_135, _use_this_queue_T_136) node use_this_queue_22 = mux(wrapped, _use_this_queue_T_134, _use_this_queue_T_137) node _T_3122 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3123 = and(_T_3122, use_this_queue_22) connect Queue10_UInt8_22.io.enq.valid, _T_3123 node _use_this_queue_T_138 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_139 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_140 = or(_use_this_queue_T_138, _use_this_queue_T_139) node _use_this_queue_T_141 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_142 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_143 = and(_use_this_queue_T_141, _use_this_queue_T_142) node use_this_queue_23 = mux(wrapped, _use_this_queue_T_140, _use_this_queue_T_143) node _T_3124 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3125 = and(_T_3124, use_this_queue_23) connect Queue10_UInt8_23.io.enq.valid, _T_3125 node _use_this_queue_T_144 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_145 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_146 = or(_use_this_queue_T_144, _use_this_queue_T_145) node _use_this_queue_T_147 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_148 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_149 = and(_use_this_queue_T_147, _use_this_queue_T_148) node use_this_queue_24 = mux(wrapped, _use_this_queue_T_146, _use_this_queue_T_149) node _T_3126 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3127 = and(_T_3126, use_this_queue_24) connect Queue10_UInt8_24.io.enq.valid, _T_3127 node _use_this_queue_T_150 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_151 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_152 = or(_use_this_queue_T_150, _use_this_queue_T_151) node _use_this_queue_T_153 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_154 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_155 = and(_use_this_queue_T_153, _use_this_queue_T_154) node use_this_queue_25 = mux(wrapped, _use_this_queue_T_152, _use_this_queue_T_155) node _T_3128 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3129 = and(_T_3128, use_this_queue_25) connect Queue10_UInt8_25.io.enq.valid, _T_3129 node _use_this_queue_T_156 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_157 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157) node _use_this_queue_T_159 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_160 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_161 = and(_use_this_queue_T_159, _use_this_queue_T_160) node use_this_queue_26 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_161) node _T_3130 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3131 = and(_T_3130, use_this_queue_26) connect Queue10_UInt8_26.io.enq.valid, _T_3131 node _use_this_queue_T_162 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_163 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_164 = or(_use_this_queue_T_162, _use_this_queue_T_163) node _use_this_queue_T_165 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_166 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_167 = and(_use_this_queue_T_165, _use_this_queue_T_166) node use_this_queue_27 = mux(wrapped, _use_this_queue_T_164, _use_this_queue_T_167) node _T_3132 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3133 = and(_T_3132, use_this_queue_27) connect Queue10_UInt8_27.io.enq.valid, _T_3133 node _use_this_queue_T_168 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_169 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_170 = or(_use_this_queue_T_168, _use_this_queue_T_169) node _use_this_queue_T_171 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_172 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_173 = and(_use_this_queue_T_171, _use_this_queue_T_172) node use_this_queue_28 = mux(wrapped, _use_this_queue_T_170, _use_this_queue_T_173) node _T_3134 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3135 = and(_T_3134, use_this_queue_28) connect Queue10_UInt8_28.io.enq.valid, _T_3135 node _use_this_queue_T_174 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_175 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_176 = or(_use_this_queue_T_174, _use_this_queue_T_175) node _use_this_queue_T_177 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_178 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_179 = and(_use_this_queue_T_177, _use_this_queue_T_178) node use_this_queue_29 = mux(wrapped, _use_this_queue_T_176, _use_this_queue_T_179) node _T_3136 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3137 = and(_T_3136, use_this_queue_29) connect Queue10_UInt8_29.io.enq.valid, _T_3137 node _use_this_queue_T_180 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_181 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_182 = or(_use_this_queue_T_180, _use_this_queue_T_181) node _use_this_queue_T_183 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_184 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_185 = and(_use_this_queue_T_183, _use_this_queue_T_184) node use_this_queue_30 = mux(wrapped, _use_this_queue_T_182, _use_this_queue_T_185) node _T_3138 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3139 = and(_T_3138, use_this_queue_30) connect Queue10_UInt8_30.io.enq.valid, _T_3139 node _use_this_queue_T_186 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_187 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_188 = or(_use_this_queue_T_186, _use_this_queue_T_187) node _use_this_queue_T_189 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_190 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_191 = and(_use_this_queue_T_189, _use_this_queue_T_190) node use_this_queue_31 = mux(wrapped, _use_this_queue_T_188, _use_this_queue_T_191) node _T_3140 = and(incoming_writes_Q.io.deq.valid, all_queues_ready) node _T_3141 = and(_T_3140, use_this_queue_31) connect Queue10_UInt8_31.io.enq.valid, _T_3141 when Queue10_UInt8.io.deq.valid : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_3142 = asUInt(reset) node _T_3143 = eq(_T_3142, UInt<1>(0h0)) when _T_3143 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_3144 = asUInt(reset) node _T_3145 = eq(_T_3144, UInt<1>(0h0)) when _T_3145 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<1>(0h0), Queue10_UInt8.io.deq.bits) : printf_3 when Queue10_UInt8_1.io.deq.valid : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_3146 = asUInt(reset) node _T_3147 = eq(_T_3146, UInt<1>(0h0)) when _T_3147 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_3148 = asUInt(reset) node _T_3149 = eq(_T_3148, UInt<1>(0h0)) when _T_3149 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<1>(0h1), Queue10_UInt8_1.io.deq.bits) : printf_5 when Queue10_UInt8_2.io.deq.valid : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_3150 = asUInt(reset) node _T_3151 = eq(_T_3150, UInt<1>(0h0)) when _T_3151 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6 node _T_3152 = asUInt(reset) node _T_3153 = eq(_T_3152, UInt<1>(0h0)) when _T_3153 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<2>(0h2), Queue10_UInt8_2.io.deq.bits) : printf_7 when Queue10_UInt8_3.io.deq.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_3154 = asUInt(reset) node _T_3155 = eq(_T_3154, UInt<1>(0h0)) when _T_3155 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8 node _T_3156 = asUInt(reset) node _T_3157 = eq(_T_3156, UInt<1>(0h0)) when _T_3157 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<2>(0h3), Queue10_UInt8_3.io.deq.bits) : printf_9 when Queue10_UInt8_4.io.deq.valid : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_3158 = asUInt(reset) node _T_3159 = eq(_T_3158, UInt<1>(0h0)) when _T_3159 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10 node _T_3160 = asUInt(reset) node _T_3161 = eq(_T_3160, UInt<1>(0h0)) when _T_3161 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<3>(0h4), Queue10_UInt8_4.io.deq.bits) : printf_11 when Queue10_UInt8_5.io.deq.valid : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _T_3162 = asUInt(reset) node _T_3163 = eq(_T_3162, UInt<1>(0h0)) when _T_3163 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12 node _T_3164 = asUInt(reset) node _T_3165 = eq(_T_3164, UInt<1>(0h0)) when _T_3165 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<3>(0h5), Queue10_UInt8_5.io.deq.bits) : printf_13 when Queue10_UInt8_6.io.deq.valid : regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_3166 = asUInt(reset) node _T_3167 = eq(_T_3166, UInt<1>(0h0)) when _T_3167 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14 node _T_3168 = asUInt(reset) node _T_3169 = eq(_T_3168, UInt<1>(0h0)) when _T_3169 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<3>(0h6), Queue10_UInt8_6.io.deq.bits) : printf_15 when Queue10_UInt8_7.io.deq.valid : regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_3170 = asUInt(reset) node _T_3171 = eq(_T_3170, UInt<1>(0h0)) when _T_3171 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16 node _T_3172 = asUInt(reset) node _T_3173 = eq(_T_3172, UInt<1>(0h0)) when _T_3173 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<3>(0h7), Queue10_UInt8_7.io.deq.bits) : printf_17 when Queue10_UInt8_8.io.deq.valid : regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_3174 = asUInt(reset) node _T_3175 = eq(_T_3174, UInt<1>(0h0)) when _T_3175 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18 node _T_3176 = asUInt(reset) node _T_3177 = eq(_T_3176, UInt<1>(0h0)) when _T_3177 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0h8), Queue10_UInt8_8.io.deq.bits) : printf_19 when Queue10_UInt8_9.io.deq.valid : regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_3178 = asUInt(reset) node _T_3179 = eq(_T_3178, UInt<1>(0h0)) when _T_3179 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20 node _T_3180 = asUInt(reset) node _T_3181 = eq(_T_3180, UInt<1>(0h0)) when _T_3181 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0h9), Queue10_UInt8_9.io.deq.bits) : printf_21 when Queue10_UInt8_10.io.deq.valid : regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_3182 = asUInt(reset) node _T_3183 = eq(_T_3182, UInt<1>(0h0)) when _T_3183 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22 node _T_3184 = asUInt(reset) node _T_3185 = eq(_T_3184, UInt<1>(0h0)) when _T_3185 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0ha), Queue10_UInt8_10.io.deq.bits) : printf_23 when Queue10_UInt8_11.io.deq.valid : regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_3186 = asUInt(reset) node _T_3187 = eq(_T_3186, UInt<1>(0h0)) when _T_3187 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24 node _T_3188 = asUInt(reset) node _T_3189 = eq(_T_3188, UInt<1>(0h0)) when _T_3189 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0hb), Queue10_UInt8_11.io.deq.bits) : printf_25 when Queue10_UInt8_12.io.deq.valid : regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_3190 = asUInt(reset) node _T_3191 = eq(_T_3190, UInt<1>(0h0)) when _T_3191 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26 node _T_3192 = asUInt(reset) node _T_3193 = eq(_T_3192, UInt<1>(0h0)) when _T_3193 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0hc), Queue10_UInt8_12.io.deq.bits) : printf_27 when Queue10_UInt8_13.io.deq.valid : regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_3194 = asUInt(reset) node _T_3195 = eq(_T_3194, UInt<1>(0h0)) when _T_3195 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28 node _T_3196 = asUInt(reset) node _T_3197 = eq(_T_3196, UInt<1>(0h0)) when _T_3197 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0hd), Queue10_UInt8_13.io.deq.bits) : printf_29 when Queue10_UInt8_14.io.deq.valid : regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_3198 = asUInt(reset) node _T_3199 = eq(_T_3198, UInt<1>(0h0)) when _T_3199 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30 node _T_3200 = asUInt(reset) node _T_3201 = eq(_T_3200, UInt<1>(0h0)) when _T_3201 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0he), Queue10_UInt8_14.io.deq.bits) : printf_31 when Queue10_UInt8_15.io.deq.valid : regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_3202 = asUInt(reset) node _T_3203 = eq(_T_3202, UInt<1>(0h0)) when _T_3203 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32 node _T_3204 = asUInt(reset) node _T_3205 = eq(_T_3204, UInt<1>(0h0)) when _T_3205 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<4>(0hf), Queue10_UInt8_15.io.deq.bits) : printf_33 when Queue10_UInt8_16.io.deq.valid : regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_3206 = asUInt(reset) node _T_3207 = eq(_T_3206, UInt<1>(0h0)) when _T_3207 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34 node _T_3208 = asUInt(reset) node _T_3209 = eq(_T_3208, UInt<1>(0h0)) when _T_3209 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h10), Queue10_UInt8_16.io.deq.bits) : printf_35 when Queue10_UInt8_17.io.deq.valid : regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_3210 = asUInt(reset) node _T_3211 = eq(_T_3210, UInt<1>(0h0)) when _T_3211 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36 node _T_3212 = asUInt(reset) node _T_3213 = eq(_T_3212, UInt<1>(0h0)) when _T_3213 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h11), Queue10_UInt8_17.io.deq.bits) : printf_37 when Queue10_UInt8_18.io.deq.valid : regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_3214 = asUInt(reset) node _T_3215 = eq(_T_3214, UInt<1>(0h0)) when _T_3215 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38 node _T_3216 = asUInt(reset) node _T_3217 = eq(_T_3216, UInt<1>(0h0)) when _T_3217 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h12), Queue10_UInt8_18.io.deq.bits) : printf_39 when Queue10_UInt8_19.io.deq.valid : regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_3218 = asUInt(reset) node _T_3219 = eq(_T_3218, UInt<1>(0h0)) when _T_3219 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_40 node _T_3220 = asUInt(reset) node _T_3221 = eq(_T_3220, UInt<1>(0h0)) when _T_3221 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h13), Queue10_UInt8_19.io.deq.bits) : printf_41 when Queue10_UInt8_20.io.deq.valid : regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_3222 = asUInt(reset) node _T_3223 = eq(_T_3222, UInt<1>(0h0)) when _T_3223 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_42 node _T_3224 = asUInt(reset) node _T_3225 = eq(_T_3224, UInt<1>(0h0)) when _T_3225 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h14), Queue10_UInt8_20.io.deq.bits) : printf_43 when Queue10_UInt8_21.io.deq.valid : regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_3226 = asUInt(reset) node _T_3227 = eq(_T_3226, UInt<1>(0h0)) when _T_3227 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_44 node _T_3228 = asUInt(reset) node _T_3229 = eq(_T_3228, UInt<1>(0h0)) when _T_3229 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h15), Queue10_UInt8_21.io.deq.bits) : printf_45 when Queue10_UInt8_22.io.deq.valid : regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_3230 = asUInt(reset) node _T_3231 = eq(_T_3230, UInt<1>(0h0)) when _T_3231 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_46 node _T_3232 = asUInt(reset) node _T_3233 = eq(_T_3232, UInt<1>(0h0)) when _T_3233 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h16), Queue10_UInt8_22.io.deq.bits) : printf_47 when Queue10_UInt8_23.io.deq.valid : regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_3234 = asUInt(reset) node _T_3235 = eq(_T_3234, UInt<1>(0h0)) when _T_3235 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_48 node _T_3236 = asUInt(reset) node _T_3237 = eq(_T_3236, UInt<1>(0h0)) when _T_3237 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h17), Queue10_UInt8_23.io.deq.bits) : printf_49 when Queue10_UInt8_24.io.deq.valid : regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_3238 = asUInt(reset) node _T_3239 = eq(_T_3238, UInt<1>(0h0)) when _T_3239 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_50 node _T_3240 = asUInt(reset) node _T_3241 = eq(_T_3240, UInt<1>(0h0)) when _T_3241 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h18), Queue10_UInt8_24.io.deq.bits) : printf_51 when Queue10_UInt8_25.io.deq.valid : regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_3242 = asUInt(reset) node _T_3243 = eq(_T_3242, UInt<1>(0h0)) when _T_3243 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_52 node _T_3244 = asUInt(reset) node _T_3245 = eq(_T_3244, UInt<1>(0h0)) when _T_3245 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h19), Queue10_UInt8_25.io.deq.bits) : printf_53 when Queue10_UInt8_26.io.deq.valid : regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_3246 = asUInt(reset) node _T_3247 = eq(_T_3246, UInt<1>(0h0)) when _T_3247 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_54 node _T_3248 = asUInt(reset) node _T_3249 = eq(_T_3248, UInt<1>(0h0)) when _T_3249 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1a), Queue10_UInt8_26.io.deq.bits) : printf_55 when Queue10_UInt8_27.io.deq.valid : regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_3250 = asUInt(reset) node _T_3251 = eq(_T_3250, UInt<1>(0h0)) when _T_3251 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_56 node _T_3252 = asUInt(reset) node _T_3253 = eq(_T_3252, UInt<1>(0h0)) when _T_3253 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1b), Queue10_UInt8_27.io.deq.bits) : printf_57 when Queue10_UInt8_28.io.deq.valid : regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_3254 = asUInt(reset) node _T_3255 = eq(_T_3254, UInt<1>(0h0)) when _T_3255 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_58 node _T_3256 = asUInt(reset) node _T_3257 = eq(_T_3256, UInt<1>(0h0)) when _T_3257 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1c), Queue10_UInt8_28.io.deq.bits) : printf_59 when Queue10_UInt8_29.io.deq.valid : regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_3258 = asUInt(reset) node _T_3259 = eq(_T_3258, UInt<1>(0h0)) when _T_3259 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_60 node _T_3260 = asUInt(reset) node _T_3261 = eq(_T_3260, UInt<1>(0h0)) when _T_3261 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1d), Queue10_UInt8_29.io.deq.bits) : printf_61 when Queue10_UInt8_30.io.deq.valid : regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_3262 = asUInt(reset) node _T_3263 = eq(_T_3262, UInt<1>(0h0)) when _T_3263 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_62 node _T_3264 = asUInt(reset) node _T_3265 = eq(_T_3264, UInt<1>(0h0)) when _T_3265 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1e), Queue10_UInt8_30.io.deq.bits) : printf_63 when Queue10_UInt8_31.io.deq.valid : regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_3266 = asUInt(reset) node _T_3267 = eq(_T_3266, UInt<1>(0h0)) when _T_3267 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_64 node _T_3268 = asUInt(reset) node _T_3269 = eq(_T_3268, UInt<1>(0h0)) when _T_3269 : printf(clock, UInt<1>(0h1), "lrb: qi%d,0x%x\n", UInt<5>(0h1f), Queue10_UInt8_31.io.deq.bits) : printf_65 regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0) wire remapVecData : UInt<8>[32] wire remapVecValids : UInt<1>[32] wire remapVecReadys : UInt<1>[32] connect remapVecData[0], UInt<1>(0h0) connect remapVecValids[0], UInt<1>(0h0) connect Queue10_UInt8.io.deq.ready, UInt<1>(0h0) connect remapVecData[1], UInt<1>(0h0) connect remapVecValids[1], UInt<1>(0h0) connect Queue10_UInt8_1.io.deq.ready, UInt<1>(0h0) connect remapVecData[2], UInt<1>(0h0) connect remapVecValids[2], UInt<1>(0h0) connect Queue10_UInt8_2.io.deq.ready, UInt<1>(0h0) connect remapVecData[3], UInt<1>(0h0) connect remapVecValids[3], UInt<1>(0h0) connect Queue10_UInt8_3.io.deq.ready, UInt<1>(0h0) connect remapVecData[4], UInt<1>(0h0) connect remapVecValids[4], UInt<1>(0h0) connect Queue10_UInt8_4.io.deq.ready, UInt<1>(0h0) connect remapVecData[5], UInt<1>(0h0) connect remapVecValids[5], UInt<1>(0h0) connect Queue10_UInt8_5.io.deq.ready, UInt<1>(0h0) connect remapVecData[6], UInt<1>(0h0) connect remapVecValids[6], UInt<1>(0h0) connect Queue10_UInt8_6.io.deq.ready, UInt<1>(0h0) connect remapVecData[7], UInt<1>(0h0) connect remapVecValids[7], UInt<1>(0h0) connect Queue10_UInt8_7.io.deq.ready, UInt<1>(0h0) connect remapVecData[8], UInt<1>(0h0) connect remapVecValids[8], UInt<1>(0h0) connect Queue10_UInt8_8.io.deq.ready, UInt<1>(0h0) connect remapVecData[9], UInt<1>(0h0) connect remapVecValids[9], UInt<1>(0h0) connect Queue10_UInt8_9.io.deq.ready, UInt<1>(0h0) connect remapVecData[10], UInt<1>(0h0) connect remapVecValids[10], UInt<1>(0h0) connect Queue10_UInt8_10.io.deq.ready, UInt<1>(0h0) connect remapVecData[11], UInt<1>(0h0) connect remapVecValids[11], UInt<1>(0h0) connect Queue10_UInt8_11.io.deq.ready, UInt<1>(0h0) connect remapVecData[12], UInt<1>(0h0) connect remapVecValids[12], UInt<1>(0h0) connect Queue10_UInt8_12.io.deq.ready, UInt<1>(0h0) connect remapVecData[13], UInt<1>(0h0) connect remapVecValids[13], UInt<1>(0h0) connect Queue10_UInt8_13.io.deq.ready, UInt<1>(0h0) connect remapVecData[14], UInt<1>(0h0) connect remapVecValids[14], UInt<1>(0h0) connect Queue10_UInt8_14.io.deq.ready, UInt<1>(0h0) connect remapVecData[15], UInt<1>(0h0) connect remapVecValids[15], UInt<1>(0h0) connect Queue10_UInt8_15.io.deq.ready, UInt<1>(0h0) connect remapVecData[16], UInt<1>(0h0) connect remapVecValids[16], UInt<1>(0h0) connect Queue10_UInt8_16.io.deq.ready, UInt<1>(0h0) connect remapVecData[17], UInt<1>(0h0) connect remapVecValids[17], UInt<1>(0h0) connect Queue10_UInt8_17.io.deq.ready, UInt<1>(0h0) connect remapVecData[18], UInt<1>(0h0) connect remapVecValids[18], UInt<1>(0h0) connect Queue10_UInt8_18.io.deq.ready, UInt<1>(0h0) connect remapVecData[19], UInt<1>(0h0) connect remapVecValids[19], UInt<1>(0h0) connect Queue10_UInt8_19.io.deq.ready, UInt<1>(0h0) connect remapVecData[20], UInt<1>(0h0) connect remapVecValids[20], UInt<1>(0h0) connect Queue10_UInt8_20.io.deq.ready, UInt<1>(0h0) connect remapVecData[21], UInt<1>(0h0) connect remapVecValids[21], UInt<1>(0h0) connect Queue10_UInt8_21.io.deq.ready, UInt<1>(0h0) connect remapVecData[22], UInt<1>(0h0) connect remapVecValids[22], UInt<1>(0h0) connect Queue10_UInt8_22.io.deq.ready, UInt<1>(0h0) connect remapVecData[23], UInt<1>(0h0) connect remapVecValids[23], UInt<1>(0h0) connect Queue10_UInt8_23.io.deq.ready, UInt<1>(0h0) connect remapVecData[24], UInt<1>(0h0) connect remapVecValids[24], UInt<1>(0h0) connect Queue10_UInt8_24.io.deq.ready, UInt<1>(0h0) connect remapVecData[25], UInt<1>(0h0) connect remapVecValids[25], UInt<1>(0h0) connect Queue10_UInt8_25.io.deq.ready, UInt<1>(0h0) connect remapVecData[26], UInt<1>(0h0) connect remapVecValids[26], UInt<1>(0h0) connect Queue10_UInt8_26.io.deq.ready, UInt<1>(0h0) connect remapVecData[27], UInt<1>(0h0) connect remapVecValids[27], UInt<1>(0h0) connect Queue10_UInt8_27.io.deq.ready, UInt<1>(0h0) connect remapVecData[28], UInt<1>(0h0) connect remapVecValids[28], UInt<1>(0h0) connect Queue10_UInt8_28.io.deq.ready, UInt<1>(0h0) connect remapVecData[29], UInt<1>(0h0) connect remapVecValids[29], UInt<1>(0h0) connect Queue10_UInt8_29.io.deq.ready, UInt<1>(0h0) connect remapVecData[30], UInt<1>(0h0) connect remapVecValids[30], UInt<1>(0h0) connect Queue10_UInt8_30.io.deq.ready, UInt<1>(0h0) connect remapVecData[31], UInt<1>(0h0) connect remapVecValids[31], UInt<1>(0h0) connect Queue10_UInt8_31.io.deq.ready, UInt<1>(0h0) node _remapindex_T = add(UInt<1>(0h0), read_start_index) node remapindex = rem(_remapindex_T, UInt<6>(0h20)) node _T_3270 = eq(UInt<1>(0h0), remapindex) when _T_3270 : connect remapVecData[0], Queue10_UInt8.io.deq.bits connect remapVecValids[0], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[0] node _T_3271 = eq(UInt<1>(0h1), remapindex) when _T_3271 : connect remapVecData[0], Queue10_UInt8_1.io.deq.bits connect remapVecValids[0], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[0] node _T_3272 = eq(UInt<2>(0h2), remapindex) when _T_3272 : connect remapVecData[0], Queue10_UInt8_2.io.deq.bits connect remapVecValids[0], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[0] node _T_3273 = eq(UInt<2>(0h3), remapindex) when _T_3273 : connect remapVecData[0], Queue10_UInt8_3.io.deq.bits connect remapVecValids[0], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[0] node _T_3274 = eq(UInt<3>(0h4), remapindex) when _T_3274 : connect remapVecData[0], Queue10_UInt8_4.io.deq.bits connect remapVecValids[0], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[0] node _T_3275 = eq(UInt<3>(0h5), remapindex) when _T_3275 : connect remapVecData[0], Queue10_UInt8_5.io.deq.bits connect remapVecValids[0], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[0] node _T_3276 = eq(UInt<3>(0h6), remapindex) when _T_3276 : connect remapVecData[0], Queue10_UInt8_6.io.deq.bits connect remapVecValids[0], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[0] node _T_3277 = eq(UInt<3>(0h7), remapindex) when _T_3277 : connect remapVecData[0], Queue10_UInt8_7.io.deq.bits connect remapVecValids[0], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[0] node _T_3278 = eq(UInt<4>(0h8), remapindex) when _T_3278 : connect remapVecData[0], Queue10_UInt8_8.io.deq.bits connect remapVecValids[0], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[0] node _T_3279 = eq(UInt<4>(0h9), remapindex) when _T_3279 : connect remapVecData[0], Queue10_UInt8_9.io.deq.bits connect remapVecValids[0], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[0] node _T_3280 = eq(UInt<4>(0ha), remapindex) when _T_3280 : connect remapVecData[0], Queue10_UInt8_10.io.deq.bits connect remapVecValids[0], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[0] node _T_3281 = eq(UInt<4>(0hb), remapindex) when _T_3281 : connect remapVecData[0], Queue10_UInt8_11.io.deq.bits connect remapVecValids[0], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[0] node _T_3282 = eq(UInt<4>(0hc), remapindex) when _T_3282 : connect remapVecData[0], Queue10_UInt8_12.io.deq.bits connect remapVecValids[0], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[0] node _T_3283 = eq(UInt<4>(0hd), remapindex) when _T_3283 : connect remapVecData[0], Queue10_UInt8_13.io.deq.bits connect remapVecValids[0], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[0] node _T_3284 = eq(UInt<4>(0he), remapindex) when _T_3284 : connect remapVecData[0], Queue10_UInt8_14.io.deq.bits connect remapVecValids[0], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[0] node _T_3285 = eq(UInt<4>(0hf), remapindex) when _T_3285 : connect remapVecData[0], Queue10_UInt8_15.io.deq.bits connect remapVecValids[0], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[0] node _T_3286 = eq(UInt<5>(0h10), remapindex) when _T_3286 : connect remapVecData[0], Queue10_UInt8_16.io.deq.bits connect remapVecValids[0], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[0] node _T_3287 = eq(UInt<5>(0h11), remapindex) when _T_3287 : connect remapVecData[0], Queue10_UInt8_17.io.deq.bits connect remapVecValids[0], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[0] node _T_3288 = eq(UInt<5>(0h12), remapindex) when _T_3288 : connect remapVecData[0], Queue10_UInt8_18.io.deq.bits connect remapVecValids[0], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[0] node _T_3289 = eq(UInt<5>(0h13), remapindex) when _T_3289 : connect remapVecData[0], Queue10_UInt8_19.io.deq.bits connect remapVecValids[0], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[0] node _T_3290 = eq(UInt<5>(0h14), remapindex) when _T_3290 : connect remapVecData[0], Queue10_UInt8_20.io.deq.bits connect remapVecValids[0], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[0] node _T_3291 = eq(UInt<5>(0h15), remapindex) when _T_3291 : connect remapVecData[0], Queue10_UInt8_21.io.deq.bits connect remapVecValids[0], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[0] node _T_3292 = eq(UInt<5>(0h16), remapindex) when _T_3292 : connect remapVecData[0], Queue10_UInt8_22.io.deq.bits connect remapVecValids[0], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[0] node _T_3293 = eq(UInt<5>(0h17), remapindex) when _T_3293 : connect remapVecData[0], Queue10_UInt8_23.io.deq.bits connect remapVecValids[0], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[0] node _T_3294 = eq(UInt<5>(0h18), remapindex) when _T_3294 : connect remapVecData[0], Queue10_UInt8_24.io.deq.bits connect remapVecValids[0], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[0] node _T_3295 = eq(UInt<5>(0h19), remapindex) when _T_3295 : connect remapVecData[0], Queue10_UInt8_25.io.deq.bits connect remapVecValids[0], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[0] node _T_3296 = eq(UInt<5>(0h1a), remapindex) when _T_3296 : connect remapVecData[0], Queue10_UInt8_26.io.deq.bits connect remapVecValids[0], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[0] node _T_3297 = eq(UInt<5>(0h1b), remapindex) when _T_3297 : connect remapVecData[0], Queue10_UInt8_27.io.deq.bits connect remapVecValids[0], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[0] node _T_3298 = eq(UInt<5>(0h1c), remapindex) when _T_3298 : connect remapVecData[0], Queue10_UInt8_28.io.deq.bits connect remapVecValids[0], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[0] node _T_3299 = eq(UInt<5>(0h1d), remapindex) when _T_3299 : connect remapVecData[0], Queue10_UInt8_29.io.deq.bits connect remapVecValids[0], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[0] node _T_3300 = eq(UInt<5>(0h1e), remapindex) when _T_3300 : connect remapVecData[0], Queue10_UInt8_30.io.deq.bits connect remapVecValids[0], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[0] node _T_3301 = eq(UInt<5>(0h1f), remapindex) when _T_3301 : connect remapVecData[0], Queue10_UInt8_31.io.deq.bits connect remapVecValids[0], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[0] node _remapindex_T_1 = add(UInt<1>(0h1), read_start_index) node remapindex_1 = rem(_remapindex_T_1, UInt<6>(0h20)) node _T_3302 = eq(UInt<1>(0h0), remapindex_1) when _T_3302 : connect remapVecData[1], Queue10_UInt8.io.deq.bits connect remapVecValids[1], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[1] node _T_3303 = eq(UInt<1>(0h1), remapindex_1) when _T_3303 : connect remapVecData[1], Queue10_UInt8_1.io.deq.bits connect remapVecValids[1], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[1] node _T_3304 = eq(UInt<2>(0h2), remapindex_1) when _T_3304 : connect remapVecData[1], Queue10_UInt8_2.io.deq.bits connect remapVecValids[1], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[1] node _T_3305 = eq(UInt<2>(0h3), remapindex_1) when _T_3305 : connect remapVecData[1], Queue10_UInt8_3.io.deq.bits connect remapVecValids[1], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[1] node _T_3306 = eq(UInt<3>(0h4), remapindex_1) when _T_3306 : connect remapVecData[1], Queue10_UInt8_4.io.deq.bits connect remapVecValids[1], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[1] node _T_3307 = eq(UInt<3>(0h5), remapindex_1) when _T_3307 : connect remapVecData[1], Queue10_UInt8_5.io.deq.bits connect remapVecValids[1], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[1] node _T_3308 = eq(UInt<3>(0h6), remapindex_1) when _T_3308 : connect remapVecData[1], Queue10_UInt8_6.io.deq.bits connect remapVecValids[1], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[1] node _T_3309 = eq(UInt<3>(0h7), remapindex_1) when _T_3309 : connect remapVecData[1], Queue10_UInt8_7.io.deq.bits connect remapVecValids[1], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[1] node _T_3310 = eq(UInt<4>(0h8), remapindex_1) when _T_3310 : connect remapVecData[1], Queue10_UInt8_8.io.deq.bits connect remapVecValids[1], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[1] node _T_3311 = eq(UInt<4>(0h9), remapindex_1) when _T_3311 : connect remapVecData[1], Queue10_UInt8_9.io.deq.bits connect remapVecValids[1], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[1] node _T_3312 = eq(UInt<4>(0ha), remapindex_1) when _T_3312 : connect remapVecData[1], Queue10_UInt8_10.io.deq.bits connect remapVecValids[1], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[1] node _T_3313 = eq(UInt<4>(0hb), remapindex_1) when _T_3313 : connect remapVecData[1], Queue10_UInt8_11.io.deq.bits connect remapVecValids[1], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[1] node _T_3314 = eq(UInt<4>(0hc), remapindex_1) when _T_3314 : connect remapVecData[1], Queue10_UInt8_12.io.deq.bits connect remapVecValids[1], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[1] node _T_3315 = eq(UInt<4>(0hd), remapindex_1) when _T_3315 : connect remapVecData[1], Queue10_UInt8_13.io.deq.bits connect remapVecValids[1], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[1] node _T_3316 = eq(UInt<4>(0he), remapindex_1) when _T_3316 : connect remapVecData[1], Queue10_UInt8_14.io.deq.bits connect remapVecValids[1], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[1] node _T_3317 = eq(UInt<4>(0hf), remapindex_1) when _T_3317 : connect remapVecData[1], Queue10_UInt8_15.io.deq.bits connect remapVecValids[1], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[1] node _T_3318 = eq(UInt<5>(0h10), remapindex_1) when _T_3318 : connect remapVecData[1], Queue10_UInt8_16.io.deq.bits connect remapVecValids[1], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[1] node _T_3319 = eq(UInt<5>(0h11), remapindex_1) when _T_3319 : connect remapVecData[1], Queue10_UInt8_17.io.deq.bits connect remapVecValids[1], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[1] node _T_3320 = eq(UInt<5>(0h12), remapindex_1) when _T_3320 : connect remapVecData[1], Queue10_UInt8_18.io.deq.bits connect remapVecValids[1], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[1] node _T_3321 = eq(UInt<5>(0h13), remapindex_1) when _T_3321 : connect remapVecData[1], Queue10_UInt8_19.io.deq.bits connect remapVecValids[1], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[1] node _T_3322 = eq(UInt<5>(0h14), remapindex_1) when _T_3322 : connect remapVecData[1], Queue10_UInt8_20.io.deq.bits connect remapVecValids[1], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[1] node _T_3323 = eq(UInt<5>(0h15), remapindex_1) when _T_3323 : connect remapVecData[1], Queue10_UInt8_21.io.deq.bits connect remapVecValids[1], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[1] node _T_3324 = eq(UInt<5>(0h16), remapindex_1) when _T_3324 : connect remapVecData[1], Queue10_UInt8_22.io.deq.bits connect remapVecValids[1], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[1] node _T_3325 = eq(UInt<5>(0h17), remapindex_1) when _T_3325 : connect remapVecData[1], Queue10_UInt8_23.io.deq.bits connect remapVecValids[1], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[1] node _T_3326 = eq(UInt<5>(0h18), remapindex_1) when _T_3326 : connect remapVecData[1], Queue10_UInt8_24.io.deq.bits connect remapVecValids[1], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[1] node _T_3327 = eq(UInt<5>(0h19), remapindex_1) when _T_3327 : connect remapVecData[1], Queue10_UInt8_25.io.deq.bits connect remapVecValids[1], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[1] node _T_3328 = eq(UInt<5>(0h1a), remapindex_1) when _T_3328 : connect remapVecData[1], Queue10_UInt8_26.io.deq.bits connect remapVecValids[1], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[1] node _T_3329 = eq(UInt<5>(0h1b), remapindex_1) when _T_3329 : connect remapVecData[1], Queue10_UInt8_27.io.deq.bits connect remapVecValids[1], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[1] node _T_3330 = eq(UInt<5>(0h1c), remapindex_1) when _T_3330 : connect remapVecData[1], Queue10_UInt8_28.io.deq.bits connect remapVecValids[1], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[1] node _T_3331 = eq(UInt<5>(0h1d), remapindex_1) when _T_3331 : connect remapVecData[1], Queue10_UInt8_29.io.deq.bits connect remapVecValids[1], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[1] node _T_3332 = eq(UInt<5>(0h1e), remapindex_1) when _T_3332 : connect remapVecData[1], Queue10_UInt8_30.io.deq.bits connect remapVecValids[1], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[1] node _T_3333 = eq(UInt<5>(0h1f), remapindex_1) when _T_3333 : connect remapVecData[1], Queue10_UInt8_31.io.deq.bits connect remapVecValids[1], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[1] node _remapindex_T_2 = add(UInt<2>(0h2), read_start_index) node remapindex_2 = rem(_remapindex_T_2, UInt<6>(0h20)) node _T_3334 = eq(UInt<1>(0h0), remapindex_2) when _T_3334 : connect remapVecData[2], Queue10_UInt8.io.deq.bits connect remapVecValids[2], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[2] node _T_3335 = eq(UInt<1>(0h1), remapindex_2) when _T_3335 : connect remapVecData[2], Queue10_UInt8_1.io.deq.bits connect remapVecValids[2], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[2] node _T_3336 = eq(UInt<2>(0h2), remapindex_2) when _T_3336 : connect remapVecData[2], Queue10_UInt8_2.io.deq.bits connect remapVecValids[2], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[2] node _T_3337 = eq(UInt<2>(0h3), remapindex_2) when _T_3337 : connect remapVecData[2], Queue10_UInt8_3.io.deq.bits connect remapVecValids[2], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[2] node _T_3338 = eq(UInt<3>(0h4), remapindex_2) when _T_3338 : connect remapVecData[2], Queue10_UInt8_4.io.deq.bits connect remapVecValids[2], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[2] node _T_3339 = eq(UInt<3>(0h5), remapindex_2) when _T_3339 : connect remapVecData[2], Queue10_UInt8_5.io.deq.bits connect remapVecValids[2], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[2] node _T_3340 = eq(UInt<3>(0h6), remapindex_2) when _T_3340 : connect remapVecData[2], Queue10_UInt8_6.io.deq.bits connect remapVecValids[2], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[2] node _T_3341 = eq(UInt<3>(0h7), remapindex_2) when _T_3341 : connect remapVecData[2], Queue10_UInt8_7.io.deq.bits connect remapVecValids[2], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[2] node _T_3342 = eq(UInt<4>(0h8), remapindex_2) when _T_3342 : connect remapVecData[2], Queue10_UInt8_8.io.deq.bits connect remapVecValids[2], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[2] node _T_3343 = eq(UInt<4>(0h9), remapindex_2) when _T_3343 : connect remapVecData[2], Queue10_UInt8_9.io.deq.bits connect remapVecValids[2], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[2] node _T_3344 = eq(UInt<4>(0ha), remapindex_2) when _T_3344 : connect remapVecData[2], Queue10_UInt8_10.io.deq.bits connect remapVecValids[2], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[2] node _T_3345 = eq(UInt<4>(0hb), remapindex_2) when _T_3345 : connect remapVecData[2], Queue10_UInt8_11.io.deq.bits connect remapVecValids[2], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[2] node _T_3346 = eq(UInt<4>(0hc), remapindex_2) when _T_3346 : connect remapVecData[2], Queue10_UInt8_12.io.deq.bits connect remapVecValids[2], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[2] node _T_3347 = eq(UInt<4>(0hd), remapindex_2) when _T_3347 : connect remapVecData[2], Queue10_UInt8_13.io.deq.bits connect remapVecValids[2], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[2] node _T_3348 = eq(UInt<4>(0he), remapindex_2) when _T_3348 : connect remapVecData[2], Queue10_UInt8_14.io.deq.bits connect remapVecValids[2], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[2] node _T_3349 = eq(UInt<4>(0hf), remapindex_2) when _T_3349 : connect remapVecData[2], Queue10_UInt8_15.io.deq.bits connect remapVecValids[2], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[2] node _T_3350 = eq(UInt<5>(0h10), remapindex_2) when _T_3350 : connect remapVecData[2], Queue10_UInt8_16.io.deq.bits connect remapVecValids[2], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[2] node _T_3351 = eq(UInt<5>(0h11), remapindex_2) when _T_3351 : connect remapVecData[2], Queue10_UInt8_17.io.deq.bits connect remapVecValids[2], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[2] node _T_3352 = eq(UInt<5>(0h12), remapindex_2) when _T_3352 : connect remapVecData[2], Queue10_UInt8_18.io.deq.bits connect remapVecValids[2], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[2] node _T_3353 = eq(UInt<5>(0h13), remapindex_2) when _T_3353 : connect remapVecData[2], Queue10_UInt8_19.io.deq.bits connect remapVecValids[2], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[2] node _T_3354 = eq(UInt<5>(0h14), remapindex_2) when _T_3354 : connect remapVecData[2], Queue10_UInt8_20.io.deq.bits connect remapVecValids[2], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[2] node _T_3355 = eq(UInt<5>(0h15), remapindex_2) when _T_3355 : connect remapVecData[2], Queue10_UInt8_21.io.deq.bits connect remapVecValids[2], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[2] node _T_3356 = eq(UInt<5>(0h16), remapindex_2) when _T_3356 : connect remapVecData[2], Queue10_UInt8_22.io.deq.bits connect remapVecValids[2], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[2] node _T_3357 = eq(UInt<5>(0h17), remapindex_2) when _T_3357 : connect remapVecData[2], Queue10_UInt8_23.io.deq.bits connect remapVecValids[2], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[2] node _T_3358 = eq(UInt<5>(0h18), remapindex_2) when _T_3358 : connect remapVecData[2], Queue10_UInt8_24.io.deq.bits connect remapVecValids[2], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[2] node _T_3359 = eq(UInt<5>(0h19), remapindex_2) when _T_3359 : connect remapVecData[2], Queue10_UInt8_25.io.deq.bits connect remapVecValids[2], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[2] node _T_3360 = eq(UInt<5>(0h1a), remapindex_2) when _T_3360 : connect remapVecData[2], Queue10_UInt8_26.io.deq.bits connect remapVecValids[2], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[2] node _T_3361 = eq(UInt<5>(0h1b), remapindex_2) when _T_3361 : connect remapVecData[2], Queue10_UInt8_27.io.deq.bits connect remapVecValids[2], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[2] node _T_3362 = eq(UInt<5>(0h1c), remapindex_2) when _T_3362 : connect remapVecData[2], Queue10_UInt8_28.io.deq.bits connect remapVecValids[2], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[2] node _T_3363 = eq(UInt<5>(0h1d), remapindex_2) when _T_3363 : connect remapVecData[2], Queue10_UInt8_29.io.deq.bits connect remapVecValids[2], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[2] node _T_3364 = eq(UInt<5>(0h1e), remapindex_2) when _T_3364 : connect remapVecData[2], Queue10_UInt8_30.io.deq.bits connect remapVecValids[2], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[2] node _T_3365 = eq(UInt<5>(0h1f), remapindex_2) when _T_3365 : connect remapVecData[2], Queue10_UInt8_31.io.deq.bits connect remapVecValids[2], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[2] node _remapindex_T_3 = add(UInt<2>(0h3), read_start_index) node remapindex_3 = rem(_remapindex_T_3, UInt<6>(0h20)) node _T_3366 = eq(UInt<1>(0h0), remapindex_3) when _T_3366 : connect remapVecData[3], Queue10_UInt8.io.deq.bits connect remapVecValids[3], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[3] node _T_3367 = eq(UInt<1>(0h1), remapindex_3) when _T_3367 : connect remapVecData[3], Queue10_UInt8_1.io.deq.bits connect remapVecValids[3], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[3] node _T_3368 = eq(UInt<2>(0h2), remapindex_3) when _T_3368 : connect remapVecData[3], Queue10_UInt8_2.io.deq.bits connect remapVecValids[3], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[3] node _T_3369 = eq(UInt<2>(0h3), remapindex_3) when _T_3369 : connect remapVecData[3], Queue10_UInt8_3.io.deq.bits connect remapVecValids[3], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[3] node _T_3370 = eq(UInt<3>(0h4), remapindex_3) when _T_3370 : connect remapVecData[3], Queue10_UInt8_4.io.deq.bits connect remapVecValids[3], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[3] node _T_3371 = eq(UInt<3>(0h5), remapindex_3) when _T_3371 : connect remapVecData[3], Queue10_UInt8_5.io.deq.bits connect remapVecValids[3], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[3] node _T_3372 = eq(UInt<3>(0h6), remapindex_3) when _T_3372 : connect remapVecData[3], Queue10_UInt8_6.io.deq.bits connect remapVecValids[3], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[3] node _T_3373 = eq(UInt<3>(0h7), remapindex_3) when _T_3373 : connect remapVecData[3], Queue10_UInt8_7.io.deq.bits connect remapVecValids[3], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[3] node _T_3374 = eq(UInt<4>(0h8), remapindex_3) when _T_3374 : connect remapVecData[3], Queue10_UInt8_8.io.deq.bits connect remapVecValids[3], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[3] node _T_3375 = eq(UInt<4>(0h9), remapindex_3) when _T_3375 : connect remapVecData[3], Queue10_UInt8_9.io.deq.bits connect remapVecValids[3], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[3] node _T_3376 = eq(UInt<4>(0ha), remapindex_3) when _T_3376 : connect remapVecData[3], Queue10_UInt8_10.io.deq.bits connect remapVecValids[3], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[3] node _T_3377 = eq(UInt<4>(0hb), remapindex_3) when _T_3377 : connect remapVecData[3], Queue10_UInt8_11.io.deq.bits connect remapVecValids[3], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[3] node _T_3378 = eq(UInt<4>(0hc), remapindex_3) when _T_3378 : connect remapVecData[3], Queue10_UInt8_12.io.deq.bits connect remapVecValids[3], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[3] node _T_3379 = eq(UInt<4>(0hd), remapindex_3) when _T_3379 : connect remapVecData[3], Queue10_UInt8_13.io.deq.bits connect remapVecValids[3], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[3] node _T_3380 = eq(UInt<4>(0he), remapindex_3) when _T_3380 : connect remapVecData[3], Queue10_UInt8_14.io.deq.bits connect remapVecValids[3], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[3] node _T_3381 = eq(UInt<4>(0hf), remapindex_3) when _T_3381 : connect remapVecData[3], Queue10_UInt8_15.io.deq.bits connect remapVecValids[3], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[3] node _T_3382 = eq(UInt<5>(0h10), remapindex_3) when _T_3382 : connect remapVecData[3], Queue10_UInt8_16.io.deq.bits connect remapVecValids[3], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[3] node _T_3383 = eq(UInt<5>(0h11), remapindex_3) when _T_3383 : connect remapVecData[3], Queue10_UInt8_17.io.deq.bits connect remapVecValids[3], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[3] node _T_3384 = eq(UInt<5>(0h12), remapindex_3) when _T_3384 : connect remapVecData[3], Queue10_UInt8_18.io.deq.bits connect remapVecValids[3], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[3] node _T_3385 = eq(UInt<5>(0h13), remapindex_3) when _T_3385 : connect remapVecData[3], Queue10_UInt8_19.io.deq.bits connect remapVecValids[3], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[3] node _T_3386 = eq(UInt<5>(0h14), remapindex_3) when _T_3386 : connect remapVecData[3], Queue10_UInt8_20.io.deq.bits connect remapVecValids[3], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[3] node _T_3387 = eq(UInt<5>(0h15), remapindex_3) when _T_3387 : connect remapVecData[3], Queue10_UInt8_21.io.deq.bits connect remapVecValids[3], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[3] node _T_3388 = eq(UInt<5>(0h16), remapindex_3) when _T_3388 : connect remapVecData[3], Queue10_UInt8_22.io.deq.bits connect remapVecValids[3], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[3] node _T_3389 = eq(UInt<5>(0h17), remapindex_3) when _T_3389 : connect remapVecData[3], Queue10_UInt8_23.io.deq.bits connect remapVecValids[3], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[3] node _T_3390 = eq(UInt<5>(0h18), remapindex_3) when _T_3390 : connect remapVecData[3], Queue10_UInt8_24.io.deq.bits connect remapVecValids[3], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[3] node _T_3391 = eq(UInt<5>(0h19), remapindex_3) when _T_3391 : connect remapVecData[3], Queue10_UInt8_25.io.deq.bits connect remapVecValids[3], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[3] node _T_3392 = eq(UInt<5>(0h1a), remapindex_3) when _T_3392 : connect remapVecData[3], Queue10_UInt8_26.io.deq.bits connect remapVecValids[3], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[3] node _T_3393 = eq(UInt<5>(0h1b), remapindex_3) when _T_3393 : connect remapVecData[3], Queue10_UInt8_27.io.deq.bits connect remapVecValids[3], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[3] node _T_3394 = eq(UInt<5>(0h1c), remapindex_3) when _T_3394 : connect remapVecData[3], Queue10_UInt8_28.io.deq.bits connect remapVecValids[3], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[3] node _T_3395 = eq(UInt<5>(0h1d), remapindex_3) when _T_3395 : connect remapVecData[3], Queue10_UInt8_29.io.deq.bits connect remapVecValids[3], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[3] node _T_3396 = eq(UInt<5>(0h1e), remapindex_3) when _T_3396 : connect remapVecData[3], Queue10_UInt8_30.io.deq.bits connect remapVecValids[3], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[3] node _T_3397 = eq(UInt<5>(0h1f), remapindex_3) when _T_3397 : connect remapVecData[3], Queue10_UInt8_31.io.deq.bits connect remapVecValids[3], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[3] node _remapindex_T_4 = add(UInt<3>(0h4), read_start_index) node remapindex_4 = rem(_remapindex_T_4, UInt<6>(0h20)) node _T_3398 = eq(UInt<1>(0h0), remapindex_4) when _T_3398 : connect remapVecData[4], Queue10_UInt8.io.deq.bits connect remapVecValids[4], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[4] node _T_3399 = eq(UInt<1>(0h1), remapindex_4) when _T_3399 : connect remapVecData[4], Queue10_UInt8_1.io.deq.bits connect remapVecValids[4], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[4] node _T_3400 = eq(UInt<2>(0h2), remapindex_4) when _T_3400 : connect remapVecData[4], Queue10_UInt8_2.io.deq.bits connect remapVecValids[4], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[4] node _T_3401 = eq(UInt<2>(0h3), remapindex_4) when _T_3401 : connect remapVecData[4], Queue10_UInt8_3.io.deq.bits connect remapVecValids[4], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[4] node _T_3402 = eq(UInt<3>(0h4), remapindex_4) when _T_3402 : connect remapVecData[4], Queue10_UInt8_4.io.deq.bits connect remapVecValids[4], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[4] node _T_3403 = eq(UInt<3>(0h5), remapindex_4) when _T_3403 : connect remapVecData[4], Queue10_UInt8_5.io.deq.bits connect remapVecValids[4], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[4] node _T_3404 = eq(UInt<3>(0h6), remapindex_4) when _T_3404 : connect remapVecData[4], Queue10_UInt8_6.io.deq.bits connect remapVecValids[4], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[4] node _T_3405 = eq(UInt<3>(0h7), remapindex_4) when _T_3405 : connect remapVecData[4], Queue10_UInt8_7.io.deq.bits connect remapVecValids[4], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[4] node _T_3406 = eq(UInt<4>(0h8), remapindex_4) when _T_3406 : connect remapVecData[4], Queue10_UInt8_8.io.deq.bits connect remapVecValids[4], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[4] node _T_3407 = eq(UInt<4>(0h9), remapindex_4) when _T_3407 : connect remapVecData[4], Queue10_UInt8_9.io.deq.bits connect remapVecValids[4], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[4] node _T_3408 = eq(UInt<4>(0ha), remapindex_4) when _T_3408 : connect remapVecData[4], Queue10_UInt8_10.io.deq.bits connect remapVecValids[4], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[4] node _T_3409 = eq(UInt<4>(0hb), remapindex_4) when _T_3409 : connect remapVecData[4], Queue10_UInt8_11.io.deq.bits connect remapVecValids[4], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[4] node _T_3410 = eq(UInt<4>(0hc), remapindex_4) when _T_3410 : connect remapVecData[4], Queue10_UInt8_12.io.deq.bits connect remapVecValids[4], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[4] node _T_3411 = eq(UInt<4>(0hd), remapindex_4) when _T_3411 : connect remapVecData[4], Queue10_UInt8_13.io.deq.bits connect remapVecValids[4], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[4] node _T_3412 = eq(UInt<4>(0he), remapindex_4) when _T_3412 : connect remapVecData[4], Queue10_UInt8_14.io.deq.bits connect remapVecValids[4], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[4] node _T_3413 = eq(UInt<4>(0hf), remapindex_4) when _T_3413 : connect remapVecData[4], Queue10_UInt8_15.io.deq.bits connect remapVecValids[4], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[4] node _T_3414 = eq(UInt<5>(0h10), remapindex_4) when _T_3414 : connect remapVecData[4], Queue10_UInt8_16.io.deq.bits connect remapVecValids[4], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[4] node _T_3415 = eq(UInt<5>(0h11), remapindex_4) when _T_3415 : connect remapVecData[4], Queue10_UInt8_17.io.deq.bits connect remapVecValids[4], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[4] node _T_3416 = eq(UInt<5>(0h12), remapindex_4) when _T_3416 : connect remapVecData[4], Queue10_UInt8_18.io.deq.bits connect remapVecValids[4], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[4] node _T_3417 = eq(UInt<5>(0h13), remapindex_4) when _T_3417 : connect remapVecData[4], Queue10_UInt8_19.io.deq.bits connect remapVecValids[4], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[4] node _T_3418 = eq(UInt<5>(0h14), remapindex_4) when _T_3418 : connect remapVecData[4], Queue10_UInt8_20.io.deq.bits connect remapVecValids[4], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[4] node _T_3419 = eq(UInt<5>(0h15), remapindex_4) when _T_3419 : connect remapVecData[4], Queue10_UInt8_21.io.deq.bits connect remapVecValids[4], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[4] node _T_3420 = eq(UInt<5>(0h16), remapindex_4) when _T_3420 : connect remapVecData[4], Queue10_UInt8_22.io.deq.bits connect remapVecValids[4], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[4] node _T_3421 = eq(UInt<5>(0h17), remapindex_4) when _T_3421 : connect remapVecData[4], Queue10_UInt8_23.io.deq.bits connect remapVecValids[4], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[4] node _T_3422 = eq(UInt<5>(0h18), remapindex_4) when _T_3422 : connect remapVecData[4], Queue10_UInt8_24.io.deq.bits connect remapVecValids[4], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[4] node _T_3423 = eq(UInt<5>(0h19), remapindex_4) when _T_3423 : connect remapVecData[4], Queue10_UInt8_25.io.deq.bits connect remapVecValids[4], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[4] node _T_3424 = eq(UInt<5>(0h1a), remapindex_4) when _T_3424 : connect remapVecData[4], Queue10_UInt8_26.io.deq.bits connect remapVecValids[4], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[4] node _T_3425 = eq(UInt<5>(0h1b), remapindex_4) when _T_3425 : connect remapVecData[4], Queue10_UInt8_27.io.deq.bits connect remapVecValids[4], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[4] node _T_3426 = eq(UInt<5>(0h1c), remapindex_4) when _T_3426 : connect remapVecData[4], Queue10_UInt8_28.io.deq.bits connect remapVecValids[4], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[4] node _T_3427 = eq(UInt<5>(0h1d), remapindex_4) when _T_3427 : connect remapVecData[4], Queue10_UInt8_29.io.deq.bits connect remapVecValids[4], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[4] node _T_3428 = eq(UInt<5>(0h1e), remapindex_4) when _T_3428 : connect remapVecData[4], Queue10_UInt8_30.io.deq.bits connect remapVecValids[4], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[4] node _T_3429 = eq(UInt<5>(0h1f), remapindex_4) when _T_3429 : connect remapVecData[4], Queue10_UInt8_31.io.deq.bits connect remapVecValids[4], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[4] node _remapindex_T_5 = add(UInt<3>(0h5), read_start_index) node remapindex_5 = rem(_remapindex_T_5, UInt<6>(0h20)) node _T_3430 = eq(UInt<1>(0h0), remapindex_5) when _T_3430 : connect remapVecData[5], Queue10_UInt8.io.deq.bits connect remapVecValids[5], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[5] node _T_3431 = eq(UInt<1>(0h1), remapindex_5) when _T_3431 : connect remapVecData[5], Queue10_UInt8_1.io.deq.bits connect remapVecValids[5], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[5] node _T_3432 = eq(UInt<2>(0h2), remapindex_5) when _T_3432 : connect remapVecData[5], Queue10_UInt8_2.io.deq.bits connect remapVecValids[5], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[5] node _T_3433 = eq(UInt<2>(0h3), remapindex_5) when _T_3433 : connect remapVecData[5], Queue10_UInt8_3.io.deq.bits connect remapVecValids[5], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[5] node _T_3434 = eq(UInt<3>(0h4), remapindex_5) when _T_3434 : connect remapVecData[5], Queue10_UInt8_4.io.deq.bits connect remapVecValids[5], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[5] node _T_3435 = eq(UInt<3>(0h5), remapindex_5) when _T_3435 : connect remapVecData[5], Queue10_UInt8_5.io.deq.bits connect remapVecValids[5], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[5] node _T_3436 = eq(UInt<3>(0h6), remapindex_5) when _T_3436 : connect remapVecData[5], Queue10_UInt8_6.io.deq.bits connect remapVecValids[5], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[5] node _T_3437 = eq(UInt<3>(0h7), remapindex_5) when _T_3437 : connect remapVecData[5], Queue10_UInt8_7.io.deq.bits connect remapVecValids[5], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[5] node _T_3438 = eq(UInt<4>(0h8), remapindex_5) when _T_3438 : connect remapVecData[5], Queue10_UInt8_8.io.deq.bits connect remapVecValids[5], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[5] node _T_3439 = eq(UInt<4>(0h9), remapindex_5) when _T_3439 : connect remapVecData[5], Queue10_UInt8_9.io.deq.bits connect remapVecValids[5], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[5] node _T_3440 = eq(UInt<4>(0ha), remapindex_5) when _T_3440 : connect remapVecData[5], Queue10_UInt8_10.io.deq.bits connect remapVecValids[5], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[5] node _T_3441 = eq(UInt<4>(0hb), remapindex_5) when _T_3441 : connect remapVecData[5], Queue10_UInt8_11.io.deq.bits connect remapVecValids[5], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[5] node _T_3442 = eq(UInt<4>(0hc), remapindex_5) when _T_3442 : connect remapVecData[5], Queue10_UInt8_12.io.deq.bits connect remapVecValids[5], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[5] node _T_3443 = eq(UInt<4>(0hd), remapindex_5) when _T_3443 : connect remapVecData[5], Queue10_UInt8_13.io.deq.bits connect remapVecValids[5], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[5] node _T_3444 = eq(UInt<4>(0he), remapindex_5) when _T_3444 : connect remapVecData[5], Queue10_UInt8_14.io.deq.bits connect remapVecValids[5], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[5] node _T_3445 = eq(UInt<4>(0hf), remapindex_5) when _T_3445 : connect remapVecData[5], Queue10_UInt8_15.io.deq.bits connect remapVecValids[5], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[5] node _T_3446 = eq(UInt<5>(0h10), remapindex_5) when _T_3446 : connect remapVecData[5], Queue10_UInt8_16.io.deq.bits connect remapVecValids[5], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[5] node _T_3447 = eq(UInt<5>(0h11), remapindex_5) when _T_3447 : connect remapVecData[5], Queue10_UInt8_17.io.deq.bits connect remapVecValids[5], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[5] node _T_3448 = eq(UInt<5>(0h12), remapindex_5) when _T_3448 : connect remapVecData[5], Queue10_UInt8_18.io.deq.bits connect remapVecValids[5], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[5] node _T_3449 = eq(UInt<5>(0h13), remapindex_5) when _T_3449 : connect remapVecData[5], Queue10_UInt8_19.io.deq.bits connect remapVecValids[5], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[5] node _T_3450 = eq(UInt<5>(0h14), remapindex_5) when _T_3450 : connect remapVecData[5], Queue10_UInt8_20.io.deq.bits connect remapVecValids[5], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[5] node _T_3451 = eq(UInt<5>(0h15), remapindex_5) when _T_3451 : connect remapVecData[5], Queue10_UInt8_21.io.deq.bits connect remapVecValids[5], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[5] node _T_3452 = eq(UInt<5>(0h16), remapindex_5) when _T_3452 : connect remapVecData[5], Queue10_UInt8_22.io.deq.bits connect remapVecValids[5], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[5] node _T_3453 = eq(UInt<5>(0h17), remapindex_5) when _T_3453 : connect remapVecData[5], Queue10_UInt8_23.io.deq.bits connect remapVecValids[5], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[5] node _T_3454 = eq(UInt<5>(0h18), remapindex_5) when _T_3454 : connect remapVecData[5], Queue10_UInt8_24.io.deq.bits connect remapVecValids[5], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[5] node _T_3455 = eq(UInt<5>(0h19), remapindex_5) when _T_3455 : connect remapVecData[5], Queue10_UInt8_25.io.deq.bits connect remapVecValids[5], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[5] node _T_3456 = eq(UInt<5>(0h1a), remapindex_5) when _T_3456 : connect remapVecData[5], Queue10_UInt8_26.io.deq.bits connect remapVecValids[5], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[5] node _T_3457 = eq(UInt<5>(0h1b), remapindex_5) when _T_3457 : connect remapVecData[5], Queue10_UInt8_27.io.deq.bits connect remapVecValids[5], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[5] node _T_3458 = eq(UInt<5>(0h1c), remapindex_5) when _T_3458 : connect remapVecData[5], Queue10_UInt8_28.io.deq.bits connect remapVecValids[5], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[5] node _T_3459 = eq(UInt<5>(0h1d), remapindex_5) when _T_3459 : connect remapVecData[5], Queue10_UInt8_29.io.deq.bits connect remapVecValids[5], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[5] node _T_3460 = eq(UInt<5>(0h1e), remapindex_5) when _T_3460 : connect remapVecData[5], Queue10_UInt8_30.io.deq.bits connect remapVecValids[5], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[5] node _T_3461 = eq(UInt<5>(0h1f), remapindex_5) when _T_3461 : connect remapVecData[5], Queue10_UInt8_31.io.deq.bits connect remapVecValids[5], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[5] node _remapindex_T_6 = add(UInt<3>(0h6), read_start_index) node remapindex_6 = rem(_remapindex_T_6, UInt<6>(0h20)) node _T_3462 = eq(UInt<1>(0h0), remapindex_6) when _T_3462 : connect remapVecData[6], Queue10_UInt8.io.deq.bits connect remapVecValids[6], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[6] node _T_3463 = eq(UInt<1>(0h1), remapindex_6) when _T_3463 : connect remapVecData[6], Queue10_UInt8_1.io.deq.bits connect remapVecValids[6], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[6] node _T_3464 = eq(UInt<2>(0h2), remapindex_6) when _T_3464 : connect remapVecData[6], Queue10_UInt8_2.io.deq.bits connect remapVecValids[6], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[6] node _T_3465 = eq(UInt<2>(0h3), remapindex_6) when _T_3465 : connect remapVecData[6], Queue10_UInt8_3.io.deq.bits connect remapVecValids[6], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[6] node _T_3466 = eq(UInt<3>(0h4), remapindex_6) when _T_3466 : connect remapVecData[6], Queue10_UInt8_4.io.deq.bits connect remapVecValids[6], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[6] node _T_3467 = eq(UInt<3>(0h5), remapindex_6) when _T_3467 : connect remapVecData[6], Queue10_UInt8_5.io.deq.bits connect remapVecValids[6], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[6] node _T_3468 = eq(UInt<3>(0h6), remapindex_6) when _T_3468 : connect remapVecData[6], Queue10_UInt8_6.io.deq.bits connect remapVecValids[6], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[6] node _T_3469 = eq(UInt<3>(0h7), remapindex_6) when _T_3469 : connect remapVecData[6], Queue10_UInt8_7.io.deq.bits connect remapVecValids[6], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[6] node _T_3470 = eq(UInt<4>(0h8), remapindex_6) when _T_3470 : connect remapVecData[6], Queue10_UInt8_8.io.deq.bits connect remapVecValids[6], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[6] node _T_3471 = eq(UInt<4>(0h9), remapindex_6) when _T_3471 : connect remapVecData[6], Queue10_UInt8_9.io.deq.bits connect remapVecValids[6], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[6] node _T_3472 = eq(UInt<4>(0ha), remapindex_6) when _T_3472 : connect remapVecData[6], Queue10_UInt8_10.io.deq.bits connect remapVecValids[6], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[6] node _T_3473 = eq(UInt<4>(0hb), remapindex_6) when _T_3473 : connect remapVecData[6], Queue10_UInt8_11.io.deq.bits connect remapVecValids[6], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[6] node _T_3474 = eq(UInt<4>(0hc), remapindex_6) when _T_3474 : connect remapVecData[6], Queue10_UInt8_12.io.deq.bits connect remapVecValids[6], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[6] node _T_3475 = eq(UInt<4>(0hd), remapindex_6) when _T_3475 : connect remapVecData[6], Queue10_UInt8_13.io.deq.bits connect remapVecValids[6], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[6] node _T_3476 = eq(UInt<4>(0he), remapindex_6) when _T_3476 : connect remapVecData[6], Queue10_UInt8_14.io.deq.bits connect remapVecValids[6], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[6] node _T_3477 = eq(UInt<4>(0hf), remapindex_6) when _T_3477 : connect remapVecData[6], Queue10_UInt8_15.io.deq.bits connect remapVecValids[6], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[6] node _T_3478 = eq(UInt<5>(0h10), remapindex_6) when _T_3478 : connect remapVecData[6], Queue10_UInt8_16.io.deq.bits connect remapVecValids[6], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[6] node _T_3479 = eq(UInt<5>(0h11), remapindex_6) when _T_3479 : connect remapVecData[6], Queue10_UInt8_17.io.deq.bits connect remapVecValids[6], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[6] node _T_3480 = eq(UInt<5>(0h12), remapindex_6) when _T_3480 : connect remapVecData[6], Queue10_UInt8_18.io.deq.bits connect remapVecValids[6], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[6] node _T_3481 = eq(UInt<5>(0h13), remapindex_6) when _T_3481 : connect remapVecData[6], Queue10_UInt8_19.io.deq.bits connect remapVecValids[6], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[6] node _T_3482 = eq(UInt<5>(0h14), remapindex_6) when _T_3482 : connect remapVecData[6], Queue10_UInt8_20.io.deq.bits connect remapVecValids[6], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[6] node _T_3483 = eq(UInt<5>(0h15), remapindex_6) when _T_3483 : connect remapVecData[6], Queue10_UInt8_21.io.deq.bits connect remapVecValids[6], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[6] node _T_3484 = eq(UInt<5>(0h16), remapindex_6) when _T_3484 : connect remapVecData[6], Queue10_UInt8_22.io.deq.bits connect remapVecValids[6], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[6] node _T_3485 = eq(UInt<5>(0h17), remapindex_6) when _T_3485 : connect remapVecData[6], Queue10_UInt8_23.io.deq.bits connect remapVecValids[6], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[6] node _T_3486 = eq(UInt<5>(0h18), remapindex_6) when _T_3486 : connect remapVecData[6], Queue10_UInt8_24.io.deq.bits connect remapVecValids[6], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[6] node _T_3487 = eq(UInt<5>(0h19), remapindex_6) when _T_3487 : connect remapVecData[6], Queue10_UInt8_25.io.deq.bits connect remapVecValids[6], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[6] node _T_3488 = eq(UInt<5>(0h1a), remapindex_6) when _T_3488 : connect remapVecData[6], Queue10_UInt8_26.io.deq.bits connect remapVecValids[6], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[6] node _T_3489 = eq(UInt<5>(0h1b), remapindex_6) when _T_3489 : connect remapVecData[6], Queue10_UInt8_27.io.deq.bits connect remapVecValids[6], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[6] node _T_3490 = eq(UInt<5>(0h1c), remapindex_6) when _T_3490 : connect remapVecData[6], Queue10_UInt8_28.io.deq.bits connect remapVecValids[6], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[6] node _T_3491 = eq(UInt<5>(0h1d), remapindex_6) when _T_3491 : connect remapVecData[6], Queue10_UInt8_29.io.deq.bits connect remapVecValids[6], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[6] node _T_3492 = eq(UInt<5>(0h1e), remapindex_6) when _T_3492 : connect remapVecData[6], Queue10_UInt8_30.io.deq.bits connect remapVecValids[6], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[6] node _T_3493 = eq(UInt<5>(0h1f), remapindex_6) when _T_3493 : connect remapVecData[6], Queue10_UInt8_31.io.deq.bits connect remapVecValids[6], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[6] node _remapindex_T_7 = add(UInt<3>(0h7), read_start_index) node remapindex_7 = rem(_remapindex_T_7, UInt<6>(0h20)) node _T_3494 = eq(UInt<1>(0h0), remapindex_7) when _T_3494 : connect remapVecData[7], Queue10_UInt8.io.deq.bits connect remapVecValids[7], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[7] node _T_3495 = eq(UInt<1>(0h1), remapindex_7) when _T_3495 : connect remapVecData[7], Queue10_UInt8_1.io.deq.bits connect remapVecValids[7], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[7] node _T_3496 = eq(UInt<2>(0h2), remapindex_7) when _T_3496 : connect remapVecData[7], Queue10_UInt8_2.io.deq.bits connect remapVecValids[7], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[7] node _T_3497 = eq(UInt<2>(0h3), remapindex_7) when _T_3497 : connect remapVecData[7], Queue10_UInt8_3.io.deq.bits connect remapVecValids[7], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[7] node _T_3498 = eq(UInt<3>(0h4), remapindex_7) when _T_3498 : connect remapVecData[7], Queue10_UInt8_4.io.deq.bits connect remapVecValids[7], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[7] node _T_3499 = eq(UInt<3>(0h5), remapindex_7) when _T_3499 : connect remapVecData[7], Queue10_UInt8_5.io.deq.bits connect remapVecValids[7], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[7] node _T_3500 = eq(UInt<3>(0h6), remapindex_7) when _T_3500 : connect remapVecData[7], Queue10_UInt8_6.io.deq.bits connect remapVecValids[7], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[7] node _T_3501 = eq(UInt<3>(0h7), remapindex_7) when _T_3501 : connect remapVecData[7], Queue10_UInt8_7.io.deq.bits connect remapVecValids[7], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[7] node _T_3502 = eq(UInt<4>(0h8), remapindex_7) when _T_3502 : connect remapVecData[7], Queue10_UInt8_8.io.deq.bits connect remapVecValids[7], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[7] node _T_3503 = eq(UInt<4>(0h9), remapindex_7) when _T_3503 : connect remapVecData[7], Queue10_UInt8_9.io.deq.bits connect remapVecValids[7], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[7] node _T_3504 = eq(UInt<4>(0ha), remapindex_7) when _T_3504 : connect remapVecData[7], Queue10_UInt8_10.io.deq.bits connect remapVecValids[7], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[7] node _T_3505 = eq(UInt<4>(0hb), remapindex_7) when _T_3505 : connect remapVecData[7], Queue10_UInt8_11.io.deq.bits connect remapVecValids[7], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[7] node _T_3506 = eq(UInt<4>(0hc), remapindex_7) when _T_3506 : connect remapVecData[7], Queue10_UInt8_12.io.deq.bits connect remapVecValids[7], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[7] node _T_3507 = eq(UInt<4>(0hd), remapindex_7) when _T_3507 : connect remapVecData[7], Queue10_UInt8_13.io.deq.bits connect remapVecValids[7], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[7] node _T_3508 = eq(UInt<4>(0he), remapindex_7) when _T_3508 : connect remapVecData[7], Queue10_UInt8_14.io.deq.bits connect remapVecValids[7], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[7] node _T_3509 = eq(UInt<4>(0hf), remapindex_7) when _T_3509 : connect remapVecData[7], Queue10_UInt8_15.io.deq.bits connect remapVecValids[7], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[7] node _T_3510 = eq(UInt<5>(0h10), remapindex_7) when _T_3510 : connect remapVecData[7], Queue10_UInt8_16.io.deq.bits connect remapVecValids[7], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[7] node _T_3511 = eq(UInt<5>(0h11), remapindex_7) when _T_3511 : connect remapVecData[7], Queue10_UInt8_17.io.deq.bits connect remapVecValids[7], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[7] node _T_3512 = eq(UInt<5>(0h12), remapindex_7) when _T_3512 : connect remapVecData[7], Queue10_UInt8_18.io.deq.bits connect remapVecValids[7], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[7] node _T_3513 = eq(UInt<5>(0h13), remapindex_7) when _T_3513 : connect remapVecData[7], Queue10_UInt8_19.io.deq.bits connect remapVecValids[7], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[7] node _T_3514 = eq(UInt<5>(0h14), remapindex_7) when _T_3514 : connect remapVecData[7], Queue10_UInt8_20.io.deq.bits connect remapVecValids[7], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[7] node _T_3515 = eq(UInt<5>(0h15), remapindex_7) when _T_3515 : connect remapVecData[7], Queue10_UInt8_21.io.deq.bits connect remapVecValids[7], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[7] node _T_3516 = eq(UInt<5>(0h16), remapindex_7) when _T_3516 : connect remapVecData[7], Queue10_UInt8_22.io.deq.bits connect remapVecValids[7], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[7] node _T_3517 = eq(UInt<5>(0h17), remapindex_7) when _T_3517 : connect remapVecData[7], Queue10_UInt8_23.io.deq.bits connect remapVecValids[7], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[7] node _T_3518 = eq(UInt<5>(0h18), remapindex_7) when _T_3518 : connect remapVecData[7], Queue10_UInt8_24.io.deq.bits connect remapVecValids[7], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[7] node _T_3519 = eq(UInt<5>(0h19), remapindex_7) when _T_3519 : connect remapVecData[7], Queue10_UInt8_25.io.deq.bits connect remapVecValids[7], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[7] node _T_3520 = eq(UInt<5>(0h1a), remapindex_7) when _T_3520 : connect remapVecData[7], Queue10_UInt8_26.io.deq.bits connect remapVecValids[7], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[7] node _T_3521 = eq(UInt<5>(0h1b), remapindex_7) when _T_3521 : connect remapVecData[7], Queue10_UInt8_27.io.deq.bits connect remapVecValids[7], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[7] node _T_3522 = eq(UInt<5>(0h1c), remapindex_7) when _T_3522 : connect remapVecData[7], Queue10_UInt8_28.io.deq.bits connect remapVecValids[7], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[7] node _T_3523 = eq(UInt<5>(0h1d), remapindex_7) when _T_3523 : connect remapVecData[7], Queue10_UInt8_29.io.deq.bits connect remapVecValids[7], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[7] node _T_3524 = eq(UInt<5>(0h1e), remapindex_7) when _T_3524 : connect remapVecData[7], Queue10_UInt8_30.io.deq.bits connect remapVecValids[7], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[7] node _T_3525 = eq(UInt<5>(0h1f), remapindex_7) when _T_3525 : connect remapVecData[7], Queue10_UInt8_31.io.deq.bits connect remapVecValids[7], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[7] node _remapindex_T_8 = add(UInt<4>(0h8), read_start_index) node remapindex_8 = rem(_remapindex_T_8, UInt<6>(0h20)) node _T_3526 = eq(UInt<1>(0h0), remapindex_8) when _T_3526 : connect remapVecData[8], Queue10_UInt8.io.deq.bits connect remapVecValids[8], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[8] node _T_3527 = eq(UInt<1>(0h1), remapindex_8) when _T_3527 : connect remapVecData[8], Queue10_UInt8_1.io.deq.bits connect remapVecValids[8], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[8] node _T_3528 = eq(UInt<2>(0h2), remapindex_8) when _T_3528 : connect remapVecData[8], Queue10_UInt8_2.io.deq.bits connect remapVecValids[8], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[8] node _T_3529 = eq(UInt<2>(0h3), remapindex_8) when _T_3529 : connect remapVecData[8], Queue10_UInt8_3.io.deq.bits connect remapVecValids[8], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[8] node _T_3530 = eq(UInt<3>(0h4), remapindex_8) when _T_3530 : connect remapVecData[8], Queue10_UInt8_4.io.deq.bits connect remapVecValids[8], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[8] node _T_3531 = eq(UInt<3>(0h5), remapindex_8) when _T_3531 : connect remapVecData[8], Queue10_UInt8_5.io.deq.bits connect remapVecValids[8], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[8] node _T_3532 = eq(UInt<3>(0h6), remapindex_8) when _T_3532 : connect remapVecData[8], Queue10_UInt8_6.io.deq.bits connect remapVecValids[8], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[8] node _T_3533 = eq(UInt<3>(0h7), remapindex_8) when _T_3533 : connect remapVecData[8], Queue10_UInt8_7.io.deq.bits connect remapVecValids[8], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[8] node _T_3534 = eq(UInt<4>(0h8), remapindex_8) when _T_3534 : connect remapVecData[8], Queue10_UInt8_8.io.deq.bits connect remapVecValids[8], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[8] node _T_3535 = eq(UInt<4>(0h9), remapindex_8) when _T_3535 : connect remapVecData[8], Queue10_UInt8_9.io.deq.bits connect remapVecValids[8], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[8] node _T_3536 = eq(UInt<4>(0ha), remapindex_8) when _T_3536 : connect remapVecData[8], Queue10_UInt8_10.io.deq.bits connect remapVecValids[8], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[8] node _T_3537 = eq(UInt<4>(0hb), remapindex_8) when _T_3537 : connect remapVecData[8], Queue10_UInt8_11.io.deq.bits connect remapVecValids[8], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[8] node _T_3538 = eq(UInt<4>(0hc), remapindex_8) when _T_3538 : connect remapVecData[8], Queue10_UInt8_12.io.deq.bits connect remapVecValids[8], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[8] node _T_3539 = eq(UInt<4>(0hd), remapindex_8) when _T_3539 : connect remapVecData[8], Queue10_UInt8_13.io.deq.bits connect remapVecValids[8], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[8] node _T_3540 = eq(UInt<4>(0he), remapindex_8) when _T_3540 : connect remapVecData[8], Queue10_UInt8_14.io.deq.bits connect remapVecValids[8], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[8] node _T_3541 = eq(UInt<4>(0hf), remapindex_8) when _T_3541 : connect remapVecData[8], Queue10_UInt8_15.io.deq.bits connect remapVecValids[8], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[8] node _T_3542 = eq(UInt<5>(0h10), remapindex_8) when _T_3542 : connect remapVecData[8], Queue10_UInt8_16.io.deq.bits connect remapVecValids[8], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[8] node _T_3543 = eq(UInt<5>(0h11), remapindex_8) when _T_3543 : connect remapVecData[8], Queue10_UInt8_17.io.deq.bits connect remapVecValids[8], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[8] node _T_3544 = eq(UInt<5>(0h12), remapindex_8) when _T_3544 : connect remapVecData[8], Queue10_UInt8_18.io.deq.bits connect remapVecValids[8], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[8] node _T_3545 = eq(UInt<5>(0h13), remapindex_8) when _T_3545 : connect remapVecData[8], Queue10_UInt8_19.io.deq.bits connect remapVecValids[8], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[8] node _T_3546 = eq(UInt<5>(0h14), remapindex_8) when _T_3546 : connect remapVecData[8], Queue10_UInt8_20.io.deq.bits connect remapVecValids[8], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[8] node _T_3547 = eq(UInt<5>(0h15), remapindex_8) when _T_3547 : connect remapVecData[8], Queue10_UInt8_21.io.deq.bits connect remapVecValids[8], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[8] node _T_3548 = eq(UInt<5>(0h16), remapindex_8) when _T_3548 : connect remapVecData[8], Queue10_UInt8_22.io.deq.bits connect remapVecValids[8], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[8] node _T_3549 = eq(UInt<5>(0h17), remapindex_8) when _T_3549 : connect remapVecData[8], Queue10_UInt8_23.io.deq.bits connect remapVecValids[8], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[8] node _T_3550 = eq(UInt<5>(0h18), remapindex_8) when _T_3550 : connect remapVecData[8], Queue10_UInt8_24.io.deq.bits connect remapVecValids[8], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[8] node _T_3551 = eq(UInt<5>(0h19), remapindex_8) when _T_3551 : connect remapVecData[8], Queue10_UInt8_25.io.deq.bits connect remapVecValids[8], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[8] node _T_3552 = eq(UInt<5>(0h1a), remapindex_8) when _T_3552 : connect remapVecData[8], Queue10_UInt8_26.io.deq.bits connect remapVecValids[8], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[8] node _T_3553 = eq(UInt<5>(0h1b), remapindex_8) when _T_3553 : connect remapVecData[8], Queue10_UInt8_27.io.deq.bits connect remapVecValids[8], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[8] node _T_3554 = eq(UInt<5>(0h1c), remapindex_8) when _T_3554 : connect remapVecData[8], Queue10_UInt8_28.io.deq.bits connect remapVecValids[8], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[8] node _T_3555 = eq(UInt<5>(0h1d), remapindex_8) when _T_3555 : connect remapVecData[8], Queue10_UInt8_29.io.deq.bits connect remapVecValids[8], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[8] node _T_3556 = eq(UInt<5>(0h1e), remapindex_8) when _T_3556 : connect remapVecData[8], Queue10_UInt8_30.io.deq.bits connect remapVecValids[8], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[8] node _T_3557 = eq(UInt<5>(0h1f), remapindex_8) when _T_3557 : connect remapVecData[8], Queue10_UInt8_31.io.deq.bits connect remapVecValids[8], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[8] node _remapindex_T_9 = add(UInt<4>(0h9), read_start_index) node remapindex_9 = rem(_remapindex_T_9, UInt<6>(0h20)) node _T_3558 = eq(UInt<1>(0h0), remapindex_9) when _T_3558 : connect remapVecData[9], Queue10_UInt8.io.deq.bits connect remapVecValids[9], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[9] node _T_3559 = eq(UInt<1>(0h1), remapindex_9) when _T_3559 : connect remapVecData[9], Queue10_UInt8_1.io.deq.bits connect remapVecValids[9], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[9] node _T_3560 = eq(UInt<2>(0h2), remapindex_9) when _T_3560 : connect remapVecData[9], Queue10_UInt8_2.io.deq.bits connect remapVecValids[9], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[9] node _T_3561 = eq(UInt<2>(0h3), remapindex_9) when _T_3561 : connect remapVecData[9], Queue10_UInt8_3.io.deq.bits connect remapVecValids[9], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[9] node _T_3562 = eq(UInt<3>(0h4), remapindex_9) when _T_3562 : connect remapVecData[9], Queue10_UInt8_4.io.deq.bits connect remapVecValids[9], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[9] node _T_3563 = eq(UInt<3>(0h5), remapindex_9) when _T_3563 : connect remapVecData[9], Queue10_UInt8_5.io.deq.bits connect remapVecValids[9], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[9] node _T_3564 = eq(UInt<3>(0h6), remapindex_9) when _T_3564 : connect remapVecData[9], Queue10_UInt8_6.io.deq.bits connect remapVecValids[9], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[9] node _T_3565 = eq(UInt<3>(0h7), remapindex_9) when _T_3565 : connect remapVecData[9], Queue10_UInt8_7.io.deq.bits connect remapVecValids[9], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[9] node _T_3566 = eq(UInt<4>(0h8), remapindex_9) when _T_3566 : connect remapVecData[9], Queue10_UInt8_8.io.deq.bits connect remapVecValids[9], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[9] node _T_3567 = eq(UInt<4>(0h9), remapindex_9) when _T_3567 : connect remapVecData[9], Queue10_UInt8_9.io.deq.bits connect remapVecValids[9], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[9] node _T_3568 = eq(UInt<4>(0ha), remapindex_9) when _T_3568 : connect remapVecData[9], Queue10_UInt8_10.io.deq.bits connect remapVecValids[9], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[9] node _T_3569 = eq(UInt<4>(0hb), remapindex_9) when _T_3569 : connect remapVecData[9], Queue10_UInt8_11.io.deq.bits connect remapVecValids[9], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[9] node _T_3570 = eq(UInt<4>(0hc), remapindex_9) when _T_3570 : connect remapVecData[9], Queue10_UInt8_12.io.deq.bits connect remapVecValids[9], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[9] node _T_3571 = eq(UInt<4>(0hd), remapindex_9) when _T_3571 : connect remapVecData[9], Queue10_UInt8_13.io.deq.bits connect remapVecValids[9], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[9] node _T_3572 = eq(UInt<4>(0he), remapindex_9) when _T_3572 : connect remapVecData[9], Queue10_UInt8_14.io.deq.bits connect remapVecValids[9], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[9] node _T_3573 = eq(UInt<4>(0hf), remapindex_9) when _T_3573 : connect remapVecData[9], Queue10_UInt8_15.io.deq.bits connect remapVecValids[9], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[9] node _T_3574 = eq(UInt<5>(0h10), remapindex_9) when _T_3574 : connect remapVecData[9], Queue10_UInt8_16.io.deq.bits connect remapVecValids[9], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[9] node _T_3575 = eq(UInt<5>(0h11), remapindex_9) when _T_3575 : connect remapVecData[9], Queue10_UInt8_17.io.deq.bits connect remapVecValids[9], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[9] node _T_3576 = eq(UInt<5>(0h12), remapindex_9) when _T_3576 : connect remapVecData[9], Queue10_UInt8_18.io.deq.bits connect remapVecValids[9], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[9] node _T_3577 = eq(UInt<5>(0h13), remapindex_9) when _T_3577 : connect remapVecData[9], Queue10_UInt8_19.io.deq.bits connect remapVecValids[9], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[9] node _T_3578 = eq(UInt<5>(0h14), remapindex_9) when _T_3578 : connect remapVecData[9], Queue10_UInt8_20.io.deq.bits connect remapVecValids[9], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[9] node _T_3579 = eq(UInt<5>(0h15), remapindex_9) when _T_3579 : connect remapVecData[9], Queue10_UInt8_21.io.deq.bits connect remapVecValids[9], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[9] node _T_3580 = eq(UInt<5>(0h16), remapindex_9) when _T_3580 : connect remapVecData[9], Queue10_UInt8_22.io.deq.bits connect remapVecValids[9], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[9] node _T_3581 = eq(UInt<5>(0h17), remapindex_9) when _T_3581 : connect remapVecData[9], Queue10_UInt8_23.io.deq.bits connect remapVecValids[9], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[9] node _T_3582 = eq(UInt<5>(0h18), remapindex_9) when _T_3582 : connect remapVecData[9], Queue10_UInt8_24.io.deq.bits connect remapVecValids[9], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[9] node _T_3583 = eq(UInt<5>(0h19), remapindex_9) when _T_3583 : connect remapVecData[9], Queue10_UInt8_25.io.deq.bits connect remapVecValids[9], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[9] node _T_3584 = eq(UInt<5>(0h1a), remapindex_9) when _T_3584 : connect remapVecData[9], Queue10_UInt8_26.io.deq.bits connect remapVecValids[9], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[9] node _T_3585 = eq(UInt<5>(0h1b), remapindex_9) when _T_3585 : connect remapVecData[9], Queue10_UInt8_27.io.deq.bits connect remapVecValids[9], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[9] node _T_3586 = eq(UInt<5>(0h1c), remapindex_9) when _T_3586 : connect remapVecData[9], Queue10_UInt8_28.io.deq.bits connect remapVecValids[9], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[9] node _T_3587 = eq(UInt<5>(0h1d), remapindex_9) when _T_3587 : connect remapVecData[9], Queue10_UInt8_29.io.deq.bits connect remapVecValids[9], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[9] node _T_3588 = eq(UInt<5>(0h1e), remapindex_9) when _T_3588 : connect remapVecData[9], Queue10_UInt8_30.io.deq.bits connect remapVecValids[9], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[9] node _T_3589 = eq(UInt<5>(0h1f), remapindex_9) when _T_3589 : connect remapVecData[9], Queue10_UInt8_31.io.deq.bits connect remapVecValids[9], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[9] node _remapindex_T_10 = add(UInt<4>(0ha), read_start_index) node remapindex_10 = rem(_remapindex_T_10, UInt<6>(0h20)) node _T_3590 = eq(UInt<1>(0h0), remapindex_10) when _T_3590 : connect remapVecData[10], Queue10_UInt8.io.deq.bits connect remapVecValids[10], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[10] node _T_3591 = eq(UInt<1>(0h1), remapindex_10) when _T_3591 : connect remapVecData[10], Queue10_UInt8_1.io.deq.bits connect remapVecValids[10], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[10] node _T_3592 = eq(UInt<2>(0h2), remapindex_10) when _T_3592 : connect remapVecData[10], Queue10_UInt8_2.io.deq.bits connect remapVecValids[10], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[10] node _T_3593 = eq(UInt<2>(0h3), remapindex_10) when _T_3593 : connect remapVecData[10], Queue10_UInt8_3.io.deq.bits connect remapVecValids[10], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[10] node _T_3594 = eq(UInt<3>(0h4), remapindex_10) when _T_3594 : connect remapVecData[10], Queue10_UInt8_4.io.deq.bits connect remapVecValids[10], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[10] node _T_3595 = eq(UInt<3>(0h5), remapindex_10) when _T_3595 : connect remapVecData[10], Queue10_UInt8_5.io.deq.bits connect remapVecValids[10], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[10] node _T_3596 = eq(UInt<3>(0h6), remapindex_10) when _T_3596 : connect remapVecData[10], Queue10_UInt8_6.io.deq.bits connect remapVecValids[10], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[10] node _T_3597 = eq(UInt<3>(0h7), remapindex_10) when _T_3597 : connect remapVecData[10], Queue10_UInt8_7.io.deq.bits connect remapVecValids[10], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[10] node _T_3598 = eq(UInt<4>(0h8), remapindex_10) when _T_3598 : connect remapVecData[10], Queue10_UInt8_8.io.deq.bits connect remapVecValids[10], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[10] node _T_3599 = eq(UInt<4>(0h9), remapindex_10) when _T_3599 : connect remapVecData[10], Queue10_UInt8_9.io.deq.bits connect remapVecValids[10], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[10] node _T_3600 = eq(UInt<4>(0ha), remapindex_10) when _T_3600 : connect remapVecData[10], Queue10_UInt8_10.io.deq.bits connect remapVecValids[10], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[10] node _T_3601 = eq(UInt<4>(0hb), remapindex_10) when _T_3601 : connect remapVecData[10], Queue10_UInt8_11.io.deq.bits connect remapVecValids[10], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[10] node _T_3602 = eq(UInt<4>(0hc), remapindex_10) when _T_3602 : connect remapVecData[10], Queue10_UInt8_12.io.deq.bits connect remapVecValids[10], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[10] node _T_3603 = eq(UInt<4>(0hd), remapindex_10) when _T_3603 : connect remapVecData[10], Queue10_UInt8_13.io.deq.bits connect remapVecValids[10], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[10] node _T_3604 = eq(UInt<4>(0he), remapindex_10) when _T_3604 : connect remapVecData[10], Queue10_UInt8_14.io.deq.bits connect remapVecValids[10], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[10] node _T_3605 = eq(UInt<4>(0hf), remapindex_10) when _T_3605 : connect remapVecData[10], Queue10_UInt8_15.io.deq.bits connect remapVecValids[10], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[10] node _T_3606 = eq(UInt<5>(0h10), remapindex_10) when _T_3606 : connect remapVecData[10], Queue10_UInt8_16.io.deq.bits connect remapVecValids[10], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[10] node _T_3607 = eq(UInt<5>(0h11), remapindex_10) when _T_3607 : connect remapVecData[10], Queue10_UInt8_17.io.deq.bits connect remapVecValids[10], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[10] node _T_3608 = eq(UInt<5>(0h12), remapindex_10) when _T_3608 : connect remapVecData[10], Queue10_UInt8_18.io.deq.bits connect remapVecValids[10], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[10] node _T_3609 = eq(UInt<5>(0h13), remapindex_10) when _T_3609 : connect remapVecData[10], Queue10_UInt8_19.io.deq.bits connect remapVecValids[10], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[10] node _T_3610 = eq(UInt<5>(0h14), remapindex_10) when _T_3610 : connect remapVecData[10], Queue10_UInt8_20.io.deq.bits connect remapVecValids[10], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[10] node _T_3611 = eq(UInt<5>(0h15), remapindex_10) when _T_3611 : connect remapVecData[10], Queue10_UInt8_21.io.deq.bits connect remapVecValids[10], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[10] node _T_3612 = eq(UInt<5>(0h16), remapindex_10) when _T_3612 : connect remapVecData[10], Queue10_UInt8_22.io.deq.bits connect remapVecValids[10], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[10] node _T_3613 = eq(UInt<5>(0h17), remapindex_10) when _T_3613 : connect remapVecData[10], Queue10_UInt8_23.io.deq.bits connect remapVecValids[10], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[10] node _T_3614 = eq(UInt<5>(0h18), remapindex_10) when _T_3614 : connect remapVecData[10], Queue10_UInt8_24.io.deq.bits connect remapVecValids[10], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[10] node _T_3615 = eq(UInt<5>(0h19), remapindex_10) when _T_3615 : connect remapVecData[10], Queue10_UInt8_25.io.deq.bits connect remapVecValids[10], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[10] node _T_3616 = eq(UInt<5>(0h1a), remapindex_10) when _T_3616 : connect remapVecData[10], Queue10_UInt8_26.io.deq.bits connect remapVecValids[10], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[10] node _T_3617 = eq(UInt<5>(0h1b), remapindex_10) when _T_3617 : connect remapVecData[10], Queue10_UInt8_27.io.deq.bits connect remapVecValids[10], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[10] node _T_3618 = eq(UInt<5>(0h1c), remapindex_10) when _T_3618 : connect remapVecData[10], Queue10_UInt8_28.io.deq.bits connect remapVecValids[10], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[10] node _T_3619 = eq(UInt<5>(0h1d), remapindex_10) when _T_3619 : connect remapVecData[10], Queue10_UInt8_29.io.deq.bits connect remapVecValids[10], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[10] node _T_3620 = eq(UInt<5>(0h1e), remapindex_10) when _T_3620 : connect remapVecData[10], Queue10_UInt8_30.io.deq.bits connect remapVecValids[10], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[10] node _T_3621 = eq(UInt<5>(0h1f), remapindex_10) when _T_3621 : connect remapVecData[10], Queue10_UInt8_31.io.deq.bits connect remapVecValids[10], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[10] node _remapindex_T_11 = add(UInt<4>(0hb), read_start_index) node remapindex_11 = rem(_remapindex_T_11, UInt<6>(0h20)) node _T_3622 = eq(UInt<1>(0h0), remapindex_11) when _T_3622 : connect remapVecData[11], Queue10_UInt8.io.deq.bits connect remapVecValids[11], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[11] node _T_3623 = eq(UInt<1>(0h1), remapindex_11) when _T_3623 : connect remapVecData[11], Queue10_UInt8_1.io.deq.bits connect remapVecValids[11], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[11] node _T_3624 = eq(UInt<2>(0h2), remapindex_11) when _T_3624 : connect remapVecData[11], Queue10_UInt8_2.io.deq.bits connect remapVecValids[11], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[11] node _T_3625 = eq(UInt<2>(0h3), remapindex_11) when _T_3625 : connect remapVecData[11], Queue10_UInt8_3.io.deq.bits connect remapVecValids[11], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[11] node _T_3626 = eq(UInt<3>(0h4), remapindex_11) when _T_3626 : connect remapVecData[11], Queue10_UInt8_4.io.deq.bits connect remapVecValids[11], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[11] node _T_3627 = eq(UInt<3>(0h5), remapindex_11) when _T_3627 : connect remapVecData[11], Queue10_UInt8_5.io.deq.bits connect remapVecValids[11], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[11] node _T_3628 = eq(UInt<3>(0h6), remapindex_11) when _T_3628 : connect remapVecData[11], Queue10_UInt8_6.io.deq.bits connect remapVecValids[11], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[11] node _T_3629 = eq(UInt<3>(0h7), remapindex_11) when _T_3629 : connect remapVecData[11], Queue10_UInt8_7.io.deq.bits connect remapVecValids[11], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[11] node _T_3630 = eq(UInt<4>(0h8), remapindex_11) when _T_3630 : connect remapVecData[11], Queue10_UInt8_8.io.deq.bits connect remapVecValids[11], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[11] node _T_3631 = eq(UInt<4>(0h9), remapindex_11) when _T_3631 : connect remapVecData[11], Queue10_UInt8_9.io.deq.bits connect remapVecValids[11], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[11] node _T_3632 = eq(UInt<4>(0ha), remapindex_11) when _T_3632 : connect remapVecData[11], Queue10_UInt8_10.io.deq.bits connect remapVecValids[11], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[11] node _T_3633 = eq(UInt<4>(0hb), remapindex_11) when _T_3633 : connect remapVecData[11], Queue10_UInt8_11.io.deq.bits connect remapVecValids[11], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[11] node _T_3634 = eq(UInt<4>(0hc), remapindex_11) when _T_3634 : connect remapVecData[11], Queue10_UInt8_12.io.deq.bits connect remapVecValids[11], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[11] node _T_3635 = eq(UInt<4>(0hd), remapindex_11) when _T_3635 : connect remapVecData[11], Queue10_UInt8_13.io.deq.bits connect remapVecValids[11], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[11] node _T_3636 = eq(UInt<4>(0he), remapindex_11) when _T_3636 : connect remapVecData[11], Queue10_UInt8_14.io.deq.bits connect remapVecValids[11], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[11] node _T_3637 = eq(UInt<4>(0hf), remapindex_11) when _T_3637 : connect remapVecData[11], Queue10_UInt8_15.io.deq.bits connect remapVecValids[11], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[11] node _T_3638 = eq(UInt<5>(0h10), remapindex_11) when _T_3638 : connect remapVecData[11], Queue10_UInt8_16.io.deq.bits connect remapVecValids[11], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[11] node _T_3639 = eq(UInt<5>(0h11), remapindex_11) when _T_3639 : connect remapVecData[11], Queue10_UInt8_17.io.deq.bits connect remapVecValids[11], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[11] node _T_3640 = eq(UInt<5>(0h12), remapindex_11) when _T_3640 : connect remapVecData[11], Queue10_UInt8_18.io.deq.bits connect remapVecValids[11], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[11] node _T_3641 = eq(UInt<5>(0h13), remapindex_11) when _T_3641 : connect remapVecData[11], Queue10_UInt8_19.io.deq.bits connect remapVecValids[11], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[11] node _T_3642 = eq(UInt<5>(0h14), remapindex_11) when _T_3642 : connect remapVecData[11], Queue10_UInt8_20.io.deq.bits connect remapVecValids[11], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[11] node _T_3643 = eq(UInt<5>(0h15), remapindex_11) when _T_3643 : connect remapVecData[11], Queue10_UInt8_21.io.deq.bits connect remapVecValids[11], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[11] node _T_3644 = eq(UInt<5>(0h16), remapindex_11) when _T_3644 : connect remapVecData[11], Queue10_UInt8_22.io.deq.bits connect remapVecValids[11], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[11] node _T_3645 = eq(UInt<5>(0h17), remapindex_11) when _T_3645 : connect remapVecData[11], Queue10_UInt8_23.io.deq.bits connect remapVecValids[11], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[11] node _T_3646 = eq(UInt<5>(0h18), remapindex_11) when _T_3646 : connect remapVecData[11], Queue10_UInt8_24.io.deq.bits connect remapVecValids[11], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[11] node _T_3647 = eq(UInt<5>(0h19), remapindex_11) when _T_3647 : connect remapVecData[11], Queue10_UInt8_25.io.deq.bits connect remapVecValids[11], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[11] node _T_3648 = eq(UInt<5>(0h1a), remapindex_11) when _T_3648 : connect remapVecData[11], Queue10_UInt8_26.io.deq.bits connect remapVecValids[11], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[11] node _T_3649 = eq(UInt<5>(0h1b), remapindex_11) when _T_3649 : connect remapVecData[11], Queue10_UInt8_27.io.deq.bits connect remapVecValids[11], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[11] node _T_3650 = eq(UInt<5>(0h1c), remapindex_11) when _T_3650 : connect remapVecData[11], Queue10_UInt8_28.io.deq.bits connect remapVecValids[11], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[11] node _T_3651 = eq(UInt<5>(0h1d), remapindex_11) when _T_3651 : connect remapVecData[11], Queue10_UInt8_29.io.deq.bits connect remapVecValids[11], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[11] node _T_3652 = eq(UInt<5>(0h1e), remapindex_11) when _T_3652 : connect remapVecData[11], Queue10_UInt8_30.io.deq.bits connect remapVecValids[11], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[11] node _T_3653 = eq(UInt<5>(0h1f), remapindex_11) when _T_3653 : connect remapVecData[11], Queue10_UInt8_31.io.deq.bits connect remapVecValids[11], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[11] node _remapindex_T_12 = add(UInt<4>(0hc), read_start_index) node remapindex_12 = rem(_remapindex_T_12, UInt<6>(0h20)) node _T_3654 = eq(UInt<1>(0h0), remapindex_12) when _T_3654 : connect remapVecData[12], Queue10_UInt8.io.deq.bits connect remapVecValids[12], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[12] node _T_3655 = eq(UInt<1>(0h1), remapindex_12) when _T_3655 : connect remapVecData[12], Queue10_UInt8_1.io.deq.bits connect remapVecValids[12], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[12] node _T_3656 = eq(UInt<2>(0h2), remapindex_12) when _T_3656 : connect remapVecData[12], Queue10_UInt8_2.io.deq.bits connect remapVecValids[12], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[12] node _T_3657 = eq(UInt<2>(0h3), remapindex_12) when _T_3657 : connect remapVecData[12], Queue10_UInt8_3.io.deq.bits connect remapVecValids[12], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[12] node _T_3658 = eq(UInt<3>(0h4), remapindex_12) when _T_3658 : connect remapVecData[12], Queue10_UInt8_4.io.deq.bits connect remapVecValids[12], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[12] node _T_3659 = eq(UInt<3>(0h5), remapindex_12) when _T_3659 : connect remapVecData[12], Queue10_UInt8_5.io.deq.bits connect remapVecValids[12], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[12] node _T_3660 = eq(UInt<3>(0h6), remapindex_12) when _T_3660 : connect remapVecData[12], Queue10_UInt8_6.io.deq.bits connect remapVecValids[12], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[12] node _T_3661 = eq(UInt<3>(0h7), remapindex_12) when _T_3661 : connect remapVecData[12], Queue10_UInt8_7.io.deq.bits connect remapVecValids[12], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[12] node _T_3662 = eq(UInt<4>(0h8), remapindex_12) when _T_3662 : connect remapVecData[12], Queue10_UInt8_8.io.deq.bits connect remapVecValids[12], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[12] node _T_3663 = eq(UInt<4>(0h9), remapindex_12) when _T_3663 : connect remapVecData[12], Queue10_UInt8_9.io.deq.bits connect remapVecValids[12], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[12] node _T_3664 = eq(UInt<4>(0ha), remapindex_12) when _T_3664 : connect remapVecData[12], Queue10_UInt8_10.io.deq.bits connect remapVecValids[12], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[12] node _T_3665 = eq(UInt<4>(0hb), remapindex_12) when _T_3665 : connect remapVecData[12], Queue10_UInt8_11.io.deq.bits connect remapVecValids[12], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[12] node _T_3666 = eq(UInt<4>(0hc), remapindex_12) when _T_3666 : connect remapVecData[12], Queue10_UInt8_12.io.deq.bits connect remapVecValids[12], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[12] node _T_3667 = eq(UInt<4>(0hd), remapindex_12) when _T_3667 : connect remapVecData[12], Queue10_UInt8_13.io.deq.bits connect remapVecValids[12], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[12] node _T_3668 = eq(UInt<4>(0he), remapindex_12) when _T_3668 : connect remapVecData[12], Queue10_UInt8_14.io.deq.bits connect remapVecValids[12], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[12] node _T_3669 = eq(UInt<4>(0hf), remapindex_12) when _T_3669 : connect remapVecData[12], Queue10_UInt8_15.io.deq.bits connect remapVecValids[12], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[12] node _T_3670 = eq(UInt<5>(0h10), remapindex_12) when _T_3670 : connect remapVecData[12], Queue10_UInt8_16.io.deq.bits connect remapVecValids[12], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[12] node _T_3671 = eq(UInt<5>(0h11), remapindex_12) when _T_3671 : connect remapVecData[12], Queue10_UInt8_17.io.deq.bits connect remapVecValids[12], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[12] node _T_3672 = eq(UInt<5>(0h12), remapindex_12) when _T_3672 : connect remapVecData[12], Queue10_UInt8_18.io.deq.bits connect remapVecValids[12], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[12] node _T_3673 = eq(UInt<5>(0h13), remapindex_12) when _T_3673 : connect remapVecData[12], Queue10_UInt8_19.io.deq.bits connect remapVecValids[12], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[12] node _T_3674 = eq(UInt<5>(0h14), remapindex_12) when _T_3674 : connect remapVecData[12], Queue10_UInt8_20.io.deq.bits connect remapVecValids[12], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[12] node _T_3675 = eq(UInt<5>(0h15), remapindex_12) when _T_3675 : connect remapVecData[12], Queue10_UInt8_21.io.deq.bits connect remapVecValids[12], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[12] node _T_3676 = eq(UInt<5>(0h16), remapindex_12) when _T_3676 : connect remapVecData[12], Queue10_UInt8_22.io.deq.bits connect remapVecValids[12], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[12] node _T_3677 = eq(UInt<5>(0h17), remapindex_12) when _T_3677 : connect remapVecData[12], Queue10_UInt8_23.io.deq.bits connect remapVecValids[12], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[12] node _T_3678 = eq(UInt<5>(0h18), remapindex_12) when _T_3678 : connect remapVecData[12], Queue10_UInt8_24.io.deq.bits connect remapVecValids[12], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[12] node _T_3679 = eq(UInt<5>(0h19), remapindex_12) when _T_3679 : connect remapVecData[12], Queue10_UInt8_25.io.deq.bits connect remapVecValids[12], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[12] node _T_3680 = eq(UInt<5>(0h1a), remapindex_12) when _T_3680 : connect remapVecData[12], Queue10_UInt8_26.io.deq.bits connect remapVecValids[12], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[12] node _T_3681 = eq(UInt<5>(0h1b), remapindex_12) when _T_3681 : connect remapVecData[12], Queue10_UInt8_27.io.deq.bits connect remapVecValids[12], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[12] node _T_3682 = eq(UInt<5>(0h1c), remapindex_12) when _T_3682 : connect remapVecData[12], Queue10_UInt8_28.io.deq.bits connect remapVecValids[12], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[12] node _T_3683 = eq(UInt<5>(0h1d), remapindex_12) when _T_3683 : connect remapVecData[12], Queue10_UInt8_29.io.deq.bits connect remapVecValids[12], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[12] node _T_3684 = eq(UInt<5>(0h1e), remapindex_12) when _T_3684 : connect remapVecData[12], Queue10_UInt8_30.io.deq.bits connect remapVecValids[12], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[12] node _T_3685 = eq(UInt<5>(0h1f), remapindex_12) when _T_3685 : connect remapVecData[12], Queue10_UInt8_31.io.deq.bits connect remapVecValids[12], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[12] node _remapindex_T_13 = add(UInt<4>(0hd), read_start_index) node remapindex_13 = rem(_remapindex_T_13, UInt<6>(0h20)) node _T_3686 = eq(UInt<1>(0h0), remapindex_13) when _T_3686 : connect remapVecData[13], Queue10_UInt8.io.deq.bits connect remapVecValids[13], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[13] node _T_3687 = eq(UInt<1>(0h1), remapindex_13) when _T_3687 : connect remapVecData[13], Queue10_UInt8_1.io.deq.bits connect remapVecValids[13], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[13] node _T_3688 = eq(UInt<2>(0h2), remapindex_13) when _T_3688 : connect remapVecData[13], Queue10_UInt8_2.io.deq.bits connect remapVecValids[13], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[13] node _T_3689 = eq(UInt<2>(0h3), remapindex_13) when _T_3689 : connect remapVecData[13], Queue10_UInt8_3.io.deq.bits connect remapVecValids[13], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[13] node _T_3690 = eq(UInt<3>(0h4), remapindex_13) when _T_3690 : connect remapVecData[13], Queue10_UInt8_4.io.deq.bits connect remapVecValids[13], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[13] node _T_3691 = eq(UInt<3>(0h5), remapindex_13) when _T_3691 : connect remapVecData[13], Queue10_UInt8_5.io.deq.bits connect remapVecValids[13], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[13] node _T_3692 = eq(UInt<3>(0h6), remapindex_13) when _T_3692 : connect remapVecData[13], Queue10_UInt8_6.io.deq.bits connect remapVecValids[13], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[13] node _T_3693 = eq(UInt<3>(0h7), remapindex_13) when _T_3693 : connect remapVecData[13], Queue10_UInt8_7.io.deq.bits connect remapVecValids[13], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[13] node _T_3694 = eq(UInt<4>(0h8), remapindex_13) when _T_3694 : connect remapVecData[13], Queue10_UInt8_8.io.deq.bits connect remapVecValids[13], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[13] node _T_3695 = eq(UInt<4>(0h9), remapindex_13) when _T_3695 : connect remapVecData[13], Queue10_UInt8_9.io.deq.bits connect remapVecValids[13], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[13] node _T_3696 = eq(UInt<4>(0ha), remapindex_13) when _T_3696 : connect remapVecData[13], Queue10_UInt8_10.io.deq.bits connect remapVecValids[13], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[13] node _T_3697 = eq(UInt<4>(0hb), remapindex_13) when _T_3697 : connect remapVecData[13], Queue10_UInt8_11.io.deq.bits connect remapVecValids[13], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[13] node _T_3698 = eq(UInt<4>(0hc), remapindex_13) when _T_3698 : connect remapVecData[13], Queue10_UInt8_12.io.deq.bits connect remapVecValids[13], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[13] node _T_3699 = eq(UInt<4>(0hd), remapindex_13) when _T_3699 : connect remapVecData[13], Queue10_UInt8_13.io.deq.bits connect remapVecValids[13], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[13] node _T_3700 = eq(UInt<4>(0he), remapindex_13) when _T_3700 : connect remapVecData[13], Queue10_UInt8_14.io.deq.bits connect remapVecValids[13], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[13] node _T_3701 = eq(UInt<4>(0hf), remapindex_13) when _T_3701 : connect remapVecData[13], Queue10_UInt8_15.io.deq.bits connect remapVecValids[13], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[13] node _T_3702 = eq(UInt<5>(0h10), remapindex_13) when _T_3702 : connect remapVecData[13], Queue10_UInt8_16.io.deq.bits connect remapVecValids[13], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[13] node _T_3703 = eq(UInt<5>(0h11), remapindex_13) when _T_3703 : connect remapVecData[13], Queue10_UInt8_17.io.deq.bits connect remapVecValids[13], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[13] node _T_3704 = eq(UInt<5>(0h12), remapindex_13) when _T_3704 : connect remapVecData[13], Queue10_UInt8_18.io.deq.bits connect remapVecValids[13], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[13] node _T_3705 = eq(UInt<5>(0h13), remapindex_13) when _T_3705 : connect remapVecData[13], Queue10_UInt8_19.io.deq.bits connect remapVecValids[13], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[13] node _T_3706 = eq(UInt<5>(0h14), remapindex_13) when _T_3706 : connect remapVecData[13], Queue10_UInt8_20.io.deq.bits connect remapVecValids[13], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[13] node _T_3707 = eq(UInt<5>(0h15), remapindex_13) when _T_3707 : connect remapVecData[13], Queue10_UInt8_21.io.deq.bits connect remapVecValids[13], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[13] node _T_3708 = eq(UInt<5>(0h16), remapindex_13) when _T_3708 : connect remapVecData[13], Queue10_UInt8_22.io.deq.bits connect remapVecValids[13], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[13] node _T_3709 = eq(UInt<5>(0h17), remapindex_13) when _T_3709 : connect remapVecData[13], Queue10_UInt8_23.io.deq.bits connect remapVecValids[13], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[13] node _T_3710 = eq(UInt<5>(0h18), remapindex_13) when _T_3710 : connect remapVecData[13], Queue10_UInt8_24.io.deq.bits connect remapVecValids[13], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[13] node _T_3711 = eq(UInt<5>(0h19), remapindex_13) when _T_3711 : connect remapVecData[13], Queue10_UInt8_25.io.deq.bits connect remapVecValids[13], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[13] node _T_3712 = eq(UInt<5>(0h1a), remapindex_13) when _T_3712 : connect remapVecData[13], Queue10_UInt8_26.io.deq.bits connect remapVecValids[13], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[13] node _T_3713 = eq(UInt<5>(0h1b), remapindex_13) when _T_3713 : connect remapVecData[13], Queue10_UInt8_27.io.deq.bits connect remapVecValids[13], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[13] node _T_3714 = eq(UInt<5>(0h1c), remapindex_13) when _T_3714 : connect remapVecData[13], Queue10_UInt8_28.io.deq.bits connect remapVecValids[13], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[13] node _T_3715 = eq(UInt<5>(0h1d), remapindex_13) when _T_3715 : connect remapVecData[13], Queue10_UInt8_29.io.deq.bits connect remapVecValids[13], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[13] node _T_3716 = eq(UInt<5>(0h1e), remapindex_13) when _T_3716 : connect remapVecData[13], Queue10_UInt8_30.io.deq.bits connect remapVecValids[13], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[13] node _T_3717 = eq(UInt<5>(0h1f), remapindex_13) when _T_3717 : connect remapVecData[13], Queue10_UInt8_31.io.deq.bits connect remapVecValids[13], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[13] node _remapindex_T_14 = add(UInt<4>(0he), read_start_index) node remapindex_14 = rem(_remapindex_T_14, UInt<6>(0h20)) node _T_3718 = eq(UInt<1>(0h0), remapindex_14) when _T_3718 : connect remapVecData[14], Queue10_UInt8.io.deq.bits connect remapVecValids[14], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[14] node _T_3719 = eq(UInt<1>(0h1), remapindex_14) when _T_3719 : connect remapVecData[14], Queue10_UInt8_1.io.deq.bits connect remapVecValids[14], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[14] node _T_3720 = eq(UInt<2>(0h2), remapindex_14) when _T_3720 : connect remapVecData[14], Queue10_UInt8_2.io.deq.bits connect remapVecValids[14], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[14] node _T_3721 = eq(UInt<2>(0h3), remapindex_14) when _T_3721 : connect remapVecData[14], Queue10_UInt8_3.io.deq.bits connect remapVecValids[14], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[14] node _T_3722 = eq(UInt<3>(0h4), remapindex_14) when _T_3722 : connect remapVecData[14], Queue10_UInt8_4.io.deq.bits connect remapVecValids[14], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[14] node _T_3723 = eq(UInt<3>(0h5), remapindex_14) when _T_3723 : connect remapVecData[14], Queue10_UInt8_5.io.deq.bits connect remapVecValids[14], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[14] node _T_3724 = eq(UInt<3>(0h6), remapindex_14) when _T_3724 : connect remapVecData[14], Queue10_UInt8_6.io.deq.bits connect remapVecValids[14], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[14] node _T_3725 = eq(UInt<3>(0h7), remapindex_14) when _T_3725 : connect remapVecData[14], Queue10_UInt8_7.io.deq.bits connect remapVecValids[14], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[14] node _T_3726 = eq(UInt<4>(0h8), remapindex_14) when _T_3726 : connect remapVecData[14], Queue10_UInt8_8.io.deq.bits connect remapVecValids[14], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[14] node _T_3727 = eq(UInt<4>(0h9), remapindex_14) when _T_3727 : connect remapVecData[14], Queue10_UInt8_9.io.deq.bits connect remapVecValids[14], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[14] node _T_3728 = eq(UInt<4>(0ha), remapindex_14) when _T_3728 : connect remapVecData[14], Queue10_UInt8_10.io.deq.bits connect remapVecValids[14], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[14] node _T_3729 = eq(UInt<4>(0hb), remapindex_14) when _T_3729 : connect remapVecData[14], Queue10_UInt8_11.io.deq.bits connect remapVecValids[14], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[14] node _T_3730 = eq(UInt<4>(0hc), remapindex_14) when _T_3730 : connect remapVecData[14], Queue10_UInt8_12.io.deq.bits connect remapVecValids[14], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[14] node _T_3731 = eq(UInt<4>(0hd), remapindex_14) when _T_3731 : connect remapVecData[14], Queue10_UInt8_13.io.deq.bits connect remapVecValids[14], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[14] node _T_3732 = eq(UInt<4>(0he), remapindex_14) when _T_3732 : connect remapVecData[14], Queue10_UInt8_14.io.deq.bits connect remapVecValids[14], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[14] node _T_3733 = eq(UInt<4>(0hf), remapindex_14) when _T_3733 : connect remapVecData[14], Queue10_UInt8_15.io.deq.bits connect remapVecValids[14], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[14] node _T_3734 = eq(UInt<5>(0h10), remapindex_14) when _T_3734 : connect remapVecData[14], Queue10_UInt8_16.io.deq.bits connect remapVecValids[14], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[14] node _T_3735 = eq(UInt<5>(0h11), remapindex_14) when _T_3735 : connect remapVecData[14], Queue10_UInt8_17.io.deq.bits connect remapVecValids[14], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[14] node _T_3736 = eq(UInt<5>(0h12), remapindex_14) when _T_3736 : connect remapVecData[14], Queue10_UInt8_18.io.deq.bits connect remapVecValids[14], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[14] node _T_3737 = eq(UInt<5>(0h13), remapindex_14) when _T_3737 : connect remapVecData[14], Queue10_UInt8_19.io.deq.bits connect remapVecValids[14], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[14] node _T_3738 = eq(UInt<5>(0h14), remapindex_14) when _T_3738 : connect remapVecData[14], Queue10_UInt8_20.io.deq.bits connect remapVecValids[14], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[14] node _T_3739 = eq(UInt<5>(0h15), remapindex_14) when _T_3739 : connect remapVecData[14], Queue10_UInt8_21.io.deq.bits connect remapVecValids[14], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[14] node _T_3740 = eq(UInt<5>(0h16), remapindex_14) when _T_3740 : connect remapVecData[14], Queue10_UInt8_22.io.deq.bits connect remapVecValids[14], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[14] node _T_3741 = eq(UInt<5>(0h17), remapindex_14) when _T_3741 : connect remapVecData[14], Queue10_UInt8_23.io.deq.bits connect remapVecValids[14], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[14] node _T_3742 = eq(UInt<5>(0h18), remapindex_14) when _T_3742 : connect remapVecData[14], Queue10_UInt8_24.io.deq.bits connect remapVecValids[14], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[14] node _T_3743 = eq(UInt<5>(0h19), remapindex_14) when _T_3743 : connect remapVecData[14], Queue10_UInt8_25.io.deq.bits connect remapVecValids[14], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[14] node _T_3744 = eq(UInt<5>(0h1a), remapindex_14) when _T_3744 : connect remapVecData[14], Queue10_UInt8_26.io.deq.bits connect remapVecValids[14], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[14] node _T_3745 = eq(UInt<5>(0h1b), remapindex_14) when _T_3745 : connect remapVecData[14], Queue10_UInt8_27.io.deq.bits connect remapVecValids[14], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[14] node _T_3746 = eq(UInt<5>(0h1c), remapindex_14) when _T_3746 : connect remapVecData[14], Queue10_UInt8_28.io.deq.bits connect remapVecValids[14], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[14] node _T_3747 = eq(UInt<5>(0h1d), remapindex_14) when _T_3747 : connect remapVecData[14], Queue10_UInt8_29.io.deq.bits connect remapVecValids[14], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[14] node _T_3748 = eq(UInt<5>(0h1e), remapindex_14) when _T_3748 : connect remapVecData[14], Queue10_UInt8_30.io.deq.bits connect remapVecValids[14], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[14] node _T_3749 = eq(UInt<5>(0h1f), remapindex_14) when _T_3749 : connect remapVecData[14], Queue10_UInt8_31.io.deq.bits connect remapVecValids[14], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[14] node _remapindex_T_15 = add(UInt<4>(0hf), read_start_index) node remapindex_15 = rem(_remapindex_T_15, UInt<6>(0h20)) node _T_3750 = eq(UInt<1>(0h0), remapindex_15) when _T_3750 : connect remapVecData[15], Queue10_UInt8.io.deq.bits connect remapVecValids[15], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[15] node _T_3751 = eq(UInt<1>(0h1), remapindex_15) when _T_3751 : connect remapVecData[15], Queue10_UInt8_1.io.deq.bits connect remapVecValids[15], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[15] node _T_3752 = eq(UInt<2>(0h2), remapindex_15) when _T_3752 : connect remapVecData[15], Queue10_UInt8_2.io.deq.bits connect remapVecValids[15], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[15] node _T_3753 = eq(UInt<2>(0h3), remapindex_15) when _T_3753 : connect remapVecData[15], Queue10_UInt8_3.io.deq.bits connect remapVecValids[15], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[15] node _T_3754 = eq(UInt<3>(0h4), remapindex_15) when _T_3754 : connect remapVecData[15], Queue10_UInt8_4.io.deq.bits connect remapVecValids[15], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[15] node _T_3755 = eq(UInt<3>(0h5), remapindex_15) when _T_3755 : connect remapVecData[15], Queue10_UInt8_5.io.deq.bits connect remapVecValids[15], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[15] node _T_3756 = eq(UInt<3>(0h6), remapindex_15) when _T_3756 : connect remapVecData[15], Queue10_UInt8_6.io.deq.bits connect remapVecValids[15], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[15] node _T_3757 = eq(UInt<3>(0h7), remapindex_15) when _T_3757 : connect remapVecData[15], Queue10_UInt8_7.io.deq.bits connect remapVecValids[15], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[15] node _T_3758 = eq(UInt<4>(0h8), remapindex_15) when _T_3758 : connect remapVecData[15], Queue10_UInt8_8.io.deq.bits connect remapVecValids[15], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[15] node _T_3759 = eq(UInt<4>(0h9), remapindex_15) when _T_3759 : connect remapVecData[15], Queue10_UInt8_9.io.deq.bits connect remapVecValids[15], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[15] node _T_3760 = eq(UInt<4>(0ha), remapindex_15) when _T_3760 : connect remapVecData[15], Queue10_UInt8_10.io.deq.bits connect remapVecValids[15], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[15] node _T_3761 = eq(UInt<4>(0hb), remapindex_15) when _T_3761 : connect remapVecData[15], Queue10_UInt8_11.io.deq.bits connect remapVecValids[15], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[15] node _T_3762 = eq(UInt<4>(0hc), remapindex_15) when _T_3762 : connect remapVecData[15], Queue10_UInt8_12.io.deq.bits connect remapVecValids[15], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[15] node _T_3763 = eq(UInt<4>(0hd), remapindex_15) when _T_3763 : connect remapVecData[15], Queue10_UInt8_13.io.deq.bits connect remapVecValids[15], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[15] node _T_3764 = eq(UInt<4>(0he), remapindex_15) when _T_3764 : connect remapVecData[15], Queue10_UInt8_14.io.deq.bits connect remapVecValids[15], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[15] node _T_3765 = eq(UInt<4>(0hf), remapindex_15) when _T_3765 : connect remapVecData[15], Queue10_UInt8_15.io.deq.bits connect remapVecValids[15], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[15] node _T_3766 = eq(UInt<5>(0h10), remapindex_15) when _T_3766 : connect remapVecData[15], Queue10_UInt8_16.io.deq.bits connect remapVecValids[15], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[15] node _T_3767 = eq(UInt<5>(0h11), remapindex_15) when _T_3767 : connect remapVecData[15], Queue10_UInt8_17.io.deq.bits connect remapVecValids[15], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[15] node _T_3768 = eq(UInt<5>(0h12), remapindex_15) when _T_3768 : connect remapVecData[15], Queue10_UInt8_18.io.deq.bits connect remapVecValids[15], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[15] node _T_3769 = eq(UInt<5>(0h13), remapindex_15) when _T_3769 : connect remapVecData[15], Queue10_UInt8_19.io.deq.bits connect remapVecValids[15], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[15] node _T_3770 = eq(UInt<5>(0h14), remapindex_15) when _T_3770 : connect remapVecData[15], Queue10_UInt8_20.io.deq.bits connect remapVecValids[15], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[15] node _T_3771 = eq(UInt<5>(0h15), remapindex_15) when _T_3771 : connect remapVecData[15], Queue10_UInt8_21.io.deq.bits connect remapVecValids[15], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[15] node _T_3772 = eq(UInt<5>(0h16), remapindex_15) when _T_3772 : connect remapVecData[15], Queue10_UInt8_22.io.deq.bits connect remapVecValids[15], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[15] node _T_3773 = eq(UInt<5>(0h17), remapindex_15) when _T_3773 : connect remapVecData[15], Queue10_UInt8_23.io.deq.bits connect remapVecValids[15], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[15] node _T_3774 = eq(UInt<5>(0h18), remapindex_15) when _T_3774 : connect remapVecData[15], Queue10_UInt8_24.io.deq.bits connect remapVecValids[15], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[15] node _T_3775 = eq(UInt<5>(0h19), remapindex_15) when _T_3775 : connect remapVecData[15], Queue10_UInt8_25.io.deq.bits connect remapVecValids[15], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[15] node _T_3776 = eq(UInt<5>(0h1a), remapindex_15) when _T_3776 : connect remapVecData[15], Queue10_UInt8_26.io.deq.bits connect remapVecValids[15], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[15] node _T_3777 = eq(UInt<5>(0h1b), remapindex_15) when _T_3777 : connect remapVecData[15], Queue10_UInt8_27.io.deq.bits connect remapVecValids[15], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[15] node _T_3778 = eq(UInt<5>(0h1c), remapindex_15) when _T_3778 : connect remapVecData[15], Queue10_UInt8_28.io.deq.bits connect remapVecValids[15], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[15] node _T_3779 = eq(UInt<5>(0h1d), remapindex_15) when _T_3779 : connect remapVecData[15], Queue10_UInt8_29.io.deq.bits connect remapVecValids[15], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[15] node _T_3780 = eq(UInt<5>(0h1e), remapindex_15) when _T_3780 : connect remapVecData[15], Queue10_UInt8_30.io.deq.bits connect remapVecValids[15], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[15] node _T_3781 = eq(UInt<5>(0h1f), remapindex_15) when _T_3781 : connect remapVecData[15], Queue10_UInt8_31.io.deq.bits connect remapVecValids[15], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[15] node _remapindex_T_16 = add(UInt<5>(0h10), read_start_index) node remapindex_16 = rem(_remapindex_T_16, UInt<6>(0h20)) node _T_3782 = eq(UInt<1>(0h0), remapindex_16) when _T_3782 : connect remapVecData[16], Queue10_UInt8.io.deq.bits connect remapVecValids[16], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[16] node _T_3783 = eq(UInt<1>(0h1), remapindex_16) when _T_3783 : connect remapVecData[16], Queue10_UInt8_1.io.deq.bits connect remapVecValids[16], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[16] node _T_3784 = eq(UInt<2>(0h2), remapindex_16) when _T_3784 : connect remapVecData[16], Queue10_UInt8_2.io.deq.bits connect remapVecValids[16], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[16] node _T_3785 = eq(UInt<2>(0h3), remapindex_16) when _T_3785 : connect remapVecData[16], Queue10_UInt8_3.io.deq.bits connect remapVecValids[16], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[16] node _T_3786 = eq(UInt<3>(0h4), remapindex_16) when _T_3786 : connect remapVecData[16], Queue10_UInt8_4.io.deq.bits connect remapVecValids[16], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[16] node _T_3787 = eq(UInt<3>(0h5), remapindex_16) when _T_3787 : connect remapVecData[16], Queue10_UInt8_5.io.deq.bits connect remapVecValids[16], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[16] node _T_3788 = eq(UInt<3>(0h6), remapindex_16) when _T_3788 : connect remapVecData[16], Queue10_UInt8_6.io.deq.bits connect remapVecValids[16], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[16] node _T_3789 = eq(UInt<3>(0h7), remapindex_16) when _T_3789 : connect remapVecData[16], Queue10_UInt8_7.io.deq.bits connect remapVecValids[16], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[16] node _T_3790 = eq(UInt<4>(0h8), remapindex_16) when _T_3790 : connect remapVecData[16], Queue10_UInt8_8.io.deq.bits connect remapVecValids[16], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[16] node _T_3791 = eq(UInt<4>(0h9), remapindex_16) when _T_3791 : connect remapVecData[16], Queue10_UInt8_9.io.deq.bits connect remapVecValids[16], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[16] node _T_3792 = eq(UInt<4>(0ha), remapindex_16) when _T_3792 : connect remapVecData[16], Queue10_UInt8_10.io.deq.bits connect remapVecValids[16], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[16] node _T_3793 = eq(UInt<4>(0hb), remapindex_16) when _T_3793 : connect remapVecData[16], Queue10_UInt8_11.io.deq.bits connect remapVecValids[16], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[16] node _T_3794 = eq(UInt<4>(0hc), remapindex_16) when _T_3794 : connect remapVecData[16], Queue10_UInt8_12.io.deq.bits connect remapVecValids[16], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[16] node _T_3795 = eq(UInt<4>(0hd), remapindex_16) when _T_3795 : connect remapVecData[16], Queue10_UInt8_13.io.deq.bits connect remapVecValids[16], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[16] node _T_3796 = eq(UInt<4>(0he), remapindex_16) when _T_3796 : connect remapVecData[16], Queue10_UInt8_14.io.deq.bits connect remapVecValids[16], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[16] node _T_3797 = eq(UInt<4>(0hf), remapindex_16) when _T_3797 : connect remapVecData[16], Queue10_UInt8_15.io.deq.bits connect remapVecValids[16], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[16] node _T_3798 = eq(UInt<5>(0h10), remapindex_16) when _T_3798 : connect remapVecData[16], Queue10_UInt8_16.io.deq.bits connect remapVecValids[16], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[16] node _T_3799 = eq(UInt<5>(0h11), remapindex_16) when _T_3799 : connect remapVecData[16], Queue10_UInt8_17.io.deq.bits connect remapVecValids[16], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[16] node _T_3800 = eq(UInt<5>(0h12), remapindex_16) when _T_3800 : connect remapVecData[16], Queue10_UInt8_18.io.deq.bits connect remapVecValids[16], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[16] node _T_3801 = eq(UInt<5>(0h13), remapindex_16) when _T_3801 : connect remapVecData[16], Queue10_UInt8_19.io.deq.bits connect remapVecValids[16], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[16] node _T_3802 = eq(UInt<5>(0h14), remapindex_16) when _T_3802 : connect remapVecData[16], Queue10_UInt8_20.io.deq.bits connect remapVecValids[16], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[16] node _T_3803 = eq(UInt<5>(0h15), remapindex_16) when _T_3803 : connect remapVecData[16], Queue10_UInt8_21.io.deq.bits connect remapVecValids[16], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[16] node _T_3804 = eq(UInt<5>(0h16), remapindex_16) when _T_3804 : connect remapVecData[16], Queue10_UInt8_22.io.deq.bits connect remapVecValids[16], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[16] node _T_3805 = eq(UInt<5>(0h17), remapindex_16) when _T_3805 : connect remapVecData[16], Queue10_UInt8_23.io.deq.bits connect remapVecValids[16], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[16] node _T_3806 = eq(UInt<5>(0h18), remapindex_16) when _T_3806 : connect remapVecData[16], Queue10_UInt8_24.io.deq.bits connect remapVecValids[16], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[16] node _T_3807 = eq(UInt<5>(0h19), remapindex_16) when _T_3807 : connect remapVecData[16], Queue10_UInt8_25.io.deq.bits connect remapVecValids[16], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[16] node _T_3808 = eq(UInt<5>(0h1a), remapindex_16) when _T_3808 : connect remapVecData[16], Queue10_UInt8_26.io.deq.bits connect remapVecValids[16], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[16] node _T_3809 = eq(UInt<5>(0h1b), remapindex_16) when _T_3809 : connect remapVecData[16], Queue10_UInt8_27.io.deq.bits connect remapVecValids[16], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[16] node _T_3810 = eq(UInt<5>(0h1c), remapindex_16) when _T_3810 : connect remapVecData[16], Queue10_UInt8_28.io.deq.bits connect remapVecValids[16], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[16] node _T_3811 = eq(UInt<5>(0h1d), remapindex_16) when _T_3811 : connect remapVecData[16], Queue10_UInt8_29.io.deq.bits connect remapVecValids[16], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[16] node _T_3812 = eq(UInt<5>(0h1e), remapindex_16) when _T_3812 : connect remapVecData[16], Queue10_UInt8_30.io.deq.bits connect remapVecValids[16], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[16] node _T_3813 = eq(UInt<5>(0h1f), remapindex_16) when _T_3813 : connect remapVecData[16], Queue10_UInt8_31.io.deq.bits connect remapVecValids[16], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[16] node _remapindex_T_17 = add(UInt<5>(0h11), read_start_index) node remapindex_17 = rem(_remapindex_T_17, UInt<6>(0h20)) node _T_3814 = eq(UInt<1>(0h0), remapindex_17) when _T_3814 : connect remapVecData[17], Queue10_UInt8.io.deq.bits connect remapVecValids[17], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[17] node _T_3815 = eq(UInt<1>(0h1), remapindex_17) when _T_3815 : connect remapVecData[17], Queue10_UInt8_1.io.deq.bits connect remapVecValids[17], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[17] node _T_3816 = eq(UInt<2>(0h2), remapindex_17) when _T_3816 : connect remapVecData[17], Queue10_UInt8_2.io.deq.bits connect remapVecValids[17], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[17] node _T_3817 = eq(UInt<2>(0h3), remapindex_17) when _T_3817 : connect remapVecData[17], Queue10_UInt8_3.io.deq.bits connect remapVecValids[17], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[17] node _T_3818 = eq(UInt<3>(0h4), remapindex_17) when _T_3818 : connect remapVecData[17], Queue10_UInt8_4.io.deq.bits connect remapVecValids[17], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[17] node _T_3819 = eq(UInt<3>(0h5), remapindex_17) when _T_3819 : connect remapVecData[17], Queue10_UInt8_5.io.deq.bits connect remapVecValids[17], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[17] node _T_3820 = eq(UInt<3>(0h6), remapindex_17) when _T_3820 : connect remapVecData[17], Queue10_UInt8_6.io.deq.bits connect remapVecValids[17], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[17] node _T_3821 = eq(UInt<3>(0h7), remapindex_17) when _T_3821 : connect remapVecData[17], Queue10_UInt8_7.io.deq.bits connect remapVecValids[17], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[17] node _T_3822 = eq(UInt<4>(0h8), remapindex_17) when _T_3822 : connect remapVecData[17], Queue10_UInt8_8.io.deq.bits connect remapVecValids[17], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[17] node _T_3823 = eq(UInt<4>(0h9), remapindex_17) when _T_3823 : connect remapVecData[17], Queue10_UInt8_9.io.deq.bits connect remapVecValids[17], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[17] node _T_3824 = eq(UInt<4>(0ha), remapindex_17) when _T_3824 : connect remapVecData[17], Queue10_UInt8_10.io.deq.bits connect remapVecValids[17], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[17] node _T_3825 = eq(UInt<4>(0hb), remapindex_17) when _T_3825 : connect remapVecData[17], Queue10_UInt8_11.io.deq.bits connect remapVecValids[17], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[17] node _T_3826 = eq(UInt<4>(0hc), remapindex_17) when _T_3826 : connect remapVecData[17], Queue10_UInt8_12.io.deq.bits connect remapVecValids[17], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[17] node _T_3827 = eq(UInt<4>(0hd), remapindex_17) when _T_3827 : connect remapVecData[17], Queue10_UInt8_13.io.deq.bits connect remapVecValids[17], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[17] node _T_3828 = eq(UInt<4>(0he), remapindex_17) when _T_3828 : connect remapVecData[17], Queue10_UInt8_14.io.deq.bits connect remapVecValids[17], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[17] node _T_3829 = eq(UInt<4>(0hf), remapindex_17) when _T_3829 : connect remapVecData[17], Queue10_UInt8_15.io.deq.bits connect remapVecValids[17], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[17] node _T_3830 = eq(UInt<5>(0h10), remapindex_17) when _T_3830 : connect remapVecData[17], Queue10_UInt8_16.io.deq.bits connect remapVecValids[17], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[17] node _T_3831 = eq(UInt<5>(0h11), remapindex_17) when _T_3831 : connect remapVecData[17], Queue10_UInt8_17.io.deq.bits connect remapVecValids[17], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[17] node _T_3832 = eq(UInt<5>(0h12), remapindex_17) when _T_3832 : connect remapVecData[17], Queue10_UInt8_18.io.deq.bits connect remapVecValids[17], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[17] node _T_3833 = eq(UInt<5>(0h13), remapindex_17) when _T_3833 : connect remapVecData[17], Queue10_UInt8_19.io.deq.bits connect remapVecValids[17], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[17] node _T_3834 = eq(UInt<5>(0h14), remapindex_17) when _T_3834 : connect remapVecData[17], Queue10_UInt8_20.io.deq.bits connect remapVecValids[17], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[17] node _T_3835 = eq(UInt<5>(0h15), remapindex_17) when _T_3835 : connect remapVecData[17], Queue10_UInt8_21.io.deq.bits connect remapVecValids[17], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[17] node _T_3836 = eq(UInt<5>(0h16), remapindex_17) when _T_3836 : connect remapVecData[17], Queue10_UInt8_22.io.deq.bits connect remapVecValids[17], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[17] node _T_3837 = eq(UInt<5>(0h17), remapindex_17) when _T_3837 : connect remapVecData[17], Queue10_UInt8_23.io.deq.bits connect remapVecValids[17], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[17] node _T_3838 = eq(UInt<5>(0h18), remapindex_17) when _T_3838 : connect remapVecData[17], Queue10_UInt8_24.io.deq.bits connect remapVecValids[17], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[17] node _T_3839 = eq(UInt<5>(0h19), remapindex_17) when _T_3839 : connect remapVecData[17], Queue10_UInt8_25.io.deq.bits connect remapVecValids[17], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[17] node _T_3840 = eq(UInt<5>(0h1a), remapindex_17) when _T_3840 : connect remapVecData[17], Queue10_UInt8_26.io.deq.bits connect remapVecValids[17], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[17] node _T_3841 = eq(UInt<5>(0h1b), remapindex_17) when _T_3841 : connect remapVecData[17], Queue10_UInt8_27.io.deq.bits connect remapVecValids[17], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[17] node _T_3842 = eq(UInt<5>(0h1c), remapindex_17) when _T_3842 : connect remapVecData[17], Queue10_UInt8_28.io.deq.bits connect remapVecValids[17], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[17] node _T_3843 = eq(UInt<5>(0h1d), remapindex_17) when _T_3843 : connect remapVecData[17], Queue10_UInt8_29.io.deq.bits connect remapVecValids[17], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[17] node _T_3844 = eq(UInt<5>(0h1e), remapindex_17) when _T_3844 : connect remapVecData[17], Queue10_UInt8_30.io.deq.bits connect remapVecValids[17], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[17] node _T_3845 = eq(UInt<5>(0h1f), remapindex_17) when _T_3845 : connect remapVecData[17], Queue10_UInt8_31.io.deq.bits connect remapVecValids[17], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[17] node _remapindex_T_18 = add(UInt<5>(0h12), read_start_index) node remapindex_18 = rem(_remapindex_T_18, UInt<6>(0h20)) node _T_3846 = eq(UInt<1>(0h0), remapindex_18) when _T_3846 : connect remapVecData[18], Queue10_UInt8.io.deq.bits connect remapVecValids[18], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[18] node _T_3847 = eq(UInt<1>(0h1), remapindex_18) when _T_3847 : connect remapVecData[18], Queue10_UInt8_1.io.deq.bits connect remapVecValids[18], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[18] node _T_3848 = eq(UInt<2>(0h2), remapindex_18) when _T_3848 : connect remapVecData[18], Queue10_UInt8_2.io.deq.bits connect remapVecValids[18], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[18] node _T_3849 = eq(UInt<2>(0h3), remapindex_18) when _T_3849 : connect remapVecData[18], Queue10_UInt8_3.io.deq.bits connect remapVecValids[18], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[18] node _T_3850 = eq(UInt<3>(0h4), remapindex_18) when _T_3850 : connect remapVecData[18], Queue10_UInt8_4.io.deq.bits connect remapVecValids[18], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[18] node _T_3851 = eq(UInt<3>(0h5), remapindex_18) when _T_3851 : connect remapVecData[18], Queue10_UInt8_5.io.deq.bits connect remapVecValids[18], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[18] node _T_3852 = eq(UInt<3>(0h6), remapindex_18) when _T_3852 : connect remapVecData[18], Queue10_UInt8_6.io.deq.bits connect remapVecValids[18], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[18] node _T_3853 = eq(UInt<3>(0h7), remapindex_18) when _T_3853 : connect remapVecData[18], Queue10_UInt8_7.io.deq.bits connect remapVecValids[18], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[18] node _T_3854 = eq(UInt<4>(0h8), remapindex_18) when _T_3854 : connect remapVecData[18], Queue10_UInt8_8.io.deq.bits connect remapVecValids[18], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[18] node _T_3855 = eq(UInt<4>(0h9), remapindex_18) when _T_3855 : connect remapVecData[18], Queue10_UInt8_9.io.deq.bits connect remapVecValids[18], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[18] node _T_3856 = eq(UInt<4>(0ha), remapindex_18) when _T_3856 : connect remapVecData[18], Queue10_UInt8_10.io.deq.bits connect remapVecValids[18], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[18] node _T_3857 = eq(UInt<4>(0hb), remapindex_18) when _T_3857 : connect remapVecData[18], Queue10_UInt8_11.io.deq.bits connect remapVecValids[18], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[18] node _T_3858 = eq(UInt<4>(0hc), remapindex_18) when _T_3858 : connect remapVecData[18], Queue10_UInt8_12.io.deq.bits connect remapVecValids[18], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[18] node _T_3859 = eq(UInt<4>(0hd), remapindex_18) when _T_3859 : connect remapVecData[18], Queue10_UInt8_13.io.deq.bits connect remapVecValids[18], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[18] node _T_3860 = eq(UInt<4>(0he), remapindex_18) when _T_3860 : connect remapVecData[18], Queue10_UInt8_14.io.deq.bits connect remapVecValids[18], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[18] node _T_3861 = eq(UInt<4>(0hf), remapindex_18) when _T_3861 : connect remapVecData[18], Queue10_UInt8_15.io.deq.bits connect remapVecValids[18], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[18] node _T_3862 = eq(UInt<5>(0h10), remapindex_18) when _T_3862 : connect remapVecData[18], Queue10_UInt8_16.io.deq.bits connect remapVecValids[18], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[18] node _T_3863 = eq(UInt<5>(0h11), remapindex_18) when _T_3863 : connect remapVecData[18], Queue10_UInt8_17.io.deq.bits connect remapVecValids[18], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[18] node _T_3864 = eq(UInt<5>(0h12), remapindex_18) when _T_3864 : connect remapVecData[18], Queue10_UInt8_18.io.deq.bits connect remapVecValids[18], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[18] node _T_3865 = eq(UInt<5>(0h13), remapindex_18) when _T_3865 : connect remapVecData[18], Queue10_UInt8_19.io.deq.bits connect remapVecValids[18], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[18] node _T_3866 = eq(UInt<5>(0h14), remapindex_18) when _T_3866 : connect remapVecData[18], Queue10_UInt8_20.io.deq.bits connect remapVecValids[18], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[18] node _T_3867 = eq(UInt<5>(0h15), remapindex_18) when _T_3867 : connect remapVecData[18], Queue10_UInt8_21.io.deq.bits connect remapVecValids[18], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[18] node _T_3868 = eq(UInt<5>(0h16), remapindex_18) when _T_3868 : connect remapVecData[18], Queue10_UInt8_22.io.deq.bits connect remapVecValids[18], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[18] node _T_3869 = eq(UInt<5>(0h17), remapindex_18) when _T_3869 : connect remapVecData[18], Queue10_UInt8_23.io.deq.bits connect remapVecValids[18], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[18] node _T_3870 = eq(UInt<5>(0h18), remapindex_18) when _T_3870 : connect remapVecData[18], Queue10_UInt8_24.io.deq.bits connect remapVecValids[18], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[18] node _T_3871 = eq(UInt<5>(0h19), remapindex_18) when _T_3871 : connect remapVecData[18], Queue10_UInt8_25.io.deq.bits connect remapVecValids[18], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[18] node _T_3872 = eq(UInt<5>(0h1a), remapindex_18) when _T_3872 : connect remapVecData[18], Queue10_UInt8_26.io.deq.bits connect remapVecValids[18], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[18] node _T_3873 = eq(UInt<5>(0h1b), remapindex_18) when _T_3873 : connect remapVecData[18], Queue10_UInt8_27.io.deq.bits connect remapVecValids[18], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[18] node _T_3874 = eq(UInt<5>(0h1c), remapindex_18) when _T_3874 : connect remapVecData[18], Queue10_UInt8_28.io.deq.bits connect remapVecValids[18], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[18] node _T_3875 = eq(UInt<5>(0h1d), remapindex_18) when _T_3875 : connect remapVecData[18], Queue10_UInt8_29.io.deq.bits connect remapVecValids[18], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[18] node _T_3876 = eq(UInt<5>(0h1e), remapindex_18) when _T_3876 : connect remapVecData[18], Queue10_UInt8_30.io.deq.bits connect remapVecValids[18], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[18] node _T_3877 = eq(UInt<5>(0h1f), remapindex_18) when _T_3877 : connect remapVecData[18], Queue10_UInt8_31.io.deq.bits connect remapVecValids[18], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[18] node _remapindex_T_19 = add(UInt<5>(0h13), read_start_index) node remapindex_19 = rem(_remapindex_T_19, UInt<6>(0h20)) node _T_3878 = eq(UInt<1>(0h0), remapindex_19) when _T_3878 : connect remapVecData[19], Queue10_UInt8.io.deq.bits connect remapVecValids[19], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[19] node _T_3879 = eq(UInt<1>(0h1), remapindex_19) when _T_3879 : connect remapVecData[19], Queue10_UInt8_1.io.deq.bits connect remapVecValids[19], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[19] node _T_3880 = eq(UInt<2>(0h2), remapindex_19) when _T_3880 : connect remapVecData[19], Queue10_UInt8_2.io.deq.bits connect remapVecValids[19], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[19] node _T_3881 = eq(UInt<2>(0h3), remapindex_19) when _T_3881 : connect remapVecData[19], Queue10_UInt8_3.io.deq.bits connect remapVecValids[19], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[19] node _T_3882 = eq(UInt<3>(0h4), remapindex_19) when _T_3882 : connect remapVecData[19], Queue10_UInt8_4.io.deq.bits connect remapVecValids[19], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[19] node _T_3883 = eq(UInt<3>(0h5), remapindex_19) when _T_3883 : connect remapVecData[19], Queue10_UInt8_5.io.deq.bits connect remapVecValids[19], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[19] node _T_3884 = eq(UInt<3>(0h6), remapindex_19) when _T_3884 : connect remapVecData[19], Queue10_UInt8_6.io.deq.bits connect remapVecValids[19], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[19] node _T_3885 = eq(UInt<3>(0h7), remapindex_19) when _T_3885 : connect remapVecData[19], Queue10_UInt8_7.io.deq.bits connect remapVecValids[19], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[19] node _T_3886 = eq(UInt<4>(0h8), remapindex_19) when _T_3886 : connect remapVecData[19], Queue10_UInt8_8.io.deq.bits connect remapVecValids[19], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[19] node _T_3887 = eq(UInt<4>(0h9), remapindex_19) when _T_3887 : connect remapVecData[19], Queue10_UInt8_9.io.deq.bits connect remapVecValids[19], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[19] node _T_3888 = eq(UInt<4>(0ha), remapindex_19) when _T_3888 : connect remapVecData[19], Queue10_UInt8_10.io.deq.bits connect remapVecValids[19], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[19] node _T_3889 = eq(UInt<4>(0hb), remapindex_19) when _T_3889 : connect remapVecData[19], Queue10_UInt8_11.io.deq.bits connect remapVecValids[19], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[19] node _T_3890 = eq(UInt<4>(0hc), remapindex_19) when _T_3890 : connect remapVecData[19], Queue10_UInt8_12.io.deq.bits connect remapVecValids[19], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[19] node _T_3891 = eq(UInt<4>(0hd), remapindex_19) when _T_3891 : connect remapVecData[19], Queue10_UInt8_13.io.deq.bits connect remapVecValids[19], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[19] node _T_3892 = eq(UInt<4>(0he), remapindex_19) when _T_3892 : connect remapVecData[19], Queue10_UInt8_14.io.deq.bits connect remapVecValids[19], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[19] node _T_3893 = eq(UInt<4>(0hf), remapindex_19) when _T_3893 : connect remapVecData[19], Queue10_UInt8_15.io.deq.bits connect remapVecValids[19], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[19] node _T_3894 = eq(UInt<5>(0h10), remapindex_19) when _T_3894 : connect remapVecData[19], Queue10_UInt8_16.io.deq.bits connect remapVecValids[19], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[19] node _T_3895 = eq(UInt<5>(0h11), remapindex_19) when _T_3895 : connect remapVecData[19], Queue10_UInt8_17.io.deq.bits connect remapVecValids[19], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[19] node _T_3896 = eq(UInt<5>(0h12), remapindex_19) when _T_3896 : connect remapVecData[19], Queue10_UInt8_18.io.deq.bits connect remapVecValids[19], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[19] node _T_3897 = eq(UInt<5>(0h13), remapindex_19) when _T_3897 : connect remapVecData[19], Queue10_UInt8_19.io.deq.bits connect remapVecValids[19], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[19] node _T_3898 = eq(UInt<5>(0h14), remapindex_19) when _T_3898 : connect remapVecData[19], Queue10_UInt8_20.io.deq.bits connect remapVecValids[19], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[19] node _T_3899 = eq(UInt<5>(0h15), remapindex_19) when _T_3899 : connect remapVecData[19], Queue10_UInt8_21.io.deq.bits connect remapVecValids[19], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[19] node _T_3900 = eq(UInt<5>(0h16), remapindex_19) when _T_3900 : connect remapVecData[19], Queue10_UInt8_22.io.deq.bits connect remapVecValids[19], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[19] node _T_3901 = eq(UInt<5>(0h17), remapindex_19) when _T_3901 : connect remapVecData[19], Queue10_UInt8_23.io.deq.bits connect remapVecValids[19], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[19] node _T_3902 = eq(UInt<5>(0h18), remapindex_19) when _T_3902 : connect remapVecData[19], Queue10_UInt8_24.io.deq.bits connect remapVecValids[19], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[19] node _T_3903 = eq(UInt<5>(0h19), remapindex_19) when _T_3903 : connect remapVecData[19], Queue10_UInt8_25.io.deq.bits connect remapVecValids[19], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[19] node _T_3904 = eq(UInt<5>(0h1a), remapindex_19) when _T_3904 : connect remapVecData[19], Queue10_UInt8_26.io.deq.bits connect remapVecValids[19], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[19] node _T_3905 = eq(UInt<5>(0h1b), remapindex_19) when _T_3905 : connect remapVecData[19], Queue10_UInt8_27.io.deq.bits connect remapVecValids[19], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[19] node _T_3906 = eq(UInt<5>(0h1c), remapindex_19) when _T_3906 : connect remapVecData[19], Queue10_UInt8_28.io.deq.bits connect remapVecValids[19], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[19] node _T_3907 = eq(UInt<5>(0h1d), remapindex_19) when _T_3907 : connect remapVecData[19], Queue10_UInt8_29.io.deq.bits connect remapVecValids[19], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[19] node _T_3908 = eq(UInt<5>(0h1e), remapindex_19) when _T_3908 : connect remapVecData[19], Queue10_UInt8_30.io.deq.bits connect remapVecValids[19], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[19] node _T_3909 = eq(UInt<5>(0h1f), remapindex_19) when _T_3909 : connect remapVecData[19], Queue10_UInt8_31.io.deq.bits connect remapVecValids[19], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[19] node _remapindex_T_20 = add(UInt<5>(0h14), read_start_index) node remapindex_20 = rem(_remapindex_T_20, UInt<6>(0h20)) node _T_3910 = eq(UInt<1>(0h0), remapindex_20) when _T_3910 : connect remapVecData[20], Queue10_UInt8.io.deq.bits connect remapVecValids[20], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[20] node _T_3911 = eq(UInt<1>(0h1), remapindex_20) when _T_3911 : connect remapVecData[20], Queue10_UInt8_1.io.deq.bits connect remapVecValids[20], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[20] node _T_3912 = eq(UInt<2>(0h2), remapindex_20) when _T_3912 : connect remapVecData[20], Queue10_UInt8_2.io.deq.bits connect remapVecValids[20], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[20] node _T_3913 = eq(UInt<2>(0h3), remapindex_20) when _T_3913 : connect remapVecData[20], Queue10_UInt8_3.io.deq.bits connect remapVecValids[20], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[20] node _T_3914 = eq(UInt<3>(0h4), remapindex_20) when _T_3914 : connect remapVecData[20], Queue10_UInt8_4.io.deq.bits connect remapVecValids[20], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[20] node _T_3915 = eq(UInt<3>(0h5), remapindex_20) when _T_3915 : connect remapVecData[20], Queue10_UInt8_5.io.deq.bits connect remapVecValids[20], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[20] node _T_3916 = eq(UInt<3>(0h6), remapindex_20) when _T_3916 : connect remapVecData[20], Queue10_UInt8_6.io.deq.bits connect remapVecValids[20], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[20] node _T_3917 = eq(UInt<3>(0h7), remapindex_20) when _T_3917 : connect remapVecData[20], Queue10_UInt8_7.io.deq.bits connect remapVecValids[20], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[20] node _T_3918 = eq(UInt<4>(0h8), remapindex_20) when _T_3918 : connect remapVecData[20], Queue10_UInt8_8.io.deq.bits connect remapVecValids[20], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[20] node _T_3919 = eq(UInt<4>(0h9), remapindex_20) when _T_3919 : connect remapVecData[20], Queue10_UInt8_9.io.deq.bits connect remapVecValids[20], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[20] node _T_3920 = eq(UInt<4>(0ha), remapindex_20) when _T_3920 : connect remapVecData[20], Queue10_UInt8_10.io.deq.bits connect remapVecValids[20], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[20] node _T_3921 = eq(UInt<4>(0hb), remapindex_20) when _T_3921 : connect remapVecData[20], Queue10_UInt8_11.io.deq.bits connect remapVecValids[20], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[20] node _T_3922 = eq(UInt<4>(0hc), remapindex_20) when _T_3922 : connect remapVecData[20], Queue10_UInt8_12.io.deq.bits connect remapVecValids[20], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[20] node _T_3923 = eq(UInt<4>(0hd), remapindex_20) when _T_3923 : connect remapVecData[20], Queue10_UInt8_13.io.deq.bits connect remapVecValids[20], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[20] node _T_3924 = eq(UInt<4>(0he), remapindex_20) when _T_3924 : connect remapVecData[20], Queue10_UInt8_14.io.deq.bits connect remapVecValids[20], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[20] node _T_3925 = eq(UInt<4>(0hf), remapindex_20) when _T_3925 : connect remapVecData[20], Queue10_UInt8_15.io.deq.bits connect remapVecValids[20], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[20] node _T_3926 = eq(UInt<5>(0h10), remapindex_20) when _T_3926 : connect remapVecData[20], Queue10_UInt8_16.io.deq.bits connect remapVecValids[20], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[20] node _T_3927 = eq(UInt<5>(0h11), remapindex_20) when _T_3927 : connect remapVecData[20], Queue10_UInt8_17.io.deq.bits connect remapVecValids[20], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[20] node _T_3928 = eq(UInt<5>(0h12), remapindex_20) when _T_3928 : connect remapVecData[20], Queue10_UInt8_18.io.deq.bits connect remapVecValids[20], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[20] node _T_3929 = eq(UInt<5>(0h13), remapindex_20) when _T_3929 : connect remapVecData[20], Queue10_UInt8_19.io.deq.bits connect remapVecValids[20], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[20] node _T_3930 = eq(UInt<5>(0h14), remapindex_20) when _T_3930 : connect remapVecData[20], Queue10_UInt8_20.io.deq.bits connect remapVecValids[20], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[20] node _T_3931 = eq(UInt<5>(0h15), remapindex_20) when _T_3931 : connect remapVecData[20], Queue10_UInt8_21.io.deq.bits connect remapVecValids[20], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[20] node _T_3932 = eq(UInt<5>(0h16), remapindex_20) when _T_3932 : connect remapVecData[20], Queue10_UInt8_22.io.deq.bits connect remapVecValids[20], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[20] node _T_3933 = eq(UInt<5>(0h17), remapindex_20) when _T_3933 : connect remapVecData[20], Queue10_UInt8_23.io.deq.bits connect remapVecValids[20], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[20] node _T_3934 = eq(UInt<5>(0h18), remapindex_20) when _T_3934 : connect remapVecData[20], Queue10_UInt8_24.io.deq.bits connect remapVecValids[20], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[20] node _T_3935 = eq(UInt<5>(0h19), remapindex_20) when _T_3935 : connect remapVecData[20], Queue10_UInt8_25.io.deq.bits connect remapVecValids[20], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[20] node _T_3936 = eq(UInt<5>(0h1a), remapindex_20) when _T_3936 : connect remapVecData[20], Queue10_UInt8_26.io.deq.bits connect remapVecValids[20], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[20] node _T_3937 = eq(UInt<5>(0h1b), remapindex_20) when _T_3937 : connect remapVecData[20], Queue10_UInt8_27.io.deq.bits connect remapVecValids[20], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[20] node _T_3938 = eq(UInt<5>(0h1c), remapindex_20) when _T_3938 : connect remapVecData[20], Queue10_UInt8_28.io.deq.bits connect remapVecValids[20], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[20] node _T_3939 = eq(UInt<5>(0h1d), remapindex_20) when _T_3939 : connect remapVecData[20], Queue10_UInt8_29.io.deq.bits connect remapVecValids[20], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[20] node _T_3940 = eq(UInt<5>(0h1e), remapindex_20) when _T_3940 : connect remapVecData[20], Queue10_UInt8_30.io.deq.bits connect remapVecValids[20], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[20] node _T_3941 = eq(UInt<5>(0h1f), remapindex_20) when _T_3941 : connect remapVecData[20], Queue10_UInt8_31.io.deq.bits connect remapVecValids[20], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[20] node _remapindex_T_21 = add(UInt<5>(0h15), read_start_index) node remapindex_21 = rem(_remapindex_T_21, UInt<6>(0h20)) node _T_3942 = eq(UInt<1>(0h0), remapindex_21) when _T_3942 : connect remapVecData[21], Queue10_UInt8.io.deq.bits connect remapVecValids[21], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[21] node _T_3943 = eq(UInt<1>(0h1), remapindex_21) when _T_3943 : connect remapVecData[21], Queue10_UInt8_1.io.deq.bits connect remapVecValids[21], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[21] node _T_3944 = eq(UInt<2>(0h2), remapindex_21) when _T_3944 : connect remapVecData[21], Queue10_UInt8_2.io.deq.bits connect remapVecValids[21], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[21] node _T_3945 = eq(UInt<2>(0h3), remapindex_21) when _T_3945 : connect remapVecData[21], Queue10_UInt8_3.io.deq.bits connect remapVecValids[21], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[21] node _T_3946 = eq(UInt<3>(0h4), remapindex_21) when _T_3946 : connect remapVecData[21], Queue10_UInt8_4.io.deq.bits connect remapVecValids[21], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[21] node _T_3947 = eq(UInt<3>(0h5), remapindex_21) when _T_3947 : connect remapVecData[21], Queue10_UInt8_5.io.deq.bits connect remapVecValids[21], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[21] node _T_3948 = eq(UInt<3>(0h6), remapindex_21) when _T_3948 : connect remapVecData[21], Queue10_UInt8_6.io.deq.bits connect remapVecValids[21], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[21] node _T_3949 = eq(UInt<3>(0h7), remapindex_21) when _T_3949 : connect remapVecData[21], Queue10_UInt8_7.io.deq.bits connect remapVecValids[21], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[21] node _T_3950 = eq(UInt<4>(0h8), remapindex_21) when _T_3950 : connect remapVecData[21], Queue10_UInt8_8.io.deq.bits connect remapVecValids[21], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[21] node _T_3951 = eq(UInt<4>(0h9), remapindex_21) when _T_3951 : connect remapVecData[21], Queue10_UInt8_9.io.deq.bits connect remapVecValids[21], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[21] node _T_3952 = eq(UInt<4>(0ha), remapindex_21) when _T_3952 : connect remapVecData[21], Queue10_UInt8_10.io.deq.bits connect remapVecValids[21], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[21] node _T_3953 = eq(UInt<4>(0hb), remapindex_21) when _T_3953 : connect remapVecData[21], Queue10_UInt8_11.io.deq.bits connect remapVecValids[21], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[21] node _T_3954 = eq(UInt<4>(0hc), remapindex_21) when _T_3954 : connect remapVecData[21], Queue10_UInt8_12.io.deq.bits connect remapVecValids[21], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[21] node _T_3955 = eq(UInt<4>(0hd), remapindex_21) when _T_3955 : connect remapVecData[21], Queue10_UInt8_13.io.deq.bits connect remapVecValids[21], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[21] node _T_3956 = eq(UInt<4>(0he), remapindex_21) when _T_3956 : connect remapVecData[21], Queue10_UInt8_14.io.deq.bits connect remapVecValids[21], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[21] node _T_3957 = eq(UInt<4>(0hf), remapindex_21) when _T_3957 : connect remapVecData[21], Queue10_UInt8_15.io.deq.bits connect remapVecValids[21], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[21] node _T_3958 = eq(UInt<5>(0h10), remapindex_21) when _T_3958 : connect remapVecData[21], Queue10_UInt8_16.io.deq.bits connect remapVecValids[21], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[21] node _T_3959 = eq(UInt<5>(0h11), remapindex_21) when _T_3959 : connect remapVecData[21], Queue10_UInt8_17.io.deq.bits connect remapVecValids[21], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[21] node _T_3960 = eq(UInt<5>(0h12), remapindex_21) when _T_3960 : connect remapVecData[21], Queue10_UInt8_18.io.deq.bits connect remapVecValids[21], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[21] node _T_3961 = eq(UInt<5>(0h13), remapindex_21) when _T_3961 : connect remapVecData[21], Queue10_UInt8_19.io.deq.bits connect remapVecValids[21], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[21] node _T_3962 = eq(UInt<5>(0h14), remapindex_21) when _T_3962 : connect remapVecData[21], Queue10_UInt8_20.io.deq.bits connect remapVecValids[21], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[21] node _T_3963 = eq(UInt<5>(0h15), remapindex_21) when _T_3963 : connect remapVecData[21], Queue10_UInt8_21.io.deq.bits connect remapVecValids[21], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[21] node _T_3964 = eq(UInt<5>(0h16), remapindex_21) when _T_3964 : connect remapVecData[21], Queue10_UInt8_22.io.deq.bits connect remapVecValids[21], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[21] node _T_3965 = eq(UInt<5>(0h17), remapindex_21) when _T_3965 : connect remapVecData[21], Queue10_UInt8_23.io.deq.bits connect remapVecValids[21], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[21] node _T_3966 = eq(UInt<5>(0h18), remapindex_21) when _T_3966 : connect remapVecData[21], Queue10_UInt8_24.io.deq.bits connect remapVecValids[21], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[21] node _T_3967 = eq(UInt<5>(0h19), remapindex_21) when _T_3967 : connect remapVecData[21], Queue10_UInt8_25.io.deq.bits connect remapVecValids[21], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[21] node _T_3968 = eq(UInt<5>(0h1a), remapindex_21) when _T_3968 : connect remapVecData[21], Queue10_UInt8_26.io.deq.bits connect remapVecValids[21], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[21] node _T_3969 = eq(UInt<5>(0h1b), remapindex_21) when _T_3969 : connect remapVecData[21], Queue10_UInt8_27.io.deq.bits connect remapVecValids[21], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[21] node _T_3970 = eq(UInt<5>(0h1c), remapindex_21) when _T_3970 : connect remapVecData[21], Queue10_UInt8_28.io.deq.bits connect remapVecValids[21], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[21] node _T_3971 = eq(UInt<5>(0h1d), remapindex_21) when _T_3971 : connect remapVecData[21], Queue10_UInt8_29.io.deq.bits connect remapVecValids[21], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[21] node _T_3972 = eq(UInt<5>(0h1e), remapindex_21) when _T_3972 : connect remapVecData[21], Queue10_UInt8_30.io.deq.bits connect remapVecValids[21], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[21] node _T_3973 = eq(UInt<5>(0h1f), remapindex_21) when _T_3973 : connect remapVecData[21], Queue10_UInt8_31.io.deq.bits connect remapVecValids[21], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[21] node _remapindex_T_22 = add(UInt<5>(0h16), read_start_index) node remapindex_22 = rem(_remapindex_T_22, UInt<6>(0h20)) node _T_3974 = eq(UInt<1>(0h0), remapindex_22) when _T_3974 : connect remapVecData[22], Queue10_UInt8.io.deq.bits connect remapVecValids[22], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[22] node _T_3975 = eq(UInt<1>(0h1), remapindex_22) when _T_3975 : connect remapVecData[22], Queue10_UInt8_1.io.deq.bits connect remapVecValids[22], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[22] node _T_3976 = eq(UInt<2>(0h2), remapindex_22) when _T_3976 : connect remapVecData[22], Queue10_UInt8_2.io.deq.bits connect remapVecValids[22], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[22] node _T_3977 = eq(UInt<2>(0h3), remapindex_22) when _T_3977 : connect remapVecData[22], Queue10_UInt8_3.io.deq.bits connect remapVecValids[22], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[22] node _T_3978 = eq(UInt<3>(0h4), remapindex_22) when _T_3978 : connect remapVecData[22], Queue10_UInt8_4.io.deq.bits connect remapVecValids[22], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[22] node _T_3979 = eq(UInt<3>(0h5), remapindex_22) when _T_3979 : connect remapVecData[22], Queue10_UInt8_5.io.deq.bits connect remapVecValids[22], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[22] node _T_3980 = eq(UInt<3>(0h6), remapindex_22) when _T_3980 : connect remapVecData[22], Queue10_UInt8_6.io.deq.bits connect remapVecValids[22], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[22] node _T_3981 = eq(UInt<3>(0h7), remapindex_22) when _T_3981 : connect remapVecData[22], Queue10_UInt8_7.io.deq.bits connect remapVecValids[22], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[22] node _T_3982 = eq(UInt<4>(0h8), remapindex_22) when _T_3982 : connect remapVecData[22], Queue10_UInt8_8.io.deq.bits connect remapVecValids[22], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[22] node _T_3983 = eq(UInt<4>(0h9), remapindex_22) when _T_3983 : connect remapVecData[22], Queue10_UInt8_9.io.deq.bits connect remapVecValids[22], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[22] node _T_3984 = eq(UInt<4>(0ha), remapindex_22) when _T_3984 : connect remapVecData[22], Queue10_UInt8_10.io.deq.bits connect remapVecValids[22], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[22] node _T_3985 = eq(UInt<4>(0hb), remapindex_22) when _T_3985 : connect remapVecData[22], Queue10_UInt8_11.io.deq.bits connect remapVecValids[22], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[22] node _T_3986 = eq(UInt<4>(0hc), remapindex_22) when _T_3986 : connect remapVecData[22], Queue10_UInt8_12.io.deq.bits connect remapVecValids[22], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[22] node _T_3987 = eq(UInt<4>(0hd), remapindex_22) when _T_3987 : connect remapVecData[22], Queue10_UInt8_13.io.deq.bits connect remapVecValids[22], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[22] node _T_3988 = eq(UInt<4>(0he), remapindex_22) when _T_3988 : connect remapVecData[22], Queue10_UInt8_14.io.deq.bits connect remapVecValids[22], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[22] node _T_3989 = eq(UInt<4>(0hf), remapindex_22) when _T_3989 : connect remapVecData[22], Queue10_UInt8_15.io.deq.bits connect remapVecValids[22], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[22] node _T_3990 = eq(UInt<5>(0h10), remapindex_22) when _T_3990 : connect remapVecData[22], Queue10_UInt8_16.io.deq.bits connect remapVecValids[22], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[22] node _T_3991 = eq(UInt<5>(0h11), remapindex_22) when _T_3991 : connect remapVecData[22], Queue10_UInt8_17.io.deq.bits connect remapVecValids[22], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[22] node _T_3992 = eq(UInt<5>(0h12), remapindex_22) when _T_3992 : connect remapVecData[22], Queue10_UInt8_18.io.deq.bits connect remapVecValids[22], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[22] node _T_3993 = eq(UInt<5>(0h13), remapindex_22) when _T_3993 : connect remapVecData[22], Queue10_UInt8_19.io.deq.bits connect remapVecValids[22], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[22] node _T_3994 = eq(UInt<5>(0h14), remapindex_22) when _T_3994 : connect remapVecData[22], Queue10_UInt8_20.io.deq.bits connect remapVecValids[22], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[22] node _T_3995 = eq(UInt<5>(0h15), remapindex_22) when _T_3995 : connect remapVecData[22], Queue10_UInt8_21.io.deq.bits connect remapVecValids[22], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[22] node _T_3996 = eq(UInt<5>(0h16), remapindex_22) when _T_3996 : connect remapVecData[22], Queue10_UInt8_22.io.deq.bits connect remapVecValids[22], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[22] node _T_3997 = eq(UInt<5>(0h17), remapindex_22) when _T_3997 : connect remapVecData[22], Queue10_UInt8_23.io.deq.bits connect remapVecValids[22], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[22] node _T_3998 = eq(UInt<5>(0h18), remapindex_22) when _T_3998 : connect remapVecData[22], Queue10_UInt8_24.io.deq.bits connect remapVecValids[22], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[22] node _T_3999 = eq(UInt<5>(0h19), remapindex_22) when _T_3999 : connect remapVecData[22], Queue10_UInt8_25.io.deq.bits connect remapVecValids[22], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[22] node _T_4000 = eq(UInt<5>(0h1a), remapindex_22) when _T_4000 : connect remapVecData[22], Queue10_UInt8_26.io.deq.bits connect remapVecValids[22], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[22] node _T_4001 = eq(UInt<5>(0h1b), remapindex_22) when _T_4001 : connect remapVecData[22], Queue10_UInt8_27.io.deq.bits connect remapVecValids[22], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[22] node _T_4002 = eq(UInt<5>(0h1c), remapindex_22) when _T_4002 : connect remapVecData[22], Queue10_UInt8_28.io.deq.bits connect remapVecValids[22], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[22] node _T_4003 = eq(UInt<5>(0h1d), remapindex_22) when _T_4003 : connect remapVecData[22], Queue10_UInt8_29.io.deq.bits connect remapVecValids[22], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[22] node _T_4004 = eq(UInt<5>(0h1e), remapindex_22) when _T_4004 : connect remapVecData[22], Queue10_UInt8_30.io.deq.bits connect remapVecValids[22], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[22] node _T_4005 = eq(UInt<5>(0h1f), remapindex_22) when _T_4005 : connect remapVecData[22], Queue10_UInt8_31.io.deq.bits connect remapVecValids[22], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[22] node _remapindex_T_23 = add(UInt<5>(0h17), read_start_index) node remapindex_23 = rem(_remapindex_T_23, UInt<6>(0h20)) node _T_4006 = eq(UInt<1>(0h0), remapindex_23) when _T_4006 : connect remapVecData[23], Queue10_UInt8.io.deq.bits connect remapVecValids[23], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[23] node _T_4007 = eq(UInt<1>(0h1), remapindex_23) when _T_4007 : connect remapVecData[23], Queue10_UInt8_1.io.deq.bits connect remapVecValids[23], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[23] node _T_4008 = eq(UInt<2>(0h2), remapindex_23) when _T_4008 : connect remapVecData[23], Queue10_UInt8_2.io.deq.bits connect remapVecValids[23], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[23] node _T_4009 = eq(UInt<2>(0h3), remapindex_23) when _T_4009 : connect remapVecData[23], Queue10_UInt8_3.io.deq.bits connect remapVecValids[23], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[23] node _T_4010 = eq(UInt<3>(0h4), remapindex_23) when _T_4010 : connect remapVecData[23], Queue10_UInt8_4.io.deq.bits connect remapVecValids[23], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[23] node _T_4011 = eq(UInt<3>(0h5), remapindex_23) when _T_4011 : connect remapVecData[23], Queue10_UInt8_5.io.deq.bits connect remapVecValids[23], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[23] node _T_4012 = eq(UInt<3>(0h6), remapindex_23) when _T_4012 : connect remapVecData[23], Queue10_UInt8_6.io.deq.bits connect remapVecValids[23], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[23] node _T_4013 = eq(UInt<3>(0h7), remapindex_23) when _T_4013 : connect remapVecData[23], Queue10_UInt8_7.io.deq.bits connect remapVecValids[23], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[23] node _T_4014 = eq(UInt<4>(0h8), remapindex_23) when _T_4014 : connect remapVecData[23], Queue10_UInt8_8.io.deq.bits connect remapVecValids[23], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[23] node _T_4015 = eq(UInt<4>(0h9), remapindex_23) when _T_4015 : connect remapVecData[23], Queue10_UInt8_9.io.deq.bits connect remapVecValids[23], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[23] node _T_4016 = eq(UInt<4>(0ha), remapindex_23) when _T_4016 : connect remapVecData[23], Queue10_UInt8_10.io.deq.bits connect remapVecValids[23], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[23] node _T_4017 = eq(UInt<4>(0hb), remapindex_23) when _T_4017 : connect remapVecData[23], Queue10_UInt8_11.io.deq.bits connect remapVecValids[23], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[23] node _T_4018 = eq(UInt<4>(0hc), remapindex_23) when _T_4018 : connect remapVecData[23], Queue10_UInt8_12.io.deq.bits connect remapVecValids[23], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[23] node _T_4019 = eq(UInt<4>(0hd), remapindex_23) when _T_4019 : connect remapVecData[23], Queue10_UInt8_13.io.deq.bits connect remapVecValids[23], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[23] node _T_4020 = eq(UInt<4>(0he), remapindex_23) when _T_4020 : connect remapVecData[23], Queue10_UInt8_14.io.deq.bits connect remapVecValids[23], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[23] node _T_4021 = eq(UInt<4>(0hf), remapindex_23) when _T_4021 : connect remapVecData[23], Queue10_UInt8_15.io.deq.bits connect remapVecValids[23], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[23] node _T_4022 = eq(UInt<5>(0h10), remapindex_23) when _T_4022 : connect remapVecData[23], Queue10_UInt8_16.io.deq.bits connect remapVecValids[23], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[23] node _T_4023 = eq(UInt<5>(0h11), remapindex_23) when _T_4023 : connect remapVecData[23], Queue10_UInt8_17.io.deq.bits connect remapVecValids[23], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[23] node _T_4024 = eq(UInt<5>(0h12), remapindex_23) when _T_4024 : connect remapVecData[23], Queue10_UInt8_18.io.deq.bits connect remapVecValids[23], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[23] node _T_4025 = eq(UInt<5>(0h13), remapindex_23) when _T_4025 : connect remapVecData[23], Queue10_UInt8_19.io.deq.bits connect remapVecValids[23], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[23] node _T_4026 = eq(UInt<5>(0h14), remapindex_23) when _T_4026 : connect remapVecData[23], Queue10_UInt8_20.io.deq.bits connect remapVecValids[23], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[23] node _T_4027 = eq(UInt<5>(0h15), remapindex_23) when _T_4027 : connect remapVecData[23], Queue10_UInt8_21.io.deq.bits connect remapVecValids[23], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[23] node _T_4028 = eq(UInt<5>(0h16), remapindex_23) when _T_4028 : connect remapVecData[23], Queue10_UInt8_22.io.deq.bits connect remapVecValids[23], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[23] node _T_4029 = eq(UInt<5>(0h17), remapindex_23) when _T_4029 : connect remapVecData[23], Queue10_UInt8_23.io.deq.bits connect remapVecValids[23], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[23] node _T_4030 = eq(UInt<5>(0h18), remapindex_23) when _T_4030 : connect remapVecData[23], Queue10_UInt8_24.io.deq.bits connect remapVecValids[23], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[23] node _T_4031 = eq(UInt<5>(0h19), remapindex_23) when _T_4031 : connect remapVecData[23], Queue10_UInt8_25.io.deq.bits connect remapVecValids[23], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[23] node _T_4032 = eq(UInt<5>(0h1a), remapindex_23) when _T_4032 : connect remapVecData[23], Queue10_UInt8_26.io.deq.bits connect remapVecValids[23], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[23] node _T_4033 = eq(UInt<5>(0h1b), remapindex_23) when _T_4033 : connect remapVecData[23], Queue10_UInt8_27.io.deq.bits connect remapVecValids[23], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[23] node _T_4034 = eq(UInt<5>(0h1c), remapindex_23) when _T_4034 : connect remapVecData[23], Queue10_UInt8_28.io.deq.bits connect remapVecValids[23], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[23] node _T_4035 = eq(UInt<5>(0h1d), remapindex_23) when _T_4035 : connect remapVecData[23], Queue10_UInt8_29.io.deq.bits connect remapVecValids[23], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[23] node _T_4036 = eq(UInt<5>(0h1e), remapindex_23) when _T_4036 : connect remapVecData[23], Queue10_UInt8_30.io.deq.bits connect remapVecValids[23], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[23] node _T_4037 = eq(UInt<5>(0h1f), remapindex_23) when _T_4037 : connect remapVecData[23], Queue10_UInt8_31.io.deq.bits connect remapVecValids[23], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[23] node _remapindex_T_24 = add(UInt<5>(0h18), read_start_index) node remapindex_24 = rem(_remapindex_T_24, UInt<6>(0h20)) node _T_4038 = eq(UInt<1>(0h0), remapindex_24) when _T_4038 : connect remapVecData[24], Queue10_UInt8.io.deq.bits connect remapVecValids[24], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[24] node _T_4039 = eq(UInt<1>(0h1), remapindex_24) when _T_4039 : connect remapVecData[24], Queue10_UInt8_1.io.deq.bits connect remapVecValids[24], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[24] node _T_4040 = eq(UInt<2>(0h2), remapindex_24) when _T_4040 : connect remapVecData[24], Queue10_UInt8_2.io.deq.bits connect remapVecValids[24], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[24] node _T_4041 = eq(UInt<2>(0h3), remapindex_24) when _T_4041 : connect remapVecData[24], Queue10_UInt8_3.io.deq.bits connect remapVecValids[24], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[24] node _T_4042 = eq(UInt<3>(0h4), remapindex_24) when _T_4042 : connect remapVecData[24], Queue10_UInt8_4.io.deq.bits connect remapVecValids[24], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[24] node _T_4043 = eq(UInt<3>(0h5), remapindex_24) when _T_4043 : connect remapVecData[24], Queue10_UInt8_5.io.deq.bits connect remapVecValids[24], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[24] node _T_4044 = eq(UInt<3>(0h6), remapindex_24) when _T_4044 : connect remapVecData[24], Queue10_UInt8_6.io.deq.bits connect remapVecValids[24], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[24] node _T_4045 = eq(UInt<3>(0h7), remapindex_24) when _T_4045 : connect remapVecData[24], Queue10_UInt8_7.io.deq.bits connect remapVecValids[24], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[24] node _T_4046 = eq(UInt<4>(0h8), remapindex_24) when _T_4046 : connect remapVecData[24], Queue10_UInt8_8.io.deq.bits connect remapVecValids[24], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[24] node _T_4047 = eq(UInt<4>(0h9), remapindex_24) when _T_4047 : connect remapVecData[24], Queue10_UInt8_9.io.deq.bits connect remapVecValids[24], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[24] node _T_4048 = eq(UInt<4>(0ha), remapindex_24) when _T_4048 : connect remapVecData[24], Queue10_UInt8_10.io.deq.bits connect remapVecValids[24], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[24] node _T_4049 = eq(UInt<4>(0hb), remapindex_24) when _T_4049 : connect remapVecData[24], Queue10_UInt8_11.io.deq.bits connect remapVecValids[24], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[24] node _T_4050 = eq(UInt<4>(0hc), remapindex_24) when _T_4050 : connect remapVecData[24], Queue10_UInt8_12.io.deq.bits connect remapVecValids[24], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[24] node _T_4051 = eq(UInt<4>(0hd), remapindex_24) when _T_4051 : connect remapVecData[24], Queue10_UInt8_13.io.deq.bits connect remapVecValids[24], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[24] node _T_4052 = eq(UInt<4>(0he), remapindex_24) when _T_4052 : connect remapVecData[24], Queue10_UInt8_14.io.deq.bits connect remapVecValids[24], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[24] node _T_4053 = eq(UInt<4>(0hf), remapindex_24) when _T_4053 : connect remapVecData[24], Queue10_UInt8_15.io.deq.bits connect remapVecValids[24], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[24] node _T_4054 = eq(UInt<5>(0h10), remapindex_24) when _T_4054 : connect remapVecData[24], Queue10_UInt8_16.io.deq.bits connect remapVecValids[24], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[24] node _T_4055 = eq(UInt<5>(0h11), remapindex_24) when _T_4055 : connect remapVecData[24], Queue10_UInt8_17.io.deq.bits connect remapVecValids[24], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[24] node _T_4056 = eq(UInt<5>(0h12), remapindex_24) when _T_4056 : connect remapVecData[24], Queue10_UInt8_18.io.deq.bits connect remapVecValids[24], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[24] node _T_4057 = eq(UInt<5>(0h13), remapindex_24) when _T_4057 : connect remapVecData[24], Queue10_UInt8_19.io.deq.bits connect remapVecValids[24], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[24] node _T_4058 = eq(UInt<5>(0h14), remapindex_24) when _T_4058 : connect remapVecData[24], Queue10_UInt8_20.io.deq.bits connect remapVecValids[24], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[24] node _T_4059 = eq(UInt<5>(0h15), remapindex_24) when _T_4059 : connect remapVecData[24], Queue10_UInt8_21.io.deq.bits connect remapVecValids[24], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[24] node _T_4060 = eq(UInt<5>(0h16), remapindex_24) when _T_4060 : connect remapVecData[24], Queue10_UInt8_22.io.deq.bits connect remapVecValids[24], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[24] node _T_4061 = eq(UInt<5>(0h17), remapindex_24) when _T_4061 : connect remapVecData[24], Queue10_UInt8_23.io.deq.bits connect remapVecValids[24], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[24] node _T_4062 = eq(UInt<5>(0h18), remapindex_24) when _T_4062 : connect remapVecData[24], Queue10_UInt8_24.io.deq.bits connect remapVecValids[24], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[24] node _T_4063 = eq(UInt<5>(0h19), remapindex_24) when _T_4063 : connect remapVecData[24], Queue10_UInt8_25.io.deq.bits connect remapVecValids[24], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[24] node _T_4064 = eq(UInt<5>(0h1a), remapindex_24) when _T_4064 : connect remapVecData[24], Queue10_UInt8_26.io.deq.bits connect remapVecValids[24], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[24] node _T_4065 = eq(UInt<5>(0h1b), remapindex_24) when _T_4065 : connect remapVecData[24], Queue10_UInt8_27.io.deq.bits connect remapVecValids[24], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[24] node _T_4066 = eq(UInt<5>(0h1c), remapindex_24) when _T_4066 : connect remapVecData[24], Queue10_UInt8_28.io.deq.bits connect remapVecValids[24], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[24] node _T_4067 = eq(UInt<5>(0h1d), remapindex_24) when _T_4067 : connect remapVecData[24], Queue10_UInt8_29.io.deq.bits connect remapVecValids[24], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[24] node _T_4068 = eq(UInt<5>(0h1e), remapindex_24) when _T_4068 : connect remapVecData[24], Queue10_UInt8_30.io.deq.bits connect remapVecValids[24], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[24] node _T_4069 = eq(UInt<5>(0h1f), remapindex_24) when _T_4069 : connect remapVecData[24], Queue10_UInt8_31.io.deq.bits connect remapVecValids[24], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[24] node _remapindex_T_25 = add(UInt<5>(0h19), read_start_index) node remapindex_25 = rem(_remapindex_T_25, UInt<6>(0h20)) node _T_4070 = eq(UInt<1>(0h0), remapindex_25) when _T_4070 : connect remapVecData[25], Queue10_UInt8.io.deq.bits connect remapVecValids[25], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[25] node _T_4071 = eq(UInt<1>(0h1), remapindex_25) when _T_4071 : connect remapVecData[25], Queue10_UInt8_1.io.deq.bits connect remapVecValids[25], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[25] node _T_4072 = eq(UInt<2>(0h2), remapindex_25) when _T_4072 : connect remapVecData[25], Queue10_UInt8_2.io.deq.bits connect remapVecValids[25], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[25] node _T_4073 = eq(UInt<2>(0h3), remapindex_25) when _T_4073 : connect remapVecData[25], Queue10_UInt8_3.io.deq.bits connect remapVecValids[25], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[25] node _T_4074 = eq(UInt<3>(0h4), remapindex_25) when _T_4074 : connect remapVecData[25], Queue10_UInt8_4.io.deq.bits connect remapVecValids[25], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[25] node _T_4075 = eq(UInt<3>(0h5), remapindex_25) when _T_4075 : connect remapVecData[25], Queue10_UInt8_5.io.deq.bits connect remapVecValids[25], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[25] node _T_4076 = eq(UInt<3>(0h6), remapindex_25) when _T_4076 : connect remapVecData[25], Queue10_UInt8_6.io.deq.bits connect remapVecValids[25], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[25] node _T_4077 = eq(UInt<3>(0h7), remapindex_25) when _T_4077 : connect remapVecData[25], Queue10_UInt8_7.io.deq.bits connect remapVecValids[25], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[25] node _T_4078 = eq(UInt<4>(0h8), remapindex_25) when _T_4078 : connect remapVecData[25], Queue10_UInt8_8.io.deq.bits connect remapVecValids[25], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[25] node _T_4079 = eq(UInt<4>(0h9), remapindex_25) when _T_4079 : connect remapVecData[25], Queue10_UInt8_9.io.deq.bits connect remapVecValids[25], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[25] node _T_4080 = eq(UInt<4>(0ha), remapindex_25) when _T_4080 : connect remapVecData[25], Queue10_UInt8_10.io.deq.bits connect remapVecValids[25], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[25] node _T_4081 = eq(UInt<4>(0hb), remapindex_25) when _T_4081 : connect remapVecData[25], Queue10_UInt8_11.io.deq.bits connect remapVecValids[25], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[25] node _T_4082 = eq(UInt<4>(0hc), remapindex_25) when _T_4082 : connect remapVecData[25], Queue10_UInt8_12.io.deq.bits connect remapVecValids[25], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[25] node _T_4083 = eq(UInt<4>(0hd), remapindex_25) when _T_4083 : connect remapVecData[25], Queue10_UInt8_13.io.deq.bits connect remapVecValids[25], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[25] node _T_4084 = eq(UInt<4>(0he), remapindex_25) when _T_4084 : connect remapVecData[25], Queue10_UInt8_14.io.deq.bits connect remapVecValids[25], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[25] node _T_4085 = eq(UInt<4>(0hf), remapindex_25) when _T_4085 : connect remapVecData[25], Queue10_UInt8_15.io.deq.bits connect remapVecValids[25], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[25] node _T_4086 = eq(UInt<5>(0h10), remapindex_25) when _T_4086 : connect remapVecData[25], Queue10_UInt8_16.io.deq.bits connect remapVecValids[25], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[25] node _T_4087 = eq(UInt<5>(0h11), remapindex_25) when _T_4087 : connect remapVecData[25], Queue10_UInt8_17.io.deq.bits connect remapVecValids[25], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[25] node _T_4088 = eq(UInt<5>(0h12), remapindex_25) when _T_4088 : connect remapVecData[25], Queue10_UInt8_18.io.deq.bits connect remapVecValids[25], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[25] node _T_4089 = eq(UInt<5>(0h13), remapindex_25) when _T_4089 : connect remapVecData[25], Queue10_UInt8_19.io.deq.bits connect remapVecValids[25], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[25] node _T_4090 = eq(UInt<5>(0h14), remapindex_25) when _T_4090 : connect remapVecData[25], Queue10_UInt8_20.io.deq.bits connect remapVecValids[25], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[25] node _T_4091 = eq(UInt<5>(0h15), remapindex_25) when _T_4091 : connect remapVecData[25], Queue10_UInt8_21.io.deq.bits connect remapVecValids[25], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[25] node _T_4092 = eq(UInt<5>(0h16), remapindex_25) when _T_4092 : connect remapVecData[25], Queue10_UInt8_22.io.deq.bits connect remapVecValids[25], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[25] node _T_4093 = eq(UInt<5>(0h17), remapindex_25) when _T_4093 : connect remapVecData[25], Queue10_UInt8_23.io.deq.bits connect remapVecValids[25], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[25] node _T_4094 = eq(UInt<5>(0h18), remapindex_25) when _T_4094 : connect remapVecData[25], Queue10_UInt8_24.io.deq.bits connect remapVecValids[25], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[25] node _T_4095 = eq(UInt<5>(0h19), remapindex_25) when _T_4095 : connect remapVecData[25], Queue10_UInt8_25.io.deq.bits connect remapVecValids[25], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[25] node _T_4096 = eq(UInt<5>(0h1a), remapindex_25) when _T_4096 : connect remapVecData[25], Queue10_UInt8_26.io.deq.bits connect remapVecValids[25], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[25] node _T_4097 = eq(UInt<5>(0h1b), remapindex_25) when _T_4097 : connect remapVecData[25], Queue10_UInt8_27.io.deq.bits connect remapVecValids[25], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[25] node _T_4098 = eq(UInt<5>(0h1c), remapindex_25) when _T_4098 : connect remapVecData[25], Queue10_UInt8_28.io.deq.bits connect remapVecValids[25], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[25] node _T_4099 = eq(UInt<5>(0h1d), remapindex_25) when _T_4099 : connect remapVecData[25], Queue10_UInt8_29.io.deq.bits connect remapVecValids[25], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[25] node _T_4100 = eq(UInt<5>(0h1e), remapindex_25) when _T_4100 : connect remapVecData[25], Queue10_UInt8_30.io.deq.bits connect remapVecValids[25], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[25] node _T_4101 = eq(UInt<5>(0h1f), remapindex_25) when _T_4101 : connect remapVecData[25], Queue10_UInt8_31.io.deq.bits connect remapVecValids[25], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[25] node _remapindex_T_26 = add(UInt<5>(0h1a), read_start_index) node remapindex_26 = rem(_remapindex_T_26, UInt<6>(0h20)) node _T_4102 = eq(UInt<1>(0h0), remapindex_26) when _T_4102 : connect remapVecData[26], Queue10_UInt8.io.deq.bits connect remapVecValids[26], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[26] node _T_4103 = eq(UInt<1>(0h1), remapindex_26) when _T_4103 : connect remapVecData[26], Queue10_UInt8_1.io.deq.bits connect remapVecValids[26], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[26] node _T_4104 = eq(UInt<2>(0h2), remapindex_26) when _T_4104 : connect remapVecData[26], Queue10_UInt8_2.io.deq.bits connect remapVecValids[26], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[26] node _T_4105 = eq(UInt<2>(0h3), remapindex_26) when _T_4105 : connect remapVecData[26], Queue10_UInt8_3.io.deq.bits connect remapVecValids[26], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[26] node _T_4106 = eq(UInt<3>(0h4), remapindex_26) when _T_4106 : connect remapVecData[26], Queue10_UInt8_4.io.deq.bits connect remapVecValids[26], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[26] node _T_4107 = eq(UInt<3>(0h5), remapindex_26) when _T_4107 : connect remapVecData[26], Queue10_UInt8_5.io.deq.bits connect remapVecValids[26], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[26] node _T_4108 = eq(UInt<3>(0h6), remapindex_26) when _T_4108 : connect remapVecData[26], Queue10_UInt8_6.io.deq.bits connect remapVecValids[26], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[26] node _T_4109 = eq(UInt<3>(0h7), remapindex_26) when _T_4109 : connect remapVecData[26], Queue10_UInt8_7.io.deq.bits connect remapVecValids[26], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[26] node _T_4110 = eq(UInt<4>(0h8), remapindex_26) when _T_4110 : connect remapVecData[26], Queue10_UInt8_8.io.deq.bits connect remapVecValids[26], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[26] node _T_4111 = eq(UInt<4>(0h9), remapindex_26) when _T_4111 : connect remapVecData[26], Queue10_UInt8_9.io.deq.bits connect remapVecValids[26], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[26] node _T_4112 = eq(UInt<4>(0ha), remapindex_26) when _T_4112 : connect remapVecData[26], Queue10_UInt8_10.io.deq.bits connect remapVecValids[26], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[26] node _T_4113 = eq(UInt<4>(0hb), remapindex_26) when _T_4113 : connect remapVecData[26], Queue10_UInt8_11.io.deq.bits connect remapVecValids[26], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[26] node _T_4114 = eq(UInt<4>(0hc), remapindex_26) when _T_4114 : connect remapVecData[26], Queue10_UInt8_12.io.deq.bits connect remapVecValids[26], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[26] node _T_4115 = eq(UInt<4>(0hd), remapindex_26) when _T_4115 : connect remapVecData[26], Queue10_UInt8_13.io.deq.bits connect remapVecValids[26], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[26] node _T_4116 = eq(UInt<4>(0he), remapindex_26) when _T_4116 : connect remapVecData[26], Queue10_UInt8_14.io.deq.bits connect remapVecValids[26], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[26] node _T_4117 = eq(UInt<4>(0hf), remapindex_26) when _T_4117 : connect remapVecData[26], Queue10_UInt8_15.io.deq.bits connect remapVecValids[26], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[26] node _T_4118 = eq(UInt<5>(0h10), remapindex_26) when _T_4118 : connect remapVecData[26], Queue10_UInt8_16.io.deq.bits connect remapVecValids[26], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[26] node _T_4119 = eq(UInt<5>(0h11), remapindex_26) when _T_4119 : connect remapVecData[26], Queue10_UInt8_17.io.deq.bits connect remapVecValids[26], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[26] node _T_4120 = eq(UInt<5>(0h12), remapindex_26) when _T_4120 : connect remapVecData[26], Queue10_UInt8_18.io.deq.bits connect remapVecValids[26], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[26] node _T_4121 = eq(UInt<5>(0h13), remapindex_26) when _T_4121 : connect remapVecData[26], Queue10_UInt8_19.io.deq.bits connect remapVecValids[26], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[26] node _T_4122 = eq(UInt<5>(0h14), remapindex_26) when _T_4122 : connect remapVecData[26], Queue10_UInt8_20.io.deq.bits connect remapVecValids[26], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[26] node _T_4123 = eq(UInt<5>(0h15), remapindex_26) when _T_4123 : connect remapVecData[26], Queue10_UInt8_21.io.deq.bits connect remapVecValids[26], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[26] node _T_4124 = eq(UInt<5>(0h16), remapindex_26) when _T_4124 : connect remapVecData[26], Queue10_UInt8_22.io.deq.bits connect remapVecValids[26], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[26] node _T_4125 = eq(UInt<5>(0h17), remapindex_26) when _T_4125 : connect remapVecData[26], Queue10_UInt8_23.io.deq.bits connect remapVecValids[26], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[26] node _T_4126 = eq(UInt<5>(0h18), remapindex_26) when _T_4126 : connect remapVecData[26], Queue10_UInt8_24.io.deq.bits connect remapVecValids[26], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[26] node _T_4127 = eq(UInt<5>(0h19), remapindex_26) when _T_4127 : connect remapVecData[26], Queue10_UInt8_25.io.deq.bits connect remapVecValids[26], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[26] node _T_4128 = eq(UInt<5>(0h1a), remapindex_26) when _T_4128 : connect remapVecData[26], Queue10_UInt8_26.io.deq.bits connect remapVecValids[26], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[26] node _T_4129 = eq(UInt<5>(0h1b), remapindex_26) when _T_4129 : connect remapVecData[26], Queue10_UInt8_27.io.deq.bits connect remapVecValids[26], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[26] node _T_4130 = eq(UInt<5>(0h1c), remapindex_26) when _T_4130 : connect remapVecData[26], Queue10_UInt8_28.io.deq.bits connect remapVecValids[26], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[26] node _T_4131 = eq(UInt<5>(0h1d), remapindex_26) when _T_4131 : connect remapVecData[26], Queue10_UInt8_29.io.deq.bits connect remapVecValids[26], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[26] node _T_4132 = eq(UInt<5>(0h1e), remapindex_26) when _T_4132 : connect remapVecData[26], Queue10_UInt8_30.io.deq.bits connect remapVecValids[26], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[26] node _T_4133 = eq(UInt<5>(0h1f), remapindex_26) when _T_4133 : connect remapVecData[26], Queue10_UInt8_31.io.deq.bits connect remapVecValids[26], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[26] node _remapindex_T_27 = add(UInt<5>(0h1b), read_start_index) node remapindex_27 = rem(_remapindex_T_27, UInt<6>(0h20)) node _T_4134 = eq(UInt<1>(0h0), remapindex_27) when _T_4134 : connect remapVecData[27], Queue10_UInt8.io.deq.bits connect remapVecValids[27], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[27] node _T_4135 = eq(UInt<1>(0h1), remapindex_27) when _T_4135 : connect remapVecData[27], Queue10_UInt8_1.io.deq.bits connect remapVecValids[27], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[27] node _T_4136 = eq(UInt<2>(0h2), remapindex_27) when _T_4136 : connect remapVecData[27], Queue10_UInt8_2.io.deq.bits connect remapVecValids[27], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[27] node _T_4137 = eq(UInt<2>(0h3), remapindex_27) when _T_4137 : connect remapVecData[27], Queue10_UInt8_3.io.deq.bits connect remapVecValids[27], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[27] node _T_4138 = eq(UInt<3>(0h4), remapindex_27) when _T_4138 : connect remapVecData[27], Queue10_UInt8_4.io.deq.bits connect remapVecValids[27], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[27] node _T_4139 = eq(UInt<3>(0h5), remapindex_27) when _T_4139 : connect remapVecData[27], Queue10_UInt8_5.io.deq.bits connect remapVecValids[27], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[27] node _T_4140 = eq(UInt<3>(0h6), remapindex_27) when _T_4140 : connect remapVecData[27], Queue10_UInt8_6.io.deq.bits connect remapVecValids[27], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[27] node _T_4141 = eq(UInt<3>(0h7), remapindex_27) when _T_4141 : connect remapVecData[27], Queue10_UInt8_7.io.deq.bits connect remapVecValids[27], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[27] node _T_4142 = eq(UInt<4>(0h8), remapindex_27) when _T_4142 : connect remapVecData[27], Queue10_UInt8_8.io.deq.bits connect remapVecValids[27], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[27] node _T_4143 = eq(UInt<4>(0h9), remapindex_27) when _T_4143 : connect remapVecData[27], Queue10_UInt8_9.io.deq.bits connect remapVecValids[27], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[27] node _T_4144 = eq(UInt<4>(0ha), remapindex_27) when _T_4144 : connect remapVecData[27], Queue10_UInt8_10.io.deq.bits connect remapVecValids[27], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[27] node _T_4145 = eq(UInt<4>(0hb), remapindex_27) when _T_4145 : connect remapVecData[27], Queue10_UInt8_11.io.deq.bits connect remapVecValids[27], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[27] node _T_4146 = eq(UInt<4>(0hc), remapindex_27) when _T_4146 : connect remapVecData[27], Queue10_UInt8_12.io.deq.bits connect remapVecValids[27], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[27] node _T_4147 = eq(UInt<4>(0hd), remapindex_27) when _T_4147 : connect remapVecData[27], Queue10_UInt8_13.io.deq.bits connect remapVecValids[27], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[27] node _T_4148 = eq(UInt<4>(0he), remapindex_27) when _T_4148 : connect remapVecData[27], Queue10_UInt8_14.io.deq.bits connect remapVecValids[27], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[27] node _T_4149 = eq(UInt<4>(0hf), remapindex_27) when _T_4149 : connect remapVecData[27], Queue10_UInt8_15.io.deq.bits connect remapVecValids[27], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[27] node _T_4150 = eq(UInt<5>(0h10), remapindex_27) when _T_4150 : connect remapVecData[27], Queue10_UInt8_16.io.deq.bits connect remapVecValids[27], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[27] node _T_4151 = eq(UInt<5>(0h11), remapindex_27) when _T_4151 : connect remapVecData[27], Queue10_UInt8_17.io.deq.bits connect remapVecValids[27], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[27] node _T_4152 = eq(UInt<5>(0h12), remapindex_27) when _T_4152 : connect remapVecData[27], Queue10_UInt8_18.io.deq.bits connect remapVecValids[27], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[27] node _T_4153 = eq(UInt<5>(0h13), remapindex_27) when _T_4153 : connect remapVecData[27], Queue10_UInt8_19.io.deq.bits connect remapVecValids[27], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[27] node _T_4154 = eq(UInt<5>(0h14), remapindex_27) when _T_4154 : connect remapVecData[27], Queue10_UInt8_20.io.deq.bits connect remapVecValids[27], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[27] node _T_4155 = eq(UInt<5>(0h15), remapindex_27) when _T_4155 : connect remapVecData[27], Queue10_UInt8_21.io.deq.bits connect remapVecValids[27], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[27] node _T_4156 = eq(UInt<5>(0h16), remapindex_27) when _T_4156 : connect remapVecData[27], Queue10_UInt8_22.io.deq.bits connect remapVecValids[27], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[27] node _T_4157 = eq(UInt<5>(0h17), remapindex_27) when _T_4157 : connect remapVecData[27], Queue10_UInt8_23.io.deq.bits connect remapVecValids[27], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[27] node _T_4158 = eq(UInt<5>(0h18), remapindex_27) when _T_4158 : connect remapVecData[27], Queue10_UInt8_24.io.deq.bits connect remapVecValids[27], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[27] node _T_4159 = eq(UInt<5>(0h19), remapindex_27) when _T_4159 : connect remapVecData[27], Queue10_UInt8_25.io.deq.bits connect remapVecValids[27], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[27] node _T_4160 = eq(UInt<5>(0h1a), remapindex_27) when _T_4160 : connect remapVecData[27], Queue10_UInt8_26.io.deq.bits connect remapVecValids[27], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[27] node _T_4161 = eq(UInt<5>(0h1b), remapindex_27) when _T_4161 : connect remapVecData[27], Queue10_UInt8_27.io.deq.bits connect remapVecValids[27], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[27] node _T_4162 = eq(UInt<5>(0h1c), remapindex_27) when _T_4162 : connect remapVecData[27], Queue10_UInt8_28.io.deq.bits connect remapVecValids[27], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[27] node _T_4163 = eq(UInt<5>(0h1d), remapindex_27) when _T_4163 : connect remapVecData[27], Queue10_UInt8_29.io.deq.bits connect remapVecValids[27], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[27] node _T_4164 = eq(UInt<5>(0h1e), remapindex_27) when _T_4164 : connect remapVecData[27], Queue10_UInt8_30.io.deq.bits connect remapVecValids[27], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[27] node _T_4165 = eq(UInt<5>(0h1f), remapindex_27) when _T_4165 : connect remapVecData[27], Queue10_UInt8_31.io.deq.bits connect remapVecValids[27], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[27] node _remapindex_T_28 = add(UInt<5>(0h1c), read_start_index) node remapindex_28 = rem(_remapindex_T_28, UInt<6>(0h20)) node _T_4166 = eq(UInt<1>(0h0), remapindex_28) when _T_4166 : connect remapVecData[28], Queue10_UInt8.io.deq.bits connect remapVecValids[28], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[28] node _T_4167 = eq(UInt<1>(0h1), remapindex_28) when _T_4167 : connect remapVecData[28], Queue10_UInt8_1.io.deq.bits connect remapVecValids[28], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[28] node _T_4168 = eq(UInt<2>(0h2), remapindex_28) when _T_4168 : connect remapVecData[28], Queue10_UInt8_2.io.deq.bits connect remapVecValids[28], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[28] node _T_4169 = eq(UInt<2>(0h3), remapindex_28) when _T_4169 : connect remapVecData[28], Queue10_UInt8_3.io.deq.bits connect remapVecValids[28], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[28] node _T_4170 = eq(UInt<3>(0h4), remapindex_28) when _T_4170 : connect remapVecData[28], Queue10_UInt8_4.io.deq.bits connect remapVecValids[28], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[28] node _T_4171 = eq(UInt<3>(0h5), remapindex_28) when _T_4171 : connect remapVecData[28], Queue10_UInt8_5.io.deq.bits connect remapVecValids[28], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[28] node _T_4172 = eq(UInt<3>(0h6), remapindex_28) when _T_4172 : connect remapVecData[28], Queue10_UInt8_6.io.deq.bits connect remapVecValids[28], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[28] node _T_4173 = eq(UInt<3>(0h7), remapindex_28) when _T_4173 : connect remapVecData[28], Queue10_UInt8_7.io.deq.bits connect remapVecValids[28], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[28] node _T_4174 = eq(UInt<4>(0h8), remapindex_28) when _T_4174 : connect remapVecData[28], Queue10_UInt8_8.io.deq.bits connect remapVecValids[28], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[28] node _T_4175 = eq(UInt<4>(0h9), remapindex_28) when _T_4175 : connect remapVecData[28], Queue10_UInt8_9.io.deq.bits connect remapVecValids[28], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[28] node _T_4176 = eq(UInt<4>(0ha), remapindex_28) when _T_4176 : connect remapVecData[28], Queue10_UInt8_10.io.deq.bits connect remapVecValids[28], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[28] node _T_4177 = eq(UInt<4>(0hb), remapindex_28) when _T_4177 : connect remapVecData[28], Queue10_UInt8_11.io.deq.bits connect remapVecValids[28], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[28] node _T_4178 = eq(UInt<4>(0hc), remapindex_28) when _T_4178 : connect remapVecData[28], Queue10_UInt8_12.io.deq.bits connect remapVecValids[28], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[28] node _T_4179 = eq(UInt<4>(0hd), remapindex_28) when _T_4179 : connect remapVecData[28], Queue10_UInt8_13.io.deq.bits connect remapVecValids[28], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[28] node _T_4180 = eq(UInt<4>(0he), remapindex_28) when _T_4180 : connect remapVecData[28], Queue10_UInt8_14.io.deq.bits connect remapVecValids[28], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[28] node _T_4181 = eq(UInt<4>(0hf), remapindex_28) when _T_4181 : connect remapVecData[28], Queue10_UInt8_15.io.deq.bits connect remapVecValids[28], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[28] node _T_4182 = eq(UInt<5>(0h10), remapindex_28) when _T_4182 : connect remapVecData[28], Queue10_UInt8_16.io.deq.bits connect remapVecValids[28], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[28] node _T_4183 = eq(UInt<5>(0h11), remapindex_28) when _T_4183 : connect remapVecData[28], Queue10_UInt8_17.io.deq.bits connect remapVecValids[28], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[28] node _T_4184 = eq(UInt<5>(0h12), remapindex_28) when _T_4184 : connect remapVecData[28], Queue10_UInt8_18.io.deq.bits connect remapVecValids[28], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[28] node _T_4185 = eq(UInt<5>(0h13), remapindex_28) when _T_4185 : connect remapVecData[28], Queue10_UInt8_19.io.deq.bits connect remapVecValids[28], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[28] node _T_4186 = eq(UInt<5>(0h14), remapindex_28) when _T_4186 : connect remapVecData[28], Queue10_UInt8_20.io.deq.bits connect remapVecValids[28], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[28] node _T_4187 = eq(UInt<5>(0h15), remapindex_28) when _T_4187 : connect remapVecData[28], Queue10_UInt8_21.io.deq.bits connect remapVecValids[28], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[28] node _T_4188 = eq(UInt<5>(0h16), remapindex_28) when _T_4188 : connect remapVecData[28], Queue10_UInt8_22.io.deq.bits connect remapVecValids[28], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[28] node _T_4189 = eq(UInt<5>(0h17), remapindex_28) when _T_4189 : connect remapVecData[28], Queue10_UInt8_23.io.deq.bits connect remapVecValids[28], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[28] node _T_4190 = eq(UInt<5>(0h18), remapindex_28) when _T_4190 : connect remapVecData[28], Queue10_UInt8_24.io.deq.bits connect remapVecValids[28], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[28] node _T_4191 = eq(UInt<5>(0h19), remapindex_28) when _T_4191 : connect remapVecData[28], Queue10_UInt8_25.io.deq.bits connect remapVecValids[28], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[28] node _T_4192 = eq(UInt<5>(0h1a), remapindex_28) when _T_4192 : connect remapVecData[28], Queue10_UInt8_26.io.deq.bits connect remapVecValids[28], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[28] node _T_4193 = eq(UInt<5>(0h1b), remapindex_28) when _T_4193 : connect remapVecData[28], Queue10_UInt8_27.io.deq.bits connect remapVecValids[28], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[28] node _T_4194 = eq(UInt<5>(0h1c), remapindex_28) when _T_4194 : connect remapVecData[28], Queue10_UInt8_28.io.deq.bits connect remapVecValids[28], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[28] node _T_4195 = eq(UInt<5>(0h1d), remapindex_28) when _T_4195 : connect remapVecData[28], Queue10_UInt8_29.io.deq.bits connect remapVecValids[28], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[28] node _T_4196 = eq(UInt<5>(0h1e), remapindex_28) when _T_4196 : connect remapVecData[28], Queue10_UInt8_30.io.deq.bits connect remapVecValids[28], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[28] node _T_4197 = eq(UInt<5>(0h1f), remapindex_28) when _T_4197 : connect remapVecData[28], Queue10_UInt8_31.io.deq.bits connect remapVecValids[28], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[28] node _remapindex_T_29 = add(UInt<5>(0h1d), read_start_index) node remapindex_29 = rem(_remapindex_T_29, UInt<6>(0h20)) node _T_4198 = eq(UInt<1>(0h0), remapindex_29) when _T_4198 : connect remapVecData[29], Queue10_UInt8.io.deq.bits connect remapVecValids[29], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[29] node _T_4199 = eq(UInt<1>(0h1), remapindex_29) when _T_4199 : connect remapVecData[29], Queue10_UInt8_1.io.deq.bits connect remapVecValids[29], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[29] node _T_4200 = eq(UInt<2>(0h2), remapindex_29) when _T_4200 : connect remapVecData[29], Queue10_UInt8_2.io.deq.bits connect remapVecValids[29], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[29] node _T_4201 = eq(UInt<2>(0h3), remapindex_29) when _T_4201 : connect remapVecData[29], Queue10_UInt8_3.io.deq.bits connect remapVecValids[29], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[29] node _T_4202 = eq(UInt<3>(0h4), remapindex_29) when _T_4202 : connect remapVecData[29], Queue10_UInt8_4.io.deq.bits connect remapVecValids[29], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[29] node _T_4203 = eq(UInt<3>(0h5), remapindex_29) when _T_4203 : connect remapVecData[29], Queue10_UInt8_5.io.deq.bits connect remapVecValids[29], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[29] node _T_4204 = eq(UInt<3>(0h6), remapindex_29) when _T_4204 : connect remapVecData[29], Queue10_UInt8_6.io.deq.bits connect remapVecValids[29], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[29] node _T_4205 = eq(UInt<3>(0h7), remapindex_29) when _T_4205 : connect remapVecData[29], Queue10_UInt8_7.io.deq.bits connect remapVecValids[29], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[29] node _T_4206 = eq(UInt<4>(0h8), remapindex_29) when _T_4206 : connect remapVecData[29], Queue10_UInt8_8.io.deq.bits connect remapVecValids[29], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[29] node _T_4207 = eq(UInt<4>(0h9), remapindex_29) when _T_4207 : connect remapVecData[29], Queue10_UInt8_9.io.deq.bits connect remapVecValids[29], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[29] node _T_4208 = eq(UInt<4>(0ha), remapindex_29) when _T_4208 : connect remapVecData[29], Queue10_UInt8_10.io.deq.bits connect remapVecValids[29], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[29] node _T_4209 = eq(UInt<4>(0hb), remapindex_29) when _T_4209 : connect remapVecData[29], Queue10_UInt8_11.io.deq.bits connect remapVecValids[29], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[29] node _T_4210 = eq(UInt<4>(0hc), remapindex_29) when _T_4210 : connect remapVecData[29], Queue10_UInt8_12.io.deq.bits connect remapVecValids[29], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[29] node _T_4211 = eq(UInt<4>(0hd), remapindex_29) when _T_4211 : connect remapVecData[29], Queue10_UInt8_13.io.deq.bits connect remapVecValids[29], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[29] node _T_4212 = eq(UInt<4>(0he), remapindex_29) when _T_4212 : connect remapVecData[29], Queue10_UInt8_14.io.deq.bits connect remapVecValids[29], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[29] node _T_4213 = eq(UInt<4>(0hf), remapindex_29) when _T_4213 : connect remapVecData[29], Queue10_UInt8_15.io.deq.bits connect remapVecValids[29], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[29] node _T_4214 = eq(UInt<5>(0h10), remapindex_29) when _T_4214 : connect remapVecData[29], Queue10_UInt8_16.io.deq.bits connect remapVecValids[29], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[29] node _T_4215 = eq(UInt<5>(0h11), remapindex_29) when _T_4215 : connect remapVecData[29], Queue10_UInt8_17.io.deq.bits connect remapVecValids[29], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[29] node _T_4216 = eq(UInt<5>(0h12), remapindex_29) when _T_4216 : connect remapVecData[29], Queue10_UInt8_18.io.deq.bits connect remapVecValids[29], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[29] node _T_4217 = eq(UInt<5>(0h13), remapindex_29) when _T_4217 : connect remapVecData[29], Queue10_UInt8_19.io.deq.bits connect remapVecValids[29], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[29] node _T_4218 = eq(UInt<5>(0h14), remapindex_29) when _T_4218 : connect remapVecData[29], Queue10_UInt8_20.io.deq.bits connect remapVecValids[29], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[29] node _T_4219 = eq(UInt<5>(0h15), remapindex_29) when _T_4219 : connect remapVecData[29], Queue10_UInt8_21.io.deq.bits connect remapVecValids[29], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[29] node _T_4220 = eq(UInt<5>(0h16), remapindex_29) when _T_4220 : connect remapVecData[29], Queue10_UInt8_22.io.deq.bits connect remapVecValids[29], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[29] node _T_4221 = eq(UInt<5>(0h17), remapindex_29) when _T_4221 : connect remapVecData[29], Queue10_UInt8_23.io.deq.bits connect remapVecValids[29], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[29] node _T_4222 = eq(UInt<5>(0h18), remapindex_29) when _T_4222 : connect remapVecData[29], Queue10_UInt8_24.io.deq.bits connect remapVecValids[29], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[29] node _T_4223 = eq(UInt<5>(0h19), remapindex_29) when _T_4223 : connect remapVecData[29], Queue10_UInt8_25.io.deq.bits connect remapVecValids[29], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[29] node _T_4224 = eq(UInt<5>(0h1a), remapindex_29) when _T_4224 : connect remapVecData[29], Queue10_UInt8_26.io.deq.bits connect remapVecValids[29], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[29] node _T_4225 = eq(UInt<5>(0h1b), remapindex_29) when _T_4225 : connect remapVecData[29], Queue10_UInt8_27.io.deq.bits connect remapVecValids[29], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[29] node _T_4226 = eq(UInt<5>(0h1c), remapindex_29) when _T_4226 : connect remapVecData[29], Queue10_UInt8_28.io.deq.bits connect remapVecValids[29], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[29] node _T_4227 = eq(UInt<5>(0h1d), remapindex_29) when _T_4227 : connect remapVecData[29], Queue10_UInt8_29.io.deq.bits connect remapVecValids[29], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[29] node _T_4228 = eq(UInt<5>(0h1e), remapindex_29) when _T_4228 : connect remapVecData[29], Queue10_UInt8_30.io.deq.bits connect remapVecValids[29], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[29] node _T_4229 = eq(UInt<5>(0h1f), remapindex_29) when _T_4229 : connect remapVecData[29], Queue10_UInt8_31.io.deq.bits connect remapVecValids[29], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[29] node _remapindex_T_30 = add(UInt<5>(0h1e), read_start_index) node remapindex_30 = rem(_remapindex_T_30, UInt<6>(0h20)) node _T_4230 = eq(UInt<1>(0h0), remapindex_30) when _T_4230 : connect remapVecData[30], Queue10_UInt8.io.deq.bits connect remapVecValids[30], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[30] node _T_4231 = eq(UInt<1>(0h1), remapindex_30) when _T_4231 : connect remapVecData[30], Queue10_UInt8_1.io.deq.bits connect remapVecValids[30], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[30] node _T_4232 = eq(UInt<2>(0h2), remapindex_30) when _T_4232 : connect remapVecData[30], Queue10_UInt8_2.io.deq.bits connect remapVecValids[30], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[30] node _T_4233 = eq(UInt<2>(0h3), remapindex_30) when _T_4233 : connect remapVecData[30], Queue10_UInt8_3.io.deq.bits connect remapVecValids[30], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[30] node _T_4234 = eq(UInt<3>(0h4), remapindex_30) when _T_4234 : connect remapVecData[30], Queue10_UInt8_4.io.deq.bits connect remapVecValids[30], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[30] node _T_4235 = eq(UInt<3>(0h5), remapindex_30) when _T_4235 : connect remapVecData[30], Queue10_UInt8_5.io.deq.bits connect remapVecValids[30], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[30] node _T_4236 = eq(UInt<3>(0h6), remapindex_30) when _T_4236 : connect remapVecData[30], Queue10_UInt8_6.io.deq.bits connect remapVecValids[30], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[30] node _T_4237 = eq(UInt<3>(0h7), remapindex_30) when _T_4237 : connect remapVecData[30], Queue10_UInt8_7.io.deq.bits connect remapVecValids[30], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[30] node _T_4238 = eq(UInt<4>(0h8), remapindex_30) when _T_4238 : connect remapVecData[30], Queue10_UInt8_8.io.deq.bits connect remapVecValids[30], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[30] node _T_4239 = eq(UInt<4>(0h9), remapindex_30) when _T_4239 : connect remapVecData[30], Queue10_UInt8_9.io.deq.bits connect remapVecValids[30], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[30] node _T_4240 = eq(UInt<4>(0ha), remapindex_30) when _T_4240 : connect remapVecData[30], Queue10_UInt8_10.io.deq.bits connect remapVecValids[30], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[30] node _T_4241 = eq(UInt<4>(0hb), remapindex_30) when _T_4241 : connect remapVecData[30], Queue10_UInt8_11.io.deq.bits connect remapVecValids[30], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[30] node _T_4242 = eq(UInt<4>(0hc), remapindex_30) when _T_4242 : connect remapVecData[30], Queue10_UInt8_12.io.deq.bits connect remapVecValids[30], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[30] node _T_4243 = eq(UInt<4>(0hd), remapindex_30) when _T_4243 : connect remapVecData[30], Queue10_UInt8_13.io.deq.bits connect remapVecValids[30], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[30] node _T_4244 = eq(UInt<4>(0he), remapindex_30) when _T_4244 : connect remapVecData[30], Queue10_UInt8_14.io.deq.bits connect remapVecValids[30], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[30] node _T_4245 = eq(UInt<4>(0hf), remapindex_30) when _T_4245 : connect remapVecData[30], Queue10_UInt8_15.io.deq.bits connect remapVecValids[30], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[30] node _T_4246 = eq(UInt<5>(0h10), remapindex_30) when _T_4246 : connect remapVecData[30], Queue10_UInt8_16.io.deq.bits connect remapVecValids[30], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[30] node _T_4247 = eq(UInt<5>(0h11), remapindex_30) when _T_4247 : connect remapVecData[30], Queue10_UInt8_17.io.deq.bits connect remapVecValids[30], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[30] node _T_4248 = eq(UInt<5>(0h12), remapindex_30) when _T_4248 : connect remapVecData[30], Queue10_UInt8_18.io.deq.bits connect remapVecValids[30], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[30] node _T_4249 = eq(UInt<5>(0h13), remapindex_30) when _T_4249 : connect remapVecData[30], Queue10_UInt8_19.io.deq.bits connect remapVecValids[30], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[30] node _T_4250 = eq(UInt<5>(0h14), remapindex_30) when _T_4250 : connect remapVecData[30], Queue10_UInt8_20.io.deq.bits connect remapVecValids[30], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[30] node _T_4251 = eq(UInt<5>(0h15), remapindex_30) when _T_4251 : connect remapVecData[30], Queue10_UInt8_21.io.deq.bits connect remapVecValids[30], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[30] node _T_4252 = eq(UInt<5>(0h16), remapindex_30) when _T_4252 : connect remapVecData[30], Queue10_UInt8_22.io.deq.bits connect remapVecValids[30], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[30] node _T_4253 = eq(UInt<5>(0h17), remapindex_30) when _T_4253 : connect remapVecData[30], Queue10_UInt8_23.io.deq.bits connect remapVecValids[30], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[30] node _T_4254 = eq(UInt<5>(0h18), remapindex_30) when _T_4254 : connect remapVecData[30], Queue10_UInt8_24.io.deq.bits connect remapVecValids[30], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[30] node _T_4255 = eq(UInt<5>(0h19), remapindex_30) when _T_4255 : connect remapVecData[30], Queue10_UInt8_25.io.deq.bits connect remapVecValids[30], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[30] node _T_4256 = eq(UInt<5>(0h1a), remapindex_30) when _T_4256 : connect remapVecData[30], Queue10_UInt8_26.io.deq.bits connect remapVecValids[30], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[30] node _T_4257 = eq(UInt<5>(0h1b), remapindex_30) when _T_4257 : connect remapVecData[30], Queue10_UInt8_27.io.deq.bits connect remapVecValids[30], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[30] node _T_4258 = eq(UInt<5>(0h1c), remapindex_30) when _T_4258 : connect remapVecData[30], Queue10_UInt8_28.io.deq.bits connect remapVecValids[30], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[30] node _T_4259 = eq(UInt<5>(0h1d), remapindex_30) when _T_4259 : connect remapVecData[30], Queue10_UInt8_29.io.deq.bits connect remapVecValids[30], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[30] node _T_4260 = eq(UInt<5>(0h1e), remapindex_30) when _T_4260 : connect remapVecData[30], Queue10_UInt8_30.io.deq.bits connect remapVecValids[30], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[30] node _T_4261 = eq(UInt<5>(0h1f), remapindex_30) when _T_4261 : connect remapVecData[30], Queue10_UInt8_31.io.deq.bits connect remapVecValids[30], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[30] node _remapindex_T_31 = add(UInt<5>(0h1f), read_start_index) node remapindex_31 = rem(_remapindex_T_31, UInt<6>(0h20)) node _T_4262 = eq(UInt<1>(0h0), remapindex_31) when _T_4262 : connect remapVecData[31], Queue10_UInt8.io.deq.bits connect remapVecValids[31], Queue10_UInt8.io.deq.valid connect Queue10_UInt8.io.deq.ready, remapVecReadys[31] node _T_4263 = eq(UInt<1>(0h1), remapindex_31) when _T_4263 : connect remapVecData[31], Queue10_UInt8_1.io.deq.bits connect remapVecValids[31], Queue10_UInt8_1.io.deq.valid connect Queue10_UInt8_1.io.deq.ready, remapVecReadys[31] node _T_4264 = eq(UInt<2>(0h2), remapindex_31) when _T_4264 : connect remapVecData[31], Queue10_UInt8_2.io.deq.bits connect remapVecValids[31], Queue10_UInt8_2.io.deq.valid connect Queue10_UInt8_2.io.deq.ready, remapVecReadys[31] node _T_4265 = eq(UInt<2>(0h3), remapindex_31) when _T_4265 : connect remapVecData[31], Queue10_UInt8_3.io.deq.bits connect remapVecValids[31], Queue10_UInt8_3.io.deq.valid connect Queue10_UInt8_3.io.deq.ready, remapVecReadys[31] node _T_4266 = eq(UInt<3>(0h4), remapindex_31) when _T_4266 : connect remapVecData[31], Queue10_UInt8_4.io.deq.bits connect remapVecValids[31], Queue10_UInt8_4.io.deq.valid connect Queue10_UInt8_4.io.deq.ready, remapVecReadys[31] node _T_4267 = eq(UInt<3>(0h5), remapindex_31) when _T_4267 : connect remapVecData[31], Queue10_UInt8_5.io.deq.bits connect remapVecValids[31], Queue10_UInt8_5.io.deq.valid connect Queue10_UInt8_5.io.deq.ready, remapVecReadys[31] node _T_4268 = eq(UInt<3>(0h6), remapindex_31) when _T_4268 : connect remapVecData[31], Queue10_UInt8_6.io.deq.bits connect remapVecValids[31], Queue10_UInt8_6.io.deq.valid connect Queue10_UInt8_6.io.deq.ready, remapVecReadys[31] node _T_4269 = eq(UInt<3>(0h7), remapindex_31) when _T_4269 : connect remapVecData[31], Queue10_UInt8_7.io.deq.bits connect remapVecValids[31], Queue10_UInt8_7.io.deq.valid connect Queue10_UInt8_7.io.deq.ready, remapVecReadys[31] node _T_4270 = eq(UInt<4>(0h8), remapindex_31) when _T_4270 : connect remapVecData[31], Queue10_UInt8_8.io.deq.bits connect remapVecValids[31], Queue10_UInt8_8.io.deq.valid connect Queue10_UInt8_8.io.deq.ready, remapVecReadys[31] node _T_4271 = eq(UInt<4>(0h9), remapindex_31) when _T_4271 : connect remapVecData[31], Queue10_UInt8_9.io.deq.bits connect remapVecValids[31], Queue10_UInt8_9.io.deq.valid connect Queue10_UInt8_9.io.deq.ready, remapVecReadys[31] node _T_4272 = eq(UInt<4>(0ha), remapindex_31) when _T_4272 : connect remapVecData[31], Queue10_UInt8_10.io.deq.bits connect remapVecValids[31], Queue10_UInt8_10.io.deq.valid connect Queue10_UInt8_10.io.deq.ready, remapVecReadys[31] node _T_4273 = eq(UInt<4>(0hb), remapindex_31) when _T_4273 : connect remapVecData[31], Queue10_UInt8_11.io.deq.bits connect remapVecValids[31], Queue10_UInt8_11.io.deq.valid connect Queue10_UInt8_11.io.deq.ready, remapVecReadys[31] node _T_4274 = eq(UInt<4>(0hc), remapindex_31) when _T_4274 : connect remapVecData[31], Queue10_UInt8_12.io.deq.bits connect remapVecValids[31], Queue10_UInt8_12.io.deq.valid connect Queue10_UInt8_12.io.deq.ready, remapVecReadys[31] node _T_4275 = eq(UInt<4>(0hd), remapindex_31) when _T_4275 : connect remapVecData[31], Queue10_UInt8_13.io.deq.bits connect remapVecValids[31], Queue10_UInt8_13.io.deq.valid connect Queue10_UInt8_13.io.deq.ready, remapVecReadys[31] node _T_4276 = eq(UInt<4>(0he), remapindex_31) when _T_4276 : connect remapVecData[31], Queue10_UInt8_14.io.deq.bits connect remapVecValids[31], Queue10_UInt8_14.io.deq.valid connect Queue10_UInt8_14.io.deq.ready, remapVecReadys[31] node _T_4277 = eq(UInt<4>(0hf), remapindex_31) when _T_4277 : connect remapVecData[31], Queue10_UInt8_15.io.deq.bits connect remapVecValids[31], Queue10_UInt8_15.io.deq.valid connect Queue10_UInt8_15.io.deq.ready, remapVecReadys[31] node _T_4278 = eq(UInt<5>(0h10), remapindex_31) when _T_4278 : connect remapVecData[31], Queue10_UInt8_16.io.deq.bits connect remapVecValids[31], Queue10_UInt8_16.io.deq.valid connect Queue10_UInt8_16.io.deq.ready, remapVecReadys[31] node _T_4279 = eq(UInt<5>(0h11), remapindex_31) when _T_4279 : connect remapVecData[31], Queue10_UInt8_17.io.deq.bits connect remapVecValids[31], Queue10_UInt8_17.io.deq.valid connect Queue10_UInt8_17.io.deq.ready, remapVecReadys[31] node _T_4280 = eq(UInt<5>(0h12), remapindex_31) when _T_4280 : connect remapVecData[31], Queue10_UInt8_18.io.deq.bits connect remapVecValids[31], Queue10_UInt8_18.io.deq.valid connect Queue10_UInt8_18.io.deq.ready, remapVecReadys[31] node _T_4281 = eq(UInt<5>(0h13), remapindex_31) when _T_4281 : connect remapVecData[31], Queue10_UInt8_19.io.deq.bits connect remapVecValids[31], Queue10_UInt8_19.io.deq.valid connect Queue10_UInt8_19.io.deq.ready, remapVecReadys[31] node _T_4282 = eq(UInt<5>(0h14), remapindex_31) when _T_4282 : connect remapVecData[31], Queue10_UInt8_20.io.deq.bits connect remapVecValids[31], Queue10_UInt8_20.io.deq.valid connect Queue10_UInt8_20.io.deq.ready, remapVecReadys[31] node _T_4283 = eq(UInt<5>(0h15), remapindex_31) when _T_4283 : connect remapVecData[31], Queue10_UInt8_21.io.deq.bits connect remapVecValids[31], Queue10_UInt8_21.io.deq.valid connect Queue10_UInt8_21.io.deq.ready, remapVecReadys[31] node _T_4284 = eq(UInt<5>(0h16), remapindex_31) when _T_4284 : connect remapVecData[31], Queue10_UInt8_22.io.deq.bits connect remapVecValids[31], Queue10_UInt8_22.io.deq.valid connect Queue10_UInt8_22.io.deq.ready, remapVecReadys[31] node _T_4285 = eq(UInt<5>(0h17), remapindex_31) when _T_4285 : connect remapVecData[31], Queue10_UInt8_23.io.deq.bits connect remapVecValids[31], Queue10_UInt8_23.io.deq.valid connect Queue10_UInt8_23.io.deq.ready, remapVecReadys[31] node _T_4286 = eq(UInt<5>(0h18), remapindex_31) when _T_4286 : connect remapVecData[31], Queue10_UInt8_24.io.deq.bits connect remapVecValids[31], Queue10_UInt8_24.io.deq.valid connect Queue10_UInt8_24.io.deq.ready, remapVecReadys[31] node _T_4287 = eq(UInt<5>(0h19), remapindex_31) when _T_4287 : connect remapVecData[31], Queue10_UInt8_25.io.deq.bits connect remapVecValids[31], Queue10_UInt8_25.io.deq.valid connect Queue10_UInt8_25.io.deq.ready, remapVecReadys[31] node _T_4288 = eq(UInt<5>(0h1a), remapindex_31) when _T_4288 : connect remapVecData[31], Queue10_UInt8_26.io.deq.bits connect remapVecValids[31], Queue10_UInt8_26.io.deq.valid connect Queue10_UInt8_26.io.deq.ready, remapVecReadys[31] node _T_4289 = eq(UInt<5>(0h1b), remapindex_31) when _T_4289 : connect remapVecData[31], Queue10_UInt8_27.io.deq.bits connect remapVecValids[31], Queue10_UInt8_27.io.deq.valid connect Queue10_UInt8_27.io.deq.ready, remapVecReadys[31] node _T_4290 = eq(UInt<5>(0h1c), remapindex_31) when _T_4290 : connect remapVecData[31], Queue10_UInt8_28.io.deq.bits connect remapVecValids[31], Queue10_UInt8_28.io.deq.valid connect Queue10_UInt8_28.io.deq.ready, remapVecReadys[31] node _T_4291 = eq(UInt<5>(0h1d), remapindex_31) when _T_4291 : connect remapVecData[31], Queue10_UInt8_29.io.deq.bits connect remapVecValids[31], Queue10_UInt8_29.io.deq.valid connect Queue10_UInt8_29.io.deq.ready, remapVecReadys[31] node _T_4292 = eq(UInt<5>(0h1e), remapindex_31) when _T_4292 : connect remapVecData[31], Queue10_UInt8_30.io.deq.bits connect remapVecValids[31], Queue10_UInt8_30.io.deq.valid connect Queue10_UInt8_30.io.deq.ready, remapVecReadys[31] node _T_4293 = eq(UInt<5>(0h1f), remapindex_31) when _T_4293 : connect remapVecData[31], Queue10_UInt8_31.io.deq.bits connect remapVecValids[31], Queue10_UInt8_31.io.deq.valid connect Queue10_UInt8_31.io.deq.ready, remapVecReadys[31] node io_consumer_output_data_lo_lo_lo_lo = cat(remapVecData[1], remapVecData[0]) node io_consumer_output_data_lo_lo_lo_hi = cat(remapVecData[3], remapVecData[2]) node io_consumer_output_data_lo_lo_lo = cat(io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo) node io_consumer_output_data_lo_lo_hi_lo = cat(remapVecData[5], remapVecData[4]) node io_consumer_output_data_lo_lo_hi_hi = cat(remapVecData[7], remapVecData[6]) node io_consumer_output_data_lo_lo_hi = cat(io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo) node io_consumer_output_data_lo_lo = cat(io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo) node io_consumer_output_data_lo_hi_lo_lo = cat(remapVecData[9], remapVecData[8]) node io_consumer_output_data_lo_hi_lo_hi = cat(remapVecData[11], remapVecData[10]) node io_consumer_output_data_lo_hi_lo = cat(io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo) node io_consumer_output_data_lo_hi_hi_lo = cat(remapVecData[13], remapVecData[12]) node io_consumer_output_data_lo_hi_hi_hi = cat(remapVecData[15], remapVecData[14]) node io_consumer_output_data_lo_hi_hi = cat(io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo) node io_consumer_output_data_lo_hi = cat(io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo) node io_consumer_output_data_lo = cat(io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo) node io_consumer_output_data_hi_lo_lo_lo = cat(remapVecData[17], remapVecData[16]) node io_consumer_output_data_hi_lo_lo_hi = cat(remapVecData[19], remapVecData[18]) node io_consumer_output_data_hi_lo_lo = cat(io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo) node io_consumer_output_data_hi_lo_hi_lo = cat(remapVecData[21], remapVecData[20]) node io_consumer_output_data_hi_lo_hi_hi = cat(remapVecData[23], remapVecData[22]) node io_consumer_output_data_hi_lo_hi = cat(io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo) node io_consumer_output_data_hi_lo = cat(io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo) node io_consumer_output_data_hi_hi_lo_lo = cat(remapVecData[25], remapVecData[24]) node io_consumer_output_data_hi_hi_lo_hi = cat(remapVecData[27], remapVecData[26]) node io_consumer_output_data_hi_hi_lo = cat(io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo) node io_consumer_output_data_hi_hi_hi_lo = cat(remapVecData[29], remapVecData[28]) node io_consumer_output_data_hi_hi_hi_hi = cat(remapVecData[31], remapVecData[30]) node io_consumer_output_data_hi_hi_hi = cat(io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo) node io_consumer_output_data_hi_hi = cat(io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo) node io_consumer_output_data_hi = cat(io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo) node _io_consumer_output_data_T = cat(io_consumer_output_data_hi, io_consumer_output_data_lo) connect io.consumer.output_data, _io_consumer_output_data_T node _count_valids_T = add(remapVecValids[0], remapVecValids[1]) node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2]) node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3]) node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4]) node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5]) node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6]) node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7]) node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8]) node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9]) node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10]) node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11]) node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12]) node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13]) node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14]) node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15]) node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16]) node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17]) node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18]) node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19]) node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20]) node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21]) node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22]) node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23]) node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24]) node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25]) node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26]) node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27]) node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28]) node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29]) node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30]) node count_valids = add(_count_valids_T_29, remapVecValids[31]) node enough_data = neq(count_valids, UInt<1>(0h0)) connect io.consumer.available_output_bytes, count_valids connect io.consumer.output_last_chunk, UInt<1>(0h0) node _T_4294 = and(io.consumer.output_ready, enough_data) when _T_4294 : regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_4295 = asUInt(reset) node _T_4296 = eq(_T_4295, UInt<1>(0h0)) when _T_4296 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_66 node _T_4297 = asUInt(reset) node _T_4298 = eq(_T_4297, UInt<1>(0h0)) when _T_4298 : printf(clock, UInt<1>(0h1), "lrb READ: bytesread %d\n", io.consumer.user_consumed_bytes) : printf_67 regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_4299 = asUInt(reset) node _T_4300 = eq(_T_4299, UInt<1>(0h0)) when _T_4300 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_68 node _T_4301 = asUInt(reset) node _T_4302 = eq(_T_4301, UInt<1>(0h0)) when _T_4302 : printf(clock, UInt<1>(0h1), "lrb read data: 0x%x\n", io.consumer.output_data) : printf_69 connect io.consumer.output_valid, enough_data node _remapVecReadys_0_T = lt(UInt<1>(0h0), io.consumer.user_consumed_bytes) node _remapVecReadys_0_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_1) connect remapVecReadys[0], _remapVecReadys_0_T_2 node _remapVecReadys_1_T = lt(UInt<1>(0h1), io.consumer.user_consumed_bytes) node _remapVecReadys_1_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_1) connect remapVecReadys[1], _remapVecReadys_1_T_2 node _remapVecReadys_2_T = lt(UInt<2>(0h2), io.consumer.user_consumed_bytes) node _remapVecReadys_2_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_1) connect remapVecReadys[2], _remapVecReadys_2_T_2 node _remapVecReadys_3_T = lt(UInt<2>(0h3), io.consumer.user_consumed_bytes) node _remapVecReadys_3_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_1) connect remapVecReadys[3], _remapVecReadys_3_T_2 node _remapVecReadys_4_T = lt(UInt<3>(0h4), io.consumer.user_consumed_bytes) node _remapVecReadys_4_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_1) connect remapVecReadys[4], _remapVecReadys_4_T_2 node _remapVecReadys_5_T = lt(UInt<3>(0h5), io.consumer.user_consumed_bytes) node _remapVecReadys_5_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_1) connect remapVecReadys[5], _remapVecReadys_5_T_2 node _remapVecReadys_6_T = lt(UInt<3>(0h6), io.consumer.user_consumed_bytes) node _remapVecReadys_6_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_1) connect remapVecReadys[6], _remapVecReadys_6_T_2 node _remapVecReadys_7_T = lt(UInt<3>(0h7), io.consumer.user_consumed_bytes) node _remapVecReadys_7_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_1) connect remapVecReadys[7], _remapVecReadys_7_T_2 node _remapVecReadys_8_T = lt(UInt<4>(0h8), io.consumer.user_consumed_bytes) node _remapVecReadys_8_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_1) connect remapVecReadys[8], _remapVecReadys_8_T_2 node _remapVecReadys_9_T = lt(UInt<4>(0h9), io.consumer.user_consumed_bytes) node _remapVecReadys_9_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_1) connect remapVecReadys[9], _remapVecReadys_9_T_2 node _remapVecReadys_10_T = lt(UInt<4>(0ha), io.consumer.user_consumed_bytes) node _remapVecReadys_10_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_1) connect remapVecReadys[10], _remapVecReadys_10_T_2 node _remapVecReadys_11_T = lt(UInt<4>(0hb), io.consumer.user_consumed_bytes) node _remapVecReadys_11_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_1) connect remapVecReadys[11], _remapVecReadys_11_T_2 node _remapVecReadys_12_T = lt(UInt<4>(0hc), io.consumer.user_consumed_bytes) node _remapVecReadys_12_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_1) connect remapVecReadys[12], _remapVecReadys_12_T_2 node _remapVecReadys_13_T = lt(UInt<4>(0hd), io.consumer.user_consumed_bytes) node _remapVecReadys_13_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_1) connect remapVecReadys[13], _remapVecReadys_13_T_2 node _remapVecReadys_14_T = lt(UInt<4>(0he), io.consumer.user_consumed_bytes) node _remapVecReadys_14_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_1) connect remapVecReadys[14], _remapVecReadys_14_T_2 node _remapVecReadys_15_T = lt(UInt<4>(0hf), io.consumer.user_consumed_bytes) node _remapVecReadys_15_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_1) connect remapVecReadys[15], _remapVecReadys_15_T_2 node _remapVecReadys_16_T = lt(UInt<5>(0h10), io.consumer.user_consumed_bytes) node _remapVecReadys_16_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_1) connect remapVecReadys[16], _remapVecReadys_16_T_2 node _remapVecReadys_17_T = lt(UInt<5>(0h11), io.consumer.user_consumed_bytes) node _remapVecReadys_17_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_1) connect remapVecReadys[17], _remapVecReadys_17_T_2 node _remapVecReadys_18_T = lt(UInt<5>(0h12), io.consumer.user_consumed_bytes) node _remapVecReadys_18_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_1) connect remapVecReadys[18], _remapVecReadys_18_T_2 node _remapVecReadys_19_T = lt(UInt<5>(0h13), io.consumer.user_consumed_bytes) node _remapVecReadys_19_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_1) connect remapVecReadys[19], _remapVecReadys_19_T_2 node _remapVecReadys_20_T = lt(UInt<5>(0h14), io.consumer.user_consumed_bytes) node _remapVecReadys_20_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_1) connect remapVecReadys[20], _remapVecReadys_20_T_2 node _remapVecReadys_21_T = lt(UInt<5>(0h15), io.consumer.user_consumed_bytes) node _remapVecReadys_21_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_1) connect remapVecReadys[21], _remapVecReadys_21_T_2 node _remapVecReadys_22_T = lt(UInt<5>(0h16), io.consumer.user_consumed_bytes) node _remapVecReadys_22_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_1) connect remapVecReadys[22], _remapVecReadys_22_T_2 node _remapVecReadys_23_T = lt(UInt<5>(0h17), io.consumer.user_consumed_bytes) node _remapVecReadys_23_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_1) connect remapVecReadys[23], _remapVecReadys_23_T_2 node _remapVecReadys_24_T = lt(UInt<5>(0h18), io.consumer.user_consumed_bytes) node _remapVecReadys_24_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_1) connect remapVecReadys[24], _remapVecReadys_24_T_2 node _remapVecReadys_25_T = lt(UInt<5>(0h19), io.consumer.user_consumed_bytes) node _remapVecReadys_25_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_1) connect remapVecReadys[25], _remapVecReadys_25_T_2 node _remapVecReadys_26_T = lt(UInt<5>(0h1a), io.consumer.user_consumed_bytes) node _remapVecReadys_26_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_1) connect remapVecReadys[26], _remapVecReadys_26_T_2 node _remapVecReadys_27_T = lt(UInt<5>(0h1b), io.consumer.user_consumed_bytes) node _remapVecReadys_27_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_1) connect remapVecReadys[27], _remapVecReadys_27_T_2 node _remapVecReadys_28_T = lt(UInt<5>(0h1c), io.consumer.user_consumed_bytes) node _remapVecReadys_28_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_1) connect remapVecReadys[28], _remapVecReadys_28_T_2 node _remapVecReadys_29_T = lt(UInt<5>(0h1d), io.consumer.user_consumed_bytes) node _remapVecReadys_29_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_1) connect remapVecReadys[29], _remapVecReadys_29_T_2 node _remapVecReadys_30_T = lt(UInt<5>(0h1e), io.consumer.user_consumed_bytes) node _remapVecReadys_30_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_1) connect remapVecReadys[30], _remapVecReadys_30_T_2 node _remapVecReadys_31_T = lt(UInt<5>(0h1f), io.consumer.user_consumed_bytes) node _remapVecReadys_31_T_1 = and(io.consumer.output_ready, enough_data) node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_1) connect remapVecReadys[31], _remapVecReadys_31_T_2 node _T_4303 = and(io.consumer.output_ready, enough_data) when _T_4303 : node _read_start_index_T = add(read_start_index, io.consumer.user_consumed_bytes) node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20)) connect read_start_index, _read_start_index_T_1

module ZstdCompressorLitRotBuf_2( // @[ZstdLitRotBuf.scala:152:7] input clock, // @[ZstdLitRotBuf.scala:152:7] input reset, // @[ZstdLitRotBuf.scala:152:7] output io_memwrites_in_ready, // @[ZstdLitRotBuf.scala:153:14] input io_memwrites_in_valid, // @[ZstdLitRotBuf.scala:153:14] input [255:0] io_memwrites_in_bits_data, // @[ZstdLitRotBuf.scala:153:14] input io_memwrites_in_bits_end_of_message, // @[ZstdLitRotBuf.scala:153:14] input [5:0] io_consumer_user_consumed_bytes, // @[ZstdLitRotBuf.scala:153:14] output [5:0] io_consumer_available_output_bytes, // @[ZstdLitRotBuf.scala:153:14] output io_consumer_output_valid, // @[ZstdLitRotBuf.scala:153:14] input io_consumer_output_ready, // @[ZstdLitRotBuf.scala:153:14] output [255:0] io_consumer_output_data // @[ZstdLitRotBuf.scala:153:14] ); wire _Queue10_UInt8_31_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_31_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_31_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_30_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_30_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_30_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_29_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_29_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_29_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_28_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_28_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_28_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_27_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_27_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_27_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_26_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_26_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_26_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_25_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_25_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_25_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_24_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_24_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_24_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_23_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_23_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_23_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_22_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_22_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_22_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_21_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_21_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_21_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_20_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_20_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_20_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_19_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_19_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_19_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_18_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_18_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_18_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_17_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_17_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_17_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_16_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_16_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_16_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_15_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_15_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_15_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_14_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_14_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_14_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_13_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_13_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_13_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_12_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_12_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_12_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_11_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_11_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_11_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_10_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_10_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_10_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_9_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_9_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_9_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_8_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_8_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_7_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_7_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_7_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_6_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_6_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_6_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_5_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_5_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_5_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_4_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_4_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_4_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_3_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_3_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_3_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_2_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_2_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_2_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_1_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_1_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_1_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52] wire _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52] wire [7:0] _Queue10_UInt8_io_deq_bits; // @[ZstdLitRotBuf.scala:173:52] wire _incoming_writes_Q_io_deq_valid; // @[ZstdLitRotBuf.scala:158:33] wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[ZstdLitRotBuf.scala:158:33] wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[ZstdLitRotBuf.scala:158:33] wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdLitRotBuf.scala:158:33] wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[ZstdLitRotBuf.scala:152:7] wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[ZstdLitRotBuf.scala:152:7] wire io_memwrites_in_bits_end_of_message_0 = io_memwrites_in_bits_end_of_message; // @[ZstdLitRotBuf.scala:152:7] wire [5:0] io_consumer_user_consumed_bytes_0 = io_consumer_user_consumed_bytes; // @[ZstdLitRotBuf.scala:152:7] wire io_consumer_output_ready_0 = io_consumer_output_ready; // @[ZstdLitRotBuf.scala:152:7] wire [5:0] io_memwrites_in_bits_validbytes = 6'h1; // @[ZstdLitRotBuf.scala:152:7] wire io_consumer_output_last_chunk = 1'h0; // @[ZstdLitRotBuf.scala:152:7] wire enough_data; // @[ZstdLitRotBuf.scala:251:34] wire [255:0] _io_consumer_output_data_T; // @[ZstdLitRotBuf.scala:246:33] wire io_memwrites_in_ready_0; // @[ZstdLitRotBuf.scala:152:7] wire [5:0] io_consumer_available_output_bytes_0; // @[ZstdLitRotBuf.scala:152:7] wire io_consumer_output_valid_0; // @[ZstdLitRotBuf.scala:152:7] wire [255:0] io_consumer_output_data_0; // @[ZstdLitRotBuf.scala:152:7] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [5:0] write_start_index; // @[ZstdLitRotBuf.scala:172:34] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[ZstdLitRotBuf.scala:172:34, :182:34] wire [6:0] _GEN = _idx_T % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx = _GEN[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_0 = _idx_T_1 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_1 = _GEN_0[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_1 = _idx_T_2 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_2 = _GEN_1[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_2 = _idx_T_3 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_3 = _GEN_2[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_3 = _idx_T_4 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_4 = _GEN_3[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_4 = _idx_T_5 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_5 = _GEN_4[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_5 = _idx_T_6 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_6 = _GEN_5[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_6 = _idx_T_7 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_7 = _GEN_6[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_7 = _idx_T_8 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_8 = _GEN_7[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_8 = _idx_T_9 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_9 = _GEN_8[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_9 = _idx_T_10 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_10 = _GEN_9[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_10 = _idx_T_11 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_11 = _GEN_10[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_11 = _idx_T_12 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_12 = _GEN_11[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_12 = _idx_T_13 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_13 = _GEN_12[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_13 = _idx_T_14 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_14 = _GEN_13[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_14 = _idx_T_15 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_15 = _GEN_14[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_15 = _idx_T_16 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_16 = _GEN_15[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_16 = _idx_T_17 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_17 = _GEN_16[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_17 = _idx_T_18 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_18 = _GEN_17[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_18 = _idx_T_19 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_19 = _GEN_18[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_19 = _idx_T_20 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_20 = _GEN_19[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_20 = _idx_T_21 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_21 = _GEN_20[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_21 = _idx_T_22 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_22 = _GEN_21[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_22 = _idx_T_23 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_23 = _GEN_22[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_23 = _idx_T_24 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_24 = _GEN_23[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_24 = _idx_T_25 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_25 = _GEN_24[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_25 = _idx_T_26 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_26 = _GEN_25[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_26 = _idx_T_27 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_27 = _GEN_26[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_27 = _idx_T_28 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_28 = _GEN_27[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_28 = _idx_T_29 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_29 = _GEN_28[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_29 = _idx_T_30 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_30 = _GEN_29[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[ZstdLitRotBuf.scala:182:34] wire [6:0] _GEN_30 = _idx_T_31 % 7'h20; // @[ZstdLitRotBuf.scala:182:{34,48}] wire [5:0] idx_31 = _GEN_30[5:0]; // @[ZstdLitRotBuf.scala:182:48] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdLitRotBuf.scala:158:33, :182:34, :190:47] wire [6:0] _GEN_31 = wrap_len_index_wide % 7'h20; // @[ZstdLitRotBuf.scala:190:47, :191:48] wire [5:0] wrap_len_index_end = _GEN_31[5:0]; // @[ZstdLitRotBuf.scala:191:48] wire wrapped = |(wrap_len_index_wide[6:5]); // @[ZstdLitRotBuf.scala:190:47, :192:37] wire _all_queues_ready_T = _Queue10_UInt8_io_enq_ready & _Queue10_UInt8_1_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue10_UInt8_2_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue10_UInt8_3_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue10_UInt8_4_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue10_UInt8_5_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue10_UInt8_6_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue10_UInt8_7_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue10_UInt8_8_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue10_UInt8_9_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue10_UInt8_10_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue10_UInt8_11_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue10_UInt8_12_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue10_UInt8_13_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue10_UInt8_14_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue10_UInt8_15_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue10_UInt8_16_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue10_UInt8_17_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue10_UInt8_18_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue10_UInt8_19_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue10_UInt8_20_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue10_UInt8_21_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue10_UInt8_22_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue10_UInt8_23_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue10_UInt8_24_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue10_UInt8_25_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue10_UInt8_26_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue10_UInt8_27_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue10_UInt8_28_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue10_UInt8_29_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue10_UInt8_30_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue10_UInt8_31_io_enq_ready; // @[ZstdLitRotBuf.scala:173:52, :194:68] wire _T_3140 = _incoming_writes_Q_io_deq_valid & all_queues_ready; // @[Misc.scala:29:18] wire _GEN_32 = write_start_index == 6'h0; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T = _GEN_32; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_3; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_3 = _GEN_32; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_1 = |wrap_len_index_end; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_2 = _use_this_queue_T | _use_this_queue_T_1; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_4 = |wrap_len_index_end; // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_33 = write_start_index < 6'h2; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_6; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_6 = _GEN_33; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_9; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_9 = _GEN_33; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_7 = |(wrap_len_index_end[5:1]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 | _use_this_queue_T_7; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_10 = |(wrap_len_index_end[5:1]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_34 = write_start_index < 6'h3; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_12; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_12 = _GEN_34; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_15; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_15 = _GEN_34; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_35 = wrap_len_index_end > 6'h2; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_13; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_13 = _GEN_35; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_16; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_16 = _GEN_35; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 | _use_this_queue_T_13; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_36 = write_start_index < 6'h4; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_18; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_18 = _GEN_36; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_21; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_21 = _GEN_36; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_19 = |(wrap_len_index_end[5:2]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 | _use_this_queue_T_19; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_22 = |(wrap_len_index_end[5:2]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_37 = write_start_index < 6'h5; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_24; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_24 = _GEN_37; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_27; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_27 = _GEN_37; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_38 = wrap_len_index_end > 6'h4; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_25; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_25 = _GEN_38; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_28; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_28 = _GEN_38; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 | _use_this_queue_T_25; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_39 = write_start_index < 6'h6; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_30; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_30 = _GEN_39; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_33; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_33 = _GEN_39; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_40 = wrap_len_index_end > 6'h5; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_31; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_31 = _GEN_40; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_34; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_34 = _GEN_40; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_41 = write_start_index < 6'h7; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_36; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_36 = _GEN_41; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_39; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_39 = _GEN_41; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_42 = wrap_len_index_end > 6'h6; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_37; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_37 = _GEN_42; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_40; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_40 = _GEN_42; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 | _use_this_queue_T_37; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_43 = write_start_index < 6'h8; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_42; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_42 = _GEN_43; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_45; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_45 = _GEN_43; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_43 = |(wrap_len_index_end[5:3]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 | _use_this_queue_T_43; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_46 = |(wrap_len_index_end[5:3]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_44 = write_start_index < 6'h9; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_48; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_48 = _GEN_44; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_51; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_51 = _GEN_44; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_45 = wrap_len_index_end > 6'h8; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_49; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_49 = _GEN_45; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_52; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_52 = _GEN_45; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 | _use_this_queue_T_49; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_46 = write_start_index < 6'hA; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_54; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_54 = _GEN_46; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_57; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_57 = _GEN_46; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_47 = wrap_len_index_end > 6'h9; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_55; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_55 = _GEN_47; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_58; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_58 = _GEN_47; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 | _use_this_queue_T_55; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_48 = write_start_index < 6'hB; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_60; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_60 = _GEN_48; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_63; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_63 = _GEN_48; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_49 = wrap_len_index_end > 6'hA; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_61; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_61 = _GEN_49; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_64; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_64 = _GEN_49; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 | _use_this_queue_T_61; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_50 = write_start_index < 6'hC; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_66; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_66 = _GEN_50; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_69; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_69 = _GEN_50; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_51 = wrap_len_index_end > 6'hB; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_67; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_67 = _GEN_51; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_70; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_70 = _GEN_51; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 | _use_this_queue_T_67; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_52 = write_start_index < 6'hD; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_72; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_72 = _GEN_52; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_75; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_75 = _GEN_52; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_53 = wrap_len_index_end > 6'hC; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_73; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_73 = _GEN_53; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_76; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_76 = _GEN_53; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_54 = write_start_index < 6'hE; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_78; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_78 = _GEN_54; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_81; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_81 = _GEN_54; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_55 = wrap_len_index_end > 6'hD; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_79; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_79 = _GEN_55; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_82; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_82 = _GEN_55; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 | _use_this_queue_T_79; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_56 = write_start_index < 6'hF; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_84; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_84 = _GEN_56; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_87; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_87 = _GEN_56; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_57 = wrap_len_index_end > 6'hE; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_85; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_85 = _GEN_57; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_88; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_88 = _GEN_57; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 | _use_this_queue_T_85; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_58 = write_start_index < 6'h10; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_90; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_90 = _GEN_58; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_93; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_93 = _GEN_58; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _use_this_queue_T_91 = |(wrap_len_index_end[5:4]); // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 | _use_this_queue_T_91; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_94 = |(wrap_len_index_end[5:4]); // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_59 = write_start_index < 6'h11; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_96; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_96 = _GEN_59; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_99; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_99 = _GEN_59; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_60 = wrap_len_index_end > 6'h10; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_97; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_97 = _GEN_60; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_100; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_100 = _GEN_60; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 | _use_this_queue_T_97; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_61 = write_start_index < 6'h12; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_102; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_102 = _GEN_61; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_105; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_105 = _GEN_61; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_62 = wrap_len_index_end > 6'h11; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_103; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_103 = _GEN_62; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_106; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_106 = _GEN_62; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 | _use_this_queue_T_103; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_63 = write_start_index < 6'h13; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_108; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_108 = _GEN_63; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_111; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_111 = _GEN_63; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_64 = wrap_len_index_end > 6'h12; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_109; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_109 = _GEN_64; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_112; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_112 = _GEN_64; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 | _use_this_queue_T_109; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_65 = write_start_index < 6'h14; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_114; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_114 = _GEN_65; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_117; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_117 = _GEN_65; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_66 = wrap_len_index_end > 6'h13; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_115; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_115 = _GEN_66; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_118; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_118 = _GEN_66; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_67 = write_start_index < 6'h15; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_120; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_120 = _GEN_67; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_123; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_123 = _GEN_67; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_68 = wrap_len_index_end > 6'h14; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_121; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_121 = _GEN_68; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_124; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_124 = _GEN_68; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 | _use_this_queue_T_121; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_69 = write_start_index < 6'h16; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_126; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_126 = _GEN_69; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_129; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_129 = _GEN_69; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_70 = wrap_len_index_end > 6'h15; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_127; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_127 = _GEN_70; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_130; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_130 = _GEN_70; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 | _use_this_queue_T_127; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_71 = write_start_index < 6'h17; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_132; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_132 = _GEN_71; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_135; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_135 = _GEN_71; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_72 = wrap_len_index_end > 6'h16; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_133; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_133 = _GEN_72; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_136; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_136 = _GEN_72; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 | _use_this_queue_T_133; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_73 = write_start_index < 6'h18; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_138; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_138 = _GEN_73; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_141; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_141 = _GEN_73; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_74 = wrap_len_index_end > 6'h17; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_139; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_139 = _GEN_74; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_142; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_142 = _GEN_74; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 | _use_this_queue_T_139; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_75 = write_start_index < 6'h19; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_144; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_144 = _GEN_75; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_147; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_147 = _GEN_75; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_76 = wrap_len_index_end > 6'h18; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_145; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_145 = _GEN_76; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_148; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_148 = _GEN_76; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 | _use_this_queue_T_145; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_77 = write_start_index < 6'h1A; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_150; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_150 = _GEN_77; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_153; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_153 = _GEN_77; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_78 = wrap_len_index_end > 6'h19; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_151; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_151 = _GEN_78; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_154; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_154 = _GEN_78; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 | _use_this_queue_T_151; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_79 = write_start_index < 6'h1B; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_156; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_156 = _GEN_79; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_159; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_159 = _GEN_79; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_80 = wrap_len_index_end > 6'h1A; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_157; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_157 = _GEN_80; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_160; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_160 = _GEN_80; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_81 = write_start_index < 6'h1C; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_162; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_162 = _GEN_81; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_165; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_165 = _GEN_81; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_82 = wrap_len_index_end > 6'h1B; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_163; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_163 = _GEN_82; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_166; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_166 = _GEN_82; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 | _use_this_queue_T_163; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_83 = write_start_index < 6'h1D; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_168; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_168 = _GEN_83; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_171; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_171 = _GEN_83; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_84 = wrap_len_index_end > 6'h1C; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_169; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_169 = _GEN_84; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_172; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_172 = _GEN_84; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 | _use_this_queue_T_169; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_85 = write_start_index < 6'h1E; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_174; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_174 = _GEN_85; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_177; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_177 = _GEN_85; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_86 = wrap_len_index_end > 6'h1D; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_175; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_175 = _GEN_86; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_178; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_178 = _GEN_86; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 | _use_this_queue_T_175; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _GEN_87 = write_start_index < 6'h1F; // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_180; // @[ZstdLitRotBuf.scala:210:41] assign _use_this_queue_T_180 = _GEN_87; // @[ZstdLitRotBuf.scala:210:41] wire _use_this_queue_T_183; // @[ZstdLitRotBuf.scala:211:41] assign _use_this_queue_T_183 = _GEN_87; // @[ZstdLitRotBuf.scala:210:41, :211:41] wire _GEN_88 = wrap_len_index_end > 6'h1E; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_181; // @[ZstdLitRotBuf.scala:210:77] assign _use_this_queue_T_181 = _GEN_88; // @[ZstdLitRotBuf.scala:210:77] wire _use_this_queue_T_184; // @[ZstdLitRotBuf.scala:211:77] assign _use_this_queue_T_184 = _GEN_88; // @[ZstdLitRotBuf.scala:210:77, :211:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 | _use_this_queue_T_181; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[ZstdLitRotBuf.scala:172:34, :210:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[ZstdLitRotBuf.scala:191:48, :210:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[ZstdLitRotBuf.scala:191:48, :210:77, :211:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 | _use_this_queue_T_187; // @[ZstdLitRotBuf.scala:210:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[ZstdLitRotBuf.scala:172:34, :210:41, :211:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[ZstdLitRotBuf.scala:211:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[ZstdLitRotBuf.scala:192:37, :209:29, :210:63, :211:63] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[ZstdLitRotBuf.scala:222:33] wire [7:0] remapVecData_0; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_1; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_2; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_3; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_4; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_5; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_6; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_7; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_8; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_9; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_10; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_11; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_12; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_13; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_14; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_15; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_16; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_17; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_18; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_19; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_20; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_21; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_22; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_23; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_24; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_25; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_26; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_27; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_28; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_29; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_30; // @[ZstdLitRotBuf.scala:225:26] wire [7:0] remapVecData_31; // @[ZstdLitRotBuf.scala:225:26] wire remapVecValids_0; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_1; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_2; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_3; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_4; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_5; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_6; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_7; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_8; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_9; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_10; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_11; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_12; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_13; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_14; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_15; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_16; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_17; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_18; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_19; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_20; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_21; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_22; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_23; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_24; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_25; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_26; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_27; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_28; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_29; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_30; // @[ZstdLitRotBuf.scala:226:28] wire remapVecValids_31; // @[ZstdLitRotBuf.scala:226:28] wire _remapVecReadys_0_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_1_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_2_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_3_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_4_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_5_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_6_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_7_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_8_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_9_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_10_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_11_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_12_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_13_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_14_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_15_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_16_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_17_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_18_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_19_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_20_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_21_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_22_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_23_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_24_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_25_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_26_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_27_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_28_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_29_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_30_T_2; // @[ZstdLitRotBuf.scala:270:78] wire _remapVecReadys_31_T_2; // @[ZstdLitRotBuf.scala:270:78] wire remapVecReadys_0; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_1; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_2; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_3; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_4; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_5; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_6; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_7; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_8; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_9; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_10; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_11; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_12; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_13; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_14; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_15; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_16; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_17; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_18; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_19; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_20; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_21; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_22; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_23; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_24; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_25; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_26; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_27; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_28; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_29; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_30; // @[ZstdLitRotBuf.scala:227:28] wire remapVecReadys_31; // @[ZstdLitRotBuf.scala:227:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[ZstdLitRotBuf.scala:222:33, :237:33] wire [6:0] _GEN_89 = _remapindex_T % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex = _GEN_89[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3270 = remapindex == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3271 = remapindex == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3272 = remapindex == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3273 = remapindex == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3274 = remapindex == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3275 = remapindex == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3276 = remapindex == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3277 = remapindex == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3278 = remapindex == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3279 = remapindex == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3280 = remapindex == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3281 = remapindex == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3282 = remapindex == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3283 = remapindex == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3284 = remapindex == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3285 = remapindex == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3286 = remapindex == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3287 = remapindex == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3288 = remapindex == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3289 = remapindex == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3290 = remapindex == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3291 = remapindex == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3292 = remapindex == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3293 = remapindex == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3294 = remapindex == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3295 = remapindex == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3296 = remapindex == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3297 = remapindex == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3298 = remapindex == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3299 = remapindex == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3300 = remapindex == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3301 = remapindex == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_0 = _T_3301 ? _Queue10_UInt8_31_io_deq_bits : _T_3300 ? _Queue10_UInt8_30_io_deq_bits : _T_3299 ? _Queue10_UInt8_29_io_deq_bits : _T_3298 ? _Queue10_UInt8_28_io_deq_bits : _T_3297 ? _Queue10_UInt8_27_io_deq_bits : _T_3296 ? _Queue10_UInt8_26_io_deq_bits : _T_3295 ? _Queue10_UInt8_25_io_deq_bits : _T_3294 ? _Queue10_UInt8_24_io_deq_bits : _T_3293 ? _Queue10_UInt8_23_io_deq_bits : _T_3292 ? _Queue10_UInt8_22_io_deq_bits : _T_3291 ? _Queue10_UInt8_21_io_deq_bits : _T_3290 ? _Queue10_UInt8_20_io_deq_bits : _T_3289 ? _Queue10_UInt8_19_io_deq_bits : _T_3288 ? _Queue10_UInt8_18_io_deq_bits : _T_3287 ? _Queue10_UInt8_17_io_deq_bits : _T_3286 ? _Queue10_UInt8_16_io_deq_bits : _T_3285 ? _Queue10_UInt8_15_io_deq_bits : _T_3284 ? _Queue10_UInt8_14_io_deq_bits : _T_3283 ? _Queue10_UInt8_13_io_deq_bits : _T_3282 ? _Queue10_UInt8_12_io_deq_bits : _T_3281 ? _Queue10_UInt8_11_io_deq_bits : _T_3280 ? _Queue10_UInt8_10_io_deq_bits : _T_3279 ? _Queue10_UInt8_9_io_deq_bits : _T_3278 ? _Queue10_UInt8_8_io_deq_bits : _T_3277 ? _Queue10_UInt8_7_io_deq_bits : _T_3276 ? _Queue10_UInt8_6_io_deq_bits : _T_3275 ? _Queue10_UInt8_5_io_deq_bits : _T_3274 ? _Queue10_UInt8_4_io_deq_bits : _T_3273 ? _Queue10_UInt8_3_io_deq_bits : _T_3272 ? _Queue10_UInt8_2_io_deq_bits : _T_3271 ? _Queue10_UInt8_1_io_deq_bits : _T_3270 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_0 = _T_3301 ? _Queue10_UInt8_31_io_deq_valid : _T_3300 ? _Queue10_UInt8_30_io_deq_valid : _T_3299 ? _Queue10_UInt8_29_io_deq_valid : _T_3298 ? _Queue10_UInt8_28_io_deq_valid : _T_3297 ? _Queue10_UInt8_27_io_deq_valid : _T_3296 ? _Queue10_UInt8_26_io_deq_valid : _T_3295 ? _Queue10_UInt8_25_io_deq_valid : _T_3294 ? _Queue10_UInt8_24_io_deq_valid : _T_3293 ? _Queue10_UInt8_23_io_deq_valid : _T_3292 ? _Queue10_UInt8_22_io_deq_valid : _T_3291 ? _Queue10_UInt8_21_io_deq_valid : _T_3290 ? _Queue10_UInt8_20_io_deq_valid : _T_3289 ? _Queue10_UInt8_19_io_deq_valid : _T_3288 ? _Queue10_UInt8_18_io_deq_valid : _T_3287 ? _Queue10_UInt8_17_io_deq_valid : _T_3286 ? _Queue10_UInt8_16_io_deq_valid : _T_3285 ? _Queue10_UInt8_15_io_deq_valid : _T_3284 ? _Queue10_UInt8_14_io_deq_valid : _T_3283 ? _Queue10_UInt8_13_io_deq_valid : _T_3282 ? _Queue10_UInt8_12_io_deq_valid : _T_3281 ? _Queue10_UInt8_11_io_deq_valid : _T_3280 ? _Queue10_UInt8_10_io_deq_valid : _T_3279 ? _Queue10_UInt8_9_io_deq_valid : _T_3278 ? _Queue10_UInt8_8_io_deq_valid : _T_3277 ? _Queue10_UInt8_7_io_deq_valid : _T_3276 ? _Queue10_UInt8_6_io_deq_valid : _T_3275 ? _Queue10_UInt8_5_io_deq_valid : _T_3274 ? _Queue10_UInt8_4_io_deq_valid : _T_3273 ? _Queue10_UInt8_3_io_deq_valid : _T_3272 ? _Queue10_UInt8_2_io_deq_valid : _T_3271 ? _Queue10_UInt8_1_io_deq_valid : _T_3270 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_90 = _remapindex_T_1 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_1 = _GEN_90[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3302 = remapindex_1 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3303 = remapindex_1 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3304 = remapindex_1 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3305 = remapindex_1 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3306 = remapindex_1 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3307 = remapindex_1 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3308 = remapindex_1 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3309 = remapindex_1 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3310 = remapindex_1 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3311 = remapindex_1 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3312 = remapindex_1 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3313 = remapindex_1 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3314 = remapindex_1 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3315 = remapindex_1 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3316 = remapindex_1 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3317 = remapindex_1 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3318 = remapindex_1 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3319 = remapindex_1 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3320 = remapindex_1 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3321 = remapindex_1 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3322 = remapindex_1 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3323 = remapindex_1 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3324 = remapindex_1 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3325 = remapindex_1 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3326 = remapindex_1 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3327 = remapindex_1 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3328 = remapindex_1 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3329 = remapindex_1 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3330 = remapindex_1 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3331 = remapindex_1 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3332 = remapindex_1 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3333 = remapindex_1 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_1 = _T_3333 ? _Queue10_UInt8_31_io_deq_bits : _T_3332 ? _Queue10_UInt8_30_io_deq_bits : _T_3331 ? _Queue10_UInt8_29_io_deq_bits : _T_3330 ? _Queue10_UInt8_28_io_deq_bits : _T_3329 ? _Queue10_UInt8_27_io_deq_bits : _T_3328 ? _Queue10_UInt8_26_io_deq_bits : _T_3327 ? _Queue10_UInt8_25_io_deq_bits : _T_3326 ? _Queue10_UInt8_24_io_deq_bits : _T_3325 ? _Queue10_UInt8_23_io_deq_bits : _T_3324 ? _Queue10_UInt8_22_io_deq_bits : _T_3323 ? _Queue10_UInt8_21_io_deq_bits : _T_3322 ? _Queue10_UInt8_20_io_deq_bits : _T_3321 ? _Queue10_UInt8_19_io_deq_bits : _T_3320 ? _Queue10_UInt8_18_io_deq_bits : _T_3319 ? _Queue10_UInt8_17_io_deq_bits : _T_3318 ? _Queue10_UInt8_16_io_deq_bits : _T_3317 ? _Queue10_UInt8_15_io_deq_bits : _T_3316 ? _Queue10_UInt8_14_io_deq_bits : _T_3315 ? _Queue10_UInt8_13_io_deq_bits : _T_3314 ? _Queue10_UInt8_12_io_deq_bits : _T_3313 ? _Queue10_UInt8_11_io_deq_bits : _T_3312 ? _Queue10_UInt8_10_io_deq_bits : _T_3311 ? _Queue10_UInt8_9_io_deq_bits : _T_3310 ? _Queue10_UInt8_8_io_deq_bits : _T_3309 ? _Queue10_UInt8_7_io_deq_bits : _T_3308 ? _Queue10_UInt8_6_io_deq_bits : _T_3307 ? _Queue10_UInt8_5_io_deq_bits : _T_3306 ? _Queue10_UInt8_4_io_deq_bits : _T_3305 ? _Queue10_UInt8_3_io_deq_bits : _T_3304 ? _Queue10_UInt8_2_io_deq_bits : _T_3303 ? _Queue10_UInt8_1_io_deq_bits : _T_3302 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_1 = _T_3333 ? _Queue10_UInt8_31_io_deq_valid : _T_3332 ? _Queue10_UInt8_30_io_deq_valid : _T_3331 ? _Queue10_UInt8_29_io_deq_valid : _T_3330 ? _Queue10_UInt8_28_io_deq_valid : _T_3329 ? _Queue10_UInt8_27_io_deq_valid : _T_3328 ? _Queue10_UInt8_26_io_deq_valid : _T_3327 ? _Queue10_UInt8_25_io_deq_valid : _T_3326 ? _Queue10_UInt8_24_io_deq_valid : _T_3325 ? _Queue10_UInt8_23_io_deq_valid : _T_3324 ? _Queue10_UInt8_22_io_deq_valid : _T_3323 ? _Queue10_UInt8_21_io_deq_valid : _T_3322 ? _Queue10_UInt8_20_io_deq_valid : _T_3321 ? _Queue10_UInt8_19_io_deq_valid : _T_3320 ? _Queue10_UInt8_18_io_deq_valid : _T_3319 ? _Queue10_UInt8_17_io_deq_valid : _T_3318 ? _Queue10_UInt8_16_io_deq_valid : _T_3317 ? _Queue10_UInt8_15_io_deq_valid : _T_3316 ? _Queue10_UInt8_14_io_deq_valid : _T_3315 ? _Queue10_UInt8_13_io_deq_valid : _T_3314 ? _Queue10_UInt8_12_io_deq_valid : _T_3313 ? _Queue10_UInt8_11_io_deq_valid : _T_3312 ? _Queue10_UInt8_10_io_deq_valid : _T_3311 ? _Queue10_UInt8_9_io_deq_valid : _T_3310 ? _Queue10_UInt8_8_io_deq_valid : _T_3309 ? _Queue10_UInt8_7_io_deq_valid : _T_3308 ? _Queue10_UInt8_6_io_deq_valid : _T_3307 ? _Queue10_UInt8_5_io_deq_valid : _T_3306 ? _Queue10_UInt8_4_io_deq_valid : _T_3305 ? _Queue10_UInt8_3_io_deq_valid : _T_3304 ? _Queue10_UInt8_2_io_deq_valid : _T_3303 ? _Queue10_UInt8_1_io_deq_valid : _T_3302 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_91 = _remapindex_T_2 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_2 = _GEN_91[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3334 = remapindex_2 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3335 = remapindex_2 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3336 = remapindex_2 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3337 = remapindex_2 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3338 = remapindex_2 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3339 = remapindex_2 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3340 = remapindex_2 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3341 = remapindex_2 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3342 = remapindex_2 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3343 = remapindex_2 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3344 = remapindex_2 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3345 = remapindex_2 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3346 = remapindex_2 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3347 = remapindex_2 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3348 = remapindex_2 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3349 = remapindex_2 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3350 = remapindex_2 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3351 = remapindex_2 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3352 = remapindex_2 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3353 = remapindex_2 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3354 = remapindex_2 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3355 = remapindex_2 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3356 = remapindex_2 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3357 = remapindex_2 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3358 = remapindex_2 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3359 = remapindex_2 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3360 = remapindex_2 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3361 = remapindex_2 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3362 = remapindex_2 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3363 = remapindex_2 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3364 = remapindex_2 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3365 = remapindex_2 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_2 = _T_3365 ? _Queue10_UInt8_31_io_deq_bits : _T_3364 ? _Queue10_UInt8_30_io_deq_bits : _T_3363 ? _Queue10_UInt8_29_io_deq_bits : _T_3362 ? _Queue10_UInt8_28_io_deq_bits : _T_3361 ? _Queue10_UInt8_27_io_deq_bits : _T_3360 ? _Queue10_UInt8_26_io_deq_bits : _T_3359 ? _Queue10_UInt8_25_io_deq_bits : _T_3358 ? _Queue10_UInt8_24_io_deq_bits : _T_3357 ? _Queue10_UInt8_23_io_deq_bits : _T_3356 ? _Queue10_UInt8_22_io_deq_bits : _T_3355 ? _Queue10_UInt8_21_io_deq_bits : _T_3354 ? _Queue10_UInt8_20_io_deq_bits : _T_3353 ? _Queue10_UInt8_19_io_deq_bits : _T_3352 ? _Queue10_UInt8_18_io_deq_bits : _T_3351 ? _Queue10_UInt8_17_io_deq_bits : _T_3350 ? _Queue10_UInt8_16_io_deq_bits : _T_3349 ? _Queue10_UInt8_15_io_deq_bits : _T_3348 ? _Queue10_UInt8_14_io_deq_bits : _T_3347 ? _Queue10_UInt8_13_io_deq_bits : _T_3346 ? _Queue10_UInt8_12_io_deq_bits : _T_3345 ? _Queue10_UInt8_11_io_deq_bits : _T_3344 ? _Queue10_UInt8_10_io_deq_bits : _T_3343 ? _Queue10_UInt8_9_io_deq_bits : _T_3342 ? _Queue10_UInt8_8_io_deq_bits : _T_3341 ? _Queue10_UInt8_7_io_deq_bits : _T_3340 ? _Queue10_UInt8_6_io_deq_bits : _T_3339 ? _Queue10_UInt8_5_io_deq_bits : _T_3338 ? _Queue10_UInt8_4_io_deq_bits : _T_3337 ? _Queue10_UInt8_3_io_deq_bits : _T_3336 ? _Queue10_UInt8_2_io_deq_bits : _T_3335 ? _Queue10_UInt8_1_io_deq_bits : _T_3334 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_2 = _T_3365 ? _Queue10_UInt8_31_io_deq_valid : _T_3364 ? _Queue10_UInt8_30_io_deq_valid : _T_3363 ? _Queue10_UInt8_29_io_deq_valid : _T_3362 ? _Queue10_UInt8_28_io_deq_valid : _T_3361 ? _Queue10_UInt8_27_io_deq_valid : _T_3360 ? _Queue10_UInt8_26_io_deq_valid : _T_3359 ? _Queue10_UInt8_25_io_deq_valid : _T_3358 ? _Queue10_UInt8_24_io_deq_valid : _T_3357 ? _Queue10_UInt8_23_io_deq_valid : _T_3356 ? _Queue10_UInt8_22_io_deq_valid : _T_3355 ? _Queue10_UInt8_21_io_deq_valid : _T_3354 ? _Queue10_UInt8_20_io_deq_valid : _T_3353 ? _Queue10_UInt8_19_io_deq_valid : _T_3352 ? _Queue10_UInt8_18_io_deq_valid : _T_3351 ? _Queue10_UInt8_17_io_deq_valid : _T_3350 ? _Queue10_UInt8_16_io_deq_valid : _T_3349 ? _Queue10_UInt8_15_io_deq_valid : _T_3348 ? _Queue10_UInt8_14_io_deq_valid : _T_3347 ? _Queue10_UInt8_13_io_deq_valid : _T_3346 ? _Queue10_UInt8_12_io_deq_valid : _T_3345 ? _Queue10_UInt8_11_io_deq_valid : _T_3344 ? _Queue10_UInt8_10_io_deq_valid : _T_3343 ? _Queue10_UInt8_9_io_deq_valid : _T_3342 ? _Queue10_UInt8_8_io_deq_valid : _T_3341 ? _Queue10_UInt8_7_io_deq_valid : _T_3340 ? _Queue10_UInt8_6_io_deq_valid : _T_3339 ? _Queue10_UInt8_5_io_deq_valid : _T_3338 ? _Queue10_UInt8_4_io_deq_valid : _T_3337 ? _Queue10_UInt8_3_io_deq_valid : _T_3336 ? _Queue10_UInt8_2_io_deq_valid : _T_3335 ? _Queue10_UInt8_1_io_deq_valid : _T_3334 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_92 = _remapindex_T_3 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_3 = _GEN_92[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3366 = remapindex_3 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3367 = remapindex_3 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3368 = remapindex_3 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3369 = remapindex_3 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3370 = remapindex_3 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3371 = remapindex_3 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3372 = remapindex_3 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3373 = remapindex_3 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3374 = remapindex_3 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3375 = remapindex_3 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3376 = remapindex_3 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3377 = remapindex_3 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3378 = remapindex_3 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3379 = remapindex_3 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3380 = remapindex_3 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3381 = remapindex_3 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3382 = remapindex_3 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3383 = remapindex_3 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3384 = remapindex_3 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3385 = remapindex_3 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3386 = remapindex_3 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3387 = remapindex_3 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3388 = remapindex_3 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3389 = remapindex_3 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3390 = remapindex_3 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3391 = remapindex_3 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3392 = remapindex_3 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3393 = remapindex_3 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3394 = remapindex_3 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3395 = remapindex_3 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3396 = remapindex_3 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3397 = remapindex_3 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_3 = _T_3397 ? _Queue10_UInt8_31_io_deq_bits : _T_3396 ? _Queue10_UInt8_30_io_deq_bits : _T_3395 ? _Queue10_UInt8_29_io_deq_bits : _T_3394 ? _Queue10_UInt8_28_io_deq_bits : _T_3393 ? _Queue10_UInt8_27_io_deq_bits : _T_3392 ? _Queue10_UInt8_26_io_deq_bits : _T_3391 ? _Queue10_UInt8_25_io_deq_bits : _T_3390 ? _Queue10_UInt8_24_io_deq_bits : _T_3389 ? _Queue10_UInt8_23_io_deq_bits : _T_3388 ? _Queue10_UInt8_22_io_deq_bits : _T_3387 ? _Queue10_UInt8_21_io_deq_bits : _T_3386 ? _Queue10_UInt8_20_io_deq_bits : _T_3385 ? _Queue10_UInt8_19_io_deq_bits : _T_3384 ? _Queue10_UInt8_18_io_deq_bits : _T_3383 ? _Queue10_UInt8_17_io_deq_bits : _T_3382 ? _Queue10_UInt8_16_io_deq_bits : _T_3381 ? _Queue10_UInt8_15_io_deq_bits : _T_3380 ? _Queue10_UInt8_14_io_deq_bits : _T_3379 ? _Queue10_UInt8_13_io_deq_bits : _T_3378 ? _Queue10_UInt8_12_io_deq_bits : _T_3377 ? _Queue10_UInt8_11_io_deq_bits : _T_3376 ? _Queue10_UInt8_10_io_deq_bits : _T_3375 ? _Queue10_UInt8_9_io_deq_bits : _T_3374 ? _Queue10_UInt8_8_io_deq_bits : _T_3373 ? _Queue10_UInt8_7_io_deq_bits : _T_3372 ? _Queue10_UInt8_6_io_deq_bits : _T_3371 ? _Queue10_UInt8_5_io_deq_bits : _T_3370 ? _Queue10_UInt8_4_io_deq_bits : _T_3369 ? _Queue10_UInt8_3_io_deq_bits : _T_3368 ? _Queue10_UInt8_2_io_deq_bits : _T_3367 ? _Queue10_UInt8_1_io_deq_bits : _T_3366 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_3 = _T_3397 ? _Queue10_UInt8_31_io_deq_valid : _T_3396 ? _Queue10_UInt8_30_io_deq_valid : _T_3395 ? _Queue10_UInt8_29_io_deq_valid : _T_3394 ? _Queue10_UInt8_28_io_deq_valid : _T_3393 ? _Queue10_UInt8_27_io_deq_valid : _T_3392 ? _Queue10_UInt8_26_io_deq_valid : _T_3391 ? _Queue10_UInt8_25_io_deq_valid : _T_3390 ? _Queue10_UInt8_24_io_deq_valid : _T_3389 ? _Queue10_UInt8_23_io_deq_valid : _T_3388 ? _Queue10_UInt8_22_io_deq_valid : _T_3387 ? _Queue10_UInt8_21_io_deq_valid : _T_3386 ? _Queue10_UInt8_20_io_deq_valid : _T_3385 ? _Queue10_UInt8_19_io_deq_valid : _T_3384 ? _Queue10_UInt8_18_io_deq_valid : _T_3383 ? _Queue10_UInt8_17_io_deq_valid : _T_3382 ? _Queue10_UInt8_16_io_deq_valid : _T_3381 ? _Queue10_UInt8_15_io_deq_valid : _T_3380 ? _Queue10_UInt8_14_io_deq_valid : _T_3379 ? _Queue10_UInt8_13_io_deq_valid : _T_3378 ? _Queue10_UInt8_12_io_deq_valid : _T_3377 ? _Queue10_UInt8_11_io_deq_valid : _T_3376 ? _Queue10_UInt8_10_io_deq_valid : _T_3375 ? _Queue10_UInt8_9_io_deq_valid : _T_3374 ? _Queue10_UInt8_8_io_deq_valid : _T_3373 ? _Queue10_UInt8_7_io_deq_valid : _T_3372 ? _Queue10_UInt8_6_io_deq_valid : _T_3371 ? _Queue10_UInt8_5_io_deq_valid : _T_3370 ? _Queue10_UInt8_4_io_deq_valid : _T_3369 ? _Queue10_UInt8_3_io_deq_valid : _T_3368 ? _Queue10_UInt8_2_io_deq_valid : _T_3367 ? _Queue10_UInt8_1_io_deq_valid : _T_3366 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_93 = _remapindex_T_4 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_4 = _GEN_93[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3398 = remapindex_4 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3399 = remapindex_4 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3400 = remapindex_4 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3401 = remapindex_4 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3402 = remapindex_4 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3403 = remapindex_4 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3404 = remapindex_4 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3405 = remapindex_4 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3406 = remapindex_4 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3407 = remapindex_4 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3408 = remapindex_4 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3409 = remapindex_4 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3410 = remapindex_4 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3411 = remapindex_4 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3412 = remapindex_4 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3413 = remapindex_4 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3414 = remapindex_4 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3415 = remapindex_4 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3416 = remapindex_4 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3417 = remapindex_4 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3418 = remapindex_4 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3419 = remapindex_4 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3420 = remapindex_4 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3421 = remapindex_4 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3422 = remapindex_4 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3423 = remapindex_4 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3424 = remapindex_4 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3425 = remapindex_4 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3426 = remapindex_4 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3427 = remapindex_4 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3428 = remapindex_4 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3429 = remapindex_4 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_4 = _T_3429 ? _Queue10_UInt8_31_io_deq_bits : _T_3428 ? _Queue10_UInt8_30_io_deq_bits : _T_3427 ? _Queue10_UInt8_29_io_deq_bits : _T_3426 ? _Queue10_UInt8_28_io_deq_bits : _T_3425 ? _Queue10_UInt8_27_io_deq_bits : _T_3424 ? _Queue10_UInt8_26_io_deq_bits : _T_3423 ? _Queue10_UInt8_25_io_deq_bits : _T_3422 ? _Queue10_UInt8_24_io_deq_bits : _T_3421 ? _Queue10_UInt8_23_io_deq_bits : _T_3420 ? _Queue10_UInt8_22_io_deq_bits : _T_3419 ? _Queue10_UInt8_21_io_deq_bits : _T_3418 ? _Queue10_UInt8_20_io_deq_bits : _T_3417 ? _Queue10_UInt8_19_io_deq_bits : _T_3416 ? _Queue10_UInt8_18_io_deq_bits : _T_3415 ? _Queue10_UInt8_17_io_deq_bits : _T_3414 ? _Queue10_UInt8_16_io_deq_bits : _T_3413 ? _Queue10_UInt8_15_io_deq_bits : _T_3412 ? _Queue10_UInt8_14_io_deq_bits : _T_3411 ? _Queue10_UInt8_13_io_deq_bits : _T_3410 ? _Queue10_UInt8_12_io_deq_bits : _T_3409 ? _Queue10_UInt8_11_io_deq_bits : _T_3408 ? _Queue10_UInt8_10_io_deq_bits : _T_3407 ? _Queue10_UInt8_9_io_deq_bits : _T_3406 ? _Queue10_UInt8_8_io_deq_bits : _T_3405 ? _Queue10_UInt8_7_io_deq_bits : _T_3404 ? _Queue10_UInt8_6_io_deq_bits : _T_3403 ? _Queue10_UInt8_5_io_deq_bits : _T_3402 ? _Queue10_UInt8_4_io_deq_bits : _T_3401 ? _Queue10_UInt8_3_io_deq_bits : _T_3400 ? _Queue10_UInt8_2_io_deq_bits : _T_3399 ? _Queue10_UInt8_1_io_deq_bits : _T_3398 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_4 = _T_3429 ? _Queue10_UInt8_31_io_deq_valid : _T_3428 ? _Queue10_UInt8_30_io_deq_valid : _T_3427 ? _Queue10_UInt8_29_io_deq_valid : _T_3426 ? _Queue10_UInt8_28_io_deq_valid : _T_3425 ? _Queue10_UInt8_27_io_deq_valid : _T_3424 ? _Queue10_UInt8_26_io_deq_valid : _T_3423 ? _Queue10_UInt8_25_io_deq_valid : _T_3422 ? _Queue10_UInt8_24_io_deq_valid : _T_3421 ? _Queue10_UInt8_23_io_deq_valid : _T_3420 ? _Queue10_UInt8_22_io_deq_valid : _T_3419 ? _Queue10_UInt8_21_io_deq_valid : _T_3418 ? _Queue10_UInt8_20_io_deq_valid : _T_3417 ? _Queue10_UInt8_19_io_deq_valid : _T_3416 ? _Queue10_UInt8_18_io_deq_valid : _T_3415 ? _Queue10_UInt8_17_io_deq_valid : _T_3414 ? _Queue10_UInt8_16_io_deq_valid : _T_3413 ? _Queue10_UInt8_15_io_deq_valid : _T_3412 ? _Queue10_UInt8_14_io_deq_valid : _T_3411 ? _Queue10_UInt8_13_io_deq_valid : _T_3410 ? _Queue10_UInt8_12_io_deq_valid : _T_3409 ? _Queue10_UInt8_11_io_deq_valid : _T_3408 ? _Queue10_UInt8_10_io_deq_valid : _T_3407 ? _Queue10_UInt8_9_io_deq_valid : _T_3406 ? _Queue10_UInt8_8_io_deq_valid : _T_3405 ? _Queue10_UInt8_7_io_deq_valid : _T_3404 ? _Queue10_UInt8_6_io_deq_valid : _T_3403 ? _Queue10_UInt8_5_io_deq_valid : _T_3402 ? _Queue10_UInt8_4_io_deq_valid : _T_3401 ? _Queue10_UInt8_3_io_deq_valid : _T_3400 ? _Queue10_UInt8_2_io_deq_valid : _T_3399 ? _Queue10_UInt8_1_io_deq_valid : _T_3398 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_94 = _remapindex_T_5 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_5 = _GEN_94[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3430 = remapindex_5 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3431 = remapindex_5 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3432 = remapindex_5 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3433 = remapindex_5 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3434 = remapindex_5 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3435 = remapindex_5 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3436 = remapindex_5 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3437 = remapindex_5 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3438 = remapindex_5 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3439 = remapindex_5 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3440 = remapindex_5 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3441 = remapindex_5 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3442 = remapindex_5 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3443 = remapindex_5 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3444 = remapindex_5 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3445 = remapindex_5 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3446 = remapindex_5 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3447 = remapindex_5 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3448 = remapindex_5 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3449 = remapindex_5 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3450 = remapindex_5 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3451 = remapindex_5 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3452 = remapindex_5 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3453 = remapindex_5 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3454 = remapindex_5 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3455 = remapindex_5 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3456 = remapindex_5 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3457 = remapindex_5 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3458 = remapindex_5 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3459 = remapindex_5 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3460 = remapindex_5 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3461 = remapindex_5 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_5 = _T_3461 ? _Queue10_UInt8_31_io_deq_bits : _T_3460 ? _Queue10_UInt8_30_io_deq_bits : _T_3459 ? _Queue10_UInt8_29_io_deq_bits : _T_3458 ? _Queue10_UInt8_28_io_deq_bits : _T_3457 ? _Queue10_UInt8_27_io_deq_bits : _T_3456 ? _Queue10_UInt8_26_io_deq_bits : _T_3455 ? _Queue10_UInt8_25_io_deq_bits : _T_3454 ? _Queue10_UInt8_24_io_deq_bits : _T_3453 ? _Queue10_UInt8_23_io_deq_bits : _T_3452 ? _Queue10_UInt8_22_io_deq_bits : _T_3451 ? _Queue10_UInt8_21_io_deq_bits : _T_3450 ? _Queue10_UInt8_20_io_deq_bits : _T_3449 ? _Queue10_UInt8_19_io_deq_bits : _T_3448 ? _Queue10_UInt8_18_io_deq_bits : _T_3447 ? _Queue10_UInt8_17_io_deq_bits : _T_3446 ? _Queue10_UInt8_16_io_deq_bits : _T_3445 ? _Queue10_UInt8_15_io_deq_bits : _T_3444 ? _Queue10_UInt8_14_io_deq_bits : _T_3443 ? _Queue10_UInt8_13_io_deq_bits : _T_3442 ? _Queue10_UInt8_12_io_deq_bits : _T_3441 ? _Queue10_UInt8_11_io_deq_bits : _T_3440 ? _Queue10_UInt8_10_io_deq_bits : _T_3439 ? _Queue10_UInt8_9_io_deq_bits : _T_3438 ? _Queue10_UInt8_8_io_deq_bits : _T_3437 ? _Queue10_UInt8_7_io_deq_bits : _T_3436 ? _Queue10_UInt8_6_io_deq_bits : _T_3435 ? _Queue10_UInt8_5_io_deq_bits : _T_3434 ? _Queue10_UInt8_4_io_deq_bits : _T_3433 ? _Queue10_UInt8_3_io_deq_bits : _T_3432 ? _Queue10_UInt8_2_io_deq_bits : _T_3431 ? _Queue10_UInt8_1_io_deq_bits : _T_3430 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_5 = _T_3461 ? _Queue10_UInt8_31_io_deq_valid : _T_3460 ? _Queue10_UInt8_30_io_deq_valid : _T_3459 ? _Queue10_UInt8_29_io_deq_valid : _T_3458 ? _Queue10_UInt8_28_io_deq_valid : _T_3457 ? _Queue10_UInt8_27_io_deq_valid : _T_3456 ? _Queue10_UInt8_26_io_deq_valid : _T_3455 ? _Queue10_UInt8_25_io_deq_valid : _T_3454 ? _Queue10_UInt8_24_io_deq_valid : _T_3453 ? _Queue10_UInt8_23_io_deq_valid : _T_3452 ? _Queue10_UInt8_22_io_deq_valid : _T_3451 ? _Queue10_UInt8_21_io_deq_valid : _T_3450 ? _Queue10_UInt8_20_io_deq_valid : _T_3449 ? _Queue10_UInt8_19_io_deq_valid : _T_3448 ? _Queue10_UInt8_18_io_deq_valid : _T_3447 ? _Queue10_UInt8_17_io_deq_valid : _T_3446 ? _Queue10_UInt8_16_io_deq_valid : _T_3445 ? _Queue10_UInt8_15_io_deq_valid : _T_3444 ? _Queue10_UInt8_14_io_deq_valid : _T_3443 ? _Queue10_UInt8_13_io_deq_valid : _T_3442 ? _Queue10_UInt8_12_io_deq_valid : _T_3441 ? _Queue10_UInt8_11_io_deq_valid : _T_3440 ? _Queue10_UInt8_10_io_deq_valid : _T_3439 ? _Queue10_UInt8_9_io_deq_valid : _T_3438 ? _Queue10_UInt8_8_io_deq_valid : _T_3437 ? _Queue10_UInt8_7_io_deq_valid : _T_3436 ? _Queue10_UInt8_6_io_deq_valid : _T_3435 ? _Queue10_UInt8_5_io_deq_valid : _T_3434 ? _Queue10_UInt8_4_io_deq_valid : _T_3433 ? _Queue10_UInt8_3_io_deq_valid : _T_3432 ? _Queue10_UInt8_2_io_deq_valid : _T_3431 ? _Queue10_UInt8_1_io_deq_valid : _T_3430 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_95 = _remapindex_T_6 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_6 = _GEN_95[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3462 = remapindex_6 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3463 = remapindex_6 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3464 = remapindex_6 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3465 = remapindex_6 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3466 = remapindex_6 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3467 = remapindex_6 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3468 = remapindex_6 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3469 = remapindex_6 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3470 = remapindex_6 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3471 = remapindex_6 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3472 = remapindex_6 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3473 = remapindex_6 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3474 = remapindex_6 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3475 = remapindex_6 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3476 = remapindex_6 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3477 = remapindex_6 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3478 = remapindex_6 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3479 = remapindex_6 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3480 = remapindex_6 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3481 = remapindex_6 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3482 = remapindex_6 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3483 = remapindex_6 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3484 = remapindex_6 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3485 = remapindex_6 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3486 = remapindex_6 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3487 = remapindex_6 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3488 = remapindex_6 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3489 = remapindex_6 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3490 = remapindex_6 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3491 = remapindex_6 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3492 = remapindex_6 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3493 = remapindex_6 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_6 = _T_3493 ? _Queue10_UInt8_31_io_deq_bits : _T_3492 ? _Queue10_UInt8_30_io_deq_bits : _T_3491 ? _Queue10_UInt8_29_io_deq_bits : _T_3490 ? _Queue10_UInt8_28_io_deq_bits : _T_3489 ? _Queue10_UInt8_27_io_deq_bits : _T_3488 ? _Queue10_UInt8_26_io_deq_bits : _T_3487 ? _Queue10_UInt8_25_io_deq_bits : _T_3486 ? _Queue10_UInt8_24_io_deq_bits : _T_3485 ? _Queue10_UInt8_23_io_deq_bits : _T_3484 ? _Queue10_UInt8_22_io_deq_bits : _T_3483 ? _Queue10_UInt8_21_io_deq_bits : _T_3482 ? _Queue10_UInt8_20_io_deq_bits : _T_3481 ? _Queue10_UInt8_19_io_deq_bits : _T_3480 ? _Queue10_UInt8_18_io_deq_bits : _T_3479 ? _Queue10_UInt8_17_io_deq_bits : _T_3478 ? _Queue10_UInt8_16_io_deq_bits : _T_3477 ? _Queue10_UInt8_15_io_deq_bits : _T_3476 ? _Queue10_UInt8_14_io_deq_bits : _T_3475 ? _Queue10_UInt8_13_io_deq_bits : _T_3474 ? _Queue10_UInt8_12_io_deq_bits : _T_3473 ? _Queue10_UInt8_11_io_deq_bits : _T_3472 ? _Queue10_UInt8_10_io_deq_bits : _T_3471 ? _Queue10_UInt8_9_io_deq_bits : _T_3470 ? _Queue10_UInt8_8_io_deq_bits : _T_3469 ? _Queue10_UInt8_7_io_deq_bits : _T_3468 ? _Queue10_UInt8_6_io_deq_bits : _T_3467 ? _Queue10_UInt8_5_io_deq_bits : _T_3466 ? _Queue10_UInt8_4_io_deq_bits : _T_3465 ? _Queue10_UInt8_3_io_deq_bits : _T_3464 ? _Queue10_UInt8_2_io_deq_bits : _T_3463 ? _Queue10_UInt8_1_io_deq_bits : _T_3462 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_6 = _T_3493 ? _Queue10_UInt8_31_io_deq_valid : _T_3492 ? _Queue10_UInt8_30_io_deq_valid : _T_3491 ? _Queue10_UInt8_29_io_deq_valid : _T_3490 ? _Queue10_UInt8_28_io_deq_valid : _T_3489 ? _Queue10_UInt8_27_io_deq_valid : _T_3488 ? _Queue10_UInt8_26_io_deq_valid : _T_3487 ? _Queue10_UInt8_25_io_deq_valid : _T_3486 ? _Queue10_UInt8_24_io_deq_valid : _T_3485 ? _Queue10_UInt8_23_io_deq_valid : _T_3484 ? _Queue10_UInt8_22_io_deq_valid : _T_3483 ? _Queue10_UInt8_21_io_deq_valid : _T_3482 ? _Queue10_UInt8_20_io_deq_valid : _T_3481 ? _Queue10_UInt8_19_io_deq_valid : _T_3480 ? _Queue10_UInt8_18_io_deq_valid : _T_3479 ? _Queue10_UInt8_17_io_deq_valid : _T_3478 ? _Queue10_UInt8_16_io_deq_valid : _T_3477 ? _Queue10_UInt8_15_io_deq_valid : _T_3476 ? _Queue10_UInt8_14_io_deq_valid : _T_3475 ? _Queue10_UInt8_13_io_deq_valid : _T_3474 ? _Queue10_UInt8_12_io_deq_valid : _T_3473 ? _Queue10_UInt8_11_io_deq_valid : _T_3472 ? _Queue10_UInt8_10_io_deq_valid : _T_3471 ? _Queue10_UInt8_9_io_deq_valid : _T_3470 ? _Queue10_UInt8_8_io_deq_valid : _T_3469 ? _Queue10_UInt8_7_io_deq_valid : _T_3468 ? _Queue10_UInt8_6_io_deq_valid : _T_3467 ? _Queue10_UInt8_5_io_deq_valid : _T_3466 ? _Queue10_UInt8_4_io_deq_valid : _T_3465 ? _Queue10_UInt8_3_io_deq_valid : _T_3464 ? _Queue10_UInt8_2_io_deq_valid : _T_3463 ? _Queue10_UInt8_1_io_deq_valid : _T_3462 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_96 = _remapindex_T_7 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_7 = _GEN_96[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3494 = remapindex_7 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3495 = remapindex_7 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3496 = remapindex_7 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3497 = remapindex_7 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3498 = remapindex_7 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3499 = remapindex_7 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3500 = remapindex_7 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3501 = remapindex_7 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3502 = remapindex_7 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3503 = remapindex_7 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3504 = remapindex_7 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3505 = remapindex_7 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3506 = remapindex_7 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3507 = remapindex_7 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3508 = remapindex_7 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3509 = remapindex_7 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3510 = remapindex_7 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3511 = remapindex_7 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3512 = remapindex_7 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3513 = remapindex_7 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3514 = remapindex_7 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3515 = remapindex_7 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3516 = remapindex_7 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3517 = remapindex_7 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3518 = remapindex_7 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3519 = remapindex_7 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3520 = remapindex_7 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3521 = remapindex_7 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3522 = remapindex_7 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3523 = remapindex_7 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3524 = remapindex_7 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3525 = remapindex_7 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_7 = _T_3525 ? _Queue10_UInt8_31_io_deq_bits : _T_3524 ? _Queue10_UInt8_30_io_deq_bits : _T_3523 ? _Queue10_UInt8_29_io_deq_bits : _T_3522 ? _Queue10_UInt8_28_io_deq_bits : _T_3521 ? _Queue10_UInt8_27_io_deq_bits : _T_3520 ? _Queue10_UInt8_26_io_deq_bits : _T_3519 ? _Queue10_UInt8_25_io_deq_bits : _T_3518 ? _Queue10_UInt8_24_io_deq_bits : _T_3517 ? _Queue10_UInt8_23_io_deq_bits : _T_3516 ? _Queue10_UInt8_22_io_deq_bits : _T_3515 ? _Queue10_UInt8_21_io_deq_bits : _T_3514 ? _Queue10_UInt8_20_io_deq_bits : _T_3513 ? _Queue10_UInt8_19_io_deq_bits : _T_3512 ? _Queue10_UInt8_18_io_deq_bits : _T_3511 ? _Queue10_UInt8_17_io_deq_bits : _T_3510 ? _Queue10_UInt8_16_io_deq_bits : _T_3509 ? _Queue10_UInt8_15_io_deq_bits : _T_3508 ? _Queue10_UInt8_14_io_deq_bits : _T_3507 ? _Queue10_UInt8_13_io_deq_bits : _T_3506 ? _Queue10_UInt8_12_io_deq_bits : _T_3505 ? _Queue10_UInt8_11_io_deq_bits : _T_3504 ? _Queue10_UInt8_10_io_deq_bits : _T_3503 ? _Queue10_UInt8_9_io_deq_bits : _T_3502 ? _Queue10_UInt8_8_io_deq_bits : _T_3501 ? _Queue10_UInt8_7_io_deq_bits : _T_3500 ? _Queue10_UInt8_6_io_deq_bits : _T_3499 ? _Queue10_UInt8_5_io_deq_bits : _T_3498 ? _Queue10_UInt8_4_io_deq_bits : _T_3497 ? _Queue10_UInt8_3_io_deq_bits : _T_3496 ? _Queue10_UInt8_2_io_deq_bits : _T_3495 ? _Queue10_UInt8_1_io_deq_bits : _T_3494 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_7 = _T_3525 ? _Queue10_UInt8_31_io_deq_valid : _T_3524 ? _Queue10_UInt8_30_io_deq_valid : _T_3523 ? _Queue10_UInt8_29_io_deq_valid : _T_3522 ? _Queue10_UInt8_28_io_deq_valid : _T_3521 ? _Queue10_UInt8_27_io_deq_valid : _T_3520 ? _Queue10_UInt8_26_io_deq_valid : _T_3519 ? _Queue10_UInt8_25_io_deq_valid : _T_3518 ? _Queue10_UInt8_24_io_deq_valid : _T_3517 ? _Queue10_UInt8_23_io_deq_valid : _T_3516 ? _Queue10_UInt8_22_io_deq_valid : _T_3515 ? _Queue10_UInt8_21_io_deq_valid : _T_3514 ? _Queue10_UInt8_20_io_deq_valid : _T_3513 ? _Queue10_UInt8_19_io_deq_valid : _T_3512 ? _Queue10_UInt8_18_io_deq_valid : _T_3511 ? _Queue10_UInt8_17_io_deq_valid : _T_3510 ? _Queue10_UInt8_16_io_deq_valid : _T_3509 ? _Queue10_UInt8_15_io_deq_valid : _T_3508 ? _Queue10_UInt8_14_io_deq_valid : _T_3507 ? _Queue10_UInt8_13_io_deq_valid : _T_3506 ? _Queue10_UInt8_12_io_deq_valid : _T_3505 ? _Queue10_UInt8_11_io_deq_valid : _T_3504 ? _Queue10_UInt8_10_io_deq_valid : _T_3503 ? _Queue10_UInt8_9_io_deq_valid : _T_3502 ? _Queue10_UInt8_8_io_deq_valid : _T_3501 ? _Queue10_UInt8_7_io_deq_valid : _T_3500 ? _Queue10_UInt8_6_io_deq_valid : _T_3499 ? _Queue10_UInt8_5_io_deq_valid : _T_3498 ? _Queue10_UInt8_4_io_deq_valid : _T_3497 ? _Queue10_UInt8_3_io_deq_valid : _T_3496 ? _Queue10_UInt8_2_io_deq_valid : _T_3495 ? _Queue10_UInt8_1_io_deq_valid : _T_3494 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_97 = _remapindex_T_8 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_8 = _GEN_97[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3526 = remapindex_8 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3527 = remapindex_8 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3528 = remapindex_8 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3529 = remapindex_8 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3530 = remapindex_8 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3531 = remapindex_8 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3532 = remapindex_8 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3533 = remapindex_8 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3534 = remapindex_8 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3535 = remapindex_8 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3536 = remapindex_8 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3537 = remapindex_8 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3538 = remapindex_8 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3539 = remapindex_8 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3540 = remapindex_8 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3541 = remapindex_8 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3542 = remapindex_8 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3543 = remapindex_8 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3544 = remapindex_8 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3545 = remapindex_8 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3546 = remapindex_8 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3547 = remapindex_8 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3548 = remapindex_8 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3549 = remapindex_8 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3550 = remapindex_8 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3551 = remapindex_8 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3552 = remapindex_8 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3553 = remapindex_8 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3554 = remapindex_8 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3555 = remapindex_8 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3556 = remapindex_8 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3557 = remapindex_8 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_8 = _T_3557 ? _Queue10_UInt8_31_io_deq_bits : _T_3556 ? _Queue10_UInt8_30_io_deq_bits : _T_3555 ? _Queue10_UInt8_29_io_deq_bits : _T_3554 ? _Queue10_UInt8_28_io_deq_bits : _T_3553 ? _Queue10_UInt8_27_io_deq_bits : _T_3552 ? _Queue10_UInt8_26_io_deq_bits : _T_3551 ? _Queue10_UInt8_25_io_deq_bits : _T_3550 ? _Queue10_UInt8_24_io_deq_bits : _T_3549 ? _Queue10_UInt8_23_io_deq_bits : _T_3548 ? _Queue10_UInt8_22_io_deq_bits : _T_3547 ? _Queue10_UInt8_21_io_deq_bits : _T_3546 ? _Queue10_UInt8_20_io_deq_bits : _T_3545 ? _Queue10_UInt8_19_io_deq_bits : _T_3544 ? _Queue10_UInt8_18_io_deq_bits : _T_3543 ? _Queue10_UInt8_17_io_deq_bits : _T_3542 ? _Queue10_UInt8_16_io_deq_bits : _T_3541 ? _Queue10_UInt8_15_io_deq_bits : _T_3540 ? _Queue10_UInt8_14_io_deq_bits : _T_3539 ? _Queue10_UInt8_13_io_deq_bits : _T_3538 ? _Queue10_UInt8_12_io_deq_bits : _T_3537 ? _Queue10_UInt8_11_io_deq_bits : _T_3536 ? _Queue10_UInt8_10_io_deq_bits : _T_3535 ? _Queue10_UInt8_9_io_deq_bits : _T_3534 ? _Queue10_UInt8_8_io_deq_bits : _T_3533 ? _Queue10_UInt8_7_io_deq_bits : _T_3532 ? _Queue10_UInt8_6_io_deq_bits : _T_3531 ? _Queue10_UInt8_5_io_deq_bits : _T_3530 ? _Queue10_UInt8_4_io_deq_bits : _T_3529 ? _Queue10_UInt8_3_io_deq_bits : _T_3528 ? _Queue10_UInt8_2_io_deq_bits : _T_3527 ? _Queue10_UInt8_1_io_deq_bits : _T_3526 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_8 = _T_3557 ? _Queue10_UInt8_31_io_deq_valid : _T_3556 ? _Queue10_UInt8_30_io_deq_valid : _T_3555 ? _Queue10_UInt8_29_io_deq_valid : _T_3554 ? _Queue10_UInt8_28_io_deq_valid : _T_3553 ? _Queue10_UInt8_27_io_deq_valid : _T_3552 ? _Queue10_UInt8_26_io_deq_valid : _T_3551 ? _Queue10_UInt8_25_io_deq_valid : _T_3550 ? _Queue10_UInt8_24_io_deq_valid : _T_3549 ? _Queue10_UInt8_23_io_deq_valid : _T_3548 ? _Queue10_UInt8_22_io_deq_valid : _T_3547 ? _Queue10_UInt8_21_io_deq_valid : _T_3546 ? _Queue10_UInt8_20_io_deq_valid : _T_3545 ? _Queue10_UInt8_19_io_deq_valid : _T_3544 ? _Queue10_UInt8_18_io_deq_valid : _T_3543 ? _Queue10_UInt8_17_io_deq_valid : _T_3542 ? _Queue10_UInt8_16_io_deq_valid : _T_3541 ? _Queue10_UInt8_15_io_deq_valid : _T_3540 ? _Queue10_UInt8_14_io_deq_valid : _T_3539 ? _Queue10_UInt8_13_io_deq_valid : _T_3538 ? _Queue10_UInt8_12_io_deq_valid : _T_3537 ? _Queue10_UInt8_11_io_deq_valid : _T_3536 ? _Queue10_UInt8_10_io_deq_valid : _T_3535 ? _Queue10_UInt8_9_io_deq_valid : _T_3534 ? _Queue10_UInt8_8_io_deq_valid : _T_3533 ? _Queue10_UInt8_7_io_deq_valid : _T_3532 ? _Queue10_UInt8_6_io_deq_valid : _T_3531 ? _Queue10_UInt8_5_io_deq_valid : _T_3530 ? _Queue10_UInt8_4_io_deq_valid : _T_3529 ? _Queue10_UInt8_3_io_deq_valid : _T_3528 ? _Queue10_UInt8_2_io_deq_valid : _T_3527 ? _Queue10_UInt8_1_io_deq_valid : _T_3526 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_98 = _remapindex_T_9 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_9 = _GEN_98[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3558 = remapindex_9 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3559 = remapindex_9 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3560 = remapindex_9 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3561 = remapindex_9 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3562 = remapindex_9 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3563 = remapindex_9 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3564 = remapindex_9 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3565 = remapindex_9 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3566 = remapindex_9 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3567 = remapindex_9 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3568 = remapindex_9 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3569 = remapindex_9 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3570 = remapindex_9 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3571 = remapindex_9 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3572 = remapindex_9 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3573 = remapindex_9 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3574 = remapindex_9 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3575 = remapindex_9 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3576 = remapindex_9 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3577 = remapindex_9 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3578 = remapindex_9 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3579 = remapindex_9 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3580 = remapindex_9 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3581 = remapindex_9 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3582 = remapindex_9 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3583 = remapindex_9 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3584 = remapindex_9 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3585 = remapindex_9 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3586 = remapindex_9 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3587 = remapindex_9 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3588 = remapindex_9 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3589 = remapindex_9 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_9 = _T_3589 ? _Queue10_UInt8_31_io_deq_bits : _T_3588 ? _Queue10_UInt8_30_io_deq_bits : _T_3587 ? _Queue10_UInt8_29_io_deq_bits : _T_3586 ? _Queue10_UInt8_28_io_deq_bits : _T_3585 ? _Queue10_UInt8_27_io_deq_bits : _T_3584 ? _Queue10_UInt8_26_io_deq_bits : _T_3583 ? _Queue10_UInt8_25_io_deq_bits : _T_3582 ? _Queue10_UInt8_24_io_deq_bits : _T_3581 ? _Queue10_UInt8_23_io_deq_bits : _T_3580 ? _Queue10_UInt8_22_io_deq_bits : _T_3579 ? _Queue10_UInt8_21_io_deq_bits : _T_3578 ? _Queue10_UInt8_20_io_deq_bits : _T_3577 ? _Queue10_UInt8_19_io_deq_bits : _T_3576 ? _Queue10_UInt8_18_io_deq_bits : _T_3575 ? _Queue10_UInt8_17_io_deq_bits : _T_3574 ? _Queue10_UInt8_16_io_deq_bits : _T_3573 ? _Queue10_UInt8_15_io_deq_bits : _T_3572 ? _Queue10_UInt8_14_io_deq_bits : _T_3571 ? _Queue10_UInt8_13_io_deq_bits : _T_3570 ? _Queue10_UInt8_12_io_deq_bits : _T_3569 ? _Queue10_UInt8_11_io_deq_bits : _T_3568 ? _Queue10_UInt8_10_io_deq_bits : _T_3567 ? _Queue10_UInt8_9_io_deq_bits : _T_3566 ? _Queue10_UInt8_8_io_deq_bits : _T_3565 ? _Queue10_UInt8_7_io_deq_bits : _T_3564 ? _Queue10_UInt8_6_io_deq_bits : _T_3563 ? _Queue10_UInt8_5_io_deq_bits : _T_3562 ? _Queue10_UInt8_4_io_deq_bits : _T_3561 ? _Queue10_UInt8_3_io_deq_bits : _T_3560 ? _Queue10_UInt8_2_io_deq_bits : _T_3559 ? _Queue10_UInt8_1_io_deq_bits : _T_3558 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_9 = _T_3589 ? _Queue10_UInt8_31_io_deq_valid : _T_3588 ? _Queue10_UInt8_30_io_deq_valid : _T_3587 ? _Queue10_UInt8_29_io_deq_valid : _T_3586 ? _Queue10_UInt8_28_io_deq_valid : _T_3585 ? _Queue10_UInt8_27_io_deq_valid : _T_3584 ? _Queue10_UInt8_26_io_deq_valid : _T_3583 ? _Queue10_UInt8_25_io_deq_valid : _T_3582 ? _Queue10_UInt8_24_io_deq_valid : _T_3581 ? _Queue10_UInt8_23_io_deq_valid : _T_3580 ? _Queue10_UInt8_22_io_deq_valid : _T_3579 ? _Queue10_UInt8_21_io_deq_valid : _T_3578 ? _Queue10_UInt8_20_io_deq_valid : _T_3577 ? _Queue10_UInt8_19_io_deq_valid : _T_3576 ? _Queue10_UInt8_18_io_deq_valid : _T_3575 ? _Queue10_UInt8_17_io_deq_valid : _T_3574 ? _Queue10_UInt8_16_io_deq_valid : _T_3573 ? _Queue10_UInt8_15_io_deq_valid : _T_3572 ? _Queue10_UInt8_14_io_deq_valid : _T_3571 ? _Queue10_UInt8_13_io_deq_valid : _T_3570 ? _Queue10_UInt8_12_io_deq_valid : _T_3569 ? _Queue10_UInt8_11_io_deq_valid : _T_3568 ? _Queue10_UInt8_10_io_deq_valid : _T_3567 ? _Queue10_UInt8_9_io_deq_valid : _T_3566 ? _Queue10_UInt8_8_io_deq_valid : _T_3565 ? _Queue10_UInt8_7_io_deq_valid : _T_3564 ? _Queue10_UInt8_6_io_deq_valid : _T_3563 ? _Queue10_UInt8_5_io_deq_valid : _T_3562 ? _Queue10_UInt8_4_io_deq_valid : _T_3561 ? _Queue10_UInt8_3_io_deq_valid : _T_3560 ? _Queue10_UInt8_2_io_deq_valid : _T_3559 ? _Queue10_UInt8_1_io_deq_valid : _T_3558 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_99 = _remapindex_T_10 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_10 = _GEN_99[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3590 = remapindex_10 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3591 = remapindex_10 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3592 = remapindex_10 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3593 = remapindex_10 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3594 = remapindex_10 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3595 = remapindex_10 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3596 = remapindex_10 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3597 = remapindex_10 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3598 = remapindex_10 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3599 = remapindex_10 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3600 = remapindex_10 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3601 = remapindex_10 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3602 = remapindex_10 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3603 = remapindex_10 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3604 = remapindex_10 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3605 = remapindex_10 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3606 = remapindex_10 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3607 = remapindex_10 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3608 = remapindex_10 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3609 = remapindex_10 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3610 = remapindex_10 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3611 = remapindex_10 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3612 = remapindex_10 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3613 = remapindex_10 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3614 = remapindex_10 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3615 = remapindex_10 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3616 = remapindex_10 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3617 = remapindex_10 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3618 = remapindex_10 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3619 = remapindex_10 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3620 = remapindex_10 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3621 = remapindex_10 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_10 = _T_3621 ? _Queue10_UInt8_31_io_deq_bits : _T_3620 ? _Queue10_UInt8_30_io_deq_bits : _T_3619 ? _Queue10_UInt8_29_io_deq_bits : _T_3618 ? _Queue10_UInt8_28_io_deq_bits : _T_3617 ? _Queue10_UInt8_27_io_deq_bits : _T_3616 ? _Queue10_UInt8_26_io_deq_bits : _T_3615 ? _Queue10_UInt8_25_io_deq_bits : _T_3614 ? _Queue10_UInt8_24_io_deq_bits : _T_3613 ? _Queue10_UInt8_23_io_deq_bits : _T_3612 ? _Queue10_UInt8_22_io_deq_bits : _T_3611 ? _Queue10_UInt8_21_io_deq_bits : _T_3610 ? _Queue10_UInt8_20_io_deq_bits : _T_3609 ? _Queue10_UInt8_19_io_deq_bits : _T_3608 ? _Queue10_UInt8_18_io_deq_bits : _T_3607 ? _Queue10_UInt8_17_io_deq_bits : _T_3606 ? _Queue10_UInt8_16_io_deq_bits : _T_3605 ? _Queue10_UInt8_15_io_deq_bits : _T_3604 ? _Queue10_UInt8_14_io_deq_bits : _T_3603 ? _Queue10_UInt8_13_io_deq_bits : _T_3602 ? _Queue10_UInt8_12_io_deq_bits : _T_3601 ? _Queue10_UInt8_11_io_deq_bits : _T_3600 ? _Queue10_UInt8_10_io_deq_bits : _T_3599 ? _Queue10_UInt8_9_io_deq_bits : _T_3598 ? _Queue10_UInt8_8_io_deq_bits : _T_3597 ? _Queue10_UInt8_7_io_deq_bits : _T_3596 ? _Queue10_UInt8_6_io_deq_bits : _T_3595 ? _Queue10_UInt8_5_io_deq_bits : _T_3594 ? _Queue10_UInt8_4_io_deq_bits : _T_3593 ? _Queue10_UInt8_3_io_deq_bits : _T_3592 ? _Queue10_UInt8_2_io_deq_bits : _T_3591 ? _Queue10_UInt8_1_io_deq_bits : _T_3590 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_10 = _T_3621 ? _Queue10_UInt8_31_io_deq_valid : _T_3620 ? _Queue10_UInt8_30_io_deq_valid : _T_3619 ? _Queue10_UInt8_29_io_deq_valid : _T_3618 ? _Queue10_UInt8_28_io_deq_valid : _T_3617 ? _Queue10_UInt8_27_io_deq_valid : _T_3616 ? _Queue10_UInt8_26_io_deq_valid : _T_3615 ? _Queue10_UInt8_25_io_deq_valid : _T_3614 ? _Queue10_UInt8_24_io_deq_valid : _T_3613 ? _Queue10_UInt8_23_io_deq_valid : _T_3612 ? _Queue10_UInt8_22_io_deq_valid : _T_3611 ? _Queue10_UInt8_21_io_deq_valid : _T_3610 ? _Queue10_UInt8_20_io_deq_valid : _T_3609 ? _Queue10_UInt8_19_io_deq_valid : _T_3608 ? _Queue10_UInt8_18_io_deq_valid : _T_3607 ? _Queue10_UInt8_17_io_deq_valid : _T_3606 ? _Queue10_UInt8_16_io_deq_valid : _T_3605 ? _Queue10_UInt8_15_io_deq_valid : _T_3604 ? _Queue10_UInt8_14_io_deq_valid : _T_3603 ? _Queue10_UInt8_13_io_deq_valid : _T_3602 ? _Queue10_UInt8_12_io_deq_valid : _T_3601 ? _Queue10_UInt8_11_io_deq_valid : _T_3600 ? _Queue10_UInt8_10_io_deq_valid : _T_3599 ? _Queue10_UInt8_9_io_deq_valid : _T_3598 ? _Queue10_UInt8_8_io_deq_valid : _T_3597 ? _Queue10_UInt8_7_io_deq_valid : _T_3596 ? _Queue10_UInt8_6_io_deq_valid : _T_3595 ? _Queue10_UInt8_5_io_deq_valid : _T_3594 ? _Queue10_UInt8_4_io_deq_valid : _T_3593 ? _Queue10_UInt8_3_io_deq_valid : _T_3592 ? _Queue10_UInt8_2_io_deq_valid : _T_3591 ? _Queue10_UInt8_1_io_deq_valid : _T_3590 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_100 = _remapindex_T_11 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_11 = _GEN_100[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3622 = remapindex_11 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3623 = remapindex_11 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3624 = remapindex_11 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3625 = remapindex_11 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3626 = remapindex_11 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3627 = remapindex_11 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3628 = remapindex_11 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3629 = remapindex_11 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3630 = remapindex_11 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3631 = remapindex_11 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3632 = remapindex_11 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3633 = remapindex_11 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3634 = remapindex_11 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3635 = remapindex_11 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3636 = remapindex_11 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3637 = remapindex_11 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3638 = remapindex_11 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3639 = remapindex_11 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3640 = remapindex_11 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3641 = remapindex_11 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3642 = remapindex_11 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3643 = remapindex_11 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3644 = remapindex_11 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3645 = remapindex_11 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3646 = remapindex_11 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3647 = remapindex_11 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3648 = remapindex_11 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3649 = remapindex_11 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3650 = remapindex_11 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3651 = remapindex_11 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3652 = remapindex_11 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3653 = remapindex_11 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_11 = _T_3653 ? _Queue10_UInt8_31_io_deq_bits : _T_3652 ? _Queue10_UInt8_30_io_deq_bits : _T_3651 ? _Queue10_UInt8_29_io_deq_bits : _T_3650 ? _Queue10_UInt8_28_io_deq_bits : _T_3649 ? _Queue10_UInt8_27_io_deq_bits : _T_3648 ? _Queue10_UInt8_26_io_deq_bits : _T_3647 ? _Queue10_UInt8_25_io_deq_bits : _T_3646 ? _Queue10_UInt8_24_io_deq_bits : _T_3645 ? _Queue10_UInt8_23_io_deq_bits : _T_3644 ? _Queue10_UInt8_22_io_deq_bits : _T_3643 ? _Queue10_UInt8_21_io_deq_bits : _T_3642 ? _Queue10_UInt8_20_io_deq_bits : _T_3641 ? _Queue10_UInt8_19_io_deq_bits : _T_3640 ? _Queue10_UInt8_18_io_deq_bits : _T_3639 ? _Queue10_UInt8_17_io_deq_bits : _T_3638 ? _Queue10_UInt8_16_io_deq_bits : _T_3637 ? _Queue10_UInt8_15_io_deq_bits : _T_3636 ? _Queue10_UInt8_14_io_deq_bits : _T_3635 ? _Queue10_UInt8_13_io_deq_bits : _T_3634 ? _Queue10_UInt8_12_io_deq_bits : _T_3633 ? _Queue10_UInt8_11_io_deq_bits : _T_3632 ? _Queue10_UInt8_10_io_deq_bits : _T_3631 ? _Queue10_UInt8_9_io_deq_bits : _T_3630 ? _Queue10_UInt8_8_io_deq_bits : _T_3629 ? _Queue10_UInt8_7_io_deq_bits : _T_3628 ? _Queue10_UInt8_6_io_deq_bits : _T_3627 ? _Queue10_UInt8_5_io_deq_bits : _T_3626 ? _Queue10_UInt8_4_io_deq_bits : _T_3625 ? _Queue10_UInt8_3_io_deq_bits : _T_3624 ? _Queue10_UInt8_2_io_deq_bits : _T_3623 ? _Queue10_UInt8_1_io_deq_bits : _T_3622 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_11 = _T_3653 ? _Queue10_UInt8_31_io_deq_valid : _T_3652 ? _Queue10_UInt8_30_io_deq_valid : _T_3651 ? _Queue10_UInt8_29_io_deq_valid : _T_3650 ? _Queue10_UInt8_28_io_deq_valid : _T_3649 ? _Queue10_UInt8_27_io_deq_valid : _T_3648 ? _Queue10_UInt8_26_io_deq_valid : _T_3647 ? _Queue10_UInt8_25_io_deq_valid : _T_3646 ? _Queue10_UInt8_24_io_deq_valid : _T_3645 ? _Queue10_UInt8_23_io_deq_valid : _T_3644 ? _Queue10_UInt8_22_io_deq_valid : _T_3643 ? _Queue10_UInt8_21_io_deq_valid : _T_3642 ? _Queue10_UInt8_20_io_deq_valid : _T_3641 ? _Queue10_UInt8_19_io_deq_valid : _T_3640 ? _Queue10_UInt8_18_io_deq_valid : _T_3639 ? _Queue10_UInt8_17_io_deq_valid : _T_3638 ? _Queue10_UInt8_16_io_deq_valid : _T_3637 ? _Queue10_UInt8_15_io_deq_valid : _T_3636 ? _Queue10_UInt8_14_io_deq_valid : _T_3635 ? _Queue10_UInt8_13_io_deq_valid : _T_3634 ? _Queue10_UInt8_12_io_deq_valid : _T_3633 ? _Queue10_UInt8_11_io_deq_valid : _T_3632 ? _Queue10_UInt8_10_io_deq_valid : _T_3631 ? _Queue10_UInt8_9_io_deq_valid : _T_3630 ? _Queue10_UInt8_8_io_deq_valid : _T_3629 ? _Queue10_UInt8_7_io_deq_valid : _T_3628 ? _Queue10_UInt8_6_io_deq_valid : _T_3627 ? _Queue10_UInt8_5_io_deq_valid : _T_3626 ? _Queue10_UInt8_4_io_deq_valid : _T_3625 ? _Queue10_UInt8_3_io_deq_valid : _T_3624 ? _Queue10_UInt8_2_io_deq_valid : _T_3623 ? _Queue10_UInt8_1_io_deq_valid : _T_3622 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_101 = _remapindex_T_12 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_12 = _GEN_101[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3654 = remapindex_12 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3655 = remapindex_12 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3656 = remapindex_12 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3657 = remapindex_12 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3658 = remapindex_12 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3659 = remapindex_12 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3660 = remapindex_12 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3661 = remapindex_12 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3662 = remapindex_12 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3663 = remapindex_12 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3664 = remapindex_12 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3665 = remapindex_12 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3666 = remapindex_12 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3667 = remapindex_12 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3668 = remapindex_12 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3669 = remapindex_12 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3670 = remapindex_12 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3671 = remapindex_12 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3672 = remapindex_12 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3673 = remapindex_12 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3674 = remapindex_12 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3675 = remapindex_12 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3676 = remapindex_12 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3677 = remapindex_12 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3678 = remapindex_12 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3679 = remapindex_12 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3680 = remapindex_12 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3681 = remapindex_12 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3682 = remapindex_12 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3683 = remapindex_12 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3684 = remapindex_12 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3685 = remapindex_12 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_12 = _T_3685 ? _Queue10_UInt8_31_io_deq_bits : _T_3684 ? _Queue10_UInt8_30_io_deq_bits : _T_3683 ? _Queue10_UInt8_29_io_deq_bits : _T_3682 ? _Queue10_UInt8_28_io_deq_bits : _T_3681 ? _Queue10_UInt8_27_io_deq_bits : _T_3680 ? _Queue10_UInt8_26_io_deq_bits : _T_3679 ? _Queue10_UInt8_25_io_deq_bits : _T_3678 ? _Queue10_UInt8_24_io_deq_bits : _T_3677 ? _Queue10_UInt8_23_io_deq_bits : _T_3676 ? _Queue10_UInt8_22_io_deq_bits : _T_3675 ? _Queue10_UInt8_21_io_deq_bits : _T_3674 ? _Queue10_UInt8_20_io_deq_bits : _T_3673 ? _Queue10_UInt8_19_io_deq_bits : _T_3672 ? _Queue10_UInt8_18_io_deq_bits : _T_3671 ? _Queue10_UInt8_17_io_deq_bits : _T_3670 ? _Queue10_UInt8_16_io_deq_bits : _T_3669 ? _Queue10_UInt8_15_io_deq_bits : _T_3668 ? _Queue10_UInt8_14_io_deq_bits : _T_3667 ? _Queue10_UInt8_13_io_deq_bits : _T_3666 ? _Queue10_UInt8_12_io_deq_bits : _T_3665 ? _Queue10_UInt8_11_io_deq_bits : _T_3664 ? _Queue10_UInt8_10_io_deq_bits : _T_3663 ? _Queue10_UInt8_9_io_deq_bits : _T_3662 ? _Queue10_UInt8_8_io_deq_bits : _T_3661 ? _Queue10_UInt8_7_io_deq_bits : _T_3660 ? _Queue10_UInt8_6_io_deq_bits : _T_3659 ? _Queue10_UInt8_5_io_deq_bits : _T_3658 ? _Queue10_UInt8_4_io_deq_bits : _T_3657 ? _Queue10_UInt8_3_io_deq_bits : _T_3656 ? _Queue10_UInt8_2_io_deq_bits : _T_3655 ? _Queue10_UInt8_1_io_deq_bits : _T_3654 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_12 = _T_3685 ? _Queue10_UInt8_31_io_deq_valid : _T_3684 ? _Queue10_UInt8_30_io_deq_valid : _T_3683 ? _Queue10_UInt8_29_io_deq_valid : _T_3682 ? _Queue10_UInt8_28_io_deq_valid : _T_3681 ? _Queue10_UInt8_27_io_deq_valid : _T_3680 ? _Queue10_UInt8_26_io_deq_valid : _T_3679 ? _Queue10_UInt8_25_io_deq_valid : _T_3678 ? _Queue10_UInt8_24_io_deq_valid : _T_3677 ? _Queue10_UInt8_23_io_deq_valid : _T_3676 ? _Queue10_UInt8_22_io_deq_valid : _T_3675 ? _Queue10_UInt8_21_io_deq_valid : _T_3674 ? _Queue10_UInt8_20_io_deq_valid : _T_3673 ? _Queue10_UInt8_19_io_deq_valid : _T_3672 ? _Queue10_UInt8_18_io_deq_valid : _T_3671 ? _Queue10_UInt8_17_io_deq_valid : _T_3670 ? _Queue10_UInt8_16_io_deq_valid : _T_3669 ? _Queue10_UInt8_15_io_deq_valid : _T_3668 ? _Queue10_UInt8_14_io_deq_valid : _T_3667 ? _Queue10_UInt8_13_io_deq_valid : _T_3666 ? _Queue10_UInt8_12_io_deq_valid : _T_3665 ? _Queue10_UInt8_11_io_deq_valid : _T_3664 ? _Queue10_UInt8_10_io_deq_valid : _T_3663 ? _Queue10_UInt8_9_io_deq_valid : _T_3662 ? _Queue10_UInt8_8_io_deq_valid : _T_3661 ? _Queue10_UInt8_7_io_deq_valid : _T_3660 ? _Queue10_UInt8_6_io_deq_valid : _T_3659 ? _Queue10_UInt8_5_io_deq_valid : _T_3658 ? _Queue10_UInt8_4_io_deq_valid : _T_3657 ? _Queue10_UInt8_3_io_deq_valid : _T_3656 ? _Queue10_UInt8_2_io_deq_valid : _T_3655 ? _Queue10_UInt8_1_io_deq_valid : _T_3654 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_102 = _remapindex_T_13 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_13 = _GEN_102[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3686 = remapindex_13 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3687 = remapindex_13 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3688 = remapindex_13 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3689 = remapindex_13 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3690 = remapindex_13 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3691 = remapindex_13 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3692 = remapindex_13 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3693 = remapindex_13 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3694 = remapindex_13 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3695 = remapindex_13 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3696 = remapindex_13 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3697 = remapindex_13 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3698 = remapindex_13 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3699 = remapindex_13 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3700 = remapindex_13 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3701 = remapindex_13 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3702 = remapindex_13 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3703 = remapindex_13 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3704 = remapindex_13 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3705 = remapindex_13 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3706 = remapindex_13 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3707 = remapindex_13 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3708 = remapindex_13 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3709 = remapindex_13 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3710 = remapindex_13 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3711 = remapindex_13 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3712 = remapindex_13 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3713 = remapindex_13 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3714 = remapindex_13 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3715 = remapindex_13 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3716 = remapindex_13 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3717 = remapindex_13 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_13 = _T_3717 ? _Queue10_UInt8_31_io_deq_bits : _T_3716 ? _Queue10_UInt8_30_io_deq_bits : _T_3715 ? _Queue10_UInt8_29_io_deq_bits : _T_3714 ? _Queue10_UInt8_28_io_deq_bits : _T_3713 ? _Queue10_UInt8_27_io_deq_bits : _T_3712 ? _Queue10_UInt8_26_io_deq_bits : _T_3711 ? _Queue10_UInt8_25_io_deq_bits : _T_3710 ? _Queue10_UInt8_24_io_deq_bits : _T_3709 ? _Queue10_UInt8_23_io_deq_bits : _T_3708 ? _Queue10_UInt8_22_io_deq_bits : _T_3707 ? _Queue10_UInt8_21_io_deq_bits : _T_3706 ? _Queue10_UInt8_20_io_deq_bits : _T_3705 ? _Queue10_UInt8_19_io_deq_bits : _T_3704 ? _Queue10_UInt8_18_io_deq_bits : _T_3703 ? _Queue10_UInt8_17_io_deq_bits : _T_3702 ? _Queue10_UInt8_16_io_deq_bits : _T_3701 ? _Queue10_UInt8_15_io_deq_bits : _T_3700 ? _Queue10_UInt8_14_io_deq_bits : _T_3699 ? _Queue10_UInt8_13_io_deq_bits : _T_3698 ? _Queue10_UInt8_12_io_deq_bits : _T_3697 ? _Queue10_UInt8_11_io_deq_bits : _T_3696 ? _Queue10_UInt8_10_io_deq_bits : _T_3695 ? _Queue10_UInt8_9_io_deq_bits : _T_3694 ? _Queue10_UInt8_8_io_deq_bits : _T_3693 ? _Queue10_UInt8_7_io_deq_bits : _T_3692 ? _Queue10_UInt8_6_io_deq_bits : _T_3691 ? _Queue10_UInt8_5_io_deq_bits : _T_3690 ? _Queue10_UInt8_4_io_deq_bits : _T_3689 ? _Queue10_UInt8_3_io_deq_bits : _T_3688 ? _Queue10_UInt8_2_io_deq_bits : _T_3687 ? _Queue10_UInt8_1_io_deq_bits : _T_3686 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_13 = _T_3717 ? _Queue10_UInt8_31_io_deq_valid : _T_3716 ? _Queue10_UInt8_30_io_deq_valid : _T_3715 ? _Queue10_UInt8_29_io_deq_valid : _T_3714 ? _Queue10_UInt8_28_io_deq_valid : _T_3713 ? _Queue10_UInt8_27_io_deq_valid : _T_3712 ? _Queue10_UInt8_26_io_deq_valid : _T_3711 ? _Queue10_UInt8_25_io_deq_valid : _T_3710 ? _Queue10_UInt8_24_io_deq_valid : _T_3709 ? _Queue10_UInt8_23_io_deq_valid : _T_3708 ? _Queue10_UInt8_22_io_deq_valid : _T_3707 ? _Queue10_UInt8_21_io_deq_valid : _T_3706 ? _Queue10_UInt8_20_io_deq_valid : _T_3705 ? _Queue10_UInt8_19_io_deq_valid : _T_3704 ? _Queue10_UInt8_18_io_deq_valid : _T_3703 ? _Queue10_UInt8_17_io_deq_valid : _T_3702 ? _Queue10_UInt8_16_io_deq_valid : _T_3701 ? _Queue10_UInt8_15_io_deq_valid : _T_3700 ? _Queue10_UInt8_14_io_deq_valid : _T_3699 ? _Queue10_UInt8_13_io_deq_valid : _T_3698 ? _Queue10_UInt8_12_io_deq_valid : _T_3697 ? _Queue10_UInt8_11_io_deq_valid : _T_3696 ? _Queue10_UInt8_10_io_deq_valid : _T_3695 ? _Queue10_UInt8_9_io_deq_valid : _T_3694 ? _Queue10_UInt8_8_io_deq_valid : _T_3693 ? _Queue10_UInt8_7_io_deq_valid : _T_3692 ? _Queue10_UInt8_6_io_deq_valid : _T_3691 ? _Queue10_UInt8_5_io_deq_valid : _T_3690 ? _Queue10_UInt8_4_io_deq_valid : _T_3689 ? _Queue10_UInt8_3_io_deq_valid : _T_3688 ? _Queue10_UInt8_2_io_deq_valid : _T_3687 ? _Queue10_UInt8_1_io_deq_valid : _T_3686 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_103 = _remapindex_T_14 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_14 = _GEN_103[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3718 = remapindex_14 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3719 = remapindex_14 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3720 = remapindex_14 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3721 = remapindex_14 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3722 = remapindex_14 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3723 = remapindex_14 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3724 = remapindex_14 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3725 = remapindex_14 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3726 = remapindex_14 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3727 = remapindex_14 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3728 = remapindex_14 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3729 = remapindex_14 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3730 = remapindex_14 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3731 = remapindex_14 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3732 = remapindex_14 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3733 = remapindex_14 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3734 = remapindex_14 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3735 = remapindex_14 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3736 = remapindex_14 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3737 = remapindex_14 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3738 = remapindex_14 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3739 = remapindex_14 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3740 = remapindex_14 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3741 = remapindex_14 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3742 = remapindex_14 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3743 = remapindex_14 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3744 = remapindex_14 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3745 = remapindex_14 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3746 = remapindex_14 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3747 = remapindex_14 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3748 = remapindex_14 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3749 = remapindex_14 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_14 = _T_3749 ? _Queue10_UInt8_31_io_deq_bits : _T_3748 ? _Queue10_UInt8_30_io_deq_bits : _T_3747 ? _Queue10_UInt8_29_io_deq_bits : _T_3746 ? _Queue10_UInt8_28_io_deq_bits : _T_3745 ? _Queue10_UInt8_27_io_deq_bits : _T_3744 ? _Queue10_UInt8_26_io_deq_bits : _T_3743 ? _Queue10_UInt8_25_io_deq_bits : _T_3742 ? _Queue10_UInt8_24_io_deq_bits : _T_3741 ? _Queue10_UInt8_23_io_deq_bits : _T_3740 ? _Queue10_UInt8_22_io_deq_bits : _T_3739 ? _Queue10_UInt8_21_io_deq_bits : _T_3738 ? _Queue10_UInt8_20_io_deq_bits : _T_3737 ? _Queue10_UInt8_19_io_deq_bits : _T_3736 ? _Queue10_UInt8_18_io_deq_bits : _T_3735 ? _Queue10_UInt8_17_io_deq_bits : _T_3734 ? _Queue10_UInt8_16_io_deq_bits : _T_3733 ? _Queue10_UInt8_15_io_deq_bits : _T_3732 ? _Queue10_UInt8_14_io_deq_bits : _T_3731 ? _Queue10_UInt8_13_io_deq_bits : _T_3730 ? _Queue10_UInt8_12_io_deq_bits : _T_3729 ? _Queue10_UInt8_11_io_deq_bits : _T_3728 ? _Queue10_UInt8_10_io_deq_bits : _T_3727 ? _Queue10_UInt8_9_io_deq_bits : _T_3726 ? _Queue10_UInt8_8_io_deq_bits : _T_3725 ? _Queue10_UInt8_7_io_deq_bits : _T_3724 ? _Queue10_UInt8_6_io_deq_bits : _T_3723 ? _Queue10_UInt8_5_io_deq_bits : _T_3722 ? _Queue10_UInt8_4_io_deq_bits : _T_3721 ? _Queue10_UInt8_3_io_deq_bits : _T_3720 ? _Queue10_UInt8_2_io_deq_bits : _T_3719 ? _Queue10_UInt8_1_io_deq_bits : _T_3718 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_14 = _T_3749 ? _Queue10_UInt8_31_io_deq_valid : _T_3748 ? _Queue10_UInt8_30_io_deq_valid : _T_3747 ? _Queue10_UInt8_29_io_deq_valid : _T_3746 ? _Queue10_UInt8_28_io_deq_valid : _T_3745 ? _Queue10_UInt8_27_io_deq_valid : _T_3744 ? _Queue10_UInt8_26_io_deq_valid : _T_3743 ? _Queue10_UInt8_25_io_deq_valid : _T_3742 ? _Queue10_UInt8_24_io_deq_valid : _T_3741 ? _Queue10_UInt8_23_io_deq_valid : _T_3740 ? _Queue10_UInt8_22_io_deq_valid : _T_3739 ? _Queue10_UInt8_21_io_deq_valid : _T_3738 ? _Queue10_UInt8_20_io_deq_valid : _T_3737 ? _Queue10_UInt8_19_io_deq_valid : _T_3736 ? _Queue10_UInt8_18_io_deq_valid : _T_3735 ? _Queue10_UInt8_17_io_deq_valid : _T_3734 ? _Queue10_UInt8_16_io_deq_valid : _T_3733 ? _Queue10_UInt8_15_io_deq_valid : _T_3732 ? _Queue10_UInt8_14_io_deq_valid : _T_3731 ? _Queue10_UInt8_13_io_deq_valid : _T_3730 ? _Queue10_UInt8_12_io_deq_valid : _T_3729 ? _Queue10_UInt8_11_io_deq_valid : _T_3728 ? _Queue10_UInt8_10_io_deq_valid : _T_3727 ? _Queue10_UInt8_9_io_deq_valid : _T_3726 ? _Queue10_UInt8_8_io_deq_valid : _T_3725 ? _Queue10_UInt8_7_io_deq_valid : _T_3724 ? _Queue10_UInt8_6_io_deq_valid : _T_3723 ? _Queue10_UInt8_5_io_deq_valid : _T_3722 ? _Queue10_UInt8_4_io_deq_valid : _T_3721 ? _Queue10_UInt8_3_io_deq_valid : _T_3720 ? _Queue10_UInt8_2_io_deq_valid : _T_3719 ? _Queue10_UInt8_1_io_deq_valid : _T_3718 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_104 = _remapindex_T_15 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_15 = _GEN_104[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3750 = remapindex_15 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3751 = remapindex_15 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3752 = remapindex_15 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3753 = remapindex_15 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3754 = remapindex_15 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3755 = remapindex_15 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3756 = remapindex_15 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3757 = remapindex_15 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3758 = remapindex_15 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3759 = remapindex_15 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3760 = remapindex_15 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3761 = remapindex_15 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3762 = remapindex_15 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3763 = remapindex_15 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3764 = remapindex_15 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3765 = remapindex_15 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3766 = remapindex_15 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3767 = remapindex_15 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3768 = remapindex_15 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3769 = remapindex_15 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3770 = remapindex_15 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3771 = remapindex_15 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3772 = remapindex_15 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3773 = remapindex_15 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3774 = remapindex_15 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3775 = remapindex_15 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3776 = remapindex_15 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3777 = remapindex_15 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3778 = remapindex_15 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3779 = remapindex_15 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3780 = remapindex_15 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3781 = remapindex_15 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_15 = _T_3781 ? _Queue10_UInt8_31_io_deq_bits : _T_3780 ? _Queue10_UInt8_30_io_deq_bits : _T_3779 ? _Queue10_UInt8_29_io_deq_bits : _T_3778 ? _Queue10_UInt8_28_io_deq_bits : _T_3777 ? _Queue10_UInt8_27_io_deq_bits : _T_3776 ? _Queue10_UInt8_26_io_deq_bits : _T_3775 ? _Queue10_UInt8_25_io_deq_bits : _T_3774 ? _Queue10_UInt8_24_io_deq_bits : _T_3773 ? _Queue10_UInt8_23_io_deq_bits : _T_3772 ? _Queue10_UInt8_22_io_deq_bits : _T_3771 ? _Queue10_UInt8_21_io_deq_bits : _T_3770 ? _Queue10_UInt8_20_io_deq_bits : _T_3769 ? _Queue10_UInt8_19_io_deq_bits : _T_3768 ? _Queue10_UInt8_18_io_deq_bits : _T_3767 ? _Queue10_UInt8_17_io_deq_bits : _T_3766 ? _Queue10_UInt8_16_io_deq_bits : _T_3765 ? _Queue10_UInt8_15_io_deq_bits : _T_3764 ? _Queue10_UInt8_14_io_deq_bits : _T_3763 ? _Queue10_UInt8_13_io_deq_bits : _T_3762 ? _Queue10_UInt8_12_io_deq_bits : _T_3761 ? _Queue10_UInt8_11_io_deq_bits : _T_3760 ? _Queue10_UInt8_10_io_deq_bits : _T_3759 ? _Queue10_UInt8_9_io_deq_bits : _T_3758 ? _Queue10_UInt8_8_io_deq_bits : _T_3757 ? _Queue10_UInt8_7_io_deq_bits : _T_3756 ? _Queue10_UInt8_6_io_deq_bits : _T_3755 ? _Queue10_UInt8_5_io_deq_bits : _T_3754 ? _Queue10_UInt8_4_io_deq_bits : _T_3753 ? _Queue10_UInt8_3_io_deq_bits : _T_3752 ? _Queue10_UInt8_2_io_deq_bits : _T_3751 ? _Queue10_UInt8_1_io_deq_bits : _T_3750 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_15 = _T_3781 ? _Queue10_UInt8_31_io_deq_valid : _T_3780 ? _Queue10_UInt8_30_io_deq_valid : _T_3779 ? _Queue10_UInt8_29_io_deq_valid : _T_3778 ? _Queue10_UInt8_28_io_deq_valid : _T_3777 ? _Queue10_UInt8_27_io_deq_valid : _T_3776 ? _Queue10_UInt8_26_io_deq_valid : _T_3775 ? _Queue10_UInt8_25_io_deq_valid : _T_3774 ? _Queue10_UInt8_24_io_deq_valid : _T_3773 ? _Queue10_UInt8_23_io_deq_valid : _T_3772 ? _Queue10_UInt8_22_io_deq_valid : _T_3771 ? _Queue10_UInt8_21_io_deq_valid : _T_3770 ? _Queue10_UInt8_20_io_deq_valid : _T_3769 ? _Queue10_UInt8_19_io_deq_valid : _T_3768 ? _Queue10_UInt8_18_io_deq_valid : _T_3767 ? _Queue10_UInt8_17_io_deq_valid : _T_3766 ? _Queue10_UInt8_16_io_deq_valid : _T_3765 ? _Queue10_UInt8_15_io_deq_valid : _T_3764 ? _Queue10_UInt8_14_io_deq_valid : _T_3763 ? _Queue10_UInt8_13_io_deq_valid : _T_3762 ? _Queue10_UInt8_12_io_deq_valid : _T_3761 ? _Queue10_UInt8_11_io_deq_valid : _T_3760 ? _Queue10_UInt8_10_io_deq_valid : _T_3759 ? _Queue10_UInt8_9_io_deq_valid : _T_3758 ? _Queue10_UInt8_8_io_deq_valid : _T_3757 ? _Queue10_UInt8_7_io_deq_valid : _T_3756 ? _Queue10_UInt8_6_io_deq_valid : _T_3755 ? _Queue10_UInt8_5_io_deq_valid : _T_3754 ? _Queue10_UInt8_4_io_deq_valid : _T_3753 ? _Queue10_UInt8_3_io_deq_valid : _T_3752 ? _Queue10_UInt8_2_io_deq_valid : _T_3751 ? _Queue10_UInt8_1_io_deq_valid : _T_3750 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_105 = _remapindex_T_16 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_16 = _GEN_105[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3782 = remapindex_16 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3783 = remapindex_16 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3784 = remapindex_16 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3785 = remapindex_16 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3786 = remapindex_16 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3787 = remapindex_16 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3788 = remapindex_16 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3789 = remapindex_16 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3790 = remapindex_16 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3791 = remapindex_16 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3792 = remapindex_16 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3793 = remapindex_16 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3794 = remapindex_16 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3795 = remapindex_16 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3796 = remapindex_16 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3797 = remapindex_16 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3798 = remapindex_16 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3799 = remapindex_16 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3800 = remapindex_16 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3801 = remapindex_16 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3802 = remapindex_16 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3803 = remapindex_16 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3804 = remapindex_16 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3805 = remapindex_16 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3806 = remapindex_16 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3807 = remapindex_16 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3808 = remapindex_16 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3809 = remapindex_16 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3810 = remapindex_16 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3811 = remapindex_16 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3812 = remapindex_16 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3813 = remapindex_16 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_16 = _T_3813 ? _Queue10_UInt8_31_io_deq_bits : _T_3812 ? _Queue10_UInt8_30_io_deq_bits : _T_3811 ? _Queue10_UInt8_29_io_deq_bits : _T_3810 ? _Queue10_UInt8_28_io_deq_bits : _T_3809 ? _Queue10_UInt8_27_io_deq_bits : _T_3808 ? _Queue10_UInt8_26_io_deq_bits : _T_3807 ? _Queue10_UInt8_25_io_deq_bits : _T_3806 ? _Queue10_UInt8_24_io_deq_bits : _T_3805 ? _Queue10_UInt8_23_io_deq_bits : _T_3804 ? _Queue10_UInt8_22_io_deq_bits : _T_3803 ? _Queue10_UInt8_21_io_deq_bits : _T_3802 ? _Queue10_UInt8_20_io_deq_bits : _T_3801 ? _Queue10_UInt8_19_io_deq_bits : _T_3800 ? _Queue10_UInt8_18_io_deq_bits : _T_3799 ? _Queue10_UInt8_17_io_deq_bits : _T_3798 ? _Queue10_UInt8_16_io_deq_bits : _T_3797 ? _Queue10_UInt8_15_io_deq_bits : _T_3796 ? _Queue10_UInt8_14_io_deq_bits : _T_3795 ? _Queue10_UInt8_13_io_deq_bits : _T_3794 ? _Queue10_UInt8_12_io_deq_bits : _T_3793 ? _Queue10_UInt8_11_io_deq_bits : _T_3792 ? _Queue10_UInt8_10_io_deq_bits : _T_3791 ? _Queue10_UInt8_9_io_deq_bits : _T_3790 ? _Queue10_UInt8_8_io_deq_bits : _T_3789 ? _Queue10_UInt8_7_io_deq_bits : _T_3788 ? _Queue10_UInt8_6_io_deq_bits : _T_3787 ? _Queue10_UInt8_5_io_deq_bits : _T_3786 ? _Queue10_UInt8_4_io_deq_bits : _T_3785 ? _Queue10_UInt8_3_io_deq_bits : _T_3784 ? _Queue10_UInt8_2_io_deq_bits : _T_3783 ? _Queue10_UInt8_1_io_deq_bits : _T_3782 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_16 = _T_3813 ? _Queue10_UInt8_31_io_deq_valid : _T_3812 ? _Queue10_UInt8_30_io_deq_valid : _T_3811 ? _Queue10_UInt8_29_io_deq_valid : _T_3810 ? _Queue10_UInt8_28_io_deq_valid : _T_3809 ? _Queue10_UInt8_27_io_deq_valid : _T_3808 ? _Queue10_UInt8_26_io_deq_valid : _T_3807 ? _Queue10_UInt8_25_io_deq_valid : _T_3806 ? _Queue10_UInt8_24_io_deq_valid : _T_3805 ? _Queue10_UInt8_23_io_deq_valid : _T_3804 ? _Queue10_UInt8_22_io_deq_valid : _T_3803 ? _Queue10_UInt8_21_io_deq_valid : _T_3802 ? _Queue10_UInt8_20_io_deq_valid : _T_3801 ? _Queue10_UInt8_19_io_deq_valid : _T_3800 ? _Queue10_UInt8_18_io_deq_valid : _T_3799 ? _Queue10_UInt8_17_io_deq_valid : _T_3798 ? _Queue10_UInt8_16_io_deq_valid : _T_3797 ? _Queue10_UInt8_15_io_deq_valid : _T_3796 ? _Queue10_UInt8_14_io_deq_valid : _T_3795 ? _Queue10_UInt8_13_io_deq_valid : _T_3794 ? _Queue10_UInt8_12_io_deq_valid : _T_3793 ? _Queue10_UInt8_11_io_deq_valid : _T_3792 ? _Queue10_UInt8_10_io_deq_valid : _T_3791 ? _Queue10_UInt8_9_io_deq_valid : _T_3790 ? _Queue10_UInt8_8_io_deq_valid : _T_3789 ? _Queue10_UInt8_7_io_deq_valid : _T_3788 ? _Queue10_UInt8_6_io_deq_valid : _T_3787 ? _Queue10_UInt8_5_io_deq_valid : _T_3786 ? _Queue10_UInt8_4_io_deq_valid : _T_3785 ? _Queue10_UInt8_3_io_deq_valid : _T_3784 ? _Queue10_UInt8_2_io_deq_valid : _T_3783 ? _Queue10_UInt8_1_io_deq_valid : _T_3782 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_106 = _remapindex_T_17 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_17 = _GEN_106[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3814 = remapindex_17 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3815 = remapindex_17 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3816 = remapindex_17 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3817 = remapindex_17 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3818 = remapindex_17 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3819 = remapindex_17 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3820 = remapindex_17 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3821 = remapindex_17 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3822 = remapindex_17 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3823 = remapindex_17 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3824 = remapindex_17 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3825 = remapindex_17 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3826 = remapindex_17 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3827 = remapindex_17 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3828 = remapindex_17 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3829 = remapindex_17 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3830 = remapindex_17 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3831 = remapindex_17 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3832 = remapindex_17 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3833 = remapindex_17 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3834 = remapindex_17 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3835 = remapindex_17 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3836 = remapindex_17 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3837 = remapindex_17 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3838 = remapindex_17 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3839 = remapindex_17 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3840 = remapindex_17 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3841 = remapindex_17 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3842 = remapindex_17 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3843 = remapindex_17 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3844 = remapindex_17 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3845 = remapindex_17 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_17 = _T_3845 ? _Queue10_UInt8_31_io_deq_bits : _T_3844 ? _Queue10_UInt8_30_io_deq_bits : _T_3843 ? _Queue10_UInt8_29_io_deq_bits : _T_3842 ? _Queue10_UInt8_28_io_deq_bits : _T_3841 ? _Queue10_UInt8_27_io_deq_bits : _T_3840 ? _Queue10_UInt8_26_io_deq_bits : _T_3839 ? _Queue10_UInt8_25_io_deq_bits : _T_3838 ? _Queue10_UInt8_24_io_deq_bits : _T_3837 ? _Queue10_UInt8_23_io_deq_bits : _T_3836 ? _Queue10_UInt8_22_io_deq_bits : _T_3835 ? _Queue10_UInt8_21_io_deq_bits : _T_3834 ? _Queue10_UInt8_20_io_deq_bits : _T_3833 ? _Queue10_UInt8_19_io_deq_bits : _T_3832 ? _Queue10_UInt8_18_io_deq_bits : _T_3831 ? _Queue10_UInt8_17_io_deq_bits : _T_3830 ? _Queue10_UInt8_16_io_deq_bits : _T_3829 ? _Queue10_UInt8_15_io_deq_bits : _T_3828 ? _Queue10_UInt8_14_io_deq_bits : _T_3827 ? _Queue10_UInt8_13_io_deq_bits : _T_3826 ? _Queue10_UInt8_12_io_deq_bits : _T_3825 ? _Queue10_UInt8_11_io_deq_bits : _T_3824 ? _Queue10_UInt8_10_io_deq_bits : _T_3823 ? _Queue10_UInt8_9_io_deq_bits : _T_3822 ? _Queue10_UInt8_8_io_deq_bits : _T_3821 ? _Queue10_UInt8_7_io_deq_bits : _T_3820 ? _Queue10_UInt8_6_io_deq_bits : _T_3819 ? _Queue10_UInt8_5_io_deq_bits : _T_3818 ? _Queue10_UInt8_4_io_deq_bits : _T_3817 ? _Queue10_UInt8_3_io_deq_bits : _T_3816 ? _Queue10_UInt8_2_io_deq_bits : _T_3815 ? _Queue10_UInt8_1_io_deq_bits : _T_3814 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_17 = _T_3845 ? _Queue10_UInt8_31_io_deq_valid : _T_3844 ? _Queue10_UInt8_30_io_deq_valid : _T_3843 ? _Queue10_UInt8_29_io_deq_valid : _T_3842 ? _Queue10_UInt8_28_io_deq_valid : _T_3841 ? _Queue10_UInt8_27_io_deq_valid : _T_3840 ? _Queue10_UInt8_26_io_deq_valid : _T_3839 ? _Queue10_UInt8_25_io_deq_valid : _T_3838 ? _Queue10_UInt8_24_io_deq_valid : _T_3837 ? _Queue10_UInt8_23_io_deq_valid : _T_3836 ? _Queue10_UInt8_22_io_deq_valid : _T_3835 ? _Queue10_UInt8_21_io_deq_valid : _T_3834 ? _Queue10_UInt8_20_io_deq_valid : _T_3833 ? _Queue10_UInt8_19_io_deq_valid : _T_3832 ? _Queue10_UInt8_18_io_deq_valid : _T_3831 ? _Queue10_UInt8_17_io_deq_valid : _T_3830 ? _Queue10_UInt8_16_io_deq_valid : _T_3829 ? _Queue10_UInt8_15_io_deq_valid : _T_3828 ? _Queue10_UInt8_14_io_deq_valid : _T_3827 ? _Queue10_UInt8_13_io_deq_valid : _T_3826 ? _Queue10_UInt8_12_io_deq_valid : _T_3825 ? _Queue10_UInt8_11_io_deq_valid : _T_3824 ? _Queue10_UInt8_10_io_deq_valid : _T_3823 ? _Queue10_UInt8_9_io_deq_valid : _T_3822 ? _Queue10_UInt8_8_io_deq_valid : _T_3821 ? _Queue10_UInt8_7_io_deq_valid : _T_3820 ? _Queue10_UInt8_6_io_deq_valid : _T_3819 ? _Queue10_UInt8_5_io_deq_valid : _T_3818 ? _Queue10_UInt8_4_io_deq_valid : _T_3817 ? _Queue10_UInt8_3_io_deq_valid : _T_3816 ? _Queue10_UInt8_2_io_deq_valid : _T_3815 ? _Queue10_UInt8_1_io_deq_valid : _T_3814 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_107 = _remapindex_T_18 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_18 = _GEN_107[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3846 = remapindex_18 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3847 = remapindex_18 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3848 = remapindex_18 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3849 = remapindex_18 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3850 = remapindex_18 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3851 = remapindex_18 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3852 = remapindex_18 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3853 = remapindex_18 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3854 = remapindex_18 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3855 = remapindex_18 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3856 = remapindex_18 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3857 = remapindex_18 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3858 = remapindex_18 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3859 = remapindex_18 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3860 = remapindex_18 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3861 = remapindex_18 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3862 = remapindex_18 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3863 = remapindex_18 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3864 = remapindex_18 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3865 = remapindex_18 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3866 = remapindex_18 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3867 = remapindex_18 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3868 = remapindex_18 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3869 = remapindex_18 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3870 = remapindex_18 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3871 = remapindex_18 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3872 = remapindex_18 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3873 = remapindex_18 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3874 = remapindex_18 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3875 = remapindex_18 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3876 = remapindex_18 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3877 = remapindex_18 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_18 = _T_3877 ? _Queue10_UInt8_31_io_deq_bits : _T_3876 ? _Queue10_UInt8_30_io_deq_bits : _T_3875 ? _Queue10_UInt8_29_io_deq_bits : _T_3874 ? _Queue10_UInt8_28_io_deq_bits : _T_3873 ? _Queue10_UInt8_27_io_deq_bits : _T_3872 ? _Queue10_UInt8_26_io_deq_bits : _T_3871 ? _Queue10_UInt8_25_io_deq_bits : _T_3870 ? _Queue10_UInt8_24_io_deq_bits : _T_3869 ? _Queue10_UInt8_23_io_deq_bits : _T_3868 ? _Queue10_UInt8_22_io_deq_bits : _T_3867 ? _Queue10_UInt8_21_io_deq_bits : _T_3866 ? _Queue10_UInt8_20_io_deq_bits : _T_3865 ? _Queue10_UInt8_19_io_deq_bits : _T_3864 ? _Queue10_UInt8_18_io_deq_bits : _T_3863 ? _Queue10_UInt8_17_io_deq_bits : _T_3862 ? _Queue10_UInt8_16_io_deq_bits : _T_3861 ? _Queue10_UInt8_15_io_deq_bits : _T_3860 ? _Queue10_UInt8_14_io_deq_bits : _T_3859 ? _Queue10_UInt8_13_io_deq_bits : _T_3858 ? _Queue10_UInt8_12_io_deq_bits : _T_3857 ? _Queue10_UInt8_11_io_deq_bits : _T_3856 ? _Queue10_UInt8_10_io_deq_bits : _T_3855 ? _Queue10_UInt8_9_io_deq_bits : _T_3854 ? _Queue10_UInt8_8_io_deq_bits : _T_3853 ? _Queue10_UInt8_7_io_deq_bits : _T_3852 ? _Queue10_UInt8_6_io_deq_bits : _T_3851 ? _Queue10_UInt8_5_io_deq_bits : _T_3850 ? _Queue10_UInt8_4_io_deq_bits : _T_3849 ? _Queue10_UInt8_3_io_deq_bits : _T_3848 ? _Queue10_UInt8_2_io_deq_bits : _T_3847 ? _Queue10_UInt8_1_io_deq_bits : _T_3846 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_18 = _T_3877 ? _Queue10_UInt8_31_io_deq_valid : _T_3876 ? _Queue10_UInt8_30_io_deq_valid : _T_3875 ? _Queue10_UInt8_29_io_deq_valid : _T_3874 ? _Queue10_UInt8_28_io_deq_valid : _T_3873 ? _Queue10_UInt8_27_io_deq_valid : _T_3872 ? _Queue10_UInt8_26_io_deq_valid : _T_3871 ? _Queue10_UInt8_25_io_deq_valid : _T_3870 ? _Queue10_UInt8_24_io_deq_valid : _T_3869 ? _Queue10_UInt8_23_io_deq_valid : _T_3868 ? _Queue10_UInt8_22_io_deq_valid : _T_3867 ? _Queue10_UInt8_21_io_deq_valid : _T_3866 ? _Queue10_UInt8_20_io_deq_valid : _T_3865 ? _Queue10_UInt8_19_io_deq_valid : _T_3864 ? _Queue10_UInt8_18_io_deq_valid : _T_3863 ? _Queue10_UInt8_17_io_deq_valid : _T_3862 ? _Queue10_UInt8_16_io_deq_valid : _T_3861 ? _Queue10_UInt8_15_io_deq_valid : _T_3860 ? _Queue10_UInt8_14_io_deq_valid : _T_3859 ? _Queue10_UInt8_13_io_deq_valid : _T_3858 ? _Queue10_UInt8_12_io_deq_valid : _T_3857 ? _Queue10_UInt8_11_io_deq_valid : _T_3856 ? _Queue10_UInt8_10_io_deq_valid : _T_3855 ? _Queue10_UInt8_9_io_deq_valid : _T_3854 ? _Queue10_UInt8_8_io_deq_valid : _T_3853 ? _Queue10_UInt8_7_io_deq_valid : _T_3852 ? _Queue10_UInt8_6_io_deq_valid : _T_3851 ? _Queue10_UInt8_5_io_deq_valid : _T_3850 ? _Queue10_UInt8_4_io_deq_valid : _T_3849 ? _Queue10_UInt8_3_io_deq_valid : _T_3848 ? _Queue10_UInt8_2_io_deq_valid : _T_3847 ? _Queue10_UInt8_1_io_deq_valid : _T_3846 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_108 = _remapindex_T_19 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_19 = _GEN_108[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3878 = remapindex_19 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3879 = remapindex_19 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3880 = remapindex_19 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3881 = remapindex_19 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3882 = remapindex_19 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3883 = remapindex_19 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3884 = remapindex_19 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3885 = remapindex_19 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3886 = remapindex_19 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3887 = remapindex_19 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3888 = remapindex_19 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3889 = remapindex_19 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3890 = remapindex_19 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3891 = remapindex_19 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3892 = remapindex_19 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3893 = remapindex_19 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3894 = remapindex_19 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3895 = remapindex_19 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3896 = remapindex_19 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3897 = remapindex_19 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3898 = remapindex_19 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3899 = remapindex_19 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3900 = remapindex_19 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3901 = remapindex_19 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3902 = remapindex_19 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3903 = remapindex_19 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3904 = remapindex_19 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3905 = remapindex_19 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3906 = remapindex_19 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3907 = remapindex_19 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3908 = remapindex_19 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3909 = remapindex_19 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_19 = _T_3909 ? _Queue10_UInt8_31_io_deq_bits : _T_3908 ? _Queue10_UInt8_30_io_deq_bits : _T_3907 ? _Queue10_UInt8_29_io_deq_bits : _T_3906 ? _Queue10_UInt8_28_io_deq_bits : _T_3905 ? _Queue10_UInt8_27_io_deq_bits : _T_3904 ? _Queue10_UInt8_26_io_deq_bits : _T_3903 ? _Queue10_UInt8_25_io_deq_bits : _T_3902 ? _Queue10_UInt8_24_io_deq_bits : _T_3901 ? _Queue10_UInt8_23_io_deq_bits : _T_3900 ? _Queue10_UInt8_22_io_deq_bits : _T_3899 ? _Queue10_UInt8_21_io_deq_bits : _T_3898 ? _Queue10_UInt8_20_io_deq_bits : _T_3897 ? _Queue10_UInt8_19_io_deq_bits : _T_3896 ? _Queue10_UInt8_18_io_deq_bits : _T_3895 ? _Queue10_UInt8_17_io_deq_bits : _T_3894 ? _Queue10_UInt8_16_io_deq_bits : _T_3893 ? _Queue10_UInt8_15_io_deq_bits : _T_3892 ? _Queue10_UInt8_14_io_deq_bits : _T_3891 ? _Queue10_UInt8_13_io_deq_bits : _T_3890 ? _Queue10_UInt8_12_io_deq_bits : _T_3889 ? _Queue10_UInt8_11_io_deq_bits : _T_3888 ? _Queue10_UInt8_10_io_deq_bits : _T_3887 ? _Queue10_UInt8_9_io_deq_bits : _T_3886 ? _Queue10_UInt8_8_io_deq_bits : _T_3885 ? _Queue10_UInt8_7_io_deq_bits : _T_3884 ? _Queue10_UInt8_6_io_deq_bits : _T_3883 ? _Queue10_UInt8_5_io_deq_bits : _T_3882 ? _Queue10_UInt8_4_io_deq_bits : _T_3881 ? _Queue10_UInt8_3_io_deq_bits : _T_3880 ? _Queue10_UInt8_2_io_deq_bits : _T_3879 ? _Queue10_UInt8_1_io_deq_bits : _T_3878 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_19 = _T_3909 ? _Queue10_UInt8_31_io_deq_valid : _T_3908 ? _Queue10_UInt8_30_io_deq_valid : _T_3907 ? _Queue10_UInt8_29_io_deq_valid : _T_3906 ? _Queue10_UInt8_28_io_deq_valid : _T_3905 ? _Queue10_UInt8_27_io_deq_valid : _T_3904 ? _Queue10_UInt8_26_io_deq_valid : _T_3903 ? _Queue10_UInt8_25_io_deq_valid : _T_3902 ? _Queue10_UInt8_24_io_deq_valid : _T_3901 ? _Queue10_UInt8_23_io_deq_valid : _T_3900 ? _Queue10_UInt8_22_io_deq_valid : _T_3899 ? _Queue10_UInt8_21_io_deq_valid : _T_3898 ? _Queue10_UInt8_20_io_deq_valid : _T_3897 ? _Queue10_UInt8_19_io_deq_valid : _T_3896 ? _Queue10_UInt8_18_io_deq_valid : _T_3895 ? _Queue10_UInt8_17_io_deq_valid : _T_3894 ? _Queue10_UInt8_16_io_deq_valid : _T_3893 ? _Queue10_UInt8_15_io_deq_valid : _T_3892 ? _Queue10_UInt8_14_io_deq_valid : _T_3891 ? _Queue10_UInt8_13_io_deq_valid : _T_3890 ? _Queue10_UInt8_12_io_deq_valid : _T_3889 ? _Queue10_UInt8_11_io_deq_valid : _T_3888 ? _Queue10_UInt8_10_io_deq_valid : _T_3887 ? _Queue10_UInt8_9_io_deq_valid : _T_3886 ? _Queue10_UInt8_8_io_deq_valid : _T_3885 ? _Queue10_UInt8_7_io_deq_valid : _T_3884 ? _Queue10_UInt8_6_io_deq_valid : _T_3883 ? _Queue10_UInt8_5_io_deq_valid : _T_3882 ? _Queue10_UInt8_4_io_deq_valid : _T_3881 ? _Queue10_UInt8_3_io_deq_valid : _T_3880 ? _Queue10_UInt8_2_io_deq_valid : _T_3879 ? _Queue10_UInt8_1_io_deq_valid : _T_3878 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_109 = _remapindex_T_20 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_20 = _GEN_109[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3910 = remapindex_20 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3911 = remapindex_20 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3912 = remapindex_20 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3913 = remapindex_20 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3914 = remapindex_20 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3915 = remapindex_20 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3916 = remapindex_20 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3917 = remapindex_20 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3918 = remapindex_20 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3919 = remapindex_20 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3920 = remapindex_20 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3921 = remapindex_20 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3922 = remapindex_20 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3923 = remapindex_20 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3924 = remapindex_20 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3925 = remapindex_20 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3926 = remapindex_20 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3927 = remapindex_20 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3928 = remapindex_20 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3929 = remapindex_20 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3930 = remapindex_20 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3931 = remapindex_20 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3932 = remapindex_20 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3933 = remapindex_20 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3934 = remapindex_20 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3935 = remapindex_20 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3936 = remapindex_20 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3937 = remapindex_20 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3938 = remapindex_20 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3939 = remapindex_20 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3940 = remapindex_20 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3941 = remapindex_20 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_20 = _T_3941 ? _Queue10_UInt8_31_io_deq_bits : _T_3940 ? _Queue10_UInt8_30_io_deq_bits : _T_3939 ? _Queue10_UInt8_29_io_deq_bits : _T_3938 ? _Queue10_UInt8_28_io_deq_bits : _T_3937 ? _Queue10_UInt8_27_io_deq_bits : _T_3936 ? _Queue10_UInt8_26_io_deq_bits : _T_3935 ? _Queue10_UInt8_25_io_deq_bits : _T_3934 ? _Queue10_UInt8_24_io_deq_bits : _T_3933 ? _Queue10_UInt8_23_io_deq_bits : _T_3932 ? _Queue10_UInt8_22_io_deq_bits : _T_3931 ? _Queue10_UInt8_21_io_deq_bits : _T_3930 ? _Queue10_UInt8_20_io_deq_bits : _T_3929 ? _Queue10_UInt8_19_io_deq_bits : _T_3928 ? _Queue10_UInt8_18_io_deq_bits : _T_3927 ? _Queue10_UInt8_17_io_deq_bits : _T_3926 ? _Queue10_UInt8_16_io_deq_bits : _T_3925 ? _Queue10_UInt8_15_io_deq_bits : _T_3924 ? _Queue10_UInt8_14_io_deq_bits : _T_3923 ? _Queue10_UInt8_13_io_deq_bits : _T_3922 ? _Queue10_UInt8_12_io_deq_bits : _T_3921 ? _Queue10_UInt8_11_io_deq_bits : _T_3920 ? _Queue10_UInt8_10_io_deq_bits : _T_3919 ? _Queue10_UInt8_9_io_deq_bits : _T_3918 ? _Queue10_UInt8_8_io_deq_bits : _T_3917 ? _Queue10_UInt8_7_io_deq_bits : _T_3916 ? _Queue10_UInt8_6_io_deq_bits : _T_3915 ? _Queue10_UInt8_5_io_deq_bits : _T_3914 ? _Queue10_UInt8_4_io_deq_bits : _T_3913 ? _Queue10_UInt8_3_io_deq_bits : _T_3912 ? _Queue10_UInt8_2_io_deq_bits : _T_3911 ? _Queue10_UInt8_1_io_deq_bits : _T_3910 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_20 = _T_3941 ? _Queue10_UInt8_31_io_deq_valid : _T_3940 ? _Queue10_UInt8_30_io_deq_valid : _T_3939 ? _Queue10_UInt8_29_io_deq_valid : _T_3938 ? _Queue10_UInt8_28_io_deq_valid : _T_3937 ? _Queue10_UInt8_27_io_deq_valid : _T_3936 ? _Queue10_UInt8_26_io_deq_valid : _T_3935 ? _Queue10_UInt8_25_io_deq_valid : _T_3934 ? _Queue10_UInt8_24_io_deq_valid : _T_3933 ? _Queue10_UInt8_23_io_deq_valid : _T_3932 ? _Queue10_UInt8_22_io_deq_valid : _T_3931 ? _Queue10_UInt8_21_io_deq_valid : _T_3930 ? _Queue10_UInt8_20_io_deq_valid : _T_3929 ? _Queue10_UInt8_19_io_deq_valid : _T_3928 ? _Queue10_UInt8_18_io_deq_valid : _T_3927 ? _Queue10_UInt8_17_io_deq_valid : _T_3926 ? _Queue10_UInt8_16_io_deq_valid : _T_3925 ? _Queue10_UInt8_15_io_deq_valid : _T_3924 ? _Queue10_UInt8_14_io_deq_valid : _T_3923 ? _Queue10_UInt8_13_io_deq_valid : _T_3922 ? _Queue10_UInt8_12_io_deq_valid : _T_3921 ? _Queue10_UInt8_11_io_deq_valid : _T_3920 ? _Queue10_UInt8_10_io_deq_valid : _T_3919 ? _Queue10_UInt8_9_io_deq_valid : _T_3918 ? _Queue10_UInt8_8_io_deq_valid : _T_3917 ? _Queue10_UInt8_7_io_deq_valid : _T_3916 ? _Queue10_UInt8_6_io_deq_valid : _T_3915 ? _Queue10_UInt8_5_io_deq_valid : _T_3914 ? _Queue10_UInt8_4_io_deq_valid : _T_3913 ? _Queue10_UInt8_3_io_deq_valid : _T_3912 ? _Queue10_UInt8_2_io_deq_valid : _T_3911 ? _Queue10_UInt8_1_io_deq_valid : _T_3910 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_110 = _remapindex_T_21 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_21 = _GEN_110[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3942 = remapindex_21 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3943 = remapindex_21 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3944 = remapindex_21 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3945 = remapindex_21 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3946 = remapindex_21 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3947 = remapindex_21 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3948 = remapindex_21 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3949 = remapindex_21 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3950 = remapindex_21 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3951 = remapindex_21 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3952 = remapindex_21 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3953 = remapindex_21 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3954 = remapindex_21 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3955 = remapindex_21 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3956 = remapindex_21 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3957 = remapindex_21 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3958 = remapindex_21 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3959 = remapindex_21 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3960 = remapindex_21 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3961 = remapindex_21 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3962 = remapindex_21 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3963 = remapindex_21 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3964 = remapindex_21 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3965 = remapindex_21 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3966 = remapindex_21 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3967 = remapindex_21 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3968 = remapindex_21 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3969 = remapindex_21 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3970 = remapindex_21 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3971 = remapindex_21 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3972 = remapindex_21 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3973 = remapindex_21 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_21 = _T_3973 ? _Queue10_UInt8_31_io_deq_bits : _T_3972 ? _Queue10_UInt8_30_io_deq_bits : _T_3971 ? _Queue10_UInt8_29_io_deq_bits : _T_3970 ? _Queue10_UInt8_28_io_deq_bits : _T_3969 ? _Queue10_UInt8_27_io_deq_bits : _T_3968 ? _Queue10_UInt8_26_io_deq_bits : _T_3967 ? _Queue10_UInt8_25_io_deq_bits : _T_3966 ? _Queue10_UInt8_24_io_deq_bits : _T_3965 ? _Queue10_UInt8_23_io_deq_bits : _T_3964 ? _Queue10_UInt8_22_io_deq_bits : _T_3963 ? _Queue10_UInt8_21_io_deq_bits : _T_3962 ? _Queue10_UInt8_20_io_deq_bits : _T_3961 ? _Queue10_UInt8_19_io_deq_bits : _T_3960 ? _Queue10_UInt8_18_io_deq_bits : _T_3959 ? _Queue10_UInt8_17_io_deq_bits : _T_3958 ? _Queue10_UInt8_16_io_deq_bits : _T_3957 ? _Queue10_UInt8_15_io_deq_bits : _T_3956 ? _Queue10_UInt8_14_io_deq_bits : _T_3955 ? _Queue10_UInt8_13_io_deq_bits : _T_3954 ? _Queue10_UInt8_12_io_deq_bits : _T_3953 ? _Queue10_UInt8_11_io_deq_bits : _T_3952 ? _Queue10_UInt8_10_io_deq_bits : _T_3951 ? _Queue10_UInt8_9_io_deq_bits : _T_3950 ? _Queue10_UInt8_8_io_deq_bits : _T_3949 ? _Queue10_UInt8_7_io_deq_bits : _T_3948 ? _Queue10_UInt8_6_io_deq_bits : _T_3947 ? _Queue10_UInt8_5_io_deq_bits : _T_3946 ? _Queue10_UInt8_4_io_deq_bits : _T_3945 ? _Queue10_UInt8_3_io_deq_bits : _T_3944 ? _Queue10_UInt8_2_io_deq_bits : _T_3943 ? _Queue10_UInt8_1_io_deq_bits : _T_3942 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_21 = _T_3973 ? _Queue10_UInt8_31_io_deq_valid : _T_3972 ? _Queue10_UInt8_30_io_deq_valid : _T_3971 ? _Queue10_UInt8_29_io_deq_valid : _T_3970 ? _Queue10_UInt8_28_io_deq_valid : _T_3969 ? _Queue10_UInt8_27_io_deq_valid : _T_3968 ? _Queue10_UInt8_26_io_deq_valid : _T_3967 ? _Queue10_UInt8_25_io_deq_valid : _T_3966 ? _Queue10_UInt8_24_io_deq_valid : _T_3965 ? _Queue10_UInt8_23_io_deq_valid : _T_3964 ? _Queue10_UInt8_22_io_deq_valid : _T_3963 ? _Queue10_UInt8_21_io_deq_valid : _T_3962 ? _Queue10_UInt8_20_io_deq_valid : _T_3961 ? _Queue10_UInt8_19_io_deq_valid : _T_3960 ? _Queue10_UInt8_18_io_deq_valid : _T_3959 ? _Queue10_UInt8_17_io_deq_valid : _T_3958 ? _Queue10_UInt8_16_io_deq_valid : _T_3957 ? _Queue10_UInt8_15_io_deq_valid : _T_3956 ? _Queue10_UInt8_14_io_deq_valid : _T_3955 ? _Queue10_UInt8_13_io_deq_valid : _T_3954 ? _Queue10_UInt8_12_io_deq_valid : _T_3953 ? _Queue10_UInt8_11_io_deq_valid : _T_3952 ? _Queue10_UInt8_10_io_deq_valid : _T_3951 ? _Queue10_UInt8_9_io_deq_valid : _T_3950 ? _Queue10_UInt8_8_io_deq_valid : _T_3949 ? _Queue10_UInt8_7_io_deq_valid : _T_3948 ? _Queue10_UInt8_6_io_deq_valid : _T_3947 ? _Queue10_UInt8_5_io_deq_valid : _T_3946 ? _Queue10_UInt8_4_io_deq_valid : _T_3945 ? _Queue10_UInt8_3_io_deq_valid : _T_3944 ? _Queue10_UInt8_2_io_deq_valid : _T_3943 ? _Queue10_UInt8_1_io_deq_valid : _T_3942 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_111 = _remapindex_T_22 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_22 = _GEN_111[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_3974 = remapindex_22 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3975 = remapindex_22 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3976 = remapindex_22 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3977 = remapindex_22 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3978 = remapindex_22 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3979 = remapindex_22 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3980 = remapindex_22 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3981 = remapindex_22 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3982 = remapindex_22 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3983 = remapindex_22 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3984 = remapindex_22 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3985 = remapindex_22 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3986 = remapindex_22 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3987 = remapindex_22 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3988 = remapindex_22 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3989 = remapindex_22 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3990 = remapindex_22 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3991 = remapindex_22 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3992 = remapindex_22 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3993 = remapindex_22 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3994 = remapindex_22 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3995 = remapindex_22 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3996 = remapindex_22 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3997 = remapindex_22 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3998 = remapindex_22 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_3999 = remapindex_22 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4000 = remapindex_22 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4001 = remapindex_22 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4002 = remapindex_22 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4003 = remapindex_22 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4004 = remapindex_22 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4005 = remapindex_22 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_22 = _T_4005 ? _Queue10_UInt8_31_io_deq_bits : _T_4004 ? _Queue10_UInt8_30_io_deq_bits : _T_4003 ? _Queue10_UInt8_29_io_deq_bits : _T_4002 ? _Queue10_UInt8_28_io_deq_bits : _T_4001 ? _Queue10_UInt8_27_io_deq_bits : _T_4000 ? _Queue10_UInt8_26_io_deq_bits : _T_3999 ? _Queue10_UInt8_25_io_deq_bits : _T_3998 ? _Queue10_UInt8_24_io_deq_bits : _T_3997 ? _Queue10_UInt8_23_io_deq_bits : _T_3996 ? _Queue10_UInt8_22_io_deq_bits : _T_3995 ? _Queue10_UInt8_21_io_deq_bits : _T_3994 ? _Queue10_UInt8_20_io_deq_bits : _T_3993 ? _Queue10_UInt8_19_io_deq_bits : _T_3992 ? _Queue10_UInt8_18_io_deq_bits : _T_3991 ? _Queue10_UInt8_17_io_deq_bits : _T_3990 ? _Queue10_UInt8_16_io_deq_bits : _T_3989 ? _Queue10_UInt8_15_io_deq_bits : _T_3988 ? _Queue10_UInt8_14_io_deq_bits : _T_3987 ? _Queue10_UInt8_13_io_deq_bits : _T_3986 ? _Queue10_UInt8_12_io_deq_bits : _T_3985 ? _Queue10_UInt8_11_io_deq_bits : _T_3984 ? _Queue10_UInt8_10_io_deq_bits : _T_3983 ? _Queue10_UInt8_9_io_deq_bits : _T_3982 ? _Queue10_UInt8_8_io_deq_bits : _T_3981 ? _Queue10_UInt8_7_io_deq_bits : _T_3980 ? _Queue10_UInt8_6_io_deq_bits : _T_3979 ? _Queue10_UInt8_5_io_deq_bits : _T_3978 ? _Queue10_UInt8_4_io_deq_bits : _T_3977 ? _Queue10_UInt8_3_io_deq_bits : _T_3976 ? _Queue10_UInt8_2_io_deq_bits : _T_3975 ? _Queue10_UInt8_1_io_deq_bits : _T_3974 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_22 = _T_4005 ? _Queue10_UInt8_31_io_deq_valid : _T_4004 ? _Queue10_UInt8_30_io_deq_valid : _T_4003 ? _Queue10_UInt8_29_io_deq_valid : _T_4002 ? _Queue10_UInt8_28_io_deq_valid : _T_4001 ? _Queue10_UInt8_27_io_deq_valid : _T_4000 ? _Queue10_UInt8_26_io_deq_valid : _T_3999 ? _Queue10_UInt8_25_io_deq_valid : _T_3998 ? _Queue10_UInt8_24_io_deq_valid : _T_3997 ? _Queue10_UInt8_23_io_deq_valid : _T_3996 ? _Queue10_UInt8_22_io_deq_valid : _T_3995 ? _Queue10_UInt8_21_io_deq_valid : _T_3994 ? _Queue10_UInt8_20_io_deq_valid : _T_3993 ? _Queue10_UInt8_19_io_deq_valid : _T_3992 ? _Queue10_UInt8_18_io_deq_valid : _T_3991 ? _Queue10_UInt8_17_io_deq_valid : _T_3990 ? _Queue10_UInt8_16_io_deq_valid : _T_3989 ? _Queue10_UInt8_15_io_deq_valid : _T_3988 ? _Queue10_UInt8_14_io_deq_valid : _T_3987 ? _Queue10_UInt8_13_io_deq_valid : _T_3986 ? _Queue10_UInt8_12_io_deq_valid : _T_3985 ? _Queue10_UInt8_11_io_deq_valid : _T_3984 ? _Queue10_UInt8_10_io_deq_valid : _T_3983 ? _Queue10_UInt8_9_io_deq_valid : _T_3982 ? _Queue10_UInt8_8_io_deq_valid : _T_3981 ? _Queue10_UInt8_7_io_deq_valid : _T_3980 ? _Queue10_UInt8_6_io_deq_valid : _T_3979 ? _Queue10_UInt8_5_io_deq_valid : _T_3978 ? _Queue10_UInt8_4_io_deq_valid : _T_3977 ? _Queue10_UInt8_3_io_deq_valid : _T_3976 ? _Queue10_UInt8_2_io_deq_valid : _T_3975 ? _Queue10_UInt8_1_io_deq_valid : _T_3974 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_112 = _remapindex_T_23 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_23 = _GEN_112[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4006 = remapindex_23 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4007 = remapindex_23 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4008 = remapindex_23 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4009 = remapindex_23 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4010 = remapindex_23 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4011 = remapindex_23 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4012 = remapindex_23 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4013 = remapindex_23 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4014 = remapindex_23 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4015 = remapindex_23 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4016 = remapindex_23 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4017 = remapindex_23 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4018 = remapindex_23 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4019 = remapindex_23 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4020 = remapindex_23 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4021 = remapindex_23 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4022 = remapindex_23 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4023 = remapindex_23 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4024 = remapindex_23 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4025 = remapindex_23 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4026 = remapindex_23 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4027 = remapindex_23 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4028 = remapindex_23 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4029 = remapindex_23 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4030 = remapindex_23 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4031 = remapindex_23 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4032 = remapindex_23 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4033 = remapindex_23 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4034 = remapindex_23 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4035 = remapindex_23 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4036 = remapindex_23 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4037 = remapindex_23 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_23 = _T_4037 ? _Queue10_UInt8_31_io_deq_bits : _T_4036 ? _Queue10_UInt8_30_io_deq_bits : _T_4035 ? _Queue10_UInt8_29_io_deq_bits : _T_4034 ? _Queue10_UInt8_28_io_deq_bits : _T_4033 ? _Queue10_UInt8_27_io_deq_bits : _T_4032 ? _Queue10_UInt8_26_io_deq_bits : _T_4031 ? _Queue10_UInt8_25_io_deq_bits : _T_4030 ? _Queue10_UInt8_24_io_deq_bits : _T_4029 ? _Queue10_UInt8_23_io_deq_bits : _T_4028 ? _Queue10_UInt8_22_io_deq_bits : _T_4027 ? _Queue10_UInt8_21_io_deq_bits : _T_4026 ? _Queue10_UInt8_20_io_deq_bits : _T_4025 ? _Queue10_UInt8_19_io_deq_bits : _T_4024 ? _Queue10_UInt8_18_io_deq_bits : _T_4023 ? _Queue10_UInt8_17_io_deq_bits : _T_4022 ? _Queue10_UInt8_16_io_deq_bits : _T_4021 ? _Queue10_UInt8_15_io_deq_bits : _T_4020 ? _Queue10_UInt8_14_io_deq_bits : _T_4019 ? _Queue10_UInt8_13_io_deq_bits : _T_4018 ? _Queue10_UInt8_12_io_deq_bits : _T_4017 ? _Queue10_UInt8_11_io_deq_bits : _T_4016 ? _Queue10_UInt8_10_io_deq_bits : _T_4015 ? _Queue10_UInt8_9_io_deq_bits : _T_4014 ? _Queue10_UInt8_8_io_deq_bits : _T_4013 ? _Queue10_UInt8_7_io_deq_bits : _T_4012 ? _Queue10_UInt8_6_io_deq_bits : _T_4011 ? _Queue10_UInt8_5_io_deq_bits : _T_4010 ? _Queue10_UInt8_4_io_deq_bits : _T_4009 ? _Queue10_UInt8_3_io_deq_bits : _T_4008 ? _Queue10_UInt8_2_io_deq_bits : _T_4007 ? _Queue10_UInt8_1_io_deq_bits : _T_4006 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_23 = _T_4037 ? _Queue10_UInt8_31_io_deq_valid : _T_4036 ? _Queue10_UInt8_30_io_deq_valid : _T_4035 ? _Queue10_UInt8_29_io_deq_valid : _T_4034 ? _Queue10_UInt8_28_io_deq_valid : _T_4033 ? _Queue10_UInt8_27_io_deq_valid : _T_4032 ? _Queue10_UInt8_26_io_deq_valid : _T_4031 ? _Queue10_UInt8_25_io_deq_valid : _T_4030 ? _Queue10_UInt8_24_io_deq_valid : _T_4029 ? _Queue10_UInt8_23_io_deq_valid : _T_4028 ? _Queue10_UInt8_22_io_deq_valid : _T_4027 ? _Queue10_UInt8_21_io_deq_valid : _T_4026 ? _Queue10_UInt8_20_io_deq_valid : _T_4025 ? _Queue10_UInt8_19_io_deq_valid : _T_4024 ? _Queue10_UInt8_18_io_deq_valid : _T_4023 ? _Queue10_UInt8_17_io_deq_valid : _T_4022 ? _Queue10_UInt8_16_io_deq_valid : _T_4021 ? _Queue10_UInt8_15_io_deq_valid : _T_4020 ? _Queue10_UInt8_14_io_deq_valid : _T_4019 ? _Queue10_UInt8_13_io_deq_valid : _T_4018 ? _Queue10_UInt8_12_io_deq_valid : _T_4017 ? _Queue10_UInt8_11_io_deq_valid : _T_4016 ? _Queue10_UInt8_10_io_deq_valid : _T_4015 ? _Queue10_UInt8_9_io_deq_valid : _T_4014 ? _Queue10_UInt8_8_io_deq_valid : _T_4013 ? _Queue10_UInt8_7_io_deq_valid : _T_4012 ? _Queue10_UInt8_6_io_deq_valid : _T_4011 ? _Queue10_UInt8_5_io_deq_valid : _T_4010 ? _Queue10_UInt8_4_io_deq_valid : _T_4009 ? _Queue10_UInt8_3_io_deq_valid : _T_4008 ? _Queue10_UInt8_2_io_deq_valid : _T_4007 ? _Queue10_UInt8_1_io_deq_valid : _T_4006 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_113 = _remapindex_T_24 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_24 = _GEN_113[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4038 = remapindex_24 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4039 = remapindex_24 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4040 = remapindex_24 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4041 = remapindex_24 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4042 = remapindex_24 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4043 = remapindex_24 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4044 = remapindex_24 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4045 = remapindex_24 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4046 = remapindex_24 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4047 = remapindex_24 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4048 = remapindex_24 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4049 = remapindex_24 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4050 = remapindex_24 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4051 = remapindex_24 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4052 = remapindex_24 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4053 = remapindex_24 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4054 = remapindex_24 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4055 = remapindex_24 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4056 = remapindex_24 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4057 = remapindex_24 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4058 = remapindex_24 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4059 = remapindex_24 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4060 = remapindex_24 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4061 = remapindex_24 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4062 = remapindex_24 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4063 = remapindex_24 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4064 = remapindex_24 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4065 = remapindex_24 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4066 = remapindex_24 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4067 = remapindex_24 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4068 = remapindex_24 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4069 = remapindex_24 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_24 = _T_4069 ? _Queue10_UInt8_31_io_deq_bits : _T_4068 ? _Queue10_UInt8_30_io_deq_bits : _T_4067 ? _Queue10_UInt8_29_io_deq_bits : _T_4066 ? _Queue10_UInt8_28_io_deq_bits : _T_4065 ? _Queue10_UInt8_27_io_deq_bits : _T_4064 ? _Queue10_UInt8_26_io_deq_bits : _T_4063 ? _Queue10_UInt8_25_io_deq_bits : _T_4062 ? _Queue10_UInt8_24_io_deq_bits : _T_4061 ? _Queue10_UInt8_23_io_deq_bits : _T_4060 ? _Queue10_UInt8_22_io_deq_bits : _T_4059 ? _Queue10_UInt8_21_io_deq_bits : _T_4058 ? _Queue10_UInt8_20_io_deq_bits : _T_4057 ? _Queue10_UInt8_19_io_deq_bits : _T_4056 ? _Queue10_UInt8_18_io_deq_bits : _T_4055 ? _Queue10_UInt8_17_io_deq_bits : _T_4054 ? _Queue10_UInt8_16_io_deq_bits : _T_4053 ? _Queue10_UInt8_15_io_deq_bits : _T_4052 ? _Queue10_UInt8_14_io_deq_bits : _T_4051 ? _Queue10_UInt8_13_io_deq_bits : _T_4050 ? _Queue10_UInt8_12_io_deq_bits : _T_4049 ? _Queue10_UInt8_11_io_deq_bits : _T_4048 ? _Queue10_UInt8_10_io_deq_bits : _T_4047 ? _Queue10_UInt8_9_io_deq_bits : _T_4046 ? _Queue10_UInt8_8_io_deq_bits : _T_4045 ? _Queue10_UInt8_7_io_deq_bits : _T_4044 ? _Queue10_UInt8_6_io_deq_bits : _T_4043 ? _Queue10_UInt8_5_io_deq_bits : _T_4042 ? _Queue10_UInt8_4_io_deq_bits : _T_4041 ? _Queue10_UInt8_3_io_deq_bits : _T_4040 ? _Queue10_UInt8_2_io_deq_bits : _T_4039 ? _Queue10_UInt8_1_io_deq_bits : _T_4038 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_24 = _T_4069 ? _Queue10_UInt8_31_io_deq_valid : _T_4068 ? _Queue10_UInt8_30_io_deq_valid : _T_4067 ? _Queue10_UInt8_29_io_deq_valid : _T_4066 ? _Queue10_UInt8_28_io_deq_valid : _T_4065 ? _Queue10_UInt8_27_io_deq_valid : _T_4064 ? _Queue10_UInt8_26_io_deq_valid : _T_4063 ? _Queue10_UInt8_25_io_deq_valid : _T_4062 ? _Queue10_UInt8_24_io_deq_valid : _T_4061 ? _Queue10_UInt8_23_io_deq_valid : _T_4060 ? _Queue10_UInt8_22_io_deq_valid : _T_4059 ? _Queue10_UInt8_21_io_deq_valid : _T_4058 ? _Queue10_UInt8_20_io_deq_valid : _T_4057 ? _Queue10_UInt8_19_io_deq_valid : _T_4056 ? _Queue10_UInt8_18_io_deq_valid : _T_4055 ? _Queue10_UInt8_17_io_deq_valid : _T_4054 ? _Queue10_UInt8_16_io_deq_valid : _T_4053 ? _Queue10_UInt8_15_io_deq_valid : _T_4052 ? _Queue10_UInt8_14_io_deq_valid : _T_4051 ? _Queue10_UInt8_13_io_deq_valid : _T_4050 ? _Queue10_UInt8_12_io_deq_valid : _T_4049 ? _Queue10_UInt8_11_io_deq_valid : _T_4048 ? _Queue10_UInt8_10_io_deq_valid : _T_4047 ? _Queue10_UInt8_9_io_deq_valid : _T_4046 ? _Queue10_UInt8_8_io_deq_valid : _T_4045 ? _Queue10_UInt8_7_io_deq_valid : _T_4044 ? _Queue10_UInt8_6_io_deq_valid : _T_4043 ? _Queue10_UInt8_5_io_deq_valid : _T_4042 ? _Queue10_UInt8_4_io_deq_valid : _T_4041 ? _Queue10_UInt8_3_io_deq_valid : _T_4040 ? _Queue10_UInt8_2_io_deq_valid : _T_4039 ? _Queue10_UInt8_1_io_deq_valid : _T_4038 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_114 = _remapindex_T_25 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_25 = _GEN_114[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4070 = remapindex_25 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4071 = remapindex_25 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4072 = remapindex_25 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4073 = remapindex_25 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4074 = remapindex_25 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4075 = remapindex_25 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4076 = remapindex_25 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4077 = remapindex_25 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4078 = remapindex_25 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4079 = remapindex_25 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4080 = remapindex_25 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4081 = remapindex_25 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4082 = remapindex_25 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4083 = remapindex_25 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4084 = remapindex_25 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4085 = remapindex_25 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4086 = remapindex_25 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4087 = remapindex_25 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4088 = remapindex_25 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4089 = remapindex_25 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4090 = remapindex_25 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4091 = remapindex_25 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4092 = remapindex_25 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4093 = remapindex_25 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4094 = remapindex_25 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4095 = remapindex_25 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4096 = remapindex_25 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4097 = remapindex_25 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4098 = remapindex_25 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4099 = remapindex_25 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4100 = remapindex_25 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4101 = remapindex_25 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_25 = _T_4101 ? _Queue10_UInt8_31_io_deq_bits : _T_4100 ? _Queue10_UInt8_30_io_deq_bits : _T_4099 ? _Queue10_UInt8_29_io_deq_bits : _T_4098 ? _Queue10_UInt8_28_io_deq_bits : _T_4097 ? _Queue10_UInt8_27_io_deq_bits : _T_4096 ? _Queue10_UInt8_26_io_deq_bits : _T_4095 ? _Queue10_UInt8_25_io_deq_bits : _T_4094 ? _Queue10_UInt8_24_io_deq_bits : _T_4093 ? _Queue10_UInt8_23_io_deq_bits : _T_4092 ? _Queue10_UInt8_22_io_deq_bits : _T_4091 ? _Queue10_UInt8_21_io_deq_bits : _T_4090 ? _Queue10_UInt8_20_io_deq_bits : _T_4089 ? _Queue10_UInt8_19_io_deq_bits : _T_4088 ? _Queue10_UInt8_18_io_deq_bits : _T_4087 ? _Queue10_UInt8_17_io_deq_bits : _T_4086 ? _Queue10_UInt8_16_io_deq_bits : _T_4085 ? _Queue10_UInt8_15_io_deq_bits : _T_4084 ? _Queue10_UInt8_14_io_deq_bits : _T_4083 ? _Queue10_UInt8_13_io_deq_bits : _T_4082 ? _Queue10_UInt8_12_io_deq_bits : _T_4081 ? _Queue10_UInt8_11_io_deq_bits : _T_4080 ? _Queue10_UInt8_10_io_deq_bits : _T_4079 ? _Queue10_UInt8_9_io_deq_bits : _T_4078 ? _Queue10_UInt8_8_io_deq_bits : _T_4077 ? _Queue10_UInt8_7_io_deq_bits : _T_4076 ? _Queue10_UInt8_6_io_deq_bits : _T_4075 ? _Queue10_UInt8_5_io_deq_bits : _T_4074 ? _Queue10_UInt8_4_io_deq_bits : _T_4073 ? _Queue10_UInt8_3_io_deq_bits : _T_4072 ? _Queue10_UInt8_2_io_deq_bits : _T_4071 ? _Queue10_UInt8_1_io_deq_bits : _T_4070 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_25 = _T_4101 ? _Queue10_UInt8_31_io_deq_valid : _T_4100 ? _Queue10_UInt8_30_io_deq_valid : _T_4099 ? _Queue10_UInt8_29_io_deq_valid : _T_4098 ? _Queue10_UInt8_28_io_deq_valid : _T_4097 ? _Queue10_UInt8_27_io_deq_valid : _T_4096 ? _Queue10_UInt8_26_io_deq_valid : _T_4095 ? _Queue10_UInt8_25_io_deq_valid : _T_4094 ? _Queue10_UInt8_24_io_deq_valid : _T_4093 ? _Queue10_UInt8_23_io_deq_valid : _T_4092 ? _Queue10_UInt8_22_io_deq_valid : _T_4091 ? _Queue10_UInt8_21_io_deq_valid : _T_4090 ? _Queue10_UInt8_20_io_deq_valid : _T_4089 ? _Queue10_UInt8_19_io_deq_valid : _T_4088 ? _Queue10_UInt8_18_io_deq_valid : _T_4087 ? _Queue10_UInt8_17_io_deq_valid : _T_4086 ? _Queue10_UInt8_16_io_deq_valid : _T_4085 ? _Queue10_UInt8_15_io_deq_valid : _T_4084 ? _Queue10_UInt8_14_io_deq_valid : _T_4083 ? _Queue10_UInt8_13_io_deq_valid : _T_4082 ? _Queue10_UInt8_12_io_deq_valid : _T_4081 ? _Queue10_UInt8_11_io_deq_valid : _T_4080 ? _Queue10_UInt8_10_io_deq_valid : _T_4079 ? _Queue10_UInt8_9_io_deq_valid : _T_4078 ? _Queue10_UInt8_8_io_deq_valid : _T_4077 ? _Queue10_UInt8_7_io_deq_valid : _T_4076 ? _Queue10_UInt8_6_io_deq_valid : _T_4075 ? _Queue10_UInt8_5_io_deq_valid : _T_4074 ? _Queue10_UInt8_4_io_deq_valid : _T_4073 ? _Queue10_UInt8_3_io_deq_valid : _T_4072 ? _Queue10_UInt8_2_io_deq_valid : _T_4071 ? _Queue10_UInt8_1_io_deq_valid : _T_4070 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_115 = _remapindex_T_26 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_26 = _GEN_115[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4102 = remapindex_26 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4103 = remapindex_26 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4104 = remapindex_26 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4105 = remapindex_26 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4106 = remapindex_26 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4107 = remapindex_26 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4108 = remapindex_26 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4109 = remapindex_26 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4110 = remapindex_26 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4111 = remapindex_26 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4112 = remapindex_26 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4113 = remapindex_26 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4114 = remapindex_26 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4115 = remapindex_26 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4116 = remapindex_26 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4117 = remapindex_26 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4118 = remapindex_26 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4119 = remapindex_26 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4120 = remapindex_26 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4121 = remapindex_26 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4122 = remapindex_26 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4123 = remapindex_26 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4124 = remapindex_26 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4125 = remapindex_26 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4126 = remapindex_26 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4127 = remapindex_26 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4128 = remapindex_26 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4129 = remapindex_26 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4130 = remapindex_26 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4131 = remapindex_26 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4132 = remapindex_26 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4133 = remapindex_26 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_26 = _T_4133 ? _Queue10_UInt8_31_io_deq_bits : _T_4132 ? _Queue10_UInt8_30_io_deq_bits : _T_4131 ? _Queue10_UInt8_29_io_deq_bits : _T_4130 ? _Queue10_UInt8_28_io_deq_bits : _T_4129 ? _Queue10_UInt8_27_io_deq_bits : _T_4128 ? _Queue10_UInt8_26_io_deq_bits : _T_4127 ? _Queue10_UInt8_25_io_deq_bits : _T_4126 ? _Queue10_UInt8_24_io_deq_bits : _T_4125 ? _Queue10_UInt8_23_io_deq_bits : _T_4124 ? _Queue10_UInt8_22_io_deq_bits : _T_4123 ? _Queue10_UInt8_21_io_deq_bits : _T_4122 ? _Queue10_UInt8_20_io_deq_bits : _T_4121 ? _Queue10_UInt8_19_io_deq_bits : _T_4120 ? _Queue10_UInt8_18_io_deq_bits : _T_4119 ? _Queue10_UInt8_17_io_deq_bits : _T_4118 ? _Queue10_UInt8_16_io_deq_bits : _T_4117 ? _Queue10_UInt8_15_io_deq_bits : _T_4116 ? _Queue10_UInt8_14_io_deq_bits : _T_4115 ? _Queue10_UInt8_13_io_deq_bits : _T_4114 ? _Queue10_UInt8_12_io_deq_bits : _T_4113 ? _Queue10_UInt8_11_io_deq_bits : _T_4112 ? _Queue10_UInt8_10_io_deq_bits : _T_4111 ? _Queue10_UInt8_9_io_deq_bits : _T_4110 ? _Queue10_UInt8_8_io_deq_bits : _T_4109 ? _Queue10_UInt8_7_io_deq_bits : _T_4108 ? _Queue10_UInt8_6_io_deq_bits : _T_4107 ? _Queue10_UInt8_5_io_deq_bits : _T_4106 ? _Queue10_UInt8_4_io_deq_bits : _T_4105 ? _Queue10_UInt8_3_io_deq_bits : _T_4104 ? _Queue10_UInt8_2_io_deq_bits : _T_4103 ? _Queue10_UInt8_1_io_deq_bits : _T_4102 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_26 = _T_4133 ? _Queue10_UInt8_31_io_deq_valid : _T_4132 ? _Queue10_UInt8_30_io_deq_valid : _T_4131 ? _Queue10_UInt8_29_io_deq_valid : _T_4130 ? _Queue10_UInt8_28_io_deq_valid : _T_4129 ? _Queue10_UInt8_27_io_deq_valid : _T_4128 ? _Queue10_UInt8_26_io_deq_valid : _T_4127 ? _Queue10_UInt8_25_io_deq_valid : _T_4126 ? _Queue10_UInt8_24_io_deq_valid : _T_4125 ? _Queue10_UInt8_23_io_deq_valid : _T_4124 ? _Queue10_UInt8_22_io_deq_valid : _T_4123 ? _Queue10_UInt8_21_io_deq_valid : _T_4122 ? _Queue10_UInt8_20_io_deq_valid : _T_4121 ? _Queue10_UInt8_19_io_deq_valid : _T_4120 ? _Queue10_UInt8_18_io_deq_valid : _T_4119 ? _Queue10_UInt8_17_io_deq_valid : _T_4118 ? _Queue10_UInt8_16_io_deq_valid : _T_4117 ? _Queue10_UInt8_15_io_deq_valid : _T_4116 ? _Queue10_UInt8_14_io_deq_valid : _T_4115 ? _Queue10_UInt8_13_io_deq_valid : _T_4114 ? _Queue10_UInt8_12_io_deq_valid : _T_4113 ? _Queue10_UInt8_11_io_deq_valid : _T_4112 ? _Queue10_UInt8_10_io_deq_valid : _T_4111 ? _Queue10_UInt8_9_io_deq_valid : _T_4110 ? _Queue10_UInt8_8_io_deq_valid : _T_4109 ? _Queue10_UInt8_7_io_deq_valid : _T_4108 ? _Queue10_UInt8_6_io_deq_valid : _T_4107 ? _Queue10_UInt8_5_io_deq_valid : _T_4106 ? _Queue10_UInt8_4_io_deq_valid : _T_4105 ? _Queue10_UInt8_3_io_deq_valid : _T_4104 ? _Queue10_UInt8_2_io_deq_valid : _T_4103 ? _Queue10_UInt8_1_io_deq_valid : _T_4102 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_116 = _remapindex_T_27 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_27 = _GEN_116[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4134 = remapindex_27 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4135 = remapindex_27 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4136 = remapindex_27 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4137 = remapindex_27 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4138 = remapindex_27 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4139 = remapindex_27 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4140 = remapindex_27 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4141 = remapindex_27 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4142 = remapindex_27 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4143 = remapindex_27 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4144 = remapindex_27 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4145 = remapindex_27 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4146 = remapindex_27 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4147 = remapindex_27 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4148 = remapindex_27 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4149 = remapindex_27 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4150 = remapindex_27 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4151 = remapindex_27 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4152 = remapindex_27 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4153 = remapindex_27 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4154 = remapindex_27 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4155 = remapindex_27 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4156 = remapindex_27 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4157 = remapindex_27 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4158 = remapindex_27 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4159 = remapindex_27 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4160 = remapindex_27 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4161 = remapindex_27 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4162 = remapindex_27 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4163 = remapindex_27 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4164 = remapindex_27 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4165 = remapindex_27 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_27 = _T_4165 ? _Queue10_UInt8_31_io_deq_bits : _T_4164 ? _Queue10_UInt8_30_io_deq_bits : _T_4163 ? _Queue10_UInt8_29_io_deq_bits : _T_4162 ? _Queue10_UInt8_28_io_deq_bits : _T_4161 ? _Queue10_UInt8_27_io_deq_bits : _T_4160 ? _Queue10_UInt8_26_io_deq_bits : _T_4159 ? _Queue10_UInt8_25_io_deq_bits : _T_4158 ? _Queue10_UInt8_24_io_deq_bits : _T_4157 ? _Queue10_UInt8_23_io_deq_bits : _T_4156 ? _Queue10_UInt8_22_io_deq_bits : _T_4155 ? _Queue10_UInt8_21_io_deq_bits : _T_4154 ? _Queue10_UInt8_20_io_deq_bits : _T_4153 ? _Queue10_UInt8_19_io_deq_bits : _T_4152 ? _Queue10_UInt8_18_io_deq_bits : _T_4151 ? _Queue10_UInt8_17_io_deq_bits : _T_4150 ? _Queue10_UInt8_16_io_deq_bits : _T_4149 ? _Queue10_UInt8_15_io_deq_bits : _T_4148 ? _Queue10_UInt8_14_io_deq_bits : _T_4147 ? _Queue10_UInt8_13_io_deq_bits : _T_4146 ? _Queue10_UInt8_12_io_deq_bits : _T_4145 ? _Queue10_UInt8_11_io_deq_bits : _T_4144 ? _Queue10_UInt8_10_io_deq_bits : _T_4143 ? _Queue10_UInt8_9_io_deq_bits : _T_4142 ? _Queue10_UInt8_8_io_deq_bits : _T_4141 ? _Queue10_UInt8_7_io_deq_bits : _T_4140 ? _Queue10_UInt8_6_io_deq_bits : _T_4139 ? _Queue10_UInt8_5_io_deq_bits : _T_4138 ? _Queue10_UInt8_4_io_deq_bits : _T_4137 ? _Queue10_UInt8_3_io_deq_bits : _T_4136 ? _Queue10_UInt8_2_io_deq_bits : _T_4135 ? _Queue10_UInt8_1_io_deq_bits : _T_4134 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_27 = _T_4165 ? _Queue10_UInt8_31_io_deq_valid : _T_4164 ? _Queue10_UInt8_30_io_deq_valid : _T_4163 ? _Queue10_UInt8_29_io_deq_valid : _T_4162 ? _Queue10_UInt8_28_io_deq_valid : _T_4161 ? _Queue10_UInt8_27_io_deq_valid : _T_4160 ? _Queue10_UInt8_26_io_deq_valid : _T_4159 ? _Queue10_UInt8_25_io_deq_valid : _T_4158 ? _Queue10_UInt8_24_io_deq_valid : _T_4157 ? _Queue10_UInt8_23_io_deq_valid : _T_4156 ? _Queue10_UInt8_22_io_deq_valid : _T_4155 ? _Queue10_UInt8_21_io_deq_valid : _T_4154 ? _Queue10_UInt8_20_io_deq_valid : _T_4153 ? _Queue10_UInt8_19_io_deq_valid : _T_4152 ? _Queue10_UInt8_18_io_deq_valid : _T_4151 ? _Queue10_UInt8_17_io_deq_valid : _T_4150 ? _Queue10_UInt8_16_io_deq_valid : _T_4149 ? _Queue10_UInt8_15_io_deq_valid : _T_4148 ? _Queue10_UInt8_14_io_deq_valid : _T_4147 ? _Queue10_UInt8_13_io_deq_valid : _T_4146 ? _Queue10_UInt8_12_io_deq_valid : _T_4145 ? _Queue10_UInt8_11_io_deq_valid : _T_4144 ? _Queue10_UInt8_10_io_deq_valid : _T_4143 ? _Queue10_UInt8_9_io_deq_valid : _T_4142 ? _Queue10_UInt8_8_io_deq_valid : _T_4141 ? _Queue10_UInt8_7_io_deq_valid : _T_4140 ? _Queue10_UInt8_6_io_deq_valid : _T_4139 ? _Queue10_UInt8_5_io_deq_valid : _T_4138 ? _Queue10_UInt8_4_io_deq_valid : _T_4137 ? _Queue10_UInt8_3_io_deq_valid : _T_4136 ? _Queue10_UInt8_2_io_deq_valid : _T_4135 ? _Queue10_UInt8_1_io_deq_valid : _T_4134 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_117 = _remapindex_T_28 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_28 = _GEN_117[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4166 = remapindex_28 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4167 = remapindex_28 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4168 = remapindex_28 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4169 = remapindex_28 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4170 = remapindex_28 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4171 = remapindex_28 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4172 = remapindex_28 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4173 = remapindex_28 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4174 = remapindex_28 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4175 = remapindex_28 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4176 = remapindex_28 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4177 = remapindex_28 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4178 = remapindex_28 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4179 = remapindex_28 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4180 = remapindex_28 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4181 = remapindex_28 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4182 = remapindex_28 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4183 = remapindex_28 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4184 = remapindex_28 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4185 = remapindex_28 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4186 = remapindex_28 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4187 = remapindex_28 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4188 = remapindex_28 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4189 = remapindex_28 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4190 = remapindex_28 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4191 = remapindex_28 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4192 = remapindex_28 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4193 = remapindex_28 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4194 = remapindex_28 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4195 = remapindex_28 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4196 = remapindex_28 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4197 = remapindex_28 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_28 = _T_4197 ? _Queue10_UInt8_31_io_deq_bits : _T_4196 ? _Queue10_UInt8_30_io_deq_bits : _T_4195 ? _Queue10_UInt8_29_io_deq_bits : _T_4194 ? _Queue10_UInt8_28_io_deq_bits : _T_4193 ? _Queue10_UInt8_27_io_deq_bits : _T_4192 ? _Queue10_UInt8_26_io_deq_bits : _T_4191 ? _Queue10_UInt8_25_io_deq_bits : _T_4190 ? _Queue10_UInt8_24_io_deq_bits : _T_4189 ? _Queue10_UInt8_23_io_deq_bits : _T_4188 ? _Queue10_UInt8_22_io_deq_bits : _T_4187 ? _Queue10_UInt8_21_io_deq_bits : _T_4186 ? _Queue10_UInt8_20_io_deq_bits : _T_4185 ? _Queue10_UInt8_19_io_deq_bits : _T_4184 ? _Queue10_UInt8_18_io_deq_bits : _T_4183 ? _Queue10_UInt8_17_io_deq_bits : _T_4182 ? _Queue10_UInt8_16_io_deq_bits : _T_4181 ? _Queue10_UInt8_15_io_deq_bits : _T_4180 ? _Queue10_UInt8_14_io_deq_bits : _T_4179 ? _Queue10_UInt8_13_io_deq_bits : _T_4178 ? _Queue10_UInt8_12_io_deq_bits : _T_4177 ? _Queue10_UInt8_11_io_deq_bits : _T_4176 ? _Queue10_UInt8_10_io_deq_bits : _T_4175 ? _Queue10_UInt8_9_io_deq_bits : _T_4174 ? _Queue10_UInt8_8_io_deq_bits : _T_4173 ? _Queue10_UInt8_7_io_deq_bits : _T_4172 ? _Queue10_UInt8_6_io_deq_bits : _T_4171 ? _Queue10_UInt8_5_io_deq_bits : _T_4170 ? _Queue10_UInt8_4_io_deq_bits : _T_4169 ? _Queue10_UInt8_3_io_deq_bits : _T_4168 ? _Queue10_UInt8_2_io_deq_bits : _T_4167 ? _Queue10_UInt8_1_io_deq_bits : _T_4166 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_28 = _T_4197 ? _Queue10_UInt8_31_io_deq_valid : _T_4196 ? _Queue10_UInt8_30_io_deq_valid : _T_4195 ? _Queue10_UInt8_29_io_deq_valid : _T_4194 ? _Queue10_UInt8_28_io_deq_valid : _T_4193 ? _Queue10_UInt8_27_io_deq_valid : _T_4192 ? _Queue10_UInt8_26_io_deq_valid : _T_4191 ? _Queue10_UInt8_25_io_deq_valid : _T_4190 ? _Queue10_UInt8_24_io_deq_valid : _T_4189 ? _Queue10_UInt8_23_io_deq_valid : _T_4188 ? _Queue10_UInt8_22_io_deq_valid : _T_4187 ? _Queue10_UInt8_21_io_deq_valid : _T_4186 ? _Queue10_UInt8_20_io_deq_valid : _T_4185 ? _Queue10_UInt8_19_io_deq_valid : _T_4184 ? _Queue10_UInt8_18_io_deq_valid : _T_4183 ? _Queue10_UInt8_17_io_deq_valid : _T_4182 ? _Queue10_UInt8_16_io_deq_valid : _T_4181 ? _Queue10_UInt8_15_io_deq_valid : _T_4180 ? _Queue10_UInt8_14_io_deq_valid : _T_4179 ? _Queue10_UInt8_13_io_deq_valid : _T_4178 ? _Queue10_UInt8_12_io_deq_valid : _T_4177 ? _Queue10_UInt8_11_io_deq_valid : _T_4176 ? _Queue10_UInt8_10_io_deq_valid : _T_4175 ? _Queue10_UInt8_9_io_deq_valid : _T_4174 ? _Queue10_UInt8_8_io_deq_valid : _T_4173 ? _Queue10_UInt8_7_io_deq_valid : _T_4172 ? _Queue10_UInt8_6_io_deq_valid : _T_4171 ? _Queue10_UInt8_5_io_deq_valid : _T_4170 ? _Queue10_UInt8_4_io_deq_valid : _T_4169 ? _Queue10_UInt8_3_io_deq_valid : _T_4168 ? _Queue10_UInt8_2_io_deq_valid : _T_4167 ? _Queue10_UInt8_1_io_deq_valid : _T_4166 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_118 = _remapindex_T_29 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_29 = _GEN_118[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4198 = remapindex_29 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4199 = remapindex_29 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4200 = remapindex_29 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4201 = remapindex_29 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4202 = remapindex_29 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4203 = remapindex_29 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4204 = remapindex_29 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4205 = remapindex_29 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4206 = remapindex_29 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4207 = remapindex_29 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4208 = remapindex_29 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4209 = remapindex_29 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4210 = remapindex_29 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4211 = remapindex_29 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4212 = remapindex_29 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4213 = remapindex_29 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4214 = remapindex_29 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4215 = remapindex_29 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4216 = remapindex_29 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4217 = remapindex_29 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4218 = remapindex_29 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4219 = remapindex_29 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4220 = remapindex_29 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4221 = remapindex_29 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4222 = remapindex_29 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4223 = remapindex_29 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4224 = remapindex_29 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4225 = remapindex_29 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4226 = remapindex_29 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4227 = remapindex_29 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4228 = remapindex_29 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4229 = remapindex_29 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_29 = _T_4229 ? _Queue10_UInt8_31_io_deq_bits : _T_4228 ? _Queue10_UInt8_30_io_deq_bits : _T_4227 ? _Queue10_UInt8_29_io_deq_bits : _T_4226 ? _Queue10_UInt8_28_io_deq_bits : _T_4225 ? _Queue10_UInt8_27_io_deq_bits : _T_4224 ? _Queue10_UInt8_26_io_deq_bits : _T_4223 ? _Queue10_UInt8_25_io_deq_bits : _T_4222 ? _Queue10_UInt8_24_io_deq_bits : _T_4221 ? _Queue10_UInt8_23_io_deq_bits : _T_4220 ? _Queue10_UInt8_22_io_deq_bits : _T_4219 ? _Queue10_UInt8_21_io_deq_bits : _T_4218 ? _Queue10_UInt8_20_io_deq_bits : _T_4217 ? _Queue10_UInt8_19_io_deq_bits : _T_4216 ? _Queue10_UInt8_18_io_deq_bits : _T_4215 ? _Queue10_UInt8_17_io_deq_bits : _T_4214 ? _Queue10_UInt8_16_io_deq_bits : _T_4213 ? _Queue10_UInt8_15_io_deq_bits : _T_4212 ? _Queue10_UInt8_14_io_deq_bits : _T_4211 ? _Queue10_UInt8_13_io_deq_bits : _T_4210 ? _Queue10_UInt8_12_io_deq_bits : _T_4209 ? _Queue10_UInt8_11_io_deq_bits : _T_4208 ? _Queue10_UInt8_10_io_deq_bits : _T_4207 ? _Queue10_UInt8_9_io_deq_bits : _T_4206 ? _Queue10_UInt8_8_io_deq_bits : _T_4205 ? _Queue10_UInt8_7_io_deq_bits : _T_4204 ? _Queue10_UInt8_6_io_deq_bits : _T_4203 ? _Queue10_UInt8_5_io_deq_bits : _T_4202 ? _Queue10_UInt8_4_io_deq_bits : _T_4201 ? _Queue10_UInt8_3_io_deq_bits : _T_4200 ? _Queue10_UInt8_2_io_deq_bits : _T_4199 ? _Queue10_UInt8_1_io_deq_bits : _T_4198 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_29 = _T_4229 ? _Queue10_UInt8_31_io_deq_valid : _T_4228 ? _Queue10_UInt8_30_io_deq_valid : _T_4227 ? _Queue10_UInt8_29_io_deq_valid : _T_4226 ? _Queue10_UInt8_28_io_deq_valid : _T_4225 ? _Queue10_UInt8_27_io_deq_valid : _T_4224 ? _Queue10_UInt8_26_io_deq_valid : _T_4223 ? _Queue10_UInt8_25_io_deq_valid : _T_4222 ? _Queue10_UInt8_24_io_deq_valid : _T_4221 ? _Queue10_UInt8_23_io_deq_valid : _T_4220 ? _Queue10_UInt8_22_io_deq_valid : _T_4219 ? _Queue10_UInt8_21_io_deq_valid : _T_4218 ? _Queue10_UInt8_20_io_deq_valid : _T_4217 ? _Queue10_UInt8_19_io_deq_valid : _T_4216 ? _Queue10_UInt8_18_io_deq_valid : _T_4215 ? _Queue10_UInt8_17_io_deq_valid : _T_4214 ? _Queue10_UInt8_16_io_deq_valid : _T_4213 ? _Queue10_UInt8_15_io_deq_valid : _T_4212 ? _Queue10_UInt8_14_io_deq_valid : _T_4211 ? _Queue10_UInt8_13_io_deq_valid : _T_4210 ? _Queue10_UInt8_12_io_deq_valid : _T_4209 ? _Queue10_UInt8_11_io_deq_valid : _T_4208 ? _Queue10_UInt8_10_io_deq_valid : _T_4207 ? _Queue10_UInt8_9_io_deq_valid : _T_4206 ? _Queue10_UInt8_8_io_deq_valid : _T_4205 ? _Queue10_UInt8_7_io_deq_valid : _T_4204 ? _Queue10_UInt8_6_io_deq_valid : _T_4203 ? _Queue10_UInt8_5_io_deq_valid : _T_4202 ? _Queue10_UInt8_4_io_deq_valid : _T_4201 ? _Queue10_UInt8_3_io_deq_valid : _T_4200 ? _Queue10_UInt8_2_io_deq_valid : _T_4199 ? _Queue10_UInt8_1_io_deq_valid : _T_4198 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_119 = _remapindex_T_30 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_30 = _GEN_119[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4230 = remapindex_30 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4231 = remapindex_30 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4232 = remapindex_30 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4233 = remapindex_30 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4234 = remapindex_30 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4235 = remapindex_30 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4236 = remapindex_30 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4237 = remapindex_30 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4238 = remapindex_30 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4239 = remapindex_30 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4240 = remapindex_30 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4241 = remapindex_30 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4242 = remapindex_30 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4243 = remapindex_30 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4244 = remapindex_30 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4245 = remapindex_30 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4246 = remapindex_30 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4247 = remapindex_30 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4248 = remapindex_30 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4249 = remapindex_30 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4250 = remapindex_30 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4251 = remapindex_30 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4252 = remapindex_30 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4253 = remapindex_30 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4254 = remapindex_30 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4255 = remapindex_30 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4256 = remapindex_30 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4257 = remapindex_30 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4258 = remapindex_30 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4259 = remapindex_30 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4260 = remapindex_30 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4261 = remapindex_30 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_30 = _T_4261 ? _Queue10_UInt8_31_io_deq_bits : _T_4260 ? _Queue10_UInt8_30_io_deq_bits : _T_4259 ? _Queue10_UInt8_29_io_deq_bits : _T_4258 ? _Queue10_UInt8_28_io_deq_bits : _T_4257 ? _Queue10_UInt8_27_io_deq_bits : _T_4256 ? _Queue10_UInt8_26_io_deq_bits : _T_4255 ? _Queue10_UInt8_25_io_deq_bits : _T_4254 ? _Queue10_UInt8_24_io_deq_bits : _T_4253 ? _Queue10_UInt8_23_io_deq_bits : _T_4252 ? _Queue10_UInt8_22_io_deq_bits : _T_4251 ? _Queue10_UInt8_21_io_deq_bits : _T_4250 ? _Queue10_UInt8_20_io_deq_bits : _T_4249 ? _Queue10_UInt8_19_io_deq_bits : _T_4248 ? _Queue10_UInt8_18_io_deq_bits : _T_4247 ? _Queue10_UInt8_17_io_deq_bits : _T_4246 ? _Queue10_UInt8_16_io_deq_bits : _T_4245 ? _Queue10_UInt8_15_io_deq_bits : _T_4244 ? _Queue10_UInt8_14_io_deq_bits : _T_4243 ? _Queue10_UInt8_13_io_deq_bits : _T_4242 ? _Queue10_UInt8_12_io_deq_bits : _T_4241 ? _Queue10_UInt8_11_io_deq_bits : _T_4240 ? _Queue10_UInt8_10_io_deq_bits : _T_4239 ? _Queue10_UInt8_9_io_deq_bits : _T_4238 ? _Queue10_UInt8_8_io_deq_bits : _T_4237 ? _Queue10_UInt8_7_io_deq_bits : _T_4236 ? _Queue10_UInt8_6_io_deq_bits : _T_4235 ? _Queue10_UInt8_5_io_deq_bits : _T_4234 ? _Queue10_UInt8_4_io_deq_bits : _T_4233 ? _Queue10_UInt8_3_io_deq_bits : _T_4232 ? _Queue10_UInt8_2_io_deq_bits : _T_4231 ? _Queue10_UInt8_1_io_deq_bits : _T_4230 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_30 = _T_4261 ? _Queue10_UInt8_31_io_deq_valid : _T_4260 ? _Queue10_UInt8_30_io_deq_valid : _T_4259 ? _Queue10_UInt8_29_io_deq_valid : _T_4258 ? _Queue10_UInt8_28_io_deq_valid : _T_4257 ? _Queue10_UInt8_27_io_deq_valid : _T_4256 ? _Queue10_UInt8_26_io_deq_valid : _T_4255 ? _Queue10_UInt8_25_io_deq_valid : _T_4254 ? _Queue10_UInt8_24_io_deq_valid : _T_4253 ? _Queue10_UInt8_23_io_deq_valid : _T_4252 ? _Queue10_UInt8_22_io_deq_valid : _T_4251 ? _Queue10_UInt8_21_io_deq_valid : _T_4250 ? _Queue10_UInt8_20_io_deq_valid : _T_4249 ? _Queue10_UInt8_19_io_deq_valid : _T_4248 ? _Queue10_UInt8_18_io_deq_valid : _T_4247 ? _Queue10_UInt8_17_io_deq_valid : _T_4246 ? _Queue10_UInt8_16_io_deq_valid : _T_4245 ? _Queue10_UInt8_15_io_deq_valid : _T_4244 ? _Queue10_UInt8_14_io_deq_valid : _T_4243 ? _Queue10_UInt8_13_io_deq_valid : _T_4242 ? _Queue10_UInt8_12_io_deq_valid : _T_4241 ? _Queue10_UInt8_11_io_deq_valid : _T_4240 ? _Queue10_UInt8_10_io_deq_valid : _T_4239 ? _Queue10_UInt8_9_io_deq_valid : _T_4238 ? _Queue10_UInt8_8_io_deq_valid : _T_4237 ? _Queue10_UInt8_7_io_deq_valid : _T_4236 ? _Queue10_UInt8_6_io_deq_valid : _T_4235 ? _Queue10_UInt8_5_io_deq_valid : _T_4234 ? _Queue10_UInt8_4_io_deq_valid : _T_4233 ? _Queue10_UInt8_3_io_deq_valid : _T_4232 ? _Queue10_UInt8_2_io_deq_valid : _T_4231 ? _Queue10_UInt8_1_io_deq_valid : _T_4230 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[ZstdLitRotBuf.scala:237:33] wire [6:0] _GEN_120 = _remapindex_T_31 % 7'h20; // @[ZstdLitRotBuf.scala:237:{33,54}] wire [5:0] remapindex_31 = _GEN_120[5:0]; // @[ZstdLitRotBuf.scala:237:54] wire _T_4262 = remapindex_31 == 6'h0; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4263 = remapindex_31 == 6'h1; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4264 = remapindex_31 == 6'h2; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4265 = remapindex_31 == 6'h3; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4266 = remapindex_31 == 6'h4; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4267 = remapindex_31 == 6'h5; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4268 = remapindex_31 == 6'h6; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4269 = remapindex_31 == 6'h7; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4270 = remapindex_31 == 6'h8; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4271 = remapindex_31 == 6'h9; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4272 = remapindex_31 == 6'hA; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4273 = remapindex_31 == 6'hB; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4274 = remapindex_31 == 6'hC; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4275 = remapindex_31 == 6'hD; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4276 = remapindex_31 == 6'hE; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4277 = remapindex_31 == 6'hF; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4278 = remapindex_31 == 6'h10; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4279 = remapindex_31 == 6'h11; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4280 = remapindex_31 == 6'h12; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4281 = remapindex_31 == 6'h13; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4282 = remapindex_31 == 6'h14; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4283 = remapindex_31 == 6'h15; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4284 = remapindex_31 == 6'h16; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4285 = remapindex_31 == 6'h17; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4286 = remapindex_31 == 6'h18; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4287 = remapindex_31 == 6'h19; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4288 = remapindex_31 == 6'h1A; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4289 = remapindex_31 == 6'h1B; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4290 = remapindex_31 == 6'h1C; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4291 = remapindex_31 == 6'h1D; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4292 = remapindex_31 == 6'h1E; // @[ZstdLitRotBuf.scala:237:54, :239:17] wire _T_4293 = remapindex_31 == 6'h1F; // @[ZstdLitRotBuf.scala:237:54, :239:17] assign remapVecData_31 = _T_4293 ? _Queue10_UInt8_31_io_deq_bits : _T_4292 ? _Queue10_UInt8_30_io_deq_bits : _T_4291 ? _Queue10_UInt8_29_io_deq_bits : _T_4290 ? _Queue10_UInt8_28_io_deq_bits : _T_4289 ? _Queue10_UInt8_27_io_deq_bits : _T_4288 ? _Queue10_UInt8_26_io_deq_bits : _T_4287 ? _Queue10_UInt8_25_io_deq_bits : _T_4286 ? _Queue10_UInt8_24_io_deq_bits : _T_4285 ? _Queue10_UInt8_23_io_deq_bits : _T_4284 ? _Queue10_UInt8_22_io_deq_bits : _T_4283 ? _Queue10_UInt8_21_io_deq_bits : _T_4282 ? _Queue10_UInt8_20_io_deq_bits : _T_4281 ? _Queue10_UInt8_19_io_deq_bits : _T_4280 ? _Queue10_UInt8_18_io_deq_bits : _T_4279 ? _Queue10_UInt8_17_io_deq_bits : _T_4278 ? _Queue10_UInt8_16_io_deq_bits : _T_4277 ? _Queue10_UInt8_15_io_deq_bits : _T_4276 ? _Queue10_UInt8_14_io_deq_bits : _T_4275 ? _Queue10_UInt8_13_io_deq_bits : _T_4274 ? _Queue10_UInt8_12_io_deq_bits : _T_4273 ? _Queue10_UInt8_11_io_deq_bits : _T_4272 ? _Queue10_UInt8_10_io_deq_bits : _T_4271 ? _Queue10_UInt8_9_io_deq_bits : _T_4270 ? _Queue10_UInt8_8_io_deq_bits : _T_4269 ? _Queue10_UInt8_7_io_deq_bits : _T_4268 ? _Queue10_UInt8_6_io_deq_bits : _T_4267 ? _Queue10_UInt8_5_io_deq_bits : _T_4266 ? _Queue10_UInt8_4_io_deq_bits : _T_4265 ? _Queue10_UInt8_3_io_deq_bits : _T_4264 ? _Queue10_UInt8_2_io_deq_bits : _T_4263 ? _Queue10_UInt8_1_io_deq_bits : _T_4262 ? _Queue10_UInt8_io_deq_bits : 8'h0; // @[ZstdLitRotBuf.scala:173:52, :225:26, :231:27, :239:{17,33}, :240:31] assign remapVecValids_31 = _T_4293 ? _Queue10_UInt8_31_io_deq_valid : _T_4292 ? _Queue10_UInt8_30_io_deq_valid : _T_4291 ? _Queue10_UInt8_29_io_deq_valid : _T_4290 ? _Queue10_UInt8_28_io_deq_valid : _T_4289 ? _Queue10_UInt8_27_io_deq_valid : _T_4288 ? _Queue10_UInt8_26_io_deq_valid : _T_4287 ? _Queue10_UInt8_25_io_deq_valid : _T_4286 ? _Queue10_UInt8_24_io_deq_valid : _T_4285 ? _Queue10_UInt8_23_io_deq_valid : _T_4284 ? _Queue10_UInt8_22_io_deq_valid : _T_4283 ? _Queue10_UInt8_21_io_deq_valid : _T_4282 ? _Queue10_UInt8_20_io_deq_valid : _T_4281 ? _Queue10_UInt8_19_io_deq_valid : _T_4280 ? _Queue10_UInt8_18_io_deq_valid : _T_4279 ? _Queue10_UInt8_17_io_deq_valid : _T_4278 ? _Queue10_UInt8_16_io_deq_valid : _T_4277 ? _Queue10_UInt8_15_io_deq_valid : _T_4276 ? _Queue10_UInt8_14_io_deq_valid : _T_4275 ? _Queue10_UInt8_13_io_deq_valid : _T_4274 ? _Queue10_UInt8_12_io_deq_valid : _T_4273 ? _Queue10_UInt8_11_io_deq_valid : _T_4272 ? _Queue10_UInt8_10_io_deq_valid : _T_4271 ? _Queue10_UInt8_9_io_deq_valid : _T_4270 ? _Queue10_UInt8_8_io_deq_valid : _T_4269 ? _Queue10_UInt8_7_io_deq_valid : _T_4268 ? _Queue10_UInt8_6_io_deq_valid : _T_4267 ? _Queue10_UInt8_5_io_deq_valid : _T_4266 ? _Queue10_UInt8_4_io_deq_valid : _T_4265 ? _Queue10_UInt8_3_io_deq_valid : _T_4264 ? _Queue10_UInt8_2_io_deq_valid : _T_4263 ? _Queue10_UInt8_1_io_deq_valid : _T_4262 & _Queue10_UInt8_io_deq_valid; // @[ZstdLitRotBuf.scala:173:52, :226:28, :232:29, :239:{17,33}, :241:33] wire [15:0] io_consumer_output_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_lo_lo = {io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_lo_hi = {io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_lo_lo = {io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_hi_lo = {io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_lo_hi_hi = {io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_lo_hi = {io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [127:0] io_consumer_output_data_lo = {io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_lo_lo = {io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_lo_hi = {io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_hi_lo = {io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_hi_lo = {io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [15:0] io_consumer_output_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [15:0] io_consumer_output_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[ZstdLitRotBuf.scala:225:26, :246:33] wire [31:0] io_consumer_output_data_hi_hi_hi = {io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [63:0] io_consumer_output_data_hi_hi = {io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] wire [127:0] io_consumer_output_data_hi = {io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo}; // @[ZstdLitRotBuf.scala:246:33] assign _io_consumer_output_data_T = {io_consumer_output_data_hi, io_consumer_output_data_lo}; // @[ZstdLitRotBuf.scala:246:33] assign io_consumer_output_data_0 = _io_consumer_output_data_T; // @[ZstdLitRotBuf.scala:152:7, :246:33] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[ZstdLitRotBuf.scala:185:{75,91}, :226:28, :249:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[ZstdLitRotBuf.scala:185:{75,91}, :226:28, :249:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[ZstdLitRotBuf.scala:226:28, :249:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[ZstdLitRotBuf.scala:226:28, :249:60] assign enough_data = |count_valids; // @[ZstdLitRotBuf.scala:249:60, :251:34] assign io_consumer_output_valid_0 = enough_data; // @[ZstdLitRotBuf.scala:152:7, :251:34] assign io_consumer_available_output_bytes_0 = count_valids[5:0]; // @[ZstdLitRotBuf.scala:152:7, :249:60, :253:38] wire _T_4303 = io_consumer_output_ready_0 & enough_data; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_4303; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_4303; // @[Misc.scala:29:18] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38]

Generate the Verilog code corresponding to this FIRRTL code module SourceB_2 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}} regreset remain : UInt<1>, clock, reset, UInt<1>(0h0) wire remain_set : UInt<1> connect remain_set, UInt<1>(0h0) wire remain_clr : UInt<1> connect remain_clr, UInt<1>(0h0) node _remain_T = or(remain, remain_set) node _remain_T_1 = not(remain_clr) node _remain_T_2 = and(_remain_T, _remain_T_1) connect remain, _remain_T_2 node busy = orr(remain) node todo = mux(busy, remain, io.req.bits.clients) node _next_T = bits(todo, 0, 0) node _next_T_1 = shl(_next_T, 1) node _next_T_2 = not(_next_T_1) node next = and(_next_T_2, todo) node _T = eq(io.req.valid, UInt<1>(0h0)) node _T_1 = neq(io.req.bits.clients, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceB.scala:59 assert (!io.req.valid || io.req.bits.clients =/= 0.U)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _T_6 = and(io.req.ready, io.req.valid) when _T_6 : connect remain_set, io.req.bits.clients wire b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect io.b, b node _b_valid_T = or(busy, io.req.valid) connect b.valid, _b_valid_T node _T_7 = and(b.ready, b.valid) when _T_7 : connect remain_clr, next node _T_8 = eq(b.ready, UInt<1>(0h0)) node _T_9 = and(b.valid, _T_8) node _tag_T = eq(busy, UInt<1>(0h0)) node _tag_T_1 = and(io.req.ready, io.req.valid) reg tag_r : UInt<9>, clock when _tag_T_1 : connect tag_r, io.req.bits.tag node tag = mux(_tag_T, io.req.bits.tag, tag_r) node _set_T = eq(busy, UInt<1>(0h0)) node _set_T_1 = and(io.req.ready, io.req.valid) reg set_r : UInt<11>, clock when _set_T_1 : connect set_r, io.req.bits.set node set = mux(_set_T, io.req.bits.set, set_r) node _param_T = eq(busy, UInt<1>(0h0)) node _param_T_1 = and(io.req.ready, io.req.valid) reg param_r : UInt<3>, clock when _param_T_1 : connect param_r, io.req.bits.param node param = mux(_param_T, io.req.bits.param, param_r) connect b.bits.opcode, UInt<3>(0h6) connect b.bits.param, param connect b.bits.size, UInt<3>(0h6) node _b_bits_source_T = bits(next, 0, 0) connect b.bits.source, UInt<6>(0h28) node b_bits_address_base_y = or(tag, UInt<9>(0h0)) node _b_bits_address_base_T = shr(b_bits_address_base_y, 9) node _b_bits_address_base_T_1 = eq(_b_bits_address_base_T, UInt<1>(0h0)) node _b_bits_address_base_T_2 = asUInt(reset) node _b_bits_address_base_T_3 = eq(_b_bits_address_base_T_2, UInt<1>(0h0)) when _b_bits_address_base_T_3 : node _b_bits_address_base_T_4 = eq(_b_bits_address_base_T_1, UInt<1>(0h0)) when _b_bits_address_base_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf assert(clock, _b_bits_address_base_T_1, UInt<1>(0h1), "") : b_bits_address_base_assert node _b_bits_address_base_T_5 = bits(b_bits_address_base_y, 8, 0) node b_bits_address_base_y_1 = or(set, UInt<11>(0h0)) node _b_bits_address_base_T_6 = shr(b_bits_address_base_y_1, 11) node _b_bits_address_base_T_7 = eq(_b_bits_address_base_T_6, UInt<1>(0h0)) node _b_bits_address_base_T_8 = asUInt(reset) node _b_bits_address_base_T_9 = eq(_b_bits_address_base_T_8, UInt<1>(0h0)) when _b_bits_address_base_T_9 : node _b_bits_address_base_T_10 = eq(_b_bits_address_base_T_7, UInt<1>(0h0)) when _b_bits_address_base_T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_1 assert(clock, _b_bits_address_base_T_7, UInt<1>(0h1), "") : b_bits_address_base_assert_1 node _b_bits_address_base_T_11 = bits(b_bits_address_base_y_1, 10, 0) node b_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0)) node _b_bits_address_base_T_12 = shr(b_bits_address_base_y_2, 6) node _b_bits_address_base_T_13 = eq(_b_bits_address_base_T_12, UInt<1>(0h0)) node _b_bits_address_base_T_14 = asUInt(reset) node _b_bits_address_base_T_15 = eq(_b_bits_address_base_T_14, UInt<1>(0h0)) when _b_bits_address_base_T_15 : node _b_bits_address_base_T_16 = eq(_b_bits_address_base_T_13, UInt<1>(0h0)) when _b_bits_address_base_T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_2 assert(clock, _b_bits_address_base_T_13, UInt<1>(0h1), "") : b_bits_address_base_assert_2 node _b_bits_address_base_T_17 = bits(b_bits_address_base_y_2, 5, 0) node b_bits_address_base_hi = cat(_b_bits_address_base_T_5, _b_bits_address_base_T_11) node b_bits_address_base = cat(b_bits_address_base_hi, _b_bits_address_base_T_17) node _b_bits_address_T = bits(b_bits_address_base, 0, 0) node _b_bits_address_T_1 = bits(b_bits_address_base, 1, 1) node _b_bits_address_T_2 = bits(b_bits_address_base, 2, 2) node _b_bits_address_T_3 = bits(b_bits_address_base, 3, 3) node _b_bits_address_T_4 = bits(b_bits_address_base, 4, 4) node _b_bits_address_T_5 = bits(b_bits_address_base, 5, 5) node _b_bits_address_T_6 = bits(b_bits_address_base, 6, 6) node _b_bits_address_T_7 = bits(b_bits_address_base, 7, 7) node _b_bits_address_T_8 = bits(b_bits_address_base, 8, 8) node _b_bits_address_T_9 = bits(b_bits_address_base, 9, 9) node _b_bits_address_T_10 = bits(b_bits_address_base, 10, 10) node _b_bits_address_T_11 = bits(b_bits_address_base, 11, 11) node _b_bits_address_T_12 = bits(b_bits_address_base, 12, 12) node _b_bits_address_T_13 = bits(b_bits_address_base, 13, 13) node _b_bits_address_T_14 = bits(b_bits_address_base, 14, 14) node _b_bits_address_T_15 = bits(b_bits_address_base, 15, 15) node _b_bits_address_T_16 = bits(b_bits_address_base, 16, 16) node _b_bits_address_T_17 = bits(b_bits_address_base, 17, 17) node _b_bits_address_T_18 = bits(b_bits_address_base, 18, 18) node _b_bits_address_T_19 = bits(b_bits_address_base, 19, 19) node _b_bits_address_T_20 = bits(b_bits_address_base, 20, 20) node _b_bits_address_T_21 = bits(b_bits_address_base, 21, 21) node _b_bits_address_T_22 = bits(b_bits_address_base, 22, 22) node _b_bits_address_T_23 = bits(b_bits_address_base, 23, 23) node _b_bits_address_T_24 = bits(b_bits_address_base, 24, 24) node _b_bits_address_T_25 = bits(b_bits_address_base, 25, 25) node b_bits_address_lo_lo_lo_lo = cat(_b_bits_address_T_1, _b_bits_address_T) node b_bits_address_lo_lo_lo_hi = cat(_b_bits_address_T_3, _b_bits_address_T_2) node b_bits_address_lo_lo_lo = cat(b_bits_address_lo_lo_lo_hi, b_bits_address_lo_lo_lo_lo) node b_bits_address_lo_lo_hi_lo = cat(_b_bits_address_T_5, _b_bits_address_T_4) node b_bits_address_lo_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node b_bits_address_lo_lo_hi = cat(b_bits_address_lo_lo_hi_hi, b_bits_address_lo_lo_hi_lo) node b_bits_address_lo_lo = cat(b_bits_address_lo_lo_hi, b_bits_address_lo_lo_lo) node b_bits_address_lo_hi_lo_lo = cat(_b_bits_address_T_6, UInt<1>(0h0)) node b_bits_address_lo_hi_lo_hi = cat(_b_bits_address_T_8, _b_bits_address_T_7) node b_bits_address_lo_hi_lo = cat(b_bits_address_lo_hi_lo_hi, b_bits_address_lo_hi_lo_lo) node b_bits_address_lo_hi_hi_lo = cat(_b_bits_address_T_10, _b_bits_address_T_9) node b_bits_address_lo_hi_hi_hi = cat(_b_bits_address_T_12, _b_bits_address_T_11) node b_bits_address_lo_hi_hi = cat(b_bits_address_lo_hi_hi_hi, b_bits_address_lo_hi_hi_lo) node b_bits_address_lo_hi = cat(b_bits_address_lo_hi_hi, b_bits_address_lo_hi_lo) node b_bits_address_lo = cat(b_bits_address_lo_hi, b_bits_address_lo_lo) node b_bits_address_hi_lo_lo_lo = cat(_b_bits_address_T_14, _b_bits_address_T_13) node b_bits_address_hi_lo_lo_hi = cat(_b_bits_address_T_16, _b_bits_address_T_15) node b_bits_address_hi_lo_lo = cat(b_bits_address_hi_lo_lo_hi, b_bits_address_hi_lo_lo_lo) node b_bits_address_hi_lo_hi_lo = cat(_b_bits_address_T_18, _b_bits_address_T_17) node b_bits_address_hi_lo_hi_hi = cat(_b_bits_address_T_20, _b_bits_address_T_19) node b_bits_address_hi_lo_hi = cat(b_bits_address_hi_lo_hi_hi, b_bits_address_hi_lo_hi_lo) node b_bits_address_hi_lo = cat(b_bits_address_hi_lo_hi, b_bits_address_hi_lo_lo) node b_bits_address_hi_hi_lo_lo = cat(_b_bits_address_T_22, _b_bits_address_T_21) node b_bits_address_hi_hi_lo_hi = cat(_b_bits_address_T_24, _b_bits_address_T_23) node b_bits_address_hi_hi_lo = cat(b_bits_address_hi_hi_lo_hi, b_bits_address_hi_hi_lo_lo) node b_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node b_bits_address_hi_hi_hi_hi = cat(_b_bits_address_T_25, UInt<1>(0h0)) node b_bits_address_hi_hi_hi = cat(b_bits_address_hi_hi_hi_hi, b_bits_address_hi_hi_hi_lo) node b_bits_address_hi_hi = cat(b_bits_address_hi_hi_hi, b_bits_address_hi_hi_lo) node b_bits_address_hi = cat(b_bits_address_hi_hi, b_bits_address_hi_lo) node _b_bits_address_T_26 = cat(b_bits_address_hi, b_bits_address_lo) connect b.bits.address, _b_bits_address_T_26 node _b_bits_mask_T = not(UInt<16>(0h0)) connect b.bits.mask, _b_bits_mask_T connect b.bits.data, UInt<1>(0h0) connect b.bits.corrupt, UInt<1>(0h0)

module SourceB_2( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [8:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [10:0] io_req_bits_set, // @[SourceB.scala:35:14] input io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [5:0] io_b_bits_source = 6'h28; // @[SourceB.scala:33:7] wire [5:0] b_bits_source = 6'h28; // @[SourceB.scala:65:17] wire [15:0] io_b_bits_mask = 16'hFFFF; // @[SourceB.scala:33:7] wire [15:0] b_bits_mask = 16'hFFFF; // @[SourceB.scala:65:17] wire [15:0] _b_bits_mask_T = 16'hFFFF; // @[SourceB.scala:81:23] wire [127:0] io_b_bits_data = 128'h0; // @[SourceB.scala:33:7] wire [127:0] b_bits_data = 128'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_lo_lo_hi_hi = 2'h0; // @[Parameters.scala:230:8] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg remain; // @[SourceB.scala:46:25] wire busy = remain; // @[SourceB.scala:46:25, :51:23] wire remain_set; // @[SourceB.scala:47:30] wire remain_clr; // @[SourceB.scala:48:30] wire _remain_T = remain | remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire _next_T = todo; // @[package.scala:254:17] wire [1:0] _next_T_1 = {_next_T, 1'h0}; // @[package.scala:254:17] wire [1:0] _next_T_2 = ~_next_T_1; // @[SourceB.scala:53:{16,31}] wire [1:0] next = {1'h0, _next_T_2[0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_126 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_126( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_152 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_152( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_5 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_10 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_5 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h15), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h13), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _T_3 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _T_4 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_5 = or(_T, _T_1) node _T_6 = or(_T_5, _T_2) node _T_7 = or(_T_6, _T_3) node _T_8 = or(_T_7, _T_4) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = and(io.in.valid, _T_9) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_11, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h2) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h13), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h13), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<2> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<1>(0h1)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`1`[1], io.router_resp.vc_sel.`1`[1] connect route_q.io.enq.bits.vc_sel.`1`[2], io.router_resp.vc_sel.`1`[2] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`2`[1], io.router_resp.vc_sel.`2`[1] connect route_q.io.enq.bits.vc_sel.`2`[2], io.router_resp.vc_sel.`2`[2] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_15 = and(io.in.ready, io.in.valid) node _T_16 = and(_T_15, io.in.bits.head) node _T_17 = and(_T_16, at_dest) when _T_17 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_18 = eq(UInt<2>(0h2), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_19 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_20 = and(route_q.io.enq.valid, _T_19) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_11 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_5 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`1`[1], io.vcalloc_resp.vc_sel.`1`[1] connect vcalloc_q.io.enq.bits.vc_sel.`1`[2], io.vcalloc_resp.vc_sel.`1`[2] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[1], io.vcalloc_resp.vc_sel.`2`[1] connect vcalloc_q.io.enq.bits.vc_sel.`2`[2], io.vcalloc_resp.vc_sel.`2`[2] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_25 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_26 = and(vcalloc_q.io.enq.valid, _T_25) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _c_T = cat(c_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[2], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node _c_T_1 = cat(c_hi_1, vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node c_hi_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[2], vcalloc_q.io.deq.bits.vc_sel.`2`[1]) node _c_T_2 = cat(c_hi_2, vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node c_lo = cat(_c_T_1, _c_T) node c_hi_3 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], _c_T_2) node _c_T_3 = cat(c_hi_3, c_lo) node c_hi_4 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _c_T_4 = cat(c_hi_4, io.out_credit_available.`0`[0]) node c_hi_5 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _c_T_5 = cat(c_hi_5, io.out_credit_available.`1`[0]) node c_hi_6 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _c_T_6 = cat(c_hi_6, io.out_credit_available.`2`[0]) node c_lo_1 = cat(_c_T_5, _c_T_4) node c_hi_7 = cat(io.out_credit_available.`3`[0], _c_T_6) node _c_T_7 = cat(c_hi_7, c_lo_1) node _c_T_8 = and(_c_T_3, _c_T_7) node c = neq(_c_T_8, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 wire out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}} connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node out_channel_oh_0 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_1 = or(vcalloc_q.io.deq.bits.vc_sel.`1`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node out_channel_oh_1 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`1`[2]) node _out_channel_oh_T_2 = or(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[1]) node out_channel_oh_2 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`2`[2]) node out_bundle_bits_out_virt_channel_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 2, 2) node out_bundle_bits_out_virt_channel_lo = bits(_out_bundle_bits_out_virt_channel_T, 1, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo) node _out_bundle_bits_out_virt_channel_T_3 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 1) node _out_bundle_bits_out_virt_channel_T_4 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_3) node out_bundle_bits_out_virt_channel_hi_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[2], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node _out_bundle_bits_out_virt_channel_T_5 = cat(out_bundle_bits_out_virt_channel_hi_2, vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_5, 2, 2) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T_5, 1, 0) node _out_bundle_bits_out_virt_channel_T_6 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_7 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_1) node _out_bundle_bits_out_virt_channel_T_8 = bits(_out_bundle_bits_out_virt_channel_T_7, 1, 1) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_6, _out_bundle_bits_out_virt_channel_T_8) node out_bundle_bits_out_virt_channel_hi_4 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[2], vcalloc_q.io.deq.bits.vc_sel.`2`[1]) node _out_bundle_bits_out_virt_channel_T_10 = cat(out_bundle_bits_out_virt_channel_hi_4, vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node out_bundle_bits_out_virt_channel_hi_5 = bits(_out_bundle_bits_out_virt_channel_T_10, 2, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_10, 1, 0) node _out_bundle_bits_out_virt_channel_T_11 = orr(out_bundle_bits_out_virt_channel_hi_5) node _out_bundle_bits_out_virt_channel_T_12 = or(out_bundle_bits_out_virt_channel_hi_5, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_13 = bits(_out_bundle_bits_out_virt_channel_T_12, 1, 1) node _out_bundle_bits_out_virt_channel_T_14 = cat(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_13) node _out_bundle_bits_out_virt_channel_T_15 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_4, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_16 = mux(out_channel_oh_1, _out_bundle_bits_out_virt_channel_T_9, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_17 = mux(out_channel_oh_2, _out_bundle_bits_out_virt_channel_T_14, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_18 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_19 = or(_out_bundle_bits_out_virt_channel_T_15, _out_bundle_bits_out_virt_channel_T_16) node _out_bundle_bits_out_virt_channel_T_20 = or(_out_bundle_bits_out_virt_channel_T_19, _out_bundle_bits_out_virt_channel_T_17) node _out_bundle_bits_out_virt_channel_T_21 = or(_out_bundle_bits_out_virt_channel_T_20, _out_bundle_bits_out_virt_channel_T_18) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<2> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_21 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1

module IngressUnit_5( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h13; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 4'hA : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'h9 : 4'h0); // @[Mux.scala:30:73] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_T_10[3], _route_buffer_io_enq_bits_flow_egress_node_T_10[2:0] | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 3'h6 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0)}; // @[Mux.scala:30:73] wire [1:0] _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_3, 1'h0}; // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'h1; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'h1; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_28 : output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulRawFN of MulRawFN_28 node mulRawFN_io_a_exp = bits(io.a, 31, 23) node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6) node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7) node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T) connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1 node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1) connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2 connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32) connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp) connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0)) node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T) node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0) node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2) connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3 connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN node mulRawFN_io_b_exp = bits(io.b, 31, 23) node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6) node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7) node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T) connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1 node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1) connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2 connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32) connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp) connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0)) node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T) node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0) node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2) connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3 connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_95 connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags

module MulRecFN_28( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_28 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_95 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module L2MemHelperLatencyInjection_9 : input clock : Clock input reset : Reset output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} output io : { flip userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip latency_inject_cycles : UInt<64>, flip sfence : UInt<1>, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip status : { valid : UInt<1>, bits : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect auto.master_out, masterNodeOut wire request_input : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}} connect request_input, io.userif.req wire response_output : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}} connect io.userif.resp, response_output reg status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock when io.status.valid : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] setting status.dprv to: %x compare %x\n", io.status.bits.dprv, UInt<2>(0h3)) : printf_1 connect status, io.status.bits inst tlb of DTLB_11 connect tlb.clock, clock connect tlb.reset, reset connect tlb.io.req.valid, request_input.valid connect tlb.io.req.bits.vaddr, request_input.bits.addr connect tlb.io.req.bits.size, request_input.bits.size connect tlb.io.req.bits.cmd, request_input.bits.cmd connect tlb.io.req.bits.passthrough, UInt<1>(0h0) node _tlb_ready_T = eq(tlb.io.resp.miss, UInt<1>(0h0)) node tlb_ready = and(tlb.io.req.ready, _tlb_ready_T) invalidate tlb.io.req.bits.prv invalidate tlb.io.req.bits.v invalidate tlb.io.sfence.bits.hv invalidate tlb.io.sfence.bits.hg connect tlb.io.ptw.customCSRs, io.ptw.customCSRs connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] connect tlb.io.ptw.gstatus, io.ptw.gstatus connect tlb.io.ptw.hstatus, io.ptw.hstatus connect tlb.io.ptw.status, io.ptw.status connect tlb.io.ptw.vsatp, io.ptw.vsatp connect tlb.io.ptw.hgatp, io.ptw.hgatp connect tlb.io.ptw.ptbr, io.ptw.ptbr connect tlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, tlb.io.ptw.req.bits connect io.ptw.req.valid, tlb.io.ptw.req.valid connect tlb.io.ptw.req.ready, io.ptw.req.ready connect tlb.io.ptw.status.uie, status.uie connect tlb.io.ptw.status.sie, status.sie connect tlb.io.ptw.status.hie, status.hie connect tlb.io.ptw.status.mie, status.mie connect tlb.io.ptw.status.upie, status.upie connect tlb.io.ptw.status.spie, status.spie connect tlb.io.ptw.status.ube, status.ube connect tlb.io.ptw.status.mpie, status.mpie connect tlb.io.ptw.status.spp, status.spp connect tlb.io.ptw.status.vs, status.vs connect tlb.io.ptw.status.mpp, status.mpp connect tlb.io.ptw.status.fs, status.fs connect tlb.io.ptw.status.xs, status.xs connect tlb.io.ptw.status.mprv, status.mprv connect tlb.io.ptw.status.sum, status.sum connect tlb.io.ptw.status.mxr, status.mxr connect tlb.io.ptw.status.tvm, status.tvm connect tlb.io.ptw.status.tw, status.tw connect tlb.io.ptw.status.tsr, status.tsr connect tlb.io.ptw.status.zero1, status.zero1 connect tlb.io.ptw.status.sd_rv32, status.sd_rv32 connect tlb.io.ptw.status.uxl, status.uxl connect tlb.io.ptw.status.sxl, status.sxl connect tlb.io.ptw.status.sbe, status.sbe connect tlb.io.ptw.status.mbe, status.mbe connect tlb.io.ptw.status.gva, status.gva connect tlb.io.ptw.status.mpv, status.mpv connect tlb.io.ptw.status.zero2, status.zero2 connect tlb.io.ptw.status.sd, status.sd connect tlb.io.ptw.status.v, status.v connect tlb.io.ptw.status.prv, status.prv connect tlb.io.ptw.status.dv, status.dv connect tlb.io.ptw.status.dprv, status.dprv connect tlb.io.ptw.status.isa, status.isa connect tlb.io.ptw.status.wfi, status.wfi connect tlb.io.ptw.status.cease, status.cease connect tlb.io.ptw.status.debug, status.debug connect tlb.io.sfence.valid, io.sfence connect tlb.io.sfence.bits.rs1, UInt<1>(0h0) connect tlb.io.sfence.bits.rs2, UInt<1>(0h0) connect tlb.io.sfence.bits.addr, UInt<1>(0h0) connect tlb.io.sfence.bits.asid, UInt<1>(0h0) connect tlb.io.kill, UInt<1>(0h0) inst outstanding_req_addr of Queue16_L2InternalTracking_3 connect outstanding_req_addr.clock, clock connect outstanding_req_addr.reset, reset inst tags_for_issue_Q of Queue8_UInt2_3 connect tags_for_issue_Q.clock, clock connect tags_for_issue_Q.reset, reset connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h0) invalidate tags_for_issue_Q.io.enq.bits regreset tags_init_reg : UInt<3>, clock, reset, UInt<3>(0h0) node _T_4 = neq(tags_init_reg, UInt<3>(0h4)) when _T_4 : connect tags_for_issue_Q.io.enq.bits, tags_init_reg connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) when tags_for_issue_Q.io.enq.ready : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] tags_for_issue_Q init with value %d\n", tags_for_issue_Q.io.enq.bits) : printf_3 node _tags_init_reg_T = add(tags_init_reg, UInt<1>(0h1)) node _tags_init_reg_T_1 = tail(_tags_init_reg_T, 1) connect tags_init_reg, _tags_init_reg_T_1 node _addr_mask_check_T = dshl(UInt<64>(0h1), request_input.bits.size) node _addr_mask_check_T_1 = sub(_addr_mask_check_T, UInt<1>(0h1)) node addr_mask_check = tail(_addr_mask_check_T_1, 1) node _assertcheck_T = eq(request_input.valid, UInt<1>(0h0)) node _assertcheck_T_1 = and(request_input.bits.addr, addr_mask_check) node _assertcheck_T_2 = eq(_assertcheck_T_1, UInt<1>(0h0)) node _assertcheck_T_3 = or(_assertcheck_T, _assertcheck_T_2) reg assertcheck : UInt<1>, clock connect assertcheck, _assertcheck_T_3 node _T_9 = eq(assertcheck, UInt<1>(0h0)) when _T_9 : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: access addr must be aligned to write width\n") : printf_5 node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(assertcheck, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed: [huf_jt_writer] L2IF: access addr must be aligned to write width\n\n at L2MemHelperLatencyInjection.scala:114 assert(assertcheck,\n") : printf_6 assert(clock, assertcheck, UInt<1>(0h1), "") : assert regreset global_memop_accepted : UInt<64>, clock, reset, UInt<64>(0h0) node _T_17 = and(io.userif.req.ready, io.userif.req.valid) when _T_17 : node _global_memop_accepted_T = add(global_memop_accepted, UInt<1>(0h1)) node _global_memop_accepted_T_1 = tail(_global_memop_accepted_T, 1) connect global_memop_accepted, _global_memop_accepted_T_1 regreset global_memop_sent : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_ackd : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_resp_to_user : UInt<64>, clock, reset, UInt<64>(0h0) node _io_userif_no_memops_inflight_T = eq(global_memop_accepted, global_memop_ackd) connect io.userif.no_memops_inflight, _io_userif_no_memops_inflight_T node _free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _free_outstanding_op_slots_T_1 = tail(_free_outstanding_op_slots_T, 1) node free_outstanding_op_slots = lt(_free_outstanding_op_slots_T_1, UInt<3>(0h4)) node _assert_free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _assert_free_outstanding_op_slots_T_1 = tail(_assert_free_outstanding_op_slots_T, 1) node assert_free_outstanding_op_slots = leq(_assert_free_outstanding_op_slots_T_1, UInt<3>(0h4)) node _T_18 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_18 : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_7 node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: Too many outstanding requests for tag count.\n") : printf_8 node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed: [huf_jt_writer] L2IF: Too many outstanding requests for tag count.\n\n at L2MemHelperLatencyInjection.scala:136 assert(assert_free_outstanding_op_slots,\n") : printf_9 assert(clock, assert_free_outstanding_op_slots, UInt<1>(0h1), "") : assert_1 node _T_26 = and(request_input.ready, request_input.valid) when _T_26 : node _global_memop_sent_T = add(global_memop_sent, UInt<1>(0h1)) node _global_memop_sent_T_1 = tail(_global_memop_sent_T, 1) connect global_memop_sent, _global_memop_sent_T_1 regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0) node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1)) node _cur_cycle_T_1 = tail(_cur_cycle_T, 1) connect cur_cycle, _cur_cycle_T_1 inst request_latency_injection_q of LatencyInjectionQueue_18 connect request_latency_injection_q.clock, clock connect request_latency_injection_q.reset, reset connect request_latency_injection_q.io.latency_cycles, io.latency_inject_cycles invalidate request_latency_injection_q.io.enq.bits.corrupt invalidate request_latency_injection_q.io.enq.bits.data invalidate request_latency_injection_q.io.enq.bits.mask invalidate request_latency_injection_q.io.enq.bits.address invalidate request_latency_injection_q.io.enq.bits.source invalidate request_latency_injection_q.io.enq.bits.size invalidate request_latency_injection_q.io.enq.bits.param invalidate request_latency_injection_q.io.enq.bits.opcode node _T_27 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_27 : node _legal_T = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_1 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_2 = and(_legal_T, _legal_T_1) node _legal_T_3 = or(UInt<1>(0h0), _legal_T_2) node _legal_T_4 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_5 = cvt(_legal_T_4) node _legal_T_6 = and(_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _legal_T_7 = asSInt(_legal_T_6) node _legal_T_8 = eq(_legal_T_7, asSInt(UInt<1>(0h0))) node _legal_T_9 = and(_legal_T_3, _legal_T_8) node _legal_T_10 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_11 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_12 = and(_legal_T_10, _legal_T_11) node _legal_T_13 = or(UInt<1>(0h0), _legal_T_12) node _legal_T_14 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_15 = cvt(_legal_T_14) node _legal_T_16 = and(_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _legal_T_17 = asSInt(_legal_T_16) node _legal_T_18 = eq(_legal_T_17, asSInt(UInt<1>(0h0))) node _legal_T_19 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_20 = cvt(_legal_T_19) node _legal_T_21 = and(_legal_T_20, asSInt(UInt<33>(0h98013000))) node _legal_T_22 = asSInt(_legal_T_21) node _legal_T_23 = eq(_legal_T_22, asSInt(UInt<1>(0h0))) node _legal_T_24 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_25 = cvt(_legal_T_24) node _legal_T_26 = and(_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _legal_T_27 = asSInt(_legal_T_26) node _legal_T_28 = eq(_legal_T_27, asSInt(UInt<1>(0h0))) node _legal_T_29 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_30 = cvt(_legal_T_29) node _legal_T_31 = and(_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _legal_T_32 = asSInt(_legal_T_31) node _legal_T_33 = eq(_legal_T_32, asSInt(UInt<1>(0h0))) node _legal_T_34 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_35 = cvt(_legal_T_34) node _legal_T_36 = and(_legal_T_35, asSInt(UInt<33>(0h98000000))) node _legal_T_37 = asSInt(_legal_T_36) node _legal_T_38 = eq(_legal_T_37, asSInt(UInt<1>(0h0))) node _legal_T_39 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_40 = cvt(_legal_T_39) node _legal_T_41 = and(_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _legal_T_42 = asSInt(_legal_T_41) node _legal_T_43 = eq(_legal_T_42, asSInt(UInt<1>(0h0))) node _legal_T_44 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_45 = cvt(_legal_T_44) node _legal_T_46 = and(_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _legal_T_47 = asSInt(_legal_T_46) node _legal_T_48 = eq(_legal_T_47, asSInt(UInt<1>(0h0))) node _legal_T_49 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_50 = cvt(_legal_T_49) node _legal_T_51 = and(_legal_T_50, asSInt(UInt<33>(0h90000000))) node _legal_T_52 = asSInt(_legal_T_51) node _legal_T_53 = eq(_legal_T_52, asSInt(UInt<1>(0h0))) node _legal_T_54 = or(_legal_T_18, _legal_T_23) node _legal_T_55 = or(_legal_T_54, _legal_T_28) node _legal_T_56 = or(_legal_T_55, _legal_T_33) node _legal_T_57 = or(_legal_T_56, _legal_T_38) node _legal_T_58 = or(_legal_T_57, _legal_T_43) node _legal_T_59 = or(_legal_T_58, _legal_T_48) node _legal_T_60 = or(_legal_T_59, _legal_T_53) node _legal_T_61 = and(_legal_T_13, _legal_T_60) node _legal_T_62 = or(UInt<1>(0h0), _legal_T_9) node legal = or(_legal_T_62, _legal_T_61) wire bundle : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle.opcode, UInt<3>(0h4) connect bundle.param, UInt<1>(0h0) connect bundle.size, request_input.bits.size connect bundle.source, tags_for_issue_Q.io.deq.bits connect bundle.address, tlb.io.resp.paddr node _a_mask_sizeOH_T = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T = pad(_a_mask_sizeOH_T, 3) node a_mask_sizeOH_shiftAmount = bits(_a_mask_sizeOH_shiftAmount_T, 2, 0) node _a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount) node _a_mask_sizeOH_T_2 = bits(_a_mask_sizeOH_T_1, 4, 0) node a_mask_sizeOH = or(_a_mask_sizeOH_T_2, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size = bits(a_mask_sizeOH, 4, 4) node a_mask_sub_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_0_2) node a_mask_sub_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit) node _a_mask_sub_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_1_2) node a_mask_sub_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_size = bits(a_mask_sizeOH, 3, 3) node a_mask_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_0_2) node a_mask_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_1_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_1_2) node a_mask_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_2_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_2_2) node a_mask_sub_sub_sub_2_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_3_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_3_2) node a_mask_sub_sub_sub_3_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_3) node a_mask_sub_sub_size = bits(a_mask_sizeOH, 2, 2) node a_mask_sub_sub_bit = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit = eq(a_mask_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_0_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T = and(a_mask_sub_sub_size, a_mask_sub_sub_0_2) node a_mask_sub_sub_0_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T) node a_mask_sub_sub_1_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_1 = and(a_mask_sub_sub_size, a_mask_sub_sub_1_2) node a_mask_sub_sub_1_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T_1) node a_mask_sub_sub_2_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_2 = and(a_mask_sub_sub_size, a_mask_sub_sub_2_2) node a_mask_sub_sub_2_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_2) node a_mask_sub_sub_3_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_3 = and(a_mask_sub_sub_size, a_mask_sub_sub_3_2) node a_mask_sub_sub_3_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_3) node a_mask_sub_sub_4_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_4 = and(a_mask_sub_sub_size, a_mask_sub_sub_4_2) node a_mask_sub_sub_4_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_4) node a_mask_sub_sub_5_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_5 = and(a_mask_sub_sub_size, a_mask_sub_sub_5_2) node a_mask_sub_sub_5_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_5) node a_mask_sub_sub_6_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_6 = and(a_mask_sub_sub_size, a_mask_sub_sub_6_2) node a_mask_sub_sub_6_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_6) node a_mask_sub_sub_7_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_7 = and(a_mask_sub_sub_size, a_mask_sub_sub_7_2) node a_mask_sub_sub_7_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_7) node a_mask_sub_size = bits(a_mask_sizeOH, 1, 1) node a_mask_sub_bit = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit = eq(a_mask_sub_bit, UInt<1>(0h0)) node a_mask_sub_0_2 = and(a_mask_sub_sub_0_2, a_mask_sub_nbit) node _a_mask_sub_acc_T = and(a_mask_sub_size, a_mask_sub_0_2) node a_mask_sub_0_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T) node a_mask_sub_1_2 = and(a_mask_sub_sub_0_2, a_mask_sub_bit) node _a_mask_sub_acc_T_1 = and(a_mask_sub_size, a_mask_sub_1_2) node a_mask_sub_1_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T_1) node a_mask_sub_2_2 = and(a_mask_sub_sub_1_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_2 = and(a_mask_sub_size, a_mask_sub_2_2) node a_mask_sub_2_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_2) node a_mask_sub_3_2 = and(a_mask_sub_sub_1_2, a_mask_sub_bit) node _a_mask_sub_acc_T_3 = and(a_mask_sub_size, a_mask_sub_3_2) node a_mask_sub_3_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_3) node a_mask_sub_4_2 = and(a_mask_sub_sub_2_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_4 = and(a_mask_sub_size, a_mask_sub_4_2) node a_mask_sub_4_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_4) node a_mask_sub_5_2 = and(a_mask_sub_sub_2_2, a_mask_sub_bit) node _a_mask_sub_acc_T_5 = and(a_mask_sub_size, a_mask_sub_5_2) node a_mask_sub_5_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_5) node a_mask_sub_6_2 = and(a_mask_sub_sub_3_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_6 = and(a_mask_sub_size, a_mask_sub_6_2) node a_mask_sub_6_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_6) node a_mask_sub_7_2 = and(a_mask_sub_sub_3_2, a_mask_sub_bit) node _a_mask_sub_acc_T_7 = and(a_mask_sub_size, a_mask_sub_7_2) node a_mask_sub_7_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_7) node a_mask_sub_8_2 = and(a_mask_sub_sub_4_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_8 = and(a_mask_sub_size, a_mask_sub_8_2) node a_mask_sub_8_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_8) node a_mask_sub_9_2 = and(a_mask_sub_sub_4_2, a_mask_sub_bit) node _a_mask_sub_acc_T_9 = and(a_mask_sub_size, a_mask_sub_9_2) node a_mask_sub_9_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_9) node a_mask_sub_10_2 = and(a_mask_sub_sub_5_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_10 = and(a_mask_sub_size, a_mask_sub_10_2) node a_mask_sub_10_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_10) node a_mask_sub_11_2 = and(a_mask_sub_sub_5_2, a_mask_sub_bit) node _a_mask_sub_acc_T_11 = and(a_mask_sub_size, a_mask_sub_11_2) node a_mask_sub_11_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_11) node a_mask_sub_12_2 = and(a_mask_sub_sub_6_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_12 = and(a_mask_sub_size, a_mask_sub_12_2) node a_mask_sub_12_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_12) node a_mask_sub_13_2 = and(a_mask_sub_sub_6_2, a_mask_sub_bit) node _a_mask_sub_acc_T_13 = and(a_mask_sub_size, a_mask_sub_13_2) node a_mask_sub_13_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_13) node a_mask_sub_14_2 = and(a_mask_sub_sub_7_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_14 = and(a_mask_sub_size, a_mask_sub_14_2) node a_mask_sub_14_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_14) node a_mask_sub_15_2 = and(a_mask_sub_sub_7_2, a_mask_sub_bit) node _a_mask_sub_acc_T_15 = and(a_mask_sub_size, a_mask_sub_15_2) node a_mask_sub_15_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_15) node a_mask_size = bits(a_mask_sizeOH, 0, 0) node a_mask_bit = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit = eq(a_mask_bit, UInt<1>(0h0)) node a_mask_eq = and(a_mask_sub_0_2, a_mask_nbit) node _a_mask_acc_T = and(a_mask_size, a_mask_eq) node a_mask_acc = or(a_mask_sub_0_1, _a_mask_acc_T) node a_mask_eq_1 = and(a_mask_sub_0_2, a_mask_bit) node _a_mask_acc_T_1 = and(a_mask_size, a_mask_eq_1) node a_mask_acc_1 = or(a_mask_sub_0_1, _a_mask_acc_T_1) node a_mask_eq_2 = and(a_mask_sub_1_2, a_mask_nbit) node _a_mask_acc_T_2 = and(a_mask_size, a_mask_eq_2) node a_mask_acc_2 = or(a_mask_sub_1_1, _a_mask_acc_T_2) node a_mask_eq_3 = and(a_mask_sub_1_2, a_mask_bit) node _a_mask_acc_T_3 = and(a_mask_size, a_mask_eq_3) node a_mask_acc_3 = or(a_mask_sub_1_1, _a_mask_acc_T_3) node a_mask_eq_4 = and(a_mask_sub_2_2, a_mask_nbit) node _a_mask_acc_T_4 = and(a_mask_size, a_mask_eq_4) node a_mask_acc_4 = or(a_mask_sub_2_1, _a_mask_acc_T_4) node a_mask_eq_5 = and(a_mask_sub_2_2, a_mask_bit) node _a_mask_acc_T_5 = and(a_mask_size, a_mask_eq_5) node a_mask_acc_5 = or(a_mask_sub_2_1, _a_mask_acc_T_5) node a_mask_eq_6 = and(a_mask_sub_3_2, a_mask_nbit) node _a_mask_acc_T_6 = and(a_mask_size, a_mask_eq_6) node a_mask_acc_6 = or(a_mask_sub_3_1, _a_mask_acc_T_6) node a_mask_eq_7 = and(a_mask_sub_3_2, a_mask_bit) node _a_mask_acc_T_7 = and(a_mask_size, a_mask_eq_7) node a_mask_acc_7 = or(a_mask_sub_3_1, _a_mask_acc_T_7) node a_mask_eq_8 = and(a_mask_sub_4_2, a_mask_nbit) node _a_mask_acc_T_8 = and(a_mask_size, a_mask_eq_8) node a_mask_acc_8 = or(a_mask_sub_4_1, _a_mask_acc_T_8) node a_mask_eq_9 = and(a_mask_sub_4_2, a_mask_bit) node _a_mask_acc_T_9 = and(a_mask_size, a_mask_eq_9) node a_mask_acc_9 = or(a_mask_sub_4_1, _a_mask_acc_T_9) node a_mask_eq_10 = and(a_mask_sub_5_2, a_mask_nbit) node _a_mask_acc_T_10 = and(a_mask_size, a_mask_eq_10) node a_mask_acc_10 = or(a_mask_sub_5_1, _a_mask_acc_T_10) node a_mask_eq_11 = and(a_mask_sub_5_2, a_mask_bit) node _a_mask_acc_T_11 = and(a_mask_size, a_mask_eq_11) node a_mask_acc_11 = or(a_mask_sub_5_1, _a_mask_acc_T_11) node a_mask_eq_12 = and(a_mask_sub_6_2, a_mask_nbit) node _a_mask_acc_T_12 = and(a_mask_size, a_mask_eq_12) node a_mask_acc_12 = or(a_mask_sub_6_1, _a_mask_acc_T_12) node a_mask_eq_13 = and(a_mask_sub_6_2, a_mask_bit) node _a_mask_acc_T_13 = and(a_mask_size, a_mask_eq_13) node a_mask_acc_13 = or(a_mask_sub_6_1, _a_mask_acc_T_13) node a_mask_eq_14 = and(a_mask_sub_7_2, a_mask_nbit) node _a_mask_acc_T_14 = and(a_mask_size, a_mask_eq_14) node a_mask_acc_14 = or(a_mask_sub_7_1, _a_mask_acc_T_14) node a_mask_eq_15 = and(a_mask_sub_7_2, a_mask_bit) node _a_mask_acc_T_15 = and(a_mask_size, a_mask_eq_15) node a_mask_acc_15 = or(a_mask_sub_7_1, _a_mask_acc_T_15) node a_mask_eq_16 = and(a_mask_sub_8_2, a_mask_nbit) node _a_mask_acc_T_16 = and(a_mask_size, a_mask_eq_16) node a_mask_acc_16 = or(a_mask_sub_8_1, _a_mask_acc_T_16) node a_mask_eq_17 = and(a_mask_sub_8_2, a_mask_bit) node _a_mask_acc_T_17 = and(a_mask_size, a_mask_eq_17) node a_mask_acc_17 = or(a_mask_sub_8_1, _a_mask_acc_T_17) node a_mask_eq_18 = and(a_mask_sub_9_2, a_mask_nbit) node _a_mask_acc_T_18 = and(a_mask_size, a_mask_eq_18) node a_mask_acc_18 = or(a_mask_sub_9_1, _a_mask_acc_T_18) node a_mask_eq_19 = and(a_mask_sub_9_2, a_mask_bit) node _a_mask_acc_T_19 = and(a_mask_size, a_mask_eq_19) node a_mask_acc_19 = or(a_mask_sub_9_1, _a_mask_acc_T_19) node a_mask_eq_20 = and(a_mask_sub_10_2, a_mask_nbit) node _a_mask_acc_T_20 = and(a_mask_size, a_mask_eq_20) node a_mask_acc_20 = or(a_mask_sub_10_1, _a_mask_acc_T_20) node a_mask_eq_21 = and(a_mask_sub_10_2, a_mask_bit) node _a_mask_acc_T_21 = and(a_mask_size, a_mask_eq_21) node a_mask_acc_21 = or(a_mask_sub_10_1, _a_mask_acc_T_21) node a_mask_eq_22 = and(a_mask_sub_11_2, a_mask_nbit) node _a_mask_acc_T_22 = and(a_mask_size, a_mask_eq_22) node a_mask_acc_22 = or(a_mask_sub_11_1, _a_mask_acc_T_22) node a_mask_eq_23 = and(a_mask_sub_11_2, a_mask_bit) node _a_mask_acc_T_23 = and(a_mask_size, a_mask_eq_23) node a_mask_acc_23 = or(a_mask_sub_11_1, _a_mask_acc_T_23) node a_mask_eq_24 = and(a_mask_sub_12_2, a_mask_nbit) node _a_mask_acc_T_24 = and(a_mask_size, a_mask_eq_24) node a_mask_acc_24 = or(a_mask_sub_12_1, _a_mask_acc_T_24) node a_mask_eq_25 = and(a_mask_sub_12_2, a_mask_bit) node _a_mask_acc_T_25 = and(a_mask_size, a_mask_eq_25) node a_mask_acc_25 = or(a_mask_sub_12_1, _a_mask_acc_T_25) node a_mask_eq_26 = and(a_mask_sub_13_2, a_mask_nbit) node _a_mask_acc_T_26 = and(a_mask_size, a_mask_eq_26) node a_mask_acc_26 = or(a_mask_sub_13_1, _a_mask_acc_T_26) node a_mask_eq_27 = and(a_mask_sub_13_2, a_mask_bit) node _a_mask_acc_T_27 = and(a_mask_size, a_mask_eq_27) node a_mask_acc_27 = or(a_mask_sub_13_1, _a_mask_acc_T_27) node a_mask_eq_28 = and(a_mask_sub_14_2, a_mask_nbit) node _a_mask_acc_T_28 = and(a_mask_size, a_mask_eq_28) node a_mask_acc_28 = or(a_mask_sub_14_1, _a_mask_acc_T_28) node a_mask_eq_29 = and(a_mask_sub_14_2, a_mask_bit) node _a_mask_acc_T_29 = and(a_mask_size, a_mask_eq_29) node a_mask_acc_29 = or(a_mask_sub_14_1, _a_mask_acc_T_29) node a_mask_eq_30 = and(a_mask_sub_15_2, a_mask_nbit) node _a_mask_acc_T_30 = and(a_mask_size, a_mask_eq_30) node a_mask_acc_30 = or(a_mask_sub_15_1, _a_mask_acc_T_30) node a_mask_eq_31 = and(a_mask_sub_15_2, a_mask_bit) node _a_mask_acc_T_31 = and(a_mask_size, a_mask_eq_31) node a_mask_acc_31 = or(a_mask_sub_15_1, _a_mask_acc_T_31) node a_mask_lo_lo_lo_lo = cat(a_mask_acc_1, a_mask_acc) node a_mask_lo_lo_lo_hi = cat(a_mask_acc_3, a_mask_acc_2) node a_mask_lo_lo_lo = cat(a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo) node a_mask_lo_lo_hi_lo = cat(a_mask_acc_5, a_mask_acc_4) node a_mask_lo_lo_hi_hi = cat(a_mask_acc_7, a_mask_acc_6) node a_mask_lo_lo_hi = cat(a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo) node a_mask_lo_lo = cat(a_mask_lo_lo_hi, a_mask_lo_lo_lo) node a_mask_lo_hi_lo_lo = cat(a_mask_acc_9, a_mask_acc_8) node a_mask_lo_hi_lo_hi = cat(a_mask_acc_11, a_mask_acc_10) node a_mask_lo_hi_lo = cat(a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo) node a_mask_lo_hi_hi_lo = cat(a_mask_acc_13, a_mask_acc_12) node a_mask_lo_hi_hi_hi = cat(a_mask_acc_15, a_mask_acc_14) node a_mask_lo_hi_hi = cat(a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo) node a_mask_lo_hi = cat(a_mask_lo_hi_hi, a_mask_lo_hi_lo) node a_mask_lo = cat(a_mask_lo_hi, a_mask_lo_lo) node a_mask_hi_lo_lo_lo = cat(a_mask_acc_17, a_mask_acc_16) node a_mask_hi_lo_lo_hi = cat(a_mask_acc_19, a_mask_acc_18) node a_mask_hi_lo_lo = cat(a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo) node a_mask_hi_lo_hi_lo = cat(a_mask_acc_21, a_mask_acc_20) node a_mask_hi_lo_hi_hi = cat(a_mask_acc_23, a_mask_acc_22) node a_mask_hi_lo_hi = cat(a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo) node a_mask_hi_lo = cat(a_mask_hi_lo_hi, a_mask_hi_lo_lo) node a_mask_hi_hi_lo_lo = cat(a_mask_acc_25, a_mask_acc_24) node a_mask_hi_hi_lo_hi = cat(a_mask_acc_27, a_mask_acc_26) node a_mask_hi_hi_lo = cat(a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo) node a_mask_hi_hi_hi_lo = cat(a_mask_acc_29, a_mask_acc_28) node a_mask_hi_hi_hi_hi = cat(a_mask_acc_31, a_mask_acc_30) node a_mask_hi_hi_hi = cat(a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo) node a_mask_hi_hi = cat(a_mask_hi_hi_hi, a_mask_hi_hi_lo) node a_mask_hi = cat(a_mask_hi_hi, a_mask_hi_lo) node _a_mask_T = cat(a_mask_hi, a_mask_lo) connect bundle.mask, _a_mask_T invalidate bundle.data connect bundle.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle.data connect request_latency_injection_q.io.enq.bits.mask, bundle.mask connect request_latency_injection_q.io.enq.bits.address, bundle.address connect request_latency_injection_q.io.enq.bits.source, bundle.source connect request_latency_injection_q.io.enq.bits.size, bundle.size connect request_latency_injection_q.io.enq.bits.param, bundle.param connect request_latency_injection_q.io.enq.bits.opcode, bundle.opcode else : node _T_28 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_28 : node _T_29 = bits(request_input.bits.addr, 4, 0) node _T_30 = shl(_T_29, 3) node _T_31 = dshl(request_input.bits.data, _T_30) node _legal_T_63 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_64 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_65 = and(_legal_T_63, _legal_T_64) node _legal_T_66 = or(UInt<1>(0h0), _legal_T_65) node _legal_T_67 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_68 = cvt(_legal_T_67) node _legal_T_69 = and(_legal_T_68, asSInt(UInt<33>(0h9a113000))) node _legal_T_70 = asSInt(_legal_T_69) node _legal_T_71 = eq(_legal_T_70, asSInt(UInt<1>(0h0))) node _legal_T_72 = and(_legal_T_66, _legal_T_71) node _legal_T_73 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_74 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_75 = and(_legal_T_73, _legal_T_74) node _legal_T_76 = or(UInt<1>(0h0), _legal_T_75) node _legal_T_77 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_78 = cvt(_legal_T_77) node _legal_T_79 = and(_legal_T_78, asSInt(UInt<33>(0h9a112000))) node _legal_T_80 = asSInt(_legal_T_79) node _legal_T_81 = eq(_legal_T_80, asSInt(UInt<1>(0h0))) node _legal_T_82 = xor(tlb.io.resp.paddr, UInt<21>(0h100000)) node _legal_T_83 = cvt(_legal_T_82) node _legal_T_84 = and(_legal_T_83, asSInt(UInt<33>(0h9a103000))) node _legal_T_85 = asSInt(_legal_T_84) node _legal_T_86 = eq(_legal_T_85, asSInt(UInt<1>(0h0))) node _legal_T_87 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_88 = cvt(_legal_T_87) node _legal_T_89 = and(_legal_T_88, asSInt(UInt<33>(0h9a110000))) node _legal_T_90 = asSInt(_legal_T_89) node _legal_T_91 = eq(_legal_T_90, asSInt(UInt<1>(0h0))) node _legal_T_92 = xor(tlb.io.resp.paddr, UInt<26>(0h2010000)) node _legal_T_93 = cvt(_legal_T_92) node _legal_T_94 = and(_legal_T_93, asSInt(UInt<33>(0h9a113000))) node _legal_T_95 = asSInt(_legal_T_94) node _legal_T_96 = eq(_legal_T_95, asSInt(UInt<1>(0h0))) node _legal_T_97 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_98 = cvt(_legal_T_97) node _legal_T_99 = and(_legal_T_98, asSInt(UInt<33>(0h98000000))) node _legal_T_100 = asSInt(_legal_T_99) node _legal_T_101 = eq(_legal_T_100, asSInt(UInt<1>(0h0))) node _legal_T_102 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_103 = cvt(_legal_T_102) node _legal_T_104 = and(_legal_T_103, asSInt(UInt<33>(0h9a110000))) node _legal_T_105 = asSInt(_legal_T_104) node _legal_T_106 = eq(_legal_T_105, asSInt(UInt<1>(0h0))) node _legal_T_107 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_108 = cvt(_legal_T_107) node _legal_T_109 = and(_legal_T_108, asSInt(UInt<33>(0h9a113000))) node _legal_T_110 = asSInt(_legal_T_109) node _legal_T_111 = eq(_legal_T_110, asSInt(UInt<1>(0h0))) node _legal_T_112 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_113 = cvt(_legal_T_112) node _legal_T_114 = and(_legal_T_113, asSInt(UInt<33>(0h90000000))) node _legal_T_115 = asSInt(_legal_T_114) node _legal_T_116 = eq(_legal_T_115, asSInt(UInt<1>(0h0))) node _legal_T_117 = or(_legal_T_81, _legal_T_86) node _legal_T_118 = or(_legal_T_117, _legal_T_91) node _legal_T_119 = or(_legal_T_118, _legal_T_96) node _legal_T_120 = or(_legal_T_119, _legal_T_101) node _legal_T_121 = or(_legal_T_120, _legal_T_106) node _legal_T_122 = or(_legal_T_121, _legal_T_111) node _legal_T_123 = or(_legal_T_122, _legal_T_116) node _legal_T_124 = and(_legal_T_76, _legal_T_123) node _legal_T_125 = or(UInt<1>(0h0), UInt<1>(0h0)) node _legal_T_126 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_127 = cvt(_legal_T_126) node _legal_T_128 = and(_legal_T_127, asSInt(UInt<33>(0h9a110000))) node _legal_T_129 = asSInt(_legal_T_128) node _legal_T_130 = eq(_legal_T_129, asSInt(UInt<1>(0h0))) node _legal_T_131 = and(_legal_T_125, _legal_T_130) node _legal_T_132 = or(UInt<1>(0h0), _legal_T_72) node _legal_T_133 = or(_legal_T_132, _legal_T_124) node legal_1 = or(_legal_T_133, _legal_T_131) wire bundle_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle_1.opcode, UInt<1>(0h0) connect bundle_1.param, UInt<1>(0h0) connect bundle_1.size, request_input.bits.size connect bundle_1.source, tags_for_issue_Q.io.deq.bits connect bundle_1.address, tlb.io.resp.paddr node _a_mask_sizeOH_T_3 = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T_1 = pad(_a_mask_sizeOH_T_3, 3) node a_mask_sizeOH_shiftAmount_1 = bits(_a_mask_sizeOH_shiftAmount_T_1, 2, 0) node _a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount_1) node _a_mask_sizeOH_T_5 = bits(_a_mask_sizeOH_T_4, 4, 0) node a_mask_sizeOH_1 = or(_a_mask_sizeOH_T_5, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 4, 4) node a_mask_sub_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_3) node a_mask_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 3, 3) node a_mask_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_4 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_4) node a_mask_sub_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_5 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_5) node a_mask_sub_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_6 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_2_2_1) node a_mask_sub_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_6) node a_mask_sub_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_7 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_3_2_1) node a_mask_sub_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_7) node a_mask_sub_sub_size_1 = bits(a_mask_sizeOH_1, 2, 2) node a_mask_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit_1 = eq(a_mask_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_8 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_0_2_1) node a_mask_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_8) node a_mask_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_9 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_1_2_1) node a_mask_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_9) node a_mask_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_10 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_2_2_1) node a_mask_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_10) node a_mask_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_11 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_3_2_1) node a_mask_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_11) node a_mask_sub_sub_4_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_12 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_4_2_1) node a_mask_sub_sub_4_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_12) node a_mask_sub_sub_5_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_13 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_5_2_1) node a_mask_sub_sub_5_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_13) node a_mask_sub_sub_6_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_14 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_6_2_1) node a_mask_sub_sub_6_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_14) node a_mask_sub_sub_7_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_15 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_7_2_1) node a_mask_sub_sub_7_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_15) node a_mask_sub_size_1 = bits(a_mask_sizeOH_1, 1, 1) node a_mask_sub_bit_1 = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit_1 = eq(a_mask_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_0_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_16 = and(a_mask_sub_size_1, a_mask_sub_0_2_1) node a_mask_sub_0_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_16) node a_mask_sub_1_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_17 = and(a_mask_sub_size_1, a_mask_sub_1_2_1) node a_mask_sub_1_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_17) node a_mask_sub_2_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_18 = and(a_mask_sub_size_1, a_mask_sub_2_2_1) node a_mask_sub_2_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_18) node a_mask_sub_3_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_19 = and(a_mask_sub_size_1, a_mask_sub_3_2_1) node a_mask_sub_3_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_19) node a_mask_sub_4_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_20 = and(a_mask_sub_size_1, a_mask_sub_4_2_1) node a_mask_sub_4_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_20) node a_mask_sub_5_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_21 = and(a_mask_sub_size_1, a_mask_sub_5_2_1) node a_mask_sub_5_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_21) node a_mask_sub_6_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_22 = and(a_mask_sub_size_1, a_mask_sub_6_2_1) node a_mask_sub_6_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_22) node a_mask_sub_7_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_23 = and(a_mask_sub_size_1, a_mask_sub_7_2_1) node a_mask_sub_7_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_23) node a_mask_sub_8_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_24 = and(a_mask_sub_size_1, a_mask_sub_8_2_1) node a_mask_sub_8_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_24) node a_mask_sub_9_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_25 = and(a_mask_sub_size_1, a_mask_sub_9_2_1) node a_mask_sub_9_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_25) node a_mask_sub_10_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_26 = and(a_mask_sub_size_1, a_mask_sub_10_2_1) node a_mask_sub_10_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_26) node a_mask_sub_11_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_27 = and(a_mask_sub_size_1, a_mask_sub_11_2_1) node a_mask_sub_11_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_27) node a_mask_sub_12_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_28 = and(a_mask_sub_size_1, a_mask_sub_12_2_1) node a_mask_sub_12_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_28) node a_mask_sub_13_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_29 = and(a_mask_sub_size_1, a_mask_sub_13_2_1) node a_mask_sub_13_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_29) node a_mask_sub_14_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_30 = and(a_mask_sub_size_1, a_mask_sub_14_2_1) node a_mask_sub_14_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_30) node a_mask_sub_15_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_31 = and(a_mask_sub_size_1, a_mask_sub_15_2_1) node a_mask_sub_15_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_31) node a_mask_size_1 = bits(a_mask_sizeOH_1, 0, 0) node a_mask_bit_1 = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit_1 = eq(a_mask_bit_1, UInt<1>(0h0)) node a_mask_eq_32 = and(a_mask_sub_0_2_1, a_mask_nbit_1) node _a_mask_acc_T_32 = and(a_mask_size_1, a_mask_eq_32) node a_mask_acc_32 = or(a_mask_sub_0_1_1, _a_mask_acc_T_32) node a_mask_eq_33 = and(a_mask_sub_0_2_1, a_mask_bit_1) node _a_mask_acc_T_33 = and(a_mask_size_1, a_mask_eq_33) node a_mask_acc_33 = or(a_mask_sub_0_1_1, _a_mask_acc_T_33) node a_mask_eq_34 = and(a_mask_sub_1_2_1, a_mask_nbit_1) node _a_mask_acc_T_34 = and(a_mask_size_1, a_mask_eq_34) node a_mask_acc_34 = or(a_mask_sub_1_1_1, _a_mask_acc_T_34) node a_mask_eq_35 = and(a_mask_sub_1_2_1, a_mask_bit_1) node _a_mask_acc_T_35 = and(a_mask_size_1, a_mask_eq_35) node a_mask_acc_35 = or(a_mask_sub_1_1_1, _a_mask_acc_T_35) node a_mask_eq_36 = and(a_mask_sub_2_2_1, a_mask_nbit_1) node _a_mask_acc_T_36 = and(a_mask_size_1, a_mask_eq_36) node a_mask_acc_36 = or(a_mask_sub_2_1_1, _a_mask_acc_T_36) node a_mask_eq_37 = and(a_mask_sub_2_2_1, a_mask_bit_1) node _a_mask_acc_T_37 = and(a_mask_size_1, a_mask_eq_37) node a_mask_acc_37 = or(a_mask_sub_2_1_1, _a_mask_acc_T_37) node a_mask_eq_38 = and(a_mask_sub_3_2_1, a_mask_nbit_1) node _a_mask_acc_T_38 = and(a_mask_size_1, a_mask_eq_38) node a_mask_acc_38 = or(a_mask_sub_3_1_1, _a_mask_acc_T_38) node a_mask_eq_39 = and(a_mask_sub_3_2_1, a_mask_bit_1) node _a_mask_acc_T_39 = and(a_mask_size_1, a_mask_eq_39) node a_mask_acc_39 = or(a_mask_sub_3_1_1, _a_mask_acc_T_39) node a_mask_eq_40 = and(a_mask_sub_4_2_1, a_mask_nbit_1) node _a_mask_acc_T_40 = and(a_mask_size_1, a_mask_eq_40) node a_mask_acc_40 = or(a_mask_sub_4_1_1, _a_mask_acc_T_40) node a_mask_eq_41 = and(a_mask_sub_4_2_1, a_mask_bit_1) node _a_mask_acc_T_41 = and(a_mask_size_1, a_mask_eq_41) node a_mask_acc_41 = or(a_mask_sub_4_1_1, _a_mask_acc_T_41) node a_mask_eq_42 = and(a_mask_sub_5_2_1, a_mask_nbit_1) node _a_mask_acc_T_42 = and(a_mask_size_1, a_mask_eq_42) node a_mask_acc_42 = or(a_mask_sub_5_1_1, _a_mask_acc_T_42) node a_mask_eq_43 = and(a_mask_sub_5_2_1, a_mask_bit_1) node _a_mask_acc_T_43 = and(a_mask_size_1, a_mask_eq_43) node a_mask_acc_43 = or(a_mask_sub_5_1_1, _a_mask_acc_T_43) node a_mask_eq_44 = and(a_mask_sub_6_2_1, a_mask_nbit_1) node _a_mask_acc_T_44 = and(a_mask_size_1, a_mask_eq_44) node a_mask_acc_44 = or(a_mask_sub_6_1_1, _a_mask_acc_T_44) node a_mask_eq_45 = and(a_mask_sub_6_2_1, a_mask_bit_1) node _a_mask_acc_T_45 = and(a_mask_size_1, a_mask_eq_45) node a_mask_acc_45 = or(a_mask_sub_6_1_1, _a_mask_acc_T_45) node a_mask_eq_46 = and(a_mask_sub_7_2_1, a_mask_nbit_1) node _a_mask_acc_T_46 = and(a_mask_size_1, a_mask_eq_46) node a_mask_acc_46 = or(a_mask_sub_7_1_1, _a_mask_acc_T_46) node a_mask_eq_47 = and(a_mask_sub_7_2_1, a_mask_bit_1) node _a_mask_acc_T_47 = and(a_mask_size_1, a_mask_eq_47) node a_mask_acc_47 = or(a_mask_sub_7_1_1, _a_mask_acc_T_47) node a_mask_eq_48 = and(a_mask_sub_8_2_1, a_mask_nbit_1) node _a_mask_acc_T_48 = and(a_mask_size_1, a_mask_eq_48) node a_mask_acc_48 = or(a_mask_sub_8_1_1, _a_mask_acc_T_48) node a_mask_eq_49 = and(a_mask_sub_8_2_1, a_mask_bit_1) node _a_mask_acc_T_49 = and(a_mask_size_1, a_mask_eq_49) node a_mask_acc_49 = or(a_mask_sub_8_1_1, _a_mask_acc_T_49) node a_mask_eq_50 = and(a_mask_sub_9_2_1, a_mask_nbit_1) node _a_mask_acc_T_50 = and(a_mask_size_1, a_mask_eq_50) node a_mask_acc_50 = or(a_mask_sub_9_1_1, _a_mask_acc_T_50) node a_mask_eq_51 = and(a_mask_sub_9_2_1, a_mask_bit_1) node _a_mask_acc_T_51 = and(a_mask_size_1, a_mask_eq_51) node a_mask_acc_51 = or(a_mask_sub_9_1_1, _a_mask_acc_T_51) node a_mask_eq_52 = and(a_mask_sub_10_2_1, a_mask_nbit_1) node _a_mask_acc_T_52 = and(a_mask_size_1, a_mask_eq_52) node a_mask_acc_52 = or(a_mask_sub_10_1_1, _a_mask_acc_T_52) node a_mask_eq_53 = and(a_mask_sub_10_2_1, a_mask_bit_1) node _a_mask_acc_T_53 = and(a_mask_size_1, a_mask_eq_53) node a_mask_acc_53 = or(a_mask_sub_10_1_1, _a_mask_acc_T_53) node a_mask_eq_54 = and(a_mask_sub_11_2_1, a_mask_nbit_1) node _a_mask_acc_T_54 = and(a_mask_size_1, a_mask_eq_54) node a_mask_acc_54 = or(a_mask_sub_11_1_1, _a_mask_acc_T_54) node a_mask_eq_55 = and(a_mask_sub_11_2_1, a_mask_bit_1) node _a_mask_acc_T_55 = and(a_mask_size_1, a_mask_eq_55) node a_mask_acc_55 = or(a_mask_sub_11_1_1, _a_mask_acc_T_55) node a_mask_eq_56 = and(a_mask_sub_12_2_1, a_mask_nbit_1) node _a_mask_acc_T_56 = and(a_mask_size_1, a_mask_eq_56) node a_mask_acc_56 = or(a_mask_sub_12_1_1, _a_mask_acc_T_56) node a_mask_eq_57 = and(a_mask_sub_12_2_1, a_mask_bit_1) node _a_mask_acc_T_57 = and(a_mask_size_1, a_mask_eq_57) node a_mask_acc_57 = or(a_mask_sub_12_1_1, _a_mask_acc_T_57) node a_mask_eq_58 = and(a_mask_sub_13_2_1, a_mask_nbit_1) node _a_mask_acc_T_58 = and(a_mask_size_1, a_mask_eq_58) node a_mask_acc_58 = or(a_mask_sub_13_1_1, _a_mask_acc_T_58) node a_mask_eq_59 = and(a_mask_sub_13_2_1, a_mask_bit_1) node _a_mask_acc_T_59 = and(a_mask_size_1, a_mask_eq_59) node a_mask_acc_59 = or(a_mask_sub_13_1_1, _a_mask_acc_T_59) node a_mask_eq_60 = and(a_mask_sub_14_2_1, a_mask_nbit_1) node _a_mask_acc_T_60 = and(a_mask_size_1, a_mask_eq_60) node a_mask_acc_60 = or(a_mask_sub_14_1_1, _a_mask_acc_T_60) node a_mask_eq_61 = and(a_mask_sub_14_2_1, a_mask_bit_1) node _a_mask_acc_T_61 = and(a_mask_size_1, a_mask_eq_61) node a_mask_acc_61 = or(a_mask_sub_14_1_1, _a_mask_acc_T_61) node a_mask_eq_62 = and(a_mask_sub_15_2_1, a_mask_nbit_1) node _a_mask_acc_T_62 = and(a_mask_size_1, a_mask_eq_62) node a_mask_acc_62 = or(a_mask_sub_15_1_1, _a_mask_acc_T_62) node a_mask_eq_63 = and(a_mask_sub_15_2_1, a_mask_bit_1) node _a_mask_acc_T_63 = and(a_mask_size_1, a_mask_eq_63) node a_mask_acc_63 = or(a_mask_sub_15_1_1, _a_mask_acc_T_63) node a_mask_lo_lo_lo_lo_1 = cat(a_mask_acc_33, a_mask_acc_32) node a_mask_lo_lo_lo_hi_1 = cat(a_mask_acc_35, a_mask_acc_34) node a_mask_lo_lo_lo_1 = cat(a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1) node a_mask_lo_lo_hi_lo_1 = cat(a_mask_acc_37, a_mask_acc_36) node a_mask_lo_lo_hi_hi_1 = cat(a_mask_acc_39, a_mask_acc_38) node a_mask_lo_lo_hi_1 = cat(a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1) node a_mask_lo_lo_1 = cat(a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1) node a_mask_lo_hi_lo_lo_1 = cat(a_mask_acc_41, a_mask_acc_40) node a_mask_lo_hi_lo_hi_1 = cat(a_mask_acc_43, a_mask_acc_42) node a_mask_lo_hi_lo_1 = cat(a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1) node a_mask_lo_hi_hi_lo_1 = cat(a_mask_acc_45, a_mask_acc_44) node a_mask_lo_hi_hi_hi_1 = cat(a_mask_acc_47, a_mask_acc_46) node a_mask_lo_hi_hi_1 = cat(a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1) node a_mask_lo_hi_1 = cat(a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1) node a_mask_lo_1 = cat(a_mask_lo_hi_1, a_mask_lo_lo_1) node a_mask_hi_lo_lo_lo_1 = cat(a_mask_acc_49, a_mask_acc_48) node a_mask_hi_lo_lo_hi_1 = cat(a_mask_acc_51, a_mask_acc_50) node a_mask_hi_lo_lo_1 = cat(a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1) node a_mask_hi_lo_hi_lo_1 = cat(a_mask_acc_53, a_mask_acc_52) node a_mask_hi_lo_hi_hi_1 = cat(a_mask_acc_55, a_mask_acc_54) node a_mask_hi_lo_hi_1 = cat(a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1) node a_mask_hi_lo_1 = cat(a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1) node a_mask_hi_hi_lo_lo_1 = cat(a_mask_acc_57, a_mask_acc_56) node a_mask_hi_hi_lo_hi_1 = cat(a_mask_acc_59, a_mask_acc_58) node a_mask_hi_hi_lo_1 = cat(a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1) node a_mask_hi_hi_hi_lo_1 = cat(a_mask_acc_61, a_mask_acc_60) node a_mask_hi_hi_hi_hi_1 = cat(a_mask_acc_63, a_mask_acc_62) node a_mask_hi_hi_hi_1 = cat(a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1) node a_mask_hi_hi_1 = cat(a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1) node a_mask_hi_1 = cat(a_mask_hi_hi_1, a_mask_hi_lo_1) node _a_mask_T_1 = cat(a_mask_hi_1, a_mask_lo_1) connect bundle_1.mask, _a_mask_T_1 connect bundle_1.data, _T_31 connect bundle_1.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle_1.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle_1.data connect request_latency_injection_q.io.enq.bits.mask, bundle_1.mask connect request_latency_injection_q.io.enq.bits.address, bundle_1.address connect request_latency_injection_q.io.enq.bits.source, bundle_1.source connect request_latency_injection_q.io.enq.bits.size, bundle_1.size connect request_latency_injection_q.io.enq.bits.param, bundle_1.param connect request_latency_injection_q.io.enq.bits.opcode, bundle_1.opcode else : when request_input.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_10 node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] ERR") : printf_11 node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: ERR\n at L2MemHelperLatencyInjection.scala:178 assert(false.B, \"ERR\")\n") : printf_12 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_2 inst Queue4_L2RespInternal of Queue4_L2RespInternal_206 connect Queue4_L2RespInternal.clock, clock connect Queue4_L2RespInternal.reset, reset inst Queue4_L2RespInternal_1 of Queue4_L2RespInternal_207 connect Queue4_L2RespInternal_1.clock, clock connect Queue4_L2RespInternal_1.reset, reset inst Queue4_L2RespInternal_2 of Queue4_L2RespInternal_208 connect Queue4_L2RespInternal_2.clock, clock connect Queue4_L2RespInternal_2.reset, reset inst Queue4_L2RespInternal_3 of Queue4_L2RespInternal_209 connect Queue4_L2RespInternal_3.clock, clock connect Queue4_L2RespInternal_3.reset, reset node _current_request_tag_has_response_space_T = eq(UInt<1>(0h0), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _current_request_tag_has_response_space_T) node _current_request_tag_has_response_space_T_2 = eq(UInt<1>(0h1), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _current_request_tag_has_response_space_T_2) node _current_request_tag_has_response_space_T_4 = eq(UInt<2>(0h2), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _current_request_tag_has_response_space_T_4) node _current_request_tag_has_response_space_T_6 = eq(UInt<2>(0h3), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _current_request_tag_has_response_space_T_6) node _current_request_tag_has_response_space_T_8 = or(_current_request_tag_has_response_space_T_1, _current_request_tag_has_response_space_T_3) node _current_request_tag_has_response_space_T_9 = or(_current_request_tag_has_response_space_T_8, _current_request_tag_has_response_space_T_5) node current_request_tag_has_response_space = or(_current_request_tag_has_response_space_T_9, _current_request_tag_has_response_space_T_7) node _outstanding_req_addr_io_enq_bits_addrindex_T = and(request_input.bits.addr, UInt<5>(0h1f)) connect outstanding_req_addr.io.enq.bits.addrindex, _outstanding_req_addr_io_enq_bits_addrindex_T connect outstanding_req_addr.io.enq.bits.tag, tags_for_issue_Q.io.deq.bits node _request_latency_injection_q_io_enq_valid_T = and(request_input.valid, tlb_ready) node _request_latency_injection_q_io_enq_valid_T_1 = and(_request_latency_injection_q_io_enq_valid_T, outstanding_req_addr.io.enq.ready) node _request_latency_injection_q_io_enq_valid_T_2 = and(_request_latency_injection_q_io_enq_valid_T_1, free_outstanding_op_slots) node _request_latency_injection_q_io_enq_valid_T_3 = and(_request_latency_injection_q_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _request_latency_injection_q_io_enq_valid_T_4 = and(_request_latency_injection_q_io_enq_valid_T_3, current_request_tag_has_response_space) connect request_latency_injection_q.io.enq.valid, _request_latency_injection_q_io_enq_valid_T_4 node _request_input_ready_T = and(request_latency_injection_q.io.enq.ready, tlb_ready) node _request_input_ready_T_1 = and(_request_input_ready_T, outstanding_req_addr.io.enq.ready) node _request_input_ready_T_2 = and(_request_input_ready_T_1, free_outstanding_op_slots) node _request_input_ready_T_3 = and(_request_input_ready_T_2, tags_for_issue_Q.io.deq.valid) node _request_input_ready_T_4 = and(_request_input_ready_T_3, current_request_tag_has_response_space) connect request_input.ready, _request_input_ready_T_4 node _outstanding_req_addr_io_enq_valid_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _outstanding_req_addr_io_enq_valid_T_1 = and(_outstanding_req_addr_io_enq_valid_T, tlb_ready) node _outstanding_req_addr_io_enq_valid_T_2 = and(_outstanding_req_addr_io_enq_valid_T_1, free_outstanding_op_slots) node _outstanding_req_addr_io_enq_valid_T_3 = and(_outstanding_req_addr_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _outstanding_req_addr_io_enq_valid_T_4 = and(_outstanding_req_addr_io_enq_valid_T_3, current_request_tag_has_response_space) connect outstanding_req_addr.io.enq.valid, _outstanding_req_addr_io_enq_valid_T_4 node _tags_for_issue_Q_io_deq_ready_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_1 = and(_tags_for_issue_Q_io_deq_ready_T, tlb_ready) node _tags_for_issue_Q_io_deq_ready_T_2 = and(_tags_for_issue_Q_io_deq_ready_T_1, outstanding_req_addr.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_3 = and(_tags_for_issue_Q_io_deq_ready_T_2, free_outstanding_op_slots) node _tags_for_issue_Q_io_deq_ready_T_4 = and(_tags_for_issue_Q_io_deq_ready_T_3, current_request_tag_has_response_space) connect tags_for_issue_Q.io.deq.ready, _tags_for_issue_Q_io_deq_ready_T_4 connect masterNodeOut.a.bits, request_latency_injection_q.io.deq.bits connect masterNodeOut.a.valid, request_latency_injection_q.io.deq.valid connect request_latency_injection_q.io.deq.ready, masterNodeOut.a.ready node _T_39 = and(masterNodeOut.a.ready, masterNodeOut.a.valid) when _T_39 : node _T_40 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_40 : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_13 node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_14 node _T_45 = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _T_46 = and(_T_45, tlb_ready) node _T_47 = and(_T_46, outstanding_req_addr.io.enq.ready) node _T_48 = and(_T_47, free_outstanding_op_slots) node _T_49 = and(_T_48, tags_for_issue_Q.io.deq.valid) node _T_50 = and(_T_49, current_request_tag_has_response_space) when _T_50 : node _T_51 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_51 : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _printf_T = asUInt(reset) node _printf_T_1 = eq(_printf_T, UInt<1>(0h0)) when _printf_T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_15 node _T_52 = asUInt(reset) node _T_53 = eq(_T_52, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "") : printf_16 node _printf_T_2 = asUInt(reset) node _printf_T_3 = eq(_printf_T_2, UInt<1>(0h0)) when _printf_T_3 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: req(write) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, data: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, request_input.bits.data, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_17 node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "") : printf_18 node _T_56 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_57 = lt(UInt<1>(0h0), _T_56) when _T_57 : node _T_58 = add(request_input.bits.addr, UInt<1>(0h0)) node _T_59 = tail(_T_58, 1) node _T_60 = dshr(request_input.bits.data, UInt<1>(0h0)) node _T_61 = bits(_T_60, 7, 0) regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_19 node _T_64 = asUInt(reset) node _T_65 = eq(_T_64, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_59, _T_61) : printf_20 node _T_66 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_67 = lt(UInt<1>(0h1), _T_66) when _T_67 : node _T_68 = add(request_input.bits.addr, UInt<1>(0h1)) node _T_69 = tail(_T_68, 1) node _T_70 = dshr(request_input.bits.data, UInt<4>(0h8)) node _T_71 = bits(_T_70, 7, 0) regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_21 node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_69, _T_71) : printf_22 node _T_76 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_77 = lt(UInt<2>(0h2), _T_76) when _T_77 : node _T_78 = add(request_input.bits.addr, UInt<2>(0h2)) node _T_79 = tail(_T_78, 1) node _T_80 = dshr(request_input.bits.data, UInt<5>(0h10)) node _T_81 = bits(_T_80, 7, 0) regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_23 node _T_84 = asUInt(reset) node _T_85 = eq(_T_84, UInt<1>(0h0)) when _T_85 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_79, _T_81) : printf_24 node _T_86 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_87 = lt(UInt<2>(0h3), _T_86) when _T_87 : node _T_88 = add(request_input.bits.addr, UInt<2>(0h3)) node _T_89 = tail(_T_88, 1) node _T_90 = dshr(request_input.bits.data, UInt<5>(0h18)) node _T_91 = bits(_T_90, 7, 0) regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_92 = asUInt(reset) node _T_93 = eq(_T_92, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_25 node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_89, _T_91) : printf_26 node _T_96 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_97 = lt(UInt<3>(0h4), _T_96) when _T_97 : node _T_98 = add(request_input.bits.addr, UInt<3>(0h4)) node _T_99 = tail(_T_98, 1) node _T_100 = dshr(request_input.bits.data, UInt<6>(0h20)) node _T_101 = bits(_T_100, 7, 0) regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_102 = asUInt(reset) node _T_103 = eq(_T_102, UInt<1>(0h0)) when _T_103 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_27 node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_99, _T_101) : printf_28 node _T_106 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_107 = lt(UInt<3>(0h5), _T_106) when _T_107 : node _T_108 = add(request_input.bits.addr, UInt<3>(0h5)) node _T_109 = tail(_T_108, 1) node _T_110 = dshr(request_input.bits.data, UInt<6>(0h28)) node _T_111 = bits(_T_110, 7, 0) regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_112 = asUInt(reset) node _T_113 = eq(_T_112, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_29 node _T_114 = asUInt(reset) node _T_115 = eq(_T_114, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_109, _T_111) : printf_30 node _T_116 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_117 = lt(UInt<3>(0h6), _T_116) when _T_117 : node _T_118 = add(request_input.bits.addr, UInt<3>(0h6)) node _T_119 = tail(_T_118, 1) node _T_120 = dshr(request_input.bits.data, UInt<6>(0h30)) node _T_121 = bits(_T_120, 7, 0) regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_31 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_119, _T_121) : printf_32 node _T_126 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_127 = lt(UInt<3>(0h7), _T_126) when _T_127 : node _T_128 = add(request_input.bits.addr, UInt<3>(0h7)) node _T_129 = tail(_T_128, 1) node _T_130 = dshr(request_input.bits.data, UInt<6>(0h38)) node _T_131 = bits(_T_130, 7, 0) regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_33 node _T_134 = asUInt(reset) node _T_135 = eq(_T_134, UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_129, _T_131) : printf_34 node _T_136 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_137 = lt(UInt<4>(0h8), _T_136) when _T_137 : node _T_138 = add(request_input.bits.addr, UInt<4>(0h8)) node _T_139 = tail(_T_138, 1) node _T_140 = dshr(request_input.bits.data, UInt<7>(0h40)) node _T_141 = bits(_T_140, 7, 0) regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_35 node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_139, _T_141) : printf_36 node _T_146 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_147 = lt(UInt<4>(0h9), _T_146) when _T_147 : node _T_148 = add(request_input.bits.addr, UInt<4>(0h9)) node _T_149 = tail(_T_148, 1) node _T_150 = dshr(request_input.bits.data, UInt<7>(0h48)) node _T_151 = bits(_T_150, 7, 0) regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_37 node _T_154 = asUInt(reset) node _T_155 = eq(_T_154, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_149, _T_151) : printf_38 node _T_156 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_157 = lt(UInt<4>(0ha), _T_156) when _T_157 : node _T_158 = add(request_input.bits.addr, UInt<4>(0ha)) node _T_159 = tail(_T_158, 1) node _T_160 = dshr(request_input.bits.data, UInt<7>(0h50)) node _T_161 = bits(_T_160, 7, 0) regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_39 node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_159, _T_161) : printf_40 node _T_166 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_167 = lt(UInt<4>(0hb), _T_166) when _T_167 : node _T_168 = add(request_input.bits.addr, UInt<4>(0hb)) node _T_169 = tail(_T_168, 1) node _T_170 = dshr(request_input.bits.data, UInt<7>(0h58)) node _T_171 = bits(_T_170, 7, 0) regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_41 node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_169, _T_171) : printf_42 node _T_176 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_177 = lt(UInt<4>(0hc), _T_176) when _T_177 : node _T_178 = add(request_input.bits.addr, UInt<4>(0hc)) node _T_179 = tail(_T_178, 1) node _T_180 = dshr(request_input.bits.data, UInt<7>(0h60)) node _T_181 = bits(_T_180, 7, 0) regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_43 node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_179, _T_181) : printf_44 node _T_186 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_187 = lt(UInt<4>(0hd), _T_186) when _T_187 : node _T_188 = add(request_input.bits.addr, UInt<4>(0hd)) node _T_189 = tail(_T_188, 1) node _T_190 = dshr(request_input.bits.data, UInt<7>(0h68)) node _T_191 = bits(_T_190, 7, 0) regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_45 node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_189, _T_191) : printf_46 node _T_196 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_197 = lt(UInt<4>(0he), _T_196) when _T_197 : node _T_198 = add(request_input.bits.addr, UInt<4>(0he)) node _T_199 = tail(_T_198, 1) node _T_200 = dshr(request_input.bits.data, UInt<7>(0h70)) node _T_201 = bits(_T_200, 7, 0) regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_47 node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_199, _T_201) : printf_48 node _T_206 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_207 = lt(UInt<4>(0hf), _T_206) when _T_207 : node _T_208 = add(request_input.bits.addr, UInt<4>(0hf)) node _T_209 = tail(_T_208, 1) node _T_210 = dshr(request_input.bits.data, UInt<7>(0h78)) node _T_211 = bits(_T_210, 7, 0) regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_49 node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_209, _T_211) : printf_50 node _T_216 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_217 = lt(UInt<5>(0h10), _T_216) when _T_217 : node _T_218 = add(request_input.bits.addr, UInt<5>(0h10)) node _T_219 = tail(_T_218, 1) node _T_220 = dshr(request_input.bits.data, UInt<8>(0h80)) node _T_221 = bits(_T_220, 7, 0) regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_51 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_219, _T_221) : printf_52 node _T_226 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_227 = lt(UInt<5>(0h11), _T_226) when _T_227 : node _T_228 = add(request_input.bits.addr, UInt<5>(0h11)) node _T_229 = tail(_T_228, 1) node _T_230 = dshr(request_input.bits.data, UInt<8>(0h88)) node _T_231 = bits(_T_230, 7, 0) regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_232 = asUInt(reset) node _T_233 = eq(_T_232, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_53 node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_229, _T_231) : printf_54 node _T_236 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_237 = lt(UInt<5>(0h12), _T_236) when _T_237 : node _T_238 = add(request_input.bits.addr, UInt<5>(0h12)) node _T_239 = tail(_T_238, 1) node _T_240 = dshr(request_input.bits.data, UInt<8>(0h90)) node _T_241 = bits(_T_240, 7, 0) regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_55 node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_239, _T_241) : printf_56 node _T_246 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_247 = lt(UInt<5>(0h13), _T_246) when _T_247 : node _T_248 = add(request_input.bits.addr, UInt<5>(0h13)) node _T_249 = tail(_T_248, 1) node _T_250 = dshr(request_input.bits.data, UInt<8>(0h98)) node _T_251 = bits(_T_250, 7, 0) regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_57 node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_249, _T_251) : printf_58 node _T_256 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_257 = lt(UInt<5>(0h14), _T_256) when _T_257 : node _T_258 = add(request_input.bits.addr, UInt<5>(0h14)) node _T_259 = tail(_T_258, 1) node _T_260 = dshr(request_input.bits.data, UInt<8>(0ha0)) node _T_261 = bits(_T_260, 7, 0) regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_59 node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_259, _T_261) : printf_60 node _T_266 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_267 = lt(UInt<5>(0h15), _T_266) when _T_267 : node _T_268 = add(request_input.bits.addr, UInt<5>(0h15)) node _T_269 = tail(_T_268, 1) node _T_270 = dshr(request_input.bits.data, UInt<8>(0ha8)) node _T_271 = bits(_T_270, 7, 0) regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_272 = asUInt(reset) node _T_273 = eq(_T_272, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_61 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_269, _T_271) : printf_62 node _T_276 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_277 = lt(UInt<5>(0h16), _T_276) when _T_277 : node _T_278 = add(request_input.bits.addr, UInt<5>(0h16)) node _T_279 = tail(_T_278, 1) node _T_280 = dshr(request_input.bits.data, UInt<8>(0hb0)) node _T_281 = bits(_T_280, 7, 0) regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_63 node _T_284 = asUInt(reset) node _T_285 = eq(_T_284, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_279, _T_281) : printf_64 node _T_286 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_287 = lt(UInt<5>(0h17), _T_286) when _T_287 : node _T_288 = add(request_input.bits.addr, UInt<5>(0h17)) node _T_289 = tail(_T_288, 1) node _T_290 = dshr(request_input.bits.data, UInt<8>(0hb8)) node _T_291 = bits(_T_290, 7, 0) regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_292 = asUInt(reset) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_65 node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_289, _T_291) : printf_66 node _T_296 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_297 = lt(UInt<5>(0h18), _T_296) when _T_297 : node _T_298 = add(request_input.bits.addr, UInt<5>(0h18)) node _T_299 = tail(_T_298, 1) node _T_300 = dshr(request_input.bits.data, UInt<8>(0hc0)) node _T_301 = bits(_T_300, 7, 0) regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_67 node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_299, _T_301) : printf_68 node _T_306 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_307 = lt(UInt<5>(0h19), _T_306) when _T_307 : node _T_308 = add(request_input.bits.addr, UInt<5>(0h19)) node _T_309 = tail(_T_308, 1) node _T_310 = dshr(request_input.bits.data, UInt<8>(0hc8)) node _T_311 = bits(_T_310, 7, 0) regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_69 node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_309, _T_311) : printf_70 node _T_316 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_317 = lt(UInt<5>(0h1a), _T_316) when _T_317 : node _T_318 = add(request_input.bits.addr, UInt<5>(0h1a)) node _T_319 = tail(_T_318, 1) node _T_320 = dshr(request_input.bits.data, UInt<8>(0hd0)) node _T_321 = bits(_T_320, 7, 0) regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_322 = asUInt(reset) node _T_323 = eq(_T_322, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_71 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_319, _T_321) : printf_72 node _T_326 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_327 = lt(UInt<5>(0h1b), _T_326) when _T_327 : node _T_328 = add(request_input.bits.addr, UInt<5>(0h1b)) node _T_329 = tail(_T_328, 1) node _T_330 = dshr(request_input.bits.data, UInt<8>(0hd8)) node _T_331 = bits(_T_330, 7, 0) regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_73 node _T_334 = asUInt(reset) node _T_335 = eq(_T_334, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_329, _T_331) : printf_74 node _T_336 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_337 = lt(UInt<5>(0h1c), _T_336) when _T_337 : node _T_338 = add(request_input.bits.addr, UInt<5>(0h1c)) node _T_339 = tail(_T_338, 1) node _T_340 = dshr(request_input.bits.data, UInt<8>(0he0)) node _T_341 = bits(_T_340, 7, 0) regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1)) node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1) connect loginfo_cycles_35, _loginfo_cycles_T_71 node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_75 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_339, _T_341) : printf_76 node _T_346 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_347 = lt(UInt<5>(0h1d), _T_346) when _T_347 : node _T_348 = add(request_input.bits.addr, UInt<5>(0h1d)) node _T_349 = tail(_T_348, 1) node _T_350 = dshr(request_input.bits.data, UInt<8>(0he8)) node _T_351 = bits(_T_350, 7, 0) regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1)) node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1) connect loginfo_cycles_36, _loginfo_cycles_T_73 node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_77 node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_349, _T_351) : printf_78 node _T_356 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_357 = lt(UInt<5>(0h1e), _T_356) when _T_357 : node _T_358 = add(request_input.bits.addr, UInt<5>(0h1e)) node _T_359 = tail(_T_358, 1) node _T_360 = dshr(request_input.bits.data, UInt<8>(0hf0)) node _T_361 = bits(_T_360, 7, 0) regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1)) node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1) connect loginfo_cycles_37, _loginfo_cycles_T_75 node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_79 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_359, _T_361) : printf_80 node _T_366 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_367 = lt(UInt<5>(0h1f), _T_366) when _T_367 : node _T_368 = add(request_input.bits.addr, UInt<5>(0h1f)) node _T_369 = tail(_T_368, 1) node _T_370 = dshr(request_input.bits.data, UInt<8>(0hf8)) node _T_371 = bits(_T_370, 7, 0) regreset loginfo_cycles_38 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_76 = add(loginfo_cycles_38, UInt<1>(0h1)) node _loginfo_cycles_T_77 = tail(_loginfo_cycles_T_76, 1) connect loginfo_cycles_38, _loginfo_cycles_T_77 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_38) : printf_81 node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [huf_jt_writer]\n", _T_369, _T_371) : printf_82 inst response_latency_injection_q of LatencyInjectionQueue_19 connect response_latency_injection_q.clock, clock connect response_latency_injection_q.reset, reset connect response_latency_injection_q.io.latency_cycles, io.latency_inject_cycles connect response_latency_injection_q.io.enq, masterNodeOut.d node _selectQready_T = eq(UInt<1>(0h0), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _selectQready_T) node _selectQready_T_2 = eq(UInt<1>(0h1), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _selectQready_T_2) node _selectQready_T_4 = eq(UInt<2>(0h2), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _selectQready_T_4) node _selectQready_T_6 = eq(UInt<2>(0h3), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _selectQready_T_6) node _selectQready_T_8 = or(_selectQready_T_1, _selectQready_T_3) node _selectQready_T_9 = or(_selectQready_T_8, _selectQready_T_5) node selectQready = or(_selectQready_T_9, _selectQready_T_7) node _T_376 = and(selectQready, response_latency_injection_q.io.deq.valid) when _T_376 : connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) connect tags_for_issue_Q.io.enq.bits, response_latency_injection_q.io.deq.bits.source node _T_377 = and(selectQready, response_latency_injection_q.io.deq.valid) node _T_378 = and(_T_377, tags_for_issue_Q.io.enq.valid) when _T_378 : regreset loginfo_cycles_39 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_78 = add(loginfo_cycles_39, UInt<1>(0h1)) node _loginfo_cycles_T_79 = tail(_loginfo_cycles_T_78, 1) connect loginfo_cycles_39, _loginfo_cycles_T_79 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_39) : printf_83 node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] tags_for_issue_Q add back tag %d\n", tags_for_issue_Q.io.enq.bits) : printf_84 node _response_latency_injection_q_io_deq_ready_T = and(selectQready, tags_for_issue_Q.io.enq.ready) connect response_latency_injection_q.io.deq.ready, _response_latency_injection_q_io_deq_ready_T node _T_383 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_384 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h0)) node _T_385 = and(_T_383, _T_384) connect Queue4_L2RespInternal.io.enq.valid, _T_385 connect Queue4_L2RespInternal.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_386 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_387 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h1)) node _T_388 = and(_T_386, _T_387) connect Queue4_L2RespInternal_1.io.enq.valid, _T_388 connect Queue4_L2RespInternal_1.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_389 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_390 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h2)) node _T_391 = and(_T_389, _T_390) connect Queue4_L2RespInternal_2.io.enq.valid, _T_391 connect Queue4_L2RespInternal_2.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_392 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_393 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h3)) node _T_394 = and(_T_392, _T_393) connect Queue4_L2RespInternal_3.io.enq.valid, _T_394 connect Queue4_L2RespInternal_3.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _queueValid_T = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_1 = and(Queue4_L2RespInternal.io.deq.valid, _queueValid_T) node _queueValid_T_2 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_3 = and(Queue4_L2RespInternal_1.io.deq.valid, _queueValid_T_2) node _queueValid_T_4 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_5 = and(Queue4_L2RespInternal_2.io.deq.valid, _queueValid_T_4) node _queueValid_T_6 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_7 = and(Queue4_L2RespInternal_3.io.deq.valid, _queueValid_T_6) node _queueValid_T_8 = or(_queueValid_T_1, _queueValid_T_3) node _queueValid_T_9 = or(_queueValid_T_8, _queueValid_T_5) node queueValid = or(_queueValid_T_9, _queueValid_T_7) node resultdata_is_current_q = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data : UInt<256> when resultdata_is_current_q : node _resultdata_data_T = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_1 = dshr(Queue4_L2RespInternal.io.deq.bits.data, _resultdata_data_T) connect resultdata_data, _resultdata_data_T_1 else : connect resultdata_data, UInt<1>(0h0) node resultdata_is_current_q_1 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_1 : UInt<256> when resultdata_is_current_q_1 : node _resultdata_data_T_2 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_3 = dshr(Queue4_L2RespInternal_1.io.deq.bits.data, _resultdata_data_T_2) connect resultdata_data_1, _resultdata_data_T_3 else : connect resultdata_data_1, UInt<1>(0h0) node resultdata_is_current_q_2 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_2 : UInt<256> when resultdata_is_current_q_2 : node _resultdata_data_T_4 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_5 = dshr(Queue4_L2RespInternal_2.io.deq.bits.data, _resultdata_data_T_4) connect resultdata_data_2, _resultdata_data_T_5 else : connect resultdata_data_2, UInt<1>(0h0) node resultdata_is_current_q_3 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_3 : UInt<256> when resultdata_is_current_q_3 : node _resultdata_data_T_6 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_7 = dshr(Queue4_L2RespInternal_3.io.deq.bits.data, _resultdata_data_T_6) connect resultdata_data_3, _resultdata_data_T_7 else : connect resultdata_data_3, UInt<1>(0h0) node _resultdata_T = or(resultdata_data, resultdata_data_1) node _resultdata_T_1 = or(_resultdata_T, resultdata_data_2) node resultdata = or(_resultdata_T_1, resultdata_data_3) connect response_output.bits.data, resultdata node _response_output_valid_T = and(queueValid, outstanding_req_addr.io.deq.valid) connect response_output.valid, _response_output_valid_T node _outstanding_req_addr_io_deq_ready_T = and(queueValid, response_output.ready) connect outstanding_req_addr.io.deq.ready, _outstanding_req_addr_io_deq_ready_T node _T_395 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_396 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h0)) node _T_397 = and(_T_395, _T_396) connect Queue4_L2RespInternal.io.deq.ready, _T_397 node _T_398 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_399 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h1)) node _T_400 = and(_T_398, _T_399) connect Queue4_L2RespInternal_1.io.deq.ready, _T_400 node _T_401 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_402 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h2)) node _T_403 = and(_T_401, _T_402) connect Queue4_L2RespInternal_2.io.deq.ready, _T_403 node _T_404 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_405 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h3)) node _T_406 = and(_T_404, _T_405) connect Queue4_L2RespInternal_3.io.deq.ready, _T_406 node _T_407 = and(masterNodeOut.d.ready, masterNodeOut.d.valid) when _T_407 : node opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) when opdata : regreset loginfo_cycles_40 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_80 = add(loginfo_cycles_40, UInt<1>(0h1)) node _loginfo_cycles_T_81 = tail(_loginfo_cycles_T_80, 1) connect loginfo_cycles_40, _loginfo_cycles_T_81 node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_40) : printf_85 node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n", masterNodeOut.d.bits.data, global_memop_ackd, masterNodeOut.d.bits.source) : printf_86 else : regreset loginfo_cycles_41 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_82 = add(loginfo_cycles_41, UInt<1>(0h1)) node _loginfo_cycles_T_83 = tail(_loginfo_cycles_T_82, 1) connect loginfo_cycles_41, _loginfo_cycles_T_83 node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_41) : printf_87 node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: resp(write) opnum: %d, gettag: %d\n", global_memop_ackd, masterNodeOut.d.bits.source) : printf_88 node _T_416 = and(response_output.ready, response_output.valid) when _T_416 : regreset loginfo_cycles_42 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_84 = add(loginfo_cycles_42, UInt<1>(0h1)) node _loginfo_cycles_T_85 = tail(_loginfo_cycles_T_84, 1) connect loginfo_cycles_42, _loginfo_cycles_T_85 node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_42) : printf_89 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "[huf_jt_writer] L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n", resultdata, global_memop_resp_to_user, outstanding_req_addr.io.deq.bits.tag) : printf_90 node _T_421 = and(response_latency_injection_q.io.deq.ready, response_latency_injection_q.io.deq.valid) when _T_421 : node _global_memop_ackd_T = add(global_memop_ackd, UInt<1>(0h1)) node _global_memop_ackd_T_1 = tail(_global_memop_ackd_T, 1) connect global_memop_ackd, _global_memop_ackd_T_1 node _T_422 = and(response_output.ready, response_output.valid) when _T_422 : node _global_memop_resp_to_user_T = add(global_memop_resp_to_user, UInt<1>(0h1)) node _global_memop_resp_to_user_T_1 = tail(_global_memop_resp_to_user_T, 1) connect global_memop_resp_to_user, _global_memop_resp_to_user_T_1 extmodule plusarg_reader_134 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_135 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module L2MemHelperLatencyInjection_9( // @[L2MemHelperLatencyInjection.scala:29:7] input clock, // @[L2MemHelperLatencyInjection.scala:29:7] input reset, // @[L2MemHelperLatencyInjection.scala:29:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_master_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_master_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [255:0] auto_master_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_master_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [255:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_userif_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_userif_req_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [2:0] io_userif_req_bits_size, // @[L2MemHelperLatencyInjection.scala:33:14] input [255:0] io_userif_req_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_bits_cmd, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_resp_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [255:0] io_userif_resp_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_no_memops_inflight, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_latency_inject_cycles, // @[L2MemHelperLatencyInjection.scala:33:14] input io_sfence, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [26:0] io_ptw_req_bits_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_bits_bits_need_gpa, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_ptw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_final, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hx, // @[L2MemHelperLatencyInjection.scala:33:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_d, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_g, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_u, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_r, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_level, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_homogeneous, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_is_pte, // @[L2MemHelperLatencyInjection.scala:33:14] input [3:0] io_ptw_ptbr_mode, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_ptbr_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_status_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spvp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_gstatus_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_ptw_gstatus_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_ptw_gstatus_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_uie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_0_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_0_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_1_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_1_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_2_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_2_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_3_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_3_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_4_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_4_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_5_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_5_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_6_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_6_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_7_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_7_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_status_bits_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_status_bits_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_uxl, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd_rv32, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_status_bits_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_xs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_uie // @[L2MemHelperLatencyInjection.scala:33:14] ); wire _response_latency_injection_q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:245:44] wire [1:0] _response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44] wire [255:0] _response_latency_injection_q_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:245:44] wire _Queue4_L2RespInternal_3_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_3_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_2_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_1_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _request_latency_injection_q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:151:43] wire _tags_for_issue_Q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:94:32] wire _tags_for_issue_Q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:94:32] wire [1:0] _tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32] wire _outstanding_req_addr_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:91:36] wire _outstanding_req_addr_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_addrindex; // @[L2MemHelperLatencyInjection.scala:91:36] wire [1:0] _outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36] wire _tlb_io_req_ready; // @[L2MemHelperLatencyInjection.scala:68:19] wire _tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19] wire [31:0] _tlb_io_resp_paddr; // @[L2MemHelperLatencyInjection.scala:68:19] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_valid_0 = io_userif_req_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_userif_req_bits_addr_0 = io_userif_req_bits_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] io_userif_req_bits_size_0 = io_userif_req_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_req_bits_data_0 = io_userif_req_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_bits_cmd_0 = io_userif_req_bits_cmd; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_ready_0 = io_userif_resp_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_latency_inject_cycles_0 = io_latency_inject_cycles; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_sfence_0 = io_sfence; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[L2MemHelperLatencyInjection.scala:29:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_valid_0 = io_status_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_debug_0 = io_status_bits_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_cease_0 = io_status_bits_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_wfi_0 = io_status_bits_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_status_bits_isa_0 = io_status_bits_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_dprv_0 = io_status_bits_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_dv_0 = io_status_bits_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_prv_0 = io_status_bits_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_v_0 = io_status_bits_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_0 = io_status_bits_sd; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_status_bits_zero2_0 = io_status_bits_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpv_0 = io_status_bits_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_gva_0 = io_status_bits_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mbe_0 = io_status_bits_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sbe_0 = io_status_bits_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_sxl_0 = io_status_bits_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_uxl_0 = io_status_bits_uxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_rv32_0 = io_status_bits_sd_rv32; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_status_bits_zero1_0 = io_status_bits_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tsr_0 = io_status_bits_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tw_0 = io_status_bits_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tvm_0 = io_status_bits_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mxr_0 = io_status_bits_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sum_0 = io_status_bits_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mprv_0 = io_status_bits_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_xs_0 = io_status_bits_xs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_fs_0 = io_status_bits_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_mpp_0 = io_status_bits_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_vs_0 = io_status_bits_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spp_0 = io_status_bits_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpie_0 = io_status_bits_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_ube_0 = io_status_bits_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spie_0 = io_status_bits_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_upie_0 = io_status_bits_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mie_0 = io_status_bits_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_hie_0 = io_status_bits_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sie_0 = io_status_bits_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_uie_0 = io_status_bits_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire _printf_T = reset; // @[annotations.scala:102:49] wire _printf_T_2 = reset; // @[annotations.scala:102:49] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_ube = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_upie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_hie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_uie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtw = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_hu = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire bundle_corrupt = 1'h0; // @[Edges.scala:460:17] wire _legal_T_125 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_131 = 1'h0; // @[Parameters.scala:684:54] wire bundle_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_valid = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_64 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_65 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_66 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_73 = 1'h1; // @[Parameters.scala:92:28] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] bundle_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] bundle_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_1_param = 3'h0; // @[Edges.scala:480:17] wire [255:0] bundle_data = 256'h0; // @[Edges.scala:460:17] wire [2:0] bundle_opcode = 3'h4; // @[Edges.scala:460:17] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire request_input_ready; // @[L2MemHelperLatencyInjection.scala:44:27] wire request_input_valid = io_userif_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [63:0] request_input_bits_addr = io_userif_req_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [2:0] request_input_bits_size = io_userif_req_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [255:0] request_input_bits_data = io_userif_req_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire request_input_bits_cmd = io_userif_req_bits_cmd_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire response_output_ready = io_userif_resp_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire response_output_valid; // @[L2MemHelperLatencyInjection.scala:53:29] wire [255:0] response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:53:29] wire _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:128:57] wire [2:0] auto_master_out_a_bits_opcode_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_a_bits_param_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_a_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_a_bits_source_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_address_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_mask_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_a_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_bits_corrupt_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_resp_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_no_memops_inflight_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_opcode_0 = masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_param_0 = masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_size_0 = masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_source_0 = masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_mask_0 = masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_data_0 = masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_corrupt_0 = masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_master_out_d_ready_0 = masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire _request_input_ready_T_4; // @[Misc.scala:26:53] assign io_userif_req_ready_0 = request_input_ready; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire _response_output_valid_T; // @[Misc.scala:26:53] assign io_userif_resp_valid_0 = response_output_valid; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire [255:0] resultdata; // @[L2MemHelperLatencyInjection.scala:307:15] assign io_userif_resp_bits_data_0 = response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] reg status_debug; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_cease; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_wfi; // @[L2MemHelperLatencyInjection.scala:62:19] reg [31:0] status_isa; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_dprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_dv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_prv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_v; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd; // @[L2MemHelperLatencyInjection.scala:62:19] reg [22:0] status_zero2; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_gva; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_sxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_uxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd_rv32; // @[L2MemHelperLatencyInjection.scala:62:19] reg [7:0] status_zero1; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tsr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tw; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tvm; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mxr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sum; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_xs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_fs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_mpp; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_vs; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spp; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_ube; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_upie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_hie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_uie; // @[L2MemHelperLatencyInjection.scala:62:19] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _tlb_ready_T = ~_tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19, :74:39] wire tlb_ready = _tlb_io_req_ready & _tlb_ready_T; // @[L2MemHelperLatencyInjection.scala:68:19, :74:{36,39}] reg [2:0] tags_init_reg; // @[L2MemHelperLatencyInjection.scala:98:30] wire _T_4 = tags_init_reg != 3'h4; // @[L2MemHelperLatencyInjection.scala:98:30, :99:23] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] wire [3:0] _tags_init_reg_T = {1'h0, tags_init_reg} + 4'h1; // @[L2MemHelperLatencyInjection.scala:98:30, :104:38] wire [2:0] _tags_init_reg_T_1 = _tags_init_reg_T[2:0]; // @[L2MemHelperLatencyInjection.scala:104:38] wire [70:0] _addr_mask_check_T = 71'h1 << request_input_bits_size; // @[L2MemHelperLatencyInjection.scala:44:27, :108:36] wire [71:0] _addr_mask_check_T_1 = {1'h0, _addr_mask_check_T} - 72'h1; // @[L2MemHelperLatencyInjection.scala:108:{36,64}] wire [70:0] addr_mask_check = _addr_mask_check_T_1[70:0]; // @[L2MemHelperLatencyInjection.scala:108:64] wire _assertcheck_T = ~request_input_valid; // @[L2MemHelperLatencyInjection.scala:44:27, :109:30] wire [70:0] _assertcheck_T_1 = {7'h0, addr_mask_check[63:0] & request_input_bits_addr}; // @[L2MemHelperLatencyInjection.scala:44:27, :108:64, :109:81] wire _assertcheck_T_2 = _assertcheck_T_1 == 71'h0; // @[L2MemHelperLatencyInjection.scala:108:64, :109:{81,100}] wire _assertcheck_T_3 = _assertcheck_T | _assertcheck_T_2; // @[L2MemHelperLatencyInjection.scala:109:{30,52,100}] reg assertcheck; // @[L2MemHelperLatencyInjection.scala:109:28] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] global_memop_accepted; // @[L2MemHelperLatencyInjection.scala:117:38] wire [64:0] _global_memop_accepted_T = {1'h0, global_memop_accepted} + 65'h1; // @[L2MemHelperLatencyInjection.scala:117:38, :119:52] wire [63:0] _global_memop_accepted_T_1 = _global_memop_accepted_T[63:0]; // @[L2MemHelperLatencyInjection.scala:119:52] reg [63:0] global_memop_sent; // @[L2MemHelperLatencyInjection.scala:122:34] reg [63:0] global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:124:34] reg [63:0] global_memop_resp_to_user; // @[L2MemHelperLatencyInjection.scala:126:42] assign _io_userif_no_memops_inflight_T = global_memop_accepted == global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:117:38, :124:34, :128:57] assign io_userif_no_memops_inflight_0 = _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:29:7, :128:57] wire [64:0] _GEN = {1'h0, global_memop_sent}; // @[L2MemHelperLatencyInjection.scala:122:34, :130:54] wire [64:0] _GEN_0 = {1'h0, global_memop_ackd}; // @[L2MemHelperLatencyInjection.scala:124:34, :130:54] wire [64:0] _GEN_1 = _GEN - _GEN_0; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:130:54] assign _free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _assert_free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:131:61] assign _assert_free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54, :131:61] wire [63:0] _free_outstanding_op_slots_T_1 = _free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:130:54] wire free_outstanding_op_slots = _free_outstanding_op_slots_T_1 < 64'h4; // @[L2MemHelperLatencyInjection.scala:130:{54,75}] wire [63:0] _assert_free_outstanding_op_slots_T_1 = _assert_free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:131:61] wire assert_free_outstanding_op_slots = _assert_free_outstanding_op_slots_T_1 < 64'h5; // @[L2MemHelperLatencyInjection.scala:131:{61,82}] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] wire [64:0] _global_memop_sent_T = _GEN + 65'h1; // @[L2MemHelperLatencyInjection.scala:130:54, :140:44] wire [63:0] _global_memop_sent_T_1 = _global_memop_sent_T[63:0]; // @[L2MemHelperLatencyInjection.scala:140:44] reg [63:0] cur_cycle; // @[L2MemHelperLatencyInjection.scala:146:26] wire [64:0] _cur_cycle_T = {1'h0, cur_cycle} + 65'h1; // @[L2MemHelperLatencyInjection.scala:146:26, :147:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[L2MemHelperLatencyInjection.scala:147:26] wire [31:0] _GEN_2 = {_tlb_io_resp_paddr[31:14], _tlb_io_resp_paddr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_4; // @[Parameters.scala:137:31] assign _legal_T_4 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _legal_T_67; // @[Parameters.scala:137:31] assign _legal_T_67 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_62 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _GEN_3 = request_input_bits_size != 3'h7; // @[Parameters.scala:92:38] wire _legal_T_11; // @[Parameters.scala:92:38] assign _legal_T_11 = _GEN_3; // @[Parameters.scala:92:38] wire _legal_T_74; // @[Parameters.scala:92:38] assign _legal_T_74 = _GEN_3; // @[Parameters.scala:92:38] wire _legal_T_12 = _legal_T_11; // @[Parameters.scala:92:{33,38}] wire _legal_T_13 = _legal_T_12; // @[Parameters.scala:684:29] wire [31:0] _legal_T_14; // @[Parameters.scala:137:31] wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_16 = _legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46] wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = {_tlb_io_resp_paddr[31:17], _tlb_io_resp_paddr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_19; // @[Parameters.scala:137:31] assign _legal_T_19 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_24; // @[Parameters.scala:137:31] assign _legal_T_24 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_126; // @[Parameters.scala:137:31] assign _legal_T_126 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_21 = _legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46] wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_26 = _legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46] wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_5 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_29; // @[Parameters.scala:137:31] assign _legal_T_29 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_87; // @[Parameters.scala:137:31] assign _legal_T_87 = _GEN_5; // @[Parameters.scala:137:31] wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_31 = _legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46] wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_6 = {_tlb_io_resp_paddr[31:28], _tlb_io_resp_paddr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_34; // @[Parameters.scala:137:31] assign _legal_T_34 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_39; // @[Parameters.scala:137:31] assign _legal_T_39 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_97; // @[Parameters.scala:137:31] assign _legal_T_97 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_102; // @[Parameters.scala:137:31] assign _legal_T_102 = _GEN_6; // @[Parameters.scala:137:31] wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_36 = _legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46] wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_41 = _legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46] wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_7 = {_tlb_io_resp_paddr[31:29], _tlb_io_resp_paddr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_44; // @[Parameters.scala:137:31] assign _legal_T_44 = _GEN_7; // @[Parameters.scala:137:31] wire [31:0] _legal_T_107; // @[Parameters.scala:137:31] assign _legal_T_107 = _GEN_7; // @[Parameters.scala:137:31] wire [32:0] _legal_T_45 = {1'h0, _legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_46 = _legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_47 = _legal_T_46; // @[Parameters.scala:137:46] wire _legal_T_48 = _legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_8 = _tlb_io_resp_paddr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _legal_T_49; // @[Parameters.scala:137:31] assign _legal_T_49 = _GEN_8; // @[Parameters.scala:137:31] wire [31:0] _legal_T_112; // @[Parameters.scala:137:31] assign _legal_T_112 = _GEN_8; // @[Parameters.scala:137:31] wire [32:0] _legal_T_50 = {1'h0, _legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_51 = _legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_52 = _legal_T_51; // @[Parameters.scala:137:46] wire _legal_T_53 = _legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_54 = _legal_T_18 | _legal_T_23; // @[Parameters.scala:685:42] wire _legal_T_55 = _legal_T_54 | _legal_T_28; // @[Parameters.scala:685:42] wire _legal_T_56 = _legal_T_55 | _legal_T_33; // @[Parameters.scala:685:42] wire _legal_T_57 = _legal_T_56 | _legal_T_38; // @[Parameters.scala:685:42] wire _legal_T_58 = _legal_T_57 | _legal_T_43; // @[Parameters.scala:685:42] wire _legal_T_59 = _legal_T_58 | _legal_T_48; // @[Parameters.scala:685:42] wire _legal_T_60 = _legal_T_59 | _legal_T_53; // @[Parameters.scala:685:42] wire _legal_T_61 = _legal_T_13 & _legal_T_60; // @[Parameters.scala:684:{29,54}, :685:42] wire legal = _legal_T_62 | _legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [31:0] _a_mask_T; // @[Misc.scala:222:10] wire [3:0] bundle_size; // @[Edges.scala:460:17] wire [1:0] bundle_source; // @[Edges.scala:460:17] wire [31:0] bundle_address; // @[Edges.scala:460:17] wire [31:0] bundle_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_9 = {1'h0, request_input_bits_size}; // @[Edges.scala:463:15] assign bundle_size = _GEN_9; // @[Edges.scala:460:17, :463:15] wire [3:0] bundle_1_size; // @[Edges.scala:480:17] assign bundle_1_size = _GEN_9; // @[Edges.scala:463:15, :480:17] wire [4:0] _GEN_10 = {2'h0, request_input_bits_size}; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _a_mask_sizeOH_T = _GEN_10; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _a_mask_sizeOH_T_3 = _GEN_10; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T = _a_mask_sizeOH_T; // @[OneHot.scala:64:31] wire [2:0] a_mask_sizeOH_shiftAmount = _a_mask_sizeOH_shiftAmount_T[2:0]; // @[OneHot.scala:64:{31,49}] wire [7:0] _a_mask_sizeOH_T_1 = 8'h1 << a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _a_mask_sizeOH_T_2 = _a_mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] a_mask_sizeOH = {_a_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire _GEN_11 = request_input_bits_size > 3'h4; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21] assign a_mask_sub_sub_sub_sub_sub_0_1 = _GEN_11; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_sub_0_1_1; // @[Misc.scala:206:21] assign a_mask_sub_sub_sub_sub_sub_0_1_1 = _GEN_11; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_size = a_mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_sub_bit = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_sub_acc_T = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _a_mask_sub_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire a_mask_sub_sub_sub_size = a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_bit = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_2_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_2_1 = a_mask_sub_sub_sub_sub_1_1 | _a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_3_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_3_1 = a_mask_sub_sub_sub_sub_1_1 | _a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_size = a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_bit = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_bit_1 = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T = a_mask_sub_sub_size & a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_0_1 = a_mask_sub_sub_sub_0_1 | _a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_1_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_1 = a_mask_sub_sub_size & a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_1_1 = a_mask_sub_sub_sub_0_1 | _a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_2_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_2 = a_mask_sub_sub_size & a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_2_1 = a_mask_sub_sub_sub_1_1 | _a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_3_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_3 = a_mask_sub_sub_size & a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_3_1 = a_mask_sub_sub_sub_1_1 | _a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_4_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_4 = a_mask_sub_sub_size & a_mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_4_1 = a_mask_sub_sub_sub_2_1 | _a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_5_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_5 = a_mask_sub_sub_size & a_mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_5_1 = a_mask_sub_sub_sub_2_1 | _a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_6_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_6 = a_mask_sub_sub_size & a_mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_6_1 = a_mask_sub_sub_sub_3_1 | _a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_7_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_7 = a_mask_sub_sub_size & a_mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_7_1 = a_mask_sub_sub_sub_3_1 | _a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_size = a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_bit = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_bit_1 = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T = a_mask_sub_size & a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_0_1 = a_mask_sub_sub_0_1 | _a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_1 = a_mask_sub_size & a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_1_1 = a_mask_sub_sub_0_1 | _a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_2 = a_mask_sub_size & a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_2_1 = a_mask_sub_sub_1_1 | _a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_3 = a_mask_sub_size & a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_3_1 = a_mask_sub_sub_1_1 | _a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_4_2 = a_mask_sub_sub_2_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_4 = a_mask_sub_size & a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_4_1 = a_mask_sub_sub_2_1 | _a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_5_2 = a_mask_sub_sub_2_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_5 = a_mask_sub_size & a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_5_1 = a_mask_sub_sub_2_1 | _a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_6_2 = a_mask_sub_sub_3_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_6 = a_mask_sub_size & a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_6_1 = a_mask_sub_sub_3_1 | _a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_7_2 = a_mask_sub_sub_3_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_7 = a_mask_sub_size & a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_7_1 = a_mask_sub_sub_3_1 | _a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_8_2 = a_mask_sub_sub_4_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_8 = a_mask_sub_size & a_mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_8_1 = a_mask_sub_sub_4_1 | _a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_sub_9_2 = a_mask_sub_sub_4_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_9 = a_mask_sub_size & a_mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_9_1 = a_mask_sub_sub_4_1 | _a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_sub_10_2 = a_mask_sub_sub_5_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_10 = a_mask_sub_size & a_mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_10_1 = a_mask_sub_sub_5_1 | _a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_sub_11_2 = a_mask_sub_sub_5_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_11 = a_mask_sub_size & a_mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_11_1 = a_mask_sub_sub_5_1 | _a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_sub_12_2 = a_mask_sub_sub_6_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_12 = a_mask_sub_size & a_mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_12_1 = a_mask_sub_sub_6_1 | _a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_sub_13_2 = a_mask_sub_sub_6_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_13 = a_mask_sub_size & a_mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_13_1 = a_mask_sub_sub_6_1 | _a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_sub_14_2 = a_mask_sub_sub_7_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_14 = a_mask_sub_size & a_mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_14_1 = a_mask_sub_sub_7_1 | _a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_sub_15_2 = a_mask_sub_sub_7_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_15 = a_mask_sub_size & a_mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_15_1 = a_mask_sub_sub_7_1 | _a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_size = a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire a_mask_bit = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_bit_1 = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_size & a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc = a_mask_sub_0_1 | _a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_size & a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_1 = a_mask_sub_0_1 | _a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_size & a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_2 = a_mask_sub_1_1 | _a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_size & a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_3 = a_mask_sub_1_1 | _a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_size & a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_4 = a_mask_sub_2_1 | _a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_size & a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_5 = a_mask_sub_2_1 | _a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_size & a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_6 = a_mask_sub_3_1 | _a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_size & a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_7 = a_mask_sub_3_1 | _a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_eq_8 = a_mask_sub_4_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_8 = a_mask_size & a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_8 = a_mask_sub_4_1 | _a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_eq_9 = a_mask_sub_4_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_9 = a_mask_size & a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_9 = a_mask_sub_4_1 | _a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_eq_10 = a_mask_sub_5_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_10 = a_mask_size & a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_10 = a_mask_sub_5_1 | _a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_eq_11 = a_mask_sub_5_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_11 = a_mask_size & a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_11 = a_mask_sub_5_1 | _a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_eq_12 = a_mask_sub_6_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_12 = a_mask_size & a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_12 = a_mask_sub_6_1 | _a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_eq_13 = a_mask_sub_6_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_13 = a_mask_size & a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_13 = a_mask_sub_6_1 | _a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_eq_14 = a_mask_sub_7_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_14 = a_mask_size & a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_14 = a_mask_sub_7_1 | _a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_eq_15 = a_mask_sub_7_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_15 = a_mask_size & a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_15 = a_mask_sub_7_1 | _a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_eq_16 = a_mask_sub_8_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_16 = a_mask_size & a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_16 = a_mask_sub_8_1 | _a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire a_mask_eq_17 = a_mask_sub_8_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_17 = a_mask_size & a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_17 = a_mask_sub_8_1 | _a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire a_mask_eq_18 = a_mask_sub_9_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_18 = a_mask_size & a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_18 = a_mask_sub_9_1 | _a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire a_mask_eq_19 = a_mask_sub_9_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_19 = a_mask_size & a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_19 = a_mask_sub_9_1 | _a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire a_mask_eq_20 = a_mask_sub_10_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_20 = a_mask_size & a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_20 = a_mask_sub_10_1 | _a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire a_mask_eq_21 = a_mask_sub_10_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_21 = a_mask_size & a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_21 = a_mask_sub_10_1 | _a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire a_mask_eq_22 = a_mask_sub_11_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_22 = a_mask_size & a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_22 = a_mask_sub_11_1 | _a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire a_mask_eq_23 = a_mask_sub_11_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_23 = a_mask_size & a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_23 = a_mask_sub_11_1 | _a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire a_mask_eq_24 = a_mask_sub_12_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_24 = a_mask_size & a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_24 = a_mask_sub_12_1 | _a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire a_mask_eq_25 = a_mask_sub_12_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_25 = a_mask_size & a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_25 = a_mask_sub_12_1 | _a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire a_mask_eq_26 = a_mask_sub_13_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_26 = a_mask_size & a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_26 = a_mask_sub_13_1 | _a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire a_mask_eq_27 = a_mask_sub_13_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_27 = a_mask_size & a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_27 = a_mask_sub_13_1 | _a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire a_mask_eq_28 = a_mask_sub_14_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_28 = a_mask_size & a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_28 = a_mask_sub_14_1 | _a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire a_mask_eq_29 = a_mask_sub_14_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_29 = a_mask_size & a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_29 = a_mask_sub_14_1 | _a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire a_mask_eq_30 = a_mask_sub_15_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_30 = a_mask_size & a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_30 = a_mask_sub_15_1 | _a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire a_mask_eq_31 = a_mask_sub_15_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_31 = a_mask_size & a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_31 = a_mask_sub_15_1 | _a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] a_mask_lo_lo_lo_lo = {a_mask_acc_1, a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_lo_hi = {a_mask_acc_3, a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_lo = {a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo = {a_mask_acc_5, a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_hi_hi = {a_mask_acc_7, a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_hi = {a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo = {a_mask_lo_lo_hi, a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo = {a_mask_acc_9, a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_lo_hi = {a_mask_acc_11, a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_lo = {a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo = {a_mask_acc_13, a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_hi_hi = {a_mask_acc_15, a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_hi = {a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi = {a_mask_lo_hi_hi, a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] a_mask_lo = {a_mask_lo_hi, a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo = {a_mask_acc_17, a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_lo_hi = {a_mask_acc_19, a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_lo = {a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo = {a_mask_acc_21, a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_hi_hi = {a_mask_acc_23, a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_hi = {a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo = {a_mask_hi_lo_hi, a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo = {a_mask_acc_25, a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_lo_hi = {a_mask_acc_27, a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_lo = {a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo = {a_mask_acc_29, a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_hi_hi = {a_mask_acc_31, a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_hi = {a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi = {a_mask_hi_hi_hi, a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] a_mask_hi = {a_mask_hi_hi, a_mask_hi_lo}; // @[Misc.scala:222:10] assign _a_mask_T = {a_mask_hi, a_mask_lo}; // @[Misc.scala:222:10] assign bundle_mask = _a_mask_T; // @[Misc.scala:222:10] wire [510:0] _T_31 = {255'h0, request_input_bits_data} << {503'h0, request_input_bits_addr[4:0], 3'h0}; // @[L2MemHelperLatencyInjection.scala:44:27, :172:{58,86}] wire [32:0] _legal_T_68 = {1'h0, _legal_T_67}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_69 = _legal_T_68 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_70 = _legal_T_69; // @[Parameters.scala:137:46] wire _legal_T_71 = _legal_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_72 = _legal_T_71; // @[Parameters.scala:684:54] wire _legal_T_132 = _legal_T_72; // @[Parameters.scala:684:54, :686:26] wire _legal_T_75 = _legal_T_74; // @[Parameters.scala:92:{33,38}] wire _legal_T_76 = _legal_T_75; // @[Parameters.scala:684:29] wire [31:0] _legal_T_77; // @[Parameters.scala:137:31] wire [32:0] _legal_T_78 = {1'h0, _legal_T_77}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_79 = _legal_T_78 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_80 = _legal_T_79; // @[Parameters.scala:137:46] wire _legal_T_81 = _legal_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_82 = {_tlb_io_resp_paddr[31:21], _tlb_io_resp_paddr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_83 = {1'h0, _legal_T_82}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_84 = _legal_T_83 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_85 = _legal_T_84; // @[Parameters.scala:137:46] wire _legal_T_86 = _legal_T_85 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_88 = {1'h0, _legal_T_87}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_89 = _legal_T_88 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_90 = _legal_T_89; // @[Parameters.scala:137:46] wire _legal_T_91 = _legal_T_90 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_92 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_93 = {1'h0, _legal_T_92}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_94 = _legal_T_93 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_95 = _legal_T_94; // @[Parameters.scala:137:46] wire _legal_T_96 = _legal_T_95 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_98 = {1'h0, _legal_T_97}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_99 = _legal_T_98 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_100 = _legal_T_99; // @[Parameters.scala:137:46] wire _legal_T_101 = _legal_T_100 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_103 = {1'h0, _legal_T_102}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_104 = _legal_T_103 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_105 = _legal_T_104; // @[Parameters.scala:137:46] wire _legal_T_106 = _legal_T_105 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_108 = {1'h0, _legal_T_107}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_109 = _legal_T_108 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_110 = _legal_T_109; // @[Parameters.scala:137:46] wire _legal_T_111 = _legal_T_110 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_113 = {1'h0, _legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_114 = _legal_T_113 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_115 = _legal_T_114; // @[Parameters.scala:137:46] wire _legal_T_116 = _legal_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_117 = _legal_T_81 | _legal_T_86; // @[Parameters.scala:685:42] wire _legal_T_118 = _legal_T_117 | _legal_T_91; // @[Parameters.scala:685:42] wire _legal_T_119 = _legal_T_118 | _legal_T_96; // @[Parameters.scala:685:42] wire _legal_T_120 = _legal_T_119 | _legal_T_101; // @[Parameters.scala:685:42] wire _legal_T_121 = _legal_T_120 | _legal_T_106; // @[Parameters.scala:685:42] wire _legal_T_122 = _legal_T_121 | _legal_T_111; // @[Parameters.scala:685:42] wire _legal_T_123 = _legal_T_122 | _legal_T_116; // @[Parameters.scala:685:42] wire _legal_T_124 = _legal_T_76 & _legal_T_123; // @[Parameters.scala:684:{29,54}, :685:42] wire [32:0] _legal_T_127 = {1'h0, _legal_T_126}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_128 = _legal_T_127 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_129 = _legal_T_128; // @[Parameters.scala:137:46] wire _legal_T_130 = _legal_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_133 = _legal_T_132 | _legal_T_124; // @[Parameters.scala:684:54, :686:26] wire legal_1 = _legal_T_133; // @[Parameters.scala:686:26] wire [31:0] _a_mask_T_1; // @[Misc.scala:222:10] wire [1:0] bundle_1_source; // @[Edges.scala:480:17] wire [31:0] bundle_1_address; // @[Edges.scala:480:17] wire [31:0] bundle_1_mask; // @[Edges.scala:480:17] wire [255:0] bundle_1_data; // @[Edges.scala:480:17] wire [4:0] _a_mask_sizeOH_shiftAmount_T_1 = _a_mask_sizeOH_T_3; // @[OneHot.scala:64:31] wire [2:0] a_mask_sizeOH_shiftAmount_1 = _a_mask_sizeOH_shiftAmount_T_1[2:0]; // @[OneHot.scala:64:{31,49}] wire [7:0] _a_mask_sizeOH_T_4 = 8'h1 << a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [4:0] _a_mask_sizeOH_T_5 = _a_mask_sizeOH_T_4[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] a_mask_sizeOH_1 = {_a_mask_sizeOH_T_5[4:1], 1'h1}; // @[OneHot.scala:65:27] wire a_mask_sub_sub_sub_sub_size_1 = a_mask_sizeOH_1[4]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _a_mask_sub_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire a_mask_sub_sub_sub_size_1 = a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_4 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_5 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_2_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_6 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_2_1_1 = a_mask_sub_sub_sub_sub_1_1_1 | _a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_3_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_7 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_3_1_1 = a_mask_sub_sub_sub_sub_1_1_1 | _a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_size_1 = a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_nbit_1 = ~a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_8 = a_mask_sub_sub_size_1 & a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_0_1_1 = a_mask_sub_sub_sub_0_1_1 | _a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_1_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_9 = a_mask_sub_sub_size_1 & a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_1_1_1 = a_mask_sub_sub_sub_0_1_1 | _a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_2_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_10 = a_mask_sub_sub_size_1 & a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_2_1_1 = a_mask_sub_sub_sub_1_1_1 | _a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_3_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_11 = a_mask_sub_sub_size_1 & a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_3_1_1 = a_mask_sub_sub_sub_1_1_1 | _a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_4_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_12 = a_mask_sub_sub_size_1 & a_mask_sub_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_4_1_1 = a_mask_sub_sub_sub_2_1_1 | _a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_5_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_13 = a_mask_sub_sub_size_1 & a_mask_sub_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_5_1_1 = a_mask_sub_sub_sub_2_1_1 | _a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_6_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_14 = a_mask_sub_sub_size_1 & a_mask_sub_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_6_1_1 = a_mask_sub_sub_sub_3_1_1 | _a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_7_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_15 = a_mask_sub_sub_size_1 & a_mask_sub_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_7_1_1 = a_mask_sub_sub_sub_3_1_1 | _a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_sub_size_1 = a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_16 = a_mask_sub_size_1 & a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_0_1_1 = a_mask_sub_sub_0_1_1 | _a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire a_mask_sub_1_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_17 = a_mask_sub_size_1 & a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_1_1_1 = a_mask_sub_sub_0_1_1 | _a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire a_mask_sub_2_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_18 = a_mask_sub_size_1 & a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_2_1_1 = a_mask_sub_sub_1_1_1 | _a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire a_mask_sub_3_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_19 = a_mask_sub_size_1 & a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_3_1_1 = a_mask_sub_sub_1_1_1 | _a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire a_mask_sub_4_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_20 = a_mask_sub_size_1 & a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_4_1_1 = a_mask_sub_sub_2_1_1 | _a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire a_mask_sub_5_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_21 = a_mask_sub_size_1 & a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_5_1_1 = a_mask_sub_sub_2_1_1 | _a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire a_mask_sub_6_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_22 = a_mask_sub_size_1 & a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_6_1_1 = a_mask_sub_sub_3_1_1 | _a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire a_mask_sub_7_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_23 = a_mask_sub_size_1 & a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_7_1_1 = a_mask_sub_sub_3_1_1 | _a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire a_mask_sub_8_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_24 = a_mask_sub_size_1 & a_mask_sub_8_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_8_1_1 = a_mask_sub_sub_4_1_1 | _a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire a_mask_sub_9_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_25 = a_mask_sub_size_1 & a_mask_sub_9_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_9_1_1 = a_mask_sub_sub_4_1_1 | _a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire a_mask_sub_10_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_26 = a_mask_sub_size_1 & a_mask_sub_10_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_10_1_1 = a_mask_sub_sub_5_1_1 | _a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire a_mask_sub_11_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_27 = a_mask_sub_size_1 & a_mask_sub_11_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_11_1_1 = a_mask_sub_sub_5_1_1 | _a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire a_mask_sub_12_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_28 = a_mask_sub_size_1 & a_mask_sub_12_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_12_1_1 = a_mask_sub_sub_6_1_1 | _a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire a_mask_sub_13_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_29 = a_mask_sub_size_1 & a_mask_sub_13_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_13_1_1 = a_mask_sub_sub_6_1_1 | _a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire a_mask_sub_14_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_30 = a_mask_sub_size_1 & a_mask_sub_14_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_14_1_1 = a_mask_sub_sub_7_1_1 | _a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire a_mask_sub_15_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_31 = a_mask_sub_size_1 & a_mask_sub_15_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_15_1_1 = a_mask_sub_sub_7_1_1 | _a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire a_mask_size_1 = a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_eq_32 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_32 = a_mask_size_1 & a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_32 = a_mask_sub_0_1_1 | _a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire a_mask_eq_33 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_33 = a_mask_size_1 & a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_33 = a_mask_sub_0_1_1 | _a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire a_mask_eq_34 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_34 = a_mask_size_1 & a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_34 = a_mask_sub_1_1_1 | _a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire a_mask_eq_35 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_35 = a_mask_size_1 & a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_35 = a_mask_sub_1_1_1 | _a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire a_mask_eq_36 = a_mask_sub_2_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_36 = a_mask_size_1 & a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_36 = a_mask_sub_2_1_1 | _a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire a_mask_eq_37 = a_mask_sub_2_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_37 = a_mask_size_1 & a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_37 = a_mask_sub_2_1_1 | _a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire a_mask_eq_38 = a_mask_sub_3_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_38 = a_mask_size_1 & a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_38 = a_mask_sub_3_1_1 | _a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire a_mask_eq_39 = a_mask_sub_3_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_39 = a_mask_size_1 & a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_39 = a_mask_sub_3_1_1 | _a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire a_mask_eq_40 = a_mask_sub_4_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_40 = a_mask_size_1 & a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_40 = a_mask_sub_4_1_1 | _a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire a_mask_eq_41 = a_mask_sub_4_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_41 = a_mask_size_1 & a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_41 = a_mask_sub_4_1_1 | _a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire a_mask_eq_42 = a_mask_sub_5_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_42 = a_mask_size_1 & a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_42 = a_mask_sub_5_1_1 | _a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire a_mask_eq_43 = a_mask_sub_5_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_43 = a_mask_size_1 & a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_43 = a_mask_sub_5_1_1 | _a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire a_mask_eq_44 = a_mask_sub_6_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_44 = a_mask_size_1 & a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_44 = a_mask_sub_6_1_1 | _a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire a_mask_eq_45 = a_mask_sub_6_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_45 = a_mask_size_1 & a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_45 = a_mask_sub_6_1_1 | _a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire a_mask_eq_46 = a_mask_sub_7_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_46 = a_mask_size_1 & a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_46 = a_mask_sub_7_1_1 | _a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire a_mask_eq_47 = a_mask_sub_7_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_47 = a_mask_size_1 & a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_47 = a_mask_sub_7_1_1 | _a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire a_mask_eq_48 = a_mask_sub_8_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_48 = a_mask_size_1 & a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_48 = a_mask_sub_8_1_1 | _a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire a_mask_eq_49 = a_mask_sub_8_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_49 = a_mask_size_1 & a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_49 = a_mask_sub_8_1_1 | _a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire a_mask_eq_50 = a_mask_sub_9_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_50 = a_mask_size_1 & a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_50 = a_mask_sub_9_1_1 | _a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire a_mask_eq_51 = a_mask_sub_9_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_51 = a_mask_size_1 & a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_51 = a_mask_sub_9_1_1 | _a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire a_mask_eq_52 = a_mask_sub_10_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_52 = a_mask_size_1 & a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_52 = a_mask_sub_10_1_1 | _a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire a_mask_eq_53 = a_mask_sub_10_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_53 = a_mask_size_1 & a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_53 = a_mask_sub_10_1_1 | _a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire a_mask_eq_54 = a_mask_sub_11_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_54 = a_mask_size_1 & a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_54 = a_mask_sub_11_1_1 | _a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire a_mask_eq_55 = a_mask_sub_11_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_55 = a_mask_size_1 & a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_55 = a_mask_sub_11_1_1 | _a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire a_mask_eq_56 = a_mask_sub_12_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_56 = a_mask_size_1 & a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_56 = a_mask_sub_12_1_1 | _a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire a_mask_eq_57 = a_mask_sub_12_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_57 = a_mask_size_1 & a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_57 = a_mask_sub_12_1_1 | _a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire a_mask_eq_58 = a_mask_sub_13_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_58 = a_mask_size_1 & a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_58 = a_mask_sub_13_1_1 | _a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire a_mask_eq_59 = a_mask_sub_13_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_59 = a_mask_size_1 & a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_59 = a_mask_sub_13_1_1 | _a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire a_mask_eq_60 = a_mask_sub_14_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_60 = a_mask_size_1 & a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_60 = a_mask_sub_14_1_1 | _a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire a_mask_eq_61 = a_mask_sub_14_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_61 = a_mask_size_1 & a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_61 = a_mask_sub_14_1_1 | _a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire a_mask_eq_62 = a_mask_sub_15_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_62 = a_mask_size_1 & a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_62 = a_mask_sub_15_1_1 | _a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire a_mask_eq_63 = a_mask_sub_15_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_63 = a_mask_size_1 & a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_63 = a_mask_sub_15_1_1 | _a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] a_mask_lo_lo_lo_lo_1 = {a_mask_acc_33, a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_lo_hi_1 = {a_mask_acc_35, a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_lo_1 = {a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo_1 = {a_mask_acc_37, a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_hi_hi_1 = {a_mask_acc_39, a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_hi_1 = {a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo_1 = {a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo_1 = {a_mask_acc_41, a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_lo_hi_1 = {a_mask_acc_43, a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_lo_1 = {a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo_1 = {a_mask_acc_45, a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_hi_hi_1 = {a_mask_acc_47, a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_hi_1 = {a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi_1 = {a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] a_mask_lo_1 = {a_mask_lo_hi_1, a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo_1 = {a_mask_acc_49, a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_lo_hi_1 = {a_mask_acc_51, a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_lo_1 = {a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo_1 = {a_mask_acc_53, a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_hi_hi_1 = {a_mask_acc_55, a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_hi_1 = {a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo_1 = {a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo_1 = {a_mask_acc_57, a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_lo_hi_1 = {a_mask_acc_59, a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_lo_1 = {a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo_1 = {a_mask_acc_61, a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_hi_hi_1 = {a_mask_acc_63, a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_hi_1 = {a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi_1 = {a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] a_mask_hi_1 = {a_mask_hi_hi_1, a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _a_mask_T_1 = {a_mask_hi_1, a_mask_lo_1}; // @[Misc.scala:222:10] assign bundle_1_mask = _a_mask_T_1; // @[Misc.scala:222:10] assign bundle_1_data = _T_31[255:0]; // @[Edges.scala:480:17, :489:15] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] wire _current_request_tag_has_response_space_T = _tags_for_issue_Q_io_deq_bits == 2'h0; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_1 = _Queue4_L2RespInternal_io_enq_ready & _current_request_tag_has_response_space_T; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_2 = _tags_for_issue_Q_io_deq_bits == 2'h1; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _current_request_tag_has_response_space_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_4 = _tags_for_issue_Q_io_deq_bits == 2'h2; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _current_request_tag_has_response_space_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_6 = &_tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _current_request_tag_has_response_space_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_8 = _current_request_tag_has_response_space_T_1 | _current_request_tag_has_response_space_T_3; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_9 = _current_request_tag_has_response_space_T_8 | _current_request_tag_has_response_space_T_5; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire current_request_tag_has_response_space = _current_request_tag_has_response_space_T_9 | _current_request_tag_has_response_space_T_7; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire [63:0] _outstanding_req_addr_io_enq_bits_addrindex_T = {59'h0, request_input_bits_addr[4:0]}; // @[L2MemHelperLatencyInjection.scala:44:27, :200:73] wire _request_latency_injection_q_io_enq_valid_T = request_input_valid & tlb_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_1 = _request_latency_injection_q_io_enq_valid_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_2 = _request_latency_injection_q_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_3 = _request_latency_injection_q_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_4 = _request_latency_injection_q_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _request_input_ready_T = _request_latency_injection_q_io_enq_ready & tlb_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_1 = _request_input_ready_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_2 = _request_input_ready_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_input_ready_T_3 = _request_input_ready_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] assign _request_input_ready_T_4 = _request_input_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] assign request_input_ready = _request_input_ready_T_4; // @[Misc.scala:26:53] wire _T_45 = request_input_valid & _request_latency_injection_q_io_enq_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T; // @[Misc.scala:26:53] assign _outstanding_req_addr_io_enq_valid_T = _T_45; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T; // @[Misc.scala:26:53] assign _tags_for_issue_Q_io_deq_ready_T = _T_45; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_1 = _outstanding_req_addr_io_enq_valid_T & tlb_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_2 = _outstanding_req_addr_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_3 = _outstanding_req_addr_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_4 = _outstanding_req_addr_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_1 = _tags_for_issue_Q_io_deq_ready_T & tlb_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_2 = _tags_for_issue_Q_io_deq_ready_T_1 & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_3 = _tags_for_issue_Q_io_deq_ready_T_2 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_4 = _tags_for_issue_Q_io_deq_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:26:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:26:33, :27:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:27:38] wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49] wire _printf_T_3 = ~_printf_T_2; // @[annotations.scala:102:49] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] wire _selectQready_T = _response_latency_injection_q_io_deq_bits_source == 2'h0; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_1 = _Queue4_L2RespInternal_io_enq_ready & _selectQready_T; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_2 = _response_latency_injection_q_io_deq_bits_source == 2'h1; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _selectQready_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_4 = _response_latency_injection_q_io_deq_bits_source == 2'h2; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _selectQready_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_6 = &_response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _selectQready_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_8 = _selectQready_T_1 | _selectQready_T_3; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_9 = _selectQready_T_8 | _selectQready_T_5; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire selectQready = _selectQready_T_9 | _selectQready_T_7; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _T_377 = selectQready & _response_latency_injection_q_io_deq_valid; // @[Misc.scala:26:53] wire tags_for_issue_Q_io_enq_valid = _T_377 | _T_4; // @[Misc.scala:26:53] wire [1:0] tags_for_issue_Q_io_enq_bits = _T_377 ? _response_latency_injection_q_io_deq_bits_source : tags_init_reg[1:0]; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] wire _response_latency_injection_q_io_deq_ready_T = selectQready & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_392 = _response_latency_injection_q_io_deq_valid & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_396 = _outstanding_req_addr_io_deq_bits_tag == 2'h0; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T = _T_396; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q = _T_396; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_1 = _Queue4_L2RespInternal_io_deq_valid & _queueValid_T; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_399 = _outstanding_req_addr_io_deq_bits_tag == 2'h1; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_2 = _T_399; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_1; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_1 = _T_399; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_3 = _Queue4_L2RespInternal_1_io_deq_valid & _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_402 = _outstanding_req_addr_io_deq_bits_tag == 2'h2; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_4 = _T_402; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_2; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_2 = _T_402; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_5 = _Queue4_L2RespInternal_2_io_deq_valid & _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_6 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_7 = _Queue4_L2RespInternal_3_io_deq_valid & _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_8 = _queueValid_T_1 | _queueValid_T_3; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_9 = _queueValid_T_8 | _queueValid_T_5; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire queueValid = _queueValid_T_9 | _queueValid_T_7; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire [255:0] resultdata_data; // @[L2MemHelperLatencyInjection.scala:300:20] wire [7:0] _GEN_12 = {_outstanding_req_addr_io_deq_bits_addrindex, 3'h0}; // @[L2MemHelperLatencyInjection.scala:91:36, :302:78] wire [7:0] _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_2 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_4 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_6 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [255:0] _resultdata_data_T_1 = _Queue4_L2RespInternal_io_deq_bits_data >> _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data = resultdata_is_current_q ? _resultdata_data_T_1 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_3 = _Queue4_L2RespInternal_1_io_deq_bits_data >> _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_1 = resultdata_is_current_q_1 ? _resultdata_data_T_3 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_5 = _Queue4_L2RespInternal_2_io_deq_bits_data >> _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_2 = resultdata_is_current_q_2 ? _resultdata_data_T_5 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire resultdata_is_current_q_3 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27, :299:31] wire [255:0] resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_7 = _Queue4_L2RespInternal_3_io_deq_bits_data >> _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_3 = resultdata_is_current_q_3 ? _resultdata_data_T_7 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] _resultdata_T = resultdata_data | resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_1 = _resultdata_T | resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign resultdata = _resultdata_T_1 | resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign response_output_bits_data = resultdata; // @[L2MemHelperLatencyInjection.scala:53:29, :307:15] assign _response_output_valid_T = queueValid & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] assign response_output_valid = _response_output_valid_T; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_deq_ready_T = queueValid & response_output_ready; // @[Misc.scala:26:53] wire _T_404 = response_output_ready & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] wire opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] wire _T_422 = response_output_ready & response_output_valid; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_1 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h1)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = and(_T_11, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_24 : node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_30 = or(_T_28, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_35 = cvt(_T_34) node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000))) node _T_37 = asSInt(_T_36) node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0))) node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_40 = cvt(_T_39) node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000))) node _T_42 = asSInt(_T_41) node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0))) node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<18>(0h2f000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<27>(0h4000000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<13>(0h1000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<30>(0h20000000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<15>(0h4000))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_38, _T_43) node _T_80 = or(_T_79, _T_48) node _T_81 = or(_T_80, _T_53) node _T_82 = or(_T_81, _T_58) node _T_83 = or(_T_82, _T_63) node _T_84 = or(_T_83, _T_68) node _T_85 = or(_T_84, _T_73) node _T_86 = or(_T_85, _T_78) node _T_87 = and(_T_33, _T_86) node _T_88 = or(UInt<1>(0h0), _T_87) node _T_89 = and(_T_32, _T_88) node _T_90 = asUInt(reset) node _T_91 = eq(_T_90, UInt<1>(0h0)) when _T_91 : node _T_92 = eq(_T_89, UInt<1>(0h0)) when _T_92 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_89, UInt<1>(0h1), "") : assert_2 node _T_93 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_94 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_95 = and(_T_93, _T_94) node _T_96 = or(UInt<1>(0h0), _T_95) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<14>(0h2000))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_103 = cvt(_T_102) node _T_104 = and(_T_103, asSInt(UInt<13>(0h1000))) node _T_105 = asSInt(_T_104) node _T_106 = eq(_T_105, asSInt(UInt<1>(0h0))) node _T_107 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<18>(0h2f000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<17>(0h10000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<27>(0h4000000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<13>(0h1000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<30>(0h20000000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<15>(0h4000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = or(_T_101, _T_106) node _T_143 = or(_T_142, _T_111) node _T_144 = or(_T_143, _T_116) node _T_145 = or(_T_144, _T_121) node _T_146 = or(_T_145, _T_126) node _T_147 = or(_T_146, _T_131) node _T_148 = or(_T_147, _T_136) node _T_149 = or(_T_148, _T_141) node _T_150 = and(_T_96, _T_149) node _T_151 = or(UInt<1>(0h0), _T_150) node _T_152 = and(UInt<1>(0h0), _T_151) node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_T_152, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_152, UInt<1>(0h1), "") : assert_3 node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(source_ok, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_159 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_159, UInt<1>(0h1), "") : assert_5 node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(is_aligned, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_166 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_166, UInt<1>(0h1), "") : assert_7 node _T_170 = not(io.in.a.bits.mask) node _T_171 = eq(_T_170, UInt<1>(0h0)) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_171, UInt<1>(0h1), "") : assert_8 node _T_175 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_175, UInt<1>(0h1), "") : assert_9 node _T_179 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_179 : node _T_180 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_181 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_184 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_185 = or(_T_183, _T_184) node _T_186 = and(_T_182, _T_185) node _T_187 = or(UInt<1>(0h0), _T_186) node _T_188 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_189 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<14>(0h2000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<13>(0h1000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h10000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<18>(0h2f000))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<17>(0h10000))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_215 = cvt(_T_214) node _T_216 = and(_T_215, asSInt(UInt<27>(0h4000000))) node _T_217 = asSInt(_T_216) node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0))) node _T_219 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_220 = cvt(_T_219) node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000))) node _T_222 = asSInt(_T_221) node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0))) node _T_224 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_225 = cvt(_T_224) node _T_226 = and(_T_225, asSInt(UInt<30>(0h20000000))) node _T_227 = asSInt(_T_226) node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_230 = cvt(_T_229) node _T_231 = and(_T_230, asSInt(UInt<15>(0h4000))) node _T_232 = asSInt(_T_231) node _T_233 = eq(_T_232, asSInt(UInt<1>(0h0))) node _T_234 = or(_T_193, _T_198) node _T_235 = or(_T_234, _T_203) node _T_236 = or(_T_235, _T_208) node _T_237 = or(_T_236, _T_213) node _T_238 = or(_T_237, _T_218) node _T_239 = or(_T_238, _T_223) node _T_240 = or(_T_239, _T_228) node _T_241 = or(_T_240, _T_233) node _T_242 = and(_T_188, _T_241) node _T_243 = or(UInt<1>(0h0), _T_242) node _T_244 = and(_T_187, _T_243) node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(_T_244, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_244, UInt<1>(0h1), "") : assert_10 node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<14>(0h2000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_258 = cvt(_T_257) node _T_259 = and(_T_258, asSInt(UInt<13>(0h1000))) node _T_260 = asSInt(_T_259) node _T_261 = eq(_T_260, asSInt(UInt<1>(0h0))) node _T_262 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_263 = cvt(_T_262) node _T_264 = and(_T_263, asSInt(UInt<17>(0h10000))) node _T_265 = asSInt(_T_264) node _T_266 = eq(_T_265, asSInt(UInt<1>(0h0))) node _T_267 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_268 = cvt(_T_267) node _T_269 = and(_T_268, asSInt(UInt<18>(0h2f000))) node _T_270 = asSInt(_T_269) node _T_271 = eq(_T_270, asSInt(UInt<1>(0h0))) node _T_272 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_273 = cvt(_T_272) node _T_274 = and(_T_273, asSInt(UInt<17>(0h10000))) node _T_275 = asSInt(_T_274) node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<27>(0h4000000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<13>(0h1000))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_288 = cvt(_T_287) node _T_289 = and(_T_288, asSInt(UInt<30>(0h20000000))) node _T_290 = asSInt(_T_289) node _T_291 = eq(_T_290, asSInt(UInt<1>(0h0))) node _T_292 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<15>(0h4000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = or(_T_256, _T_261) node _T_298 = or(_T_297, _T_266) node _T_299 = or(_T_298, _T_271) node _T_300 = or(_T_299, _T_276) node _T_301 = or(_T_300, _T_281) node _T_302 = or(_T_301, _T_286) node _T_303 = or(_T_302, _T_291) node _T_304 = or(_T_303, _T_296) node _T_305 = and(_T_251, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = and(UInt<1>(0h0), _T_306) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_307, UInt<1>(0h1), "") : assert_11 node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(source_ok, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_314 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(_T_314, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_314, UInt<1>(0h1), "") : assert_13 node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(is_aligned, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_321 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_322 = asUInt(reset) node _T_323 = eq(_T_322, UInt<1>(0h0)) when _T_323 : node _T_324 = eq(_T_321, UInt<1>(0h0)) when _T_324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_321, UInt<1>(0h1), "") : assert_15 node _T_325 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_325, UInt<1>(0h1), "") : assert_16 node _T_329 = not(io.in.a.bits.mask) node _T_330 = eq(_T_329, UInt<1>(0h0)) node _T_331 = asUInt(reset) node _T_332 = eq(_T_331, UInt<1>(0h0)) when _T_332 : node _T_333 = eq(_T_330, UInt<1>(0h0)) when _T_333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_330, UInt<1>(0h1), "") : assert_17 node _T_334 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_T_334, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_334, UInt<1>(0h1), "") : assert_18 node _T_338 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_338 : node _T_339 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_340 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_341 = and(_T_339, _T_340) node _T_342 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_343 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_344 = or(_T_342, _T_343) node _T_345 = and(_T_341, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_346, UInt<1>(0h1), "") : assert_19 node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_352 = and(_T_350, _T_351) node _T_353 = or(UInt<1>(0h0), _T_352) node _T_354 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<13>(0h1000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = and(_T_353, _T_358) node _T_360 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_361 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_362 = and(_T_360, _T_361) node _T_363 = or(UInt<1>(0h0), _T_362) node _T_364 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_365 = cvt(_T_364) node _T_366 = and(_T_365, asSInt(UInt<14>(0h2000))) node _T_367 = asSInt(_T_366) node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0))) node _T_369 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<17>(0h10000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_375 = cvt(_T_374) node _T_376 = and(_T_375, asSInt(UInt<18>(0h2f000))) node _T_377 = asSInt(_T_376) node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0))) node _T_379 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<17>(0h10000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<27>(0h4000000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<30>(0h20000000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<15>(0h4000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = or(_T_368, _T_373) node _T_405 = or(_T_404, _T_378) node _T_406 = or(_T_405, _T_383) node _T_407 = or(_T_406, _T_388) node _T_408 = or(_T_407, _T_393) node _T_409 = or(_T_408, _T_398) node _T_410 = or(_T_409, _T_403) node _T_411 = and(_T_363, _T_410) node _T_412 = or(UInt<1>(0h0), _T_359) node _T_413 = or(_T_412, _T_411) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_413, UInt<1>(0h1), "") : assert_20 node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(source_ok, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(is_aligned, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_423 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_424 = asUInt(reset) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(_T_423, UInt<1>(0h0)) when _T_426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_423, UInt<1>(0h1), "") : assert_23 node _T_427 = eq(io.in.a.bits.mask, mask) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_427, UInt<1>(0h1), "") : assert_24 node _T_431 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_431, UInt<1>(0h1), "") : assert_25 node _T_435 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_435 : node _T_436 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_437 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_440 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_441 = or(_T_439, _T_440) node _T_442 = and(_T_438, _T_441) node _T_443 = or(UInt<1>(0h0), _T_442) node _T_444 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_445 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_446 = and(_T_444, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<13>(0h1000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = and(_T_447, _T_452) node _T_454 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_455 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_456 = and(_T_454, _T_455) node _T_457 = or(UInt<1>(0h0), _T_456) node _T_458 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_459 = cvt(_T_458) node _T_460 = and(_T_459, asSInt(UInt<14>(0h2000))) node _T_461 = asSInt(_T_460) node _T_462 = eq(_T_461, asSInt(UInt<1>(0h0))) node _T_463 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_464 = cvt(_T_463) node _T_465 = and(_T_464, asSInt(UInt<18>(0h2f000))) node _T_466 = asSInt(_T_465) node _T_467 = eq(_T_466, asSInt(UInt<1>(0h0))) node _T_468 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_469 = cvt(_T_468) node _T_470 = and(_T_469, asSInt(UInt<17>(0h10000))) node _T_471 = asSInt(_T_470) node _T_472 = eq(_T_471, asSInt(UInt<1>(0h0))) node _T_473 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_474 = cvt(_T_473) node _T_475 = and(_T_474, asSInt(UInt<27>(0h4000000))) node _T_476 = asSInt(_T_475) node _T_477 = eq(_T_476, asSInt(UInt<1>(0h0))) node _T_478 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_479 = cvt(_T_478) node _T_480 = and(_T_479, asSInt(UInt<13>(0h1000))) node _T_481 = asSInt(_T_480) node _T_482 = eq(_T_481, asSInt(UInt<1>(0h0))) node _T_483 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_484 = cvt(_T_483) node _T_485 = and(_T_484, asSInt(UInt<15>(0h4000))) node _T_486 = asSInt(_T_485) node _T_487 = eq(_T_486, asSInt(UInt<1>(0h0))) node _T_488 = or(_T_462, _T_467) node _T_489 = or(_T_488, _T_472) node _T_490 = or(_T_489, _T_477) node _T_491 = or(_T_490, _T_482) node _T_492 = or(_T_491, _T_487) node _T_493 = and(_T_457, _T_492) node _T_494 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_495 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_496 = cvt(_T_495) node _T_497 = and(_T_496, asSInt(UInt<17>(0h10000))) node _T_498 = asSInt(_T_497) node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0))) node _T_500 = and(_T_494, _T_499) node _T_501 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_502 = leq(io.in.a.bits.size, UInt<4>(0h8)) node _T_503 = and(_T_501, _T_502) node _T_504 = or(UInt<1>(0h0), _T_503) node _T_505 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_506 = cvt(_T_505) node _T_507 = and(_T_506, asSInt(UInt<30>(0h20000000))) node _T_508 = asSInt(_T_507) node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0))) node _T_510 = and(_T_504, _T_509) node _T_511 = or(UInt<1>(0h0), _T_453) node _T_512 = or(_T_511, _T_493) node _T_513 = or(_T_512, _T_500) node _T_514 = or(_T_513, _T_510) node _T_515 = and(_T_443, _T_514) node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(_T_515, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_515, UInt<1>(0h1), "") : assert_26 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(source_ok, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(is_aligned, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_525 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_526 = asUInt(reset) node _T_527 = eq(_T_526, UInt<1>(0h0)) when _T_527 : node _T_528 = eq(_T_525, UInt<1>(0h0)) when _T_528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_525, UInt<1>(0h1), "") : assert_29 node _T_529 = eq(io.in.a.bits.mask, mask) node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(_T_529, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_529, UInt<1>(0h1), "") : assert_30 node _T_533 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_533 : node _T_534 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_535 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_536 = and(_T_534, _T_535) node _T_537 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_538 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_539 = or(_T_537, _T_538) node _T_540 = and(_T_536, _T_539) node _T_541 = or(UInt<1>(0h0), _T_540) node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = or(UInt<1>(0h0), _T_544) node _T_546 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_547 = cvt(_T_546) node _T_548 = and(_T_547, asSInt(UInt<13>(0h1000))) node _T_549 = asSInt(_T_548) node _T_550 = eq(_T_549, asSInt(UInt<1>(0h0))) node _T_551 = and(_T_545, _T_550) node _T_552 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_553 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_554 = and(_T_552, _T_553) node _T_555 = or(UInt<1>(0h0), _T_554) node _T_556 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_557 = cvt(_T_556) node _T_558 = and(_T_557, asSInt(UInt<14>(0h2000))) node _T_559 = asSInt(_T_558) node _T_560 = eq(_T_559, asSInt(UInt<1>(0h0))) node _T_561 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<18>(0h2f000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_567 = cvt(_T_566) node _T_568 = and(_T_567, asSInt(UInt<17>(0h10000))) node _T_569 = asSInt(_T_568) node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0))) node _T_571 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<27>(0h4000000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<13>(0h1000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<15>(0h4000))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = or(_T_560, _T_565) node _T_587 = or(_T_586, _T_570) node _T_588 = or(_T_587, _T_575) node _T_589 = or(_T_588, _T_580) node _T_590 = or(_T_589, _T_585) node _T_591 = and(_T_555, _T_590) node _T_592 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_593 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_594 = cvt(_T_593) node _T_595 = and(_T_594, asSInt(UInt<17>(0h10000))) node _T_596 = asSInt(_T_595) node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0))) node _T_598 = and(_T_592, _T_597) node _T_599 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_600 = leq(io.in.a.bits.size, UInt<4>(0h8)) node _T_601 = and(_T_599, _T_600) node _T_602 = or(UInt<1>(0h0), _T_601) node _T_603 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_604 = cvt(_T_603) node _T_605 = and(_T_604, asSInt(UInt<30>(0h20000000))) node _T_606 = asSInt(_T_605) node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0))) node _T_608 = and(_T_602, _T_607) node _T_609 = or(UInt<1>(0h0), _T_551) node _T_610 = or(_T_609, _T_591) node _T_611 = or(_T_610, _T_598) node _T_612 = or(_T_611, _T_608) node _T_613 = and(_T_541, _T_612) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_613, UInt<1>(0h1), "") : assert_31 node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(source_ok, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(is_aligned, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_623 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_623, UInt<1>(0h1), "") : assert_34 node _T_627 = not(mask) node _T_628 = and(io.in.a.bits.mask, _T_627) node _T_629 = eq(_T_628, UInt<1>(0h0)) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_629, UInt<1>(0h1), "") : assert_35 node _T_633 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_633 : node _T_634 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_635 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_636 = and(_T_634, _T_635) node _T_637 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_638 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_639 = or(_T_637, _T_638) node _T_640 = and(_T_636, _T_639) node _T_641 = or(UInt<1>(0h0), _T_640) node _T_642 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_643 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_644 = and(_T_642, _T_643) node _T_645 = or(UInt<1>(0h0), _T_644) node _T_646 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<14>(0h2000))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_652 = cvt(_T_651) node _T_653 = and(_T_652, asSInt(UInt<13>(0h1000))) node _T_654 = asSInt(_T_653) node _T_655 = eq(_T_654, asSInt(UInt<1>(0h0))) node _T_656 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_657 = cvt(_T_656) node _T_658 = and(_T_657, asSInt(UInt<18>(0h2f000))) node _T_659 = asSInt(_T_658) node _T_660 = eq(_T_659, asSInt(UInt<1>(0h0))) node _T_661 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_662 = cvt(_T_661) node _T_663 = and(_T_662, asSInt(UInt<17>(0h10000))) node _T_664 = asSInt(_T_663) node _T_665 = eq(_T_664, asSInt(UInt<1>(0h0))) node _T_666 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_667 = cvt(_T_666) node _T_668 = and(_T_667, asSInt(UInt<27>(0h4000000))) node _T_669 = asSInt(_T_668) node _T_670 = eq(_T_669, asSInt(UInt<1>(0h0))) node _T_671 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_672 = cvt(_T_671) node _T_673 = and(_T_672, asSInt(UInt<13>(0h1000))) node _T_674 = asSInt(_T_673) node _T_675 = eq(_T_674, asSInt(UInt<1>(0h0))) node _T_676 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_677 = cvt(_T_676) node _T_678 = and(_T_677, asSInt(UInt<15>(0h4000))) node _T_679 = asSInt(_T_678) node _T_680 = eq(_T_679, asSInt(UInt<1>(0h0))) node _T_681 = or(_T_650, _T_655) node _T_682 = or(_T_681, _T_660) node _T_683 = or(_T_682, _T_665) node _T_684 = or(_T_683, _T_670) node _T_685 = or(_T_684, _T_675) node _T_686 = or(_T_685, _T_680) node _T_687 = and(_T_645, _T_686) node _T_688 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_689 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_690 = cvt(_T_689) node _T_691 = and(_T_690, asSInt(UInt<17>(0h10000))) node _T_692 = asSInt(_T_691) node _T_693 = eq(_T_692, asSInt(UInt<1>(0h0))) node _T_694 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_695 = cvt(_T_694) node _T_696 = and(_T_695, asSInt(UInt<30>(0h20000000))) node _T_697 = asSInt(_T_696) node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0))) node _T_699 = or(_T_693, _T_698) node _T_700 = and(_T_688, _T_699) node _T_701 = or(UInt<1>(0h0), _T_687) node _T_702 = or(_T_701, _T_700) node _T_703 = and(_T_641, _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_703, UInt<1>(0h1), "") : assert_36 node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(source_ok, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(is_aligned, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_713 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_713, UInt<1>(0h1), "") : assert_39 node _T_717 = eq(io.in.a.bits.mask, mask) node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(_T_717, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_717, UInt<1>(0h1), "") : assert_40 node _T_721 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_721 : node _T_722 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_723 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_726 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_727 = or(_T_725, _T_726) node _T_728 = and(_T_724, _T_727) node _T_729 = or(UInt<1>(0h0), _T_728) node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_731 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_732 = and(_T_730, _T_731) node _T_733 = or(UInt<1>(0h0), _T_732) node _T_734 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_735 = cvt(_T_734) node _T_736 = and(_T_735, asSInt(UInt<14>(0h2000))) node _T_737 = asSInt(_T_736) node _T_738 = eq(_T_737, asSInt(UInt<1>(0h0))) node _T_739 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_740 = cvt(_T_739) node _T_741 = and(_T_740, asSInt(UInt<13>(0h1000))) node _T_742 = asSInt(_T_741) node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0))) node _T_744 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_745 = cvt(_T_744) node _T_746 = and(_T_745, asSInt(UInt<18>(0h2f000))) node _T_747 = asSInt(_T_746) node _T_748 = eq(_T_747, asSInt(UInt<1>(0h0))) node _T_749 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<17>(0h10000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<27>(0h4000000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<13>(0h1000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<15>(0h4000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = or(_T_738, _T_743) node _T_770 = or(_T_769, _T_748) node _T_771 = or(_T_770, _T_753) node _T_772 = or(_T_771, _T_758) node _T_773 = or(_T_772, _T_763) node _T_774 = or(_T_773, _T_768) node _T_775 = and(_T_733, _T_774) node _T_776 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_777 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_778 = cvt(_T_777) node _T_779 = and(_T_778, asSInt(UInt<17>(0h10000))) node _T_780 = asSInt(_T_779) node _T_781 = eq(_T_780, asSInt(UInt<1>(0h0))) node _T_782 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_783 = cvt(_T_782) node _T_784 = and(_T_783, asSInt(UInt<30>(0h20000000))) node _T_785 = asSInt(_T_784) node _T_786 = eq(_T_785, asSInt(UInt<1>(0h0))) node _T_787 = or(_T_781, _T_786) node _T_788 = and(_T_776, _T_787) node _T_789 = or(UInt<1>(0h0), _T_775) node _T_790 = or(_T_789, _T_788) node _T_791 = and(_T_729, _T_790) node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(_T_791, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_791, UInt<1>(0h1), "") : assert_41 node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(source_ok, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_798 = asUInt(reset) node _T_799 = eq(_T_798, UInt<1>(0h0)) when _T_799 : node _T_800 = eq(is_aligned, UInt<1>(0h0)) when _T_800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_801 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_801, UInt<1>(0h1), "") : assert_44 node _T_805 = eq(io.in.a.bits.mask, mask) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_805, UInt<1>(0h1), "") : assert_45 node _T_809 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_809 : node _T_810 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_811 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_812 = and(_T_810, _T_811) node _T_813 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_814 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_815 = or(_T_813, _T_814) node _T_816 = and(_T_812, _T_815) node _T_817 = or(UInt<1>(0h0), _T_816) node _T_818 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_819 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_820 = and(_T_818, _T_819) node _T_821 = or(UInt<1>(0h0), _T_820) node _T_822 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_823 = cvt(_T_822) node _T_824 = and(_T_823, asSInt(UInt<13>(0h1000))) node _T_825 = asSInt(_T_824) node _T_826 = eq(_T_825, asSInt(UInt<1>(0h0))) node _T_827 = and(_T_821, _T_826) node _T_828 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_829 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<14>(0h2000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<17>(0h10000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<18>(0h2f000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<30>(0h20000000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<15>(0h4000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = or(_T_833, _T_838) node _T_870 = or(_T_869, _T_843) node _T_871 = or(_T_870, _T_848) node _T_872 = or(_T_871, _T_853) node _T_873 = or(_T_872, _T_858) node _T_874 = or(_T_873, _T_863) node _T_875 = or(_T_874, _T_868) node _T_876 = and(_T_828, _T_875) node _T_877 = or(UInt<1>(0h0), _T_827) node _T_878 = or(_T_877, _T_876) node _T_879 = and(_T_817, _T_878) node _T_880 = asUInt(reset) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(_T_879, UInt<1>(0h0)) when _T_882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_879, UInt<1>(0h1), "") : assert_46 node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(source_ok, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(is_aligned, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_889 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_889, UInt<1>(0h1), "") : assert_49 node _T_893 = eq(io.in.a.bits.mask, mask) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_893, UInt<1>(0h1), "") : assert_50 node _T_897 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(_T_897, UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_897, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_901 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_901, UInt<1>(0h1), "") : assert_52 node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h1)) node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_2 connect _source_ok_WIRE_1[1], _source_ok_T_3 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_905 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_905 : node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(source_ok_1, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_909 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(_T_909, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_909, UInt<1>(0h1), "") : assert_54 node _T_913 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_913, UInt<1>(0h1), "") : assert_55 node _T_917 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_917, UInt<1>(0h1), "") : assert_56 node _T_921 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_921, UInt<1>(0h1), "") : assert_57 node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_925 : node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(source_ok_1, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(sink_ok, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_932 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_932, UInt<1>(0h1), "") : assert_60 node _T_936 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_936, UInt<1>(0h1), "") : assert_61 node _T_940 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_940, UInt<1>(0h1), "") : assert_62 node _T_944 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(_T_944, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_944, UInt<1>(0h1), "") : assert_63 node _T_948 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_949 = or(UInt<1>(0h1), _T_948) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_949, UInt<1>(0h1), "") : assert_64 node _T_953 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_953 : node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(source_ok_1, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(sink_ok, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_960 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_960, UInt<1>(0h1), "") : assert_67 node _T_964 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_964, UInt<1>(0h1), "") : assert_68 node _T_968 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_968, UInt<1>(0h1), "") : assert_69 node _T_972 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_973 = or(_T_972, io.in.d.bits.corrupt) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_973, UInt<1>(0h1), "") : assert_70 node _T_977 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_978 = or(UInt<1>(0h1), _T_977) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_978, UInt<1>(0h1), "") : assert_71 node _T_982 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_982 : node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(source_ok_1, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_986 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_986, UInt<1>(0h1), "") : assert_73 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_990, UInt<1>(0h1), "") : assert_74 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_995, UInt<1>(0h1), "") : assert_75 node _T_999 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(source_ok_1, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1003 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(_T_1003, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1003, UInt<1>(0h1), "") : assert_77 node _T_1007 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1008 = or(_T_1007, io.in.d.bits.corrupt) node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(_T_1008, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1008, UInt<1>(0h1), "") : assert_78 node _T_1012 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1013 = or(UInt<1>(0h1), _T_1012) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_79 node _T_1017 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1017 : node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(source_ok_1, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1021 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_81 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_82 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1034 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_T_1034, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1034, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1038 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1042 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1043 = asUInt(reset) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) when _T_1044 : node _T_1045 = eq(_T_1042, UInt<1>(0h0)) when _T_1045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1042, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1046 = eq(a_first, UInt<1>(0h0)) node _T_1047 = and(io.in.a.valid, _T_1046) when _T_1047 : node _T_1048 = eq(io.in.a.bits.opcode, opcode) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_87 node _T_1052 = eq(io.in.a.bits.param, param) node _T_1053 = asUInt(reset) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) when _T_1054 : node _T_1055 = eq(_T_1052, UInt<1>(0h0)) when _T_1055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1052, UInt<1>(0h1), "") : assert_88 node _T_1056 = eq(io.in.a.bits.size, size) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_89 node _T_1060 = eq(io.in.a.bits.source, source) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_90 node _T_1064 = eq(io.in.a.bits.address, address) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_91 node _T_1068 = and(io.in.a.ready, io.in.a.valid) node _T_1069 = and(_T_1068, a_first) when _T_1069 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1070 = eq(d_first, UInt<1>(0h0)) node _T_1071 = and(io.in.d.valid, _T_1070) when _T_1071 : node _T_1072 = eq(io.in.d.bits.opcode, opcode_1) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_92 node _T_1076 = eq(io.in.d.bits.param, param_1) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_93 node _T_1080 = eq(io.in.d.bits.size, size_1) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_94 node _T_1084 = eq(io.in.d.bits.source, source_1) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_95 node _T_1088 = eq(io.in.d.bits.sink, sink) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_96 node _T_1092 = eq(io.in.d.bits.denied, denied) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_97 node _T_1096 = and(io.in.d.ready, io.in.d.valid) node _T_1097 = and(_T_1096, d_first) when _T_1097 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2> connect a_set, UInt<2>(0h0) wire a_set_wo_ready : UInt<2> connect a_set_wo_ready, UInt<2>(0h0) wire a_opcodes_set : UInt<8> connect a_opcodes_set, UInt<8>(0h0) wire a_sizes_set : UInt<16> connect a_sizes_set, UInt<16>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1098 = and(io.in.a.valid, a_first_1) node _T_1099 = and(_T_1098, UInt<1>(0h1)) when _T_1099 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1100 = and(io.in.a.ready, io.in.a.valid) node _T_1101 = and(_T_1100, a_first_1) node _T_1102 = and(_T_1101, UInt<1>(0h1)) when _T_1102 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1103 = dshr(inflight, io.in.a.bits.source) node _T_1104 = bits(_T_1103, 0, 0) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2> connect d_clr, UInt<2>(0h0) wire d_clr_wo_ready : UInt<2> connect d_clr_wo_ready, UInt<2>(0h0) wire d_opcodes_clr : UInt<8> connect d_opcodes_clr, UInt<8>(0h0) wire d_sizes_clr : UInt<16> connect d_sizes_clr, UInt<16>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1109 = and(io.in.d.valid, d_first_1) node _T_1110 = and(_T_1109, UInt<1>(0h1)) node _T_1111 = eq(d_release_ack, UInt<1>(0h0)) node _T_1112 = and(_T_1110, _T_1111) when _T_1112 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1113 = and(io.in.d.ready, io.in.d.valid) node _T_1114 = and(_T_1113, d_first_1) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = eq(d_release_ack, UInt<1>(0h0)) node _T_1117 = and(_T_1115, _T_1116) when _T_1117 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1118 = and(io.in.d.valid, d_first_1) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = eq(d_release_ack, UInt<1>(0h0)) node _T_1121 = and(_T_1119, _T_1120) when _T_1121 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1122 = dshr(inflight, io.in.d.bits.source) node _T_1123 = bits(_T_1122, 0, 0) node _T_1124 = or(_T_1123, same_cycle_resp) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1128 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1129 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1130 = or(_T_1128, _T_1129) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_100 node _T_1134 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_101 else : node _T_1138 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1139 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1140 = or(_T_1138, _T_1139) node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(_T_1140, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1140, UInt<1>(0h1), "") : assert_102 node _T_1144 = eq(io.in.d.bits.size, a_size_lookup) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_103 node _T_1148 = and(io.in.d.valid, d_first_1) node _T_1149 = and(_T_1148, a_first_1) node _T_1150 = and(_T_1149, io.in.a.valid) node _T_1151 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1152 = and(_T_1150, _T_1151) node _T_1153 = eq(d_release_ack, UInt<1>(0h0)) node _T_1154 = and(_T_1152, _T_1153) when _T_1154 : node _T_1155 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1156 = or(_T_1155, io.in.a.ready) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_104 node _T_1160 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1161 = orr(a_set_wo_ready) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) node _T_1163 = or(_T_1160, _T_1162) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_2 node _T_1167 = orr(inflight) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) node _T_1169 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1170 = or(_T_1168, _T_1169) node _T_1171 = lt(watchdog, plusarg_reader.out) node _T_1172 = or(_T_1170, _T_1171) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1176 = and(io.in.a.ready, io.in.a.valid) node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = or(_T_1176, _T_1177) when _T_1178 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2> connect c_set, UInt<2>(0h0) wire c_set_wo_ready : UInt<2> connect c_set_wo_ready, UInt<2>(0h0) wire c_opcodes_set : UInt<8> connect c_opcodes_set, UInt<8>(0h0) wire c_sizes_set : UInt<16> connect c_sizes_set, UInt<16>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1179 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1180 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1181 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1182 = and(_T_1180, _T_1181) node _T_1183 = and(_T_1179, _T_1182) when _T_1183 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1184 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1185 = and(_T_1184, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1186 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1187 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = and(_T_1185, _T_1188) when _T_1189 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1190 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1191 = bits(_T_1190, 0, 0) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2> connect d_clr_1, UInt<2>(0h0) wire d_clr_wo_ready_1 : UInt<2> connect d_clr_wo_ready_1, UInt<2>(0h0) wire d_opcodes_clr_1 : UInt<8> connect d_opcodes_clr_1, UInt<8>(0h0) wire d_sizes_clr_1 : UInt<16> connect d_sizes_clr_1, UInt<16>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1196 = and(io.in.d.valid, d_first_2) node _T_1197 = and(_T_1196, UInt<1>(0h1)) node _T_1198 = and(_T_1197, d_release_ack_1) when _T_1198 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1199 = and(io.in.d.ready, io.in.d.valid) node _T_1200 = and(_T_1199, d_first_2) node _T_1201 = and(_T_1200, UInt<1>(0h1)) node _T_1202 = and(_T_1201, d_release_ack_1) when _T_1202 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1203 = and(io.in.d.valid, d_first_2) node _T_1204 = and(_T_1203, UInt<1>(0h1)) node _T_1205 = and(_T_1204, d_release_ack_1) when _T_1205 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1206 = dshr(inflight_1, io.in.d.bits.source) node _T_1207 = bits(_T_1206, 0, 0) node _T_1208 = or(_T_1207, same_cycle_resp_1) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1212 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_109 else : node _T_1216 = eq(io.in.d.bits.size, c_size_lookup) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_110 node _T_1220 = and(io.in.d.valid, d_first_2) node _T_1221 = and(_T_1220, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1222 = and(_T_1221, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1223 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1224, d_release_ack_1) node _T_1226 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1227 = and(_T_1225, _T_1226) when _T_1227 : node _T_1228 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1229 = or(_T_1228, _WIRE_23.ready) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_111 node _T_1233 = orr(c_set_wo_ready) when _T_1233 : node _T_1234 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1235 = asUInt(reset) node _T_1236 = eq(_T_1235, UInt<1>(0h0)) when _T_1236 : node _T_1237 = eq(_T_1234, UInt<1>(0h0)) when _T_1237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1234, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_3 node _T_1238 = orr(inflight_1) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) node _T_1240 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1241 = or(_T_1239, _T_1240) node _T_1242 = lt(watchdog_1, plusarg_reader_1.out) node _T_1243 = or(_T_1241, _T_1242) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1247 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1248 = and(io.in.d.ready, io.in.d.valid) node _T_1249 = or(_T_1247, _T_1248) when _T_1249 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_bufferable, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_modifiable, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_readalloc, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_writealloc, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_privileged, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_secure, // @[Monitor.scala:20:14] input io_in_a_bits_user_amba_prot_fetch, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_bufferable_0 = io_in_a_bits_user_amba_prot_bufferable; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_modifiable_0 = io_in_a_bits_user_amba_prot_modifiable; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_readalloc_0 = io_in_a_bits_user_amba_prot_readalloc; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_writealloc_0 = io_in_a_bits_user_amba_prot_writealloc; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_privileged_0 = io_in_a_bits_user_amba_prot_privileged; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_secure_0 = io_in_a_bits_user_amba_prot_secure; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_fetch_0 = io_in_a_bits_user_amba_prot_fetch; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [15:0] c_sizes_set = 16'h0; // @[Monitor.scala:741:34] wire [7:0] c_opcodes_set = 8'h0; // @[Monitor.scala:740:34] wire [1:0] c_set = 2'h0; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready = 2'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _T_1176 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1176; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1176; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1249 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1249; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1249; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1249; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_1102 = _T_1176 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1102 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1102 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1102 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1102 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1102 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1148 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1148 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_1117 = _T_1249 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1117 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1117 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1117 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1220 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1220 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_1202 = _T_1249 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1202 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1202 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1202 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_28 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_39 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_28( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_39 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_36 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_36 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_36( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_36 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<10>(0h200))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = and(_T_19, _T_24) node _T_26 = or(UInt<1>(0h0), _T_25) node _T_27 = and(_T_18, _T_26) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 node _T_31 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_32 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_33 = and(_T_31, _T_32) node _T_34 = or(UInt<1>(0h0), _T_33) node _T_35 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<10>(0h200))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = and(_T_34, _T_39) node _T_41 = or(UInt<1>(0h0), _T_40) node _T_42 = and(UInt<1>(0h0), _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_42, UInt<1>(0h1), "") : assert_3 node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_49 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_49, UInt<1>(0h1), "") : assert_5 node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(is_aligned, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_56 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_56, UInt<1>(0h1), "") : assert_7 node _T_60 = not(io.in.a.bits.mask) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_61, UInt<1>(0h1), "") : assert_8 node _T_65 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_69 : node _T_70 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_71 = and(UInt<1>(0h0), _T_70) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<10>(0h200))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = and(_T_73, _T_78) node _T_80 = or(UInt<1>(0h0), _T_79) node _T_81 = and(_T_72, _T_80) node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(_T_81, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_81, UInt<1>(0h1), "") : assert_10 node _T_85 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_86 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_87 = and(_T_85, _T_86) node _T_88 = or(UInt<1>(0h0), _T_87) node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<10>(0h200))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = and(_T_88, _T_93) node _T_95 = or(UInt<1>(0h0), _T_94) node _T_96 = and(UInt<1>(0h0), _T_95) node _T_97 = asUInt(reset) node _T_98 = eq(_T_97, UInt<1>(0h0)) when _T_98 : node _T_99 = eq(_T_96, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_96, UInt<1>(0h1), "") : assert_11 node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_103 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_103, UInt<1>(0h1), "") : assert_13 node _T_107 = asUInt(reset) node _T_108 = eq(_T_107, UInt<1>(0h0)) when _T_108 : node _T_109 = eq(is_aligned, UInt<1>(0h0)) when _T_109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_110 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_110, UInt<1>(0h1), "") : assert_15 node _T_114 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_114, UInt<1>(0h1), "") : assert_16 node _T_118 = not(io.in.a.bits.mask) node _T_119 = eq(_T_118, UInt<1>(0h0)) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_119, UInt<1>(0h1), "") : assert_17 node _T_123 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_T_123, UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_123, UInt<1>(0h1), "") : assert_18 node _T_127 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_127 : node _T_128 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_129 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_130 = and(_T_128, _T_129) node _T_131 = or(UInt<1>(0h0), _T_130) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_131, UInt<1>(0h1), "") : assert_19 node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_136 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_137 = and(_T_135, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<10>(0h200))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = and(_T_138, _T_143) node _T_145 = or(UInt<1>(0h0), _T_144) node _T_146 = asUInt(reset) node _T_147 = eq(_T_146, UInt<1>(0h0)) when _T_147 : node _T_148 = eq(_T_145, UInt<1>(0h0)) when _T_148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_145, UInt<1>(0h1), "") : assert_20 node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(is_aligned, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_155 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_155, UInt<1>(0h1), "") : assert_23 node _T_159 = eq(io.in.a.bits.mask, mask) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_159, UInt<1>(0h1), "") : assert_24 node _T_163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_163, UInt<1>(0h1), "") : assert_25 node _T_167 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_169 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_170 = and(_T_168, _T_169) node _T_171 = or(UInt<1>(0h0), _T_170) node _T_172 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_173 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_174 = and(_T_172, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<10>(0h200))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = and(_T_175, _T_180) node _T_182 = or(UInt<1>(0h0), _T_181) node _T_183 = and(_T_171, _T_182) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_183, UInt<1>(0h1), "") : assert_26 node _T_187 = asUInt(reset) node _T_188 = eq(_T_187, UInt<1>(0h0)) when _T_188 : node _T_189 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(is_aligned, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_193 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_193, UInt<1>(0h1), "") : assert_29 node _T_197 = eq(io.in.a.bits.mask, mask) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_197, UInt<1>(0h1), "") : assert_30 node _T_201 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_201 : node _T_202 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_203 = and(UInt<1>(0h0), _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_206 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_207 = and(_T_205, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<10>(0h200))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = and(_T_208, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(_T_204, _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_216, UInt<1>(0h1), "") : assert_31 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(is_aligned, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_226 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(_T_226, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_226, UInt<1>(0h1), "") : assert_34 node _T_230 = not(mask) node _T_231 = and(io.in.a.bits.mask, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_232, UInt<1>(0h1), "") : assert_35 node _T_236 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_236 : node _T_237 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_238 = and(UInt<1>(0h0), _T_237) node _T_239 = or(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<10>(0h200))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = and(_T_240, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = and(_T_239, _T_247) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_248, UInt<1>(0h1), "") : assert_36 node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(is_aligned, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_258 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_258, UInt<1>(0h1), "") : assert_39 node _T_262 = eq(io.in.a.bits.mask, mask) node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_T_262, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_262, UInt<1>(0h1), "") : assert_40 node _T_266 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_266 : node _T_267 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_268 = and(UInt<1>(0h0), _T_267) node _T_269 = or(UInt<1>(0h0), _T_268) node _T_270 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_271 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<10>(0h200))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = and(_T_270, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = and(_T_269, _T_277) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_278, UInt<1>(0h1), "") : assert_41 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : node _T_284 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(is_aligned, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_288 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_288, UInt<1>(0h1), "") : assert_44 node _T_292 = eq(io.in.a.bits.mask, mask) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_292, UInt<1>(0h1), "") : assert_45 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_296 : node _T_297 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_298 = and(UInt<1>(0h0), _T_297) node _T_299 = or(UInt<1>(0h0), _T_298) node _T_300 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<10>(0h200))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = and(_T_300, _T_305) node _T_307 = or(UInt<1>(0h0), _T_306) node _T_308 = and(_T_299, _T_307) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_308, UInt<1>(0h1), "") : assert_46 node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(is_aligned, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_318 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_318, UInt<1>(0h1), "") : assert_49 node _T_322 = eq(io.in.a.bits.mask, mask) node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(_T_322, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_322, UInt<1>(0h1), "") : assert_50 node _T_326 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_327 = asUInt(reset) node _T_328 = eq(_T_327, UInt<1>(0h0)) when _T_328 : node _T_329 = eq(_T_326, UInt<1>(0h0)) when _T_329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_326, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_330 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_331 = asUInt(reset) node _T_332 = eq(_T_331, UInt<1>(0h0)) when _T_332 : node _T_333 = eq(_T_330, UInt<1>(0h0)) when _T_333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_330, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_334 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_334 : node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_338 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_338, UInt<1>(0h1), "") : assert_54 node _T_342 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_342, UInt<1>(0h1), "") : assert_55 node _T_346 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_346, UInt<1>(0h1), "") : assert_56 node _T_350 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(_T_350, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_350, UInt<1>(0h1), "") : assert_57 node _T_354 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_354 : node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(sink_ok, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_361 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_361, UInt<1>(0h1), "") : assert_60 node _T_365 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_365, UInt<1>(0h1), "") : assert_61 node _T_369 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_369, UInt<1>(0h1), "") : assert_62 node _T_373 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_373, UInt<1>(0h1), "") : assert_63 node _T_377 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_378 = or(UInt<1>(0h1), _T_377) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_378, UInt<1>(0h1), "") : assert_64 node _T_382 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_382 : node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(sink_ok, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_389 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_389, UInt<1>(0h1), "") : assert_67 node _T_393 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_393, UInt<1>(0h1), "") : assert_68 node _T_397 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_397, UInt<1>(0h1), "") : assert_69 node _T_401 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_402 = or(_T_401, io.in.d.bits.corrupt) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_402, UInt<1>(0h1), "") : assert_70 node _T_406 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_407 = or(UInt<1>(0h1), _T_406) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_407, UInt<1>(0h1), "") : assert_71 node _T_411 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_411 : node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_415 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_415, UInt<1>(0h1), "") : assert_73 node _T_419 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_419, UInt<1>(0h1), "") : assert_74 node _T_423 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_424 = or(UInt<1>(0h1), _T_423) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_424, UInt<1>(0h1), "") : assert_75 node _T_428 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_428 : node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_432 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_432, UInt<1>(0h1), "") : assert_77 node _T_436 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_437 = or(_T_436, io.in.d.bits.corrupt) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_437, UInt<1>(0h1), "") : assert_78 node _T_441 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_442 = or(UInt<1>(0h1), _T_441) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_442, UInt<1>(0h1), "") : assert_79 node _T_446 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_450 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_450, UInt<1>(0h1), "") : assert_81 node _T_454 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_454, UInt<1>(0h1), "") : assert_82 node _T_458 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_459 = or(UInt<1>(0h1), _T_458) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_459, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_463 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_463, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_467 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_467, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_471 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_471, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_475 = eq(a_first, UInt<1>(0h0)) node _T_476 = and(io.in.a.valid, _T_475) when _T_476 : node _T_477 = eq(io.in.a.bits.opcode, opcode) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_477, UInt<1>(0h1), "") : assert_87 node _T_481 = eq(io.in.a.bits.param, param) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_481, UInt<1>(0h1), "") : assert_88 node _T_485 = eq(io.in.a.bits.size, size) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_485, UInt<1>(0h1), "") : assert_89 node _T_489 = eq(io.in.a.bits.source, source) node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_T_489, UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_489, UInt<1>(0h1), "") : assert_90 node _T_493 = eq(io.in.a.bits.address, address) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_493, UInt<1>(0h1), "") : assert_91 node _T_497 = and(io.in.a.ready, io.in.a.valid) node _T_498 = and(_T_497, a_first) when _T_498 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_499 = eq(d_first, UInt<1>(0h0)) node _T_500 = and(io.in.d.valid, _T_499) when _T_500 : node _T_501 = eq(io.in.d.bits.opcode, opcode_1) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_501, UInt<1>(0h1), "") : assert_92 node _T_505 = eq(io.in.d.bits.param, param_1) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_505, UInt<1>(0h1), "") : assert_93 node _T_509 = eq(io.in.d.bits.size, size_1) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_509, UInt<1>(0h1), "") : assert_94 node _T_513 = eq(io.in.d.bits.source, source_1) node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_T_513, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_513, UInt<1>(0h1), "") : assert_95 node _T_517 = eq(io.in.d.bits.sink, sink) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_517, UInt<1>(0h1), "") : assert_96 node _T_521 = eq(io.in.d.bits.denied, denied) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_521, UInt<1>(0h1), "") : assert_97 node _T_525 = and(io.in.d.ready, io.in.d.valid) node _T_526 = and(_T_525, d_first) when _T_526 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_527 = and(io.in.a.valid, a_first_1) node _T_528 = and(_T_527, UInt<1>(0h1)) when _T_528 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_529 = and(io.in.a.ready, io.in.a.valid) node _T_530 = and(_T_529, a_first_1) node _T_531 = and(_T_530, UInt<1>(0h1)) when _T_531 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_532 = dshr(inflight, io.in.a.bits.source) node _T_533 = bits(_T_532, 0, 0) node _T_534 = eq(_T_533, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_534, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_538 = and(io.in.d.valid, d_first_1) node _T_539 = and(_T_538, UInt<1>(0h1)) node _T_540 = eq(d_release_ack, UInt<1>(0h0)) node _T_541 = and(_T_539, _T_540) when _T_541 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_542 = and(io.in.d.ready, io.in.d.valid) node _T_543 = and(_T_542, d_first_1) node _T_544 = and(_T_543, UInt<1>(0h1)) node _T_545 = eq(d_release_ack, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) when _T_546 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_551 = dshr(inflight, io.in.d.bits.source) node _T_552 = bits(_T_551, 0, 0) node _T_553 = or(_T_552, same_cycle_resp) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_553, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_557 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_558 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_559 = or(_T_557, _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_559, UInt<1>(0h1), "") : assert_100 node _T_563 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_563, UInt<1>(0h1), "") : assert_101 else : node _T_567 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_568 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_569 = or(_T_567, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_569, UInt<1>(0h1), "") : assert_102 node _T_573 = eq(io.in.d.bits.size, a_size_lookup) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_573, UInt<1>(0h1), "") : assert_103 node _T_577 = and(io.in.d.valid, d_first_1) node _T_578 = and(_T_577, a_first_1) node _T_579 = and(_T_578, io.in.a.valid) node _T_580 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_581 = and(_T_579, _T_580) node _T_582 = eq(d_release_ack, UInt<1>(0h0)) node _T_583 = and(_T_581, _T_582) when _T_583 : node _T_584 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_585 = or(_T_584, io.in.a.ready) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_585, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_96 node _T_589 = orr(inflight) node _T_590 = eq(_T_589, UInt<1>(0h0)) node _T_591 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_592 = or(_T_590, _T_591) node _T_593 = lt(watchdog, plusarg_reader.out) node _T_594 = or(_T_592, _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_594, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_598 = and(io.in.a.ready, io.in.a.valid) node _T_599 = and(io.in.d.ready, io.in.d.valid) node _T_600 = or(_T_598, _T_599) when _T_600 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_601 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_602 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_603 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_604 = and(_T_602, _T_603) node _T_605 = and(_T_601, _T_604) when _T_605 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_606 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_607 = and(_T_606, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_608 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_609 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_610 = and(_T_608, _T_609) node _T_611 = and(_T_607, _T_610) when _T_611 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_612 = dshr(inflight_1, _WIRE_15.bits.source) node _T_613 = bits(_T_612, 0, 0) node _T_614 = eq(_T_613, UInt<1>(0h0)) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_614, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_618 = and(io.in.d.valid, d_first_2) node _T_619 = and(_T_618, UInt<1>(0h1)) node _T_620 = and(_T_619, d_release_ack_1) when _T_620 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_621 = and(io.in.d.ready, io.in.d.valid) node _T_622 = and(_T_621, d_first_2) node _T_623 = and(_T_622, UInt<1>(0h1)) node _T_624 = and(_T_623, d_release_ack_1) when _T_624 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_625 = and(io.in.d.valid, d_first_2) node _T_626 = and(_T_625, UInt<1>(0h1)) node _T_627 = and(_T_626, d_release_ack_1) when _T_627 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_628 = dshr(inflight_1, io.in.d.bits.source) node _T_629 = bits(_T_628, 0, 0) node _T_630 = or(_T_629, same_cycle_resp_1) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_630, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_634 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_634, UInt<1>(0h1), "") : assert_108 else : node _T_638 = eq(io.in.d.bits.size, c_size_lookup) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_638, UInt<1>(0h1), "") : assert_109 node _T_642 = and(io.in.d.valid, d_first_2) node _T_643 = and(_T_642, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_644 = and(_T_643, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_645 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_646 = and(_T_644, _T_645) node _T_647 = and(_T_646, d_release_ack_1) node _T_648 = eq(c_probe_ack, UInt<1>(0h0)) node _T_649 = and(_T_647, _T_648) when _T_649 : node _T_650 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_651 = or(_T_650, _WIRE_23.ready) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_651, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_97 node _T_655 = orr(inflight_1) node _T_656 = eq(_T_655, UInt<1>(0h0)) node _T_657 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_658 = or(_T_656, _T_657) node _T_659 = lt(watchdog_1, plusarg_reader_1.out) node _T_660 = or(_T_658, _T_659) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_660, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_664 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_665 = and(io.in.d.ready, io.in.d.valid) node _T_666 = or(_T_664, _T_665) when _T_666 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_48( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_598 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_598; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_598; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_666 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_666; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_666; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_666; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_528 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_528; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_528; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_598 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_577 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_577 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_666 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_642 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_642 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_666 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_88 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_105 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_88( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_105 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLUART : input clock : Clock input reset : Reset output auto : { int_xing_out : { sync : UInt<1>[1]}, flip control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, io_out : { txd : UInt<1>, flip rxd : UInt<1>}} inst buffer of TLBuffer_a29d64s14k1z2u connect buffer.clock, clock connect buffer.reset, reset inst intsource of IntSyncCrossingSource_n1x1_5 connect intsource.clock, clock connect intsource.reset, reset wire ioNodeOut : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeOut.rxd invalidate ioNodeOut.txd wire intnodeOut : UInt<1>[1] invalidate intnodeOut[0] wire controlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlNodeIn.d.bits.corrupt invalidate controlNodeIn.d.bits.data invalidate controlNodeIn.d.bits.denied invalidate controlNodeIn.d.bits.sink invalidate controlNodeIn.d.bits.source invalidate controlNodeIn.d.bits.size invalidate controlNodeIn.d.bits.param invalidate controlNodeIn.d.bits.opcode invalidate controlNodeIn.d.valid invalidate controlNodeIn.d.ready invalidate controlNodeIn.a.bits.corrupt invalidate controlNodeIn.a.bits.data invalidate controlNodeIn.a.bits.mask invalidate controlNodeIn.a.bits.address invalidate controlNodeIn.a.bits.source invalidate controlNodeIn.a.bits.size invalidate controlNodeIn.a.bits.param invalidate controlNodeIn.a.bits.opcode invalidate controlNodeIn.a.valid invalidate controlNodeIn.a.ready inst monitor of TLMonitor_63 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, controlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, controlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, controlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, controlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, controlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, controlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, controlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, controlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, controlNodeIn.d.valid connect monitor.io.in.d.ready, controlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, controlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, controlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, controlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, controlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, controlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, controlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, controlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, controlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, controlNodeIn.a.valid connect monitor.io.in.a.ready, controlNodeIn.a.ready wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingOut.d.bits.corrupt invalidate controlXingOut.d.bits.data invalidate controlXingOut.d.bits.denied invalidate controlXingOut.d.bits.sink invalidate controlXingOut.d.bits.source invalidate controlXingOut.d.bits.size invalidate controlXingOut.d.bits.param invalidate controlXingOut.d.bits.opcode invalidate controlXingOut.d.valid invalidate controlXingOut.d.ready invalidate controlXingOut.a.bits.corrupt invalidate controlXingOut.a.bits.data invalidate controlXingOut.a.bits.mask invalidate controlXingOut.a.bits.address invalidate controlXingOut.a.bits.source invalidate controlXingOut.a.bits.size invalidate controlXingOut.a.bits.param invalidate controlXingOut.a.bits.opcode invalidate controlXingOut.a.valid invalidate controlXingOut.a.ready wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingIn.d.bits.corrupt invalidate controlXingIn.d.bits.data invalidate controlXingIn.d.bits.denied invalidate controlXingIn.d.bits.sink invalidate controlXingIn.d.bits.source invalidate controlXingIn.d.bits.size invalidate controlXingIn.d.bits.param invalidate controlXingIn.d.bits.opcode invalidate controlXingIn.d.valid invalidate controlXingIn.d.ready invalidate controlXingIn.a.bits.corrupt invalidate controlXingIn.a.bits.data invalidate controlXingIn.a.bits.mask invalidate controlXingIn.a.bits.address invalidate controlXingIn.a.bits.source invalidate controlXingIn.a.bits.size invalidate controlXingIn.a.bits.param invalidate controlXingIn.a.bits.opcode invalidate controlXingIn.a.valid invalidate controlXingIn.a.ready connect controlXingOut, controlXingIn wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn connect intsource.auto.in[0], intnodeOut[0] connect buffer.auto.out.d, controlNodeIn.d connect controlNodeIn.a.bits, buffer.auto.out.a.bits connect controlNodeIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, controlNodeIn.a.ready connect buffer.auto.in, controlXingOut connect intXingIn, intsource.auto.out connect auto.io_out, ioNodeOut connect controlXingIn, auto.control_xing_in connect auto.int_xing_out, intXingOut inst txm of UARTTx connect txm.clock, clock connect txm.reset, reset inst txq of Queue8_UInt8 connect txq.clock, clock connect txq.reset, reset inst rxm of UARTRx connect rxm.clock, clock connect rxm.reset, reset inst rxq of Queue8_UInt8_1 connect rxq.clock, clock connect rxq.reset, reset regreset div : UInt<16>, clock, reset, UInt<16>(0h10f4) regreset txen : UInt<1>, clock, reset, UInt<1>(0h0) regreset rxen : UInt<1>, clock, reset, UInt<1>(0h0) regreset enwire4 : UInt<1>, clock, reset, UInt<1>(0h0) regreset invpol : UInt<1>, clock, reset, UInt<1>(0h0) regreset enparity : UInt<1>, clock, reset, UInt<1>(0h0) regreset parity : UInt<1>, clock, reset, UInt<1>(0h0) regreset errorparity : UInt<1>, clock, reset, UInt<1>(0h0) regreset errie : UInt<1>, clock, reset, UInt<1>(0h0) regreset txwm : UInt<4>, clock, reset, UInt<4>(0h0) regreset rxwm : UInt<4>, clock, reset, UInt<4>(0h0) regreset nstop : UInt<1>, clock, reset, UInt<1>(0h0) regreset data8or9 : UInt<1>, clock, reset, UInt<1>(0h1) connect txm.io.en, txen connect txm.io.in, txq.io.deq connect txm.io.div, div connect txm.io.nstop, nstop connect ioNodeOut.txd, txm.io.out connect rxm.io.en, rxen connect rxm.io.in, ioNodeOut.rxd connect rxq.io.enq.valid, rxm.io.out.valid connect rxq.io.enq.bits, rxm.io.out.bits connect rxm.io.div, div node _tx_busy_T = orr(txq.io.count) node _tx_busy_T_1 = or(txm.io.tx_busy, _tx_busy_T) node tx_busy = and(_tx_busy_T_1, txen) wire _ie_WIRE : { rxwm : UInt<1>, txwm : UInt<1>} connect _ie_WIRE.txwm, UInt<1>(0h0) connect _ie_WIRE.rxwm, UInt<1>(0h0) regreset ie : { rxwm : UInt<1>, txwm : UInt<1>}, clock, reset, _ie_WIRE wire ip : { rxwm : UInt<1>, txwm : UInt<1>} node _ip_txwm_T = lt(txq.io.count, txwm) connect ip.txwm, _ip_txwm_T node _ip_rxwm_T = gt(rxq.io.count, rxwm) connect ip.rxwm, _ip_rxwm_T node _intnodeOut_0_T = and(ip.txwm, ie.txwm) node _intnodeOut_0_T_1 = and(ip.rxwm, ie.rxwm) node _intnodeOut_0_T_2 = or(_intnodeOut_0_T, _intnodeOut_0_T_1) connect intnodeOut[0], _intnodeOut_0_T_2 wire quash : UInt<1> node _T = eq(txq.io.enq.ready, UInt<1>(0h0)) node _T_1 = eq(rxq.io.deq.valid, UInt<1>(0h0)) wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} node _in_bits_read_T = eq(controlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(controlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, controlNodeIn.a.bits.data connect in.bits.mask, controlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, controlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, controlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h3)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) node _out_T_6 = eq(out_findex, UInt<9>(0h0)) node _out_T_7 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[16] wire out_wivalid : UInt<1>[16] wire out_roready : UInt<1>[16] wire out_woready : UInt<1>[16] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_8 = bits(out_front.bits.data, 7, 0) node _out_txq_io_enq_valid_T = eq(quash, UInt<1>(0h0)) node _out_txq_io_enq_valid_T_1 = and(out_f_woready, _out_txq_io_enq_valid_T) connect txq.io.enq.valid, _out_txq_io_enq_valid_T_1 connect txq.io.enq.bits, _out_T_8 node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) node _out_T_10 = and(UInt<1>(0h1), out_f_woready) node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) node _out_T_13 = eq(out_romask, UInt<1>(0h0)) node _out_T_14 = eq(out_womask, UInt<1>(0h0)) node _out_T_15 = or(UInt<1>(0h0), UInt<8>(0h0)) node _out_T_16 = bits(_out_T_15, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 30, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 30, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 30, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 30, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_17 = bits(out_front.bits.data, 30, 8) node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_22 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_23 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_16, UInt<8>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_24 = or(out_prepend, UInt<31>(0h0)) node _out_T_25 = bits(_out_T_24, 30, 0) node _out_rimask_T_2 = bits(out_frontMask, 31, 31) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 31, 31) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 31, 31) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 31, 31) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_26 = bits(out_front.bits.data, 31, 31) node _out_quash_T = bits(_out_T_26, 0, 0) node _out_quash_T_1 = and(out_f_woready_2, _out_quash_T) connect quash, _out_quash_T_1 node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_29 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_30 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_31 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_32 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_25, UInt<31>(0h0)) node out_prepend_1 = cat(_T, _out_prepend_T_1) node _out_T_33 = or(out_prepend_1, UInt<32>(0h0)) node _out_T_34 = bits(_out_T_33, 31, 0) node _out_rimask_T_3 = bits(out_frontMask, 39, 32) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 39, 32) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 39, 32) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 39, 32) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) connect rxq.io.deq.ready, out_f_roready_3 node _out_T_35 = bits(out_front.bits.data, 39, 32) node _out_T_36 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_37 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_38 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_34, UInt<32>(0h0)) node out_prepend_2 = cat(rxq.io.deq.bits, _out_prepend_T_2) node _out_T_42 = or(out_prepend_2, UInt<40>(0h0)) node _out_T_43 = bits(_out_T_42, 39, 0) node _out_rimask_T_4 = bits(out_frontMask, 62, 40) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 62, 40) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 62, 40) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 62, 40) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_44 = bits(out_front.bits.data, 62, 40) node _out_T_45 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_46 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_49 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_50 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_43, UInt<40>(0h0)) node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3) node _out_T_51 = or(out_prepend_3, UInt<63>(0h0)) node _out_T_52 = bits(_out_T_51, 62, 0) node _out_rimask_T_5 = bits(out_frontMask, 63, 63) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 63, 63) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 63, 63) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 63, 63) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_53 = bits(out_front.bits.data, 63, 63) node _out_T_54 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_55 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_56 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_57 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_58 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_59 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_52, UInt<63>(0h0)) node out_prepend_4 = cat(_T_1, _out_prepend_T_4) node _out_T_60 = or(out_prepend_4, UInt<64>(0h0)) node _out_T_61 = bits(_out_T_60, 63, 0) node _out_rimask_T_6 = bits(out_frontMask, 0, 0) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 0, 0) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 0, 0) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 0, 0) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_62 = bits(out_front.bits.data, 0, 0) when out_f_woready_6 : connect txen, _out_T_62 node _out_T_63 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_64 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_65 = and(out_f_wivalid_6, UInt<1>(0h1)) node _out_T_66 = and(UInt<1>(0h1), out_f_woready_6) node _out_T_67 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_68 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_69 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_70 = eq(out_womask_6, UInt<1>(0h0)) node _out_T_71 = or(txen, UInt<1>(0h0)) node _out_T_72 = bits(_out_T_71, 0, 0) node _out_rimask_T_7 = bits(out_frontMask, 1, 1) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 1, 1) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 1, 1) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 1, 1) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_73 = bits(out_front.bits.data, 1, 1) when out_f_woready_7 : connect nstop, _out_T_73 node _out_T_74 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_75 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_76 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_77 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_78 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_79 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_80 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_81 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_72, UInt<1>(0h0)) node out_prepend_5 = cat(nstop, _out_prepend_T_5) node _out_T_82 = or(out_prepend_5, UInt<2>(0h0)) node _out_T_83 = bits(_out_T_82, 1, 0) node _out_rimask_T_8 = bits(out_frontMask, 19, 16) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 19, 16) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 19, 16) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 19, 16) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_84 = bits(out_front.bits.data, 19, 16) when out_f_woready_8 : connect txwm, _out_T_84 node _out_T_85 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_86 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_87 = and(out_f_wivalid_8, UInt<1>(0h1)) node _out_T_88 = and(UInt<1>(0h1), out_f_woready_8) node _out_T_89 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_90 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_91 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_92 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_83, UInt<16>(0h0)) node out_prepend_6 = cat(txwm, _out_prepend_T_6) node _out_T_93 = or(out_prepend_6, UInt<20>(0h0)) node _out_T_94 = bits(_out_T_93, 19, 0) node _out_rimask_T_9 = bits(out_frontMask, 32, 32) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 32, 32) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 32, 32) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 32, 32) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_95 = bits(out_front.bits.data, 32, 32) when out_f_woready_9 : connect rxen, _out_T_95 node _out_T_96 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_97 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_98 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_99 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_100 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_101 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_102 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_103 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_94, UInt<32>(0h0)) node out_prepend_7 = cat(rxen, _out_prepend_T_7) node _out_T_104 = or(out_prepend_7, UInt<33>(0h0)) node _out_T_105 = bits(_out_T_104, 32, 0) node _out_rimask_T_10 = bits(out_frontMask, 51, 48) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 51, 48) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 51, 48) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 51, 48) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_106 = bits(out_front.bits.data, 51, 48) when out_f_woready_10 : connect rxwm, _out_T_106 node _out_T_107 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_108 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_109 = and(out_f_wivalid_10, UInt<1>(0h1)) node _out_T_110 = and(UInt<1>(0h1), out_f_woready_10) node _out_T_111 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_112 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_113 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_114 = eq(out_womask_10, UInt<1>(0h0)) node _out_prepend_T_8 = or(_out_T_105, UInt<48>(0h0)) node out_prepend_8 = cat(rxwm, _out_prepend_T_8) node _out_T_115 = or(out_prepend_8, UInt<52>(0h0)) node _out_T_116 = bits(_out_T_115, 51, 0) node _out_rimask_T_11 = bits(out_frontMask, 0, 0) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 0, 0) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 0, 0) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 0, 0) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_117 = bits(out_front.bits.data, 0, 0) when out_f_woready_11 : connect ie.txwm, _out_T_117 node _out_T_118 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_119 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_120 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_121 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_122 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_123 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_124 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_125 = eq(out_womask_11, UInt<1>(0h0)) node _out_T_126 = or(ie.txwm, UInt<1>(0h0)) node _out_T_127 = bits(_out_T_126, 0, 0) node _out_rimask_T_12 = bits(out_frontMask, 1, 1) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 1, 1) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 1, 1) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 1, 1) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_128 = bits(out_front.bits.data, 1, 1) when out_f_woready_12 : connect ie.rxwm, _out_T_128 node _out_T_129 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_130 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_131 = and(out_f_wivalid_12, UInt<1>(0h1)) node _out_T_132 = and(UInt<1>(0h1), out_f_woready_12) node _out_T_133 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_134 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_135 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_136 = eq(out_womask_12, UInt<1>(0h0)) node _out_prepend_T_9 = or(_out_T_127, UInt<1>(0h0)) node out_prepend_9 = cat(ie.rxwm, _out_prepend_T_9) node _out_T_137 = or(out_prepend_9, UInt<2>(0h0)) node _out_T_138 = bits(_out_T_137, 1, 0) node _out_rimask_T_13 = bits(out_frontMask, 32, 32) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 32, 32) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 32, 32) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 32, 32) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) node _out_T_139 = bits(out_front.bits.data, 32, 32) node _out_T_140 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_141 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_142 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_143 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_144 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_145 = eq(out_womask_13, UInt<1>(0h0)) node _out_prepend_T_10 = or(_out_T_138, UInt<32>(0h0)) node out_prepend_10 = cat(ip.txwm, _out_prepend_T_10) node _out_T_146 = or(out_prepend_10, UInt<33>(0h0)) node _out_T_147 = bits(_out_T_146, 32, 0) node _out_rimask_T_14 = bits(out_frontMask, 33, 33) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 33, 33) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 33, 33) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 33, 33) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_148 = bits(out_front.bits.data, 33, 33) node _out_T_149 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_150 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_151 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_152 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_153 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_154 = eq(out_womask_14, UInt<1>(0h0)) node _out_prepend_T_11 = or(_out_T_147, UInt<33>(0h0)) node out_prepend_11 = cat(ip.rxwm, _out_prepend_T_11) node _out_T_155 = or(out_prepend_11, UInt<34>(0h0)) node _out_T_156 = bits(_out_T_155, 33, 0) node _out_rimask_T_15 = bits(out_frontMask, 15, 0) node out_rimask_15 = orr(_out_rimask_T_15) node _out_wimask_T_15 = bits(out_frontMask, 15, 0) node out_wimask_15 = andr(_out_wimask_T_15) node _out_romask_T_15 = bits(out_backMask, 15, 0) node out_romask_15 = orr(_out_romask_T_15) node _out_womask_T_15 = bits(out_backMask, 15, 0) node out_womask_15 = andr(_out_womask_T_15) node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) node out_f_roready_15 = and(out_roready[15], out_romask_15) node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) node out_f_woready_15 = and(out_woready[15], out_womask_15) node _out_T_157 = bits(out_front.bits.data, 15, 0) when out_f_woready_15 : connect div, _out_T_157 node _out_T_158 = and(out_f_rivalid_15, UInt<1>(0h1)) node _out_T_159 = and(UInt<1>(0h1), out_f_roready_15) node _out_T_160 = and(out_f_wivalid_15, UInt<1>(0h1)) node _out_T_161 = and(UInt<1>(0h1), out_f_woready_15) node _out_T_162 = eq(out_rimask_15, UInt<1>(0h0)) node _out_T_163 = eq(out_wimask_15, UInt<1>(0h0)) node _out_T_164 = eq(out_romask_15, UInt<1>(0h0)) node _out_T_165 = eq(out_womask_15, UInt<1>(0h0)) node _out_T_166 = or(div, UInt<16>(0h0)) node _out_T_167 = bits(_out_T_166, 15, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex = cat(_out_iindex_T_1, _out_iindex_T) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node out_oindex = cat(_out_oindex_T_1, _out_oindex_T) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[10], _out_rifireMux_T_7 connect out_rivalid[9], _out_rifireMux_T_7 connect out_rivalid[8], _out_rifireMux_T_7 connect out_rivalid[7], _out_rifireMux_T_7 connect out_rivalid[6], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_4) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[14], _out_rifireMux_T_11 connect out_rivalid[13], _out_rifireMux_T_11 connect out_rivalid[12], _out_rifireMux_T_11 connect out_rivalid[11], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_6) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[15], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[10], _out_wifireMux_T_8 connect out_wivalid[9], _out_wifireMux_T_8 connect out_wivalid[8], _out_wifireMux_T_8 connect out_wivalid[7], _out_wifireMux_T_8 connect out_wivalid[6], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_4) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[14], _out_wifireMux_T_12 connect out_wivalid[13], _out_wifireMux_T_12 connect out_wivalid[12], _out_wifireMux_T_12 connect out_wivalid[11], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_6) connect out_wifireMux_out_3, UInt<1>(0h1) connect out_wivalid[15], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[10], _out_rofireMux_T_7 connect out_roready[9], _out_rofireMux_T_7 connect out_roready[8], _out_rofireMux_T_7 connect out_roready[7], _out_rofireMux_T_7 connect out_roready[6], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_5) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[14], _out_rofireMux_T_11 connect out_roready[13], _out_rofireMux_T_11 connect out_roready[12], _out_rofireMux_T_11 connect out_roready[11], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_7) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[15], _out_rofireMux_T_15 node _out_rofireMux_T_16 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[10], _out_wofireMux_T_8 connect out_woready[9], _out_wofireMux_T_8 connect out_woready[8], _out_wofireMux_T_8 connect out_woready[7], _out_wofireMux_T_8 connect out_woready[6], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_5) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[14], _out_wofireMux_T_12 connect out_woready[13], _out_wofireMux_T_12 connect out_woready[12], _out_wofireMux_T_12 connect out_woready[11], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_7) connect out_wofireMux_out_3, UInt<1>(0h1) connect out_woready[15], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 connect _out_out_bits_data_WIRE[2], _out_T_5 connect _out_out_bits_data_WIRE[3], _out_T_7 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_61 connect _out_out_bits_data_WIRE_1[1], _out_T_116 connect _out_out_bits_data_WIRE_1[2], _out_T_156 connect _out_out_bits_data_WIRE_1[3], _out_T_167 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, controlNodeIn.a.valid connect controlNodeIn.a.ready, in.ready connect controlNodeIn.d.valid, out.valid connect out.ready, controlNodeIn.d.ready wire controlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect controlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect controlNodeIn_d_bits_d.param, UInt<1>(0h0) connect controlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect controlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect controlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect controlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate controlNodeIn_d_bits_d.data connect controlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect controlNodeIn.d.bits.corrupt, controlNodeIn_d_bits_d.corrupt connect controlNodeIn.d.bits.data, controlNodeIn_d_bits_d.data connect controlNodeIn.d.bits.denied, controlNodeIn_d_bits_d.denied connect controlNodeIn.d.bits.sink, controlNodeIn_d_bits_d.sink connect controlNodeIn.d.bits.source, controlNodeIn_d_bits_d.source connect controlNodeIn.d.bits.size, controlNodeIn_d_bits_d.size connect controlNodeIn.d.bits.param, controlNodeIn_d_bits_d.param connect controlNodeIn.d.bits.opcode, controlNodeIn_d_bits_d.opcode connect controlNodeIn.d.bits.data, out.bits.data node _controlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect controlNodeIn.d.bits.opcode, _controlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<14>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<14>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)

module TLUART( // @[UART.scala:127:25] input clock, // @[UART.scala:127:25] input reset, // @[UART.scala:127:25] output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_io_out_txd, // @[LazyModuleImp.scala:107:25] input auto_io_out_rxd // @[LazyModuleImp.scala:107:25] ); wire out_woready_2; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] wire out_backSel_0; // @[RegisterRouter.scala:87:24] wire quash; // @[RegisterRouter.scala:87:24] wire _rxq_io_deq_valid; // @[UART.scala:133:19] wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19] wire [3:0] _rxq_io_count; // @[UART.scala:133:19] wire _rxm_io_out_valid; // @[UART.scala:132:19] wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19] wire _txq_io_enq_ready; // @[UART.scala:130:19] wire _txq_io_deq_valid; // @[UART.scala:130:19] wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19] wire [3:0] _txq_io_count; // @[UART.scala:130:19] wire _txm_io_in_ready; // @[UART.scala:129:19] reg [15:0] div; // @[UART.scala:135:20] reg txen; // @[UART.scala:141:21] reg rxen; // @[UART.scala:142:21] reg [3:0] txwm; // @[UART.scala:149:21] reg [3:0] rxwm; // @[UART.scala:150:21] reg nstop; // @[UART.scala:151:22] reg ie_rxwm; // @[UART.scala:186:19] reg ie_txwm; // @[UART.scala:186:19] wire ip_txwm = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28] wire ip_rxwm = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28] wire in_bits_read = auto_control_xing_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_7 = auto_control_xing_in_a_bits_address[11:5] == 7'h0; // @[RegisterRouter.scala:75:19, :87:24] assign quash = out_woready_2 & auto_control_xing_in_a_bits_mask[3] & auto_control_xing_in_a_bits_data[31]; // @[RegisterRouter.scala:87:24] assign out_backSel_0 = auto_control_xing_in_a_bits_address[4:3] == 2'h0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = auto_control_xing_in_a_valid & auto_control_xing_in_d_ready; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] assign out_woready_2 = _out_wofireMux_T_2 & out_backSel_0 & _out_T_7; // @[RegisterRouter.scala:87:24] wire out_woready_9 = _out_wofireMux_T_2 & auto_control_xing_in_a_bits_address[4:3] == 2'h1 & _out_T_7; // @[RegisterRouter.scala:87:24] wire out_woready_12 = _out_wofireMux_T_2 & auto_control_xing_in_a_bits_address[4:3] == 2'h2 & _out_T_7; // @[RegisterRouter.scala:87:24] wire [3:0][63:0] _GEN = {{{48'h0, div}}, {{30'h0, ip_rxwm, ip_txwm, 30'h0, ie_rxwm, ie_txwm}}, {{12'h0, rxwm, 15'h0, rxen, 12'h0, txwm, 14'h0, nstop, txen}}, {{~_rxq_io_deq_valid, 23'h0, _rxq_io_deq_bits, ~_txq_io_enq_ready, 31'h0}}}; // @[MuxLiteral.scala:49:{10,48}] wire [2:0] controlXingIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] always @(posedge clock) begin // @[UART.scala:127:25] if (reset) begin // @[UART.scala:127:25] div <= 16'h10F4; // @[UART.scala:135:20] txen <= 1'h0; // @[UART.scala:127:25, :141:21] rxen <= 1'h0; // @[UART.scala:127:25, :142:21] txwm <= 4'h0; // @[UART.scala:149:21] rxwm <= 4'h0; // @[UART.scala:150:21] nstop <= 1'h0; // @[UART.scala:127:25, :151:22] ie_rxwm <= 1'h0; // @[UART.scala:127:25, :186:19] ie_txwm <= 1'h0; // @[UART.scala:127:25, :186:19] end else begin // @[UART.scala:127:25] if (_out_wofireMux_T_2 & (&(auto_control_xing_in_a_bits_address[4:3])) & _out_T_7 & (&{{8{auto_control_xing_in_a_bits_mask[1]}}, {8{auto_control_xing_in_a_bits_mask[0]}}})) // @[RegisterRouter.scala:87:24] div <= auto_control_xing_in_a_bits_data[15:0]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] txen <= auto_control_xing_in_a_bits_data[0]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[4]) // @[RegisterRouter.scala:87:24] rxen <= auto_control_xing_in_a_bits_data[32]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[2]) // @[RegisterRouter.scala:87:24] txwm <= auto_control_xing_in_a_bits_data[19:16]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[6]) // @[RegisterRouter.scala:87:24] rxwm <= auto_control_xing_in_a_bits_data[51:48]; // @[RegisterRouter.scala:87:24] if (out_woready_9 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] nstop <= auto_control_xing_in_a_bits_data[1]; // @[RegisterRouter.scala:87:24] if (out_woready_12 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] ie_rxwm <= auto_control_xing_in_a_bits_data[1]; // @[RegisterRouter.scala:87:24] if (out_woready_12 & auto_control_xing_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] ie_txwm <= auto_control_xing_in_a_bits_data[0]; // @[RegisterRouter.scala:87:24] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_6 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] connect auto.out, nodeOut connect nodeIn, auto.in inst reg of AsyncResetRegVec_w1_i0_6 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] connect reg.io.en, UInt<1>(0h1) node _T = bits(reg.io.q, 0, 0) connect nodeOut.sync[0], _T

module IntSyncCrossingSource_n1x1_6( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] AsyncResetRegVec_w1_i0_6 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d (nodeIn_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_sync_0) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module SBToTL : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}} output io : { flip rdEn : UInt<1>, flip wrEn : UInt<1>, flip addrIn : UInt<128>, flip dataIn : UInt<128>, flip sizeIn : UInt<3>, rdLegal : UInt<1>, wrLegal : UInt<1>, rdDone : UInt<1>, wrDone : UInt<1>, respError : UInt<1>, dataOut : UInt<8>, rdLoad : UInt<1>[8], sbStateOut : UInt<3>} input rf_reset : Reset wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut regreset sbState : UInt, clock, reset, UInt<1>(0h0) inst d_q of Queue2_TLBundleD_a32d8s1k1z4u connect d_q.clock, clock connect d_q.reset, reset connect d_q.io.enq.valid, nodeOut.d.valid connect d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect d_q.io.enq.bits.data, nodeOut.d.bits.data connect d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect d_q.io.enq.bits.source, nodeOut.d.bits.source connect d_q.io.enq.bits.size, nodeOut.d.bits.size connect d_q.io.enq.bits.param, nodeOut.d.bits.param connect d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, d_q.io.enq.ready node _q_io_deq_ready_T = eq(sbState, UInt<2>(0h3)) node _q_io_deq_ready_T_1 = eq(sbState, UInt<3>(0h4)) node _q_io_deq_ready_T_2 = or(_q_io_deq_ready_T, _q_io_deq_ready_T_1) connect d_q.io.deq.ready, _q_io_deq_ready_T_2 wire muxedData : UInt<8> connect muxedData, UInt<8>(0h0) regreset counter : UInt<4>, clock, reset, UInt<4>(0h0) wire vecData : UInt<8>[8] node _vecData_0_T = bits(io.dataIn, 7, 0) connect vecData[0], _vecData_0_T node _vecData_1_T = bits(io.dataIn, 15, 8) connect vecData[1], _vecData_1_T node _vecData_2_T = bits(io.dataIn, 23, 16) connect vecData[2], _vecData_2_T node _vecData_3_T = bits(io.dataIn, 31, 24) connect vecData[3], _vecData_3_T node _vecData_4_T = bits(io.dataIn, 39, 32) connect vecData[4], _vecData_4_T node _vecData_5_T = bits(io.dataIn, 47, 40) connect vecData[5], _vecData_5_T node _vecData_6_T = bits(io.dataIn, 55, 48) connect vecData[6], _vecData_6_T node _vecData_7_T = bits(io.dataIn, 63, 56) connect vecData[7], _vecData_7_T node _muxedData_T = bits(counter, 2, 0) connect muxedData, vecData[_muxedData_T] node _rdLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _rdLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _rdLegal_addr_T_2 = and(_rdLegal_addr_T, _rdLegal_addr_T_1) node _rdLegal_addr_T_3 = or(UInt<1>(0h1), _rdLegal_addr_T_2) node _rdLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _rdLegal_addr_T_5 = cvt(_rdLegal_addr_T_4) node _rdLegal_addr_T_6 = and(_rdLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _rdLegal_addr_T_7 = asSInt(_rdLegal_addr_T_6) node _rdLegal_addr_T_8 = eq(_rdLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h3000)) node _rdLegal_addr_T_10 = cvt(_rdLegal_addr_T_9) node _rdLegal_addr_T_11 = and(_rdLegal_addr_T_10, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_12 = asSInt(_rdLegal_addr_T_11) node _rdLegal_addr_T_13 = eq(_rdLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_14 = xor(io.addrIn, UInt<17>(0h10000)) node _rdLegal_addr_T_15 = cvt(_rdLegal_addr_T_14) node _rdLegal_addr_T_16 = and(_rdLegal_addr_T_15, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_17 = asSInt(_rdLegal_addr_T_16) node _rdLegal_addr_T_18 = eq(_rdLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_19 = xor(io.addrIn, UInt<21>(0h100000)) node _rdLegal_addr_T_20 = cvt(_rdLegal_addr_T_19) node _rdLegal_addr_T_21 = and(_rdLegal_addr_T_20, asSInt(UInt<18>(0h2f000))) node _rdLegal_addr_T_22 = asSInt(_rdLegal_addr_T_21) node _rdLegal_addr_T_23 = eq(_rdLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_24 = xor(io.addrIn, UInt<26>(0h2000000)) node _rdLegal_addr_T_25 = cvt(_rdLegal_addr_T_24) node _rdLegal_addr_T_26 = and(_rdLegal_addr_T_25, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_27 = asSInt(_rdLegal_addr_T_26) node _rdLegal_addr_T_28 = eq(_rdLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_29 = xor(io.addrIn, UInt<28>(0hc000000)) node _rdLegal_addr_T_30 = cvt(_rdLegal_addr_T_29) node _rdLegal_addr_T_31 = and(_rdLegal_addr_T_30, asSInt(UInt<27>(0h4000000))) node _rdLegal_addr_T_32 = asSInt(_rdLegal_addr_T_31) node _rdLegal_addr_T_33 = eq(_rdLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_34 = xor(io.addrIn, UInt<29>(0h10020000)) node _rdLegal_addr_T_35 = cvt(_rdLegal_addr_T_34) node _rdLegal_addr_T_36 = and(_rdLegal_addr_T_35, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_37 = asSInt(_rdLegal_addr_T_36) node _rdLegal_addr_T_38 = eq(_rdLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_39 = xor(io.addrIn, UInt<32>(0h80000000)) node _rdLegal_addr_T_40 = cvt(_rdLegal_addr_T_39) node _rdLegal_addr_T_41 = and(_rdLegal_addr_T_40, asSInt(UInt<19>(0h40000))) node _rdLegal_addr_T_42 = asSInt(_rdLegal_addr_T_41) node _rdLegal_addr_T_43 = eq(_rdLegal_addr_T_42, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_44 = or(_rdLegal_addr_T_8, _rdLegal_addr_T_13) node _rdLegal_addr_T_45 = or(_rdLegal_addr_T_44, _rdLegal_addr_T_18) node _rdLegal_addr_T_46 = or(_rdLegal_addr_T_45, _rdLegal_addr_T_23) node _rdLegal_addr_T_47 = or(_rdLegal_addr_T_46, _rdLegal_addr_T_28) node _rdLegal_addr_T_48 = or(_rdLegal_addr_T_47, _rdLegal_addr_T_33) node _rdLegal_addr_T_49 = or(_rdLegal_addr_T_48, _rdLegal_addr_T_38) node _rdLegal_addr_T_50 = or(_rdLegal_addr_T_49, _rdLegal_addr_T_43) node _rdLegal_addr_T_51 = and(_rdLegal_addr_T_3, _rdLegal_addr_T_50) node rdLegal_addr = or(UInt<1>(0h0), _rdLegal_addr_T_51) node _wrLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _wrLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _wrLegal_addr_T_2 = and(_wrLegal_addr_T, _wrLegal_addr_T_1) node _wrLegal_addr_T_3 = or(UInt<1>(0h1), _wrLegal_addr_T_2) node _wrLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _wrLegal_addr_T_5 = cvt(_wrLegal_addr_T_4) node _wrLegal_addr_T_6 = and(_wrLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _wrLegal_addr_T_7 = asSInt(_wrLegal_addr_T_6) node _wrLegal_addr_T_8 = eq(_wrLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h3000)) node _wrLegal_addr_T_10 = cvt(_wrLegal_addr_T_9) node _wrLegal_addr_T_11 = and(_wrLegal_addr_T_10, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_12 = asSInt(_wrLegal_addr_T_11) node _wrLegal_addr_T_13 = eq(_wrLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_14 = xor(io.addrIn, UInt<21>(0h100000)) node _wrLegal_addr_T_15 = cvt(_wrLegal_addr_T_14) node _wrLegal_addr_T_16 = and(_wrLegal_addr_T_15, asSInt(UInt<18>(0h2f000))) node _wrLegal_addr_T_17 = asSInt(_wrLegal_addr_T_16) node _wrLegal_addr_T_18 = eq(_wrLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_19 = xor(io.addrIn, UInt<26>(0h2000000)) node _wrLegal_addr_T_20 = cvt(_wrLegal_addr_T_19) node _wrLegal_addr_T_21 = and(_wrLegal_addr_T_20, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_22 = asSInt(_wrLegal_addr_T_21) node _wrLegal_addr_T_23 = eq(_wrLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_24 = xor(io.addrIn, UInt<28>(0hc000000)) node _wrLegal_addr_T_25 = cvt(_wrLegal_addr_T_24) node _wrLegal_addr_T_26 = and(_wrLegal_addr_T_25, asSInt(UInt<27>(0h4000000))) node _wrLegal_addr_T_27 = asSInt(_wrLegal_addr_T_26) node _wrLegal_addr_T_28 = eq(_wrLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_29 = xor(io.addrIn, UInt<29>(0h10020000)) node _wrLegal_addr_T_30 = cvt(_wrLegal_addr_T_29) node _wrLegal_addr_T_31 = and(_wrLegal_addr_T_30, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_32 = asSInt(_wrLegal_addr_T_31) node _wrLegal_addr_T_33 = eq(_wrLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_34 = xor(io.addrIn, UInt<32>(0h80000000)) node _wrLegal_addr_T_35 = cvt(_wrLegal_addr_T_34) node _wrLegal_addr_T_36 = and(_wrLegal_addr_T_35, asSInt(UInt<19>(0h40000))) node _wrLegal_addr_T_37 = asSInt(_wrLegal_addr_T_36) node _wrLegal_addr_T_38 = eq(_wrLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_39 = or(_wrLegal_addr_T_8, _wrLegal_addr_T_13) node _wrLegal_addr_T_40 = or(_wrLegal_addr_T_39, _wrLegal_addr_T_18) node _wrLegal_addr_T_41 = or(_wrLegal_addr_T_40, _wrLegal_addr_T_23) node _wrLegal_addr_T_42 = or(_wrLegal_addr_T_41, _wrLegal_addr_T_28) node _wrLegal_addr_T_43 = or(_wrLegal_addr_T_42, _wrLegal_addr_T_33) node _wrLegal_addr_T_44 = or(_wrLegal_addr_T_43, _wrLegal_addr_T_38) node _wrLegal_addr_T_45 = and(_wrLegal_addr_T_3, _wrLegal_addr_T_44) node _wrLegal_addr_T_46 = or(UInt<1>(0h0), UInt<1>(0h0)) node _wrLegal_addr_T_47 = xor(io.addrIn, UInt<17>(0h10000)) node _wrLegal_addr_T_48 = cvt(_wrLegal_addr_T_47) node _wrLegal_addr_T_49 = and(_wrLegal_addr_T_48, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_50 = asSInt(_wrLegal_addr_T_49) node _wrLegal_addr_T_51 = eq(_wrLegal_addr_T_50, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_52 = and(_wrLegal_addr_T_46, _wrLegal_addr_T_51) node _wrLegal_addr_T_53 = or(UInt<1>(0h0), _wrLegal_addr_T_45) node wrLegal_addr = or(_wrLegal_addr_T_53, _wrLegal_addr_T_52) node _gbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _gbits_legal_T_2 = and(_gbits_legal_T, _gbits_legal_T_1) node _gbits_legal_T_3 = or(UInt<1>(0h0), _gbits_legal_T_2) node _gbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _gbits_legal_T_5 = cvt(_gbits_legal_T_4) node _gbits_legal_T_6 = and(_gbits_legal_T_5, asSInt(UInt<33>(0h8a113000))) node _gbits_legal_T_7 = asSInt(_gbits_legal_T_6) node _gbits_legal_T_8 = eq(_gbits_legal_T_7, asSInt(UInt<1>(0h0))) node _gbits_legal_T_9 = and(_gbits_legal_T_3, _gbits_legal_T_8) node _gbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _gbits_legal_T_12 = and(_gbits_legal_T_10, _gbits_legal_T_11) node _gbits_legal_T_13 = or(UInt<1>(0h0), _gbits_legal_T_12) node _gbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _gbits_legal_T_15 = cvt(_gbits_legal_T_14) node _gbits_legal_T_16 = and(_gbits_legal_T_15, asSInt(UInt<33>(0h8a112000))) node _gbits_legal_T_17 = asSInt(_gbits_legal_T_16) node _gbits_legal_T_18 = eq(_gbits_legal_T_17, asSInt(UInt<1>(0h0))) node _gbits_legal_T_19 = xor(io.addrIn, UInt<17>(0h10000)) node _gbits_legal_T_20 = cvt(_gbits_legal_T_19) node _gbits_legal_T_21 = and(_gbits_legal_T_20, asSInt(UInt<33>(0h8a110000))) node _gbits_legal_T_22 = asSInt(_gbits_legal_T_21) node _gbits_legal_T_23 = eq(_gbits_legal_T_22, asSInt(UInt<1>(0h0))) node _gbits_legal_T_24 = xor(io.addrIn, UInt<21>(0h100000)) node _gbits_legal_T_25 = cvt(_gbits_legal_T_24) node _gbits_legal_T_26 = and(_gbits_legal_T_25, asSInt(UInt<33>(0h8a103000))) node _gbits_legal_T_27 = asSInt(_gbits_legal_T_26) node _gbits_legal_T_28 = eq(_gbits_legal_T_27, asSInt(UInt<1>(0h0))) node _gbits_legal_T_29 = xor(io.addrIn, UInt<26>(0h2000000)) node _gbits_legal_T_30 = cvt(_gbits_legal_T_29) node _gbits_legal_T_31 = and(_gbits_legal_T_30, asSInt(UInt<33>(0h8a110000))) node _gbits_legal_T_32 = asSInt(_gbits_legal_T_31) node _gbits_legal_T_33 = eq(_gbits_legal_T_32, asSInt(UInt<1>(0h0))) node _gbits_legal_T_34 = xor(io.addrIn, UInt<28>(0h8000000)) node _gbits_legal_T_35 = cvt(_gbits_legal_T_34) node _gbits_legal_T_36 = and(_gbits_legal_T_35, asSInt(UInt<33>(0h88000000))) node _gbits_legal_T_37 = asSInt(_gbits_legal_T_36) node _gbits_legal_T_38 = eq(_gbits_legal_T_37, asSInt(UInt<1>(0h0))) node _gbits_legal_T_39 = xor(io.addrIn, UInt<32>(0h80000000)) node _gbits_legal_T_40 = cvt(_gbits_legal_T_39) node _gbits_legal_T_41 = and(_gbits_legal_T_40, asSInt(UInt<33>(0h8a100000))) node _gbits_legal_T_42 = asSInt(_gbits_legal_T_41) node _gbits_legal_T_43 = eq(_gbits_legal_T_42, asSInt(UInt<1>(0h0))) node _gbits_legal_T_44 = or(_gbits_legal_T_18, _gbits_legal_T_23) node _gbits_legal_T_45 = or(_gbits_legal_T_44, _gbits_legal_T_28) node _gbits_legal_T_46 = or(_gbits_legal_T_45, _gbits_legal_T_33) node _gbits_legal_T_47 = or(_gbits_legal_T_46, _gbits_legal_T_38) node _gbits_legal_T_48 = or(_gbits_legal_T_47, _gbits_legal_T_43) node _gbits_legal_T_49 = and(_gbits_legal_T_13, _gbits_legal_T_48) node _gbits_legal_T_50 = or(UInt<1>(0h0), _gbits_legal_T_9) node gbits_legal = or(_gbits_legal_T_50, _gbits_legal_T_49) wire gbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect gbits.opcode, UInt<3>(0h4) connect gbits.param, UInt<1>(0h0) connect gbits.size, io.sizeIn connect gbits.source, UInt<1>(0h0) connect gbits.address, io.addrIn node _gbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node gbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect gbits.mask, UInt<1>(0h1) invalidate gbits.data connect gbits.corrupt, UInt<1>(0h0) node _pfbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _pfbits_legal_T_2 = and(_pfbits_legal_T, _pfbits_legal_T_1) node _pfbits_legal_T_3 = or(UInt<1>(0h0), _pfbits_legal_T_2) node _pfbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _pfbits_legal_T_5 = cvt(_pfbits_legal_T_4) node _pfbits_legal_T_6 = and(_pfbits_legal_T_5, asSInt(UInt<33>(0h8a113000))) node _pfbits_legal_T_7 = asSInt(_pfbits_legal_T_6) node _pfbits_legal_T_8 = eq(_pfbits_legal_T_7, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_9 = and(_pfbits_legal_T_3, _pfbits_legal_T_8) node _pfbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _pfbits_legal_T_12 = and(_pfbits_legal_T_10, _pfbits_legal_T_11) node _pfbits_legal_T_13 = or(UInt<1>(0h0), _pfbits_legal_T_12) node _pfbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _pfbits_legal_T_15 = cvt(_pfbits_legal_T_14) node _pfbits_legal_T_16 = and(_pfbits_legal_T_15, asSInt(UInt<33>(0h8a112000))) node _pfbits_legal_T_17 = asSInt(_pfbits_legal_T_16) node _pfbits_legal_T_18 = eq(_pfbits_legal_T_17, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_19 = xor(io.addrIn, UInt<21>(0h100000)) node _pfbits_legal_T_20 = cvt(_pfbits_legal_T_19) node _pfbits_legal_T_21 = and(_pfbits_legal_T_20, asSInt(UInt<33>(0h8a103000))) node _pfbits_legal_T_22 = asSInt(_pfbits_legal_T_21) node _pfbits_legal_T_23 = eq(_pfbits_legal_T_22, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_24 = xor(io.addrIn, UInt<26>(0h2000000)) node _pfbits_legal_T_25 = cvt(_pfbits_legal_T_24) node _pfbits_legal_T_26 = and(_pfbits_legal_T_25, asSInt(UInt<33>(0h8a110000))) node _pfbits_legal_T_27 = asSInt(_pfbits_legal_T_26) node _pfbits_legal_T_28 = eq(_pfbits_legal_T_27, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_29 = xor(io.addrIn, UInt<28>(0h8000000)) node _pfbits_legal_T_30 = cvt(_pfbits_legal_T_29) node _pfbits_legal_T_31 = and(_pfbits_legal_T_30, asSInt(UInt<33>(0h88000000))) node _pfbits_legal_T_32 = asSInt(_pfbits_legal_T_31) node _pfbits_legal_T_33 = eq(_pfbits_legal_T_32, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_34 = xor(io.addrIn, UInt<32>(0h80000000)) node _pfbits_legal_T_35 = cvt(_pfbits_legal_T_34) node _pfbits_legal_T_36 = and(_pfbits_legal_T_35, asSInt(UInt<33>(0h8a100000))) node _pfbits_legal_T_37 = asSInt(_pfbits_legal_T_36) node _pfbits_legal_T_38 = eq(_pfbits_legal_T_37, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_39 = or(_pfbits_legal_T_18, _pfbits_legal_T_23) node _pfbits_legal_T_40 = or(_pfbits_legal_T_39, _pfbits_legal_T_28) node _pfbits_legal_T_41 = or(_pfbits_legal_T_40, _pfbits_legal_T_33) node _pfbits_legal_T_42 = or(_pfbits_legal_T_41, _pfbits_legal_T_38) node _pfbits_legal_T_43 = and(_pfbits_legal_T_13, _pfbits_legal_T_42) node _pfbits_legal_T_44 = or(UInt<1>(0h0), UInt<1>(0h0)) node _pfbits_legal_T_45 = xor(io.addrIn, UInt<17>(0h10000)) node _pfbits_legal_T_46 = cvt(_pfbits_legal_T_45) node _pfbits_legal_T_47 = and(_pfbits_legal_T_46, asSInt(UInt<33>(0h8a110000))) node _pfbits_legal_T_48 = asSInt(_pfbits_legal_T_47) node _pfbits_legal_T_49 = eq(_pfbits_legal_T_48, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_50 = and(_pfbits_legal_T_44, _pfbits_legal_T_49) node _pfbits_legal_T_51 = or(UInt<1>(0h0), _pfbits_legal_T_9) node _pfbits_legal_T_52 = or(_pfbits_legal_T_51, _pfbits_legal_T_43) node pfbits_legal = or(_pfbits_legal_T_52, _pfbits_legal_T_50) wire pfbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect pfbits.opcode, UInt<1>(0h0) connect pfbits.param, UInt<1>(0h0) connect pfbits.size, io.sizeIn connect pfbits.source, UInt<1>(0h0) connect pfbits.address, io.addrIn node _pfbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node pfbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect pfbits.mask, UInt<1>(0h1) connect pfbits.data, muxedData connect pfbits.corrupt, UInt<1>(0h0) connect io.rdLegal, rdLegal_addr connect io.wrLegal, wrLegal_addr connect io.sbStateOut, sbState node _T = eq(sbState, UInt<1>(0h1)) when _T : connect nodeOut.a.bits, gbits else : connect nodeOut.a.bits, pfbits node respError = or(d_q.io.deq.bits.denied, d_q.io.deq.bits.corrupt) connect io.respError, respError node _wrTxValid_T = eq(sbState, UInt<2>(0h2)) node _wrTxValid_T_1 = and(_wrTxValid_T, nodeOut.a.valid) node wrTxValid = and(_wrTxValid_T_1, nodeOut.a.ready) node _rdTxValid_T = eq(sbState, UInt<2>(0h3)) node _rdTxValid_T_1 = and(_rdTxValid_T, d_q.io.deq.valid) node rdTxValid = and(_rdTxValid_T_1, d_q.io.deq.ready) node _txLast_T = dshl(UInt<1>(0h1), io.sizeIn) node _txLast_T_1 = sub(_txLast_T, UInt<1>(0h1)) node _txLast_T_2 = tail(_txLast_T_1, 1) node txLast = eq(counter, _txLast_T_2) node _counter_T = or(wrTxValid, rdTxValid) node _counter_T_1 = and(_counter_T, txLast) node _counter_T_2 = or(wrTxValid, rdTxValid) node _counter_T_3 = add(counter, UInt<1>(0h1)) node _counter_T_4 = tail(_counter_T_3, 1) node _counter_T_5 = mux(_counter_T_2, _counter_T_4, counter) node _counter_T_6 = mux(_counter_T_1, UInt<1>(0h0), _counter_T_5) connect counter, _counter_T_6 node _io_rdLoad_0_T = eq(counter, UInt<1>(0h0)) node _io_rdLoad_0_T_1 = and(rdTxValid, _io_rdLoad_0_T) connect io.rdLoad[0], _io_rdLoad_0_T_1 node _io_rdLoad_1_T = eq(counter, UInt<1>(0h1)) node _io_rdLoad_1_T_1 = and(rdTxValid, _io_rdLoad_1_T) connect io.rdLoad[1], _io_rdLoad_1_T_1 node _io_rdLoad_2_T = eq(counter, UInt<2>(0h2)) node _io_rdLoad_2_T_1 = and(rdTxValid, _io_rdLoad_2_T) connect io.rdLoad[2], _io_rdLoad_2_T_1 node _io_rdLoad_3_T = eq(counter, UInt<2>(0h3)) node _io_rdLoad_3_T_1 = and(rdTxValid, _io_rdLoad_3_T) connect io.rdLoad[3], _io_rdLoad_3_T_1 node _io_rdLoad_4_T = eq(counter, UInt<3>(0h4)) node _io_rdLoad_4_T_1 = and(rdTxValid, _io_rdLoad_4_T) connect io.rdLoad[4], _io_rdLoad_4_T_1 node _io_rdLoad_5_T = eq(counter, UInt<3>(0h5)) node _io_rdLoad_5_T_1 = and(rdTxValid, _io_rdLoad_5_T) connect io.rdLoad[5], _io_rdLoad_5_T_1 node _io_rdLoad_6_T = eq(counter, UInt<3>(0h6)) node _io_rdLoad_6_T_1 = and(rdTxValid, _io_rdLoad_6_T) connect io.rdLoad[6], _io_rdLoad_6_T_1 node _io_rdLoad_7_T = eq(counter, UInt<3>(0h7)) node _io_rdLoad_7_T_1 = and(rdTxValid, _io_rdLoad_7_T) connect io.rdLoad[7], _io_rdLoad_7_T_1 node _T_1 = eq(sbState, UInt<1>(0h0)) when _T_1 : node _sbState_T = and(io.rdEn, io.rdLegal) node _sbState_T_1 = and(io.wrEn, io.wrLegal) node _sbState_T_2 = mux(_sbState_T_1, UInt<2>(0h2), sbState) node _sbState_T_3 = mux(_sbState_T, UInt<1>(0h1), _sbState_T_2) connect sbState, _sbState_T_3 else : node _T_2 = eq(sbState, UInt<1>(0h1)) when _T_2 : node _sbState_T_4 = and(nodeOut.a.valid, nodeOut.a.ready) node _sbState_T_5 = mux(_sbState_T_4, UInt<2>(0h3), sbState) connect sbState, _sbState_T_5 else : node _T_3 = eq(sbState, UInt<2>(0h2)) when _T_3 : node _sbState_T_6 = and(wrTxValid, txLast) node _sbState_T_7 = mux(_sbState_T_6, UInt<3>(0h4), sbState) connect sbState, _sbState_T_7 else : node _T_4 = eq(sbState, UInt<2>(0h3)) when _T_4 : node _sbState_T_8 = and(rdTxValid, txLast) node _sbState_T_9 = mux(_sbState_T_8, UInt<1>(0h0), sbState) connect sbState, _sbState_T_9 else : node _T_5 = eq(sbState, UInt<3>(0h4)) when _T_5 : node _sbState_T_10 = and(d_q.io.deq.valid, d_q.io.deq.ready) node _sbState_T_11 = mux(_sbState_T_10, UInt<1>(0h0), sbState) connect sbState, _sbState_T_11 node _io_rdDone_T = and(rdTxValid, txLast) connect io.rdDone, _io_rdDone_T node _io_wrDone_T = eq(sbState, UInt<3>(0h4)) node _io_wrDone_T_1 = and(_io_wrDone_T, d_q.io.deq.valid) node _io_wrDone_T_2 = and(_io_wrDone_T_1, d_q.io.deq.ready) connect io.wrDone, _io_wrDone_T_2 connect io.dataOut, d_q.io.deq.bits.data node _nodeOut_a_valid_T = eq(sbState, UInt<1>(0h1)) node _nodeOut_a_valid_T_1 = eq(sbState, UInt<2>(0h2)) node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<8>(0h0) connect _WIRE.bits.mask, UInt<1>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) node _T_6 = eq(sbState, UInt<1>(0h0)) node _T_7 = eq(sbState, UInt<1>(0h1)) node _T_8 = or(_T_6, _T_7) node _T_9 = eq(sbState, UInt<2>(0h2)) node _T_10 = or(_T_8, _T_9) node _T_11 = eq(sbState, UInt<2>(0h3)) node _T_12 = or(_T_10, _T_11) node _T_13 = eq(sbState, UInt<3>(0h4)) node _T_14 = or(_T_12, _T_13) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed: SBA state machine in undefined state\n at SBA.scala:373 assert (sbState === Idle.id.U ||\n") : printf assert(clock, _T_14, UInt<1>(0h1), "") : assert node _T_18 = eq(sbState, UInt<1>(0h0)) node _T_19 = eq(sbState, UInt<1>(0h1)) node _T_20 = eq(sbState, UInt<2>(0h2)) node _T_21 = eq(sbState, UInt<2>(0h3)) node _T_22 = eq(sbState, UInt<3>(0h4)) node _T_23 = eq(io.rdLegal, UInt<1>(0h0)) node _T_24 = and(io.rdEn, _T_23) node _T_25 = eq(io.wrLegal, UInt<1>(0h0)) node _T_26 = and(io.wrEn, _T_25) extmodule plusarg_reader_74 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_75 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module SBToTL( // @[SBA.scala:273:9] input clock, // @[SBA.scala:273:9] input reset, // @[SBA.scala:273:9] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_rdEn, // @[SBA.scala:274:16] input io_wrEn, // @[SBA.scala:274:16] input [127:0] io_addrIn, // @[SBA.scala:274:16] input [127:0] io_dataIn, // @[SBA.scala:274:16] input [2:0] io_sizeIn, // @[SBA.scala:274:16] output io_rdLegal, // @[SBA.scala:274:16] output io_wrLegal, // @[SBA.scala:274:16] output io_rdDone, // @[SBA.scala:274:16] output io_wrDone, // @[SBA.scala:274:16] output io_respError, // @[SBA.scala:274:16] output [7:0] io_dataOut, // @[SBA.scala:274:16] output io_rdLoad_0, // @[SBA.scala:274:16] output io_rdLoad_1, // @[SBA.scala:274:16] output io_rdLoad_2, // @[SBA.scala:274:16] output io_rdLoad_3, // @[SBA.scala:274:16] output io_rdLoad_4, // @[SBA.scala:274:16] output io_rdLoad_5, // @[SBA.scala:274:16] output io_rdLoad_6, // @[SBA.scala:274:16] output io_rdLoad_7, // @[SBA.scala:274:16] output [2:0] io_sbStateOut, // @[SBA.scala:274:16] input rf_reset // @[SBA.scala:289:28] ); wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire auto_out_a_ready_0 = auto_out_a_ready; // @[SBA.scala:273:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[SBA.scala:273:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[SBA.scala:273:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[SBA.scala:273:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[SBA.scala:273:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[SBA.scala:273:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[SBA.scala:273:9] wire [7:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[SBA.scala:273:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[SBA.scala:273:9] wire io_rdEn_0 = io_rdEn; // @[SBA.scala:273:9] wire io_wrEn_0 = io_wrEn; // @[SBA.scala:273:9] wire [127:0] io_addrIn_0 = io_addrIn; // @[SBA.scala:273:9] wire [127:0] io_dataIn_0 = io_dataIn; // @[SBA.scala:273:9] wire [2:0] io_sizeIn_0 = io_sizeIn; // @[SBA.scala:273:9] wire auto_out_a_bits_source = 1'h0; // @[SBA.scala:273:9] wire auto_out_a_bits_corrupt = 1'h0; // @[SBA.scala:273:9] wire auto_out_d_bits_source = 1'h0; // @[SBA.scala:273:9] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire _wrLegal_addr_T_46 = 1'h0; // @[Parameters.scala:684:29] wire _wrLegal_addr_T_52 = 1'h0; // @[Parameters.scala:684:54] wire gbits_source = 1'h0; // @[Edges.scala:460:17] wire gbits_corrupt = 1'h0; // @[Edges.scala:460:17] wire _pfbits_legal_T_44 = 1'h0; // @[Parameters.scala:684:29] wire _pfbits_legal_T_50 = 1'h0; // @[Parameters.scala:684:54] wire pfbits_source = 1'h0; // @[Edges.scala:480:17] wire pfbits_corrupt = 1'h0; // @[Edges.scala:480:17] wire [2:0] auto_out_a_bits_param = 3'h0; // @[SBA.scala:273:9] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] gbits_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] pfbits_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] pfbits_param = 3'h0; // @[Edges.scala:480:17] wire auto_out_a_bits_mask = 1'h1; // @[SBA.scala:273:9] wire nodeOut_a_bits_mask = 1'h1; // @[MixedNode.scala:542:17] wire _rdLegal_addr_T = 1'h1; // @[Parameters.scala:92:28] wire _rdLegal_addr_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _wrLegal_addr_T = 1'h1; // @[Parameters.scala:92:28] wire _wrLegal_addr_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _gbits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _gbits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _gbits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _gbits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _gbits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire gbits_mask = 1'h1; // @[Edges.scala:460:17] wire gbits_a_mask_sizeOH = 1'h1; // @[Misc.scala:202:81] wire _pfbits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _pfbits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _pfbits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _pfbits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _pfbits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire pfbits_mask = 1'h1; // @[Edges.scala:480:17] wire pfbits_a_mask_sizeOH = 1'h1; // @[Misc.scala:202:81] wire [7:0] gbits_data = 8'h0; // @[Edges.scala:460:17] wire [2:0] gbits_opcode = 3'h4; // @[Edges.scala:460:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[SBA.scala:273:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[SBA.scala:273:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[SBA.scala:273:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[SBA.scala:273:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[SBA.scala:273:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[SBA.scala:273:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[SBA.scala:273:9] wire [7:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[SBA.scala:273:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[SBA.scala:273:9] wire [127:0] _rdLegal_addr_T_4 = io_addrIn_0; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_4 = io_addrIn_0; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_14 = io_addrIn_0; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_14 = io_addrIn_0; // @[Parameters.scala:137:31] wire rdLegal_addr; // @[Parameters.scala:686:26] wire [2:0] _gbits_a_mask_sizeOH_T = io_sizeIn_0; // @[Misc.scala:202:34] wire [2:0] _pfbits_a_mask_sizeOH_T = io_sizeIn_0; // @[Misc.scala:202:34] wire wrLegal_addr; // @[Parameters.scala:686:26] wire _io_rdDone_T; // @[SBA.scala:362:29] wire _io_wrDone_T_2; // @[SBA.scala:363:71] wire respError; // @[SBA.scala:335:35] wire _io_rdLoad_0_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_1_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_2_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_3_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_4_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_5_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_6_T_1; // @[SBA.scala:345:33] wire _io_rdLoad_7_T_1; // @[SBA.scala:345:33] wire [2:0] auto_out_a_bits_opcode_0; // @[SBA.scala:273:9] wire [3:0] auto_out_a_bits_size_0; // @[SBA.scala:273:9] wire [31:0] auto_out_a_bits_address_0; // @[SBA.scala:273:9] wire [7:0] auto_out_a_bits_data_0; // @[SBA.scala:273:9] wire auto_out_a_valid_0; // @[SBA.scala:273:9] wire auto_out_d_ready_0; // @[SBA.scala:273:9] wire io_rdLoad_0_0; // @[SBA.scala:273:9] wire io_rdLoad_1_0; // @[SBA.scala:273:9] wire io_rdLoad_2_0; // @[SBA.scala:273:9] wire io_rdLoad_3_0; // @[SBA.scala:273:9] wire io_rdLoad_4_0; // @[SBA.scala:273:9] wire io_rdLoad_5_0; // @[SBA.scala:273:9] wire io_rdLoad_6_0; // @[SBA.scala:273:9] wire io_rdLoad_7_0; // @[SBA.scala:273:9] wire io_rdLegal_0; // @[SBA.scala:273:9] wire io_wrLegal_0; // @[SBA.scala:273:9] wire io_rdDone_0; // @[SBA.scala:273:9] wire io_wrDone_0; // @[SBA.scala:273:9] wire io_respError_0; // @[SBA.scala:273:9] wire [7:0] io_dataOut_0; // @[SBA.scala:273:9] wire [2:0] io_sbStateOut_0; // @[SBA.scala:273:9] wire _nodeOut_a_valid_T_2; // @[SBA.scala:366:52] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[SBA.scala:273:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[SBA.scala:273:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[SBA.scala:273:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[SBA.scala:273:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[SBA.scala:273:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[SBA.scala:273:9] reg [2:0] sbState; // @[SBA.scala:295:26] assign io_sbStateOut_0 = sbState; // @[SBA.scala:273:9, :295:26] wire _T_21 = sbState == 3'h3; // @[SBA.scala:295:26, :299:25] wire _q_io_deq_ready_T; // @[SBA.scala:299:25] assign _q_io_deq_ready_T = _T_21; // @[SBA.scala:299:25] wire _rdTxValid_T; // @[SBA.scala:339:29] assign _rdTxValid_T = _T_21; // @[SBA.scala:299:25, :339:29] wire _T_22 = sbState == 3'h4; // @[SBA.scala:295:26, :299:62] wire _q_io_deq_ready_T_1; // @[SBA.scala:299:62] assign _q_io_deq_ready_T_1 = _T_22; // @[SBA.scala:299:62] wire _io_wrDone_T; // @[SBA.scala:363:28] assign _io_wrDone_T = _T_22; // @[SBA.scala:299:62, :363:28] wire _q_io_deq_ready_T_2 = _q_io_deq_ready_T | _q_io_deq_ready_T_1; // @[SBA.scala:299:{25,50,62}] wire [7:0] muxedData; // @[SBA.scala:301:29] wire [7:0] pfbits_data = muxedData; // @[Edges.scala:480:17] reg [3:0] counter; // @[SBA.scala:307:26] wire [7:0] _vecData_0_T; // @[SBA.scala:309:63] wire [7:0] _vecData_1_T; // @[SBA.scala:309:63] wire [7:0] _vecData_2_T; // @[SBA.scala:309:63] wire [7:0] _vecData_3_T; // @[SBA.scala:309:63] wire [7:0] _vecData_4_T; // @[SBA.scala:309:63] wire [7:0] _vecData_5_T; // @[SBA.scala:309:63] wire [7:0] _vecData_6_T; // @[SBA.scala:309:63] wire [7:0] _vecData_7_T; // @[SBA.scala:309:63] wire [7:0] vecData_0; // @[SBA.scala:308:25] wire [7:0] vecData_1; // @[SBA.scala:308:25] wire [7:0] vecData_2; // @[SBA.scala:308:25] wire [7:0] vecData_3; // @[SBA.scala:308:25] wire [7:0] vecData_4; // @[SBA.scala:308:25] wire [7:0] vecData_5; // @[SBA.scala:308:25] wire [7:0] vecData_6; // @[SBA.scala:308:25] wire [7:0] vecData_7; // @[SBA.scala:308:25] assign _vecData_0_T = io_dataIn_0[7:0]; // @[SBA.scala:273:9, :309:63] assign vecData_0 = _vecData_0_T; // @[SBA.scala:308:25, :309:63] assign _vecData_1_T = io_dataIn_0[15:8]; // @[SBA.scala:273:9, :309:63] assign vecData_1 = _vecData_1_T; // @[SBA.scala:308:25, :309:63] assign _vecData_2_T = io_dataIn_0[23:16]; // @[SBA.scala:273:9, :309:63] assign vecData_2 = _vecData_2_T; // @[SBA.scala:308:25, :309:63] assign _vecData_3_T = io_dataIn_0[31:24]; // @[SBA.scala:273:9, :309:63] assign vecData_3 = _vecData_3_T; // @[SBA.scala:308:25, :309:63] assign _vecData_4_T = io_dataIn_0[39:32]; // @[SBA.scala:273:9, :309:63] assign vecData_4 = _vecData_4_T; // @[SBA.scala:308:25, :309:63] assign _vecData_5_T = io_dataIn_0[47:40]; // @[SBA.scala:273:9, :309:63] assign vecData_5 = _vecData_5_T; // @[SBA.scala:308:25, :309:63] assign _vecData_6_T = io_dataIn_0[55:48]; // @[SBA.scala:273:9, :309:63] assign vecData_6 = _vecData_6_T; // @[SBA.scala:308:25, :309:63] assign _vecData_7_T = io_dataIn_0[63:56]; // @[SBA.scala:273:9, :309:63] assign vecData_7 = _vecData_7_T; // @[SBA.scala:308:25, :309:63] wire [2:0] _muxedData_T = counter[2:0]; // @[SBA.scala:307:26, :310:33] wire [7:0][7:0] _GEN = {{vecData_7}, {vecData_6}, {vecData_5}, {vecData_4}, {vecData_3}, {vecData_2}, {vecData_1}, {vecData_0}}; // @[SBA.scala:308:25, :310:15] assign muxedData = _GEN[_muxedData_T]; // @[SBA.scala:301:29, :310:{15,33}] wire _rdLegal_addr_T_1 = ~(io_sizeIn_0[2]); // @[Parameters.scala:92:38] wire _rdLegal_addr_T_2 = _rdLegal_addr_T_1; // @[Parameters.scala:92:{33,38}] wire [128:0] _rdLegal_addr_T_5 = {1'h0, _rdLegal_addr_T_4}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_6 = _rdLegal_addr_T_5 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_7 = _rdLegal_addr_T_6; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_8 = _rdLegal_addr_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_0 = {io_addrIn_0[127:14], io_addrIn_0[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_9; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_9 = _GEN_0; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_9; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_9 = _GEN_0; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_4; // @[Parameters.scala:137:31] assign _gbits_legal_T_4 = _GEN_0; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_4; // @[Parameters.scala:137:31] assign _pfbits_legal_T_4 = _GEN_0; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_10 = {1'h0, _rdLegal_addr_T_9}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_11 = _rdLegal_addr_T_10 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_12 = _rdLegal_addr_T_11; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_13 = _rdLegal_addr_T_12 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_1 = {io_addrIn_0[127:17], io_addrIn_0[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_14; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_14 = _GEN_1; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_47; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_47 = _GEN_1; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_19; // @[Parameters.scala:137:31] assign _gbits_legal_T_19 = _GEN_1; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_45; // @[Parameters.scala:137:31] assign _pfbits_legal_T_45 = _GEN_1; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_15 = {1'h0, _rdLegal_addr_T_14}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_16 = _rdLegal_addr_T_15 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_17 = _rdLegal_addr_T_16; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_18 = _rdLegal_addr_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_2 = {io_addrIn_0[127:21], io_addrIn_0[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_19; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_19 = _GEN_2; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_14; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_14 = _GEN_2; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_24; // @[Parameters.scala:137:31] assign _gbits_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_19; // @[Parameters.scala:137:31] assign _pfbits_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_20 = {1'h0, _rdLegal_addr_T_19}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_21 = _rdLegal_addr_T_20 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_22 = _rdLegal_addr_T_21; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_23 = _rdLegal_addr_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_3 = {io_addrIn_0[127:26], io_addrIn_0[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_24; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_24 = _GEN_3; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_19; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_19 = _GEN_3; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_29; // @[Parameters.scala:137:31] assign _gbits_legal_T_29 = _GEN_3; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_24; // @[Parameters.scala:137:31] assign _pfbits_legal_T_24 = _GEN_3; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_25 = {1'h0, _rdLegal_addr_T_24}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_26 = _rdLegal_addr_T_25 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_27 = _rdLegal_addr_T_26; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_28 = _rdLegal_addr_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_4 = {io_addrIn_0[127:28], io_addrIn_0[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_29; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_29 = _GEN_4; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_24; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_24 = _GEN_4; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_30 = {1'h0, _rdLegal_addr_T_29}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_31 = _rdLegal_addr_T_30 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_32 = _rdLegal_addr_T_31; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_33 = _rdLegal_addr_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_5 = {io_addrIn_0[127:29], io_addrIn_0[28:0] ^ 29'h10020000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_34; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_34 = _GEN_5; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_29; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_29 = _GEN_5; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_35 = {1'h0, _rdLegal_addr_T_34}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_36 = _rdLegal_addr_T_35 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_37 = _rdLegal_addr_T_36; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_38 = _rdLegal_addr_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] gbits_address = io_addrIn_0[31:0]; // @[Edges.scala:460:17] wire [31:0] pfbits_address = io_addrIn_0[31:0]; // @[Edges.scala:480:17] wire [127:0] _GEN_6 = {io_addrIn_0[127:32], io_addrIn_0[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [127:0] _rdLegal_addr_T_39; // @[Parameters.scala:137:31] assign _rdLegal_addr_T_39 = _GEN_6; // @[Parameters.scala:137:31] wire [127:0] _wrLegal_addr_T_34; // @[Parameters.scala:137:31] assign _wrLegal_addr_T_34 = _GEN_6; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_39; // @[Parameters.scala:137:31] assign _gbits_legal_T_39 = _GEN_6; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_34; // @[Parameters.scala:137:31] assign _pfbits_legal_T_34 = _GEN_6; // @[Parameters.scala:137:31] wire [128:0] _rdLegal_addr_T_40 = {1'h0, _rdLegal_addr_T_39}; // @[Parameters.scala:137:{31,41}] wire [128:0] _rdLegal_addr_T_41 = _rdLegal_addr_T_40 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFC0000; // @[Parameters.scala:137:{41,46}] wire [128:0] _rdLegal_addr_T_42 = _rdLegal_addr_T_41; // @[Parameters.scala:137:46] wire _rdLegal_addr_T_43 = _rdLegal_addr_T_42 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _rdLegal_addr_T_44 = _rdLegal_addr_T_8 | _rdLegal_addr_T_13; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_45 = _rdLegal_addr_T_44 | _rdLegal_addr_T_18; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_46 = _rdLegal_addr_T_45 | _rdLegal_addr_T_23; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_47 = _rdLegal_addr_T_46 | _rdLegal_addr_T_28; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_48 = _rdLegal_addr_T_47 | _rdLegal_addr_T_33; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_49 = _rdLegal_addr_T_48 | _rdLegal_addr_T_38; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_50 = _rdLegal_addr_T_49 | _rdLegal_addr_T_43; // @[Parameters.scala:685:42] wire _rdLegal_addr_T_51 = _rdLegal_addr_T_50; // @[Parameters.scala:684:54, :685:42] assign rdLegal_addr = _rdLegal_addr_T_51; // @[Parameters.scala:684:54, :686:26] assign io_rdLegal_0 = rdLegal_addr; // @[Parameters.scala:686:26] wire _wrLegal_addr_T_1 = ~(io_sizeIn_0[2]); // @[Parameters.scala:92:38] wire _wrLegal_addr_T_2 = _wrLegal_addr_T_1; // @[Parameters.scala:92:{33,38}] wire [128:0] _wrLegal_addr_T_5 = {1'h0, _wrLegal_addr_T_4}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_6 = _wrLegal_addr_T_5 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_7 = _wrLegal_addr_T_6; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_8 = _wrLegal_addr_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _wrLegal_addr_T_10 = {1'h0, _wrLegal_addr_T_9}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_11 = _wrLegal_addr_T_10 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_12 = _wrLegal_addr_T_11; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_13 = _wrLegal_addr_T_12 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _wrLegal_addr_T_15 = {1'h0, _wrLegal_addr_T_14}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_16 = _wrLegal_addr_T_15 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_17 = _wrLegal_addr_T_16; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_18 = _wrLegal_addr_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _wrLegal_addr_T_20 = {1'h0, _wrLegal_addr_T_19}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_21 = _wrLegal_addr_T_20 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_22 = _wrLegal_addr_T_21; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_23 = _wrLegal_addr_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _wrLegal_addr_T_25 = {1'h0, _wrLegal_addr_T_24}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_26 = _wrLegal_addr_T_25 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_27 = _wrLegal_addr_T_26; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_28 = _wrLegal_addr_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _wrLegal_addr_T_30 = {1'h0, _wrLegal_addr_T_29}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_31 = _wrLegal_addr_T_30 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_32 = _wrLegal_addr_T_31; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_33 = _wrLegal_addr_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _wrLegal_addr_T_35 = {1'h0, _wrLegal_addr_T_34}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_36 = _wrLegal_addr_T_35 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFC0000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_37 = _wrLegal_addr_T_36; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_38 = _wrLegal_addr_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _wrLegal_addr_T_39 = _wrLegal_addr_T_8 | _wrLegal_addr_T_13; // @[Parameters.scala:685:42] wire _wrLegal_addr_T_40 = _wrLegal_addr_T_39 | _wrLegal_addr_T_18; // @[Parameters.scala:685:42] wire _wrLegal_addr_T_41 = _wrLegal_addr_T_40 | _wrLegal_addr_T_23; // @[Parameters.scala:685:42] wire _wrLegal_addr_T_42 = _wrLegal_addr_T_41 | _wrLegal_addr_T_28; // @[Parameters.scala:685:42] wire _wrLegal_addr_T_43 = _wrLegal_addr_T_42 | _wrLegal_addr_T_33; // @[Parameters.scala:685:42] wire _wrLegal_addr_T_44 = _wrLegal_addr_T_43 | _wrLegal_addr_T_38; // @[Parameters.scala:685:42] wire _wrLegal_addr_T_45 = _wrLegal_addr_T_44; // @[Parameters.scala:684:54, :685:42] wire _wrLegal_addr_T_53 = _wrLegal_addr_T_45; // @[Parameters.scala:684:54, :686:26] wire [128:0] _wrLegal_addr_T_48 = {1'h0, _wrLegal_addr_T_47}; // @[Parameters.scala:137:{31,41}] wire [128:0] _wrLegal_addr_T_49 = _wrLegal_addr_T_48 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [128:0] _wrLegal_addr_T_50 = _wrLegal_addr_T_49; // @[Parameters.scala:137:46] wire _wrLegal_addr_T_51 = _wrLegal_addr_T_50 == 129'h0; // @[Parameters.scala:137:{46,59}] assign wrLegal_addr = _wrLegal_addr_T_53; // @[Parameters.scala:686:26] assign io_wrLegal_0 = wrLegal_addr; // @[Parameters.scala:686:26] wire [128:0] _gbits_legal_T_5 = {1'h0, _gbits_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_6 = _gbits_legal_T_5 & 129'h8A113000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_7 = _gbits_legal_T_6; // @[Parameters.scala:137:46] wire _gbits_legal_T_8 = _gbits_legal_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _gbits_legal_T_9 = _gbits_legal_T_8; // @[Parameters.scala:684:54] wire _gbits_legal_T_50 = _gbits_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _GEN_7 = io_sizeIn_0 != 3'h7; // @[Parameters.scala:92:38] wire _gbits_legal_T_11; // @[Parameters.scala:92:38] assign _gbits_legal_T_11 = _GEN_7; // @[Parameters.scala:92:38] wire _pfbits_legal_T_11; // @[Parameters.scala:92:38] assign _pfbits_legal_T_11 = _GEN_7; // @[Parameters.scala:92:38] wire _gbits_legal_T_12 = _gbits_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _gbits_legal_T_13 = _gbits_legal_T_12; // @[Parameters.scala:684:29] wire [128:0] _gbits_legal_T_15 = {1'h0, _gbits_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_16 = _gbits_legal_T_15 & 129'h8A112000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_17 = _gbits_legal_T_16; // @[Parameters.scala:137:46] wire _gbits_legal_T_18 = _gbits_legal_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _gbits_legal_T_20 = {1'h0, _gbits_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_21 = _gbits_legal_T_20 & 129'h8A110000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_22 = _gbits_legal_T_21; // @[Parameters.scala:137:46] wire _gbits_legal_T_23 = _gbits_legal_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _gbits_legal_T_25 = {1'h0, _gbits_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_26 = _gbits_legal_T_25 & 129'h8A103000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_27 = _gbits_legal_T_26; // @[Parameters.scala:137:46] wire _gbits_legal_T_28 = _gbits_legal_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _gbits_legal_T_30 = {1'h0, _gbits_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_31 = _gbits_legal_T_30 & 129'h8A110000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_32 = _gbits_legal_T_31; // @[Parameters.scala:137:46] wire _gbits_legal_T_33 = _gbits_legal_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [127:0] _GEN_8 = {io_addrIn_0[127:28], io_addrIn_0[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [127:0] _gbits_legal_T_34; // @[Parameters.scala:137:31] assign _gbits_legal_T_34 = _GEN_8; // @[Parameters.scala:137:31] wire [127:0] _pfbits_legal_T_29; // @[Parameters.scala:137:31] assign _pfbits_legal_T_29 = _GEN_8; // @[Parameters.scala:137:31] wire [128:0] _gbits_legal_T_35 = {1'h0, _gbits_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_36 = _gbits_legal_T_35 & 129'h88000000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_37 = _gbits_legal_T_36; // @[Parameters.scala:137:46] wire _gbits_legal_T_38 = _gbits_legal_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _gbits_legal_T_40 = {1'h0, _gbits_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [128:0] _gbits_legal_T_41 = _gbits_legal_T_40 & 129'h8A100000; // @[Parameters.scala:137:{41,46}] wire [128:0] _gbits_legal_T_42 = _gbits_legal_T_41; // @[Parameters.scala:137:46] wire _gbits_legal_T_43 = _gbits_legal_T_42 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _gbits_legal_T_44 = _gbits_legal_T_18 | _gbits_legal_T_23; // @[Parameters.scala:685:42] wire _gbits_legal_T_45 = _gbits_legal_T_44 | _gbits_legal_T_28; // @[Parameters.scala:685:42] wire _gbits_legal_T_46 = _gbits_legal_T_45 | _gbits_legal_T_33; // @[Parameters.scala:685:42] wire _gbits_legal_T_47 = _gbits_legal_T_46 | _gbits_legal_T_38; // @[Parameters.scala:685:42] wire _gbits_legal_T_48 = _gbits_legal_T_47 | _gbits_legal_T_43; // @[Parameters.scala:685:42] wire _gbits_legal_T_49 = _gbits_legal_T_13 & _gbits_legal_T_48; // @[Parameters.scala:684:{29,54}, :685:42] wire gbits_legal = _gbits_legal_T_50 | _gbits_legal_T_49; // @[Parameters.scala:684:54, :686:26] wire [3:0] gbits_size; // @[Edges.scala:460:17] wire [3:0] _GEN_9 = {1'h0, io_sizeIn_0}; // @[Edges.scala:463:15] assign gbits_size = _GEN_9; // @[Edges.scala:460:17, :463:15] wire [3:0] pfbits_size; // @[Edges.scala:480:17] assign pfbits_size = _GEN_9; // @[Edges.scala:463:15, :480:17] wire [128:0] _pfbits_legal_T_5 = {1'h0, _pfbits_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_6 = _pfbits_legal_T_5 & 129'h8A113000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_7 = _pfbits_legal_T_6; // @[Parameters.scala:137:46] wire _pfbits_legal_T_8 = _pfbits_legal_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _pfbits_legal_T_9 = _pfbits_legal_T_8; // @[Parameters.scala:684:54] wire _pfbits_legal_T_51 = _pfbits_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _pfbits_legal_T_12 = _pfbits_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _pfbits_legal_T_13 = _pfbits_legal_T_12; // @[Parameters.scala:684:29] wire [128:0] _pfbits_legal_T_15 = {1'h0, _pfbits_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_16 = _pfbits_legal_T_15 & 129'h8A112000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_17 = _pfbits_legal_T_16; // @[Parameters.scala:137:46] wire _pfbits_legal_T_18 = _pfbits_legal_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _pfbits_legal_T_20 = {1'h0, _pfbits_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_21 = _pfbits_legal_T_20 & 129'h8A103000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_22 = _pfbits_legal_T_21; // @[Parameters.scala:137:46] wire _pfbits_legal_T_23 = _pfbits_legal_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _pfbits_legal_T_25 = {1'h0, _pfbits_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_26 = _pfbits_legal_T_25 & 129'h8A110000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_27 = _pfbits_legal_T_26; // @[Parameters.scala:137:46] wire _pfbits_legal_T_28 = _pfbits_legal_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _pfbits_legal_T_30 = {1'h0, _pfbits_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_31 = _pfbits_legal_T_30 & 129'h88000000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_32 = _pfbits_legal_T_31; // @[Parameters.scala:137:46] wire _pfbits_legal_T_33 = _pfbits_legal_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}] wire [128:0] _pfbits_legal_T_35 = {1'h0, _pfbits_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_36 = _pfbits_legal_T_35 & 129'h8A100000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_37 = _pfbits_legal_T_36; // @[Parameters.scala:137:46] wire _pfbits_legal_T_38 = _pfbits_legal_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _pfbits_legal_T_39 = _pfbits_legal_T_18 | _pfbits_legal_T_23; // @[Parameters.scala:685:42] wire _pfbits_legal_T_40 = _pfbits_legal_T_39 | _pfbits_legal_T_28; // @[Parameters.scala:685:42] wire _pfbits_legal_T_41 = _pfbits_legal_T_40 | _pfbits_legal_T_33; // @[Parameters.scala:685:42] wire _pfbits_legal_T_42 = _pfbits_legal_T_41 | _pfbits_legal_T_38; // @[Parameters.scala:685:42] wire _pfbits_legal_T_43 = _pfbits_legal_T_13 & _pfbits_legal_T_42; // @[Parameters.scala:684:{29,54}, :685:42] wire [128:0] _pfbits_legal_T_46 = {1'h0, _pfbits_legal_T_45}; // @[Parameters.scala:137:{31,41}] wire [128:0] _pfbits_legal_T_47 = _pfbits_legal_T_46 & 129'h8A110000; // @[Parameters.scala:137:{41,46}] wire [128:0] _pfbits_legal_T_48 = _pfbits_legal_T_47; // @[Parameters.scala:137:46] wire _pfbits_legal_T_49 = _pfbits_legal_T_48 == 129'h0; // @[Parameters.scala:137:{46,59}] wire _pfbits_legal_T_52 = _pfbits_legal_T_51 | _pfbits_legal_T_43; // @[Parameters.scala:684:54, :686:26] wire pfbits_legal = _pfbits_legal_T_52; // @[Parameters.scala:686:26] wire _nodeOut_a_valid_T = sbState == 3'h1; // @[SBA.scala:295:26, :322:18, :366:28] assign nodeOut_a_bits_opcode = {_nodeOut_a_valid_T, 2'h0}; // @[SBA.scala:322:{42,54}, :323:54, :366:28] assign nodeOut_a_bits_size = _nodeOut_a_valid_T ? gbits_size : pfbits_size; // @[Edges.scala:460:17, :480:17] assign nodeOut_a_bits_address = _nodeOut_a_valid_T ? gbits_address : pfbits_address; // @[Edges.scala:460:17, :480:17] assign nodeOut_a_bits_data = _nodeOut_a_valid_T ? 8'h0 : pfbits_data; // @[Edges.scala:480:17] assign respError = _d_q_io_deq_bits_denied | _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] assign io_respError_0 = respError; // @[SBA.scala:273:9, :335:35] wire _T_20 = sbState == 3'h2; // @[SBA.scala:295:26, :338:29] wire _wrTxValid_T; // @[SBA.scala:338:29] assign _wrTxValid_T = _T_20; // @[SBA.scala:338:29] wire _nodeOut_a_valid_T_1; // @[SBA.scala:366:64] assign _nodeOut_a_valid_T_1 = _T_20; // @[SBA.scala:338:29, :366:64] wire _wrTxValid_T_1 = _wrTxValid_T & nodeOut_a_valid; // @[SBA.scala:338:{29,53}] wire wrTxValid = _wrTxValid_T_1 & nodeOut_a_ready; // @[SBA.scala:338:{53,69}] wire _rdTxValid_T_1 = _rdTxValid_T & _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire rdTxValid = _rdTxValid_T_1 & _q_io_deq_ready_T_2; // @[SBA.scala:299:50, :339:{53,70}] wire [7:0] _txLast_T = 8'h1 << io_sizeIn_0; // @[SBA.scala:273:9, :340:39] wire [8:0] _txLast_T_1 = {1'h0, _txLast_T} - 9'h1; // @[SBA.scala:340:{39,53}] wire [7:0] _txLast_T_2 = _txLast_T_1[7:0]; // @[SBA.scala:340:53] wire txLast = {4'h0, counter} == _txLast_T_2; // @[SBA.scala:307:26, :340:{29,53}] wire _GEN_10 = wrTxValid | rdTxValid; // @[SBA.scala:338:69, :339:70, :341:31] wire _counter_T; // @[SBA.scala:341:31] assign _counter_T = _GEN_10; // @[SBA.scala:341:31] wire _counter_T_2; // @[SBA.scala:342:31] assign _counter_T_2 = _GEN_10; // @[SBA.scala:341:31, :342:31] wire _counter_T_1 = _counter_T & txLast; // @[SBA.scala:340:29, :341:{31,45}] wire [4:0] _counter_T_3 = {1'h0, counter} + 5'h1; // @[SBA.scala:307:26, :342:63] wire [3:0] _counter_T_4 = _counter_T_3[3:0]; // @[SBA.scala:342:63] wire [3:0] _counter_T_5 = _counter_T_2 ? _counter_T_4 : counter; // @[SBA.scala:307:26, :342:{19,31,63}] wire [3:0] _counter_T_6 = _counter_T_1 ? 4'h0 : _counter_T_5; // @[SBA.scala:341:{19,45}, :342:19] wire _io_rdLoad_0_T = counter == 4'h0; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_0_T_1 = rdTxValid & _io_rdLoad_0_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_0_0 = _io_rdLoad_0_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_1_T = counter == 4'h1; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_1_T_1 = rdTxValid & _io_rdLoad_1_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_1_0 = _io_rdLoad_1_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_2_T = counter == 4'h2; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_2_T_1 = rdTxValid & _io_rdLoad_2_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_2_0 = _io_rdLoad_2_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_3_T = counter == 4'h3; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_3_T_1 = rdTxValid & _io_rdLoad_3_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_3_0 = _io_rdLoad_3_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_4_T = counter == 4'h4; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_4_T_1 = rdTxValid & _io_rdLoad_4_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_4_0 = _io_rdLoad_4_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_5_T = counter == 4'h5; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_5_T_1 = rdTxValid & _io_rdLoad_5_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_5_0 = _io_rdLoad_5_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_6_T = counter == 4'h6; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_6_T_1 = rdTxValid & _io_rdLoad_6_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_6_0 = _io_rdLoad_6_T_1; // @[SBA.scala:273:9, :345:33] wire _io_rdLoad_7_T = counter == 4'h7; // @[SBA.scala:307:26, :345:45] assign _io_rdLoad_7_T_1 = rdTxValid & _io_rdLoad_7_T; // @[SBA.scala:339:70, :345:{33,45}] assign io_rdLoad_7_0 = _io_rdLoad_7_T_1; // @[SBA.scala:273:9, :345:33] wire _sbState_T = io_rdEn_0 & io_rdLegal_0; // @[SBA.scala:273:9, :350:30] wire _sbState_T_1 = io_wrEn_0 & io_wrLegal_0; // @[SBA.scala:273:9, :351:30] wire [2:0] _sbState_T_2 = _sbState_T_1 ? 3'h2 : sbState; // @[SBA.scala:295:26, :351:{21,30}] wire [2:0] _sbState_T_3 = _sbState_T ? 3'h1 : _sbState_T_2; // @[SBA.scala:350:{21,30}, :351:21] wire _sbState_T_4 = nodeOut_a_valid & nodeOut_a_ready; // @[SBA.scala:353:35] wire [2:0] _sbState_T_5 = _sbState_T_4 ? 3'h3 : sbState; // @[SBA.scala:295:26, :353:{21,35}] wire _sbState_T_6 = wrTxValid & txLast; // @[SBA.scala:338:69, :340:29, :355:32] wire [2:0] _sbState_T_7 = _sbState_T_6 ? 3'h4 : sbState; // @[SBA.scala:295:26, :355:{21,32}] wire _GEN_11 = rdTxValid & txLast; // @[SBA.scala:339:70, :340:29, :357:32] wire _sbState_T_8; // @[SBA.scala:357:32] assign _sbState_T_8 = _GEN_11; // @[SBA.scala:357:32] assign _io_rdDone_T = _GEN_11; // @[SBA.scala:357:32, :362:29] wire [2:0] _sbState_T_9 = _sbState_T_8 ? 3'h0 : sbState; // @[SBA.scala:295:26, :357:{21,32}] wire _sbState_T_10 = _d_q_io_deq_valid & _q_io_deq_ready_T_2; // @[Decoupled.scala:362:21] wire [2:0] _sbState_T_11 = _sbState_T_10 ? 3'h0 : sbState; // @[SBA.scala:295:26, :359:{21,36}] assign io_rdDone_0 = _io_rdDone_T; // @[SBA.scala:273:9, :362:29] wire _io_wrDone_T_1 = _io_wrDone_T & _d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign _io_wrDone_T_2 = _io_wrDone_T_1 & _q_io_deq_ready_T_2; // @[SBA.scala:299:50, :363:{54,71}] assign io_wrDone_0 = _io_wrDone_T_2; // @[SBA.scala:273:9, :363:71] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T | _nodeOut_a_valid_T_1; // @[SBA.scala:366:{28,52,64}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[SBA.scala:366:52]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_180 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_324 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_180( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_324 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_41 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _source_ok_T_2 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 connect _source_ok_WIRE[2], _source_ok_T_2 node _source_ok_T_3 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_3, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_23 = cvt(_T_22) node _T_24 = and(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = asSInt(_T_24) node _T_26 = eq(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = or(_T_21, _T_26) node _T_28 = and(_T_11, _T_19) node _T_29 = and(_T_28, _T_27) node _T_30 = asUInt(reset) node _T_31 = eq(_T_30, UInt<1>(0h0)) when _T_31 : node _T_32 = eq(_T_29, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_29, UInt<1>(0h1), "") : assert_1 node _T_33 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_33 : node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_38 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_40 = or(_T_37, _T_38) node _T_41 = or(_T_40, _T_39) node _T_42 = and(_T_36, _T_41) node _T_43 = or(UInt<1>(0h0), _T_42) node _T_44 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<14>(0h2000))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<13>(0h1000))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<17>(0h10000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<18>(0h2f000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<13>(0h1000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<27>(0h4000000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = or(_T_49, _T_54) node _T_86 = or(_T_85, _T_59) node _T_87 = or(_T_86, _T_64) node _T_88 = or(_T_87, _T_69) node _T_89 = or(_T_88, _T_74) node _T_90 = or(_T_89, _T_79) node _T_91 = or(_T_90, _T_84) node _T_92 = and(_T_44, _T_91) node _T_93 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<29>(0h10000000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = and(_T_94, _T_105) node _T_107 = or(UInt<1>(0h0), _T_92) node _T_108 = or(_T_107, _T_106) node _T_109 = and(_T_43, _T_108) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_109, UInt<1>(0h1), "") : assert_2 node _T_113 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_115 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_113 connect _WIRE[1], _T_114 connect _WIRE[2], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_120 = or(_T_117, _T_118) node _T_121 = or(_T_120, _T_119) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_121 node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = or(UInt<1>(0h0), _T_124) node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = or(_T_130, _T_135) node _T_177 = or(_T_176, _T_140) node _T_178 = or(_T_177, _T_145) node _T_179 = or(_T_178, _T_150) node _T_180 = or(_T_179, _T_155) node _T_181 = or(_T_180, _T_160) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_170) node _T_184 = or(_T_183, _T_175) node _T_185 = and(_T_125, _T_184) node _T_186 = or(UInt<1>(0h0), _T_185) node _T_187 = and(_WIRE_1, _T_186) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_187, UInt<1>(0h1), "") : assert_3 node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(source_ok, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_194 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_194, UInt<1>(0h1), "") : assert_5 node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(is_aligned, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_201, UInt<1>(0h1), "") : assert_7 node _T_205 = not(io.in.a.bits.mask) node _T_206 = eq(_T_205, UInt<1>(0h0)) node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_T_206, UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_206, UInt<1>(0h1), "") : assert_8 node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_210, UInt<1>(0h1), "") : assert_9 node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_214 : node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_219 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_220 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_221 = or(_T_218, _T_219) node _T_222 = or(_T_221, _T_220) node _T_223 = and(_T_217, _T_222) node _T_224 = or(UInt<1>(0h0), _T_223) node _T_225 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<14>(0h2000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<18>(0h2f000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<27>(0h4000000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_230, _T_235) node _T_267 = or(_T_266, _T_240) node _T_268 = or(_T_267, _T_245) node _T_269 = or(_T_268, _T_250) node _T_270 = or(_T_269, _T_255) node _T_271 = or(_T_270, _T_260) node _T_272 = or(_T_271, _T_265) node _T_273 = and(_T_225, _T_272) node _T_274 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<29>(0h10000000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_280, _T_285) node _T_287 = and(_T_275, _T_286) node _T_288 = or(UInt<1>(0h0), _T_273) node _T_289 = or(_T_288, _T_287) node _T_290 = and(_T_224, _T_289) node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(_T_290, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_290, UInt<1>(0h1), "") : assert_10 node _T_294 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_295 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_296 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_294 connect _WIRE_2[1], _T_295 connect _WIRE_2[2], _T_296 node _T_297 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_298 = mux(_WIRE_2[0], _T_297, UInt<1>(0h0)) node _T_299 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_300 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = or(_T_298, _T_299) node _T_302 = or(_T_301, _T_300) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_302 node _T_303 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_304 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_305 = and(_T_303, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<14>(0h2000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_313 = cvt(_T_312) node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000))) node _T_315 = asSInt(_T_314) node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_318 = cvt(_T_317) node _T_319 = and(_T_318, asSInt(UInt<17>(0h10000))) node _T_320 = asSInt(_T_319) node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0))) node _T_322 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<18>(0h2f000))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<17>(0h10000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<27>(0h4000000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<13>(0h1000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<29>(0h10000000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = or(_T_311, _T_316) node _T_358 = or(_T_357, _T_321) node _T_359 = or(_T_358, _T_326) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_336) node _T_362 = or(_T_361, _T_341) node _T_363 = or(_T_362, _T_346) node _T_364 = or(_T_363, _T_351) node _T_365 = or(_T_364, _T_356) node _T_366 = and(_T_306, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_WIRE_3, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_368, UInt<1>(0h1), "") : assert_11 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(source_ok, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_375 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_375, UInt<1>(0h1), "") : assert_13 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(is_aligned, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_382 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_382, UInt<1>(0h1), "") : assert_15 node _T_386 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_386, UInt<1>(0h1), "") : assert_16 node _T_390 = not(io.in.a.bits.mask) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_391, UInt<1>(0h1), "") : assert_17 node _T_395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_395, UInt<1>(0h1), "") : assert_18 node _T_399 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_399 : node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_404 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_405 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_406 = or(_T_403, _T_404) node _T_407 = or(_T_406, _T_405) node _T_408 = and(_T_402, _T_407) node _T_409 = or(UInt<1>(0h0), _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_409, UInt<1>(0h1), "") : assert_19 node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = and(_T_416, _T_421) node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_433 = cvt(_T_432) node _T_434 = and(_T_433, asSInt(UInt<17>(0h10000))) node _T_435 = asSInt(_T_434) node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0))) node _T_437 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_438 = cvt(_T_437) node _T_439 = and(_T_438, asSInt(UInt<18>(0h2f000))) node _T_440 = asSInt(_T_439) node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0))) node _T_442 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_443 = cvt(_T_442) node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000))) node _T_445 = asSInt(_T_444) node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0))) node _T_447 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_453 = cvt(_T_452) node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000))) node _T_455 = asSInt(_T_454) node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0))) node _T_457 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<27>(0h4000000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<29>(0h10000000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = or(_T_431, _T_436) node _T_473 = or(_T_472, _T_441) node _T_474 = or(_T_473, _T_446) node _T_475 = or(_T_474, _T_451) node _T_476 = or(_T_475, _T_456) node _T_477 = or(_T_476, _T_461) node _T_478 = or(_T_477, _T_466) node _T_479 = or(_T_478, _T_471) node _T_480 = and(_T_426, _T_479) node _T_481 = or(UInt<1>(0h0), _T_422) node _T_482 = or(_T_481, _T_480) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_482, UInt<1>(0h1), "") : assert_20 node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(source_ok, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(is_aligned, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_492, UInt<1>(0h1), "") : assert_23 node _T_496 = eq(io.in.a.bits.mask, mask) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_496, UInt<1>(0h1), "") : assert_24 node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_500, UInt<1>(0h1), "") : assert_25 node _T_504 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_504 : node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_509 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_510 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_511 = or(_T_508, _T_509) node _T_512 = or(_T_511, _T_510) node _T_513 = and(_T_507, _T_512) node _T_514 = or(UInt<1>(0h0), _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = and(_T_518, _T_523) node _T_525 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_526 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_527 = and(_T_525, _T_526) node _T_528 = or(UInt<1>(0h0), _T_527) node _T_529 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<14>(0h2000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<18>(0h2f000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<17>(0h10000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<27>(0h4000000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<29>(0h10000000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = or(_T_533, _T_538) node _T_570 = or(_T_569, _T_543) node _T_571 = or(_T_570, _T_548) node _T_572 = or(_T_571, _T_553) node _T_573 = or(_T_572, _T_558) node _T_574 = or(_T_573, _T_563) node _T_575 = or(_T_574, _T_568) node _T_576 = and(_T_528, _T_575) node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = and(_T_577, _T_582) node _T_584 = or(UInt<1>(0h0), _T_524) node _T_585 = or(_T_584, _T_576) node _T_586 = or(_T_585, _T_583) node _T_587 = and(_T_514, _T_586) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_587, UInt<1>(0h1), "") : assert_26 node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(source_ok, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(is_aligned, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_597 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_597, UInt<1>(0h1), "") : assert_29 node _T_601 = eq(io.in.a.bits.mask, mask) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_601, UInt<1>(0h1), "") : assert_30 node _T_605 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_605 : node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_608 = and(_T_606, _T_607) node _T_609 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_610 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_611 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_612 = or(_T_609, _T_610) node _T_613 = or(_T_612, _T_611) node _T_614 = and(_T_608, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<27>(0h4000000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<29>(0h10000000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = or(_T_634, _T_639) node _T_671 = or(_T_670, _T_644) node _T_672 = or(_T_671, _T_649) node _T_673 = or(_T_672, _T_654) node _T_674 = or(_T_673, _T_659) node _T_675 = or(_T_674, _T_664) node _T_676 = or(_T_675, _T_669) node _T_677 = and(_T_629, _T_676) node _T_678 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_680 = cvt(_T_679) node _T_681 = and(_T_680, asSInt(UInt<17>(0h10000))) node _T_682 = asSInt(_T_681) node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0))) node _T_684 = and(_T_678, _T_683) node _T_685 = or(UInt<1>(0h0), _T_625) node _T_686 = or(_T_685, _T_677) node _T_687 = or(_T_686, _T_684) node _T_688 = and(_T_615, _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_688, UInt<1>(0h1), "") : assert_31 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(source_ok, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(is_aligned, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_698, UInt<1>(0h1), "") : assert_34 node _T_702 = not(mask) node _T_703 = and(io.in.a.bits.mask, _T_702) node _T_704 = eq(_T_703, UInt<1>(0h0)) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_704, UInt<1>(0h1), "") : assert_35 node _T_708 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_708 : node _T_709 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_710 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_711 = and(_T_709, _T_710) node _T_712 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_713 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_714 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_715 = or(_T_712, _T_713) node _T_716 = or(_T_715, _T_714) node _T_717 = and(_T_711, _T_716) node _T_718 = or(UInt<1>(0h0), _T_717) node _T_719 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_720 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<14>(0h2000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_749 = cvt(_T_748) node _T_750 = and(_T_749, asSInt(UInt<17>(0h10000))) node _T_751 = asSInt(_T_750) node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0))) node _T_753 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<27>(0h4000000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_764 = cvt(_T_763) node _T_765 = and(_T_764, asSInt(UInt<29>(0h10000000))) node _T_766 = asSInt(_T_765) node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0))) node _T_768 = or(_T_727, _T_732) node _T_769 = or(_T_768, _T_737) node _T_770 = or(_T_769, _T_742) node _T_771 = or(_T_770, _T_747) node _T_772 = or(_T_771, _T_752) node _T_773 = or(_T_772, _T_757) node _T_774 = or(_T_773, _T_762) node _T_775 = or(_T_774, _T_767) node _T_776 = and(_T_722, _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_776) node _T_785 = or(_T_784, _T_783) node _T_786 = and(_T_718, _T_785) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_786, UInt<1>(0h1), "") : assert_36 node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(source_ok, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(is_aligned, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_796 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_796, UInt<1>(0h1), "") : assert_39 node _T_800 = eq(io.in.a.bits.mask, mask) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_800, UInt<1>(0h1), "") : assert_40 node _T_804 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_809 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_810 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_811 = or(_T_808, _T_809) node _T_812 = or(_T_811, _T_810) node _T_813 = and(_T_807, _T_812) node _T_814 = or(UInt<1>(0h0), _T_813) node _T_815 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_816 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_817 = and(_T_815, _T_816) node _T_818 = or(UInt<1>(0h0), _T_817) node _T_819 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<14>(0h2000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<18>(0h2f000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<17>(0h10000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<29>(0h10000000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = or(_T_823, _T_828) node _T_865 = or(_T_864, _T_833) node _T_866 = or(_T_865, _T_838) node _T_867 = or(_T_866, _T_843) node _T_868 = or(_T_867, _T_848) node _T_869 = or(_T_868, _T_853) node _T_870 = or(_T_869, _T_858) node _T_871 = or(_T_870, _T_863) node _T_872 = and(_T_818, _T_871) node _T_873 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_874 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<17>(0h10000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = and(_T_873, _T_878) node _T_880 = or(UInt<1>(0h0), _T_872) node _T_881 = or(_T_880, _T_879) node _T_882 = and(_T_814, _T_881) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_882, UInt<1>(0h1), "") : assert_41 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(is_aligned, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_892, UInt<1>(0h1), "") : assert_44 node _T_896 = eq(io.in.a.bits.mask, mask) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_896, UInt<1>(0h1), "") : assert_45 node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_905 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_906 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_907 = or(_T_904, _T_905) node _T_908 = or(_T_907, _T_906) node _T_909 = and(_T_903, _T_908) node _T_910 = or(UInt<1>(0h0), _T_909) node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_912 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_913 = and(_T_911, _T_912) node _T_914 = or(UInt<1>(0h0), _T_913) node _T_915 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<13>(0h1000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = and(_T_914, _T_919) node _T_921 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<14>(0h2000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_948 = cvt(_T_947) node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000))) node _T_950 = asSInt(_T_949) node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0))) node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_953 = cvt(_T_952) node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000))) node _T_955 = asSInt(_T_954) node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0))) node _T_957 = or(_T_926, _T_931) node _T_958 = or(_T_957, _T_936) node _T_959 = or(_T_958, _T_941) node _T_960 = or(_T_959, _T_946) node _T_961 = or(_T_960, _T_951) node _T_962 = or(_T_961, _T_956) node _T_963 = and(_T_921, _T_962) node _T_964 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_965 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_966 = and(_T_964, _T_965) node _T_967 = or(UInt<1>(0h0), _T_966) node _T_968 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_969 = cvt(_T_968) node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000))) node _T_971 = asSInt(_T_970) node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0))) node _T_973 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_974 = cvt(_T_973) node _T_975 = and(_T_974, asSInt(UInt<29>(0h10000000))) node _T_976 = asSInt(_T_975) node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0))) node _T_978 = or(_T_972, _T_977) node _T_979 = and(_T_967, _T_978) node _T_980 = or(UInt<1>(0h0), _T_920) node _T_981 = or(_T_980, _T_963) node _T_982 = or(_T_981, _T_979) node _T_983 = and(_T_910, _T_982) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_983, UInt<1>(0h1), "") : assert_46 node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(source_ok, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(is_aligned, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_993 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_993, UInt<1>(0h1), "") : assert_49 node _T_997 = eq(io.in.a.bits.mask, mask) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_997, UInt<1>(0h1), "") : assert_50 node _T_1001 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1005 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_52 node _source_ok_T_4 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.d.bits.source, UInt<1>(0h1)) node _source_ok_T_6 = eq(io.in.d.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_4 connect _source_ok_WIRE_1[1], _source_ok_T_5 connect _source_ok_WIRE_1[2], _source_ok_T_6 node _source_ok_T_7 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_7, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1009 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1009 : node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(source_ok_1, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_54 node _T_1017 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_55 node _T_1021 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_56 node _T_1025 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_57 node _T_1029 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1029 : node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(source_ok_1, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(sink_ok, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1036 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_60 node _T_1040 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_61 node _T_1044 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_62 node _T_1048 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_63 node _T_1052 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1053 = or(UInt<1>(0h1), _T_1052) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_64 node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1057 : node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(source_ok_1, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(sink_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1064 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_67 node _T_1068 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_68 node _T_1072 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_69 node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1077 = or(_T_1076, io.in.d.bits.corrupt) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_70 node _T_1081 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1082 = or(UInt<1>(0h1), _T_1081) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_71 node _T_1086 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1086 : node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(source_ok_1, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1090 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_73 node _T_1094 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_74 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(UInt<1>(0h1), _T_1098) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_75 node _T_1103 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1103 : node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(source_ok_1, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1107 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_T_1107, UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1107, UInt<1>(0h1), "") : assert_77 node _T_1111 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1112 = or(_T_1111, io.in.d.bits.corrupt) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_78 node _T_1116 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1117 = or(UInt<1>(0h1), _T_1116) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_79 node _T_1121 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1121 : node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(source_ok_1, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1125 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_81 node _T_1129 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_82 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(UInt<1>(0h1), _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1138 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_84 node _T_1142 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) node _T_1144 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = or(_T_1143, _T_1148) node _T_1150 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<1>(0h0))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = or(_T_1151, _T_1156) node _T_1158 = eq(io.in.b.bits.source, UInt<2>(0h2)) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) node _T_1160 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1161 = cvt(_T_1160) node _T_1162 = and(_T_1161, asSInt(UInt<1>(0h0))) node _T_1163 = asSInt(_T_1162) node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0))) node _T_1165 = or(_T_1159, _T_1164) node _T_1166 = and(_T_1149, _T_1157) node _T_1167 = and(_T_1166, _T_1165) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _legal_source_T_2 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 connect _legal_source_WIRE[2], _legal_source_T_2 node _legal_source_T_3 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_4 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_5 = mux(_legal_source_WIRE[2], UInt<2>(0h2), UInt<1>(0h0)) node _legal_source_T_6 = or(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_7 = or(_legal_source_T_6, _legal_source_T_5) wire _legal_source_WIRE_1 : UInt<2> connect _legal_source_WIRE_1, _legal_source_T_7 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1171 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1171 : node _T_1172 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1173 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1174 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1172 connect _WIRE_4[1], _T_1173 connect _WIRE_4[2], _T_1174 node _T_1175 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1176 = mux(_WIRE_4[0], _T_1175, UInt<1>(0h0)) node _T_1177 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1178 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1179 = or(_T_1176, _T_1177) node _T_1180 = or(_T_1179, _T_1178) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1180 node _T_1181 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1182 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1183 = and(_T_1181, _T_1182) node _T_1184 = or(UInt<1>(0h0), _T_1183) node _T_1185 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1186 = cvt(_T_1185) node _T_1187 = and(_T_1186, asSInt(UInt<14>(0h2000))) node _T_1188 = asSInt(_T_1187) node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0))) node _T_1190 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<13>(0h1000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<17>(0h10000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1201 = cvt(_T_1200) node _T_1202 = and(_T_1201, asSInt(UInt<18>(0h2f000))) node _T_1203 = asSInt(_T_1202) node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0))) node _T_1205 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1206 = cvt(_T_1205) node _T_1207 = and(_T_1206, asSInt(UInt<17>(0h10000))) node _T_1208 = asSInt(_T_1207) node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0))) node _T_1210 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1211 = cvt(_T_1210) node _T_1212 = and(_T_1211, asSInt(UInt<13>(0h1000))) node _T_1213 = asSInt(_T_1212) node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1216 = cvt(_T_1215) node _T_1217 = and(_T_1216, asSInt(UInt<17>(0h10000))) node _T_1218 = asSInt(_T_1217) node _T_1219 = eq(_T_1218, asSInt(UInt<1>(0h0))) node _T_1220 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<27>(0h4000000))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<29>(0h10000000))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1189, _T_1194) node _T_1236 = or(_T_1235, _T_1199) node _T_1237 = or(_T_1236, _T_1204) node _T_1238 = or(_T_1237, _T_1209) node _T_1239 = or(_T_1238, _T_1214) node _T_1240 = or(_T_1239, _T_1219) node _T_1241 = or(_T_1240, _T_1224) node _T_1242 = or(_T_1241, _T_1229) node _T_1243 = or(_T_1242, _T_1234) node _T_1244 = and(_T_1184, _T_1243) node _T_1245 = or(UInt<1>(0h0), _T_1244) node _T_1246 = and(_WIRE_5, _T_1245) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_86 node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(address_ok, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(legal_source, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1259 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_90 node _T_1263 = eq(io.in.b.bits.mask, mask_1) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_91 node _T_1267 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(_T_1267, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1267, UInt<1>(0h1), "") : assert_92 node _T_1271 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1271 : node _T_1272 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1273 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1274 = and(_T_1272, _T_1273) node _T_1275 = or(UInt<1>(0h0), _T_1274) node _T_1276 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1277 = cvt(_T_1276) node _T_1278 = and(_T_1277, asSInt(UInt<14>(0h2000))) node _T_1279 = asSInt(_T_1278) node _T_1280 = eq(_T_1279, asSInt(UInt<1>(0h0))) node _T_1281 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1282 = cvt(_T_1281) node _T_1283 = and(_T_1282, asSInt(UInt<13>(0h1000))) node _T_1284 = asSInt(_T_1283) node _T_1285 = eq(_T_1284, asSInt(UInt<1>(0h0))) node _T_1286 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1287 = cvt(_T_1286) node _T_1288 = and(_T_1287, asSInt(UInt<17>(0h10000))) node _T_1289 = asSInt(_T_1288) node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0))) node _T_1291 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1292 = cvt(_T_1291) node _T_1293 = and(_T_1292, asSInt(UInt<18>(0h2f000))) node _T_1294 = asSInt(_T_1293) node _T_1295 = eq(_T_1294, asSInt(UInt<1>(0h0))) node _T_1296 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1297 = cvt(_T_1296) node _T_1298 = and(_T_1297, asSInt(UInt<17>(0h10000))) node _T_1299 = asSInt(_T_1298) node _T_1300 = eq(_T_1299, asSInt(UInt<1>(0h0))) node _T_1301 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1302 = cvt(_T_1301) node _T_1303 = and(_T_1302, asSInt(UInt<13>(0h1000))) node _T_1304 = asSInt(_T_1303) node _T_1305 = eq(_T_1304, asSInt(UInt<1>(0h0))) node _T_1306 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1307 = cvt(_T_1306) node _T_1308 = and(_T_1307, asSInt(UInt<17>(0h10000))) node _T_1309 = asSInt(_T_1308) node _T_1310 = eq(_T_1309, asSInt(UInt<1>(0h0))) node _T_1311 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1312 = cvt(_T_1311) node _T_1313 = and(_T_1312, asSInt(UInt<27>(0h4000000))) node _T_1314 = asSInt(_T_1313) node _T_1315 = eq(_T_1314, asSInt(UInt<1>(0h0))) node _T_1316 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1317 = cvt(_T_1316) node _T_1318 = and(_T_1317, asSInt(UInt<13>(0h1000))) node _T_1319 = asSInt(_T_1318) node _T_1320 = eq(_T_1319, asSInt(UInt<1>(0h0))) node _T_1321 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1322 = cvt(_T_1321) node _T_1323 = and(_T_1322, asSInt(UInt<29>(0h10000000))) node _T_1324 = asSInt(_T_1323) node _T_1325 = eq(_T_1324, asSInt(UInt<1>(0h0))) node _T_1326 = or(_T_1280, _T_1285) node _T_1327 = or(_T_1326, _T_1290) node _T_1328 = or(_T_1327, _T_1295) node _T_1329 = or(_T_1328, _T_1300) node _T_1330 = or(_T_1329, _T_1305) node _T_1331 = or(_T_1330, _T_1310) node _T_1332 = or(_T_1331, _T_1315) node _T_1333 = or(_T_1332, _T_1320) node _T_1334 = or(_T_1333, _T_1325) node _T_1335 = and(_T_1275, _T_1334) node _T_1336 = or(UInt<1>(0h0), _T_1335) node _T_1337 = and(UInt<1>(0h0), _T_1336) node _T_1338 = asUInt(reset) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) when _T_1339 : node _T_1340 = eq(_T_1337, UInt<1>(0h0)) when _T_1340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1337, UInt<1>(0h1), "") : assert_93 node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(address_ok, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(legal_source, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1350 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_97 node _T_1354 = eq(io.in.b.bits.mask, mask_1) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_98 node _T_1358 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_99 node _T_1362 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1362 : node _T_1363 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1364 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1365 = and(_T_1363, _T_1364) node _T_1366 = or(UInt<1>(0h0), _T_1365) node _T_1367 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1368 = cvt(_T_1367) node _T_1369 = and(_T_1368, asSInt(UInt<14>(0h2000))) node _T_1370 = asSInt(_T_1369) node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0))) node _T_1372 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1373 = cvt(_T_1372) node _T_1374 = and(_T_1373, asSInt(UInt<13>(0h1000))) node _T_1375 = asSInt(_T_1374) node _T_1376 = eq(_T_1375, asSInt(UInt<1>(0h0))) node _T_1377 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h10000))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<18>(0h2f000))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1388 = cvt(_T_1387) node _T_1389 = and(_T_1388, asSInt(UInt<17>(0h10000))) node _T_1390 = asSInt(_T_1389) node _T_1391 = eq(_T_1390, asSInt(UInt<1>(0h0))) node _T_1392 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1393 = cvt(_T_1392) node _T_1394 = and(_T_1393, asSInt(UInt<13>(0h1000))) node _T_1395 = asSInt(_T_1394) node _T_1396 = eq(_T_1395, asSInt(UInt<1>(0h0))) node _T_1397 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1398 = cvt(_T_1397) node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000))) node _T_1400 = asSInt(_T_1399) node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0))) node _T_1402 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1403 = cvt(_T_1402) node _T_1404 = and(_T_1403, asSInt(UInt<27>(0h4000000))) node _T_1405 = asSInt(_T_1404) node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0))) node _T_1407 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1408 = cvt(_T_1407) node _T_1409 = and(_T_1408, asSInt(UInt<13>(0h1000))) node _T_1410 = asSInt(_T_1409) node _T_1411 = eq(_T_1410, asSInt(UInt<1>(0h0))) node _T_1412 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1413 = cvt(_T_1412) node _T_1414 = and(_T_1413, asSInt(UInt<29>(0h10000000))) node _T_1415 = asSInt(_T_1414) node _T_1416 = eq(_T_1415, asSInt(UInt<1>(0h0))) node _T_1417 = or(_T_1371, _T_1376) node _T_1418 = or(_T_1417, _T_1381) node _T_1419 = or(_T_1418, _T_1386) node _T_1420 = or(_T_1419, _T_1391) node _T_1421 = or(_T_1420, _T_1396) node _T_1422 = or(_T_1421, _T_1401) node _T_1423 = or(_T_1422, _T_1406) node _T_1424 = or(_T_1423, _T_1411) node _T_1425 = or(_T_1424, _T_1416) node _T_1426 = and(_T_1366, _T_1425) node _T_1427 = or(UInt<1>(0h0), _T_1426) node _T_1428 = and(UInt<1>(0h0), _T_1427) node _T_1429 = asUInt(reset) node _T_1430 = eq(_T_1429, UInt<1>(0h0)) when _T_1430 : node _T_1431 = eq(_T_1428, UInt<1>(0h0)) when _T_1431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1428, UInt<1>(0h1), "") : assert_100 node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(address_ok, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1435 = asUInt(reset) node _T_1436 = eq(_T_1435, UInt<1>(0h0)) when _T_1436 : node _T_1437 = eq(legal_source, UInt<1>(0h0)) when _T_1437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1441 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_104 node _T_1445 = eq(io.in.b.bits.mask, mask_1) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_105 node _T_1449 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1449 : node _T_1450 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1451 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1452 = and(_T_1450, _T_1451) node _T_1453 = or(UInt<1>(0h0), _T_1452) node _T_1454 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1455 = cvt(_T_1454) node _T_1456 = and(_T_1455, asSInt(UInt<14>(0h2000))) node _T_1457 = asSInt(_T_1456) node _T_1458 = eq(_T_1457, asSInt(UInt<1>(0h0))) node _T_1459 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1460 = cvt(_T_1459) node _T_1461 = and(_T_1460, asSInt(UInt<13>(0h1000))) node _T_1462 = asSInt(_T_1461) node _T_1463 = eq(_T_1462, asSInt(UInt<1>(0h0))) node _T_1464 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1465 = cvt(_T_1464) node _T_1466 = and(_T_1465, asSInt(UInt<17>(0h10000))) node _T_1467 = asSInt(_T_1466) node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0))) node _T_1469 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1470 = cvt(_T_1469) node _T_1471 = and(_T_1470, asSInt(UInt<18>(0h2f000))) node _T_1472 = asSInt(_T_1471) node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0))) node _T_1474 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<17>(0h10000))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1480 = cvt(_T_1479) node _T_1481 = and(_T_1480, asSInt(UInt<13>(0h1000))) node _T_1482 = asSInt(_T_1481) node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0))) node _T_1484 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1485 = cvt(_T_1484) node _T_1486 = and(_T_1485, asSInt(UInt<17>(0h10000))) node _T_1487 = asSInt(_T_1486) node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0))) node _T_1489 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<27>(0h4000000))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1495 = cvt(_T_1494) node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000))) node _T_1497 = asSInt(_T_1496) node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0))) node _T_1499 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1500 = cvt(_T_1499) node _T_1501 = and(_T_1500, asSInt(UInt<29>(0h10000000))) node _T_1502 = asSInt(_T_1501) node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0))) node _T_1504 = or(_T_1458, _T_1463) node _T_1505 = or(_T_1504, _T_1468) node _T_1506 = or(_T_1505, _T_1473) node _T_1507 = or(_T_1506, _T_1478) node _T_1508 = or(_T_1507, _T_1483) node _T_1509 = or(_T_1508, _T_1488) node _T_1510 = or(_T_1509, _T_1493) node _T_1511 = or(_T_1510, _T_1498) node _T_1512 = or(_T_1511, _T_1503) node _T_1513 = and(_T_1453, _T_1512) node _T_1514 = or(UInt<1>(0h0), _T_1513) node _T_1515 = and(UInt<1>(0h0), _T_1514) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_106 node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(address_ok, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(legal_source, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1528 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_110 node _T_1532 = not(mask_1) node _T_1533 = and(io.in.b.bits.mask, _T_1532) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_111 node _T_1538 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1538 : node _T_1539 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1540 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1541 = and(_T_1539, _T_1540) node _T_1542 = or(UInt<1>(0h0), _T_1541) node _T_1543 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1544 = cvt(_T_1543) node _T_1545 = and(_T_1544, asSInt(UInt<14>(0h2000))) node _T_1546 = asSInt(_T_1545) node _T_1547 = eq(_T_1546, asSInt(UInt<1>(0h0))) node _T_1548 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1549 = cvt(_T_1548) node _T_1550 = and(_T_1549, asSInt(UInt<13>(0h1000))) node _T_1551 = asSInt(_T_1550) node _T_1552 = eq(_T_1551, asSInt(UInt<1>(0h0))) node _T_1553 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1554 = cvt(_T_1553) node _T_1555 = and(_T_1554, asSInt(UInt<17>(0h10000))) node _T_1556 = asSInt(_T_1555) node _T_1557 = eq(_T_1556, asSInt(UInt<1>(0h0))) node _T_1558 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1559 = cvt(_T_1558) node _T_1560 = and(_T_1559, asSInt(UInt<18>(0h2f000))) node _T_1561 = asSInt(_T_1560) node _T_1562 = eq(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1564 = cvt(_T_1563) node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000))) node _T_1566 = asSInt(_T_1565) node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0))) node _T_1568 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<13>(0h1000))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1574 = cvt(_T_1573) node _T_1575 = and(_T_1574, asSInt(UInt<17>(0h10000))) node _T_1576 = asSInt(_T_1575) node _T_1577 = eq(_T_1576, asSInt(UInt<1>(0h0))) node _T_1578 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1579 = cvt(_T_1578) node _T_1580 = and(_T_1579, asSInt(UInt<27>(0h4000000))) node _T_1581 = asSInt(_T_1580) node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0))) node _T_1583 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1584 = cvt(_T_1583) node _T_1585 = and(_T_1584, asSInt(UInt<13>(0h1000))) node _T_1586 = asSInt(_T_1585) node _T_1587 = eq(_T_1586, asSInt(UInt<1>(0h0))) node _T_1588 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1589 = cvt(_T_1588) node _T_1590 = and(_T_1589, asSInt(UInt<29>(0h10000000))) node _T_1591 = asSInt(_T_1590) node _T_1592 = eq(_T_1591, asSInt(UInt<1>(0h0))) node _T_1593 = or(_T_1547, _T_1552) node _T_1594 = or(_T_1593, _T_1557) node _T_1595 = or(_T_1594, _T_1562) node _T_1596 = or(_T_1595, _T_1567) node _T_1597 = or(_T_1596, _T_1572) node _T_1598 = or(_T_1597, _T_1577) node _T_1599 = or(_T_1598, _T_1582) node _T_1600 = or(_T_1599, _T_1587) node _T_1601 = or(_T_1600, _T_1592) node _T_1602 = and(_T_1542, _T_1601) node _T_1603 = or(UInt<1>(0h0), _T_1602) node _T_1604 = and(UInt<1>(0h0), _T_1603) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_112 node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(address_ok, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(legal_source, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1617 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_116 node _T_1621 = eq(io.in.b.bits.mask, mask_1) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_117 node _T_1625 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1625 : node _T_1626 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1627 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1628 = and(_T_1626, _T_1627) node _T_1629 = or(UInt<1>(0h0), _T_1628) node _T_1630 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1631 = cvt(_T_1630) node _T_1632 = and(_T_1631, asSInt(UInt<14>(0h2000))) node _T_1633 = asSInt(_T_1632) node _T_1634 = eq(_T_1633, asSInt(UInt<1>(0h0))) node _T_1635 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1636 = cvt(_T_1635) node _T_1637 = and(_T_1636, asSInt(UInt<13>(0h1000))) node _T_1638 = asSInt(_T_1637) node _T_1639 = eq(_T_1638, asSInt(UInt<1>(0h0))) node _T_1640 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1641 = cvt(_T_1640) node _T_1642 = and(_T_1641, asSInt(UInt<17>(0h10000))) node _T_1643 = asSInt(_T_1642) node _T_1644 = eq(_T_1643, asSInt(UInt<1>(0h0))) node _T_1645 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1646 = cvt(_T_1645) node _T_1647 = and(_T_1646, asSInt(UInt<18>(0h2f000))) node _T_1648 = asSInt(_T_1647) node _T_1649 = eq(_T_1648, asSInt(UInt<1>(0h0))) node _T_1650 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1651 = cvt(_T_1650) node _T_1652 = and(_T_1651, asSInt(UInt<17>(0h10000))) node _T_1653 = asSInt(_T_1652) node _T_1654 = eq(_T_1653, asSInt(UInt<1>(0h0))) node _T_1655 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1656 = cvt(_T_1655) node _T_1657 = and(_T_1656, asSInt(UInt<13>(0h1000))) node _T_1658 = asSInt(_T_1657) node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0))) node _T_1660 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1661 = cvt(_T_1660) node _T_1662 = and(_T_1661, asSInt(UInt<17>(0h10000))) node _T_1663 = asSInt(_T_1662) node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0))) node _T_1665 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1666 = cvt(_T_1665) node _T_1667 = and(_T_1666, asSInt(UInt<27>(0h4000000))) node _T_1668 = asSInt(_T_1667) node _T_1669 = eq(_T_1668, asSInt(UInt<1>(0h0))) node _T_1670 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1671 = cvt(_T_1670) node _T_1672 = and(_T_1671, asSInt(UInt<13>(0h1000))) node _T_1673 = asSInt(_T_1672) node _T_1674 = eq(_T_1673, asSInt(UInt<1>(0h0))) node _T_1675 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1676 = cvt(_T_1675) node _T_1677 = and(_T_1676, asSInt(UInt<29>(0h10000000))) node _T_1678 = asSInt(_T_1677) node _T_1679 = eq(_T_1678, asSInt(UInt<1>(0h0))) node _T_1680 = or(_T_1634, _T_1639) node _T_1681 = or(_T_1680, _T_1644) node _T_1682 = or(_T_1681, _T_1649) node _T_1683 = or(_T_1682, _T_1654) node _T_1684 = or(_T_1683, _T_1659) node _T_1685 = or(_T_1684, _T_1664) node _T_1686 = or(_T_1685, _T_1669) node _T_1687 = or(_T_1686, _T_1674) node _T_1688 = or(_T_1687, _T_1679) node _T_1689 = and(_T_1629, _T_1688) node _T_1690 = or(UInt<1>(0h0), _T_1689) node _T_1691 = and(UInt<1>(0h0), _T_1690) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_118 node _T_1695 = asUInt(reset) node _T_1696 = eq(_T_1695, UInt<1>(0h0)) when _T_1696 : node _T_1697 = eq(address_ok, UInt<1>(0h0)) when _T_1697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1698 = asUInt(reset) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) when _T_1699 : node _T_1700 = eq(legal_source, UInt<1>(0h0)) when _T_1700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1701 = asUInt(reset) node _T_1702 = eq(_T_1701, UInt<1>(0h0)) when _T_1702 : node _T_1703 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1704 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(_T_1704, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1704, UInt<1>(0h1), "") : assert_122 node _T_1708 = eq(io.in.b.bits.mask, mask_1) node _T_1709 = asUInt(reset) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(_T_1708, UInt<1>(0h0)) when _T_1711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1708, UInt<1>(0h1), "") : assert_123 node _T_1712 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1712 : node _T_1713 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1714 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1715 = and(_T_1713, _T_1714) node _T_1716 = or(UInt<1>(0h0), _T_1715) node _T_1717 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1718 = cvt(_T_1717) node _T_1719 = and(_T_1718, asSInt(UInt<14>(0h2000))) node _T_1720 = asSInt(_T_1719) node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0))) node _T_1722 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1723 = cvt(_T_1722) node _T_1724 = and(_T_1723, asSInt(UInt<13>(0h1000))) node _T_1725 = asSInt(_T_1724) node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0))) node _T_1727 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1728 = cvt(_T_1727) node _T_1729 = and(_T_1728, asSInt(UInt<17>(0h10000))) node _T_1730 = asSInt(_T_1729) node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0))) node _T_1732 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1733 = cvt(_T_1732) node _T_1734 = and(_T_1733, asSInt(UInt<18>(0h2f000))) node _T_1735 = asSInt(_T_1734) node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0))) node _T_1737 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1738 = cvt(_T_1737) node _T_1739 = and(_T_1738, asSInt(UInt<17>(0h10000))) node _T_1740 = asSInt(_T_1739) node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0))) node _T_1742 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1743 = cvt(_T_1742) node _T_1744 = and(_T_1743, asSInt(UInt<13>(0h1000))) node _T_1745 = asSInt(_T_1744) node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1748 = cvt(_T_1747) node _T_1749 = and(_T_1748, asSInt(UInt<17>(0h10000))) node _T_1750 = asSInt(_T_1749) node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0))) node _T_1752 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<27>(0h4000000))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1758 = cvt(_T_1757) node _T_1759 = and(_T_1758, asSInt(UInt<13>(0h1000))) node _T_1760 = asSInt(_T_1759) node _T_1761 = eq(_T_1760, asSInt(UInt<1>(0h0))) node _T_1762 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<29>(0h10000000))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1721, _T_1726) node _T_1768 = or(_T_1767, _T_1731) node _T_1769 = or(_T_1768, _T_1736) node _T_1770 = or(_T_1769, _T_1741) node _T_1771 = or(_T_1770, _T_1746) node _T_1772 = or(_T_1771, _T_1751) node _T_1773 = or(_T_1772, _T_1756) node _T_1774 = or(_T_1773, _T_1761) node _T_1775 = or(_T_1774, _T_1766) node _T_1776 = and(_T_1716, _T_1775) node _T_1777 = or(UInt<1>(0h0), _T_1776) node _T_1778 = and(UInt<1>(0h0), _T_1777) node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(_T_1778, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1778, UInt<1>(0h1), "") : assert_124 node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(address_ok, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1785 = asUInt(reset) node _T_1786 = eq(_T_1785, UInt<1>(0h0)) when _T_1786 : node _T_1787 = eq(legal_source, UInt<1>(0h0)) when _T_1787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1791 = eq(io.in.b.bits.mask, mask_1) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_128 node _T_1795 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1796 = asUInt(reset) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) when _T_1797 : node _T_1798 = eq(_T_1795, UInt<1>(0h0)) when _T_1798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1795, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1799 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_130 node _source_ok_T_8 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_9 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _source_ok_T_10 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_8 connect _source_ok_WIRE_2[1], _source_ok_T_9 connect _source_ok_WIRE_2[2], _source_ok_T_10 node _source_ok_T_11 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_11, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _T_1803 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) node _T_1805 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1806 = cvt(_T_1805) node _T_1807 = and(_T_1806, asSInt(UInt<1>(0h0))) node _T_1808 = asSInt(_T_1807) node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0))) node _T_1810 = or(_T_1804, _T_1809) node _T_1811 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1812 = eq(_T_1811, UInt<1>(0h0)) node _T_1813 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1814 = cvt(_T_1813) node _T_1815 = and(_T_1814, asSInt(UInt<1>(0h0))) node _T_1816 = asSInt(_T_1815) node _T_1817 = eq(_T_1816, asSInt(UInt<1>(0h0))) node _T_1818 = or(_T_1812, _T_1817) node _T_1819 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1820 = eq(_T_1819, UInt<1>(0h0)) node _T_1821 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1822 = cvt(_T_1821) node _T_1823 = and(_T_1822, asSInt(UInt<1>(0h0))) node _T_1824 = asSInt(_T_1823) node _T_1825 = eq(_T_1824, asSInt(UInt<1>(0h0))) node _T_1826 = or(_T_1820, _T_1825) node _T_1827 = and(_T_1810, _T_1818) node _T_1828 = and(_T_1827, _T_1826) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_131 node _T_1832 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1832 : node _T_1833 = asUInt(reset) node _T_1834 = eq(_T_1833, UInt<1>(0h0)) when _T_1834 : node _T_1835 = eq(address_ok_1, UInt<1>(0h0)) when _T_1835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1836 = asUInt(reset) node _T_1837 = eq(_T_1836, UInt<1>(0h0)) when _T_1837 : node _T_1838 = eq(source_ok_2, UInt<1>(0h0)) when _T_1838 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1839 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1840 = asUInt(reset) node _T_1841 = eq(_T_1840, UInt<1>(0h0)) when _T_1841 : node _T_1842 = eq(_T_1839, UInt<1>(0h0)) when _T_1842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1839, UInt<1>(0h1), "") : assert_134 node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1846 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_136 node _T_1850 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(_T_1850, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1850, UInt<1>(0h1), "") : assert_137 node _T_1854 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1854 : node _T_1855 = asUInt(reset) node _T_1856 = eq(_T_1855, UInt<1>(0h0)) when _T_1856 : node _T_1857 = eq(address_ok_1, UInt<1>(0h0)) when _T_1857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(source_ok_2, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1861 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(_T_1861, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1861, UInt<1>(0h1), "") : assert_140 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1868 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_142 node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1872 : node _T_1873 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1874 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1875 = and(_T_1873, _T_1874) node _T_1876 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1877 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1878 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1879 = or(_T_1876, _T_1877) node _T_1880 = or(_T_1879, _T_1878) node _T_1881 = and(_T_1875, _T_1880) node _T_1882 = or(UInt<1>(0h0), _T_1881) node _T_1883 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1884 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1885 = cvt(_T_1884) node _T_1886 = and(_T_1885, asSInt(UInt<14>(0h2000))) node _T_1887 = asSInt(_T_1886) node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0))) node _T_1889 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1890 = cvt(_T_1889) node _T_1891 = and(_T_1890, asSInt(UInt<13>(0h1000))) node _T_1892 = asSInt(_T_1891) node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1895 = cvt(_T_1894) node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000))) node _T_1897 = asSInt(_T_1896) node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0))) node _T_1899 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1900 = cvt(_T_1899) node _T_1901 = and(_T_1900, asSInt(UInt<18>(0h2f000))) node _T_1902 = asSInt(_T_1901) node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1905 = cvt(_T_1904) node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000))) node _T_1907 = asSInt(_T_1906) node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1910 = cvt(_T_1909) node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000))) node _T_1912 = asSInt(_T_1911) node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0))) node _T_1914 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1915 = cvt(_T_1914) node _T_1916 = and(_T_1915, asSInt(UInt<27>(0h4000000))) node _T_1917 = asSInt(_T_1916) node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0))) node _T_1919 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1920 = cvt(_T_1919) node _T_1921 = and(_T_1920, asSInt(UInt<13>(0h1000))) node _T_1922 = asSInt(_T_1921) node _T_1923 = eq(_T_1922, asSInt(UInt<1>(0h0))) node _T_1924 = or(_T_1888, _T_1893) node _T_1925 = or(_T_1924, _T_1898) node _T_1926 = or(_T_1925, _T_1903) node _T_1927 = or(_T_1926, _T_1908) node _T_1928 = or(_T_1927, _T_1913) node _T_1929 = or(_T_1928, _T_1918) node _T_1930 = or(_T_1929, _T_1923) node _T_1931 = and(_T_1883, _T_1930) node _T_1932 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1933 = or(UInt<1>(0h0), _T_1932) node _T_1934 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1935 = cvt(_T_1934) node _T_1936 = and(_T_1935, asSInt(UInt<17>(0h10000))) node _T_1937 = asSInt(_T_1936) node _T_1938 = eq(_T_1937, asSInt(UInt<1>(0h0))) node _T_1939 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1940 = cvt(_T_1939) node _T_1941 = and(_T_1940, asSInt(UInt<29>(0h10000000))) node _T_1942 = asSInt(_T_1941) node _T_1943 = eq(_T_1942, asSInt(UInt<1>(0h0))) node _T_1944 = or(_T_1938, _T_1943) node _T_1945 = and(_T_1933, _T_1944) node _T_1946 = or(UInt<1>(0h0), _T_1931) node _T_1947 = or(_T_1946, _T_1945) node _T_1948 = and(_T_1882, _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_143 node _T_1952 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1953 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1954 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_1952 connect _WIRE_6[1], _T_1953 connect _WIRE_6[2], _T_1954 node _T_1955 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1956 = mux(_WIRE_6[0], _T_1955, UInt<1>(0h0)) node _T_1957 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1958 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1959 = or(_T_1956, _T_1957) node _T_1960 = or(_T_1959, _T_1958) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1960 node _T_1961 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1962 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1963 = and(_T_1961, _T_1962) node _T_1964 = or(UInt<1>(0h0), _T_1963) node _T_1965 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1966 = cvt(_T_1965) node _T_1967 = and(_T_1966, asSInt(UInt<14>(0h2000))) node _T_1968 = asSInt(_T_1967) node _T_1969 = eq(_T_1968, asSInt(UInt<1>(0h0))) node _T_1970 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1971 = cvt(_T_1970) node _T_1972 = and(_T_1971, asSInt(UInt<13>(0h1000))) node _T_1973 = asSInt(_T_1972) node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0))) node _T_1975 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<17>(0h10000))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1981 = cvt(_T_1980) node _T_1982 = and(_T_1981, asSInt(UInt<18>(0h2f000))) node _T_1983 = asSInt(_T_1982) node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0))) node _T_1985 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1986 = cvt(_T_1985) node _T_1987 = and(_T_1986, asSInt(UInt<17>(0h10000))) node _T_1988 = asSInt(_T_1987) node _T_1989 = eq(_T_1988, asSInt(UInt<1>(0h0))) node _T_1990 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1991 = cvt(_T_1990) node _T_1992 = and(_T_1991, asSInt(UInt<13>(0h1000))) node _T_1993 = asSInt(_T_1992) node _T_1994 = eq(_T_1993, asSInt(UInt<1>(0h0))) node _T_1995 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1996 = cvt(_T_1995) node _T_1997 = and(_T_1996, asSInt(UInt<17>(0h10000))) node _T_1998 = asSInt(_T_1997) node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0))) node _T_2000 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2001 = cvt(_T_2000) node _T_2002 = and(_T_2001, asSInt(UInt<27>(0h4000000))) node _T_2003 = asSInt(_T_2002) node _T_2004 = eq(_T_2003, asSInt(UInt<1>(0h0))) node _T_2005 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2006 = cvt(_T_2005) node _T_2007 = and(_T_2006, asSInt(UInt<13>(0h1000))) node _T_2008 = asSInt(_T_2007) node _T_2009 = eq(_T_2008, asSInt(UInt<1>(0h0))) node _T_2010 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2011 = cvt(_T_2010) node _T_2012 = and(_T_2011, asSInt(UInt<29>(0h10000000))) node _T_2013 = asSInt(_T_2012) node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0))) node _T_2015 = or(_T_1969, _T_1974) node _T_2016 = or(_T_2015, _T_1979) node _T_2017 = or(_T_2016, _T_1984) node _T_2018 = or(_T_2017, _T_1989) node _T_2019 = or(_T_2018, _T_1994) node _T_2020 = or(_T_2019, _T_1999) node _T_2021 = or(_T_2020, _T_2004) node _T_2022 = or(_T_2021, _T_2009) node _T_2023 = or(_T_2022, _T_2014) node _T_2024 = and(_T_1964, _T_2023) node _T_2025 = or(UInt<1>(0h0), _T_2024) node _T_2026 = and(_WIRE_7, _T_2025) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_144 node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(source_ok_2, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2033 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_146 node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2040 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_148 node _T_2044 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_149 node _T_2048 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2048 : node _T_2049 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2050 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2051 = and(_T_2049, _T_2050) node _T_2052 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2053 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2054 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_2055 = or(_T_2052, _T_2053) node _T_2056 = or(_T_2055, _T_2054) node _T_2057 = and(_T_2051, _T_2056) node _T_2058 = or(UInt<1>(0h0), _T_2057) node _T_2059 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2060 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<14>(0h2000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<13>(0h1000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<17>(0h10000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<18>(0h2f000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<17>(0h10000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = or(_T_2064, _T_2069) node _T_2101 = or(_T_2100, _T_2074) node _T_2102 = or(_T_2101, _T_2079) node _T_2103 = or(_T_2102, _T_2084) node _T_2104 = or(_T_2103, _T_2089) node _T_2105 = or(_T_2104, _T_2094) node _T_2106 = or(_T_2105, _T_2099) node _T_2107 = and(_T_2059, _T_2106) node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2109 = or(UInt<1>(0h0), _T_2108) node _T_2110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2111 = cvt(_T_2110) node _T_2112 = and(_T_2111, asSInt(UInt<17>(0h10000))) node _T_2113 = asSInt(_T_2112) node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0))) node _T_2115 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2116 = cvt(_T_2115) node _T_2117 = and(_T_2116, asSInt(UInt<29>(0h10000000))) node _T_2118 = asSInt(_T_2117) node _T_2119 = eq(_T_2118, asSInt(UInt<1>(0h0))) node _T_2120 = or(_T_2114, _T_2119) node _T_2121 = and(_T_2109, _T_2120) node _T_2122 = or(UInt<1>(0h0), _T_2107) node _T_2123 = or(_T_2122, _T_2121) node _T_2124 = and(_T_2058, _T_2123) node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(_T_2124, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2124, UInt<1>(0h1), "") : assert_150 node _T_2128 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2130 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2128 connect _WIRE_8[1], _T_2129 connect _WIRE_8[2], _T_2130 node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2132 = mux(_WIRE_8[0], _T_2131, UInt<1>(0h0)) node _T_2133 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2134 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2135 = or(_T_2132, _T_2133) node _T_2136 = or(_T_2135, _T_2134) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2136 node _T_2137 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2138 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2139 = and(_T_2137, _T_2138) node _T_2140 = or(UInt<1>(0h0), _T_2139) node _T_2141 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2142 = cvt(_T_2141) node _T_2143 = and(_T_2142, asSInt(UInt<14>(0h2000))) node _T_2144 = asSInt(_T_2143) node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0))) node _T_2146 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2147 = cvt(_T_2146) node _T_2148 = and(_T_2147, asSInt(UInt<13>(0h1000))) node _T_2149 = asSInt(_T_2148) node _T_2150 = eq(_T_2149, asSInt(UInt<1>(0h0))) node _T_2151 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2152 = cvt(_T_2151) node _T_2153 = and(_T_2152, asSInt(UInt<17>(0h10000))) node _T_2154 = asSInt(_T_2153) node _T_2155 = eq(_T_2154, asSInt(UInt<1>(0h0))) node _T_2156 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2157 = cvt(_T_2156) node _T_2158 = and(_T_2157, asSInt(UInt<18>(0h2f000))) node _T_2159 = asSInt(_T_2158) node _T_2160 = eq(_T_2159, asSInt(UInt<1>(0h0))) node _T_2161 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2162 = cvt(_T_2161) node _T_2163 = and(_T_2162, asSInt(UInt<17>(0h10000))) node _T_2164 = asSInt(_T_2163) node _T_2165 = eq(_T_2164, asSInt(UInt<1>(0h0))) node _T_2166 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2167 = cvt(_T_2166) node _T_2168 = and(_T_2167, asSInt(UInt<13>(0h1000))) node _T_2169 = asSInt(_T_2168) node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0))) node _T_2171 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2172 = cvt(_T_2171) node _T_2173 = and(_T_2172, asSInt(UInt<17>(0h10000))) node _T_2174 = asSInt(_T_2173) node _T_2175 = eq(_T_2174, asSInt(UInt<1>(0h0))) node _T_2176 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2177 = cvt(_T_2176) node _T_2178 = and(_T_2177, asSInt(UInt<27>(0h4000000))) node _T_2179 = asSInt(_T_2178) node _T_2180 = eq(_T_2179, asSInt(UInt<1>(0h0))) node _T_2181 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2182 = cvt(_T_2181) node _T_2183 = and(_T_2182, asSInt(UInt<13>(0h1000))) node _T_2184 = asSInt(_T_2183) node _T_2185 = eq(_T_2184, asSInt(UInt<1>(0h0))) node _T_2186 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2187 = cvt(_T_2186) node _T_2188 = and(_T_2187, asSInt(UInt<29>(0h10000000))) node _T_2189 = asSInt(_T_2188) node _T_2190 = eq(_T_2189, asSInt(UInt<1>(0h0))) node _T_2191 = or(_T_2145, _T_2150) node _T_2192 = or(_T_2191, _T_2155) node _T_2193 = or(_T_2192, _T_2160) node _T_2194 = or(_T_2193, _T_2165) node _T_2195 = or(_T_2194, _T_2170) node _T_2196 = or(_T_2195, _T_2175) node _T_2197 = or(_T_2196, _T_2180) node _T_2198 = or(_T_2197, _T_2185) node _T_2199 = or(_T_2198, _T_2190) node _T_2200 = and(_T_2140, _T_2199) node _T_2201 = or(UInt<1>(0h0), _T_2200) node _T_2202 = and(_WIRE_9, _T_2201) node _T_2203 = asUInt(reset) node _T_2204 = eq(_T_2203, UInt<1>(0h0)) when _T_2204 : node _T_2205 = eq(_T_2202, UInt<1>(0h0)) when _T_2205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2202, UInt<1>(0h1), "") : assert_151 node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : node _T_2208 = eq(source_ok_2, UInt<1>(0h0)) when _T_2208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2209 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_153 node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2216 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2217 = asUInt(reset) node _T_2218 = eq(_T_2217, UInt<1>(0h0)) when _T_2218 : node _T_2219 = eq(_T_2216, UInt<1>(0h0)) when _T_2219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2216, UInt<1>(0h1), "") : assert_155 node _T_2220 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2220 : node _T_2221 = asUInt(reset) node _T_2222 = eq(_T_2221, UInt<1>(0h0)) when _T_2222 : node _T_2223 = eq(address_ok_1, UInt<1>(0h0)) when _T_2223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(source_ok_2, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2230 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_159 node _T_2234 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2235 = asUInt(reset) node _T_2236 = eq(_T_2235, UInt<1>(0h0)) when _T_2236 : node _T_2237 = eq(_T_2234, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2234, UInt<1>(0h1), "") : assert_160 node _T_2238 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2238 : node _T_2239 = asUInt(reset) node _T_2240 = eq(_T_2239, UInt<1>(0h0)) when _T_2240 : node _T_2241 = eq(address_ok_1, UInt<1>(0h0)) when _T_2241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(source_ok_2, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2248 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_164 node _T_2252 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2252 : node _T_2253 = asUInt(reset) node _T_2254 = eq(_T_2253, UInt<1>(0h0)) when _T_2254 : node _T_2255 = eq(address_ok_1, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2256 = asUInt(reset) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) when _T_2257 : node _T_2258 = eq(source_ok_2, UInt<1>(0h0)) when _T_2258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2262 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_168 node _T_2266 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(_T_2266, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2266, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2273 = eq(a_first, UInt<1>(0h0)) node _T_2274 = and(io.in.a.valid, _T_2273) when _T_2274 : node _T_2275 = eq(io.in.a.bits.opcode, opcode) node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : node _T_2278 = eq(_T_2275, UInt<1>(0h0)) when _T_2278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2275, UInt<1>(0h1), "") : assert_171 node _T_2279 = eq(io.in.a.bits.param, param) node _T_2280 = asUInt(reset) node _T_2281 = eq(_T_2280, UInt<1>(0h0)) when _T_2281 : node _T_2282 = eq(_T_2279, UInt<1>(0h0)) when _T_2282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2279, UInt<1>(0h1), "") : assert_172 node _T_2283 = eq(io.in.a.bits.size, size) node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(_T_2283, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2283, UInt<1>(0h1), "") : assert_173 node _T_2287 = eq(io.in.a.bits.source, source) node _T_2288 = asUInt(reset) node _T_2289 = eq(_T_2288, UInt<1>(0h0)) when _T_2289 : node _T_2290 = eq(_T_2287, UInt<1>(0h0)) when _T_2290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2287, UInt<1>(0h1), "") : assert_174 node _T_2291 = eq(io.in.a.bits.address, address) node _T_2292 = asUInt(reset) node _T_2293 = eq(_T_2292, UInt<1>(0h0)) when _T_2293 : node _T_2294 = eq(_T_2291, UInt<1>(0h0)) when _T_2294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2291, UInt<1>(0h1), "") : assert_175 node _T_2295 = and(io.in.a.ready, io.in.a.valid) node _T_2296 = and(_T_2295, a_first) when _T_2296 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2297 = eq(d_first, UInt<1>(0h0)) node _T_2298 = and(io.in.d.valid, _T_2297) when _T_2298 : node _T_2299 = eq(io.in.d.bits.opcode, opcode_1) node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : node _T_2302 = eq(_T_2299, UInt<1>(0h0)) when _T_2302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2299, UInt<1>(0h1), "") : assert_176 node _T_2303 = eq(io.in.d.bits.param, param_1) node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(_T_2303, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2303, UInt<1>(0h1), "") : assert_177 node _T_2307 = eq(io.in.d.bits.size, size_1) node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : node _T_2310 = eq(_T_2307, UInt<1>(0h0)) when _T_2310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2307, UInt<1>(0h1), "") : assert_178 node _T_2311 = eq(io.in.d.bits.source, source_1) node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : node _T_2314 = eq(_T_2311, UInt<1>(0h0)) when _T_2314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2311, UInt<1>(0h1), "") : assert_179 node _T_2315 = eq(io.in.d.bits.sink, sink) node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : node _T_2318 = eq(_T_2315, UInt<1>(0h0)) when _T_2318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2315, UInt<1>(0h1), "") : assert_180 node _T_2319 = eq(io.in.d.bits.denied, denied) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_181 node _T_2323 = and(io.in.d.ready, io.in.d.valid) node _T_2324 = and(_T_2323, d_first) when _T_2324 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2325 = eq(b_first, UInt<1>(0h0)) node _T_2326 = and(io.in.b.valid, _T_2325) when _T_2326 : node _T_2327 = eq(io.in.b.bits.opcode, opcode_2) node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : node _T_2330 = eq(_T_2327, UInt<1>(0h0)) when _T_2330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2327, UInt<1>(0h1), "") : assert_182 node _T_2331 = eq(io.in.b.bits.param, param_2) node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(_T_2331, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2331, UInt<1>(0h1), "") : assert_183 node _T_2335 = eq(io.in.b.bits.size, size_2) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_184 node _T_2339 = eq(io.in.b.bits.source, source_2) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_185 node _T_2343 = eq(io.in.b.bits.address, address_1) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_186 node _T_2347 = and(io.in.b.ready, io.in.b.valid) node _T_2348 = and(_T_2347, b_first) when _T_2348 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2349 = eq(c_first, UInt<1>(0h0)) node _T_2350 = and(io.in.c.valid, _T_2349) when _T_2350 : node _T_2351 = eq(io.in.c.bits.opcode, opcode_3) node _T_2352 = asUInt(reset) node _T_2353 = eq(_T_2352, UInt<1>(0h0)) when _T_2353 : node _T_2354 = eq(_T_2351, UInt<1>(0h0)) when _T_2354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2351, UInt<1>(0h1), "") : assert_187 node _T_2355 = eq(io.in.c.bits.param, param_3) node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(_T_2355, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2355, UInt<1>(0h1), "") : assert_188 node _T_2359 = eq(io.in.c.bits.size, size_3) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(_T_2359, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2359, UInt<1>(0h1), "") : assert_189 node _T_2363 = eq(io.in.c.bits.source, source_3) node _T_2364 = asUInt(reset) node _T_2365 = eq(_T_2364, UInt<1>(0h0)) when _T_2365 : node _T_2366 = eq(_T_2363, UInt<1>(0h0)) when _T_2366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2363, UInt<1>(0h1), "") : assert_190 node _T_2367 = eq(io.in.c.bits.address, address_2) node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(_T_2367, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2367, UInt<1>(0h1), "") : assert_191 node _T_2371 = and(io.in.c.ready, io.in.c.valid) node _T_2372 = and(_T_2371, c_first) when _T_2372 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes : UInt<24>, clock, reset, UInt<24>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<3> connect a_set, UInt<3>(0h0) wire a_set_wo_ready : UInt<3> connect a_set_wo_ready, UInt<3>(0h0) wire a_opcodes_set : UInt<12> connect a_opcodes_set, UInt<12>(0h0) wire a_sizes_set : UInt<24> connect a_sizes_set, UInt<24>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2373 = and(io.in.a.valid, a_first_1) node _T_2374 = and(_T_2373, UInt<1>(0h1)) when _T_2374 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2375 = and(io.in.a.ready, io.in.a.valid) node _T_2376 = and(_T_2375, a_first_1) node _T_2377 = and(_T_2376, UInt<1>(0h1)) when _T_2377 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2378 = dshr(inflight, io.in.a.bits.source) node _T_2379 = bits(_T_2378, 0, 0) node _T_2380 = eq(_T_2379, UInt<1>(0h0)) node _T_2381 = asUInt(reset) node _T_2382 = eq(_T_2381, UInt<1>(0h0)) when _T_2382 : node _T_2383 = eq(_T_2380, UInt<1>(0h0)) when _T_2383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2380, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<3> connect d_clr, UInt<3>(0h0) wire d_clr_wo_ready : UInt<3> connect d_clr_wo_ready, UInt<3>(0h0) wire d_opcodes_clr : UInt<12> connect d_opcodes_clr, UInt<12>(0h0) wire d_sizes_clr : UInt<24> connect d_sizes_clr, UInt<24>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2384 = and(io.in.d.valid, d_first_1) node _T_2385 = and(_T_2384, UInt<1>(0h1)) node _T_2386 = eq(d_release_ack, UInt<1>(0h0)) node _T_2387 = and(_T_2385, _T_2386) when _T_2387 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2388 = and(io.in.d.ready, io.in.d.valid) node _T_2389 = and(_T_2388, d_first_1) node _T_2390 = and(_T_2389, UInt<1>(0h1)) node _T_2391 = eq(d_release_ack, UInt<1>(0h0)) node _T_2392 = and(_T_2390, _T_2391) when _T_2392 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2393 = and(io.in.d.valid, d_first_1) node _T_2394 = and(_T_2393, UInt<1>(0h1)) node _T_2395 = eq(d_release_ack, UInt<1>(0h0)) node _T_2396 = and(_T_2394, _T_2395) when _T_2396 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2397 = dshr(inflight, io.in.d.bits.source) node _T_2398 = bits(_T_2397, 0, 0) node _T_2399 = or(_T_2398, same_cycle_resp) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2403 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2404 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2405 = or(_T_2403, _T_2404) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_194 node _T_2409 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_195 else : node _T_2413 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2414 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2415 = or(_T_2413, _T_2414) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_196 node _T_2419 = eq(io.in.d.bits.size, a_size_lookup) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_197 node _T_2423 = and(io.in.d.valid, d_first_1) node _T_2424 = and(_T_2423, a_first_1) node _T_2425 = and(_T_2424, io.in.a.valid) node _T_2426 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2427 = and(_T_2425, _T_2426) node _T_2428 = eq(d_release_ack, UInt<1>(0h0)) node _T_2429 = and(_T_2427, _T_2428) when _T_2429 : node _T_2430 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2431 = or(_T_2430, io.in.a.ready) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_198 node _T_2435 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2436 = orr(a_set_wo_ready) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) node _T_2438 = or(_T_2435, _T_2437) node _T_2439 = asUInt(reset) node _T_2440 = eq(_T_2439, UInt<1>(0h0)) when _T_2440 : node _T_2441 = eq(_T_2438, UInt<1>(0h0)) when _T_2441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2438, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_83 node _T_2442 = orr(inflight) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) node _T_2444 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2445 = or(_T_2443, _T_2444) node _T_2446 = lt(watchdog, plusarg_reader.out) node _T_2447 = or(_T_2445, _T_2446) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2451 = and(io.in.a.ready, io.in.a.valid) node _T_2452 = and(io.in.d.ready, io.in.d.valid) node _T_2453 = or(_T_2451, _T_2452) when _T_2453 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes_1 : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes_1 : UInt<24>, clock, reset, UInt<24>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<3> connect c_set, UInt<3>(0h0) wire c_set_wo_ready : UInt<3> connect c_set_wo_ready, UInt<3>(0h0) wire c_opcodes_set : UInt<12> connect c_opcodes_set, UInt<12>(0h0) wire c_sizes_set : UInt<24> connect c_sizes_set, UInt<24>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2454 = and(io.in.c.valid, c_first_1) node _T_2455 = bits(io.in.c.bits.opcode, 2, 2) node _T_2456 = bits(io.in.c.bits.opcode, 1, 1) node _T_2457 = and(_T_2455, _T_2456) node _T_2458 = and(_T_2454, _T_2457) when _T_2458 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2459 = and(io.in.c.ready, io.in.c.valid) node _T_2460 = and(_T_2459, c_first_1) node _T_2461 = bits(io.in.c.bits.opcode, 2, 2) node _T_2462 = bits(io.in.c.bits.opcode, 1, 1) node _T_2463 = and(_T_2461, _T_2462) node _T_2464 = and(_T_2460, _T_2463) when _T_2464 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2465 = dshr(inflight_1, io.in.c.bits.source) node _T_2466 = bits(_T_2465, 0, 0) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<3> connect d_clr_1, UInt<3>(0h0) wire d_clr_wo_ready_1 : UInt<3> connect d_clr_wo_ready_1, UInt<3>(0h0) wire d_opcodes_clr_1 : UInt<12> connect d_opcodes_clr_1, UInt<12>(0h0) wire d_sizes_clr_1 : UInt<24> connect d_sizes_clr_1, UInt<24>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2471 = and(io.in.d.valid, d_first_2) node _T_2472 = and(_T_2471, UInt<1>(0h1)) node _T_2473 = and(_T_2472, d_release_ack_1) when _T_2473 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2474 = and(io.in.d.ready, io.in.d.valid) node _T_2475 = and(_T_2474, d_first_2) node _T_2476 = and(_T_2475, UInt<1>(0h1)) node _T_2477 = and(_T_2476, d_release_ack_1) when _T_2477 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2478 = and(io.in.d.valid, d_first_2) node _T_2479 = and(_T_2478, UInt<1>(0h1)) node _T_2480 = and(_T_2479, d_release_ack_1) when _T_2480 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2481 = dshr(inflight_1, io.in.d.bits.source) node _T_2482 = bits(_T_2481, 0, 0) node _T_2483 = or(_T_2482, same_cycle_resp_1) node _T_2484 = asUInt(reset) node _T_2485 = eq(_T_2484, UInt<1>(0h0)) when _T_2485 : node _T_2486 = eq(_T_2483, UInt<1>(0h0)) when _T_2486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2483, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2487 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2488 = asUInt(reset) node _T_2489 = eq(_T_2488, UInt<1>(0h0)) when _T_2489 : node _T_2490 = eq(_T_2487, UInt<1>(0h0)) when _T_2490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2487, UInt<1>(0h1), "") : assert_203 else : node _T_2491 = eq(io.in.d.bits.size, c_size_lookup) node _T_2492 = asUInt(reset) node _T_2493 = eq(_T_2492, UInt<1>(0h0)) when _T_2493 : node _T_2494 = eq(_T_2491, UInt<1>(0h0)) when _T_2494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2491, UInt<1>(0h1), "") : assert_204 node _T_2495 = and(io.in.d.valid, d_first_2) node _T_2496 = and(_T_2495, c_first_1) node _T_2497 = and(_T_2496, io.in.c.valid) node _T_2498 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2499 = and(_T_2497, _T_2498) node _T_2500 = and(_T_2499, d_release_ack_1) node _T_2501 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2502 = and(_T_2500, _T_2501) when _T_2502 : node _T_2503 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2504 = or(_T_2503, io.in.c.ready) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_205 node _T_2508 = orr(c_set_wo_ready) when _T_2508 : node _T_2509 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_84 node _T_2513 = orr(inflight_1) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) node _T_2515 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2516 = or(_T_2514, _T_2515) node _T_2517 = lt(watchdog_1, plusarg_reader_1.out) node _T_2518 = or(_T_2516, _T_2517) node _T_2519 = asUInt(reset) node _T_2520 = eq(_T_2519, UInt<1>(0h0)) when _T_2520 : node _T_2521 = eq(_T_2518, UInt<1>(0h0)) when _T_2521 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2518, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2522 = and(io.in.c.ready, io.in.c.valid) node _T_2523 = and(io.in.d.ready, io.in.d.valid) node _T_2524 = or(_T_2522, _T_2523) when _T_2524 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2525 = and(io.in.d.ready, io.in.d.valid) node _T_2526 = and(_T_2525, d_first_3) node _T_2527 = bits(io.in.d.bits.opcode, 2, 2) node _T_2528 = bits(io.in.d.bits.opcode, 1, 1) node _T_2529 = eq(_T_2528, UInt<1>(0h0)) node _T_2530 = and(_T_2527, _T_2529) node _T_2531 = and(_T_2526, _T_2530) when _T_2531 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2532 = dshr(inflight_2, io.in.d.bits.sink) node _T_2533 = bits(_T_2532, 0, 0) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) node _T_2535 = asUInt(reset) node _T_2536 = eq(_T_2535, UInt<1>(0h0)) when _T_2536 : node _T_2537 = eq(_T_2534, UInt<1>(0h0)) when _T_2537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2534, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2538 = and(io.in.e.ready, io.in.e.valid) node _T_2539 = and(_T_2538, UInt<1>(0h1)) node _T_2540 = and(_T_2539, UInt<1>(0h1)) when _T_2540 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2541 = or(d_set, inflight_2) node _T_2542 = dshr(_T_2541, io.in.e.bits.sink) node _T_2543 = bits(_T_2542, 0, 0) node _T_2544 = asUInt(reset) node _T_2545 = eq(_T_2544, UInt<1>(0h0)) when _T_2545 : node _T_2546 = eq(_T_2543, UInt<1>(0h0)) when _T_2546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2543, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_41( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _legal_source_T = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31] wire _legal_source_T_4 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_6 = _legal_source_T_4; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_5 = {_legal_source_WIRE_2, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = {1'h0, _legal_source_T_6} | _legal_source_T_5; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_23 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_24 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2540 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2540 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s5k5z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_14 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s5k5z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s5k5z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_4.bits.sink, UInt<5>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_10.bits.sink, UInt<5>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_39 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_40 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLBuffer_a32d64s5k5z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [4:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [4:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_14 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s5k5z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k5z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_45 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut

module MulFullRawFN_45( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule